Coremarkpro#18
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X3 gains a 2 MiB UltraRAM memory tier at 0x01000000 (6-cycle read, 2-cycle write) backing the CoreMark-Pro heap; genesys2 and the yosys flow keep URAM uninstantiated. Six CoreMark-Pro workloads (core, cjpeg, linear_alg, nnet, parser, sha) run on X3 hardware through load_software.py, passing -v1 validation and -v0 performance (>=10s each); software_registry.py carries the per-workload calibration, and the link map gives the heap 1936 KiB against a measured 112 KiB stack reserve. Five RTL bugs found and fixed along the way, each with a red->green cocotb test: 1. branch_prediction_controller: the registered prediction handoff survived a same-cycle PD/slot-2 redirect across stalls, desyncing pc_reg from the fetched bytes. 2. data_mem_request_router: a queued URAM load read could issue while a multi-cycle URAM store was still in flight. 3. store_queue: partial-flush hole reuse broke ring order, stranding committed stores behind younger uncommitted entries (the linear_alg deadlock). Rebuilt as pure tail allocation with a retimed flush tail pullback (also removes an 18-LUT-level post-opt timing path). 4. store_queue: the flush kill predicate missed same-cycle combinational commits, losing a committed store to a flush-after-head. 5. if_stage: pd_redirect_q's wrong-path bubble pulse was not stall-aware; a stall straddling the bubble let the release cycle and the realigned cycle both dispatch the same bundle (duplicate ROB allocation).
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