flash: nor: dw-spi: add RiscV support - #28
Merged
Conversation
aap-sc
self-requested a review
August 20, 2026 14:31
aap-sc
reviewed
Aug 24, 2026
Collaborator
|
@matsievskiysv checkpatch run against your patchset complains around patches 04, 05, 07, and 08. You could run it like this: Could you clean that up, please? |
added 12 commits
August 24, 2026 10:07
Linux driver distinguishes PSSI and HSSI IP variants, which seemingly differ in configuration register fields layout. Add an option to support the HSSI layout. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Describe -hssi controller option. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Move optional -spi_mst and -if_owner_offset options from mandatory to optional argument list. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Refactor driver code for easier support of multiple target loaders. Shuffle structure fields for better packing. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Move loader buffers out of functions to allow higher level functions calculating required working area size. This is needed to support small work-area sizes. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Add missing hexadecimal prefix to error message. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Some SoCs may use onboard SRAM memory for work-area prior to DDR being trained. Add support for using small work-areas with the driver. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Add RISCV64 loader for the driver. Tested on FPGA with W25Q128JW Flash chip. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Allow base addresses to be located at the address 0, which is the case for some SoCs. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Use flash size to determine addressing mode. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Add fallback action to read unknown Flash device info from SFDP header. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Add support for Syntacore SCR5 target. Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
matsievskiysv
force-pushed
the
dw-spi-update
branch
from
August 24, 2026 07:10
b95293e to
739fe8b
Compare
Author
Updated code. Checkpatch reports no errors now. |
aap-sc
approved these changes
Aug 26, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Add RiscV architecture support for dw-spi NOR Flash driver. Functionality was tested on FPGA prototype; MIPS functionality was checked for regression.
Other improvements: