update new spi flash for rockchip && fix the devtype and devnum environment variables might be cleared

arch/arm/mach-rockchip/boot_rkimg.c

@@ -90,8 +90,10 @@ static void boot_devtype_init(void)
 	char *src = "scan";
 	static int done;	/* static */
 	int ret;
+	bool need_reinit;
 
-	if (done)
+	need_reinit = !done || !env_get("devtype") || !env_get("devnum");
+	if (!need_reinit)
 		return;
 
 #ifdef CONFIG_MP_BOOT

drivers/mtd/nand/spi/Kconfig

@@ -39,16 +39,6 @@ config SPI_NAND_WINBOND
 	help
 	  Add support for various WINBOND SPI Nand flash chips
 
-if SPI_NAND_WINBOND
-
-config SPI_NAND_WINBOND_CONT_READ
-	bool "WINBOND SPI flash continuous read support"
-	default n
-	help
-	 Add support for WINBOND SPI Nand flash chips cont read.
-
-endif
-
 config SPI_NAND_DOSILICON
 	bool "DOSILICON SPI flash support"
 	default y
@@ -140,4 +130,35 @@ config SPI_NAND_ZBIT
 	bool "ZBIT SPI flash support"
 	help
 	  Add support for various ZBIT SPI Nand flash chips
+
+config SPI_NAND_HIKSEMI
+	default y
+	bool "HIKSEMI SPI flash support"
+	help
+	  Add support for various HIKSEMI SPI Nand flash chips
+
+config SPI_NAND_KINGSTON
+	default y
+	bool "KINGSTON SPI flash support"
+	help
+	  Add support for various KINGSTON SPI Nand flash chips
+
+config SPI_NAND_ISSI
+	default y
+	bool "ISSI SPI flash support"
+	help
+	  Add support for various ISSI SPI Nand flash chips
+
+config SPI_NAND_TITAN
+	default y
+	bool "TITAN SPI flash support"
+	help
+	  Add support for various TITAN SPI Nand flash chips
+
+config SPI_NAND_CONT_READ
+	bool "Enable SPI flash continuous read support"
+	default n
+	help
+	 Add support for SPI Nand flash chips cont read.
+
 endif

drivers/mtd/nand/spi/Makefile

@@ -17,8 +17,12 @@ obj-$(CONFIG_SPI_NAND_BIWIN) += biwin.o
 obj-$(CONFIG_SPI_NAND_ETRON) += etron.o
 obj-$(CONFIG_SPI_NAND_JSC) += jsc.o
 obj-$(CONFIG_SPI_NAND_SILICONGO) += silicongo.o
+obj-$(CONFIG_SPI_NAND_TITAN) += titan.o
 obj-$(CONFIG_SPI_NAND_UNIM) += unim.o
 obj-$(CONFIG_SPI_NAND_SKYHIGH) += skyhigh.o
 obj-$(CONFIG_SPI_NAND_GSTO) += gsto.o
 obj-$(CONFIG_SPI_NAND_ZBIT) += zbit.o
+obj-$(CONFIG_SPI_NAND_HIKSEMI) += hiksemi.o
+obj-$(CONFIG_SPI_NAND_KINGSTON) += kingston.o
+obj-$(CONFIG_SPI_NAND_ISSI) += issi.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o

drivers/mtd/nand/spi/core.c

@@ -289,8 +289,6 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
 		if (ret)
 			return ret;
 
-		if (spinand->support_cont_read)
-			op.addr.nbytes = 3;
 		ret = spi_mem_exec_op(spinand->slave, &op);
 		if (ret)
 			return ret;
@@ -524,33 +522,66 @@ static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
 	return -EINVAL;
 }
 
+static int spinand_read_page_wait(struct spinand_device *spinand, u8 *s)
+{
+	unsigned long start, stop;
+	u8 status;
+	int ret;
+
+	start = get_timer(0);
+	stop = 400;
+	do {
+		ret = spinand_read_status(spinand, &status);
+		if (ret)
+			return ret;
+
+		if (status & STATUS_BUSY)
+			continue;
+
+		ret = spinand_read_status(spinand, &status);
+		if (ret)
+			return ret;
+
+		if (!(status & STATUS_BUSY))
+			break;
+
+	} while (get_timer(start) < stop);
+
+	*s = status;
+
+	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
+}
+
 static int spinand_read_page(struct spinand_device *spinand,
 			     const struct nand_page_io_req *req,
 			     bool ecc_enabled)
 {
-	u8 status = 0;
+	u8 status;
 	int ret;
 
 	ret = spinand_load_page_op(spinand, req);
 	if (ret)
 		return ret;
 
-	ret = spinand_wait(spinand, &status);
-	/*
-	 * When there is data outside of OIP in the status, the status data is
-	 * inaccurate and needs to be reconfirmed
-	 */
-	if (spinand->id.data[0] == 0x01 && status && !ret)
+	/* Workaround for Skyhigh */
+	if (spinand->id.data[0] == 0x01) {
+		ret = spinand_read_page_wait(spinand, &status);
+		if (ret)
+			return ret;
+	} else {
 		ret = spinand_wait(spinand, &status);
-	if (ret < 0)
-		return ret;
+		if (ret)
+			return ret;
+	}
 
 	ret = spinand_read_from_cache_op(spinand, req);
 	if (ret)
 		return ret;
 
-	if (spinand->support_cont_read && !(spinand->slave->mode & SPI_DMA_PREPARE))
+#ifdef CONFIG_SPI_NAND_CONT_READ
+	if (!(spinand->slave->mode & SPI_DMA_PREPARE))
 		spinand_wait(spinand, &status);
+#endif
 
 	if (!ecc_enabled)
 		return 0;
@@ -594,6 +625,11 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
 	bool ecc_failed = false;
 	int ret = 0;
 
+	if (spinand->support_cont_read && (from & mtd->writesize_mask)) {
+		printf("spinand cont read at unaligned offset %llx %x\n", from, mtd->writesize_mask);
+		return -EINVAL;
+	}
+
 	if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
 		enable_ecc = true;
 
@@ -877,9 +913,11 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
 #endif
 #ifdef CONFIG_SPI_NAND_ESMT
 	&esmt_spinand_manufacturer,
+	&esmt_elite_spinand_manufacturer,
 #endif
 #ifdef CONFIG_SPI_NAND_XINCUN
 	&xincun_spinand_manufacturer,
+	&xincun_6c_spinand_manufacturer,
 #endif
 #ifdef CONFIG_SPI_NAND_XTX
 	&xtx_spinand_manufacturer,
@@ -905,6 +943,9 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
 #ifdef CONFIG_SPI_NAND_SILICONGO
 	&silicongo_spinand_manufacturer,
 #endif
+#ifdef CONFIG_SPI_NAND_TITAN
+	&titan_spinand_manufacturer,
+#endif
 #ifdef CONFIG_SPI_NAND_UNIM
 	&unim_spinand_manufacturer,
 	&unim_zl_spinand_manufacturer,
@@ -918,6 +959,15 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
 #ifdef CONFIG_SPI_NAND_ZBIT
 	&zbit_spinand_manufacturer,
 #endif
+#ifdef CONFIG_SPI_NAND_HIKSEMI
+	&hiksemi_spinand_manufacturer,
+#endif
+#ifdef CONFIG_SPI_NAND_KINGSTON
+	&kingston_spinand_manufacturer,
+#endif
+#ifdef CONFIG_SPI_NAND_ISSI
+	&issi_spinand_manufacturer,
+#endif
 };
 
 static int spinand_manufacturer_match(struct spinand_device *spinand,

drivers/mtd/nand/spi/dosilicon.c

@@ -121,6 +121,36 @@ static int ds35xxgb_ecc_get_status(struct spinand_device *spinand,
 	return -EINVAL;
 }
 
+static int ds35xxge_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 128;
+	region->length = 128;
+
+	return 0;
+}
+
+static int ds35xxge_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 1 bytes for the BBM. */
+	region->offset = 1;
+	region->length = 127;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops ds35xxge_ooblayout = {
+	.ecc = ds35xxge_ooblayout_ecc,
+	.rfree = ds35xxge_ooblayout_free,
+};
+
 static const struct spinand_info dosilicon_spinand_table[] = {
 	SPINAND_INFO("DS35X1GA",
 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
@@ -263,6 +293,52 @@ static const struct spinand_info dosilicon_spinand_table[] = {
 					      &update_cache_variants),
 		     SPINAND_HAS_QE_BIT,
 		     SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+	SPINAND_INFO("DS35Q2GBS",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+	SPINAND_INFO("DS35Q4GE-IB",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&ds35xxge_ooblayout, ds35xxgb_ecc_get_status)),
+	SPINAND_INFO("DS35Q8GM-IG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB8),
+		     NAND_MEMORG(1, 2048, 128, 64, 8192, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+	SPINAND_INFO("DS35Q2GD-IB",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+	SPINAND_INFO("DS35M4GM-IB",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA4),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+				     ds35xxgb_ecc_get_status)),
 };
 
 static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {

drivers/mtd/nand/spi/esmt.c

@@ -13,6 +13,7 @@
 #include <linux/mtd/spinand.h>
 
 #define SPINAND_MFR_ESMT		0xC8
+#define SPINAND_MFR_ESMT_ELITE		0x8C
 
 static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
@@ -134,6 +135,18 @@ static const struct spinand_info esmt_spinand_table[] = {
 		     SPINAND_ECCINFO(&f50l2g41ka_ooblayout, f50l2g41ka_ecc_ecc_get_status)),
 };
 
+static const struct spinand_info esmt_elite_spinand_table[] = {
+	SPINAND_INFO("F50L1G41LC",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x2C),
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&f50lxx41x_ooblayout, NULL)),
+};
+
 static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {
 };
 
@@ -144,3 +157,11 @@ const struct spinand_manufacturer esmt_spinand_manufacturer = {
 	.nchips = ARRAY_SIZE(esmt_spinand_table),
 	.ops = &esmt_spinand_manuf_ops,
 };
+
+const struct spinand_manufacturer esmt_elite_spinand_manufacturer = {
+	.id = SPINAND_MFR_ESMT_ELITE,
+	.name = "esmt_elite",
+	.chips = esmt_elite_spinand_table,
+	.nchips = ARRAY_SIZE(esmt_elite_spinand_table),
+	.ops = &esmt_spinand_manuf_ops,
+};