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Add a phased classical action for SelectedMajoranaFermion #1778
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@@ -13,7 +13,7 @@ | |||||||||||||||||||||||||||||||
| # limitations under the License. | ||||||||||||||||||||||||||||||||
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| from functools import cached_property | ||||||||||||||||||||||||||||||||
| from typing import Iterator, Sequence, Tuple, Union | ||||||||||||||||||||||||||||||||
| from typing import Dict, Iterator, Sequence, Tuple, Union | ||||||||||||||||||||||||||||||||
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| import attrs | ||||||||||||||||||||||||||||||||
| import cirq | ||||||||||||||||||||||||||||||||
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@@ -25,6 +25,7 @@ | |||||||||||||||||||||||||||||||
| from qualtran._infra.data_types import BQUInt | ||||||||||||||||||||||||||||||||
| from qualtran._infra.gate_with_registers import total_bits | ||||||||||||||||||||||||||||||||
| from qualtran.bloqs.multiplexers.unary_iteration_bloq import UnaryIterationGate | ||||||||||||||||||||||||||||||||
| from qualtran.simulation.classical_sim import ClassicalValT | ||||||||||||||||||||||||||||||||
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| @attrs.frozen | ||||||||||||||||||||||||||||||||
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@@ -137,5 +138,43 @@ def nth_operation( # type: ignore[override] | |||||||||||||||||||||||||||||||
| yield self.target_gate(target[target_idx]).controlled_by(control) | ||||||||||||||||||||||||||||||||
| yield cirq.CZ(*accumulator, target[target_idx]) | ||||||||||||||||||||||||||||||||
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| def on_classical_vals(self, **vals) -> Dict[str, 'ClassicalValT']: | ||||||||||||||||||||||||||||||||
| if self.target_gate != cirq.X and self.target_gate != cirq.Z: | ||||||||||||||||||||||||||||||||
| return NotImplemented | ||||||||||||||||||||||||||||||||
| if len(self.control_registers) > 1 or len(self.selection_registers) > 1: | ||||||||||||||||||||||||||||||||
| return NotImplemented | ||||||||||||||||||||||||||||||||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. The current check
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| control_name = self.control_registers[0].name | ||||||||||||||||||||||||||||||||
| control = vals[control_name] | ||||||||||||||||||||||||||||||||
| selection_name = self.selection_registers[0].name | ||||||||||||||||||||||||||||||||
| selection = vals[selection_name] | ||||||||||||||||||||||||||||||||
| target = vals['target'] | ||||||||||||||||||||||||||||||||
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| # When target_gate == cirq.X, the action is (modulo phase) a single bitflip. | ||||||||||||||||||||||||||||||||
| if control and self.target_gate == cirq.X: | ||||||||||||||||||||||||||||||||
| max_selection = self.selection_registers[0].dtype.iteration_length_or_zero() - 1 | ||||||||||||||||||||||||||||||||
| target = (2 ** (max_selection - selection)) ^ target | ||||||||||||||||||||||||||||||||
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Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. can you add a comment describing how this logic works
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Done.
Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Can you be even more explicit with how the bit twiddling operations correspond to the promised action of the subroutine "flip the selection-th bit in target. the selection-th bit is addressed with the unsigned integer 2^(N - i) in our big endian convention" or something like that
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. If
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| # When target_gate == cirq.Z, the action is only in the phase. | ||||||||||||||||||||||||||||||||
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| return {control_name: control, selection_name: selection, 'target': target} | ||||||||||||||||||||||||||||||||
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| def basis_state_phase(self, **vals) -> Union[complex, None]: | ||||||||||||||||||||||||||||||||
| if self.target_gate != cirq.X and self.target_gate != cirq.Z: | ||||||||||||||||||||||||||||||||
| return None | ||||||||||||||||||||||||||||||||
| if len(self.control_registers) > 1 or len(self.selection_registers) > 1: | ||||||||||||||||||||||||||||||||
| return None | ||||||||||||||||||||||||||||||||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Similar to
Suggested change
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| control_name = self.control_registers[0].name | ||||||||||||||||||||||||||||||||
| control = vals[control_name] | ||||||||||||||||||||||||||||||||
| selection_name = self.selection_registers[0].name | ||||||||||||||||||||||||||||||||
| selection = vals[selection_name] | ||||||||||||||||||||||||||||||||
| target = vals['target'] | ||||||||||||||||||||||||||||||||
| if control: | ||||||||||||||||||||||||||||||||
| max_selection = self.selection_registers[0].dtype.iteration_length_or_zero() - 1 | ||||||||||||||||||||||||||||||||
| if self.target_gate == cirq.X: | ||||||||||||||||||||||||||||||||
| num_phases = (target >> (max_selection - selection + 1)).bit_count() | ||||||||||||||||||||||||||||||||
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Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. explain how this works |
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| else: | ||||||||||||||||||||||||||||||||
| num_phases = (target >> (max_selection - selection)).bit_count() | ||||||||||||||||||||||||||||||||
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Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. explain how this works and why it's different from the |
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| return 1 if (num_phases % 2) == 0 else -1 | ||||||||||||||||||||||||||||||||
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| return 1 | ||||||||||||||||||||||||||||||||
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| def __str__(self): | ||||||||||||||||||||||||||||||||
| return f'SelectedMajoranaFermion({self.target_gate})' | ||||||||||||||||||||||||||||||||
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is this restriction necessary?
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I'm not sure - it is hard for me to understand what this gate does in the general case. Is my understanding in #1699 (comment) correct?