Skip to content

wip: sidecar: sync RAX from intercept message in handle_io_port_exit #3360

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
emirceski wants to merge 4 commits into
base: main
Choose a base branch
from
Open

wip: sidecar: sync RAX from intercept message in handle_io_port_exit #3360

Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
7393a78
Fixes ICM 781515258
emirceski Apr 22, 2026
722fc0f
Merge branch 'microsoft:main' into sidecar-interrupt-reentry-fix
emirceski Apr 22, 2026
21df6df
sidecar: preserve CR2 slot and check is_valid when syncing guest regi…
emirceski Apr 22, 2026
e4e66ee
sidecar: sync rax from the intercept message
emirceski Apr 23, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 9 additions & 7 deletions openhcl/virt_mshv_vtl/src/processor/mshv/x64.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -707,25 +707,27 @@ impl<'a, 'b> InterceptHandler<'a, 'b> {

tracing::trace!(msg = %format_args!("{:x?}", message), "io_port");

assert_eq!(
message.rax,
self.vp.runner.cpu_context().gps_no_rsp[protocol::RAX]
);

// Sync RAX from the intercept message. For sidecar VPs, cpu_context
// may be stale if the register page was unavailable or invalid.
let rax = message.rax;
Comment thread
emirceski marked this conversation as resolved.
let interruption_pending = message.header.execution_state.interruption_pending();

if message.access_info.string_op() || message.access_info.rep_prefix() {
self.vp.runner.cpu_context_mut().gps_no_rsp[protocol::RAX] = rax;
Comment thread
emirceski marked this conversation as resolved.
Copy link

Copilot AI Apr 23, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

RAX is written into cpu_context in both branches, which makes it easy to accidentally diverge later. Since the assignment is unconditional, consider moving it before the if and/or taking a single mutable reference to the CPU context once and reusing it to avoid repeated cpu_context_mut() calls. This reduces duplication and makes the intent clearer.

Copilot uses AI. Check for mistakes.
let cache = self.vp.emulation_cache(self.intercepted_vtl);
self.vp
.emulate(dev, interruption_pending, self.intercepted_vtl, cache)
.await
} else {
let next_rip = next_rip(&message.header);
let access_size = message.access_info.access_size();
let is_write = message.header.intercept_access_type == HvInterceptAccessType::WRITE;
let port = message.port_number;
self.vp.runner.cpu_context_mut().gps_no_rsp[protocol::RAX] = rax;
Copy link

Copilot AI Apr 23, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

RAX is written into cpu_context in both branches, which makes it easy to accidentally diverge later. Since the assignment is unconditional, consider moving it before the if and/or taking a single mutable reference to the CPU context once and reusing it to avoid repeated cpu_context_mut() calls. This reduces duplication and makes the intent clearer.

Copilot uses AI. Check for mistakes.
virt_support_x86emu::emulate::emulate_io(
self.vp.vp_index(),
message.header.intercept_access_type == HvInterceptAccessType::WRITE,
message.port_number,
is_write,
port,
&mut self.vp.runner.cpu_context_mut().gps_no_rsp[protocol::RAX],
access_size,
dev,
Expand Down
Loading