Add Apple Silicon support with 128-byte cache line size - #106
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Thank you for your contribution, Alasdair. |
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Apple's M-series (M1-M4) and A-series (A14+) use 128-byte cache lines, I use
__APPLE__&&__aarch64__to detect Apple Silicon and correct cache line size for alignment. I also add macOS to the CMake CI matrix to keep this supported.