riscv: DIV, DIVU, REM and REMU are neither constant-time nor DOIT - #1544
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riscv: DIV, DIVU, REM and REMU are neither constant-time nor DOIT#1544clebreto wants to merge 1 commit into
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They have data-dependent latency on typical implementations and are
deliberately excluded from the Zkt ("Data-Independent Execution Latency
Subset") safe list of the RISC-V specification, which is the reference
for data operand independent timing on this architecture.
The DOIT classification of every RISC-V instruction is now written
explicitly in the instruction descriptors and documented against the
Zkt list. Loads and stores, which Zkt does not cover, keep the same
assumption as on the other architectures: the address is leaked, and
the latency is assumed not to depend on the transferred values.
Pseudo-instructions are classified according to their canonical
expansions. Zkt exempts HINT encodings (rd = x0) from the latency
requirement, but Jasmin cannot emit them: x0 is not part of the
declared register file.
Fixes jasmin-lang#1013
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Fixes #1013.
RISC-V has no run-time flag akin to Intel DOIT or ARM DIT; the reference for data operand independent timing is the ratified Zkt extension ("Data-Independent Execution Latency Subset", chapter Zkt of the Scalar Cryptography spec). Its safe list covers, for the RV32IM subset modelled by Jasmin, all the base ALU instructions and
mul/mulh/mulhu/mulhsu, and deliberately excludes division and remainder.Changes:
riscv_instr_decl.v: theDOIT/NOT_DOITconstructors are now passed explicitly to the descriptor helpers at every call site (as done for the other architectures in arch: carry the DOIT classification in the instruction descriptors #1520);DIV,DIVU,REMandREMUbecomeNOT_DOIT. A documentation block records the classification rationale against the Zkt list, including:MV→addi,NOT→xori,NEG→sub,LI→lui+addi,LA→auipc+addi), all Zkt-listed;MOV, ARM's DIT coversLDR/STR), so they stayDOIT;rd = x0) from the latency requirement, but Jasmin can never emit one sincex0is not part of the declared register file.riscv_arch_full.ml:is_ct_asm_opreturnsfalseforDIV/DIVU/REM/REMU(theFIXME RISCVis resolved), matching the x86/ARM convention of assuming everything but division to be constant-time.CCT-riscvandCCT-DOIT-riscvcategories with six tests: secret#DIV/#REMrejected by the plain CT checker, secret/and%rejected under--doit(both were wrongly accepted before this change), public division accepted, and secretmul/add/xor/shift/spill accepted under--doit.docs/source/tools/ct.md.Validation: full proofs build, extraction and compiler build are green;
CCT,CCT-riscv,CCT-DOIT,CCT-DOIT-riscv,SCT(43/43) and therisc-vcompilation category (106/106) all pass.