Minimal Copper bring-up crate for the Renesas Starter Kit+ for RZ/T2M
(RTK9RZTM0S00000BE, R9A07G075M24GBG Cortex-R52).
This first pass uses direct defmt over RTT and a NoopLogger Copper logger.
The Copper graph has two source tasks emitting boolean LED commands into two sink
tasks that own the board LED resources:
blink_led0->led0_sink: LED0,P19_6, 250 ms toggle periodblink_led1->led1_sink: LED1,P19_4, 700 ms toggle period
The main entry points are in justfile:
just --list
just load
just rttUse JLINK_SERIAL, JLINK_DEVICE, JLINK_IF, or JLINK_SPEED to override
the defaults. just hex builds the optimized firmware profile; an unoptimized
Cortex-R build is currently too large for the provisional RAM image layout.
The current linker layout is for a J-Link debugger-loaded RAM image: vectors in
CPU0 ATCM at 0x00000000, data/heap in SRAM at 0x10000000, and code in SRAM
at 0x10080000. Data starts at the beginning of SRAM because SEGGER's RZ/T2M
RTT support auto-scans the first 32 KiB of system RAM for the RTT control
block. xSPI boot/flash packaging is a later step.
The image is A32 ARM code. The load scripts force CPSR to 0x200001d3
before starting because the board reset state observed through J-Link leaves the
core in T32 state.
The crate overrides the weak cortex-r-rt _start with a small local startup
shim that loads _stack_top before calling _stack_setup; this avoids the
observed non-Hyp entry path passing the current mode value as the stack top.
The connected J-Link probe visible on this host is serial 000839006698.
probe-rs is installed but does not list RZ/T2M/R9A07G075 support here, so this
crate uses SEGGER J-Link tools directly.
The expected RAM-load path is:
just loadFor GDB:
just gdb-server
arm-none-eabi-gdb target/armv8r-none-eabihf/release/cu-rz-blinky \
-x scripts/load-ram-r52.gdbFor this board/probe combination, JLinkRTTLogger currently fails to discover
the valid RTT control block even though it is visible at _SEGGER_RTT = 0x1000001c. The checked-in fallback is:
just rtt