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Replace opaque ring bases in segdense tensor convs - #72
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mma_conv! and mma_half_split! read a 3-stage cp.async ring at `stage % STAGES`. LLVM's scalar evolution treats that remainder as affine in `stage`, so loop strength reduction split the fragment addresses into separate induction variables, and the opaque mov.b32 bases only hid that from it. A slot counter advanced apart from `stage` keeps one base plus immediates without the workaround. The tensor convolutions' hot loops lose 3 to 16 instructions on every shipped architecture and conv*_b32_tc runs 0.7 to 1.2% faster on an RTX 5090; embed_b32_f16 keeps the same hot loop and time. Outputs are bitwise identical to master. Only the sm80 PTX and cubins change.
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The title clearly and concisely describes the main change: replacing opaque shared-memory ring bases in segdense tensor convolution kernels. |
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 [Medium impact] The changes since the previous review appear safe to merge.
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cargo deny now fails on three zip advisories (RUSTSEC-2026-0367, -0368 and -0369), fixed in zip 9. ndarray-npy 0.10, its latest release, still requires zip 6, and its default .npz support is what pulls zip in. The library only reads .npy files, so it turns that support off. Only the tests, which read .npz baselines, keep it, and deny.toml ignores the three advisories for that path: NpzReader reads trusted fixtures by entry and never calls the affected extract APIs.
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Review comments at @deny.toml:
- Around line 6-8: Update the advisory entries for RUSTSEC-2026-0367,
RUSTSEC-2026-0368, and RUSTSEC-2026-0369 to include allow =
["ndarray-npy@0.10.0"], first confirming the repository’s cargo-deny version
supports the allow field. Preserve the existing reasons and restrict each
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The pinned cargo-deny 0.20.2 does not accept an allow list on advisory ignores, so ban zip unless ndarray-npy pulls it in. Another dependency that adds zip now fails instead of inheriting the ignores.
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@greptileai review |
mma_conv!andmma_half_split!now advance theircp.asyncring slot with a counter instead ofstage % STAGES, and their four opaquemov.b32shared bases are removed. The fragment addresses still compile to one base register plus immediates. The other 41opaquecall sites stay because removing them measured worse or not better (see below).Why
With the default
llcpath, LLVM's scalar evolution modelsstage % 3asstage - 3 * (stage / 3), which is affine instage. Next to the producer slot(stage + STAGES - 1) % STAGES, which has the same stride, loop strength reduction gives each fragment load its own induction variable, so ptxas seesreg + regaddresses. The opaque base hid the remainder from LSR. A slot advanced separately with(slot + 1) % STAGESisn't affine instage, so it does the same job in plain source.SASS (sm80 PTX, ptxas 13.0.88)
The sm75 PTX is byte-identical to master. In the sm80 PTX only these five entries change; every other segdense entry has identical SASS on every shipped architecture (sm_89 matches sm_86). The hot loop is the main pipeline loop.
The extra registers on
*_tcdo not change occupancy: at 128 threads andmin_blocks = 2, two blocks per SM fit before and after.embed_b32_f16keeps the same hot loop; its 1–2 extra instructions sit outside it.Numerics and time (RTX 5090)
I ran
segdense_dev_checkwith seeded operands, since no reference tensors were available, at the same shapes as the reference cases. Every case passed its f64-truth and cuBLAS/cuDNN bounds and the graph-replay bitwise check. Every case, changed or not, matched master bitwise. Timings are medians over 10 interleaved master/branch passes; each pass is itself the median of 60 graph replays. Unchanged entries in the same runs moved by up to ±2% (conv2_b1), which sets the noise floor.The non-ignored lib tests also pass on the 5090 with
--features "online cuda", including resnet's cuDNN parity test. The only failures are tests that need reference tensors or model files that aren't on this machine.cargo xtask cuda-kernels checkpasses.What stays and why
opaquemma_gemm!(2)linear1_b1_tf32, the 5090 default for batch-1 TF32, ran +3.9% slower (2.42 → 2.52 µs, 9 of 10 passes); k2 0.0%, e64 −1.0%. With 4 stages, removingopaquealone gives identical SASS, so it is a no-op thereconv!(2)stage % 2gemm!(2)stage % BUFFERSconv3x3(2)stage % BUFFERSc64/c64_small, the rest identical.resnet.sm80.sm_120.cubinis also hash-pinned by the RTX 5060 Ti production bindingconv3x3,fixed, shortcut, winograd (11)% 2, constant and per-thread basesc128/c256+170 to +175 instructions on sm_120; winograd trades folds against instructions per arch;sweep2worse everywheremov.u32fromtensor::ops)% 2V stages, transform baseswtp1+73 to +95 instructions and +8 to +14 registers; wtc/wbf worse. Ring slot forwtp1's raw producer alone: hot loop 365 → 364 instructions but folded 92/96 → 90/96 and +1 register, which no timing could separate from noiseh16,tc3,tensor, resnettensor(8)opaque(tid)So the
opaquehelpers stay.Build
cuda-oxide
918bbde(unchanged),nightly-2026-08-28,llc-21, ptxas 13.0.88, viacargo xtask cuda-kernels build segdense. A local build of master reproduced the committed segdense, resnet and wideconv PTX byte for byte before any change.cargo deny
cargo denystarted failing on three newzipadvisories (RUSTSEC-2026-0367, -0368 and -0369), which are fixed inzip9.ndarray-npy0.10, its latest release, still requireszip6, and only its default.npzsupport pullszipin. The library only reads.npyfiles, so it now turns that support off and the shipped dependency graph has nozip. The tests read.npzbaselines, so a dev-dependency keepscompressed_npz, anddeny.tomlignores the three advisories for that path.NpzReaderreads entries by name or index and never calls the affectedextractAPIs.Summary by CodeRabbit
.npyusage avoids unnecessary ZIP support, while compressed.npzsupport remains available for test baselines.