Arch-Lab

Introduction

Materials and reports of computer architecture laboratory which is instructed by Ms.Zokaei in spring 2016.

Sessions

Session 2

In this session we had created 4-bit-adder, decoder and multiplexer before we created ALU based on them.

Session 3

In this session we had started by seeing mealy and moore machine while we wanted to learn FSM (Finite State Machine) in VHDL. We created ripple counter, T-FlipFlop and sequence decoder for 1001 in this session.