UVM_TestBench_For_Single_Port_RAM

A complete UVM TB for verification of single port 64KB RAM

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Edaplayground Link		Edaplayground Link
LOG_FILE.log		LOG_FILE.log
RAM TB ARCHITECTURE.png		RAM TB ARCHITECTURE.png
README.md		README.md
Sequence Description		Sequence Description
coverage_data.txt		coverage_data.txt
design.sv		design.sv
interface.sv		interface.sv
ram_agent.sv		ram_agent.sv
ram_coverage.sv		ram_coverage.sv
ram_driver.sv		ram_driver.sv
ram_env.sv		ram_env.sv
ram_monitor.sv		ram_monitor.sv
ram_scoreboard.sv		ram_scoreboard.sv
ram_sequence.sv		ram_sequence.sv
ram_sequence_item.sv		ram_sequence_item.sv
ram_sequencer.sv		ram_sequencer.sv
ram_test.sv		ram_test.sv
run.do		run.do
tb_pkg.sv		tb_pkg.sv
testbench.sv		testbench.sv

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