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- #4556 · NewPaulWalker opened
on Apr 14, 2025 1 - #4242 · castleberrysam opened
on Feb 2, 2025 11
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Misaligned load/store whose second half crosses into the non-canonical Sv39/Sv48 hole is not page-faulted; the high half aliases to the upper-half mapping
module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6498 In OpenXiangShan/XiangShan;mip.LCOFIP counter-overflow request is dropped when it coincides with a CSR write to mip/sip (mhpmevent.OF=1 but LCOFIP never set)
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6497 In OpenXiangShan/XiangShan;Legal segmented store
vsseg2e16.vsilently commits wrong store data (0 instead of the source value) — vector store-data unit emits 0 for a field on kunminghu-v3version: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6486 In OpenXiangShan/XiangShan;Stale mtval after consecutive same-direction RVV memory access faults
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedversion: kunminghu-v2Issue or PR to the stable release kunminghu-v2Issue or PR to the stable release kunminghu-v2Status: Open.#6482 In OpenXiangShan/XiangShan;[Bug][Frontend] A return target misprediction no longer reaches BPU training after #6112
module: frontendBpu, Ftq, Ifu, ICache, IBufferBpu, Ftq, Ifu, ICache, IBuffertype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6481 In OpenXiangShan/XiangShan;Legal segmented store
vsseg3e32.vtriggersrobEntries uopNum is overflow!(ROB uop-count underflow) — deterministic assertion abort on kunminghu-v3module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6475 In OpenXiangShan/XiangShan;StoreQueue
deqPtr > rdataPtrassertion fails at the physical-queue wrap boundary under vector storesmodule: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6467 In OpenXiangShan/XiangShan;[Bug] large PlatformGrain values truncate PMP/PMA generator masks
module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6456 In OpenXiangShan/XiangShan;[Bug] AMOCAS.Q STA uops can collide at the single AtomicsUnit input
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanmodule: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6452 In OpenXiangShan/XiangShan;[Bug] TIMER allows MaxHartIdBits to overlap mtimecmp with mtime
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6451 In OpenXiangShan/XiangShan;TopDownCounters object refactoring thoughts
topic: code qualityTo make code more readable & maintainableTo make code more readable & maintainabletopic: verificationTo make function/performance verification easierTo make function/performance verification easierStatus: Open.#6427 In OpenXiangShan/XiangShan;[Bug] dcsr.stopcount=1 does not stop minstret/mcycle in Debug Mode; only the instret/cycle read values are frozen
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedtype: feature/planned(issue) Feature requests that are accepted/planned(issue) Feature requests that are accepted/plannedStatus: Open.#6419 In OpenXiangShan/XiangShan;