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Codex/matrix request kinds #159

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Merged
zykucas merged 3 commits into from
Sep 7, 2026
+13 −1
Merged

Codex/matrix request kinds #159

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e4b7598
refactor(MemReqSource): distinguish matrix reads and writes
Sep 4, 2026
ead6985
feat(MemReqSource): classify matrix prefetches
Sep 4, 2026
fb76390
Merge origin/master into codex/matrix-request-kinds
Sep 4, 2026
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2 changes: 1 addition & 1 deletion src/main/scala/utility/Select.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ object SelectByFn {
})

type SelectNode = (Bool, (T, SelectT))

def pipelineReg(in: SelectNode): SelectNode = {
val (valid, (bits, sel)) = in
(RegNext(valid, false.B), (RegNext(bits), RegNext(sel)))
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12 changes: 12 additions & 0 deletions src/main/scala/utility/TLUtils/BusKeyField.scala
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Expand Up @@ -45,8 +45,14 @@ object MemReqSource extends Enumeration {
val Prefetch2L3Stride = Value("Prefetch2L3Stride")
val Prefetch2L3Berti = Value("Prefetch2L3Berti")
val Prefetch2L3Unknown = Value("Prefetch2L3Unknown")
// Kept for compatibility with the earlier matrix request-source API.
val CPUMatrixData = Value("CPUMatrixData")
val Prefetch2L2Matrix = Value("Prefetch2L2Matrix")
// Matrix accesses are issued by CUTE rather than the CPU pipeline. Keep
// reads and writes distinct so cache accounting can classify them without
// treating CUTE traffic as ordinary CPU requests.
val MatrixRead = Value("MatrixRead")
val MatrixWrite = Value("MatrixWrite")
val ReqSourceCount = Value("ReqSourceCount")

val reqSourceBits = log2Ceil(ReqSourceCount.id)
Expand All @@ -62,6 +68,12 @@ object MemReqSource extends Enumeration {
reqSource === L1DataPrefetch.id.U
}

def isMatrixReq(reqSource: UInt): Bool = {
reqSource === CPUMatrixData.id.U ||
reqSource === MatrixRead.id.U ||
reqSource === MatrixWrite.id.U
}

def isL2Prefetch(reqSource: UInt): Bool = {
reqSource === Prefetch2L2BOP.id.U ||
reqSource === Prefetch2L2PBOP.id.U ||
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