ArteryTek · Maxjta · Jun 22, 2026
diff --git a/src/flash/nor/at32f4xx.c b/src/flash/nor/at32f4xx.c
@@ -362,7 +362,7 @@ static int at32_get_device_info(struct flash_bank *bank)
 				at32x_info->cur_reg_base = at32_mcu_type[at32x_info->type_id].flash_bank1_reg;
 		}
 		else if((at32x_info->bank_addr == BANK2_BASE_ADDR || 
-		    at32x_info->bank_addr == BANK2_BASE_ADDR_4M) && 
+		    at32x_info->bank_addr == BANK2_BASE_ADDR_4M || at32x_info->bank_addr == 0) && 
 		   at32x_info->flash_size > 512)
 		{
 		      if(at32x_info->cur_reg_base == 0)
@@ -385,6 +385,7 @@ static int at32_get_device_info(struct flash_bank *bank)
 				}
 				else
 				{
+					at32x_info->bank_addr = BANK1_BASE_ADDR + 0x200000;
 					at32x_info->bank_size = (at32x_info->flash_size << 10) - 0x200000;
 					at32x_info->sector_num = at32x_info->bank_size / at32x_info->sector_size;
 				}
@@ -399,6 +400,7 @@ static int at32_get_device_info(struct flash_bank *bank)
 				}
 				else
 				{
+					at32x_info->bank_addr = BANK1_BASE_ADDR + 0x80000;
 					at32x_info->bank_size = (at32x_info->flash_size << 10) - 0x80000;
 					at32x_info->sector_num = at32x_info->bank_size / at32x_info->sector_size;
 				}
@@ -410,6 +412,7 @@ static int at32_get_device_info(struct flash_bank *bank)
 			at32x_info->bank_size = at32x_info->flash_size << 10;		
 		}
 		at32x_info->probed = 1;
+		bank->base = at32x_info->bank_addr;
 		LOG_INFO("main flash size: 0x%" PRIx32 ", sector num:  0x%" PRIx32 ", sector size: 0x%" PRIx32 ",  bank size: 0x%" PRIx32 "", 
 				 (at32x_info->flash_size << 10),  at32x_info->sector_num,  at32x_info->sector_size, at32x_info->bank_size);
 	}
@@ -941,7 +944,6 @@ static int at32x_write(struct flash_bank *bank, const uint8_t *buffer,
 	return retval;
 }
 
-
 static int at32x_probe(struct flash_bank *bank)
 {
 	struct at32_flash_info *at32x_info = bank->driver_priv;

diff --git a/tcl/target/at32f403axx.cfg b/tcl/target/at32f403axx.cfg
@@ -57,6 +57,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.bank1
 flash bank $_FLASHNAME $_CHIPNAME 0x08000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.bank2
+flash bank $_FLASHNAME $_CHIPNAME 0x08080000 0 0 0 $_TARGETNAME
 
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz

diff --git a/tcl/target/at32f403exx.cfg b/tcl/target/at32f403exx.cfg
@@ -0,0 +1,94 @@
+# script for AT32f4xx family
+
+#
+# AT32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at32f4xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } else {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.bank1
+flash bank $_FLASHNAME $_CHIPNAME 0x08000000 0 0 0 $_TARGETNAME 0x40022000 0x1FFFF800
+set _FLASHNAME $_CHIPNAME.bank2
+flash bank $_FLASHNAME $_CHIPNAME 0x08080000 0 0 0 $_TARGETNAME 0x40022040 0x1FFFF800
+
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 5000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40021030 0x02000000
+	mww 0x40021054 0x0000020d
+	sleep 1
+}
diff --git a/tcl/target/at32f406xx.cfg b/tcl/target/at32f406xx.cfg
@@ -0,0 +1,92 @@
+# script for AT32f4xx family
+
+#
+# AT32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at32f4xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } else {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.bank1
+flash bank $_FLASHNAME $_CHIPNAME 0x08000000 0 0 0 $_TARGETNAME 0x40023C00 0x1FFFF800
+
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 5000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x400238A0 0x000F5000
+	mww 0x40023C00 0x000001F1
+	sleep 1
+}
diff --git a/tcl/target/at32f407exx.cfg b/tcl/target/at32f407exx.cfg
@@ -0,0 +1,94 @@
+# script for AT32f4xx family
+
+#
+# AT32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at32f4xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } else {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.bank1
+flash bank $_FLASHNAME $_CHIPNAME 0x08000000 0 0 0 $_TARGETNAME 0x40022000 0x1FFFF800
+set _FLASHNAME $_CHIPNAME.bank2
+flash bank $_FLASHNAME $_CHIPNAME 0x08080000 0 0 0 $_TARGETNAME 0x40022040 0x1FFFF800
+
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 5000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40021030 0x02000000
+	mww 0x40021054 0x0000020d
+	sleep 1
+}
diff --git a/tcl/target/at32f407xx.cfg b/tcl/target/at32f407xx.cfg
@@ -57,6 +57,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.bank1
 flash bank $_FLASHNAME $_CHIPNAME 0x08000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.bank2
+flash bank $_FLASHNAME $_CHIPNAME 0x08080000 0 0 0 $_TARGETNAME
 
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz