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7 changes: 7 additions & 0 deletions .travis.yml
Original file line number Diff line number Diff line change
Expand Up @@ -82,3 +82,10 @@ matrix:

notifications:
email: false

branches:
# Don't build these branches
except:
# Used by bors
- trying.tmp
- staging.tmp
3 changes: 3 additions & 0 deletions bors.toml
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
status = [
"continuous-integration/travis-ci/push",
]
40 changes: 20 additions & 20 deletions src/elision.rs
Original file line number Diff line number Diff line change
Expand Up @@ -57,11 +57,11 @@ impl AtomicElisionExt for AtomicUsize {
fn elision_compare_exchange_acquire(&self, current: usize, new: usize) -> Result<usize, usize> {
unsafe {
let prev: usize;
asm!("xacquire; lock; cmpxchgl $2, $1"
: "={eax}" (prev), "+*m" (self)
: "r" (new), "{eax}" (current)
: "memory"
: "volatile");
llvm_asm!("xacquire; lock; cmpxchgl $2, $1"
: "={eax}" (prev), "+*m" (self)
: "r" (new), "{eax}" (current)
: "memory"
: "volatile");
if prev == current {
Ok(prev)
} else {
Expand All @@ -74,11 +74,11 @@ impl AtomicElisionExt for AtomicUsize {
fn elision_compare_exchange_acquire(&self, current: usize, new: usize) -> Result<usize, usize> {
unsafe {
let prev: usize;
asm!("xacquire; lock; cmpxchgq $2, $1"
: "={rax}" (prev), "+*m" (self)
: "r" (new), "{rax}" (current)
: "memory"
: "volatile");
llvm_asm!("xacquire; lock; cmpxchgq $2, $1"
: "={rax}" (prev), "+*m" (self)
: "r" (new), "{rax}" (current)
: "memory"
: "volatile");
if prev == current {
Ok(prev)
} else {
Expand All @@ -92,11 +92,11 @@ impl AtomicElisionExt for AtomicUsize {
fn elision_fetch_sub_release(&self, val: usize) -> usize {
unsafe {
let prev: usize;
asm!("xrelease; lock; xaddl $2, $1"
: "=r" (prev), "+*m" (self)
: "0" (val.wrapping_neg())
: "memory"
: "volatile");
llvm_asm!("xrelease; lock; xaddl $2, $1"
: "=r" (prev), "+*m" (self)
: "0" (val.wrapping_neg())
: "memory"
: "volatile");
prev
}
}
Expand All @@ -105,11 +105,11 @@ impl AtomicElisionExt for AtomicUsize {
fn elision_fetch_sub_release(&self, val: usize) -> usize {
unsafe {
let prev: usize;
asm!("xrelease; lock; xaddq $2, $1"
: "=r" (prev), "+*m" (self)
: "0" (val.wrapping_neg())
: "memory"
: "volatile");
llvm_asm!("xrelease; lock; xaddq $2, $1"
: "=r" (prev), "+*m" (self)
: "0" (val.wrapping_neg())
: "memory"
: "volatile");
prev
}
}
Expand Down
2 changes: 1 addition & 1 deletion src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@

#![warn(missing_docs)]
#![warn(rust_2018_idioms)]
#![cfg_attr(feature = "nightly", feature(asm))]
#![cfg_attr(feature = "nightly", feature(llvm_asm))]

mod condvar;
mod elision;
Expand Down