From 6dd7316a8a766a3bee5c4baac5014629d749a03f Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 12 Aug 2026 06:43:41 +0300 Subject: [PATCH 1/3] fix typo in sc_lib_experimental_enable_pmu_counters --- tcl/syntacore/sc_fpga_lib.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcl/syntacore/sc_fpga_lib.tcl b/tcl/syntacore/sc_fpga_lib.tcl index bfcc8d8959..3c1927eaf8 100644 --- a/tcl/syntacore/sc_fpga_lib.tcl +++ b/tcl/syntacore/sc_fpga_lib.tcl @@ -140,7 +140,7 @@ namespace eval _SC_INTERNALS { en_ir pmu_ctrs } { set pmu_ctrs [lsort -unique $pmu_ctrs] - if {[llength pmu_ctrs] > $pmu_ctrs_max} { + if {[llength $pmu_ctrs] > $pmu_ctrs_max} { error "too many PMU counters requested was requested" } set inhibit_value 0xffffffff From 9a346813c2f15cad32442d8c26e91ea67cb3e8a8 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 12 Aug 2026 06:39:24 +0300 Subject: [PATCH 2/3] scr5: fix incorrect value returned by -scr5-tlb-csr-base --- src/target/riscv/scr5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/scr5.c b/src/target/riscv/scr5.c index 15946053a7..2df3a6f6df 100644 --- a/src/target/riscv/scr5.c +++ b/src/target/riscv/scr5.c @@ -155,7 +155,7 @@ static int scr5_jim_configure(struct target *target, if (!goi->is_configure) { if (goi->argc != 0) goto cget_extra_args; - Jim_SetResultFormatted(goi->interp, "%u", pc->tlb_n_entries); + Jim_SetResultFormatted(goi->interp, "%u", pc->tlb_csr_base); return JIM_OK; } e = jim_getopt_wide(goi, &w); From f5a4a8a2387acd6a367e9f048fcb0994647fc496 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 12 Aug 2026 07:15:34 +0300 Subject: [PATCH 3/3] scr5: fix UB in tlb search routin on 64-bit targets --- src/target/riscv/scr5.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/target/riscv/scr5.c b/src/target/riscv/scr5.c index 2df3a6f6df..7ae165585a 100644 --- a/src/target/riscv/scr5.c +++ b/src/target/riscv/scr5.c @@ -230,7 +230,9 @@ static int scr5_search_tlb(struct target *target, target_addr_t virt_addr, for (unsigned int tlb_sel = 0; tlb_sel <= 1; ++tlb_sel) { for (unsigned int pte_idx = 0; pte_idx < pc->tlb_n_entries; ++pte_idx) { res = riscv_reg_set(target, tlb_scan_csr, - tlb_sel << tlb_sel_offset | pte_idx); + ((riscv_reg_t)tlb_sel << tlb_sel_offset) | pte_idx); + if (res != ERROR_OK) + goto cleanup; riscv_reg_t tlb_attr, tlb_va; res = riscv_reg_get(target, &tlb_attr, tlb_attr_csr); if (res != ERROR_OK)