Simplify cbloq.to_cirq_circuit() with sensible defaults and add cbloq.to_cirq_circuit_and_quregs() (#927)

* Simplify cbloq.to_cirq_circuit() with sensible defaults and add cbloq.to_cirq_circuit_and_quregs

* Update call sites to use to_cirq_circuit

* Fix tests and mypy

* Fix another typo

---------

Co-authored-by: Matthew Harrigan <mpharrigan@google.com>

Author: tanujkhattar

qualtran/_infra/composite_bloq.py

@@ -49,7 +49,6 @@
     import cirq
 
     from qualtran.cirq_interop._cirq_to_bloq import CirqQuregInT, CirqQuregT
-    from qualtran.cirq_interop.t_complexity_protocol import TComplexity
     from qualtran.resource_counting import BloqCountT, SympySymbolAllocator
     from qualtran.simulation.classical_sim import ClassicalValT
 
@@ -139,16 +138,19 @@ def as_cirq_op(
         """Return a cirq.CircuitOperation containing a cirq-exported version of this cbloq."""
         import cirq
 
-        circuit, out_quregs = self.to_cirq_circuit(qubit_manager=qubit_manager, **cirq_quregs)
+        circuit, out_quregs = self.to_cirq_circuit_and_quregs(
+            qubit_manager=qubit_manager, cirq_quregs=cirq_quregs
+        )
         return cirq.CircuitOperation(circuit), out_quregs
 
-    def to_cirq_circuit(
-        self, qubit_manager: Optional['cirq.QubitManager'] = None, **cirq_quregs: 'CirqQuregInT'
+    def to_cirq_circuit_and_quregs(
+        self, qubit_manager: Optional['cirq.QubitManager'] = None, **cirq_quregs
     ) -> Tuple['cirq.FrozenCircuit', Dict[str, 'CirqQuregT']]:
-        """Convert this CompositeBloq to a `cirq.Circuit`.
+        """Convert this CompositeBloq to a `cirq.Circuit` and output qubit registers.
 
         Args:
-            qubit_manager: A `cirq.QubitManager` to allocate new qubits.
+            qubit_manager: A `cirq.QubitManager` to allocate new qubits. If not provided,
+                uses `cirq.SimpleQubitManager()` by default.
             **cirq_quregs: Mapping from left register names to Cirq qubit arrays.
 
         Returns:
@@ -166,6 +168,30 @@ def to_cirq_circuit(
             self.signature, cirq_quregs, self._binst_graph, qubit_manager=qubit_manager
         )
 
+    def to_cirq_circuit(
+        self,
+        *,
+        qubit_manager: Optional['cirq.QubitManager'] = None,
+        cirq_quregs: Optional[Mapping[str, 'CirqQuregInT']] = None,
+    ) -> 'cirq.FrozenCircuit':
+        """Convert this CompositeBloq to a `cirq.Circuit`.
+
+        Args:
+            qubit_manager: A `cirq.QubitManager` to allocate new qubits. If not provided,
+                uses `cirq.SimpleQubitManager()` by default.
+            cirq_quregs: Mapping from left register names to Cirq qubit arrays. If not provided,
+                uses `get_named_qubits(self.signature.lefts())` by default.
+
+        Returns:
+            circuit: The cirq.FrozenCircuit version of this composite bloq.
+        """
+        from qualtran._infra.gate_with_registers import get_named_qubits
+
+        if cirq_quregs is None:
+            cirq_quregs = get_named_qubits(self.signature.lefts())
+
+        return self.to_cirq_circuit_and_quregs(qubit_manager=qubit_manager, **cirq_quregs)[0]
+
     @classmethod
     def from_cirq_circuit(cls, circuit: 'cirq.Circuit') -> 'CompositeBloq':
         """Construct a composite bloq from a Cirq circuit.

qualtran/_infra/composite_bloq_test.py

@@ -40,7 +40,6 @@
 )
 from qualtran._infra.composite_bloq import _create_binst_graph, _get_dangling_soquets
 from qualtran._infra.data_types import BoundedQUInt, QAny, QBit, QFxp, QUInt
-from qualtran._infra.gate_with_registers import get_named_qubits
 from qualtran.bloqs.basic_gates import CNOT, IntEffect, ZeroEffect
 from qualtran.bloqs.for_testing.atom import TestAtom, TestTwoBitOp
 from qualtran.bloqs.for_testing.many_registers import TestMultiTypedRegister, TestQFxp
@@ -164,7 +163,9 @@ def test_map_soqs():
 
 def test_bb_composite_bloq():
     cbloq_auto = TestTwoCNOT().decompose_bloq()
-    circuit, _ = cbloq_auto.to_cirq_circuit(q1=[cirq.LineQubit(1)], q2=[cirq.LineQubit(2)])
+    circuit, _ = cbloq_auto.to_cirq_circuit_and_quregs(
+        q1=[cirq.LineQubit(1)], q2=[cirq.LineQubit(2)]
+    )
     cirq.testing.assert_has_diagram(
         circuit,
         desired="""\
@@ -174,6 +175,16 @@ def test_bb_composite_bloq():
     """,
     )
 
+    circuit = cbloq_auto.to_cirq_circuit()
+    cirq.testing.assert_has_diagram(
+        circuit,
+        desired="""\
+q1: ───@───X───
+       │   │
+q2: ───X───@───
+    """,
+    )
+
 
 def test_bloq_builder():
     signature = Signature.build(x=1, y=1)
@@ -344,7 +355,7 @@ def test_complicated_target_register():
     # note: this includes the two `Dangling` generations.
     assert len(list(nx.topological_generations(binst_graph))) == 2 * 3 + 2
 
-    circuit, _ = cbloq.to_cirq_circuit(None, **get_named_qubits(bloq.signature.lefts()))
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(
         circuit,
         """\

qualtran/_infra/controlled_test.py

@@ -100,7 +100,7 @@ def test_ctrl_bloq_as_cirq_op():
 
     def _test_cirq_equivalence(bloq: Bloq, gate: cirq.Gate):
         left_quregs = get_named_qubits(bloq.signature.lefts())
-        circuit1, right_quregs = bloq.as_composite_bloq().to_cirq_circuit(None, **left_quregs)
+        circuit1 = bloq.as_composite_bloq().to_cirq_circuit(cirq_quregs=left_quregs)
         circuit2 = cirq.Circuit(
             gate.on(*merge_qubits(bloq.signature, **get_named_qubits(bloq.signature)))
         )
@@ -124,7 +124,7 @@ def _test_cirq_equivalence(bloq: Bloq, gate: cirq.Gate):
     bloq = Controlled(Swap(5), CtrlSpec(qdtypes=QUInt(4), cvs=0b0101))
     quregs = get_named_qubits(bloq.signature)
     ctrl, x, y = quregs['ctrl'], quregs['x'], quregs['y']
-    circuit1, _ = bloq.decompose_bloq().to_cirq_circuit(None, **quregs)
+    circuit1 = bloq.decompose_bloq().to_cirq_circuit(cirq_quregs=quregs)
     circuit2 = cirq.Circuit(
         cirq.SWAP(x[i], y[i]).controlled_by(*ctrl, control_values=[0, 1, 0, 1]) for i in range(5)
     )

qualtran/bloqs/basic_gates/hadamard_test.py

@@ -25,7 +25,7 @@ def test_to_cirq():
     q = bb.add(OneState())
     q = bb.add(Hadamard(), q=q)
     cbloq = bb.finalize(q=q)
-    circuit, _ = cbloq.to_cirq_circuit()
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(circuit, "_c(0): ───X───H───")
     vec1 = cbloq.tensor_contract()
     vec2 = cirq.final_state_vector(circuit)

qualtran/bloqs/basic_gates/s_gate_test.py

@@ -33,7 +33,7 @@ def test_to_cirq():
     q = bb.add(PlusState())
     q = bb.add(SGate(), q=q)
     cbloq = bb.finalize(q=q)
-    circuit, _ = cbloq.to_cirq_circuit()
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(circuit, "_c(0): ───H───S───")
 
 

qualtran/bloqs/basic_gates/states_and_effects.ipynb

@@ -1037,7 +1037,7 @@
    "outputs": [],
    "source": [
     "from cirq.contrib.svg import SVGCircuit\n",
-    "circuit, qubits = cbloq.to_cirq_circuit()\n",
+    "circuit = cbloq.to_cirq_circuit()\n",
     "SVGCircuit(circuit)"
    ]
   }

qualtran/bloqs/basic_gates/swap_test.py

@@ -65,7 +65,9 @@ def test_two_bit_swap_unitary_vs_cirq():
 def test_two_bit_swap_as_cirq_op():
     q = cirq.LineQubit.range(2)
     expected_circuit = cirq.Circuit(cirq.SWAP(*q))
-    cbloq_to_circuit, quregs = TwoBitSwap().as_composite_bloq().to_cirq_circuit(x=[q[0]], y=[q[1]])
+    cbloq_to_circuit = (
+        TwoBitSwap().as_composite_bloq().to_cirq_circuit(cirq_quregs={'x': [q[0]], 'y': [q[1]]})
+    )
     cirq.testing.assert_same_circuits(expected_circuit, cbloq_to_circuit)
 
 

qualtran/bloqs/basic_gates/t_gate_test.py

@@ -39,7 +39,7 @@ def test_to_cirq():
     q = bb.add(TGate(), q=q)
     q = bb.add(TGate(is_adjoint=True), q=q)
     cbloq = bb.finalize(q=q)
-    circuit, _ = cbloq.to_cirq_circuit()
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(circuit, "_c(0): ───H───T───T^-1───")
 
 

qualtran/bloqs/basic_gates/toffoli_test.py

@@ -42,7 +42,7 @@ def test_toffoli_cirq():
     ctrl, target = bb.add(Toffoli(), ctrl=ctrl, target=target)
     cbloq = bb.finalize(q0=ctrl[0], q1=ctrl[1], q2=target)
 
-    circuit, qubits = cbloq.to_cirq_circuit()
+    circuit, qubits = cbloq.to_cirq_circuit_and_quregs()
     cirq.testing.assert_has_diagram(
         circuit,
         """\

qualtran/bloqs/basic_gates/x_basis_test.py

@@ -62,7 +62,7 @@ def test_to_cirq():
     q = bb.add(PlusState())
     q = bb.add(XGate(), q=q)
     cbloq = bb.finalize(q=q)
-    circuit, _ = cbloq.to_cirq_circuit()
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(circuit, "_c(0): ───H───X───")
     vec1 = cbloq.tensor_contract()
     vec2 = cirq.final_state_vector(circuit)
@@ -72,7 +72,7 @@ def test_to_cirq():
     q = bb.add(MinusState())
     q = bb.add(XGate(), q=q)
     cbloq = bb.finalize(q=q)
-    circuit, _ = cbloq.to_cirq_circuit()
+    circuit = cbloq.to_cirq_circuit()
     cirq.testing.assert_has_diagram(circuit, "_c(0): ───[ _c(0): ───X───H─── ]───X───")
     vec1 = cbloq.tensor_contract()
     vec2 = cirq.final_state_vector(circuit)