diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 79b8900fd0..5016a936e9 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -69,7 +69,7 @@ jobs: container: image: ${{ needs.build-docker.outputs.image_name }} steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 - name: Build docs run: make docs @@ -81,7 +81,7 @@ jobs: container: image: ${{ needs.build-docker.outputs.image_name }} steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 # For some reason, the checkout is done by a different user # than that deploying to Github (root, possibly due to Docker). # So we need to set the repository as a safe directory. @@ -106,7 +106,7 @@ jobs: container: image: ${{ needs.build-docker.outputs.image_name }} steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 - name: Run pytest run: pytest @@ -121,7 +121,7 @@ jobs: container: image: ${{ needs.build-docker.outputs.image_name }} steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: submodules: 'recursive' - name: Hash Verilator prerequisites @@ -133,7 +133,7 @@ jobs: flags: --recursive - name: Set up cache for Verilator build id: verilator-cache - uses: actions/cache@v3 + uses: actions/cache@v4 with: path: target/snitch_cluster/bin key: verilator-${{ steps.verilator-hash.outputs.hash }} diff --git a/.github/workflows/gitlab-ci.yaml b/.github/workflows/gitlab-ci.yaml index c2e8813360..57db5a7718 100644 --- a/.github/workflows/gitlab-ci.yaml +++ b/.github/workflows/gitlab-ci.yaml @@ -16,7 +16,7 @@ jobs: github.repository == 'pulp-platform/snitch_cluster' steps: - name: Check Gitlab CI - uses: pulp-platform/pulp-actions/gitlab-ci@v2.1.0 + uses: pulp-platform/pulp-actions/gitlab-ci@v2.4.3 with: domain: iis-git.ee.ethz.ch repo: github-mirror/snitch_cluster diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index ccc39720be..5724bfb4bf 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -18,7 +18,7 @@ jobs: github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name != github.repository steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - uses: chipsalliance/verible-linter-action@main with: paths: | @@ -53,9 +53,9 @@ jobs: github.event.pull_request.head.repo.full_name != github.repository steps: - name: Check License - uses: pulp-platform/pulp-actions/lint-license@v2.1.0 + uses: pulp-platform/pulp-actions/lint-license@v2.4.3 with: - patches: 0001-Allow-hash-comments-in-assembly.patch + linters_revision: 20250217_01 # We cover ETH Zurich and lowRISC licenses and Apache 2.0 # (mostly for SW) and Solderpad for the hardware. # yamllint disable rule:line-length @@ -67,6 +67,9 @@ jobs: match_regex: true exclude_paths: | sw/snRuntime/src/omp/interface.h + hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv + hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv + hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.svh ################## # Lint YML Files # @@ -78,7 +81,7 @@ jobs: github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name != github.repository steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - name: yaml-lint uses: ibiqlik/action-yamllint@v3 with: @@ -95,9 +98,9 @@ jobs: name: Lint Python Sources steps: - name: Check out source repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Set up Python environment - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: "3.11" - name: flake8 Lint @@ -117,7 +120,7 @@ jobs: github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name != github.repository steps: - - uses: actions/checkout@v3 - - uses: DoozyX/clang-format-lint-action@v0.18.1 + - uses: actions/checkout@v4 + - uses: DoozyX/clang-format-lint-action@v0.18.2 with: clangFormatVersion: 10 diff --git a/Bender.lock b/Bender.lock index 4c80c65cce..9e99213ed5 100644 --- a/Bender.lock +++ b/Bender.lock @@ -83,8 +83,8 @@ packages: - obi - register_interface obi: - revision: 8097928cf1b43712f93d5356f336397879b4ad2c - version: 0.1.6 + revision: 0155fc34e900c7c884e081c0a1114a247937ff69 + version: 0.1.7 source: Git: https://github.com/pulp-platform/obi.git dependencies: @@ -94,7 +94,7 @@ packages: revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 version: 0.4.5 source: - Git: https://github.com/pulp-platform/register_interface + Git: https://github.com/pulp-platform/register_interface.git dependencies: - apb - axi diff --git a/Bender.yml b/Bender.yml index 1ed9b5fbf6..75dc4bd1b1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,8 +22,8 @@ dependencies: axi: { git: https://github.com/colluca/axi, rev: multicast } axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics, version: 0.6.0 } common_cells: { git: https://github.com/pulp-platform/common_cells, rev: snitch } + apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.2 } FPnew: { git: https://github.com/pulp-platform/cvfpu.git, rev: pulp-v0.1.3 } - register_interface: { git: https://github.com/pulp-platform/register_interface, version: 0.4.2 } tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version: 0.2.13 } riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg, version: 0.8.0 } cluster_icache: { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 } @@ -155,7 +155,7 @@ sources: # Level 0 - hw/snitch_cluster/src/snitch_amo_shim.sv - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv - - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv + - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv - hw/snitch_cluster/src/snitch_fpu.sv - hw/snitch_cluster/src/snitch_sequencer.sv @@ -180,7 +180,6 @@ sources: # target/common - target: any(simulation, verilator) files: - - target/common/test/tb_memory_regbus.sv - target/common/test/tb_memory_axi.sv - target: test files: @@ -189,10 +188,10 @@ sources: # target/snitch_cluster - target: snitch_cluster_wrapper files: - - target/snitch_cluster/.generated/snitch_cluster_pkg.sv + - target/snitch_cluster/generated/snitch_cluster_pkg.sv - target: all(snitch_cluster_wrapper, not(postlayout)) files: - - target/snitch_cluster/.generated/snitch_cluster_wrapper.sv + - target/snitch_cluster/generated/snitch_cluster_wrapper.sv - target: all(snitch_cluster_wrapper, postlayout) files: - nonfree/gf12/fusion/runs/0/out/15/snitch_cluster_wrapper.v diff --git a/Makefile b/Makefile index ddadb304e5..6d7ffaac29 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ ############### BENDER ?= bender -REGGEN = $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py +PEAKRDL ?= peakrdl ######################### # Files and directories # @@ -80,8 +80,8 @@ clean-docs: $(GENERATED_DOCS_DIR): mkdir -p $@ -$(GENERATED_DOCS_DIR)/peripherals.md: hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson | $(GENERATED_DOCS_DIR) - $(REGGEN) -d $< > $@ +$(GENERATED_DOCS_DIR)/peripherals.md: hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl | $(GENERATED_DOCS_DIR) + $(PEAKRDL) markdown $< -o $@ $(DOXYGEN_DOCS_DIR): $(DOXYFILE) $(DOXYGEN_INPUTS) doxygen $< diff --git a/hw/snitch_cluster/src/snitch_cluster.sv b/hw/snitch_cluster/src/snitch_cluster.sv index 9124a09cd7..3a452427d3 100644 --- a/hw/snitch_cluster/src/snitch_cluster.sv +++ b/hw/snitch_cluster/src/snitch_cluster.sv @@ -12,7 +12,7 @@ `include "common_cells/registers.svh" `include "mem_interface/typedef.svh" -`include "register_interface/typedef.svh" +`include "apb/typedef.svh" `include "reqrsp_interface/typedef.svh" `include "tcdm_interface/typedef.svh" @@ -428,6 +428,10 @@ module snitch_cluster `AXI_TYPEDEF_ALL(axi_mst_dma, addr_t, id_dma_mst_t, data_dma_t, strb_dma_t, user_dma_t) `AXI_TYPEDEF_ALL(axi_slv_dma, addr_t, id_dma_slv_t, data_dma_t, strb_dma_t, user_dma_t) + `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) + + `APB_TYPEDEF_ALL(apb, addr_t, data_t, strb_t) + `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t) `MEM_TYPEDEF_ALL(mem, tcdm_mem_addr_t, data_t, strb_t, tcdm_user_t) @@ -435,9 +439,6 @@ module snitch_cluster `TCDM_TYPEDEF_ALL(tcdm, tcdm_addr_t, data_t, strb_t, tcdm_user_t) - `REG_BUS_TYPEDEF_REQ(reg_req_t, addr_t, data_t, strb_t) - `REG_BUS_TYPEDEF_RSP(reg_rsp_t, data_t) - // Event counter increments for the TCDM. typedef struct packed { /// Number requests going in @@ -604,8 +605,10 @@ module snitch_cluster reqrsp_rsp_t [NrHives-1:0] ptw_rsp; // 5. Peripheral Subsystem - reg_req_t reg_req; - reg_rsp_t reg_rsp; + axi_lite_req_t axi_lite_req; + axi_lite_resp_t axi_lite_resp; + apb_req_t apb_req; + apb_resp_t apb_resp; // 5. Misc. Wires. logic icache_prefetch_enable; @@ -1374,26 +1377,59 @@ module snitch_cluster ); // 2. Peripherals - axi_to_reg #( - .ADDR_WIDTH (PhysicalAddrWidth), - .DATA_WIDTH (NarrowDataWidth), - .AXI_MAX_WRITE_TXNS (1), - .AXI_MAX_READ_TXNS (1), - .DECOUPLE_W (0), - .ID_WIDTH (NarrowIdWidthOut), - .USER_WIDTH (NarrowUserWidth), - .axi_req_t (axi_slv_req_t), - .axi_rsp_t (axi_slv_resp_t), - .reg_req_t (reg_req_t), - .reg_rsp_t (reg_rsp_t) - ) i_axi_to_reg ( - .clk_i, - .rst_ni, - .testmode_i (1'b0), - .axi_req_i (narrow_axi_slv_req[ClusterPeripherals]), - .axi_rsp_o (narrow_axi_slv_rsp[ClusterPeripherals]), - .reg_req_o (reg_req), - .reg_rsp_i (reg_rsp) + axi_to_axi_lite #( + .AxiAddrWidth (PhysicalAddrWidth), + .AxiDataWidth (NarrowDataWidth), + .AxiIdWidth (NarrowIdWidthOut), + .AxiUserWidth (NarrowUserWidth), + .AxiMaxWriteTxns(1), + .AxiMaxReadTxns (1), + .full_req_t (axi_slv_req_t), + .full_resp_t (axi_slv_resp_t), + .lite_req_t (axi_lite_req_t), + .lite_resp_t (axi_lite_resp_t) + ) i_axi_to_axi_lite ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .test_i (1'b0), + .slv_req_i (narrow_axi_slv_req[ClusterPeripherals]), + .slv_resp_o(narrow_axi_slv_rsp[ClusterPeripherals]), + .mst_req_o (axi_lite_req), + .mst_resp_i(axi_lite_resp) + ); + + // There is only one APB slave in the cluster, at index 0. + localparam int unsigned NumApbSlaves = 1; + localparam int unsigned NumApbConvRules = (1 + AliasRegionEnable) * NumApbSlaves; + xbar_rule_t [NumApbConvRules-1:0] apb_conv_rules; + + assign apb_conv_rules[0] = '{ + idx: 0, start_addr: cluster_periph_start_address, end_addr: cluster_periph_end_address + }; + if (AliasRegionEnable) begin : gen_apb_alias + assign apb_conv_rules[1] = '{ + idx: 0, start_addr: PeriphAliasStart, end_addr: PeriphAliasEnd + }; + end + + axi_lite_to_apb #( + .NoApbSlaves (NumApbSlaves), + .NoRules (NumApbConvRules), + .AddrWidth (PhysicalAddrWidth), + .DataWidth (NarrowDataWidth), + .axi_lite_req_t (axi_lite_req_t), + .axi_lite_resp_t (axi_lite_resp_t), + .apb_req_t (apb_req_t), + .apb_resp_t (apb_resp_t), + .rule_t (xbar_rule_t) + ) i_axi_lite_to_apb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .axi_lite_req_i (axi_lite_req), + .axi_lite_resp_o(axi_lite_resp), + .apb_req_o (apb_req), + .apb_resp_i (apb_resp), + .addr_map_i (apb_conv_rules) ); if (IntBootromEnable) begin : gen_bootrom @@ -1442,8 +1478,11 @@ module snitch_cluster end snitch_cluster_peripheral #( - .reg_req_t (reg_req_t), - .reg_rsp_t (reg_rsp_t), + .addr_t (addr_t), + .data_t (data_t), + .strb_t (strb_t), + .apb_req_t (apb_req_t), + .apb_resp_t (apb_resp_t), .tcdm_events_t (tcdm_events_t), .dma_events_t (dma_events_t), .NrCores (NrCores), @@ -1451,8 +1490,8 @@ module snitch_cluster ) i_snitch_cluster_peripheral ( .clk_i, .rst_ni, - .reg_req_i (reg_req), - .reg_rsp_o (reg_rsp), + .apb_req_i (apb_req), + .apb_resp_o (apb_resp), .icache_prefetch_enable_o (icache_prefetch_enable), .cl_clint_o (cl_interrupt), .core_events_i (core_events), diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv index 14fa529150..8db5368e0e 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv @@ -16,16 +16,19 @@ module snitch_cluster_peripheral // Nr of DMA channels parameter int unsigned DMANumChannels = 0, parameter int unsigned DMADataWidth = 0, - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, + parameter type addr_t = logic, + parameter type data_t = logic, + parameter type strb_t = logic, + parameter type apb_req_t = logic, + parameter type apb_resp_t = logic, parameter type tcdm_events_t = logic, parameter type dma_events_t = logic ) ( input logic clk_i, input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, + input apb_req_t apb_req_i, + output apb_resp_t apb_resp_o, output logic icache_prefetch_enable_o, output logic [NrCores-1:0] cl_clint_o, @@ -43,74 +46,41 @@ module snitch_cluster_peripheral `FF(dma_events_q, dma_events_i, '0) `FF(icache_events_q, icache_events_i, '0) - snitch_cluster_peripheral_reg2hw_t reg2hw; - snitch_cluster_peripheral_hw2reg_t hw2reg; - - snitch_cluster_peripheral_reg_top #( - .reg_req_t (reg_req_t), - .reg_rsp_t (reg_rsp_t) - ) i_snitch_cluster_peripheral_reg_top ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .reg_req_i (reg_req_i), - .reg_rsp_o (reg_rsp_o), - .devmode_i (1'b0), - .reg2hw (reg2hw), - .hw2reg (hw2reg) + snitch_cluster_peripheral_reg__out_t reg2hw; + snitch_cluster_peripheral_reg__in_t hw2reg; + + snitch_cluster_peripheral_reg i_snitch_cluster_peripheral_reg ( + .clk (clk_i), + .arst_n (rst_ni), + .s_apb_psel ( apb_req_i.psel ), + .s_apb_penable ( apb_req_i.penable ), + .s_apb_pwrite ( apb_req_i.pwrite ), + .s_apb_pprot ( apb_req_i.pprot ), + .s_apb_paddr (apb_req_i.paddr[SNITCH_CLUSTER_PERIPHERAL_REG_MIN_ADDR_WIDTH-1:0]), + .s_apb_pwdata ( apb_req_i.pwdata ), + .s_apb_pstrb ( apb_req_i.pstrb ), + .s_apb_pready ( apb_resp_o.pready ), + .s_apb_prdata ( apb_resp_o.prdata ), + .s_apb_pslverr ( apb_resp_o.pslverr ), + .hwif_out (reg2hw), + .hwif_in (hw2reg) ); - // As defined in the `.hjson` file. Unfortunately, - // The regtool does not generate enums for SV, - // only for C. So we have to define them here. - typedef enum logic[4:0] { - Cycle = 5'd0, - TcdmAccessed = 5'd1, - TcdmCongested = 5'd2, - IssueFpu = 5'd3, - IssueFpuSeq = 5'd4, - IssueCoreToFpu = 5'd5, - RetiredInstr = 5'd6, - RetiredLoad = 5'd7, - RetiredI = 5'd8, - RetiredAcc = 5'd9, - DmaAwStall = 5'd10, - DmaArStall = 5'd11, - DmaRStall = 5'd12, - DmaWStall = 5'd13, - DmaBufWStall = 5'd14, - DmaBufRStall = 5'd15, - DmaAwDone = 5'd16, - DmaAwBw = 5'd17, - DmaArDone = 5'd18, - DmaArBw = 5'd19, - DmaRDone = 5'd20, - DmaRBw = 5'd21, - DmaWDone = 5'd22, - DmaWBw = 5'd23, - DmaBDone = 5'd24, - DmaBusy = 5'd25, - IcacheMiss = 5'd26, - IcacheHit = 5'd27, - IcachePrefetch = 5'd28, - IcacheDoubleHit = 5'd29, - IcacheStall = 5'd30, - NumMetrics = 5'd31 - } perf_metrics_e; - // The metrics that should be tracked immediately after reset. localparam int unsigned NumPerfMetricRstValues = 7; - localparam perf_metrics_e PerfMetricRstValues[NumPerfMetricRstValues] = '{ - Cycle, - RetiredInstr, - TcdmAccessed, - IcacheMiss, - IcacheHit, - IcachePrefetch, - IcacheStall + localparam snitch_cluster_peripheral_reg__perf_metric_e + PerfMetricRstValues[NumPerfMetricRstValues] = '{ + snitch_cluster_peripheral_reg__perf_metric__cycle, + snitch_cluster_peripheral_reg__perf_metric__retired_instr, + snitch_cluster_peripheral_reg__perf_metric__tcdm_accessed, + snitch_cluster_peripheral_reg__perf_metric__icache_miss, + snitch_cluster_peripheral_reg__perf_metric__icache_hit, + snitch_cluster_peripheral_reg__perf_metric__icache_prefetch, + snitch_cluster_peripheral_reg__perf_metric__icache_stall }; logic [NumPerfCounters-1:0][47:0] perf_cnt_q, perf_cnt_d; - perf_metrics_e [NumPerfCounters-1:0] perf_metrics_q, perf_metrics_d; + snitch_cluster_peripheral_reg__perf_metric_e [NumPerfCounters-1:0] perf_metrics_q, perf_metrics_d; logic [NumPerfCounters-1:0][$clog2(NrCores)-1:0] perf_hart_sel_q, perf_hart_sel_d; logic [31:0] cl_clint_d, cl_clint_q; @@ -118,25 +88,42 @@ module snitch_cluster_peripheral // cl_clint_set/cl_clint_clear always_comb begin cl_clint_d = cl_clint_q; - if (reg2hw.cl_clint_set.qe) begin - cl_clint_d = cl_clint_q | reg2hw.cl_clint_set.q; - end else if (reg2hw.cl_clint_clear.qe) begin - cl_clint_d = cl_clint_q & ~reg2hw.cl_clint_clear.q; + if (reg2hw.cl_clint_set.req && reg2hw.cl_clint_set.req_is_wr) begin + cl_clint_d = cl_clint_q | (reg2hw.cl_clint_set.wr_biten.cl_clint_set & + reg2hw.cl_clint_set.wr_data.cl_clint_set); + end else if (reg2hw.cl_clint_clear.req && reg2hw.cl_clint_clear.req_is_wr) begin + cl_clint_d = cl_clint_q & ~(reg2hw.cl_clint_clear.wr_biten.cl_clint_clear & + reg2hw.cl_clint_clear.wr_data.cl_clint_clear); end end `FF(cl_clint_q, cl_clint_d, '0, clk_i, rst_ni) assign cl_clint_o = cl_clint_q[NrCores-1:0]; // Enable icache prefetch - assign icache_prefetch_enable_o = reg2hw.icache_prefetch_enable.q; + assign icache_prefetch_enable_o = reg2hw.icache_prefetch_enable.icache_prefetch_enable.value; // Continuously assign the perf values. for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_assign - assign hw2reg.perf_cnt[i].d = perf_cnt_q[i]; - assign hw2reg.perf_cnt_sel[i].metric.d = perf_metrics_q[i]; - assign hw2reg.perf_cnt_sel[i].hart.d = perf_hart_sel_q[i]; + assign hw2reg.perf_regs.perf_cnt[i].rd_data.perf_counter = perf_cnt_q[i]; + assign hw2reg.perf_regs.perf_cnt_sel[i].rd_data.metric = perf_metrics_q[i]; + assign hw2reg.perf_regs.perf_cnt_sel[i].rd_data.hart = perf_hart_sel_q[i]; + assign hw2reg.perf_regs.perf_cnt[i].rd_ack = reg2hw.perf_regs.perf_cnt[i].req & + !reg2hw.perf_regs.perf_cnt[i].req_is_wr; + assign hw2reg.perf_regs.perf_cnt_sel[i].rd_ack = reg2hw.perf_regs.perf_cnt_sel[i].req & + !reg2hw.perf_regs.perf_cnt_sel[i].req_is_wr; + assign hw2reg.perf_regs.perf_cnt[i].wr_ack = reg2hw.perf_regs.perf_cnt[i].req & + reg2hw.perf_regs.perf_cnt[i].req_is_wr; + assign hw2reg.perf_regs.perf_cnt_sel[i].wr_ack = reg2hw.perf_regs.perf_cnt_sel[i].req & + reg2hw.perf_regs.perf_cnt_sel[i].req_is_wr; + assign hw2reg.perf_regs.perf_cnt[i].rd_data._reserved_63_48 = '0; + assign hw2reg.perf_regs.perf_cnt_sel[i].rd_data._reserved_63_32 = '0; end + assign hw2reg.cl_clint_set.wr_ack = reg2hw.cl_clint_set.req & + reg2hw.cl_clint_set.req_is_wr; + assign hw2reg.cl_clint_clear.wr_ack = reg2hw.cl_clint_clear.req & + reg2hw.cl_clint_clear.req_is_wr; + always_comb begin perf_cnt_d = perf_cnt_q; perf_metrics_d = perf_metrics_q; @@ -149,54 +136,92 @@ module snitch_cluster_peripheral sel_core_events = core_events_i[hart_select]; sel_dma_events = dma_events_q[hart_select]; unique case (perf_metrics_q[i]) - Cycle: perf_cnt_d[i] += 1; - TcdmAccessed: perf_cnt_d[i] += tcdm_events_q.inc_accessed; - TcdmCongested: perf_cnt_d[i] += tcdm_events_q.inc_congested; - IssueFpu: perf_cnt_d[i] += sel_core_events.issue_fpu; - IssueFpuSeq: perf_cnt_d[i] += sel_core_events.issue_fpu_seq; - IssueCoreToFpu: perf_cnt_d[i] += sel_core_events.issue_core_to_fpu; - RetiredInstr: perf_cnt_d[i] += sel_core_events.retired_instr; - RetiredLoad: perf_cnt_d[i] += sel_core_events.retired_load; - RetiredI: perf_cnt_d[i] += sel_core_events.retired_i; - RetiredAcc: perf_cnt_d[i] += sel_core_events.retired_acc; - DmaAwStall: perf_cnt_d[i] += sel_dma_events.aw_stall; - DmaArStall: perf_cnt_d[i] += sel_dma_events.ar_stall; - DmaRStall: perf_cnt_d[i] += sel_dma_events.r_stall; - DmaWStall: perf_cnt_d[i] += sel_dma_events.w_stall; - DmaBufWStall: perf_cnt_d[i] += sel_dma_events.buf_w_stall; - DmaBufRStall: perf_cnt_d[i] += sel_dma_events.buf_r_stall; - DmaAwDone: perf_cnt_d[i] += sel_dma_events.aw_done; - DmaAwBw: perf_cnt_d[i] += ((sel_dma_events.aw_len + 1) << (sel_dma_events.aw_size)); - DmaArDone: perf_cnt_d[i] += sel_dma_events.ar_done; - DmaArBw: perf_cnt_d[i] += ((sel_dma_events.ar_len + 1) << (sel_dma_events.ar_size)); - DmaRDone: perf_cnt_d[i] += sel_dma_events.r_done; - DmaRBw: perf_cnt_d[i] += DMADataWidth/8; - DmaWDone: perf_cnt_d[i] += sel_dma_events.w_done; - DmaWBw: perf_cnt_d[i] += sel_dma_events.num_bytes_written; - DmaBDone: perf_cnt_d[i] += sel_dma_events.b_done; - DmaBusy: perf_cnt_d[i] += sel_dma_events.dma_busy; - IcacheMiss: perf_cnt_d[i] += icache_events_q[hart_select].l0_miss; - IcacheHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_hit; - IcachePrefetch: perf_cnt_d[i] += icache_events_q[hart_select].l0_prefetch; - IcacheDoubleHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_double_hit; - IcacheStall: perf_cnt_d[i] += icache_events_q[hart_select].l0_stall; + snitch_cluster_peripheral_reg__perf_metric__cycle: perf_cnt_d[i] += 1; + snitch_cluster_peripheral_reg__perf_metric__tcdm_accessed: perf_cnt_d[i] += + tcdm_events_q.inc_accessed; + snitch_cluster_peripheral_reg__perf_metric__tcdm_congested: perf_cnt_d[i] += + tcdm_events_q.inc_congested; + snitch_cluster_peripheral_reg__perf_metric__issue_fpu: perf_cnt_d[i] += + sel_core_events.issue_fpu; + snitch_cluster_peripheral_reg__perf_metric__issue_fpu_seq: perf_cnt_d[i] += + sel_core_events.issue_fpu_seq; + snitch_cluster_peripheral_reg__perf_metric__issue_core_to_fpu: perf_cnt_d[i] += + sel_core_events.issue_core_to_fpu; + snitch_cluster_peripheral_reg__perf_metric__retired_instr: perf_cnt_d[i] += + sel_core_events.retired_instr; + snitch_cluster_peripheral_reg__perf_metric__retired_load: perf_cnt_d[i] += + sel_core_events.retired_load; + snitch_cluster_peripheral_reg__perf_metric__retired_i: perf_cnt_d[i] += + sel_core_events.retired_i; + snitch_cluster_peripheral_reg__perf_metric__retired_acc: perf_cnt_d[i] += + sel_core_events.retired_acc; + snitch_cluster_peripheral_reg__perf_metric__dma_aw_stall: perf_cnt_d[i] += + sel_dma_events.aw_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_ar_stall: perf_cnt_d[i] += + sel_dma_events.ar_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_r_stall: perf_cnt_d[i] += + sel_dma_events.r_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_w_stall: perf_cnt_d[i] += + sel_dma_events.w_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_buf_w_stall: perf_cnt_d[i] += + sel_dma_events.buf_w_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_buf_r_stall: perf_cnt_d[i] += + sel_dma_events.buf_r_stall; + snitch_cluster_peripheral_reg__perf_metric__dma_aw_done: perf_cnt_d[i] += + sel_dma_events.aw_done; + snitch_cluster_peripheral_reg__perf_metric__dma_aw_bw: perf_cnt_d[i] += + ((sel_dma_events.aw_len + 1) << (sel_dma_events.aw_size)); + snitch_cluster_peripheral_reg__perf_metric__dma_ar_done: perf_cnt_d[i] += + sel_dma_events.ar_done; + snitch_cluster_peripheral_reg__perf_metric__dma_ar_bw: perf_cnt_d[i] += + ((sel_dma_events.ar_len + 1) << (sel_dma_events.ar_size)); + snitch_cluster_peripheral_reg__perf_metric__dma_r_done: perf_cnt_d[i] += + sel_dma_events.r_done; + snitch_cluster_peripheral_reg__perf_metric__dma_r_bw: perf_cnt_d[i] += DMADataWidth/8; + snitch_cluster_peripheral_reg__perf_metric__dma_w_done: perf_cnt_d[i] += + sel_dma_events.w_done; + snitch_cluster_peripheral_reg__perf_metric__dma_w_bw: perf_cnt_d[i] += + sel_dma_events.num_bytes_written; + snitch_cluster_peripheral_reg__perf_metric__dma_b_done: perf_cnt_d[i] += + sel_dma_events.b_done; + snitch_cluster_peripheral_reg__perf_metric__dma_busy: perf_cnt_d[i] += + sel_dma_events.dma_busy; + snitch_cluster_peripheral_reg__perf_metric__icache_miss: perf_cnt_d[i] += + icache_events_q[hart_select].l0_miss; + snitch_cluster_peripheral_reg__perf_metric__icache_hit: perf_cnt_d[i] += + icache_events_q[hart_select].l0_hit; + snitch_cluster_peripheral_reg__perf_metric__icache_prefetch: perf_cnt_d[i] += + icache_events_q[hart_select].l0_prefetch; + snitch_cluster_peripheral_reg__perf_metric__icache_double_hit: perf_cnt_d[i] += + icache_events_q[hart_select].l0_double_hit; + snitch_cluster_peripheral_reg__perf_metric__icache_stall: perf_cnt_d[i] += + icache_events_q[hart_select].l0_stall; default:; endcase // Set performance metric. - if (reg2hw.perf_cnt_sel[i].metric.qe) begin - perf_metrics_d[i] = perf_metrics_e'(reg2hw.perf_cnt_sel[i].metric.q); + if (reg2hw.perf_regs.perf_cnt_sel[i].req && + reg2hw.perf_regs.perf_cnt_sel[i].req_is_wr && + |reg2hw.perf_regs.perf_cnt_sel[i].wr_biten.metric) begin + perf_metrics_d[i] = snitch_cluster_peripheral_reg__perf_metric_e'( + reg2hw.perf_regs.perf_cnt_sel[i].wr_data.metric); end // Set hart select. - if (reg2hw.perf_cnt_sel[i].hart.qe) begin - perf_hart_sel_d[i] = reg2hw.perf_cnt_sel[i].hart.q; + if (reg2hw.perf_regs.perf_cnt_sel[i].req && + reg2hw.perf_regs.perf_cnt_sel[i].req_is_wr && + |reg2hw.perf_regs.perf_cnt_sel[i].wr_biten.hart) begin + perf_hart_sel_d[i] = reg2hw.perf_regs.perf_cnt_sel[i].wr_data.hart; end end end // Performance counter FFs. for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_cnt - `FFLARNC(perf_cnt_q[i], perf_cnt_d[i], - reg2hw.perf_cnt_en[i], reg2hw.perf_cnt[i].qe, '0, clk_i, rst_ni) + logic perf_cnt_req_and_wr; + assign perf_cnt_req_and_wr = reg2hw.perf_regs.perf_cnt[i].req & + reg2hw.perf_regs.perf_cnt[i].req_is_wr; + `FFLARNC(perf_cnt_q[i], perf_cnt_d[i], reg2hw.perf_regs.perf_cnt_en[i].enable.value, + perf_cnt_req_and_wr, + '0, clk_i, rst_ni) end // Set reset values for the metrics that should be tracked immediately after reset. @@ -204,7 +229,8 @@ module snitch_cluster_peripheral if (i < NumPerfMetricRstValues) begin : gen_perf_metrics_rst_value `FF(perf_metrics_q[i], perf_metrics_d[i], PerfMetricRstValues[i], clk_i, rst_ni) end else begin : gen_perf_metrics_default - `FF(perf_metrics_q[i], perf_metrics_d[i], Cycle, clk_i, rst_ni) + `FF(perf_metrics_q[i], perf_metrics_d[i], + snitch_cluster_peripheral_reg__perf_metric__cycle, clk_i, rst_ni) end end diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson deleted file mode 100644 index 5f59e5fbdb..0000000000 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson +++ /dev/null @@ -1,374 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details. -{ - param_list: [ - { - name: "NumPerfCounters", - desc: "Number of performance counters", - type: "int", - default: "16" - }, - { - name: "NumCtrlScratch", - desc: "Number of scratch registers", - type: "int", - default: "4" - }, - ], - name: "snitch_cluster_peripheral", - clock_primary: "clk_i", - bus_interfaces: [ - { protocol: "reg_iface", direction: "device"} - ] - regwidth: 64, - registers: [ - { - multireg: { - name: "PERF_CNT_EN", - desc: "Enable a particular performance counter to start tracking." - swaccess: "rw", - hwaccess: "hro", - count: "NumPerfCounters", - cname: "perf_cnt_en", - compact: "false", - fields: [{ - bits: "0:0", - resval: "1", - name: "ENABLE", - desc: "Enable a particular performance counter to start tracking." - }] - } - }, - { - multireg: { - name: "PERF_CNT_SEL", - desc: "Select the metric that is tracked for each performance counter.", - swaccess: "rw", - hwaccess: "hrw", - count: "NumPerfCounters", - cname: "perf_cnt_sel", - hwext: "true", - hwqe: "true", - fields: [{ - bits: "15:0", - name: "HART", - desc: '''Select from which hart in the cluster, starting from `0`, - the event should be counted. For each performance counter - the cores can be selected individually. If a hart greater - than the cluster's total hart size is selected the selection - will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` - will be selected.''' - }, - { - bits: "31:16", - name: "METRIC", - desc: "Select the metric that is tracked for each performance counter", - enum: [{ - value: "0", - name: "CYCLE", - desc: "Cycle counter. Counts up as long as the cluster is powered." - }, - { - value: "1", - name: "TCDM_ACCESSED", - desc: ''' - Increased whenever the TCDM is accessed. Each individual access is tracked, - so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM, - so it doesn't matter whether the cores or for example the SSR hardware accesses - the TCDM. _This is a cluster-global signal._''' - }, - { - value: "2", - name: "TCDM_CONGESTED", - desc: ''' - Incremented whenever an access towards the TCDM is made but the arbitration - logic didn't grant the access (due to congestion). It's strictly less than TCDM_ACCESSED. - _This is a cluster-global signal._''' - }, - { - value: "3", - name: "ISSUE_FPU", - desc: ''' - Operations performed in the FPU. Includes both operations initiated by the - sequencer and by the core. When the Xfrep extension is available, this counter is - equivalent to ISSUE_FPU_SEQ (see description of ISSUE_FPU_SEQ). If the Xfrep extension - is not supported, then it is equivalent to ISSUE_CORE_TO_FPU. _This is a hart-local signal._''' - }, - { - value: "4", - name: "ISSUE_FPU_SEQ", - desc: ''' - Incremented whenever the FPU Sequencer issues an FPU instruction. - Might not be available if the hardware doesn't support FREP. - Note that all FP instructions offloaded by the core to the FPU are routed - through the sequencer (although not necessarily buffered) and thus are also counted. - The instructions issued independently by the FPU sequencer could thus be - calculated as ISSUE_FPU_SEQ_PROPER = ISSUE_FPU_SEQ - ISSUE_CORE_TO_FPU. - _This is a hart-local signal._''' - }, - { - value: "5", - name: "ISSUE_CORE_TO_FPU", - desc: '''Incremented whenever the core issues an FPU instruction. - _This is a hart-local signal._''' - }, - { - value: "6", - name: "RETIRED_INSTR", - desc: ''' - Instructions retired by the core, both offloaded and not. Does not - count instructions issued independently by the FPU sequencer. - _This is a hart-local signal._''' - }, - { - value: "7", - name: "RETIRED_LOAD", - desc: '''Load instructions retired by the core. _This is a hart-local signal._''' - }, - { - value: "8", - name: "RETIRED_I", - desc: '''Base instructions retired by the core. _This is a hart-local signal._''' - }, - { - value: "9", - name: "RETIRED_ACC", - desc: '''Offloaded instructions retired by the core. _This is a hart-local signal._''' - }, - { - value: "10", - name: "DMA_AW_STALL", - desc: ''' - Incremented whenever aw_valid = 1 but aw_ready = 0. - _This is a DMA-local signal_''' - }, - { - value: "11", - name: "DMA_AR_STALL", - desc: ''' - Incremented whenever ar_valid = 1 but ar_ready = 0. - _This is a DMA-local signal_''' - }, - { - value: "12", - name: "DMA_R_STALL", - desc: ''' - Incremented whenever r_ready = 1 but r_valid = 0. - _This is a DMA-local signal_''' - }, - { - value: "13", - name: "DMA_W_STALL", - desc: ''' - Incremented whenever w_valid = 1 but w_ready = 0. - _This is a DMA-local signal_''' - }, - { - value: "14", - name: "DMA_BUF_W_STALL", - desc: ''' - Incremented whenever w_ready = 1 but w_valid = 0. - _This is a DMA-local signal_''' - }, - { - value: "15", - name: "DMA_BUF_R_STALL", - desc: ''' - Incremented whenever r_valid = 1 but r_ready = 0. - _This is a DMA-local signal_''' - }, - { - value: "16", - name: "DMA_AW_DONE", - desc: ''' - Incremented whenever AW handshake occurs. - _This is a DMA-local signal_''' - }, - { - value: "17", - name: "DMA_AW_BW", - desc: ''' - Whenever AW handshake occurs, the counter is incremented - by the number of bytes transfered for this transaction - _This is a DMA-local signal_''' - }, - { - value: "18", - name: "DMA_AR_DONE", - desc: ''' - Incremented whenever AR handshake occurs. - _This is a DMA-local signal_''' - }, - { - value: "19", - name: "DMA_AR_BW", - desc: ''' - Whenever AR handshake occurs, the counter is incremented - by the number of bytes transfered for this transaction - _This is a DMA-local signal_''' - }, - { - value: "20", - name: "DMA_R_DONE", - desc: ''' - Incremented whenever R handshake occurs. - _This is a DMA-local signal_''' - }, - { - value: "21", - name: "DMA_R_BW", - desc: ''' - Whenever R handshake occurs, the counter is incremented - by the number of bytes transfered in this cycle - _This is a DMA-local signal_''' - }, - { - value: "22", - name: "DMA_W_DONE", - desc: ''' - Incremented whenvever W handshake occurs. - _This is a DMA-local signal_''' - }, - { - value: "23", - name: "DMA_W_BW", - desc: ''' - Whenever W handshake occurs, the counter is incremented - by the number of bytes transfered in this cycle - _This is a DMA-local signal_''' - }, - { - value: "24", - name: "DMA_B_DONE", - desc: ''' - Incremented whenever B handshake occurs. - _This is a DMA-local signal_''' - }, - { - value: "25", - name: "DMA_BUSY", - desc: ''' - Incremented whenever DMA is busy. - _This is a DMA-local signal_''' - }, - { - value: "26", - name: "ICACHE_MISS", - desc: ''' - Incremented for instruction cache misses. - _This is a hart-local signal_''' - }, - { - value: "27", - name: "ICACHE_HIT", - desc: ''' - Incremented for instruction cache hits. - _This is a hart-local signal_''' - }, - { - value: "28", - name: "ICACHE_PREFETCH", - desc: ''' - Incremented for instruction cache prefetches. - _This is a hart-local signal_''' - }, - { - value: "29", - name: "ICACHE_DOUBLE_HIT", - desc: ''' - Incremented for instruction cache double hit. - _This is a hart-local signal_''' - }, - { - value: "30", - name: "ICACHE_STALL", - desc: ''' - Incremented for instruction cache stalls. - _This is a hart-local signal_''' - }, - ] - }] - } - }, - { - multireg: { - name: "PERF_CNT", - desc: '''Performance counter. Set corresponding PERF_CNT_SEL register depending on what - performance metric and hart you would like to track.''' - swaccess: "rw", - hwaccess: "hrw", - count: "NumPerfCounters", - cname: "perf_cnt", - hwext: "true", - hwqe: "true", - fields: [{ - bits: "47:0", - name: "PERF_COUNTER", - desc: "Performance counter" - }] - } - }, - { - multireg: { - name: "SCRATCH", - desc: '''Scratch registers. Used in the bootrom for various purposes.''' - swaccess: "rw", - hwaccess: "none", - count: "NumCtrlScratch", - cname: "ctrl_scratch", - compact: "false", - fields: [{ - bits: "31:0", - name: "SCRATCH", - desc: "Scratch register" - }] - } - }, - { - name: "CL_CLINT_SET", - desc: ''' - Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt - of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID. - ''' - hwext: "true", - hwqe: "true", - swaccess: "wo", - hwaccess: "hro", - fields: [{ - bits: "31:0", - name: "CL_CLINT_SET", - desc: "Set cluster-local interrupt of hart i" - }] - }, - { - name: "CL_CLINT_CLEAR", - desc: ''' - Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt - of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID. - ''' - hwext: "true", - hwqe: "true", - swaccess: "wo", - hwaccess: "hro", - fields: [{ - bits: "31:0", - name: "CL_CLINT_CLEAR", - desc: "Clear cluster-local interrupt of hart i" - }] - }, - { - name: "ICACHE_PREFETCH_ENABLE", - desc: '''Controls prefetching of the instruction cache.''' - swaccess: "wo", - hwaccess: "hro", - resval: "1", - fields: [{ - bits: "0:0", - name: "ICACHE_PREFETCH_ENABLE", - desc: "Enable instruction prefetching." - }] - } - ] -} diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl new file mode 100644 index 0000000000..3b2369d1e3 --- /dev/null +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl @@ -0,0 +1,257 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +`ifndef __SNITCH_CLUSTER_PERIPHERAL_REG_RDL__ +`define __SNITCH_CLUSTER_PERIPHERAL_REG_RDL__ + +addrmap snitch_cluster_peripheral_reg #( + longint unsigned NumPerfCounters = 16, + longint unsigned NumCtrlScratch = 4 +) { + default regwidth=64; + + reg perf_cnt_en { + field { + name = "enable"; + desc = "Enable a particular performance counter to start tracking."; + hw = r; + sw = rw; + } enable[0:0] = 1; + }; + + enum perf_metric { + cycle = 0 { + desc = "Cycle counter. Counts up as long as the cluster is powered."; + }; + tcdm_accessed = 1 { + desc = "Increased whenever the TCDM is accessed. Each individual access is tracked, + so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM, + so it doesn't matter whether the cores or for example the SSR hardware accesses + the TCDM. _This is a cluster-global signal._"; + }; + tcdm_congested = 2 { + desc = "Incremented whenever an access towards the TCDM is made but the arbitration + logic didn't grant the access (due to congestion). It's strictly less than tcdm_accessed. + _This is a cluster-global signal._"; + }; + issue_fpu = 3 { + desc = "Operations performed in the FPU. Includes both operations initiated by the + sequencer and by the core. When the Xfrep extension is available, this counter is + equivalent to issue_fpu_seq (see description of issue_fpu_seq). If the Xfrep extension + is not supported, then it is equivalent to issue_core_to_fpu. _This is a hart-local signal._"; + }; + issue_fpu_seq = 4 { + desc = "Incremented whenever the FPU Sequencer issues an FPU instruction. + Might not be available if the hardware doesn't support FREP. + Note that all FP instructions offloaded by the core to the FPU are routed + through the sequencer (although not necessarily buffered) and thus are also counted. + The instructions issued independently by the FPU sequencer could thus be + calculated as issue_fpu_seq_proper = issue_fpu_seq - issue_core_to_fpu. + _This is a hart-local signal._"; + }; + issue_core_to_fpu = 5 { + desc = "Incremented whenever the core issues an FPU instruction. + _This is a hart-local signal._"; + }; + retired_instr = 6 { + desc = "Instructions retired by the core, both offloaded and not. Does not + count instructions issued independently by the FPU sequencer. + _This is a hart-local signal._"; + }; + retired_load = 7 { + desc = "Load instructions retired by the core. _This is a hart-local signal._"; + }; + retired_i = 8 { + desc = "Base instructions retired by the core. _This is a hart-local signal._"; + }; + retired_acc = 9 { + desc = "Offloaded instructions retired by the core. _This is a hart-local signal._"; + }; + dma_aw_stall = 10 { + desc = "Incremented whenever aw_valid = 1 but aw_ready = 0. + _This is a DMA-local signal_"; + }; + dma_ar_stall = 11 { + desc = "Incremented whenever ar_valid = 1 but ar_ready = 0. + _This is a DMA-local signal_"; + }; + dma_r_stall = 12 { + desc = "Incremented whenever r_ready = 1 but r_valid = 0. + _This is a DMA-local signal_"; + }; + dma_w_stall = 13 { + desc = "Incremented whenever w_valid = 1 but w_ready = 0. + _This is a DMA-local signal_"; + }; + dma_buf_w_stall = 14 { + desc = "Incremented whenever w_ready = 1 but w_valid = 0. + _This is a DMA-local signal_"; + }; + dma_buf_r_stall = 15 { + desc = "Incremented whenever r_valid = 1 but r_ready = 0. + _This is a DMA-local signal_"; + }; + dma_aw_done = 16 { + desc = "Incremented whenever AW handshake occurs. + _This is a DMA-local signal_"; + }; + dma_aw_bw = 17 { + desc = "Whenever AW handshake occurs, the counter is incremented + by the number of bytes transfered for this transaction + _This is a DMA-local signal_"; + }; + dma_ar_done = 18 { + desc = "Incremented whenever AR handshake occurs. + _This is a DMA-local signal_"; + }; + dma_ar_bw = 19 { + desc = "Whenever AR handshake occurs, the counter is incremented + by the number of bytes transfered for this transaction + _This is a DMA-local signal_"; + }; + dma_r_done = 20 { + desc = "Incremented whenever R handshake occurs. + _This is a DMA-local signal_"; + }; + dma_r_bw = 21 { + desc = "Whenever R handshake occurs, the counter is incremented + by the number of bytes transfered in this cycle + _This is a DMA-local signal_"; + }; + dma_w_done = 22 { + desc = "Incremented whenvever W handshake occurs. + _This is a DMA-local signal_"; + }; + dma_w_bw = 23 { + desc = "Whenever W handshake occurs, the counter is incremented + by the number of bytes transfered in this cycle + _This is a DMA-local signal_"; + }; + dma_b_done = 24 { + desc = "Incremented whenever B handshake occurs. + _This is a DMA-local signal_"; + }; + dma_busy = 25 { + desc = "Incremented whenever DMA is busy. + _This is a DMA-local signal_"; + }; + icache_miss = 26 { + desc = "Incremented for instruction cache misses. + _This is a hart-local signal_"; + }; + icache_hit = 27 { + desc = "Incremented for instruction cache hits. + _This is a hart-local signal_"; + }; + icache_prefetch = 28 { + desc = "Incremented for instruction cache prefetches. + _This is a hart-local signal_"; + }; + icache_double_hit = 29 { + desc = "Incremented for instruction cache double hit. + _This is a hart-local signal_"; + }; + icache_stall = 30 { + desc = "Incremented for instruction cache stalls. + _This is a hart-local signal_"; + }; + }; + + reg perf_cnt_sel { + desc = "Select the metric that is tracked for each performance counter."; + field { + name = "hart"; + desc = "Select from which hart in the cluster, starting from `0`, + the event should be counted. For each performance counter + the cores can be selected individually. If a hart greater + than the cluster's total hart size is selected the selection + will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` + will be selected."; + hw = rw; + sw = rw; + } hart[15:0]; + field { + name = "metric"; + desc = "Select the metric that is tracked for each performance counter"; + hw = rw; + sw = rw; + encode = perf_metric; + } metric[31:16]; + }; + + reg perf_cnt { + desc = "Performance counter. Set corresponding perf_cnt_sel register depending on what + performance metric and hart you would like to track."; + field { + desc = "Performance counter"; + hw = rw; + sw = rw; + onwrite = wclr; + } perf_counter[47:0]; + }; + + reg scratch { + desc = "Scratch registers. Used in the bootrom for various purposes."; + field { + desc = "Scratch register"; + hw = na; + sw = rw; + } scratch[31:0] = 0; + }; + + reg cl_clint_set { + desc = "Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt + of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID."; + field { + desc = "Set cluster-local interrupt of hart i"; + sw = w; + hw = r; + } cl_clint_set[31:0]; + }; + + reg cl_clint_clear { + desc = "Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt + of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID."; + field { + desc = "Set cluster-local interrupt of hart i"; + sw = w; + hw = r; + } cl_clint_clear[31:0]; + }; + + reg icache_prefetch_enable { + desc = "Controls prefetching of the instruction cache."; + field { + desc = "Enable instruction prefetching."; + hw = r; + sw = w; + } icache_prefetch_enable[0:0] = 1; + }; + + // Required for PeakRDL to define the `perf_metric` enum in + // the generated RTL file, as this seems not to be done for + // for registers defined to be `external`. + reg unused { + desc = "Unused register added to print enum"; + field { + sw=r; hw=na; + encode = perf_metric; + } f[4:0] = 0; + }; + + regfile perf_regs { + perf_cnt_en perf_cnt_en[NumPerfCounters]; + external perf_cnt_sel perf_cnt_sel[NumPerfCounters]; + external perf_cnt perf_cnt[NumPerfCounters]; + }; + + perf_regs perf_regs; + scratch scratch[NumCtrlScratch]; + external cl_clint_set cl_clint_set; + external cl_clint_clear cl_clint_clear; + icache_prefetch_enable icache_prefetch_enable; + unused unused; +}; + +`endif // __SNITCH_CLUSTER_PERIPHERAL_REG_RDL__ diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv new file mode 100644 index 0000000000..bec328548e --- /dev/null +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv @@ -0,0 +1,383 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +module snitch_cluster_peripheral_reg ( + input wire clk, + input wire arst_n, + + input wire s_apb_psel, + input wire s_apb_penable, + input wire s_apb_pwrite, + input wire [2:0] s_apb_pprot, + input wire [8:0] s_apb_paddr, + input wire [63:0] s_apb_pwdata, + input wire [7:0] s_apb_pstrb, + output logic s_apb_pready, + output logic [63:0] s_apb_prdata, + output logic s_apb_pslverr, + + input snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_reg__in_t hwif_in, + output snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_reg__out_t hwif_out + ); + + //-------------------------------------------------------------------------- + // CPU Bus interface logic + //-------------------------------------------------------------------------- + logic cpuif_req; + logic cpuif_req_is_wr; + logic [8:0] cpuif_addr; + logic [63:0] cpuif_wr_data; + logic [63:0] cpuif_wr_biten; + logic cpuif_req_stall_wr; + logic cpuif_req_stall_rd; + + logic cpuif_rd_ack; + logic cpuif_rd_err; + logic [63:0] cpuif_rd_data; + + logic cpuif_wr_ack; + logic cpuif_wr_err; + + // Request + logic is_active; + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + is_active <= '0; + cpuif_req <= '0; + cpuif_req_is_wr <= '0; + cpuif_addr <= '0; + cpuif_wr_data <= '0; + cpuif_wr_biten <= '0; + end else begin + if(~is_active) begin + if(s_apb_psel) begin + is_active <= '1; + cpuif_req <= '1; + cpuif_req_is_wr <= s_apb_pwrite; + cpuif_addr <= {s_apb_paddr[8:3], 3'b0}; + cpuif_wr_data <= s_apb_pwdata; + for(int i=0; i<8; i++) begin + cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}}; + end + end + end else begin + cpuif_req <= '0; + if(cpuif_rd_ack || cpuif_wr_ack) begin + is_active <= '0; + end + end + end + end + + // Response + assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack; + assign s_apb_prdata = cpuif_rd_data; + assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err; + + logic cpuif_req_masked; + logic external_req; + logic external_pending; + logic external_wr_ack; + logic external_rd_ack; + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + external_pending <= '0; + end else begin + if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1; + else if(external_wr_ack | external_rd_ack) external_pending <= '0; + `ifndef SYNTHESIS + assert(!external_wr_ack || (external_pending | external_req)) + else $error("An external wr_ack strobe was asserted when no external request was active"); + assert(!external_rd_ack || (external_pending | external_req)) + else $error("An external rd_ack strobe was asserted when no external request was active"); + `endif + end + end + + // Read & write latencies are balanced. Stalls not required + // except if external + assign cpuif_req_stall_rd = external_pending; + assign cpuif_req_stall_wr = external_pending; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); + + //-------------------------------------------------------------------------- + // Address Decode + //-------------------------------------------------------------------------- + typedef struct { + struct { + logic perf_cnt_en[16]; + logic perf_cnt_sel[16]; + logic perf_cnt[16]; + } perf_regs; + logic scratch[4]; + logic cl_clint_set; + logic cl_clint_clear; + logic icache_prefetch_enable; + logic unused; + } decoded_reg_strb_t; + decoded_reg_strb_t decoded_reg_strb; + logic decoded_strb_is_external; + + logic decoded_req; + logic decoded_req_is_wr; + logic [63:0] decoded_wr_data; + logic [63:0] decoded_wr_biten; + + always_comb begin + automatic logic is_external; + is_external = '0; + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.perf_regs.perf_cnt_en[i0] = cpuif_req_masked & (cpuif_addr == 9'h0 + (9)'(i0) * 9'h8); + end + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.perf_regs.perf_cnt_sel[i0] = cpuif_req_masked & (cpuif_addr == 9'h80 + (9)'(i0) * 9'h8); + is_external |= cpuif_req_masked & (cpuif_addr == 9'h80 + (9)'(i0) * 9'h8); + end + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.perf_regs.perf_cnt[i0] = cpuif_req_masked & (cpuif_addr == 9'h100 + (9)'(i0) * 9'h8); + is_external |= cpuif_req_masked & (cpuif_addr == 9'h100 + (9)'(i0) * 9'h8); + end + for(int i0=0; i0<4; i0++) begin + decoded_reg_strb.scratch[i0] = cpuif_req_masked & (cpuif_addr == 9'h180 + (9)'(i0) * 9'h8); + end + decoded_reg_strb.cl_clint_set = cpuif_req_masked & (cpuif_addr == 9'h1a0); + is_external |= cpuif_req_masked & (cpuif_addr == 9'h1a0) & cpuif_req_is_wr; + decoded_reg_strb.cl_clint_clear = cpuif_req_masked & (cpuif_addr == 9'h1a8); + is_external |= cpuif_req_masked & (cpuif_addr == 9'h1a8) & cpuif_req_is_wr; + decoded_reg_strb.icache_prefetch_enable = cpuif_req_masked & (cpuif_addr == 9'h1b0); + decoded_reg_strb.unused = cpuif_req_masked & (cpuif_addr == 9'h1b8); + decoded_strb_is_external = is_external; + external_req = is_external; + end + + // Pass down signals to next stage + assign decoded_req = cpuif_req_masked; + assign decoded_req_is_wr = cpuif_req_is_wr; + assign decoded_wr_data = cpuif_wr_data; + assign decoded_wr_biten = cpuif_wr_biten; + + //-------------------------------------------------------------------------- + // Field logic + //-------------------------------------------------------------------------- + typedef struct { + struct { + struct { + struct { + logic next; + logic load_next; + } enable; + } perf_cnt_en[16]; + } perf_regs; + struct { + struct { + logic [31:0] next; + logic load_next; + } scratch; + } scratch[4]; + struct { + struct { + logic next; + logic load_next; + } icache_prefetch_enable; + } icache_prefetch_enable; + } field_combo_t; + field_combo_t field_combo; + + typedef struct { + struct { + struct { + struct { + logic value; + } enable; + } perf_cnt_en[16]; + } perf_regs; + struct { + struct { + logic [31:0] value; + } scratch; + } scratch[4]; + struct { + struct { + logic value; + } icache_prefetch_enable; + } icache_prefetch_enable; + } field_storage_t; + field_storage_t field_storage; + + for(genvar i0=0; i0<16; i0++) begin + // Field: snitch_cluster_peripheral_reg.perf_regs.perf_cnt_en[].enable + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.perf_regs.perf_cnt_en[i0].enable.value; + load_next_c = '0; + if(decoded_reg_strb.perf_regs.perf_cnt_en[i0] && decoded_req_is_wr) begin // SW write + next_c = (field_storage.perf_regs.perf_cnt_en[i0].enable.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.perf_regs.perf_cnt_en[i0].enable.next = next_c; + field_combo.perf_regs.perf_cnt_en[i0].enable.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.perf_regs.perf_cnt_en[i0].enable.value <= 1'h1; + end else begin + if(field_combo.perf_regs.perf_cnt_en[i0].enable.load_next) begin + field_storage.perf_regs.perf_cnt_en[i0].enable.value <= field_combo.perf_regs.perf_cnt_en[i0].enable.next; + end + end + end + assign hwif_out.perf_regs.perf_cnt_en[i0].enable.value = field_storage.perf_regs.perf_cnt_en[i0].enable.value; + end + for(genvar i0=0; i0<16; i0++) begin + + assign hwif_out.perf_regs.perf_cnt_sel[i0].req = decoded_reg_strb.perf_regs.perf_cnt_sel[i0]; + assign hwif_out.perf_regs.perf_cnt_sel[i0].req_is_wr = decoded_req_is_wr; + assign hwif_out.perf_regs.perf_cnt_sel[i0].wr_data = decoded_wr_data; + assign hwif_out.perf_regs.perf_cnt_sel[i0].wr_biten = decoded_wr_biten; + end + for(genvar i0=0; i0<16; i0++) begin + + assign hwif_out.perf_regs.perf_cnt[i0].req = decoded_reg_strb.perf_regs.perf_cnt[i0]; + assign hwif_out.perf_regs.perf_cnt[i0].req_is_wr = decoded_req_is_wr; + assign hwif_out.perf_regs.perf_cnt[i0].wr_data = decoded_wr_data; + assign hwif_out.perf_regs.perf_cnt[i0].wr_biten = decoded_wr_biten; + end + for(genvar i0=0; i0<4; i0++) begin + // Field: snitch_cluster_peripheral_reg.scratch[].scratch + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.scratch[i0].scratch.value; + load_next_c = '0; + if(decoded_reg_strb.scratch[i0] && decoded_req_is_wr) begin // SW write + next_c = (field_storage.scratch[i0].scratch.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.scratch[i0].scratch.next = next_c; + field_combo.scratch[i0].scratch.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.scratch[i0].scratch.value <= 32'h0; + end else begin + if(field_combo.scratch[i0].scratch.load_next) begin + field_storage.scratch[i0].scratch.value <= field_combo.scratch[i0].scratch.next; + end + end + end + end + + assign hwif_out.cl_clint_set.req = decoded_req_is_wr ? decoded_reg_strb.cl_clint_set : '0; + assign hwif_out.cl_clint_set.req_is_wr = decoded_req_is_wr; + assign hwif_out.cl_clint_set.wr_data = decoded_wr_data; + assign hwif_out.cl_clint_set.wr_biten = decoded_wr_biten; + + assign hwif_out.cl_clint_clear.req = decoded_req_is_wr ? decoded_reg_strb.cl_clint_clear : '0; + assign hwif_out.cl_clint_clear.req_is_wr = decoded_req_is_wr; + assign hwif_out.cl_clint_clear.wr_data = decoded_wr_data; + assign hwif_out.cl_clint_clear.wr_biten = decoded_wr_biten; + // Field: snitch_cluster_peripheral_reg.icache_prefetch_enable.icache_prefetch_enable + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.icache_prefetch_enable.icache_prefetch_enable.value; + load_next_c = '0; + if(decoded_reg_strb.icache_prefetch_enable && decoded_req_is_wr) begin // SW write + next_c = (field_storage.icache_prefetch_enable.icache_prefetch_enable.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.icache_prefetch_enable.icache_prefetch_enable.next = next_c; + field_combo.icache_prefetch_enable.icache_prefetch_enable.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.icache_prefetch_enable.icache_prefetch_enable.value <= 1'h1; + end else begin + if(field_combo.icache_prefetch_enable.icache_prefetch_enable.load_next) begin + field_storage.icache_prefetch_enable.icache_prefetch_enable.value <= field_combo.icache_prefetch_enable.icache_prefetch_enable.next; + end + end + end + assign hwif_out.icache_prefetch_enable.icache_prefetch_enable.value = field_storage.icache_prefetch_enable.icache_prefetch_enable.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + always_comb begin + automatic logic wr_ack; + wr_ack = '0; + for(int i0=0; i0<16; i0++) begin + wr_ack |= hwif_in.perf_regs.perf_cnt_sel[i0].wr_ack; + end + for(int i0=0; i0<16; i0++) begin + wr_ack |= hwif_in.perf_regs.perf_cnt[i0].wr_ack; + end + wr_ack |= hwif_in.cl_clint_set.wr_ack; + wr_ack |= hwif_in.cl_clint_clear.wr_ack; + external_wr_ack = wr_ack; + end + assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_strb_is_external); + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + + //-------------------------------------------------------------------------- + // Readback + //-------------------------------------------------------------------------- + logic readback_external_rd_ack_c; + always_comb begin + automatic logic rd_ack; + rd_ack = '0; + for(int i0=0; i0<16; i0++) begin + rd_ack |= hwif_in.perf_regs.perf_cnt_sel[i0].rd_ack; + end + for(int i0=0; i0<16; i0++) begin + rd_ack |= hwif_in.perf_regs.perf_cnt[i0].rd_ack; + end + readback_external_rd_ack_c = rd_ack; + end + + logic readback_external_rd_ack; + + assign readback_external_rd_ack = readback_external_rd_ack_c; + + logic readback_err; + logic readback_done; + logic [63:0] readback_data; + + // Assign readback values to a flattened array + logic [63:0] readback_array[53]; + for(genvar i0=0; i0<16; i0++) begin + assign readback_array[i0 * 1 + 0][0:0] = (decoded_reg_strb.perf_regs.perf_cnt_en[i0] && !decoded_req_is_wr) ? field_storage.perf_regs.perf_cnt_en[i0].enable.value : '0; + assign readback_array[i0 * 1 + 0][63:1] = '0; + end + for(genvar i0=0; i0<16; i0++) begin + assign readback_array[i0 * 1 + 16] = hwif_in.perf_regs.perf_cnt_sel[i0].rd_ack ? hwif_in.perf_regs.perf_cnt_sel[i0].rd_data : '0; + end + for(genvar i0=0; i0<16; i0++) begin + assign readback_array[i0 * 1 + 32] = hwif_in.perf_regs.perf_cnt[i0].rd_ack ? hwif_in.perf_regs.perf_cnt[i0].rd_data : '0; + end + for(genvar i0=0; i0<4; i0++) begin + assign readback_array[i0 * 1 + 48][31:0] = (decoded_reg_strb.scratch[i0] && !decoded_req_is_wr) ? field_storage.scratch[i0].scratch.value : '0; + assign readback_array[i0 * 1 + 48][63:32] = '0; + end + assign readback_array[52][4:0] = (decoded_reg_strb.unused && !decoded_req_is_wr) ? 5'h0 : '0; + assign readback_array[52][63:5] = '0; + + // Reduce the array + always_comb begin + automatic logic [63:0] readback_data_var; + readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external; + readback_err = '0; + readback_data_var = '0; + for(int i=0; i<53; i++) readback_data_var |= readback_array[i]; + readback_data = readback_data_var; + end + + assign external_rd_ack = readback_external_rd_ack; + assign cpuif_rd_ack = readback_done | readback_external_rd_ack; + assign cpuif_rd_data = readback_data; + assign cpuif_rd_err = readback_err; +endmodule diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv index 50b789c341..dc67629fcb 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv @@ -1,295 +1,166 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock package snitch_cluster_peripheral_reg_pkg; - // Param list - parameter int NumPerfCounters = 16; - parameter int NumCtrlScratch = 4; - - // Address widths within the block - parameter int BlockAw = 9; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t; - - typedef struct packed { - struct packed { - logic [15:0] q; - logic qe; - } hart; - struct packed { - logic [15:0] q; - logic qe; - } metric; - } snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t; - - typedef struct packed { - logic [47:0] q; - logic qe; - } snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t; - - typedef struct packed { - logic q; - } snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t; - - typedef struct packed { - struct packed { - logic [15:0] d; - } hart; - struct packed { - logic [15:0] d; - } metric; - } snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t; - - typedef struct packed { - logic [47:0] d; - } snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t; - - // Register -> HW type - typedef struct packed { - snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t [15:0] perf_cnt_en; // [1410:1395] - snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1394:851] - snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t [15:0] perf_cnt; // [850:67] - snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [66:34] - snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [33:1] - snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [0:0] - } snitch_cluster_peripheral_reg2hw_t; - - // HW -> register type - typedef struct packed { - snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1279:768] - snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t [15:0] perf_cnt; // [767:0] - } snitch_cluster_peripheral_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET = 9'h 0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET = 9'h 8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET = 9'h 10; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET = 9'h 18; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET = 9'h 20; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET = 9'h 28; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET = 9'h 30; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET = 9'h 38; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET = 9'h 40; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET = 9'h 48; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET = 9'h 50; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET = 9'h 58; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET = 9'h 60; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET = 9'h 68; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET = 9'h 70; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET = 9'h 78; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET = 9'h 80; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET = 9'h 88; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET = 9'h 90; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET = 9'h 98; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET = 9'h a0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET = 9'h a8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET = 9'h b0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET = 9'h b8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET = 9'h c0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET = 9'h c8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET = 9'h d0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET = 9'h d8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET = 9'h e0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET = 9'h e8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET = 9'h f0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET = 9'h f8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET = 9'h 100; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET = 9'h 108; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET = 9'h 110; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET = 9'h 118; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET = 9'h 120; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET = 9'h 128; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET = 9'h 130; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET = 9'h 138; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET = 9'h 140; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET = 9'h 148; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET = 9'h 150; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET = 9'h 158; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET = 9'h 160; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET = 9'h 168; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET = 9'h 170; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h 178; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0_OFFSET = 9'h 180; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET = 9'h 188; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2_OFFSET = 9'h 190; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3_OFFSET = 9'h 198; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 1a0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 1a8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 1b0; - - // Reset values for hwext registers and their fields - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_RESVAL = 32'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_RESVAL = 48'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_RESVAL = 32'h 0; - - // Register index - typedef enum int { - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15, - SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0, - SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1, - SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2, - SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3, - SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET, - SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR, - SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE - } snitch_cluster_peripheral_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [55] = '{ - 4'b 0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0 - 4'b 0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1 - 4'b 0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2 - 4'b 0001, // index[ 3] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3 - 4'b 0001, // index[ 4] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4 - 4'b 0001, // index[ 5] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5 - 4'b 0001, // index[ 6] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6 - 4'b 0001, // index[ 7] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7 - 4'b 0001, // index[ 8] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8 - 4'b 0001, // index[ 9] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9 - 4'b 0001, // index[10] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10 - 4'b 0001, // index[11] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11 - 4'b 0001, // index[12] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12 - 4'b 0001, // index[13] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13 - 4'b 0001, // index[14] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14 - 4'b 0001, // index[15] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15 - 4'b 1111, // index[16] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0 - 4'b 1111, // index[17] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1 - 4'b 1111, // index[18] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2 - 4'b 1111, // index[19] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3 - 4'b 1111, // index[20] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4 - 4'b 1111, // index[21] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5 - 4'b 1111, // index[22] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6 - 4'b 1111, // index[23] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7 - 4'b 1111, // index[24] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8 - 4'b 1111, // index[25] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9 - 4'b 1111, // index[26] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10 - 4'b 1111, // index[27] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11 - 4'b 1111, // index[28] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12 - 4'b 1111, // index[29] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13 - 4'b 1111, // index[30] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14 - 4'b 1111, // index[31] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15 - 4'b 1111, // index[32] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0 - 4'b 1111, // index[33] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1 - 4'b 1111, // index[34] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2 - 4'b 1111, // index[35] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3 - 4'b 1111, // index[36] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4 - 4'b 1111, // index[37] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5 - 4'b 1111, // index[38] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6 - 4'b 1111, // index[39] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7 - 4'b 1111, // index[40] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8 - 4'b 1111, // index[41] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9 - 4'b 1111, // index[42] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10 - 4'b 1111, // index[43] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11 - 4'b 1111, // index[44] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12 - 4'b 1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13 - 4'b 1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14 - 4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15 - 4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0 - 4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1 - 4'b 1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2 - 4'b 1111, // index[51] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3 - 4'b 1111, // index[52] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET - 4'b 1111, // index[53] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR - 4'b 0001 // index[54] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE - }; - + localparam SNITCH_CLUSTER_PERIPHERAL_REG_DATA_WIDTH = 64; + localparam SNITCH_CLUSTER_PERIPHERAL_REG_MIN_ADDR_WIDTH = 9; + localparam SNITCH_CLUSTER_PERIPHERAL_REG_SIZE = 'h1c0; + + localparam NumPerfCounters = 'h10; + localparam NumCtrlScratch = 'h4; + + typedef struct packed { + logic [31:0] _reserved_63_32; + logic [15:0] metric; + logic [15:0] hart; + } snitch_cluster_peripheral_reg__perf_cnt_sel__external__fields__in_t; + + typedef struct { + logic rd_ack; + snitch_cluster_peripheral_reg__perf_cnt_sel__external__fields__in_t rd_data; + logic wr_ack; + } snitch_cluster_peripheral_reg__perf_cnt_sel__external__in_t; + + typedef struct packed { + logic [15:0] _reserved_63_48; + logic [47:0] perf_counter; + } snitch_cluster_peripheral_reg__perf_cnt__external__fields__in_t; + + typedef struct { + logic rd_ack; + snitch_cluster_peripheral_reg__perf_cnt__external__fields__in_t rd_data; + logic wr_ack; + } snitch_cluster_peripheral_reg__perf_cnt__external__in_t; + + typedef struct { + snitch_cluster_peripheral_reg__perf_cnt_sel__external__in_t perf_cnt_sel[16]; + snitch_cluster_peripheral_reg__perf_cnt__external__in_t perf_cnt[16]; + } snitch_cluster_peripheral_reg__perf_regs__in_t; + + typedef struct { + logic wr_ack; + } snitch_cluster_peripheral_reg__cl_clint_set__external__in_t; + + typedef struct { + logic wr_ack; + } snitch_cluster_peripheral_reg__cl_clint_clear__external__in_t; + + typedef struct { + snitch_cluster_peripheral_reg__perf_regs__in_t perf_regs; + snitch_cluster_peripheral_reg__cl_clint_set__external__in_t cl_clint_set; + snitch_cluster_peripheral_reg__cl_clint_clear__external__in_t cl_clint_clear; + } snitch_cluster_peripheral_reg__in_t; + + typedef struct { + logic value; + } snitch_cluster_peripheral_reg__perf_cnt_en__enable__out_t; + + typedef struct { + snitch_cluster_peripheral_reg__perf_cnt_en__enable__out_t enable; + } snitch_cluster_peripheral_reg__perf_cnt_en__out_t; + + typedef struct packed { + logic [31:0] _reserved_63_32; + logic [15:0] metric; + logic [15:0] hart; + } snitch_cluster_peripheral_reg__perf_cnt_sel__external__fields__out_t; + + typedef struct { + logic req; + logic req_is_wr; + snitch_cluster_peripheral_reg__perf_cnt_sel__external__fields__out_t wr_data; + snitch_cluster_peripheral_reg__perf_cnt_sel__external__fields__out_t wr_biten; + } snitch_cluster_peripheral_reg__perf_cnt_sel__external__out_t; + + typedef struct packed { + logic [15:0] _reserved_63_48; + logic [47:0] perf_counter; + } snitch_cluster_peripheral_reg__perf_cnt__external__fields__out_t; + + typedef struct { + logic req; + logic req_is_wr; + snitch_cluster_peripheral_reg__perf_cnt__external__fields__out_t wr_data; + snitch_cluster_peripheral_reg__perf_cnt__external__fields__out_t wr_biten; + } snitch_cluster_peripheral_reg__perf_cnt__external__out_t; + + typedef struct { + snitch_cluster_peripheral_reg__perf_cnt_en__out_t perf_cnt_en[16]; + snitch_cluster_peripheral_reg__perf_cnt_sel__external__out_t perf_cnt_sel[16]; + snitch_cluster_peripheral_reg__perf_cnt__external__out_t perf_cnt[16]; + } snitch_cluster_peripheral_reg__perf_regs__out_t; + + typedef struct packed { + logic [31:0] _reserved_63_32; + logic [31:0] cl_clint_set; + } snitch_cluster_peripheral_reg__cl_clint_set__external__fields__out_t; + + typedef struct { + logic req; + logic req_is_wr; + snitch_cluster_peripheral_reg__cl_clint_set__external__fields__out_t wr_data; + snitch_cluster_peripheral_reg__cl_clint_set__external__fields__out_t wr_biten; + } snitch_cluster_peripheral_reg__cl_clint_set__external__out_t; + + typedef struct packed { + logic [31:0] _reserved_63_32; + logic [31:0] cl_clint_clear; + } snitch_cluster_peripheral_reg__cl_clint_clear__external__fields__out_t; + + typedef struct { + logic req; + logic req_is_wr; + snitch_cluster_peripheral_reg__cl_clint_clear__external__fields__out_t wr_data; + snitch_cluster_peripheral_reg__cl_clint_clear__external__fields__out_t wr_biten; + } snitch_cluster_peripheral_reg__cl_clint_clear__external__out_t; + + typedef struct { + logic value; + } snitch_cluster_peripheral_reg__icache_prefetch_enable__icache_prefetch_enable__out_t; + + typedef struct { + snitch_cluster_peripheral_reg__icache_prefetch_enable__icache_prefetch_enable__out_t icache_prefetch_enable; + } snitch_cluster_peripheral_reg__icache_prefetch_enable__out_t; + + typedef struct { + snitch_cluster_peripheral_reg__perf_regs__out_t perf_regs; + snitch_cluster_peripheral_reg__cl_clint_set__external__out_t cl_clint_set; + snitch_cluster_peripheral_reg__cl_clint_clear__external__out_t cl_clint_clear; + snitch_cluster_peripheral_reg__icache_prefetch_enable__out_t icache_prefetch_enable; + } snitch_cluster_peripheral_reg__out_t; + + typedef enum logic [4:0] { + snitch_cluster_peripheral_reg__perf_metric__cycle = 'h0, + snitch_cluster_peripheral_reg__perf_metric__tcdm_accessed = 'h1, + snitch_cluster_peripheral_reg__perf_metric__tcdm_congested = 'h2, + snitch_cluster_peripheral_reg__perf_metric__issue_fpu = 'h3, + snitch_cluster_peripheral_reg__perf_metric__issue_fpu_seq = 'h4, + snitch_cluster_peripheral_reg__perf_metric__issue_core_to_fpu = 'h5, + snitch_cluster_peripheral_reg__perf_metric__retired_instr = 'h6, + snitch_cluster_peripheral_reg__perf_metric__retired_load = 'h7, + snitch_cluster_peripheral_reg__perf_metric__retired_i = 'h8, + snitch_cluster_peripheral_reg__perf_metric__retired_acc = 'h9, + snitch_cluster_peripheral_reg__perf_metric__dma_aw_stall = 'ha, + snitch_cluster_peripheral_reg__perf_metric__dma_ar_stall = 'hb, + snitch_cluster_peripheral_reg__perf_metric__dma_r_stall = 'hc, + snitch_cluster_peripheral_reg__perf_metric__dma_w_stall = 'hd, + snitch_cluster_peripheral_reg__perf_metric__dma_buf_w_stall = 'he, + snitch_cluster_peripheral_reg__perf_metric__dma_buf_r_stall = 'hf, + snitch_cluster_peripheral_reg__perf_metric__dma_aw_done = 'h10, + snitch_cluster_peripheral_reg__perf_metric__dma_aw_bw = 'h11, + snitch_cluster_peripheral_reg__perf_metric__dma_ar_done = 'h12, + snitch_cluster_peripheral_reg__perf_metric__dma_ar_bw = 'h13, + snitch_cluster_peripheral_reg__perf_metric__dma_r_done = 'h14, + snitch_cluster_peripheral_reg__perf_metric__dma_r_bw = 'h15, + snitch_cluster_peripheral_reg__perf_metric__dma_w_done = 'h16, + snitch_cluster_peripheral_reg__perf_metric__dma_w_bw = 'h17, + snitch_cluster_peripheral_reg__perf_metric__dma_b_done = 'h18, + snitch_cluster_peripheral_reg__perf_metric__dma_busy = 'h19, + snitch_cluster_peripheral_reg__perf_metric__icache_miss = 'h1a, + snitch_cluster_peripheral_reg__perf_metric__icache_hit = 'h1b, + snitch_cluster_peripheral_reg__perf_metric__icache_prefetch = 'h1c, + snitch_cluster_peripheral_reg__perf_metric__icache_double_hit = 'h1d, + snitch_cluster_peripheral_reg__perf_metric__icache_stall = 'h1e + } snitch_cluster_peripheral_reg__perf_metric_e; endpackage - diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv deleted file mode 100644 index 62781fda62..0000000000 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv +++ /dev/null @@ -1,2416 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module snitch_cluster_peripheral_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 9 -) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_reg2hw_t reg2hw, // Write - input snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import snitch_cluster_peripheral_reg_pkg::* ; - - localparam int DW = 64; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [BlockAw-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic perf_cnt_en_0_qs; - logic perf_cnt_en_0_wd; - logic perf_cnt_en_0_we; - logic perf_cnt_en_1_qs; - logic perf_cnt_en_1_wd; - logic perf_cnt_en_1_we; - logic perf_cnt_en_2_qs; - logic perf_cnt_en_2_wd; - logic perf_cnt_en_2_we; - logic perf_cnt_en_3_qs; - logic perf_cnt_en_3_wd; - logic perf_cnt_en_3_we; - logic perf_cnt_en_4_qs; - logic perf_cnt_en_4_wd; - logic perf_cnt_en_4_we; - logic perf_cnt_en_5_qs; - logic perf_cnt_en_5_wd; - logic perf_cnt_en_5_we; - logic perf_cnt_en_6_qs; - logic perf_cnt_en_6_wd; - logic perf_cnt_en_6_we; - logic perf_cnt_en_7_qs; - logic perf_cnt_en_7_wd; - logic perf_cnt_en_7_we; - logic perf_cnt_en_8_qs; - logic perf_cnt_en_8_wd; - logic perf_cnt_en_8_we; - logic perf_cnt_en_9_qs; - logic perf_cnt_en_9_wd; - logic perf_cnt_en_9_we; - logic perf_cnt_en_10_qs; - logic perf_cnt_en_10_wd; - logic perf_cnt_en_10_we; - logic perf_cnt_en_11_qs; - logic perf_cnt_en_11_wd; - logic perf_cnt_en_11_we; - logic perf_cnt_en_12_qs; - logic perf_cnt_en_12_wd; - logic perf_cnt_en_12_we; - logic perf_cnt_en_13_qs; - logic perf_cnt_en_13_wd; - logic perf_cnt_en_13_we; - logic perf_cnt_en_14_qs; - logic perf_cnt_en_14_wd; - logic perf_cnt_en_14_we; - logic perf_cnt_en_15_qs; - logic perf_cnt_en_15_wd; - logic perf_cnt_en_15_we; - logic [15:0] perf_cnt_sel_0_hart_0_qs; - logic [15:0] perf_cnt_sel_0_hart_0_wd; - logic perf_cnt_sel_0_hart_0_we; - logic perf_cnt_sel_0_hart_0_re; - logic [15:0] perf_cnt_sel_0_metric_0_qs; - logic [15:0] perf_cnt_sel_0_metric_0_wd; - logic perf_cnt_sel_0_metric_0_we; - logic perf_cnt_sel_0_metric_0_re; - logic [15:0] perf_cnt_sel_1_hart_1_qs; - logic [15:0] perf_cnt_sel_1_hart_1_wd; - logic perf_cnt_sel_1_hart_1_we; - logic perf_cnt_sel_1_hart_1_re; - logic [15:0] perf_cnt_sel_1_metric_1_qs; - logic [15:0] perf_cnt_sel_1_metric_1_wd; - logic perf_cnt_sel_1_metric_1_we; - logic perf_cnt_sel_1_metric_1_re; - logic [15:0] perf_cnt_sel_2_hart_2_qs; - logic [15:0] perf_cnt_sel_2_hart_2_wd; - logic perf_cnt_sel_2_hart_2_we; - logic perf_cnt_sel_2_hart_2_re; - logic [15:0] perf_cnt_sel_2_metric_2_qs; - logic [15:0] perf_cnt_sel_2_metric_2_wd; - logic perf_cnt_sel_2_metric_2_we; - logic perf_cnt_sel_2_metric_2_re; - logic [15:0] perf_cnt_sel_3_hart_3_qs; - logic [15:0] perf_cnt_sel_3_hart_3_wd; - logic perf_cnt_sel_3_hart_3_we; - logic perf_cnt_sel_3_hart_3_re; - logic [15:0] perf_cnt_sel_3_metric_3_qs; - logic [15:0] perf_cnt_sel_3_metric_3_wd; - logic perf_cnt_sel_3_metric_3_we; - logic perf_cnt_sel_3_metric_3_re; - logic [15:0] perf_cnt_sel_4_hart_4_qs; - logic [15:0] perf_cnt_sel_4_hart_4_wd; - logic perf_cnt_sel_4_hart_4_we; - logic perf_cnt_sel_4_hart_4_re; - logic [15:0] perf_cnt_sel_4_metric_4_qs; - logic [15:0] perf_cnt_sel_4_metric_4_wd; - logic perf_cnt_sel_4_metric_4_we; - logic perf_cnt_sel_4_metric_4_re; - logic [15:0] perf_cnt_sel_5_hart_5_qs; - logic [15:0] perf_cnt_sel_5_hart_5_wd; - logic perf_cnt_sel_5_hart_5_we; - logic perf_cnt_sel_5_hart_5_re; - logic [15:0] perf_cnt_sel_5_metric_5_qs; - logic [15:0] perf_cnt_sel_5_metric_5_wd; - logic perf_cnt_sel_5_metric_5_we; - logic perf_cnt_sel_5_metric_5_re; - logic [15:0] perf_cnt_sel_6_hart_6_qs; - logic [15:0] perf_cnt_sel_6_hart_6_wd; - logic perf_cnt_sel_6_hart_6_we; - logic perf_cnt_sel_6_hart_6_re; - logic [15:0] perf_cnt_sel_6_metric_6_qs; - logic [15:0] perf_cnt_sel_6_metric_6_wd; - logic perf_cnt_sel_6_metric_6_we; - logic perf_cnt_sel_6_metric_6_re; - logic [15:0] perf_cnt_sel_7_hart_7_qs; - logic [15:0] perf_cnt_sel_7_hart_7_wd; - logic perf_cnt_sel_7_hart_7_we; - logic perf_cnt_sel_7_hart_7_re; - logic [15:0] perf_cnt_sel_7_metric_7_qs; - logic [15:0] perf_cnt_sel_7_metric_7_wd; - logic perf_cnt_sel_7_metric_7_we; - logic perf_cnt_sel_7_metric_7_re; - logic [15:0] perf_cnt_sel_8_hart_8_qs; - logic [15:0] perf_cnt_sel_8_hart_8_wd; - logic perf_cnt_sel_8_hart_8_we; - logic perf_cnt_sel_8_hart_8_re; - logic [15:0] perf_cnt_sel_8_metric_8_qs; - logic [15:0] perf_cnt_sel_8_metric_8_wd; - logic perf_cnt_sel_8_metric_8_we; - logic perf_cnt_sel_8_metric_8_re; - logic [15:0] perf_cnt_sel_9_hart_9_qs; - logic [15:0] perf_cnt_sel_9_hart_9_wd; - logic perf_cnt_sel_9_hart_9_we; - logic perf_cnt_sel_9_hart_9_re; - logic [15:0] perf_cnt_sel_9_metric_9_qs; - logic [15:0] perf_cnt_sel_9_metric_9_wd; - logic perf_cnt_sel_9_metric_9_we; - logic perf_cnt_sel_9_metric_9_re; - logic [15:0] perf_cnt_sel_10_hart_10_qs; - logic [15:0] perf_cnt_sel_10_hart_10_wd; - logic perf_cnt_sel_10_hart_10_we; - logic perf_cnt_sel_10_hart_10_re; - logic [15:0] perf_cnt_sel_10_metric_10_qs; - logic [15:0] perf_cnt_sel_10_metric_10_wd; - logic perf_cnt_sel_10_metric_10_we; - logic perf_cnt_sel_10_metric_10_re; - logic [15:0] perf_cnt_sel_11_hart_11_qs; - logic [15:0] perf_cnt_sel_11_hart_11_wd; - logic perf_cnt_sel_11_hart_11_we; - logic perf_cnt_sel_11_hart_11_re; - logic [15:0] perf_cnt_sel_11_metric_11_qs; - logic [15:0] perf_cnt_sel_11_metric_11_wd; - logic perf_cnt_sel_11_metric_11_we; - logic perf_cnt_sel_11_metric_11_re; - logic [15:0] perf_cnt_sel_12_hart_12_qs; - logic [15:0] perf_cnt_sel_12_hart_12_wd; - logic perf_cnt_sel_12_hart_12_we; - logic perf_cnt_sel_12_hart_12_re; - logic [15:0] perf_cnt_sel_12_metric_12_qs; - logic [15:0] perf_cnt_sel_12_metric_12_wd; - logic perf_cnt_sel_12_metric_12_we; - logic perf_cnt_sel_12_metric_12_re; - logic [15:0] perf_cnt_sel_13_hart_13_qs; - logic [15:0] perf_cnt_sel_13_hart_13_wd; - logic perf_cnt_sel_13_hart_13_we; - logic perf_cnt_sel_13_hart_13_re; - logic [15:0] perf_cnt_sel_13_metric_13_qs; - logic [15:0] perf_cnt_sel_13_metric_13_wd; - logic perf_cnt_sel_13_metric_13_we; - logic perf_cnt_sel_13_metric_13_re; - logic [15:0] perf_cnt_sel_14_hart_14_qs; - logic [15:0] perf_cnt_sel_14_hart_14_wd; - logic perf_cnt_sel_14_hart_14_we; - logic perf_cnt_sel_14_hart_14_re; - logic [15:0] perf_cnt_sel_14_metric_14_qs; - logic [15:0] perf_cnt_sel_14_metric_14_wd; - logic perf_cnt_sel_14_metric_14_we; - logic perf_cnt_sel_14_metric_14_re; - logic [15:0] perf_cnt_sel_15_hart_15_qs; - logic [15:0] perf_cnt_sel_15_hart_15_wd; - logic perf_cnt_sel_15_hart_15_we; - logic perf_cnt_sel_15_hart_15_re; - logic [15:0] perf_cnt_sel_15_metric_15_qs; - logic [15:0] perf_cnt_sel_15_metric_15_wd; - logic perf_cnt_sel_15_metric_15_we; - logic perf_cnt_sel_15_metric_15_re; - logic [47:0] perf_cnt_0_qs; - logic [47:0] perf_cnt_0_wd; - logic perf_cnt_0_we; - logic perf_cnt_0_re; - logic [47:0] perf_cnt_1_qs; - logic [47:0] perf_cnt_1_wd; - logic perf_cnt_1_we; - logic perf_cnt_1_re; - logic [47:0] perf_cnt_2_qs; - logic [47:0] perf_cnt_2_wd; - logic perf_cnt_2_we; - logic perf_cnt_2_re; - logic [47:0] perf_cnt_3_qs; - logic [47:0] perf_cnt_3_wd; - logic perf_cnt_3_we; - logic perf_cnt_3_re; - logic [47:0] perf_cnt_4_qs; - logic [47:0] perf_cnt_4_wd; - logic perf_cnt_4_we; - logic perf_cnt_4_re; - logic [47:0] perf_cnt_5_qs; - logic [47:0] perf_cnt_5_wd; - logic perf_cnt_5_we; - logic perf_cnt_5_re; - logic [47:0] perf_cnt_6_qs; - logic [47:0] perf_cnt_6_wd; - logic perf_cnt_6_we; - logic perf_cnt_6_re; - logic [47:0] perf_cnt_7_qs; - logic [47:0] perf_cnt_7_wd; - logic perf_cnt_7_we; - logic perf_cnt_7_re; - logic [47:0] perf_cnt_8_qs; - logic [47:0] perf_cnt_8_wd; - logic perf_cnt_8_we; - logic perf_cnt_8_re; - logic [47:0] perf_cnt_9_qs; - logic [47:0] perf_cnt_9_wd; - logic perf_cnt_9_we; - logic perf_cnt_9_re; - logic [47:0] perf_cnt_10_qs; - logic [47:0] perf_cnt_10_wd; - logic perf_cnt_10_we; - logic perf_cnt_10_re; - logic [47:0] perf_cnt_11_qs; - logic [47:0] perf_cnt_11_wd; - logic perf_cnt_11_we; - logic perf_cnt_11_re; - logic [47:0] perf_cnt_12_qs; - logic [47:0] perf_cnt_12_wd; - logic perf_cnt_12_we; - logic perf_cnt_12_re; - logic [47:0] perf_cnt_13_qs; - logic [47:0] perf_cnt_13_wd; - logic perf_cnt_13_we; - logic perf_cnt_13_re; - logic [47:0] perf_cnt_14_qs; - logic [47:0] perf_cnt_14_wd; - logic perf_cnt_14_we; - logic perf_cnt_14_re; - logic [47:0] perf_cnt_15_qs; - logic [47:0] perf_cnt_15_wd; - logic perf_cnt_15_we; - logic perf_cnt_15_re; - logic [31:0] scratch_0_qs; - logic [31:0] scratch_0_wd; - logic scratch_0_we; - logic [31:0] scratch_1_qs; - logic [31:0] scratch_1_wd; - logic scratch_1_we; - logic [31:0] scratch_2_qs; - logic [31:0] scratch_2_wd; - logic scratch_2_we; - logic [31:0] scratch_3_qs; - logic [31:0] scratch_3_wd; - logic scratch_3_we; - logic [31:0] cl_clint_set_wd; - logic cl_clint_set_we; - logic [31:0] cl_clint_clear_wd; - logic cl_clint_clear_we; - logic icache_prefetch_enable_wd; - logic icache_prefetch_enable_we; - - // Register instances - - // Subregister 0 of Multireg perf_cnt_en - // R[perf_cnt_en_0]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_0_we), - .wd (perf_cnt_en_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[0].q ), - - // to register interface (read) - .qs (perf_cnt_en_0_qs) - ); - - // Subregister 1 of Multireg perf_cnt_en - // R[perf_cnt_en_1]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_1_we), - .wd (perf_cnt_en_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[1].q ), - - // to register interface (read) - .qs (perf_cnt_en_1_qs) - ); - - // Subregister 2 of Multireg perf_cnt_en - // R[perf_cnt_en_2]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_2_we), - .wd (perf_cnt_en_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[2].q ), - - // to register interface (read) - .qs (perf_cnt_en_2_qs) - ); - - // Subregister 3 of Multireg perf_cnt_en - // R[perf_cnt_en_3]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_3_we), - .wd (perf_cnt_en_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[3].q ), - - // to register interface (read) - .qs (perf_cnt_en_3_qs) - ); - - // Subregister 4 of Multireg perf_cnt_en - // R[perf_cnt_en_4]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_4_we), - .wd (perf_cnt_en_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[4].q ), - - // to register interface (read) - .qs (perf_cnt_en_4_qs) - ); - - // Subregister 5 of Multireg perf_cnt_en - // R[perf_cnt_en_5]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_5_we), - .wd (perf_cnt_en_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[5].q ), - - // to register interface (read) - .qs (perf_cnt_en_5_qs) - ); - - // Subregister 6 of Multireg perf_cnt_en - // R[perf_cnt_en_6]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_6_we), - .wd (perf_cnt_en_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[6].q ), - - // to register interface (read) - .qs (perf_cnt_en_6_qs) - ); - - // Subregister 7 of Multireg perf_cnt_en - // R[perf_cnt_en_7]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_7_we), - .wd (perf_cnt_en_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[7].q ), - - // to register interface (read) - .qs (perf_cnt_en_7_qs) - ); - - // Subregister 8 of Multireg perf_cnt_en - // R[perf_cnt_en_8]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_8_we), - .wd (perf_cnt_en_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[8].q ), - - // to register interface (read) - .qs (perf_cnt_en_8_qs) - ); - - // Subregister 9 of Multireg perf_cnt_en - // R[perf_cnt_en_9]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_9_we), - .wd (perf_cnt_en_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[9].q ), - - // to register interface (read) - .qs (perf_cnt_en_9_qs) - ); - - // Subregister 10 of Multireg perf_cnt_en - // R[perf_cnt_en_10]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_10_we), - .wd (perf_cnt_en_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[10].q ), - - // to register interface (read) - .qs (perf_cnt_en_10_qs) - ); - - // Subregister 11 of Multireg perf_cnt_en - // R[perf_cnt_en_11]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_11_we), - .wd (perf_cnt_en_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[11].q ), - - // to register interface (read) - .qs (perf_cnt_en_11_qs) - ); - - // Subregister 12 of Multireg perf_cnt_en - // R[perf_cnt_en_12]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_12_we), - .wd (perf_cnt_en_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[12].q ), - - // to register interface (read) - .qs (perf_cnt_en_12_qs) - ); - - // Subregister 13 of Multireg perf_cnt_en - // R[perf_cnt_en_13]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_13_we), - .wd (perf_cnt_en_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[13].q ), - - // to register interface (read) - .qs (perf_cnt_en_13_qs) - ); - - // Subregister 14 of Multireg perf_cnt_en - // R[perf_cnt_en_14]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_14_we), - .wd (perf_cnt_en_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[14].q ), - - // to register interface (read) - .qs (perf_cnt_en_14_qs) - ); - - // Subregister 15 of Multireg perf_cnt_en - // R[perf_cnt_en_15]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_perf_cnt_en_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_cnt_en_15_we), - .wd (perf_cnt_en_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_cnt_en[15].q ), - - // to register interface (read) - .qs (perf_cnt_en_15_qs) - ); - - - - // Subregister 0 of Multireg perf_cnt_sel - // R[perf_cnt_sel_0]: V(True) - - // F[hart_0]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_0_hart_0 ( - .re (perf_cnt_sel_0_hart_0_re), - .we (perf_cnt_sel_0_hart_0_we), - .wd (perf_cnt_sel_0_hart_0_wd), - .d (hw2reg.perf_cnt_sel[0].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[0].hart.qe), - .q (reg2hw.perf_cnt_sel[0].hart.q ), - .qs (perf_cnt_sel_0_hart_0_qs) - ); - - - // F[metric_0]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_0_metric_0 ( - .re (perf_cnt_sel_0_metric_0_re), - .we (perf_cnt_sel_0_metric_0_we), - .wd (perf_cnt_sel_0_metric_0_wd), - .d (hw2reg.perf_cnt_sel[0].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[0].metric.qe), - .q (reg2hw.perf_cnt_sel[0].metric.q ), - .qs (perf_cnt_sel_0_metric_0_qs) - ); - - - // Subregister 1 of Multireg perf_cnt_sel - // R[perf_cnt_sel_1]: V(True) - - // F[hart_1]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_1_hart_1 ( - .re (perf_cnt_sel_1_hart_1_re), - .we (perf_cnt_sel_1_hart_1_we), - .wd (perf_cnt_sel_1_hart_1_wd), - .d (hw2reg.perf_cnt_sel[1].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[1].hart.qe), - .q (reg2hw.perf_cnt_sel[1].hart.q ), - .qs (perf_cnt_sel_1_hart_1_qs) - ); - - - // F[metric_1]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_1_metric_1 ( - .re (perf_cnt_sel_1_metric_1_re), - .we (perf_cnt_sel_1_metric_1_we), - .wd (perf_cnt_sel_1_metric_1_wd), - .d (hw2reg.perf_cnt_sel[1].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[1].metric.qe), - .q (reg2hw.perf_cnt_sel[1].metric.q ), - .qs (perf_cnt_sel_1_metric_1_qs) - ); - - - // Subregister 2 of Multireg perf_cnt_sel - // R[perf_cnt_sel_2]: V(True) - - // F[hart_2]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_2_hart_2 ( - .re (perf_cnt_sel_2_hart_2_re), - .we (perf_cnt_sel_2_hart_2_we), - .wd (perf_cnt_sel_2_hart_2_wd), - .d (hw2reg.perf_cnt_sel[2].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[2].hart.qe), - .q (reg2hw.perf_cnt_sel[2].hart.q ), - .qs (perf_cnt_sel_2_hart_2_qs) - ); - - - // F[metric_2]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_2_metric_2 ( - .re (perf_cnt_sel_2_metric_2_re), - .we (perf_cnt_sel_2_metric_2_we), - .wd (perf_cnt_sel_2_metric_2_wd), - .d (hw2reg.perf_cnt_sel[2].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[2].metric.qe), - .q (reg2hw.perf_cnt_sel[2].metric.q ), - .qs (perf_cnt_sel_2_metric_2_qs) - ); - - - // Subregister 3 of Multireg perf_cnt_sel - // R[perf_cnt_sel_3]: V(True) - - // F[hart_3]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_3_hart_3 ( - .re (perf_cnt_sel_3_hart_3_re), - .we (perf_cnt_sel_3_hart_3_we), - .wd (perf_cnt_sel_3_hart_3_wd), - .d (hw2reg.perf_cnt_sel[3].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[3].hart.qe), - .q (reg2hw.perf_cnt_sel[3].hart.q ), - .qs (perf_cnt_sel_3_hart_3_qs) - ); - - - // F[metric_3]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_3_metric_3 ( - .re (perf_cnt_sel_3_metric_3_re), - .we (perf_cnt_sel_3_metric_3_we), - .wd (perf_cnt_sel_3_metric_3_wd), - .d (hw2reg.perf_cnt_sel[3].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[3].metric.qe), - .q (reg2hw.perf_cnt_sel[3].metric.q ), - .qs (perf_cnt_sel_3_metric_3_qs) - ); - - - // Subregister 4 of Multireg perf_cnt_sel - // R[perf_cnt_sel_4]: V(True) - - // F[hart_4]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_4_hart_4 ( - .re (perf_cnt_sel_4_hart_4_re), - .we (perf_cnt_sel_4_hart_4_we), - .wd (perf_cnt_sel_4_hart_4_wd), - .d (hw2reg.perf_cnt_sel[4].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[4].hart.qe), - .q (reg2hw.perf_cnt_sel[4].hart.q ), - .qs (perf_cnt_sel_4_hart_4_qs) - ); - - - // F[metric_4]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_4_metric_4 ( - .re (perf_cnt_sel_4_metric_4_re), - .we (perf_cnt_sel_4_metric_4_we), - .wd (perf_cnt_sel_4_metric_4_wd), - .d (hw2reg.perf_cnt_sel[4].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[4].metric.qe), - .q (reg2hw.perf_cnt_sel[4].metric.q ), - .qs (perf_cnt_sel_4_metric_4_qs) - ); - - - // Subregister 5 of Multireg perf_cnt_sel - // R[perf_cnt_sel_5]: V(True) - - // F[hart_5]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_5_hart_5 ( - .re (perf_cnt_sel_5_hart_5_re), - .we (perf_cnt_sel_5_hart_5_we), - .wd (perf_cnt_sel_5_hart_5_wd), - .d (hw2reg.perf_cnt_sel[5].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[5].hart.qe), - .q (reg2hw.perf_cnt_sel[5].hart.q ), - .qs (perf_cnt_sel_5_hart_5_qs) - ); - - - // F[metric_5]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_5_metric_5 ( - .re (perf_cnt_sel_5_metric_5_re), - .we (perf_cnt_sel_5_metric_5_we), - .wd (perf_cnt_sel_5_metric_5_wd), - .d (hw2reg.perf_cnt_sel[5].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[5].metric.qe), - .q (reg2hw.perf_cnt_sel[5].metric.q ), - .qs (perf_cnt_sel_5_metric_5_qs) - ); - - - // Subregister 6 of Multireg perf_cnt_sel - // R[perf_cnt_sel_6]: V(True) - - // F[hart_6]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_6_hart_6 ( - .re (perf_cnt_sel_6_hart_6_re), - .we (perf_cnt_sel_6_hart_6_we), - .wd (perf_cnt_sel_6_hart_6_wd), - .d (hw2reg.perf_cnt_sel[6].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[6].hart.qe), - .q (reg2hw.perf_cnt_sel[6].hart.q ), - .qs (perf_cnt_sel_6_hart_6_qs) - ); - - - // F[metric_6]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_6_metric_6 ( - .re (perf_cnt_sel_6_metric_6_re), - .we (perf_cnt_sel_6_metric_6_we), - .wd (perf_cnt_sel_6_metric_6_wd), - .d (hw2reg.perf_cnt_sel[6].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[6].metric.qe), - .q (reg2hw.perf_cnt_sel[6].metric.q ), - .qs (perf_cnt_sel_6_metric_6_qs) - ); - - - // Subregister 7 of Multireg perf_cnt_sel - // R[perf_cnt_sel_7]: V(True) - - // F[hart_7]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_7_hart_7 ( - .re (perf_cnt_sel_7_hart_7_re), - .we (perf_cnt_sel_7_hart_7_we), - .wd (perf_cnt_sel_7_hart_7_wd), - .d (hw2reg.perf_cnt_sel[7].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[7].hart.qe), - .q (reg2hw.perf_cnt_sel[7].hart.q ), - .qs (perf_cnt_sel_7_hart_7_qs) - ); - - - // F[metric_7]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_7_metric_7 ( - .re (perf_cnt_sel_7_metric_7_re), - .we (perf_cnt_sel_7_metric_7_we), - .wd (perf_cnt_sel_7_metric_7_wd), - .d (hw2reg.perf_cnt_sel[7].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[7].metric.qe), - .q (reg2hw.perf_cnt_sel[7].metric.q ), - .qs (perf_cnt_sel_7_metric_7_qs) - ); - - - // Subregister 8 of Multireg perf_cnt_sel - // R[perf_cnt_sel_8]: V(True) - - // F[hart_8]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_8_hart_8 ( - .re (perf_cnt_sel_8_hart_8_re), - .we (perf_cnt_sel_8_hart_8_we), - .wd (perf_cnt_sel_8_hart_8_wd), - .d (hw2reg.perf_cnt_sel[8].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[8].hart.qe), - .q (reg2hw.perf_cnt_sel[8].hart.q ), - .qs (perf_cnt_sel_8_hart_8_qs) - ); - - - // F[metric_8]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_8_metric_8 ( - .re (perf_cnt_sel_8_metric_8_re), - .we (perf_cnt_sel_8_metric_8_we), - .wd (perf_cnt_sel_8_metric_8_wd), - .d (hw2reg.perf_cnt_sel[8].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[8].metric.qe), - .q (reg2hw.perf_cnt_sel[8].metric.q ), - .qs (perf_cnt_sel_8_metric_8_qs) - ); - - - // Subregister 9 of Multireg perf_cnt_sel - // R[perf_cnt_sel_9]: V(True) - - // F[hart_9]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_9_hart_9 ( - .re (perf_cnt_sel_9_hart_9_re), - .we (perf_cnt_sel_9_hart_9_we), - .wd (perf_cnt_sel_9_hart_9_wd), - .d (hw2reg.perf_cnt_sel[9].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[9].hart.qe), - .q (reg2hw.perf_cnt_sel[9].hart.q ), - .qs (perf_cnt_sel_9_hart_9_qs) - ); - - - // F[metric_9]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_9_metric_9 ( - .re (perf_cnt_sel_9_metric_9_re), - .we (perf_cnt_sel_9_metric_9_we), - .wd (perf_cnt_sel_9_metric_9_wd), - .d (hw2reg.perf_cnt_sel[9].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[9].metric.qe), - .q (reg2hw.perf_cnt_sel[9].metric.q ), - .qs (perf_cnt_sel_9_metric_9_qs) - ); - - - // Subregister 10 of Multireg perf_cnt_sel - // R[perf_cnt_sel_10]: V(True) - - // F[hart_10]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_10_hart_10 ( - .re (perf_cnt_sel_10_hart_10_re), - .we (perf_cnt_sel_10_hart_10_we), - .wd (perf_cnt_sel_10_hart_10_wd), - .d (hw2reg.perf_cnt_sel[10].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[10].hart.qe), - .q (reg2hw.perf_cnt_sel[10].hart.q ), - .qs (perf_cnt_sel_10_hart_10_qs) - ); - - - // F[metric_10]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_10_metric_10 ( - .re (perf_cnt_sel_10_metric_10_re), - .we (perf_cnt_sel_10_metric_10_we), - .wd (perf_cnt_sel_10_metric_10_wd), - .d (hw2reg.perf_cnt_sel[10].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[10].metric.qe), - .q (reg2hw.perf_cnt_sel[10].metric.q ), - .qs (perf_cnt_sel_10_metric_10_qs) - ); - - - // Subregister 11 of Multireg perf_cnt_sel - // R[perf_cnt_sel_11]: V(True) - - // F[hart_11]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_11_hart_11 ( - .re (perf_cnt_sel_11_hart_11_re), - .we (perf_cnt_sel_11_hart_11_we), - .wd (perf_cnt_sel_11_hart_11_wd), - .d (hw2reg.perf_cnt_sel[11].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[11].hart.qe), - .q (reg2hw.perf_cnt_sel[11].hart.q ), - .qs (perf_cnt_sel_11_hart_11_qs) - ); - - - // F[metric_11]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_11_metric_11 ( - .re (perf_cnt_sel_11_metric_11_re), - .we (perf_cnt_sel_11_metric_11_we), - .wd (perf_cnt_sel_11_metric_11_wd), - .d (hw2reg.perf_cnt_sel[11].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[11].metric.qe), - .q (reg2hw.perf_cnt_sel[11].metric.q ), - .qs (perf_cnt_sel_11_metric_11_qs) - ); - - - // Subregister 12 of Multireg perf_cnt_sel - // R[perf_cnt_sel_12]: V(True) - - // F[hart_12]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_12_hart_12 ( - .re (perf_cnt_sel_12_hart_12_re), - .we (perf_cnt_sel_12_hart_12_we), - .wd (perf_cnt_sel_12_hart_12_wd), - .d (hw2reg.perf_cnt_sel[12].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[12].hart.qe), - .q (reg2hw.perf_cnt_sel[12].hart.q ), - .qs (perf_cnt_sel_12_hart_12_qs) - ); - - - // F[metric_12]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_12_metric_12 ( - .re (perf_cnt_sel_12_metric_12_re), - .we (perf_cnt_sel_12_metric_12_we), - .wd (perf_cnt_sel_12_metric_12_wd), - .d (hw2reg.perf_cnt_sel[12].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[12].metric.qe), - .q (reg2hw.perf_cnt_sel[12].metric.q ), - .qs (perf_cnt_sel_12_metric_12_qs) - ); - - - // Subregister 13 of Multireg perf_cnt_sel - // R[perf_cnt_sel_13]: V(True) - - // F[hart_13]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_13_hart_13 ( - .re (perf_cnt_sel_13_hart_13_re), - .we (perf_cnt_sel_13_hart_13_we), - .wd (perf_cnt_sel_13_hart_13_wd), - .d (hw2reg.perf_cnt_sel[13].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[13].hart.qe), - .q (reg2hw.perf_cnt_sel[13].hart.q ), - .qs (perf_cnt_sel_13_hart_13_qs) - ); - - - // F[metric_13]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_13_metric_13 ( - .re (perf_cnt_sel_13_metric_13_re), - .we (perf_cnt_sel_13_metric_13_we), - .wd (perf_cnt_sel_13_metric_13_wd), - .d (hw2reg.perf_cnt_sel[13].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[13].metric.qe), - .q (reg2hw.perf_cnt_sel[13].metric.q ), - .qs (perf_cnt_sel_13_metric_13_qs) - ); - - - // Subregister 14 of Multireg perf_cnt_sel - // R[perf_cnt_sel_14]: V(True) - - // F[hart_14]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_14_hart_14 ( - .re (perf_cnt_sel_14_hart_14_re), - .we (perf_cnt_sel_14_hart_14_we), - .wd (perf_cnt_sel_14_hart_14_wd), - .d (hw2reg.perf_cnt_sel[14].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[14].hart.qe), - .q (reg2hw.perf_cnt_sel[14].hart.q ), - .qs (perf_cnt_sel_14_hart_14_qs) - ); - - - // F[metric_14]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_14_metric_14 ( - .re (perf_cnt_sel_14_metric_14_re), - .we (perf_cnt_sel_14_metric_14_we), - .wd (perf_cnt_sel_14_metric_14_wd), - .d (hw2reg.perf_cnt_sel[14].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[14].metric.qe), - .q (reg2hw.perf_cnt_sel[14].metric.q ), - .qs (perf_cnt_sel_14_metric_14_qs) - ); - - - // Subregister 15 of Multireg perf_cnt_sel - // R[perf_cnt_sel_15]: V(True) - - // F[hart_15]: 15:0 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_15_hart_15 ( - .re (perf_cnt_sel_15_hart_15_re), - .we (perf_cnt_sel_15_hart_15_we), - .wd (perf_cnt_sel_15_hart_15_wd), - .d (hw2reg.perf_cnt_sel[15].hart.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[15].hart.qe), - .q (reg2hw.perf_cnt_sel[15].hart.q ), - .qs (perf_cnt_sel_15_hart_15_qs) - ); - - - // F[metric_15]: 31:16 - prim_subreg_ext #( - .DW (16) - ) u_perf_cnt_sel_15_metric_15 ( - .re (perf_cnt_sel_15_metric_15_re), - .we (perf_cnt_sel_15_metric_15_we), - .wd (perf_cnt_sel_15_metric_15_wd), - .d (hw2reg.perf_cnt_sel[15].metric.d), - .qre (), - .qe (reg2hw.perf_cnt_sel[15].metric.qe), - .q (reg2hw.perf_cnt_sel[15].metric.q ), - .qs (perf_cnt_sel_15_metric_15_qs) - ); - - - - - // Subregister 0 of Multireg perf_cnt - // R[perf_cnt_0]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_0 ( - .re (perf_cnt_0_re), - .we (perf_cnt_0_we), - .wd (perf_cnt_0_wd), - .d (hw2reg.perf_cnt[0].d), - .qre (), - .qe (reg2hw.perf_cnt[0].qe), - .q (reg2hw.perf_cnt[0].q ), - .qs (perf_cnt_0_qs) - ); - - // Subregister 1 of Multireg perf_cnt - // R[perf_cnt_1]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_1 ( - .re (perf_cnt_1_re), - .we (perf_cnt_1_we), - .wd (perf_cnt_1_wd), - .d (hw2reg.perf_cnt[1].d), - .qre (), - .qe (reg2hw.perf_cnt[1].qe), - .q (reg2hw.perf_cnt[1].q ), - .qs (perf_cnt_1_qs) - ); - - // Subregister 2 of Multireg perf_cnt - // R[perf_cnt_2]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_2 ( - .re (perf_cnt_2_re), - .we (perf_cnt_2_we), - .wd (perf_cnt_2_wd), - .d (hw2reg.perf_cnt[2].d), - .qre (), - .qe (reg2hw.perf_cnt[2].qe), - .q (reg2hw.perf_cnt[2].q ), - .qs (perf_cnt_2_qs) - ); - - // Subregister 3 of Multireg perf_cnt - // R[perf_cnt_3]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_3 ( - .re (perf_cnt_3_re), - .we (perf_cnt_3_we), - .wd (perf_cnt_3_wd), - .d (hw2reg.perf_cnt[3].d), - .qre (), - .qe (reg2hw.perf_cnt[3].qe), - .q (reg2hw.perf_cnt[3].q ), - .qs (perf_cnt_3_qs) - ); - - // Subregister 4 of Multireg perf_cnt - // R[perf_cnt_4]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_4 ( - .re (perf_cnt_4_re), - .we (perf_cnt_4_we), - .wd (perf_cnt_4_wd), - .d (hw2reg.perf_cnt[4].d), - .qre (), - .qe (reg2hw.perf_cnt[4].qe), - .q (reg2hw.perf_cnt[4].q ), - .qs (perf_cnt_4_qs) - ); - - // Subregister 5 of Multireg perf_cnt - // R[perf_cnt_5]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_5 ( - .re (perf_cnt_5_re), - .we (perf_cnt_5_we), - .wd (perf_cnt_5_wd), - .d (hw2reg.perf_cnt[5].d), - .qre (), - .qe (reg2hw.perf_cnt[5].qe), - .q (reg2hw.perf_cnt[5].q ), - .qs (perf_cnt_5_qs) - ); - - // Subregister 6 of Multireg perf_cnt - // R[perf_cnt_6]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_6 ( - .re (perf_cnt_6_re), - .we (perf_cnt_6_we), - .wd (perf_cnt_6_wd), - .d (hw2reg.perf_cnt[6].d), - .qre (), - .qe (reg2hw.perf_cnt[6].qe), - .q (reg2hw.perf_cnt[6].q ), - .qs (perf_cnt_6_qs) - ); - - // Subregister 7 of Multireg perf_cnt - // R[perf_cnt_7]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_7 ( - .re (perf_cnt_7_re), - .we (perf_cnt_7_we), - .wd (perf_cnt_7_wd), - .d (hw2reg.perf_cnt[7].d), - .qre (), - .qe (reg2hw.perf_cnt[7].qe), - .q (reg2hw.perf_cnt[7].q ), - .qs (perf_cnt_7_qs) - ); - - // Subregister 8 of Multireg perf_cnt - // R[perf_cnt_8]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_8 ( - .re (perf_cnt_8_re), - .we (perf_cnt_8_we), - .wd (perf_cnt_8_wd), - .d (hw2reg.perf_cnt[8].d), - .qre (), - .qe (reg2hw.perf_cnt[8].qe), - .q (reg2hw.perf_cnt[8].q ), - .qs (perf_cnt_8_qs) - ); - - // Subregister 9 of Multireg perf_cnt - // R[perf_cnt_9]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_9 ( - .re (perf_cnt_9_re), - .we (perf_cnt_9_we), - .wd (perf_cnt_9_wd), - .d (hw2reg.perf_cnt[9].d), - .qre (), - .qe (reg2hw.perf_cnt[9].qe), - .q (reg2hw.perf_cnt[9].q ), - .qs (perf_cnt_9_qs) - ); - - // Subregister 10 of Multireg perf_cnt - // R[perf_cnt_10]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_10 ( - .re (perf_cnt_10_re), - .we (perf_cnt_10_we), - .wd (perf_cnt_10_wd), - .d (hw2reg.perf_cnt[10].d), - .qre (), - .qe (reg2hw.perf_cnt[10].qe), - .q (reg2hw.perf_cnt[10].q ), - .qs (perf_cnt_10_qs) - ); - - // Subregister 11 of Multireg perf_cnt - // R[perf_cnt_11]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_11 ( - .re (perf_cnt_11_re), - .we (perf_cnt_11_we), - .wd (perf_cnt_11_wd), - .d (hw2reg.perf_cnt[11].d), - .qre (), - .qe (reg2hw.perf_cnt[11].qe), - .q (reg2hw.perf_cnt[11].q ), - .qs (perf_cnt_11_qs) - ); - - // Subregister 12 of Multireg perf_cnt - // R[perf_cnt_12]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_12 ( - .re (perf_cnt_12_re), - .we (perf_cnt_12_we), - .wd (perf_cnt_12_wd), - .d (hw2reg.perf_cnt[12].d), - .qre (), - .qe (reg2hw.perf_cnt[12].qe), - .q (reg2hw.perf_cnt[12].q ), - .qs (perf_cnt_12_qs) - ); - - // Subregister 13 of Multireg perf_cnt - // R[perf_cnt_13]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_13 ( - .re (perf_cnt_13_re), - .we (perf_cnt_13_we), - .wd (perf_cnt_13_wd), - .d (hw2reg.perf_cnt[13].d), - .qre (), - .qe (reg2hw.perf_cnt[13].qe), - .q (reg2hw.perf_cnt[13].q ), - .qs (perf_cnt_13_qs) - ); - - // Subregister 14 of Multireg perf_cnt - // R[perf_cnt_14]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_14 ( - .re (perf_cnt_14_re), - .we (perf_cnt_14_we), - .wd (perf_cnt_14_wd), - .d (hw2reg.perf_cnt[14].d), - .qre (), - .qe (reg2hw.perf_cnt[14].qe), - .q (reg2hw.perf_cnt[14].q ), - .qs (perf_cnt_14_qs) - ); - - // Subregister 15 of Multireg perf_cnt - // R[perf_cnt_15]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_cnt_15 ( - .re (perf_cnt_15_re), - .we (perf_cnt_15_we), - .wd (perf_cnt_15_wd), - .d (hw2reg.perf_cnt[15].d), - .qre (), - .qe (reg2hw.perf_cnt[15].qe), - .q (reg2hw.perf_cnt[15].q ), - .qs (perf_cnt_15_qs) - ); - - - - // Subregister 0 of Multireg scratch - // R[scratch_0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_scratch_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (scratch_0_we), - .wd (scratch_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (scratch_0_qs) - ); - - // Subregister 1 of Multireg scratch - // R[scratch_1]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_scratch_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (scratch_1_we), - .wd (scratch_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (scratch_1_qs) - ); - - // Subregister 2 of Multireg scratch - // R[scratch_2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_scratch_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (scratch_2_we), - .wd (scratch_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (scratch_2_qs) - ); - - // Subregister 3 of Multireg scratch - // R[scratch_3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_scratch_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (scratch_3_we), - .wd (scratch_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (scratch_3_qs) - ); - - - // R[cl_clint_set]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_set ( - .re (1'b0), - .we (cl_clint_set_we), - .wd (cl_clint_set_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_set.qe), - .q (reg2hw.cl_clint_set.q ), - .qs () - ); - - - // R[cl_clint_clear]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_clear ( - .re (1'b0), - .we (cl_clint_clear_we), - .wd (cl_clint_clear_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_clear.qe), - .q (reg2hw.cl_clint_clear.q ), - .qs () - ); - - - // R[icache_prefetch_enable]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("WO"), - .RESVAL (1'h1) - ) u_icache_prefetch_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (icache_prefetch_enable_we), - .wd (icache_prefetch_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.icache_prefetch_enable.q ), - - .qs () - ); - - - - - logic [54:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET); - addr_hit[ 1] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET); - addr_hit[ 2] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET); - addr_hit[ 3] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET); - addr_hit[ 4] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET); - addr_hit[ 5] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET); - addr_hit[ 6] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET); - addr_hit[ 7] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET); - addr_hit[ 8] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET); - addr_hit[ 9] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET); - addr_hit[10] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET); - addr_hit[11] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET); - addr_hit[12] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET); - addr_hit[13] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET); - addr_hit[14] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET); - addr_hit[15] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET); - addr_hit[16] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET); - addr_hit[17] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET); - addr_hit[18] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET); - addr_hit[19] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET); - addr_hit[20] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET); - addr_hit[21] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET); - addr_hit[22] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET); - addr_hit[23] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET); - addr_hit[24] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET); - addr_hit[25] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET); - addr_hit[26] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET); - addr_hit[27] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET); - addr_hit[28] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET); - addr_hit[29] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET); - addr_hit[30] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET); - addr_hit[31] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET); - addr_hit[32] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET); - addr_hit[33] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET); - addr_hit[34] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET); - addr_hit[35] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET); - addr_hit[36] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET); - addr_hit[37] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET); - addr_hit[38] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET); - addr_hit[39] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET); - addr_hit[40] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET); - addr_hit[41] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET); - addr_hit[42] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET); - addr_hit[43] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET); - addr_hit[44] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET); - addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET); - addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET); - addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET); - addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0_OFFSET); - addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET); - addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2_OFFSET); - addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3_OFFSET); - addr_hit[52] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); - addr_hit[53] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); - addr_hit[54] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[20] & ~reg_be))) | - (addr_hit[21] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[22] & ~reg_be))) | - (addr_hit[23] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[23] & ~reg_be))) | - (addr_hit[24] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[24] & ~reg_be))) | - (addr_hit[25] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[25] & ~reg_be))) | - (addr_hit[26] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[26] & ~reg_be))) | - (addr_hit[27] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[27] & ~reg_be))) | - (addr_hit[28] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[28] & ~reg_be))) | - (addr_hit[29] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[29] & ~reg_be))) | - (addr_hit[30] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[30] & ~reg_be))) | - (addr_hit[31] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[31] & ~reg_be))) | - (addr_hit[32] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[32] & ~reg_be))) | - (addr_hit[33] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[33] & ~reg_be))) | - (addr_hit[34] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[34] & ~reg_be))) | - (addr_hit[35] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[35] & ~reg_be))) | - (addr_hit[36] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[36] & ~reg_be))) | - (addr_hit[37] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[37] & ~reg_be))) | - (addr_hit[38] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[38] & ~reg_be))) | - (addr_hit[39] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[39] & ~reg_be))) | - (addr_hit[40] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[40] & ~reg_be))) | - (addr_hit[41] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[41] & ~reg_be))) | - (addr_hit[42] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[42] & ~reg_be))) | - (addr_hit[43] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[43] & ~reg_be))) | - (addr_hit[44] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[44] & ~reg_be))) | - (addr_hit[45] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[45] & ~reg_be))) | - (addr_hit[46] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[46] & ~reg_be))) | - (addr_hit[47] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[47] & ~reg_be))) | - (addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) | - (addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) | - (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))) | - (addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be))) | - (addr_hit[52] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[52] & ~reg_be))) | - (addr_hit[53] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[53] & ~reg_be))) | - (addr_hit[54] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[54] & ~reg_be))))); - end - - assign perf_cnt_en_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_cnt_en_0_wd = reg_wdata[0]; - - assign perf_cnt_en_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_cnt_en_1_wd = reg_wdata[0]; - - assign perf_cnt_en_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_cnt_en_2_wd = reg_wdata[0]; - - assign perf_cnt_en_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_cnt_en_3_wd = reg_wdata[0]; - - assign perf_cnt_en_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_cnt_en_4_wd = reg_wdata[0]; - - assign perf_cnt_en_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_cnt_en_5_wd = reg_wdata[0]; - - assign perf_cnt_en_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_cnt_en_6_wd = reg_wdata[0]; - - assign perf_cnt_en_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_cnt_en_7_wd = reg_wdata[0]; - - assign perf_cnt_en_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_cnt_en_8_wd = reg_wdata[0]; - - assign perf_cnt_en_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_cnt_en_9_wd = reg_wdata[0]; - - assign perf_cnt_en_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_cnt_en_10_wd = reg_wdata[0]; - - assign perf_cnt_en_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_cnt_en_11_wd = reg_wdata[0]; - - assign perf_cnt_en_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_cnt_en_12_wd = reg_wdata[0]; - - assign perf_cnt_en_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_cnt_en_13_wd = reg_wdata[0]; - - assign perf_cnt_en_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_cnt_en_14_wd = reg_wdata[0]; - - assign perf_cnt_en_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_cnt_en_15_wd = reg_wdata[0]; - - assign perf_cnt_sel_0_hart_0_we = addr_hit[16] & reg_we & !reg_error; - assign perf_cnt_sel_0_hart_0_wd = reg_wdata[15:0]; - assign perf_cnt_sel_0_hart_0_re = addr_hit[16] & reg_re & !reg_error; - - assign perf_cnt_sel_0_metric_0_we = addr_hit[16] & reg_we & !reg_error; - assign perf_cnt_sel_0_metric_0_wd = reg_wdata[31:16]; - assign perf_cnt_sel_0_metric_0_re = addr_hit[16] & reg_re & !reg_error; - - assign perf_cnt_sel_1_hart_1_we = addr_hit[17] & reg_we & !reg_error; - assign perf_cnt_sel_1_hart_1_wd = reg_wdata[15:0]; - assign perf_cnt_sel_1_hart_1_re = addr_hit[17] & reg_re & !reg_error; - - assign perf_cnt_sel_1_metric_1_we = addr_hit[17] & reg_we & !reg_error; - assign perf_cnt_sel_1_metric_1_wd = reg_wdata[31:16]; - assign perf_cnt_sel_1_metric_1_re = addr_hit[17] & reg_re & !reg_error; - - assign perf_cnt_sel_2_hart_2_we = addr_hit[18] & reg_we & !reg_error; - assign perf_cnt_sel_2_hart_2_wd = reg_wdata[15:0]; - assign perf_cnt_sel_2_hart_2_re = addr_hit[18] & reg_re & !reg_error; - - assign perf_cnt_sel_2_metric_2_we = addr_hit[18] & reg_we & !reg_error; - assign perf_cnt_sel_2_metric_2_wd = reg_wdata[31:16]; - assign perf_cnt_sel_2_metric_2_re = addr_hit[18] & reg_re & !reg_error; - - assign perf_cnt_sel_3_hart_3_we = addr_hit[19] & reg_we & !reg_error; - assign perf_cnt_sel_3_hart_3_wd = reg_wdata[15:0]; - assign perf_cnt_sel_3_hart_3_re = addr_hit[19] & reg_re & !reg_error; - - assign perf_cnt_sel_3_metric_3_we = addr_hit[19] & reg_we & !reg_error; - assign perf_cnt_sel_3_metric_3_wd = reg_wdata[31:16]; - assign perf_cnt_sel_3_metric_3_re = addr_hit[19] & reg_re & !reg_error; - - assign perf_cnt_sel_4_hart_4_we = addr_hit[20] & reg_we & !reg_error; - assign perf_cnt_sel_4_hart_4_wd = reg_wdata[15:0]; - assign perf_cnt_sel_4_hart_4_re = addr_hit[20] & reg_re & !reg_error; - - assign perf_cnt_sel_4_metric_4_we = addr_hit[20] & reg_we & !reg_error; - assign perf_cnt_sel_4_metric_4_wd = reg_wdata[31:16]; - assign perf_cnt_sel_4_metric_4_re = addr_hit[20] & reg_re & !reg_error; - - assign perf_cnt_sel_5_hart_5_we = addr_hit[21] & reg_we & !reg_error; - assign perf_cnt_sel_5_hart_5_wd = reg_wdata[15:0]; - assign perf_cnt_sel_5_hart_5_re = addr_hit[21] & reg_re & !reg_error; - - assign perf_cnt_sel_5_metric_5_we = addr_hit[21] & reg_we & !reg_error; - assign perf_cnt_sel_5_metric_5_wd = reg_wdata[31:16]; - assign perf_cnt_sel_5_metric_5_re = addr_hit[21] & reg_re & !reg_error; - - assign perf_cnt_sel_6_hart_6_we = addr_hit[22] & reg_we & !reg_error; - assign perf_cnt_sel_6_hart_6_wd = reg_wdata[15:0]; - assign perf_cnt_sel_6_hart_6_re = addr_hit[22] & reg_re & !reg_error; - - assign perf_cnt_sel_6_metric_6_we = addr_hit[22] & reg_we & !reg_error; - assign perf_cnt_sel_6_metric_6_wd = reg_wdata[31:16]; - assign perf_cnt_sel_6_metric_6_re = addr_hit[22] & reg_re & !reg_error; - - assign perf_cnt_sel_7_hart_7_we = addr_hit[23] & reg_we & !reg_error; - assign perf_cnt_sel_7_hart_7_wd = reg_wdata[15:0]; - assign perf_cnt_sel_7_hart_7_re = addr_hit[23] & reg_re & !reg_error; - - assign perf_cnt_sel_7_metric_7_we = addr_hit[23] & reg_we & !reg_error; - assign perf_cnt_sel_7_metric_7_wd = reg_wdata[31:16]; - assign perf_cnt_sel_7_metric_7_re = addr_hit[23] & reg_re & !reg_error; - - assign perf_cnt_sel_8_hart_8_we = addr_hit[24] & reg_we & !reg_error; - assign perf_cnt_sel_8_hart_8_wd = reg_wdata[15:0]; - assign perf_cnt_sel_8_hart_8_re = addr_hit[24] & reg_re & !reg_error; - - assign perf_cnt_sel_8_metric_8_we = addr_hit[24] & reg_we & !reg_error; - assign perf_cnt_sel_8_metric_8_wd = reg_wdata[31:16]; - assign perf_cnt_sel_8_metric_8_re = addr_hit[24] & reg_re & !reg_error; - - assign perf_cnt_sel_9_hart_9_we = addr_hit[25] & reg_we & !reg_error; - assign perf_cnt_sel_9_hart_9_wd = reg_wdata[15:0]; - assign perf_cnt_sel_9_hart_9_re = addr_hit[25] & reg_re & !reg_error; - - assign perf_cnt_sel_9_metric_9_we = addr_hit[25] & reg_we & !reg_error; - assign perf_cnt_sel_9_metric_9_wd = reg_wdata[31:16]; - assign perf_cnt_sel_9_metric_9_re = addr_hit[25] & reg_re & !reg_error; - - assign perf_cnt_sel_10_hart_10_we = addr_hit[26] & reg_we & !reg_error; - assign perf_cnt_sel_10_hart_10_wd = reg_wdata[15:0]; - assign perf_cnt_sel_10_hart_10_re = addr_hit[26] & reg_re & !reg_error; - - assign perf_cnt_sel_10_metric_10_we = addr_hit[26] & reg_we & !reg_error; - assign perf_cnt_sel_10_metric_10_wd = reg_wdata[31:16]; - assign perf_cnt_sel_10_metric_10_re = addr_hit[26] & reg_re & !reg_error; - - assign perf_cnt_sel_11_hart_11_we = addr_hit[27] & reg_we & !reg_error; - assign perf_cnt_sel_11_hart_11_wd = reg_wdata[15:0]; - assign perf_cnt_sel_11_hart_11_re = addr_hit[27] & reg_re & !reg_error; - - assign perf_cnt_sel_11_metric_11_we = addr_hit[27] & reg_we & !reg_error; - assign perf_cnt_sel_11_metric_11_wd = reg_wdata[31:16]; - assign perf_cnt_sel_11_metric_11_re = addr_hit[27] & reg_re & !reg_error; - - assign perf_cnt_sel_12_hart_12_we = addr_hit[28] & reg_we & !reg_error; - assign perf_cnt_sel_12_hart_12_wd = reg_wdata[15:0]; - assign perf_cnt_sel_12_hart_12_re = addr_hit[28] & reg_re & !reg_error; - - assign perf_cnt_sel_12_metric_12_we = addr_hit[28] & reg_we & !reg_error; - assign perf_cnt_sel_12_metric_12_wd = reg_wdata[31:16]; - assign perf_cnt_sel_12_metric_12_re = addr_hit[28] & reg_re & !reg_error; - - assign perf_cnt_sel_13_hart_13_we = addr_hit[29] & reg_we & !reg_error; - assign perf_cnt_sel_13_hart_13_wd = reg_wdata[15:0]; - assign perf_cnt_sel_13_hart_13_re = addr_hit[29] & reg_re & !reg_error; - - assign perf_cnt_sel_13_metric_13_we = addr_hit[29] & reg_we & !reg_error; - assign perf_cnt_sel_13_metric_13_wd = reg_wdata[31:16]; - assign perf_cnt_sel_13_metric_13_re = addr_hit[29] & reg_re & !reg_error; - - assign perf_cnt_sel_14_hart_14_we = addr_hit[30] & reg_we & !reg_error; - assign perf_cnt_sel_14_hart_14_wd = reg_wdata[15:0]; - assign perf_cnt_sel_14_hart_14_re = addr_hit[30] & reg_re & !reg_error; - - assign perf_cnt_sel_14_metric_14_we = addr_hit[30] & reg_we & !reg_error; - assign perf_cnt_sel_14_metric_14_wd = reg_wdata[31:16]; - assign perf_cnt_sel_14_metric_14_re = addr_hit[30] & reg_re & !reg_error; - - assign perf_cnt_sel_15_hart_15_we = addr_hit[31] & reg_we & !reg_error; - assign perf_cnt_sel_15_hart_15_wd = reg_wdata[15:0]; - assign perf_cnt_sel_15_hart_15_re = addr_hit[31] & reg_re & !reg_error; - - assign perf_cnt_sel_15_metric_15_we = addr_hit[31] & reg_we & !reg_error; - assign perf_cnt_sel_15_metric_15_wd = reg_wdata[31:16]; - assign perf_cnt_sel_15_metric_15_re = addr_hit[31] & reg_re & !reg_error; - - assign perf_cnt_0_we = addr_hit[32] & reg_we & !reg_error; - assign perf_cnt_0_wd = reg_wdata[47:0]; - assign perf_cnt_0_re = addr_hit[32] & reg_re & !reg_error; - - assign perf_cnt_1_we = addr_hit[33] & reg_we & !reg_error; - assign perf_cnt_1_wd = reg_wdata[47:0]; - assign perf_cnt_1_re = addr_hit[33] & reg_re & !reg_error; - - assign perf_cnt_2_we = addr_hit[34] & reg_we & !reg_error; - assign perf_cnt_2_wd = reg_wdata[47:0]; - assign perf_cnt_2_re = addr_hit[34] & reg_re & !reg_error; - - assign perf_cnt_3_we = addr_hit[35] & reg_we & !reg_error; - assign perf_cnt_3_wd = reg_wdata[47:0]; - assign perf_cnt_3_re = addr_hit[35] & reg_re & !reg_error; - - assign perf_cnt_4_we = addr_hit[36] & reg_we & !reg_error; - assign perf_cnt_4_wd = reg_wdata[47:0]; - assign perf_cnt_4_re = addr_hit[36] & reg_re & !reg_error; - - assign perf_cnt_5_we = addr_hit[37] & reg_we & !reg_error; - assign perf_cnt_5_wd = reg_wdata[47:0]; - assign perf_cnt_5_re = addr_hit[37] & reg_re & !reg_error; - - assign perf_cnt_6_we = addr_hit[38] & reg_we & !reg_error; - assign perf_cnt_6_wd = reg_wdata[47:0]; - assign perf_cnt_6_re = addr_hit[38] & reg_re & !reg_error; - - assign perf_cnt_7_we = addr_hit[39] & reg_we & !reg_error; - assign perf_cnt_7_wd = reg_wdata[47:0]; - assign perf_cnt_7_re = addr_hit[39] & reg_re & !reg_error; - - assign perf_cnt_8_we = addr_hit[40] & reg_we & !reg_error; - assign perf_cnt_8_wd = reg_wdata[47:0]; - assign perf_cnt_8_re = addr_hit[40] & reg_re & !reg_error; - - assign perf_cnt_9_we = addr_hit[41] & reg_we & !reg_error; - assign perf_cnt_9_wd = reg_wdata[47:0]; - assign perf_cnt_9_re = addr_hit[41] & reg_re & !reg_error; - - assign perf_cnt_10_we = addr_hit[42] & reg_we & !reg_error; - assign perf_cnt_10_wd = reg_wdata[47:0]; - assign perf_cnt_10_re = addr_hit[42] & reg_re & !reg_error; - - assign perf_cnt_11_we = addr_hit[43] & reg_we & !reg_error; - assign perf_cnt_11_wd = reg_wdata[47:0]; - assign perf_cnt_11_re = addr_hit[43] & reg_re & !reg_error; - - assign perf_cnt_12_we = addr_hit[44] & reg_we & !reg_error; - assign perf_cnt_12_wd = reg_wdata[47:0]; - assign perf_cnt_12_re = addr_hit[44] & reg_re & !reg_error; - - assign perf_cnt_13_we = addr_hit[45] & reg_we & !reg_error; - assign perf_cnt_13_wd = reg_wdata[47:0]; - assign perf_cnt_13_re = addr_hit[45] & reg_re & !reg_error; - - assign perf_cnt_14_we = addr_hit[46] & reg_we & !reg_error; - assign perf_cnt_14_wd = reg_wdata[47:0]; - assign perf_cnt_14_re = addr_hit[46] & reg_re & !reg_error; - - assign perf_cnt_15_we = addr_hit[47] & reg_we & !reg_error; - assign perf_cnt_15_wd = reg_wdata[47:0]; - assign perf_cnt_15_re = addr_hit[47] & reg_re & !reg_error; - - assign scratch_0_we = addr_hit[48] & reg_we & !reg_error; - assign scratch_0_wd = reg_wdata[31:0]; - - assign scratch_1_we = addr_hit[49] & reg_we & !reg_error; - assign scratch_1_wd = reg_wdata[31:0]; - - assign scratch_2_we = addr_hit[50] & reg_we & !reg_error; - assign scratch_2_wd = reg_wdata[31:0]; - - assign scratch_3_we = addr_hit[51] & reg_we & !reg_error; - assign scratch_3_wd = reg_wdata[31:0]; - - assign cl_clint_set_we = addr_hit[52] & reg_we & !reg_error; - assign cl_clint_set_wd = reg_wdata[31:0]; - - assign cl_clint_clear_we = addr_hit[53] & reg_we & !reg_error; - assign cl_clint_clear_wd = reg_wdata[31:0]; - - assign icache_prefetch_enable_we = addr_hit[54] & reg_we & !reg_error; - assign icache_prefetch_enable_wd = reg_wdata[0]; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = perf_cnt_en_0_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = perf_cnt_en_1_qs; - end - - addr_hit[2]: begin - reg_rdata_next[0] = perf_cnt_en_2_qs; - end - - addr_hit[3]: begin - reg_rdata_next[0] = perf_cnt_en_3_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = perf_cnt_en_4_qs; - end - - addr_hit[5]: begin - reg_rdata_next[0] = perf_cnt_en_5_qs; - end - - addr_hit[6]: begin - reg_rdata_next[0] = perf_cnt_en_6_qs; - end - - addr_hit[7]: begin - reg_rdata_next[0] = perf_cnt_en_7_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = perf_cnt_en_8_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = perf_cnt_en_9_qs; - end - - addr_hit[10]: begin - reg_rdata_next[0] = perf_cnt_en_10_qs; - end - - addr_hit[11]: begin - reg_rdata_next[0] = perf_cnt_en_11_qs; - end - - addr_hit[12]: begin - reg_rdata_next[0] = perf_cnt_en_12_qs; - end - - addr_hit[13]: begin - reg_rdata_next[0] = perf_cnt_en_13_qs; - end - - addr_hit[14]: begin - reg_rdata_next[0] = perf_cnt_en_14_qs; - end - - addr_hit[15]: begin - reg_rdata_next[0] = perf_cnt_en_15_qs; - end - - addr_hit[16]: begin - reg_rdata_next[15:0] = perf_cnt_sel_0_hart_0_qs; - reg_rdata_next[31:16] = perf_cnt_sel_0_metric_0_qs; - end - - addr_hit[17]: begin - reg_rdata_next[15:0] = perf_cnt_sel_1_hart_1_qs; - reg_rdata_next[31:16] = perf_cnt_sel_1_metric_1_qs; - end - - addr_hit[18]: begin - reg_rdata_next[15:0] = perf_cnt_sel_2_hart_2_qs; - reg_rdata_next[31:16] = perf_cnt_sel_2_metric_2_qs; - end - - addr_hit[19]: begin - reg_rdata_next[15:0] = perf_cnt_sel_3_hart_3_qs; - reg_rdata_next[31:16] = perf_cnt_sel_3_metric_3_qs; - end - - addr_hit[20]: begin - reg_rdata_next[15:0] = perf_cnt_sel_4_hart_4_qs; - reg_rdata_next[31:16] = perf_cnt_sel_4_metric_4_qs; - end - - addr_hit[21]: begin - reg_rdata_next[15:0] = perf_cnt_sel_5_hart_5_qs; - reg_rdata_next[31:16] = perf_cnt_sel_5_metric_5_qs; - end - - addr_hit[22]: begin - reg_rdata_next[15:0] = perf_cnt_sel_6_hart_6_qs; - reg_rdata_next[31:16] = perf_cnt_sel_6_metric_6_qs; - end - - addr_hit[23]: begin - reg_rdata_next[15:0] = perf_cnt_sel_7_hart_7_qs; - reg_rdata_next[31:16] = perf_cnt_sel_7_metric_7_qs; - end - - addr_hit[24]: begin - reg_rdata_next[15:0] = perf_cnt_sel_8_hart_8_qs; - reg_rdata_next[31:16] = perf_cnt_sel_8_metric_8_qs; - end - - addr_hit[25]: begin - reg_rdata_next[15:0] = perf_cnt_sel_9_hart_9_qs; - reg_rdata_next[31:16] = perf_cnt_sel_9_metric_9_qs; - end - - addr_hit[26]: begin - reg_rdata_next[15:0] = perf_cnt_sel_10_hart_10_qs; - reg_rdata_next[31:16] = perf_cnt_sel_10_metric_10_qs; - end - - addr_hit[27]: begin - reg_rdata_next[15:0] = perf_cnt_sel_11_hart_11_qs; - reg_rdata_next[31:16] = perf_cnt_sel_11_metric_11_qs; - end - - addr_hit[28]: begin - reg_rdata_next[15:0] = perf_cnt_sel_12_hart_12_qs; - reg_rdata_next[31:16] = perf_cnt_sel_12_metric_12_qs; - end - - addr_hit[29]: begin - reg_rdata_next[15:0] = perf_cnt_sel_13_hart_13_qs; - reg_rdata_next[31:16] = perf_cnt_sel_13_metric_13_qs; - end - - addr_hit[30]: begin - reg_rdata_next[15:0] = perf_cnt_sel_14_hart_14_qs; - reg_rdata_next[31:16] = perf_cnt_sel_14_metric_14_qs; - end - - addr_hit[31]: begin - reg_rdata_next[15:0] = perf_cnt_sel_15_hart_15_qs; - reg_rdata_next[31:16] = perf_cnt_sel_15_metric_15_qs; - end - - addr_hit[32]: begin - reg_rdata_next[47:0] = perf_cnt_0_qs; - end - - addr_hit[33]: begin - reg_rdata_next[47:0] = perf_cnt_1_qs; - end - - addr_hit[34]: begin - reg_rdata_next[47:0] = perf_cnt_2_qs; - end - - addr_hit[35]: begin - reg_rdata_next[47:0] = perf_cnt_3_qs; - end - - addr_hit[36]: begin - reg_rdata_next[47:0] = perf_cnt_4_qs; - end - - addr_hit[37]: begin - reg_rdata_next[47:0] = perf_cnt_5_qs; - end - - addr_hit[38]: begin - reg_rdata_next[47:0] = perf_cnt_6_qs; - end - - addr_hit[39]: begin - reg_rdata_next[47:0] = perf_cnt_7_qs; - end - - addr_hit[40]: begin - reg_rdata_next[47:0] = perf_cnt_8_qs; - end - - addr_hit[41]: begin - reg_rdata_next[47:0] = perf_cnt_9_qs; - end - - addr_hit[42]: begin - reg_rdata_next[47:0] = perf_cnt_10_qs; - end - - addr_hit[43]: begin - reg_rdata_next[47:0] = perf_cnt_11_qs; - end - - addr_hit[44]: begin - reg_rdata_next[47:0] = perf_cnt_12_qs; - end - - addr_hit[45]: begin - reg_rdata_next[47:0] = perf_cnt_13_qs; - end - - addr_hit[46]: begin - reg_rdata_next[47:0] = perf_cnt_14_qs; - end - - addr_hit[47]: begin - reg_rdata_next[47:0] = perf_cnt_15_qs; - end - - addr_hit[48]: begin - reg_rdata_next[31:0] = scratch_0_qs; - end - - addr_hit[49]: begin - reg_rdata_next[31:0] = scratch_1_qs; - end - - addr_hit[50]: begin - reg_rdata_next[31:0] = scratch_2_qs; - end - - addr_hit[51]: begin - reg_rdata_next[31:0] = scratch_3_qs; - end - - addr_hit[52]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[53]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[54]: begin - reg_rdata_next[0] = '0; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule - -module snitch_cluster_peripheral_reg_top_intf -#( - parameter int AW = 9, - localparam int DW = 64 -) ( - input logic clk_i, - input logic rst_ni, - REG_BUS.in regbus_slave, - // To HW - output snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_reg2hw_t reg2hw, // Write - input snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - localparam int unsigned STRB_WIDTH = DW/8; - -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - - // Define structs for reg_bus - typedef logic [AW-1:0] addr_t; - typedef logic [DW-1:0] data_t; - typedef logic [STRB_WIDTH-1:0] strb_t; - `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) - - reg_bus_req_t s_reg_req; - reg_bus_rsp_t s_reg_rsp; - - // Assign SV interface to structs - `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) - `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - - - - snitch_cluster_peripheral_reg_top #( - .reg_req_t(reg_bus_req_t), - .reg_rsp_t(reg_bus_rsp_t), - .AW(AW) - ) i_regs ( - .clk_i, - .rst_ni, - .reg_req_i(s_reg_req), - .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write - .hw2reg, // Read - .devmode_i - ); - -endmodule - - diff --git a/hw/snitch_cluster/src/snitch_cluster_wrapper.rdl.tpl b/hw/snitch_cluster/src/snitch_cluster_wrapper.rdl.tpl new file mode 100644 index 0000000000..ffebd5419d --- /dev/null +++ b/hw/snitch_cluster/src/snitch_cluster_wrapper.rdl.tpl @@ -0,0 +1,55 @@ +## Copyright 2025 ETH Zurich and University of Bologna. +## Solderpad Hardware License, Version 0.51, see LICENSE for details. +## SPDX-License-Identifier: SHL-0.51 +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +${disclaimer} + +<%! +import math + +def next_power_of_2(n): + """Returns the next power of 2 greater than or equal to n.""" + return 1 if n == 0 else 2**math.ceil(math.log2(n)) +%> + +`ifndef __${cfg['cluster']['name'].upper()}_WRAPPER_RDL__ +`define __${cfg['cluster']['name'].upper()}_WRAPPER_RDL__ + +`include "snitch_cluster_peripheral_reg.rdl" + +addrmap ${cfg['cluster']['name']}_wrapper #( + longint unsigned BASE_ADDR = ${hex(cfg['cluster']['cluster_base_addr'])} +) { + + default regwidth = ${cfg['cluster']['data_width']}; + + mem tcdm { + mementries = ${hex(int(cfg['cluster']['tcdm']['size'] * 1024 * 8 / cfg['cluster']['data_width']))}; + memwidth = ${cfg['cluster']['data_width']}; + }; + + mem bootrom { + mementries = ${hex(int(4 * 1024 * 8 / cfg['cluster']['data_width']))}; + memwidth = ${cfg['cluster']['data_width']}; + }; + + mem zeromem { + mementries = ${hex(int(cfg['cluster']['zero_mem_size'] * 1024 * 8 / cfg['cluster']['data_width']))}; + memwidth = ${cfg['cluster']['data_width']}; + }; + + + external tcdm tcdm @BASE_ADDR; +%if cfg['cluster']['int_bootrom_enable']: + external bootrom bootrom @BASE_ADDR + ${hex(next_power_of_2(cfg['cluster']['tcdm']['size']) * 1024)}; +% endif + snitch_cluster_peripheral_reg peripheral_reg @BASE_ADDR + ${hex((next_power_of_2(cfg['cluster']['tcdm']['size']) + (int(cfg['cluster']['int_bootrom_enable']) * 4)) * 1024)}; + external zeromem zeromem @BASE_ADDR + ${hex((next_power_of_2(cfg['cluster']['tcdm']['size']) + (int(cfg['cluster']['int_bootrom_enable']) * 4) + cfg['cluster']['cluster_periph_size']) * 1024)}; + + +}; + +`endif // __${cfg['cluster']['name'].upper()}_WRAPPER_RDL__ diff --git a/pyproject.toml b/pyproject.toml index 42e6e8ab00..907d1f2bd1 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -24,6 +24,9 @@ dependencies = [ "mako", "matplotlib", "pandas", + "peakrdl", + "peakrdl-markdown", + "peakrdl-rawheader@git+https://github.com/micprog/PeakRDL-rawheader.git@72cbbe03e672abc81cbcb3c8c1697a095b2e3410", "prettytable", "progressbar2", "psutil", diff --git a/sw/saris/runtime/crt0.S b/sw/saris/runtime/crt0.S index 7b3b8644cc..1fa425eb92 100644 --- a/sw/saris/runtime/crt0.S +++ b/sw/saris/runtime/crt0.S @@ -1,6 +1,6 @@ -# Copyright 2024 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 # HTIF sections .pushsection .htif,"aw",@progbits; diff --git a/sw/snRuntime/src/perf_cnt.h b/sw/snRuntime/src/perf_cnt.h index 38d0794e1c..a788fa6a1d 100644 --- a/sw/snRuntime/src/perf_cnt.h +++ b/sw/snRuntime/src/perf_cnt.h @@ -2,36 +2,25 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#define SNRT_NUM_PERF_CNTS SNITCH_CLUSTER_PERIPHERAL_PARAM_NUM_PERF_COUNTERS - -/** - * @brief Union representing a 32-bit performance counter register, with 8-byte - * alignment. - */ -typedef union { - uint32_t value __attribute__((aligned(8))); -} perf_reg32_t; +#define SNRT_NUM_PERF_CNTS \ + (sizeof(((perf_regs_t){}).perf_cnt) / sizeof(((perf_regs_t){}).perf_cnt[0])) /** * @brief Structure representing the performance counters. * * This structure defines the memory layout of the performance counters * configuration register, as they are defined in - * `snitch_cluster_peripheral.hjson`. + * `snitch_cluster_peripheral_reg.rdl`. */ -typedef struct { - volatile perf_reg32_t enable[SNRT_NUM_PERF_CNTS]; - volatile perf_reg32_t select[SNRT_NUM_PERF_CNTS]; - volatile perf_reg32_t perf_counter[SNRT_NUM_PERF_CNTS]; -} perf_regs_t; +typedef snitch_cluster_peripheral_reg__perf_regs_t perf_regs_t; /** * @brief Get the pointer to the performance counter registers * * @return perf_regs_t* Pointer to the performance counter registers */ -inline perf_regs_t* snrt_perf_counters() { - return (perf_regs_t*)snrt_cluster_perf_counters_addr(); +inline volatile perf_regs_t* snrt_perf_counters() { + return (volatile perf_regs_t*)snrt_cluster_perf_counters_addr(); } /** @@ -43,7 +32,8 @@ inline perf_regs_t* snrt_perf_counters() { */ inline void snrt_cfg_perf_counter(uint32_t perf_cnt, uint16_t metric, uint16_t hart) { - snrt_perf_counters()->select[perf_cnt].value = (metric << 16) | hart; + snrt_perf_counters()->perf_cnt_sel[perf_cnt].f.hart = hart; + snrt_perf_counters()->perf_cnt_sel[perf_cnt].f.metric = metric; } /** @@ -52,7 +42,7 @@ inline void snrt_cfg_perf_counter(uint32_t perf_cnt, uint16_t metric, * @param perf_cnt The index of the performance counter to start. */ inline void snrt_start_perf_counter(uint32_t perf_cnt) { - snrt_perf_counters()->enable[perf_cnt].value = 0x1; + snrt_perf_counters()->perf_cnt_en[perf_cnt].f.enable = 0x1; } /** @@ -61,7 +51,7 @@ inline void snrt_start_perf_counter(uint32_t perf_cnt) { * @param perf_cnt The index of the performance counter to stop. */ inline void snrt_stop_perf_counter(uint32_t perf_cnt) { - snrt_perf_counters()->enable[perf_cnt].value = 0x0; + snrt_perf_counters()->perf_cnt_en[perf_cnt].f.enable = 0x0; } /** @@ -70,7 +60,7 @@ inline void snrt_stop_perf_counter(uint32_t perf_cnt) { * @param perf_cnt The index of the performance counter to reset. */ inline void snrt_reset_perf_counter(uint32_t perf_cnt) { - snrt_perf_counters()->perf_counter[perf_cnt].value = 0x0; + snrt_perf_counters()->perf_cnt[perf_cnt].f.perf_counter = 0x0; } /** @@ -81,5 +71,5 @@ inline void snrt_reset_perf_counter(uint32_t perf_cnt) { * @return The value of the specified performance counter. */ inline uint32_t snrt_get_perf_counter(uint32_t perf_cnt) { - return snrt_perf_counters()->perf_counter[perf_cnt].value; + return snrt_perf_counters()->perf_cnt[perf_cnt].f.perf_counter; } diff --git a/sw/snRuntime/src/start.S b/sw/snRuntime/src/start.S index ac20066379..aef6147b71 100644 --- a/sw/snRuntime/src/start.S +++ b/sw/snRuntime/src/start.S @@ -1,6 +1,6 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 .section .init _start: diff --git a/sw/snRuntime/src/start.c b/sw/snRuntime/src/start.c index e41fa8ab28..9f6e4be7e7 100644 --- a/sw/snRuntime/src/start.c +++ b/sw/snRuntime/src/start.c @@ -43,8 +43,7 @@ static inline void snrt_init_tls() { tls_ptr += size; size = (size_t)(&__tbss_end) - (size_t)(&__tbss_start); for (int i = 0; i < snrt_cluster_core_num(); i++) { - snrt_dma_start_1d(tls_ptr + i * tls_offset, - (uint64_t)snrt_zero_memory_ptr(), size); + snrt_dma_memset((void*)(tls_ptr + i * tls_offset), 0, size); } snrt_dma_wait_all(); } @@ -61,8 +60,7 @@ static inline void snrt_init_bss() { if (snrt_cluster_idx() == 0) { if (snrt_is_dm_core()) { size_t size = (size_t)(&__bss_end) - (size_t)(&__bss_start); - snrt_dma_start_1d((uint64_t)(&__bss_start), - (uint64_t)(snrt_zero_memory_ptr()), size); + snrt_dma_memset((void*)&__bss_start, 0, size); snrt_dma_wait_all(); } snrt_cluster_hw_barrier(); @@ -97,7 +95,7 @@ static inline void snrt_init_cls() { // Clear cbss section ptr += size; size = (size_t)(&__cbss_end) - (size_t)(&__cbss_start); - snrt_dma_start_1d(ptr, (uint64_t)(snrt_zero_memory_ptr()), size); + snrt_dma_memset((void*)ptr, 0, size); snrt_dma_wait_all(); } snrt_cluster_hw_barrier(); diff --git a/sw/tests/perf_cnt.c b/sw/tests/perf_cnt.c index 82bab30a9c..06d015206b 100644 --- a/sw/tests/perf_cnt.c +++ b/sw/tests/perf_cnt.c @@ -34,10 +34,7 @@ int main() { if (core_idx == 0) { for (int i = 0; i < SNRT_NUM_PERF_CNTS; i++) { // Configure and start the performance counter - snrt_cfg_perf_counter( - i, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_CYCLE, - 0); + snrt_cfg_perf_counter(i, PERF_METRIC__CYCLE, 0); snrt_start_perf_counter(i); } @@ -63,14 +60,8 @@ int main() { // Test 4: Check DMA performance with simple 1D test if (snrt_is_dm_core()) { // Configure performance counters to track DMA read and writes - snrt_cfg_perf_counter( - 0, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_AW_DONE, - 0); - snrt_cfg_perf_counter( - 1, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_AR_DONE, - 0); + snrt_cfg_perf_counter(0, PERF_METRIC__DMA_AW_DONE, 0); + snrt_cfg_perf_counter(1, PERF_METRIC__DMA_AR_DONE, 0); // Transfer around some data uint32_t *dst = @@ -101,14 +92,8 @@ int main() { // Test 5: Check DMA performance with misaligned 1D test if (snrt_is_dm_core()) { // Configure performance counters to track DMA read and write beats - snrt_cfg_perf_counter( - 0, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_W_DONE, - 0); - snrt_cfg_perf_counter( - 1, - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_R_DONE, - 0); + snrt_cfg_perf_counter(0, PERF_METRIC__DMA_W_DONE, 0); + snrt_cfg_perf_counter(1, PERF_METRIC__DMA_R_DONE, 0); // Transfer around some data uint32_t *dst = diff --git a/target/common/common.mk b/target/common/common.mk index 68649343f5..0270ca1242 100644 --- a/target/common/common.mk +++ b/target/common/common.mk @@ -14,13 +14,13 @@ UTIL_DIR ?= $(SN_ROOT)/util LOGS_DIR = $(SIM_DIR)/logs SN_PERIPH_DIR = $(SN_ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral SN_TARGET_DIR = $(SN_ROOT)/target/snitch_cluster -SN_GEN_DIR ?= $(SN_TARGET_DIR)/.generated +SN_GEN_DIR ?= $(SN_TARGET_DIR)/generated SN_HW_DIR = $(SN_ROOT)/hw SN_BIN_DIR = $(SN_TARGET_DIR)/bin # External executables BENDER ?= bender -REGGEN ?= $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py +PEAKRDL ?= peakrdl VERIBLE_FMT ?= verible-verilog-format CLANG_FORMAT ?= clang-format RISCV_MC ?= $(LLVM_BINROOT)/llvm-mc @@ -85,11 +85,11 @@ $(SN_GEN_DIR) $(SN_BIN_DIR): # Util # ######## -# Common rule to generate C header with REGGEN -# $1: target name, $2: prerequisite (hjson description file) -define reggen_generate_header - @echo "[REGGEN] Generating $1" - @$(REGGEN) -D -o $1 $2 +# Common rule to generate C header with peakRDL +# $1: target name, $2: prerequisite (rdl description file) +define peakrdl_generate_header + @echo "[peakRDL] Generating $1" + $(PEAKRDL) c-header -b ltoh $2 -o $1 @$(CLANG_FORMAT) -i $1 endef diff --git a/target/common/rtl.mk b/target/common/rtl.mk index 5e6243cf36..32b3f02db9 100644 --- a/target/common/rtl.mk +++ b/target/common/rtl.mk @@ -8,26 +8,33 @@ SN_BOOTROM_DIR ?= $(SN_TARGET_DIR)/test # Templates SN_CLUSTER_WRAPPER_TPL = $(SN_HW_DIR)/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl SN_CLUSTER_PKG_TPL = $(SN_HW_DIR)/snitch_cluster/src/snitch_cluster_pkg.sv.tpl +SN_CLUSTER_RDL_TPL = $(SN_HW_DIR)/snitch_cluster/src/snitch_cluster_wrapper.rdl.tpl # Generated RTL sources -SN_CLUSTER_WRAPPER = $(SN_GEN_DIR)/snitch_cluster_wrapper.sv -SN_CLUSTER_PKG = $(SN_GEN_DIR)/snitch_cluster_pkg.sv -SN_CLUSTER_PERIPH_TOP = $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv -SN_CLUSTER_PERIPH_PKG = $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv -SN_BOOTROM = $(SN_BOOTROM_DIR)/snitch_bootrom.sv +SN_CLUSTER_WRAPPER = $(SN_GEN_DIR)/snitch_cluster_wrapper.sv +SN_CLUSTER_PKG = $(SN_GEN_DIR)/snitch_cluster_pkg.sv +SN_CLUSTER_ADDRMAP_SVH = $(SN_GEN_DIR)/snitch_cluster_addrmap.svh +SN_CLUSTER_PERIPH = $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg.sv +SN_CLUSTER_PERIPH_PKG = $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv +SN_BOOTROM = $(SN_BOOTROM_DIR)/snitch_bootrom.sv +SN_CLUSTER_RDL = $(SN_GEN_DIR)/snitch_cluster_wrapper.rdl # All generated RTL sources -SN_GEN_RTL_SRCS = $(SN_CLUSTER_WRAPPER) $(SN_CLUSTER_PKG) $(SN_CLUSTER_PERIPH_TOP) $(SN_CLUSTER_PERIPH_PKG) $(SN_BOOTROM) +SN_GEN_RTL_SRCS = $(SN_CLUSTER_WRAPPER) $(SN_CLUSTER_PKG) $(SN_CLUSTER_ADDRMAP_SVH) $(SN_CLUSTER_PERIPH) $(SN_CLUSTER_PERIPH_PKG) $(SN_BOOTROM) # CLUSTERGEN rules $(eval $(call sn_cluster_gen_rule,$(SN_CLUSTER_WRAPPER),$(SN_CLUSTER_WRAPPER_TPL))) $(eval $(call sn_cluster_gen_rule,$(SN_CLUSTER_PKG),$(SN_CLUSTER_PKG_TPL))) - -# REGGEN rules -$(SN_CLUSTER_PERIPH_PKG): $(SN_CLUSTER_PERIPH_TOP) -$(SN_CLUSTER_PERIPH_TOP): $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg.hjson - @echo "[REGGEN] Generating peripheral regfile" - $(REGGEN) -r -t $(SN_PERIPH_DIR) $< +$(eval $(call sn_cluster_gen_rule,$(SN_CLUSTER_RDL),$(SN_CLUSTER_RDL_TPL))) + +# peakRDL rules +$(SN_CLUSTER_PERIPH_PKG): $(SN_CLUSTER_PERIPH) +$(SN_CLUSTER_PERIPH): $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg.rdl + @echo "[peakrdl] Generating $@" + $(PEAKRDL) regblock $< -o $(SN_PERIPH_DIR) --cpuif apb4-flat --default-reset arst_n +$(SN_CLUSTER_ADDRMAP_SVH): $(SN_CLUSTER_RDL) + @echo "[peakrdl] Generating $@" + $(PEAKRDL) raw-header $< -o $@ --format svh -I $(SN_PERIPH_DIR) # Bootrom rules $(SN_BOOTROM_DIR)/bootrom.elf $(SN_BOOTROM_DIR)/bootrom.dump $(SN_BOOTROM_DIR)/bootrom.bin $(SN_BOOTROM): $(SN_BOOTROM_DIR)/bootrom.S $(SN_BOOTROM_DIR)/bootrom.ld $(SN_BOOTROM_GEN) | $(SN_BOOTROM_DIR) diff --git a/target/common/test/tb_memory_axi.sv b/target/common/test/tb_memory_axi.sv index 2c8e28a6e1..28070d63db 100644 --- a/target/common/test/tb_memory_axi.sv +++ b/target/common/test/tb_memory_axi.sv @@ -28,19 +28,12 @@ module tb_memory_axi #( `include "axi/assign.svh" `include "axi/typedef.svh" - `include "register_interface/typedef.svh" - `include "register_interface/assign.svh" - `include "common_cells/assertions.svh" + `include "common_cells/registers.svh" localparam int NumBytes = AxiDataWidth/8; localparam int BusAlign = $clog2(NumBytes); - REG_BUS #( - .ADDR_WIDTH ( AxiAddrWidth ), - .DATA_WIDTH ( AxiDataWidth ) - ) regb(clk_i); - AXI_BUS #( .AXI_ADDR_WIDTH ( AxiAddrWidth ), .AXI_DATA_WIDTH ( AxiDataWidth ), @@ -88,43 +81,77 @@ module tb_memory_axi #( .out (axi_wo_atomics_cut) ); - // Convert AXI to a trivial register interface. - axi_to_reg_intf #( - .ADDR_WIDTH ( AxiAddrWidth ), - .DATA_WIDTH ( AxiDataWidth ), - .ID_WIDTH ( AxiIdWidth ), - .USER_WIDTH ( AxiUserWidth ), - .DECOUPLE_W ( 1 ), - .FULL_BW ( 1 ), - .AXI_MAX_WRITE_TXNS ( 32'd128 ), - .AXI_MAX_READ_TXNS ( 32'd128 ) - ) i_axi_to_reg ( - .clk_i, - .rst_ni, - .testmode_i ( 1'b0 ), - .in ( axi_wo_atomics_cut ), - .reg_o ( regb ) + logic mem_req, mem_req_q; + logic [AxiAddrWidth-1:0] mem_addr; + logic [AxiDataWidth-1:0] mem_wdata; + logic [AxiDataWidth/8-1:0] mem_strb; + logic mem_we; + logic [AxiDataWidth-1:0] mem_rdata_q; + + axi_to_mem_intf #( + .ADDR_WIDTH (AxiAddrWidth), + .DATA_WIDTH (AxiDataWidth), + .ID_WIDTH (AxiIdWidth), + .USER_WIDTH (AxiUserWidth), + .NUM_BANKS (1) + ) i_axi_to_mem_intf ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .busy_o ( ), + .slv (axi_wo_atomics_cut), + .mem_req_o (mem_req), + .mem_gnt_i (1'b1), // Always ready + .mem_addr_o (mem_addr), + .mem_wdata_o (mem_wdata), + .mem_strb_o (mem_strb), + .mem_atop_o ( ), // ATOPs are resolved before + .mem_we_o (mem_we), + .mem_rvalid_i(mem_req_q), + .mem_rdata_i (mem_rdata_q) ); - `REG_BUS_TYPEDEF_ALL(regbus, - logic [AxiAddrWidth-1:0], logic [AxiDataWidth-1:0], logic [NumBytes-1:0]) - - regbus_req_t regbus_req; - regbus_rsp_t regbus_rsp; + import "DPI-C" function void tb_memory_read( + input longint addr, + input int len, + output byte data[] + ); + import "DPI-C" function void tb_memory_write( + input longint addr, + input int len, + input byte data[], + input bit strb[] + ); - `REG_BUS_ASSIGN_TO_REQ(regbus_req, regb) - `REG_BUS_ASSIGN_FROM_RSP(regb, regbus_rsp) + // Respond in the next cycle to the request. + `FF(mem_req_q, mem_req, '0) + + // Handle write requests on the mem bus. + always_ff @(posedge clk_i) begin + if (rst_ni && mem_req) begin + automatic byte data[NumBytes]; + automatic bit strb[NumBytes]; + if (mem_we) begin + for (int i = 0; i < NumBytes; i++) begin + // verilog_lint: waive-start always-ff-non-blocking + data[i] = mem_wdata[i*8+:8]; + strb[i] = mem_strb[i]; + // verilog_lint: waive-start always-ff-non-blocking + end + tb_memory_write((mem_addr >> BusAlign) << BusAlign, NumBytes, data, strb); + end + end + end - tb_memory_regbus #( - .AddrWidth (AxiAddrWidth), - .DataWidth (AxiDataWidth), - .req_t (regbus_req_t), - .rsp_t (regbus_rsp_t) - ) i_tb_memory_regbus ( - .clk_i, - .rst_ni, - .req_i (regbus_req), - .rsp_o (regbus_rsp) - ); + // Handle read requests on the mem bus. + always_ff @(posedge clk_i) begin + mem_rdata_q <= '0; + if (rst_ni && mem_req) begin + automatic byte data[NumBytes]; + tb_memory_read((mem_addr >> BusAlign) << BusAlign, NumBytes, data); + for (int i = 0; i < NumBytes; i++) begin + mem_rdata_q[i*8+:8] <= data[i]; + end + end + end endmodule diff --git a/target/common/test/tb_memory_regbus.sv b/target/common/test/tb_memory_regbus.sv deleted file mode 100644 index af6c1a434d..0000000000 --- a/target/common/test/tb_memory_regbus.sv +++ /dev/null @@ -1,78 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Fabian Schuiki -// Florian Zaruba - -module tb_memory_regbus #( - /// Regbus address width. - parameter int unsigned AddrWidth = 0, - /// Regbus data width. - parameter int unsigned DataWidth = 0, - parameter type req_t = logic, - parameter type rsp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input req_t req_i, - output rsp_t rsp_o -); - - `include "register_interface/assign.svh" - - import "DPI-C" function void tb_memory_read( - input longint addr, - input int len, - output byte data[] - ); - import "DPI-C" function void tb_memory_write( - input longint addr, - input int len, - input byte data[], - input bit strb[] - ); - - localparam int NumBytes = DataWidth/8; - localparam int BusAlign = $clog2(NumBytes); - - REG_BUS #( - .ADDR_WIDTH ( AddrWidth ), - .DATA_WIDTH ( DataWidth ) - ) regb(clk_i); - - `REG_BUS_ASSIGN_FROM_REQ(regb, req_i) - `REG_BUS_ASSIGN_TO_RSP(rsp_o, regb) - - assign regb.error = 0; - assign regb.ready = 1; - - // Handle write requests on the register bus. - always_ff @(posedge clk_i) begin - if (rst_ni && regb.valid) begin - automatic byte data[NumBytes]; - automatic bit strb[NumBytes]; - if (regb.write) begin - for (int i = 0; i < NumBytes; i++) begin - // verilog_lint: waive-start always-ff-non-blocking - data[i] = regb.wdata[i*8+:8]; - strb[i] = regb.wstrb[i]; - // verilog_lint: waive-start always-ff-non-blocking - end - tb_memory_write((regb.addr >> BusAlign) << BusAlign, NumBytes, data, strb); - end - end - end - - // Handle read requests combinatorial on the register bus. - always_comb begin - if (regb.valid) begin - automatic byte data[NumBytes]; - tb_memory_read((regb.addr >> BusAlign) << BusAlign, NumBytes, data); - for (int i = 0; i < NumBytes; i++) begin - regb.rdata[i*8+:8] = data[i]; - end - end - end - -endmodule diff --git a/target/snitch_cluster/.gitignore b/target/snitch_cluster/.gitignore index d67399e11e..537fb65ca4 100644 --- a/target/snitch_cluster/.gitignore +++ b/target/snitch_cluster/.gitignore @@ -1,5 +1,5 @@ /logs/ -/.generated/ +/generated/ /bin/ /cfg/lru.json /work/ diff --git a/target/snitch_cluster/sw.mk b/target/snitch_cluster/sw.mk index 2f021c1d59..a49fe4650d 100644 --- a/target/snitch_cluster/sw.mk +++ b/target/snitch_cluster/sw.mk @@ -19,19 +19,34 @@ sn-clean-sw: sn-clean-runtime sn-clean-tests SNRT_HAL_HDRS_DIR ?= $(SN_ROOT)/target/snitch_cluster/sw/runtime/common -SNITCH_CLUSTER_CFG_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_cfg.h -SNITCH_CLUSTER_ADDRMAP_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_addrmap.h -SNITCH_CLUSTER_PERIPHERAL_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_peripheral.h - -SNRT_HAL_HDRS = $(SNITCH_CLUSTER_CFG_H) $(SNITCH_CLUSTER_ADDRMAP_H) $(SNITCH_CLUSTER_PERIPHERAL_H) +SNITCH_CLUSTER_CFG_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_cfg.h +SNITCH_CLUSTER_ADDRMAP_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_addrmap.h +SNITCH_CLUSTER_WRAPPER_ADDRMAP_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_wrapper_addrmap.h +SNITCH_CLUSTER_PERIPHERAL_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_peripheral.h +SNITCH_CLUSTER_PERIPHERAL_ADDRMAP_H = $(SNRT_HAL_HDRS_DIR)/snitch_cluster_peripheral_addrmap.h + +SNRT_HAL_HDRS = $(SNITCH_CLUSTER_CFG_H) +SNRT_HAL_HDRS += $(SNITCH_CLUSTER_ADDRMAP_H) +SNRT_HAL_HDRS += $(SNITCH_CLUSTER_WRAPPER_ADDRMAP_H) +SNRT_HAL_HDRS += $(SNITCH_CLUSTER_PERIPHERAL_H) +SNRT_HAL_HDRS += $(SNITCH_CLUSTER_PERIPHERAL_ADDRMAP_H) # CLUSTERGEN headers $(eval $(call sn_cluster_gen_rule,$(SNITCH_CLUSTER_CFG_H),$(SNITCH_CLUSTER_CFG_H).tpl)) $(eval $(call sn_cluster_gen_rule,$(SNITCH_CLUSTER_ADDRMAP_H),$(SNITCH_CLUSTER_ADDRMAP_H).tpl)) -# REGGEN headers -$(SNITCH_CLUSTER_PERIPHERAL_H): $(SN_ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson $(REGGEN) - $(call reggen_generate_header,$@,$<) +# peakrdl headers +$(SNITCH_CLUSTER_PERIPHERAL_H): $(SN_ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl + $(call peakrdl_generate_header,$@,$<) + +$(SNITCH_CLUSTER_WRAPPER_ADDRMAP_H): $(SN_GEN_DIR)/snitch_cluster_wrapper.rdl + @echo "[peakrdl] Generating addrmap header" + $(PEAKRDL) raw-header $< -o $(SNITCH_CLUSTER_WRAPPER_ADDRMAP_H) --format c -I $(SN_PERIPH_DIR) + +$(SNITCH_CLUSTER_PERIPHERAL_ADDRMAP_H): $(SN_ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl + @echo "[peakrdl] Generating addrmap header" + $(PEAKRDL) raw-header $< -o $(SNITCH_CLUSTER_PERIPHERAL_ADDRMAP_H) --format c -I $(SN_PERIPH_DIR) + .PHONY: sn-clean-headers sn-clean-sw: sn-clean-headers diff --git a/target/snitch_cluster/sw/runtime/common/.gitignore b/target/snitch_cluster/sw/runtime/common/.gitignore index 91b6de1fa1..66c80e8d63 100644 --- a/target/snitch_cluster/sw/runtime/common/.gitignore +++ b/target/snitch_cluster/sw/runtime/common/.gitignore @@ -1,3 +1,5 @@ snitch_cluster_cfg.h snitch_cluster_addrmap.h +snitch_cluster_wrapper_addrmap.h snitch_cluster_peripheral.h +snitch_cluster_peripheral_addrmap.h diff --git a/target/snitch_cluster/sw/runtime/common/snitch_cluster_defs.h b/target/snitch_cluster/sw/runtime/common/snitch_cluster_defs.h index 433bec208e..92ff6415e8 100644 --- a/target/snitch_cluster/sw/runtime/common/snitch_cluster_defs.h +++ b/target/snitch_cluster/sw/runtime/common/snitch_cluster_defs.h @@ -4,4 +4,4 @@ #include "snitch_cluster_addrmap.h" #include "snitch_cluster_cfg.h" -#include "snitch_cluster_peripheral.h" +#include "snitch_cluster_peripheral_addrmap.h" diff --git a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h index 41951881a7..12969d0b5f 100644 --- a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h +++ b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h @@ -2,7 +2,9 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include #include +#include "snitch_cluster_peripheral.h" //=============================================================== // Constants @@ -10,14 +12,15 @@ #define CLUSTER_CLINT_SET_ADDR \ (CLUSTER_PERIPH_BASE_ADDR + \ - SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_REG_OFFSET) + offsetof(snitch_cluster_peripheral_reg_t, cl_clint_set)) #define CLUSTER_CLINT_CLR_ADDR \ (CLUSTER_PERIPH_BASE_ADDR + \ - SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_REG_OFFSET) + offsetof(snitch_cluster_peripheral_reg_t, cl_clint_clear)) -#define CLUSTER_PERF_COUNTER_ADDR \ - (CLUSTER_PERIPH_BASE_ADDR + \ - SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_REG_OFFSET) +#define CLUSTER_PERF_COUNTER_ADDR \ + (CLUSTER_PERIPH_BASE_ADDR + \ + offsetof(snitch_cluster_peripheral_reg_t, perf_regs) + \ + offsetof(snitch_cluster_peripheral_reg__perf_regs_t, perf_cnt_en[0])) //=============================================================== // snRuntime interface functions diff --git a/target/snitch_cluster/sw/runtime/rtl/src/snrt.S b/target/snitch_cluster/sw/runtime/rtl/src/snrt.S index be00599080..487b242a53 100644 --- a/target/snitch_cluster/sw/runtime/rtl/src/snrt.S +++ b/target/snitch_cluster/sw/runtime/rtl/src/snrt.S @@ -1,6 +1,6 @@ -# Copyright 2023 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 #define SNRT_INIT_INT_REGS #define SNRT_INIT_FP_REGS diff --git a/target/snitch_cluster/test/bootrom.S b/target/snitch_cluster/test/bootrom.S index c36ef38e30..59767dd100 100644 --- a/target/snitch_cluster/test/bootrom.S +++ b/target/snitch_cluster/test/bootrom.S @@ -1,6 +1,6 @@ -# Copyright 2024 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 #define MSTATUS_MIE 8 diff --git a/target/snitch_cluster/test/vip_snitch_cluster.sv b/target/snitch_cluster/test/vip_snitch_cluster.sv index 7ce30f529e..e7f8c5bd73 100644 --- a/target/snitch_cluster/test/vip_snitch_cluster.sv +++ b/target/snitch_cluster/test/vip_snitch_cluster.sv @@ -2,6 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 +`include "snitch_cluster_addrmap.svh" + module vip_snitch_cluster import snitch_cluster_pkg::*; #( @@ -32,8 +34,8 @@ module vip_snitch_cluster import "DPI-C" function int unsigned get_bin_entry(); localparam addr_t PeriphBaseAddr = CfgClusterBaseAddr + ((TcdmSizeNapotRounded + BootromSize) * 1024); - localparam addr_t Scratch1Addr = PeriphBaseAddr + SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET; - localparam addr_t SnitchClClintSetAddr = PeriphBaseAddr + SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET; + localparam addr_t Scratch1Addr = PeriphBaseAddr + `SNITCH_CLUSTER_WRAPPER_PERIPHERAL_REG_SCRATCH_1_REG_OFFSET; + localparam addr_t SnitchClClintSetAddr = PeriphBaseAddr + `SNITCH_CLUSTER_WRAPPER_PERIPHERAL_REG_CL_CLINT_SET_REG_OFFSET; /////////////////////////// // Clock, Reset, etc. // diff --git a/util/lint/waiver.verible b/util/lint/waiver.verible index 5413ede541..9737251f48 100644 --- a/util/lint/waiver.verible +++ b/util/lint/waiver.verible @@ -3,7 +3,15 @@ # SPDX-License-Identifier: SHL-0.51 # Auto-generated configuration registers are waived -waive --rule=typedef-structs-unions --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" +waive --rule=explicit-parameter-storage-type --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" waive --rule=line-length --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" -waive --rule=parameter-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv" -waive --rule=no-trailing-spaces --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv" +waive --rule=parameter-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" +waive --rule=struct-union-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" +waive --rule=typedef-structs-unions --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" +waive --rule=enum-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" + +waive --rule=generate-label --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv" +waive --rule=line-length --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv" +waive --rule=no-trailing-spaces --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv" +waive --rule=parameter-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv" +waive --rule=typedef-structs-unions --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv"