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Commit cb195e5

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MarinPostmaMarinPostma
authored
Winch: v128 logical ops for x64 (#10109)
* v128.not * v128.and * v128.andnot * v128.or * rename test files * v128.xor * enable spec tests * v128.bitselect * v128.any_true * v128.load*_lane * v128.load*_lane * cleanup duplicate methods * move lane/load to wasm_store/load * rename v128 functions * ensure avx support * fmt * fix merge blips * fix unsupported tests * fix missing avx checks
1 parent 24620d9 commit cb195e5

23 files changed

Lines changed: 1081 additions & 281 deletions

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‎crates/wast-util/src/lib.rs‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -425,14 +425,9 @@ impl WastTest {
425425
"misc_testsuite/simd/almost-extmul.wast",
426426
"misc_testsuite/simd/canonicalize-nan.wast",
427427
"misc_testsuite/simd/cvt-from-uint.wast",
428-
"misc_testsuite/simd/issue4807.wast",
429428
"misc_testsuite/simd/issue6725-no-egraph-panic.wast",
430429
"misc_testsuite/simd/issue_3327_bnot_lowering.wast",
431-
"misc_testsuite/simd/load_splat_out_of_bounds.wast",
432-
"misc_testsuite/simd/unaligned-load.wast",
433-
"multi-memory/simd_memory-multi.wast",
434430
"spec_testsuite/simd_bit_shift.wast",
435-
"spec_testsuite/simd_bitwise.wast",
436431
"spec_testsuite/simd_boolean.wast",
437432
"spec_testsuite/simd_const.wast",
438433
"spec_testsuite/simd_conversions.wast",
@@ -472,16 +467,8 @@ impl WastTest {
472467
"spec_testsuite/simd_int_to_int_extend.wast",
473468
"spec_testsuite/simd_lane.wast",
474469
"spec_testsuite/simd_load.wast",
475-
"spec_testsuite/simd_load16_lane.wast",
476-
"spec_testsuite/simd_load32_lane.wast",
477-
"spec_testsuite/simd_load64_lane.wast",
478-
"spec_testsuite/simd_load8_lane.wast",
479470
"spec_testsuite/simd_load_zero.wast",
480471
"spec_testsuite/simd_splat.wast",
481-
"spec_testsuite/simd_store16_lane.wast",
482-
"spec_testsuite/simd_store32_lane.wast",
483-
"spec_testsuite/simd_store64_lane.wast",
484-
"spec_testsuite/simd_store8_lane.wast",
485472
];
486473

487474
if unsupported.iter().any(|part| self.path.ends_with(part)) {
@@ -499,6 +486,19 @@ impl WastTest {
499486
"spec_testsuite/simd_align.wast",
500487
"spec_testsuite/simd_load_extend.wast",
501488
"spec_testsuite/simd_load_splat.wast",
489+
"spec_testsuite/simd_store16_lane.wast",
490+
"spec_testsuite/simd_store32_lane.wast",
491+
"spec_testsuite/simd_store64_lane.wast",
492+
"spec_testsuite/simd_store8_lane.wast",
493+
"spec_testsuite/simd_load16_lane.wast",
494+
"spec_testsuite/simd_load32_lane.wast",
495+
"spec_testsuite/simd_load64_lane.wast",
496+
"spec_testsuite/simd_load8_lane.wast",
497+
"spec_testsuite/simd_bitwise.wast",
498+
"misc_testsuite/simd/load_splat_out_of_bounds.wast",
499+
"misc_testsuite/simd/unaligned-load.wast",
500+
"multi-memory/simd_memory-multi.wast",
501+
"misc_testsuite/simd/issue4807.wast",
502502
];
503503

504504
if unsupported.iter().any(|part| self.path.ends_with(part)) {

‎tests/disas/winch/x64/v128_ops/and.wat‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (export "_start") (result v128)
7+
(v128.and
8+
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
9+
(v128.const i64x2 0xFFFFFFFFFFFFFFFF 0)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x4a
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x1c(%rip), %xmm0
24+
;; movdqu 0x24(%rip), %xmm1
25+
;; vpand %xmm0, %xmm1, %xmm1
26+
;; movdqa %xmm1, %xmm0
27+
;; addq $0x10, %rsp
28+
;; popq %rbp
29+
;; retq
30+
;; 4a: ud2
31+
;; 4c: addb %al, (%rax)
32+
;; 4e: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/andnot.wat‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (export "_start") (result v128)
7+
(v128.andnot
8+
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
9+
(v128.const i64x2 0xFFFFFFFFFFFFFFFF 0)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x4a
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x1c(%rip), %xmm0
24+
;; movdqu 0x24(%rip), %xmm1
25+
;; vpandn %xmm1, %xmm0, %xmm1
26+
;; movdqa %xmm1, %xmm0
27+
;; addq $0x10, %rsp
28+
;; popq %rbp
29+
;; retq
30+
;; 4a: ud2
31+
;; 4c: addb %al, (%rax)
32+
;; 4e: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/any_true.wat‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (export "_start") (result i32)
7+
(v128.any_true
8+
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
9+
)))
10+
;; wasm[0]::function[0]:
11+
;; pushq %rbp
12+
;; movq %rsp, %rbp
13+
;; movq 8(%rdi), %r11
14+
;; movq 0x10(%r11), %r11
15+
;; addq $0x10, %r11
16+
;; cmpq %rsp, %r11
17+
;; ja 0x48
18+
;; 1c: movq %rdi, %r14
19+
;; subq $0x10, %rsp
20+
;; movq %rdi, 8(%rsp)
21+
;; movq %rsi, (%rsp)
22+
;; movdqu 0x1c(%rip), %xmm0
23+
;; vptest %xmm0, %xmm0
24+
;; movl $0, %eax
25+
;; setne %al
26+
;; addq $0x10, %rsp
27+
;; popq %rbp
28+
;; retq
29+
;; 48: ud2
30+
;; 4a: addb %al, (%rax)
31+
;; 4c: addb %al, (%rax)
32+
;; 4e: addb %al, (%rax)
33+
;; 50: addb %al, (%rax)
34+
;; 52: addb %al, (%rax)
35+
;; 54: addb %al, (%rax)
36+
;; 56: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/bitselect.wat‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (export "_start") (result v128)
7+
(v128.bitselect
8+
(v128.const i64x2 0x3298472837385628 0x58212382347A3994)
9+
(v128.const i64x2 0x7483929592465832 0x1285837491823847)
10+
(v128.const i64x2 0xFFFFFF0FFFFFFFFF 0xFFFFFF0FFFFFFFFF)
11+
)))
12+
;; wasm[0]::function[0]:
13+
;; pushq %rbp
14+
;; movq %rsp, %rbp
15+
;; movq 8(%rdi), %r11
16+
;; movq 0x10(%r11), %r11
17+
;; addq $0x10, %r11
18+
;; cmpq %rsp, %r11
19+
;; ja 0x5a
20+
;; 1c: movq %rdi, %r14
21+
;; subq $0x10, %rsp
22+
;; movq %rdi, 8(%rsp)
23+
;; movq %rsi, (%rsp)
24+
;; movdqu 0x2c(%rip), %xmm0
25+
;; movdqu 0x34(%rip), %xmm1
26+
;; movdqu 0x3c(%rip), %xmm2
27+
;; vpand %xmm0, %xmm2, %xmm15
28+
;; vpandn %xmm1, %xmm0, %xmm3
29+
;; vpor %xmm3, %xmm15, %xmm3
30+
;; movdqa %xmm3, %xmm0
31+
;; addq $0x10, %rsp
32+
;; popq %rbp
33+
;; retq
34+
;; 5a: ud2
35+
;; 5c: addb %al, (%rax)
36+
;; 5e: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/load_lane/load16.wat‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(memory 1 1)
7+
(func (export "_start") (result v128)
8+
(v128.load16_lane
9+
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x50
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x2c(%rip), %xmm0
24+
;; movl $0, %eax
25+
;; movq 0x50(%r14), %rcx
26+
;; addq %rax, %rcx
27+
;; movzwq (%rcx), %r11
28+
;; vpinsrw $1, %r11d, %xmm0, %xmm0
29+
;; addq $0x10, %rsp
30+
;; popq %rbp
31+
;; retq
32+
;; 50: ud2
33+
;; 52: addb %al, (%rax)
34+
;; 54: addb %al, (%rax)
35+
;; 56: addb %al, (%rax)
36+
;; 58: addb %al, (%rax)
37+
;; 5a: addb %al, (%rax)
38+
;; 5c: addb %al, (%rax)
39+
;; 5e: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/load_lane/load32.wat‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(memory 1 1)
7+
(func (export "_start") (result v128)
8+
(v128.load32_lane
9+
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x4f
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x2c(%rip), %xmm0
24+
;; movl $0, %eax
25+
;; movq 0x50(%r14), %rcx
26+
;; addq %rax, %rcx
27+
;; movl (%rcx), %r11d
28+
;; vpinsrd $1, %r11d, %xmm0, %xmm0
29+
;; addq $0x10, %rsp
30+
;; popq %rbp
31+
;; retq
32+
;; 4f: ud2
33+
;; 51: addb %al, (%rax)
34+
;; 53: addb %al, (%rax)
35+
;; 55: addb %al, (%rax)
36+
;; 57: addb %al, (%rax)
37+
;; 59: addb %al, (%rax)
38+
;; 5b: addb %al, (%rax)
39+
;; 5d: addb %al, (%rax)
40+
;; 5f: addb %bh, %bh

‎tests/disas/winch/x64/v128_ops/load_lane/load64.wat‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(memory 1 1)
7+
(func (export "_start") (result v128)
8+
(v128.load64_lane
9+
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x4f
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x2c(%rip), %xmm0
24+
;; movl $0, %eax
25+
;; movq 0x50(%r14), %rcx
26+
;; addq %rax, %rcx
27+
;; movq (%rcx), %r11
28+
;; vpinsrq $1, %r11, %xmm0, %xmm0
29+
;; addq $0x10, %rsp
30+
;; popq %rbp
31+
;; retq
32+
;; 4f: ud2
33+
;; 51: addb %al, (%rax)
34+
;; 53: addb %al, (%rax)
35+
;; 55: addb %al, (%rax)
36+
;; 57: addb %al, (%rax)
37+
;; 59: addb %al, (%rax)
38+
;; 5b: addb %al, (%rax)
39+
;; 5d: addb %al, (%rax)
40+
;; 5f: addb %bh, %bh

‎tests/disas/winch/x64/v128_ops/load_lane/load8.wat‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(memory 1 1)
7+
(func (export "_start") (result v128)
8+
(v128.load8_lane
9+
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
10+
)))
11+
;; wasm[0]::function[0]:
12+
;; pushq %rbp
13+
;; movq %rsp, %rbp
14+
;; movq 8(%rdi), %r11
15+
;; movq 0x10(%r11), %r11
16+
;; addq $0x10, %r11
17+
;; cmpq %rsp, %r11
18+
;; ja 0x50
19+
;; 1c: movq %rdi, %r14
20+
;; subq $0x10, %rsp
21+
;; movq %rdi, 8(%rsp)
22+
;; movq %rsi, (%rsp)
23+
;; movdqu 0x2c(%rip), %xmm0
24+
;; movl $0, %eax
25+
;; movq 0x50(%r14), %rcx
26+
;; addq %rax, %rcx
27+
;; movzbq (%rcx), %r11
28+
;; vpinsrb $1, %r11d, %xmm0, %xmm0
29+
;; addq $0x10, %rsp
30+
;; popq %rbp
31+
;; retq
32+
;; 50: ud2
33+
;; 52: addb %al, (%rax)
34+
;; 54: addb %al, (%rax)
35+
;; 56: addb %al, (%rax)
36+
;; 58: addb %al, (%rax)
37+
;; 5a: addb %al, (%rax)
38+
;; 5c: addb %al, (%rax)
39+
;; 5e: addb %al, (%rax)

‎tests/disas/winch/x64/v128_ops/not.wat‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
;;! target = "x86_64"
2+
;;! test = "winch"
3+
;;! flags = [ "-Ccranelift-has-avx" ]
4+
5+
(module
6+
(func (export "_start") (result v128)
7+
(v128.not (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0))))
8+
;; wasm[0]::function[0]:
9+
;; pushq %rbp
10+
;; movq %rsp, %rbp
11+
;; movq 8(%rdi), %r11
12+
;; movq 0x10(%r11), %r11
13+
;; addq $0x10, %r11
14+
;; cmpq %rsp, %r11
15+
;; ja 0x43
16+
;; 1c: movq %rdi, %r14
17+
;; subq $0x10, %rsp
18+
;; movq %rdi, 8(%rsp)
19+
;; movq %rsi, (%rsp)
20+
;; movdqu 0x1c(%rip), %xmm0
21+
;; vpcmpeqd %xmm15, %xmm15, %xmm15
22+
;; vpxor %xmm0, %xmm15, %xmm0
23+
;; addq $0x10, %rsp
24+
;; popq %rbp
25+
;; retq
26+
;; 43: ud2
27+
;; 45: addb %al, (%rax)
28+
;; 47: addb %al, (%rax)
29+
;; 49: addb %al, (%rax)
30+
;; 4b: addb %al, (%rax)
31+
;; 4d: addb %al, (%rax)
32+
;; 4f: addb %bh, %bh

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