diff --git a/src/arm64/k3-j721e-main.dtsi b/src/arm64/k3-j721e-main.dtsi
index 8d676cf61..822882d19 100644
--- a/src/arm64/k3-j721e-main.dtsi
+++ b/src/arm64/k3-j721e-main.dtsi
@@ -1625,19 +1625,15 @@
 	};
 
 	dsi0: dsi@48000000 {
-		compatible = "cdns,dsi";
+		compatible = "ti,j721e-dsi";
 		reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
 		clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
 		clock-names = "dsi_p_clk", "dsi_sys_clk";
-		resets = <&k3_reset 150 1>;
-		reset-names = "dsi_p_rst";
 		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
 		interrupt-parent = <&gic500>;
 		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
 		phys = <&dphy2>;
 		phy-names = "dphy";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
 		dsi0_ports: ports {
 			#address-cells = <1>;
@@ -2714,11 +2710,14 @@
 	};
 
 	dphy2: phy@4480000 {
-		compatible = "cdns,dphy";
-		reg = <0x0 0x04480000 0x0 0x1100>;
+		compatible = "ti,j721e-dphy";
+		reg = <0x0 0x04480000 0x0 0x1000>;
 		clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
 		clock-names = "psm", "pll_ref";
 		#phy-cells = <0>;
 		power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 296 3>;
+		assigned-clock-parents = <&k3_clks 296 4>;
+		assigned-clock-rates = <19200000>;
 	};
 };
diff --git a/src/arm64/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts b/src/arm64/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
index 216a353ec..e2eb34efa 100644
--- a/src/arm64/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
+++ b/src/arm64/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
@@ -53,6 +53,7 @@
 };
 
 &main_i2c4 {
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_i2c4_pins_default>;
 	clock-frequency = <400000>;
@@ -137,9 +138,3 @@
 	};
 
 };
-
-&dphy2 {
-	assigned-clocks = <&k3_clks 296 3>;
-	assigned-clock-parents = <&k3_clks 296 4>;
-	assigned-clock-rates = <19200000>;
-};