ACE-3 is currently a private research and development project.
- Keep synthesizable RTL, testbenches, software oracles, and generated evidence in separate directories.
- Add or update a precision/interface contract with every arithmetic change.
- Compare RTL against an independent oracle, not a copy of DUT logic.
- Preserve exact model revision and tensor identities for model-bound vectors.
- Report unsupported behavior explicitly; do not add silent floating-point or software fallback.
- Do not claim synthesis, FPGA execution, performance, or chip completion without corresponding artifacts.
Each pull request should state:
- the implemented execution boundary;
- the contract changed or preserved;
- the smallest reproducible validation command;
- the evidence produced;
- known unsupported cases and claim boundaries.
Generated model files, credentials, local state, and proprietary tool outputs must not be committed.