diff --git a/src/main/scala/utility/Select.scala b/src/main/scala/utility/Select.scala
index 6743ec6..b56fc5b 100644
--- a/src/main/scala/utility/Select.scala
+++ b/src/main/scala/utility/Select.scala
@@ -30,7 +30,7 @@ object SelectByFn {
     })
 
     type SelectNode = (Bool, (T, SelectT))
-  
+
     def pipelineReg(in: SelectNode): SelectNode = {
       val (valid, (bits, sel)) = in
       (RegNext(valid, false.B), (RegNext(bits), RegNext(sel)))
diff --git a/src/main/scala/utility/TLUtils/BusKeyField.scala b/src/main/scala/utility/TLUtils/BusKeyField.scala
index e438253..105e136 100644
--- a/src/main/scala/utility/TLUtils/BusKeyField.scala
+++ b/src/main/scala/utility/TLUtils/BusKeyField.scala
@@ -45,8 +45,14 @@ object MemReqSource extends Enumeration {
   val Prefetch2L3Stride = Value("Prefetch2L3Stride")
   val Prefetch2L3Berti = Value("Prefetch2L3Berti")
   val Prefetch2L3Unknown = Value("Prefetch2L3Unknown")
+  // Kept for compatibility with the earlier matrix request-source API.
   val CPUMatrixData = Value("CPUMatrixData")
   val Prefetch2L2Matrix = Value("Prefetch2L2Matrix")
+  // Matrix accesses are issued by CUTE rather than the CPU pipeline. Keep
+  // reads and writes distinct so cache accounting can classify them without
+  // treating CUTE traffic as ordinary CPU requests.
+  val MatrixRead = Value("MatrixRead")
+  val MatrixWrite = Value("MatrixWrite")
   val ReqSourceCount = Value("ReqSourceCount")
 
   val reqSourceBits = log2Ceil(ReqSourceCount.id)
@@ -62,6 +68,12 @@ object MemReqSource extends Enumeration {
     reqSource === L1DataPrefetch.id.U
   }
 
+  def isMatrixReq(reqSource: UInt): Bool = {
+    reqSource === CPUMatrixData.id.U ||
+    reqSource === MatrixRead.id.U ||
+    reqSource === MatrixWrite.id.U
+  }
+
   def isL2Prefetch(reqSource: UInt): Bool = {
     reqSource === Prefetch2L2BOP.id.U ||
     reqSource === Prefetch2L2PBOP.id.U ||