diff --git a/.checkpatch.conf b/.checkpatch.conf new file mode 100644 index 0000000000..f432503e1a --- /dev/null +++ b/.checkpatch.conf @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +--max-line-length=120 +--tab-size=4 +--show-types +--strict + +--typedefsfile tools/scripts/typedefs.txt + +--ignore AVOID_EXTERNS +--ignore BLOCK_COMMENT_STYLE +--ignore COMPLEX_MACRO +--ignore CONST_STRUCT +--ignore ENOSYS +--ignore FILE_PATH_CHANGES +--ignore GERRIT_CHANGE_ID +--ignore LINE_SPACING +--ignore LOGICAL_CONTINUATIONS +--ignore MACRO_WITH_FLOW_CONTROL +--ignore PARENTHESIS_ALIGNMENT +--ignore PREFER_DEFINED_ATTRIBUTE_MACRO +--ignore PREFER_FALLTHROUGH +--ignore PREFER_KERNEL_TYPES +--ignore SPLIT_STRING +--ignore SSCANF_TO_KSTRTO +--ignore SWITCH_CASE_INDENT_LEVEL +--ignore TRACING_LOGGING +--ignore VOLATILE diff --git a/.gitignore b/.gitignore index f5aa68a405..f0746c1950 100644 --- a/.gitignore +++ b/.gitignore @@ -11,9 +11,9 @@ *.la *.in -# generated source files -src/jtag/minidriver_imp.h -src/jtag/jtag_minidriver.h +# coverage files (gcov) +*.gcda +*.gcno # OpenULINK driver files generated by SDCC src/jtag/drivers/OpenULINK/*.rel @@ -68,7 +68,6 @@ doxygen doxygen.log Doxyfile libtool -*-libtool Makefile !contrib/loaders/**/Makefile stamp-h1 @@ -85,6 +84,9 @@ patches .cproject .settings +# VSCode stuff +.vscode + # Emacs temp files *~ @@ -101,3 +103,14 @@ tags GPATH GRTAGS GTAGS + +# checkpatch script files +.checkpatch-camelcase.* + +# clangd (e.g. for advanced code completion and linting) generates cache files +# into .cache +.cache + +# A compile_commands.json can be generated using bear and will help tools such +# as clangd to locate header files and use correct $CFLAGS +compile_commands.json diff --git a/.gitmodules b/.gitmodules index f2da17ed7a..abb7735382 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ -[submodule "tools/git2cl"] - path = tools/git2cl - url = https://git.savannah.nongnu.org/git/git2cl.git [submodule "jimtcl"] path = jimtcl url = https://github.com/msteveb/jimtcl.git diff --git a/.travis.yml b/.travis.yml index da6b94c3f0..28d5502c5c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0-or-later # Copyright Marek Vasut # OpenOCD on Travis CI - https://travis-ci.org/ diff --git a/AUTHORS b/AUTHORS index 2a989f37ec..7489834647 100644 --- a/AUTHORS +++ b/AUTHORS @@ -1,12 +1,2 @@ -Dominic Rath -Magnus Lundin -Michael Fischer -Spencer Oliver -Carsten Schlote -Øyvind Harboe -Duane Ellis -Michael Schwingen -Rick Altherr -David Brownell -Vincint Palatin -Zachary T Welch +Please check the source code files and/or Git history for a list of all authors +and contributors. diff --git a/HACKING b/HACKING index 96b05f2d62..785179efe9 100644 --- a/HACKING +++ b/HACKING @@ -77,6 +77,37 @@ patch: src/openocd -s ../tcl -f /path/to/openocd.cfg @endcode +- Sparse Static Analyzer + + Using this tool allows identifying some bug in C code. + In the future, OpenOCD would use the sparse attribute 'bitwise' to + detect incorrect endianness assignments. + + Example usage: + @code + mkdir build-sparse; cd build-sparse + ../configure CC=cgcc CFLAGS="-Wsparse-all -Wno-declaration-after-statement \ + -Wno-unknown-attribute -Wno-transparent-union -Wno-tautological-compare \ + -Wno-vla -Wno-flexible-array-array -D__FLT_EVAL_METHOD__=0" + make + @endcode + +- Code coverage analysis + + By inspecting the code coverage, you can identify potential gaps in your testing + and use that information to improve your test scenarios. + + Example usage: + @code + mkdir build-gcov; cd build-gcov + ../configure --enable-gcov [...] + make + # ... Now execute your test scenarios to collect OpenOCD code coverage ... + lcov --capture --directory ./src --output-file openocd-coverage.info + genhtml openocd-coverage.info --output-directory coverage_report + # ... Open coverage_report/index.html in a web browser ... + @endcode + Please consider performing these additional checks where appropriate (especially Clang Static Analyzer for big portions of new code) and mention the results (e.g. "Valgrind-clean, no new Clang analyzer @@ -138,11 +169,9 @@ git remote add review https://USERNAME:PASSWORD@review.openocd.org/p/openocd.git Gerrit server, even if you plan to use several local branches for different topics. It is possible because @c for/master is not a traditional Git branch. - -# You will need to install this hook, we will look into a better solution: -@code -scp -p -P 29418 USERNAME@review.openocd.org:hooks/commit-msg .git/hooks/ -@endcode - Or with http only: + -# You will need to install this hook to automatically add the + field "Change-Id:" in the commit message, as required by Gerrit. + We will look into a better solution: @code wget https://review.openocd.org/tools/hooks/commit-msg mv commit-msg .git/hooks @@ -171,6 +200,8 @@ while(!done) { @endcode \note use "git add ." before commit to add new files. + \note check @ref checkpatch for hint about checkpatch script + Commit message template, notice the short first line. The field 'specify touched area' should identify the main part or subsystem the patch touches. @@ -179,7 +210,9 @@ specify touched area: short comment Longer comments over several lines, explaining (where applicable) the reason for the patch and the general idea the solution is based on, -any major design decisions, etc... +any major design decisions, etc. Limit each comment line's length to 75 +characters; since 75 it's too short for a URL, you can put the URL in a +separate line preceded by 'Link: '. Signed-off-by: ... @endcode @@ -215,6 +248,12 @@ doc: fix typos @code git pull --rebase origin master @endcode + +-# When you create a new version of an old patch, check that the new patch + keeps the same 'Change-Id:' field of the old patch. + This allows the Gerrit server to recognize the patch as a new version of + the older one and keeps track of the history and the review process. + -# Send the patches to the Gerrit server for review: @code git push review @@ -227,6 +266,72 @@ git push review Further reading: http://www.coreboot.org/Git +@section checkpatch About checkpatch script + +OpenOCD source code includes the script checkpatch to let developers to +verify their patches before submitting them for review (see @ref gerrit). + +Every patch for OpenOCD project that is submitted for review on Gerrit +is tested by Jenkins. Jenkins will run the checkpatch script to analyze +each patch. +If the script highlights either errors or warnings, Gerrit will add the +score "-1" to the patch and maintainers will probably ignore the patch, +waiting for the developer to send a fixed version. + +The script checkpatch verifies the SPDX tag for new files against a very +short list of license tags. +If the license of your contribution is not listed there, but compatible +with OpenOCD license, please alert the maintainers or add the missing +license in the first patch of your patch series. + +The script checkpatch has been originally developed for the Linux kernel +source code, thus includes specific tests and checks related to Linux +coding style and to Linux code structure. While the script has been +adapted for OpenOCD specificities, it still includes some Linux related +test. It is then possible that it triggers sometimes some false +positive! + +If you think that the error identified by checkpatch is a false +positive, please report it to the openocd-devel mailing list or prepare +a patch for fixing checkpatch and send it to Gerrit for review. + +\attention The procedure below is allowed only for exceptional +cases. Do not use it to submit normal patches. + +There are exceptional cases in which you need to skip some of +the tests from checkpatch in order to pass the approval from Gerrit. + +For example, a patch that modify one line inside a big comment block +will not show the beginning or the end of the comment block. This can +prevent checkpatch to detect the comment block. Checkpatch can wrongly +consider the modified comment line as a code line, triggering a set of +false errors. + +Only for exceptional cases, it is allowed to submit patches +to Gerrit with the special field 'Checkpatch-ignore:' in the commit +message. This field will cause checkpatch to ignore the error types +listed in the field, only for the patch itself. +For errors in the commit message, the special field has to be put in +the commit message before the line that produces the error. +The special field must be added before the 'Signed-off-by:' +line, otherwise it is ignored. +To ignore multiple errors, either add multiple lines with the special +field or add multiple error types, separated by space or commas, in a +single line. +The error type is printed by checkpatch on failure. +For example the names of Windows APIs mix lower and upper case chars, +in violation of OpenOCD coding style, triggering a 'CAMELCASE' error: +@code +CHECK:CAMELCASE: Avoid CamelCase: +#96105: FILE: src/helper/log.c:505: ++ error_code = WSAGetLastError(); +@endcode +Adding in the commit message of the patch the line: +@code +Checkpatch-ignore: CAMELCASE +@endcode +will force checkpatch to ignore the CAMELCASE error. + @section timeline When can I expect my contribution to be committed? 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Except for the limited purpose of indicating that +material is shared under a Creative Commons public license or as +otherwise permitted by the Creative Commons policies published at +creativecommons.org/policies, Creative Commons does not authorize the +use of the trademark "Creative Commons" or any other trademark or logo +of Creative Commons without its prior written consent including, +without limitation, in connection with any unauthorized modifications +to any of its public licenses or any other arrangements, +understandings, or agreements concerning use of licensed material. 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For 'GNU General Public License (GPL) version 2 only' use: - SPDX-License-Identifier: GPL-2.0 - or SPDX-License-Identifier: GPL-2.0-only For 'GNU General Public License (GPL) version 2 or any later version' use: SPDX-License-Identifier: GPL-2.0-or-later License-Text: Full license text -2. Exceptions: +2. Dual Licensing Only: + + These licenses should only be used to dual license code with another + license in addition to a preferred license. These licenses are available + from the directory:: + + LICENSES/dual/ + + in the OpenOCD source tree. + + The files in this directory contain the full license text and + `Metatags`_. The file names are identical to the SPDX license + identifier which shall be used for the license in source files. + +3. Exceptions: Some licenses can be amended with exceptions which grant certain rights which the original license does not. These exceptions are available @@ -247,7 +258,7 @@ OpenOCD, can be broken down into: License-Text: Full license text -3. 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You are solely + responsible for determining the appropriateness of using or + redistributing the Work and assume any risks associated with Your + exercise of permissions under this License. + +8. Limitation of Liability. In no event and under no legal theory, whether + in tort (including negligence), contract, or otherwise, unless required + by applicable law (such as deliberate and grossly negligent acts) or + agreed to in writing, shall any Contributor be liable to You for + damages, including any direct, indirect, special, incidental, or + consequential damages of any character arising as a result of this + License or out of the use or inability to use the Work (including but + not limited to damages for loss of goodwill, work stoppage, computer + failure or malfunction, or any and all other commercial damages or + losses), even if such Contributor has been advised of the possibility of + such damages. + +9. Accepting Warranty or Additional Liability. While redistributing the + Work or Derivative Works thereof, You may choose to offer, and charge a + fee for, acceptance of support, warranty, indemnity, or other liability + obligations and/or rights consistent with this License. However, in + accepting such obligations, You may act only on Your own behalf and on + Your sole responsibility, not on behalf of any other Contributor, and + only if You agree to indemnify, defend, and hold each Contributor + harmless for any liability incurred by, or claims asserted against, such + Contributor by reason of your accepting any such warranty or additional + liability. + +END OF TERMS AND CONDITIONS diff --git a/Makefile.am b/Makefile.am index 41daf9522c..845543721d 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# not a GNU package. You can remove this line, if -# have all needed files, that a GNU package needs -AUTOMAKE_OPTIONS = gnu 1.6 +AUTOMAKE_OPTIONS = gnu 1.14 .DELETE_ON_ERROR: # make sure we pass the correct jimtcl flags to distcheck -DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim +AM_DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim # do not run Jim Tcl tests (esp. during distcheck) -check-recursive: SUBDIRS := +check-recursive: SUBDIRS := $(SUBDIRS:jimtcl=) nobase_dist_pkgdata_DATA = \ contrib/libdcc/dcc_stdio.c \ @@ -26,14 +24,22 @@ noinst_LTLIBRARIES = info_TEXINFOS = dist_man_MANS = EXTRA_DIST = +DISTCLEANFILES = if INTERNAL_JIMTCL SUBDIRS += jimtcl DIST_SUBDIRS += jimtcl +EXTRA_DIST += jimtcl/configure.gnu +# jimtcl from 0.79 to 0.82 miss cleaning jsmn.o +DISTCLEANFILES += jimtcl/jsmn/jsmn.o endif +SUBDIRS += testing +DIST_SUBDIRS += testing + # common flags used in openocd build AM_CFLAGS = $(GCC_WARNINGS) +AM_LDFLAGS = AM_CPPFLAGS = $(HOST_CPPFLAGS)\ -I$(top_srcdir)/src \ @@ -44,7 +50,15 @@ AM_CPPFLAGS = $(HOST_CPPFLAGS)\ if INTERNAL_JIMTCL AM_CPPFLAGS += -I$(top_srcdir)/jimtcl \ -I$(top_builddir)/jimtcl +else +AM_CPPFLAGS += $(JIMTCL_CFLAGS) +endif + +if USE_GCOV +AM_CFLAGS += --coverage +AM_LDFLAGS += --coverage endif + EXTRA_DIST += \ BUGS \ HACKING \ @@ -54,16 +68,20 @@ EXTRA_DIST += \ $(EXTRA_DIST_NEWS) \ Doxyfile.in \ LICENSES/license-rules.txt \ + LICENSES/dual/CC-BY-4.0 \ LICENSES/exceptions/eCos-exception-2.0 \ LICENSES/preferred/BSD-1-Clause \ LICENSES/preferred/BSD-2-Clause \ LICENSES/preferred/BSD-2-Clause-Views \ LICENSES/preferred/BSD-3-Clause \ LICENSES/preferred/BSD-Source-Code \ + LICENSES/preferred/CC0-1.0 \ LICENSES/preferred/GFDL-1.2 \ LICENSES/preferred/gfdl-1.2.texi.readme \ LICENSES/preferred/GPL-2.0 \ + LICENSES/preferred/LGPL-2.1 \ LICENSES/preferred/MIT \ + LICENSES/stand-alone/Apache-2.0 \ LICENSES/stand-alone/GPL-3.0 \ tools/logger.pl \ tools/rlink_make_speed_table \ @@ -107,9 +125,13 @@ TCL_PATH = tcl TCL_FILES = find $(srcdir)/$(TCL_PATH) -name '*.cfg' -o -name '*.tcl' -o -name '*.txt' | \ sed -e 's,^$(srcdir)/$(TCL_PATH),,' +# The git log command below generates many empty text lines with only some space characters +# for indentation purposes, so use sed to trim all trailing whitespace. dist-hook: if test -d $(srcdir)/.git -a \( ! -e $(distdir)/ChangeLog -o -w $(distdir)/ChangeLog \) ; then \ - git --git-dir $(srcdir)/.git log | $(srcdir)/tools/git2cl/git2cl > $(distdir)/ChangeLog ; \ + git --git-dir $(srcdir)/.git log --date=short --pretty="format:%ad %aN <%aE>%n%n%w(0,4,6)* %B" \ + | sed 's/[[:space:]]*$$//' > $(distdir)/ChangeLog.tmp && \ + mv $(distdir)/ChangeLog.tmp $(distdir)/ChangeLog; \ fi for i in $$($(TCL_FILES)); do \ j="$(distdir)/$(TCL_PATH)/$$i" && \ @@ -129,9 +151,9 @@ uninstall-hook: distclean-local: rm -rf Doxyfile doxygen - rm -f $(srcdir)/jimtcl/configure.gnu + -rm -f $(srcdir)/jimtcl/configure.gnu -DISTCLEANFILES = doxygen.log +DISTCLEANFILES += doxygen.log METASOURCES = AUTO diff --git a/NEWS-0.12.0 b/NEWS-0.12.0 new file mode 100644 index 0000000000..208146a460 --- /dev/null +++ b/NEWS-0.12.0 @@ -0,0 +1,132 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * add default to adapter speed when unspecified (100 kHz) + * AM335X gpio (BeagleBones) adapter driver + * BCM2835 support for SWD + * Cadence Virtual Debug (vdebug) adapter driver + * CMSIS-DAP support for SWO and SWD multidrop + * Espressif USB JTAG Programmer adapter driver + * Remote bitbang support for Windows host + * ST-LINK add TCP server support to adapter driver + * SWD multidrop support + +Boundary Scan: + +Target Layer: + * aarch64: support watchpoints + * arm: support independent TPIU and SWO for trace + * arm adi v5: support Large Physical Address Extension + * arm adi v6: support added, for jtag and swd transport + * cortex_a: support watchpoints + * elf 64bit load support + * Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores + * semihosting: support user defined operations + * Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP + +Flash Layer: + * Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support + * GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support + * Nuvoton NPCX series support + * onsemi RSL10 support + * Raspberry Pi Pico RP2040 support + * ST BlueNRG-LPS support + * ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support + * ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support + +Board, Target, and Interface Configuration Scripts: + * Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config + * Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config + * Digilent Nexys Video board config + * Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config + * Espressif ESP32 via ESP USB Bridge generic board config + * Espressif ESP32-S2 Kaluga 1 board config + * Espressif ESP32-S2 with ESP USB Bridge board config + * Espressif ESP32-S3 example board config + * Kontron SMARC-sAL28 board config + * LambdaConcept ECPIX-5 board config + * Microchip ATSAMA5D27-SOM1-EK1 board config + * Microchip EVB-LAN9255 board config + * Microchip SAME51 Curiosity Nano board config + * NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config + * NXP RT6XX board config + * Olimex H405 board config + * Radiona ULX3S board config + * Raspberry Pi 3 and Raspberry Pi 4 model B board config + * Raspberry Pi Pico-Debug board config + * Renesas R-Car V3U Falcon board config + * ST BlueNRG-LPS steval-idb012v1 board config + * ST NUCLEO-8S208RB board config + * ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config + * ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config + * ST STM32MP13x-DK board config + * TI AM625 EVM, AM642 EVM and AM654 EVM board config + * TI J721E EVM, J721S2 EVM and J7200 EVM board config + * Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config + * Cadence Xtensa generic and Xtensa VDebug target config + * Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config + * Espressif ESP32, ESP32-S2 and ESP32-S3 target config + * Microchip ATSAMA5D2 series target config + * NanoXplore NG-Ultra SoC target config + * NXP IMX8QM target config + * NXP LS1028A, LS1046A and LS1088A target config + * NXP RT600 (Xtensa HiFi DSP) target config + * onsemi RSL10 target config + * Raspberry Pi Pico RP2040 target config + * Renesas R8A779A0 V3U target config + * Renesas RZ/Five target config + * Renesas RZ/G2 MPU family target config + * Rockchip RK3399 target config + * ST BlueNRG-LPS target config + * ST STM32MP13x target config + * TI AM625, AM654, J721E and J721S2 target config + * Ashling Opella-LD interface config + * Aspeed AST2600 linuxgpiod based interface config + * Blinkinlabs JTAG_Hat interface config + * Cadence Virtual Debug (vdebug) interface config + * Espressif ESP32-S2 Kaluga 1 board's interface config + * Espressif USB Bridge jtag interface config + * Infineon DAP miniWiggler V3 interface config + * PLS SPC5 interface config + * Tigard interface config + * Lattice MachXO3 family FPGA config + +Server Layer: + * GDB: add per-target remote protocol extensions + * GDB: more 'Z' packets support + * IPDBG JtagHost server functionality + * semihosting: I/O redirection to TCP server + * telnet: support for command's autocomplete + +RTOS: + * 'none' rtos support + * Zephyr rtos support + +Documentation: + +Build and Release: + * Add json extension to jimtcl build + * Drop dependency from libusb0 + * Drop repository repo.or.cz for submodules + * Move gerrit to https://review.openocd.org/ + * Require autoconf 2.69 or newer + * Update jep106 to revision JEP106BF.01 + * Update jimtcl to version 0.81 + * Update libjaylink to version 0.3.1 + * New configure flag '--enable-jimtcl-maintainer' for jimtcl build + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/README b/README index 34dac0b1b5..875c85de3b 100644 --- a/README +++ b/README @@ -1,5 +1,4 @@ -Welcome to OpenOCD! -=================== +# Welcome to OpenOCD! OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support including: @@ -9,10 +8,10 @@ layered architecture of JTAG interface and TAP support including: - debug target support (e.g. ARM, MIPS): single-stepping, breakpoints/watchpoints, gprof profiling, etc; - flash chip drivers (e.g. CFI, NAND, internal flash); -- embedded TCL interpreter for easy scripting. +- embedded Tcl interpreter for easy scripting. Several network interfaces are available for interacting with OpenOCD: -telnet, TCL, and GDB. The GDB server enables OpenOCD to function as a +telnet, Tcl, and GDB. The GDB server enables OpenOCD to function as a "remote target" for source-level debugging of embedded systems using the GNU GDB program (and the others who talk GDB protocol, e.g. IDA Pro). @@ -26,33 +25,33 @@ This README file contains an overview of the following topics: - packaging tips. -============================ -Quickstart for the impatient -============================ +# Quickstart for the impatient If you have a popular board then just start OpenOCD with its config, e.g.: - openocd -f board/stm32f4discovery.cfg + openocd -f board/stm32f4discovery.cfg If you are connecting a particular adapter with some specific target, you need to source both the jtag interface and the target configs, e.g.: - openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \ - -f target/ti_calypso.cfg +``` +openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \ + -f target/ti_calypso.cfg +``` - openocd -f interface/stlink.cfg -c "transport select hla_swd" \ - -f target/stm32l0.cfg +``` +openocd -f interface/stlink.cfg -c "transport select swd" \ + -f target/stm32l0.cfg +``` After OpenOCD startup, connect GDB with - (gdb) target extended-remote localhost:3333 + (gdb) target extended-remote localhost:3333 -===================== -OpenOCD Documentation -===================== +# OpenOCD Documentation In addition to the in-tree documentation, the latest manuals may be viewed online at the following URLs: @@ -71,78 +70,75 @@ by subscribing to the OpenOCD developer mailing list: openocd-devel@lists.sourceforge.net -Building the OpenOCD Documentation ----------------------------------- +## Building the OpenOCD Documentation By default the OpenOCD build process prepares documentation in the -"Info format" and installs it the standard way, so that "info openocd" +"Info format" and installs it the standard way, so that `info openocd` can access it. Additionally, the OpenOCD User's Guide can be produced in the following different formats: - # If PDFVIEWER is set, this creates and views the PDF User Guide. - make pdf && ${PDFVIEWER} doc/openocd.pdf +If `PDFVIEWER` is set, this creates and views the PDF User Guide. - # If HTMLVIEWER is set, this creates and views the HTML User Guide. - make html && ${HTMLVIEWER} doc/openocd.html/index.html + make pdf && ${PDFVIEWER} doc/openocd.pdf + +If `HTMLVIEWER` is set, this creates and views the HTML User Guide. + + make html && ${HTMLVIEWER} doc/openocd.html/index.html The OpenOCD Developer Manual contains information about the internal architecture and other details about the code: - # NB! make sure doxygen is installed, type doxygen --version - make doxygen && ${HTMLVIEWER} doxygen/index.html +Note: make sure doxygen is installed, type doxygen --version + + make doxygen && ${HTMLVIEWER} doxygen/index.html -================== -Supported hardware -================== +# Supported hardware -JTAG adapters -------------- +## JTAG adapters -AICE, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835, -Bus Blaster, Buspirate, Cadence DPI, Chameleon, CMSIS-DAP, Cortino, -Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H, -embedded projects, eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2, +AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835, +Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP, +Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H, +embedded projects, Espressif USB JTAG Programmer, +eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2, FTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey, JTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick, Mellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO, OOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee, Remote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits, ST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick, -sysfsgpio, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster, +sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster, USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe, Xverve. -Debug targets -------------- +## Debug targets ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M), FA526, Feroceon/Dragonite, XScale. ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64), -Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8. +ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8, +Xtensa. -Flash drivers -------------- +## Flash drivers ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI, DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI, -i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx, +GD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx, LPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro, -NUC910, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6, Renesas RPC HF and SH QSPI, +NUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6, +Raspberry RP2040, Renesas RPC HF and SH QSPI, S3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32, STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050, TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF, XMC1xxx, XMC4xxx. -================== -Installing OpenOCD -================== +# Installing OpenOCD -A Note to OpenOCD Users ------------------------ +## A Note to OpenOCD Users If you would rather be working "with" OpenOCD rather than "on" it, your operating system or JTAG interface supplier may provide binaries for @@ -161,8 +157,7 @@ Users of these binary versions of OpenOCD must contact their Packager to ask for support or newer versions of the binaries; the OpenOCD developers do not support packages directly. -A Note to OpenOCD Packagers ---------------------------- +## A Note to OpenOCD Packagers You are a PACKAGER of OpenOCD if you: @@ -189,11 +184,9 @@ suggestions: - Use "ftdi" interface adapter driver for the FTDI-based devices. -================ -Building OpenOCD -================ +# Building OpenOCD -The INSTALL file contains generic instructions for running 'configure' +The INSTALL file contains generic instructions for running `configure` and compiling the OpenOCD source code. That file is provided by default for all GNU autotools packages. If you are not familiar with the GNU autotools, then you should read those instructions first. @@ -201,8 +194,7 @@ the GNU autotools, then you should read those instructions first. The remainder of this document tries to provide some instructions for those looking for a quick-install. -OpenOCD Dependencies --------------------- +## OpenOCD Dependencies GCC or Clang is currently required to build OpenOCD. The developers have begun to enforce strict code warnings (-Wall, -Werror, -Wextra, @@ -216,7 +208,8 @@ You'll also need: - make - libtool -- pkg-config >= 0.23 (or compatible) +- pkg-config >= 0.23 or pkgconf +- libjim >= 0.79 Additionally, for building from git: @@ -224,17 +217,27 @@ Additionally, for building from git: - automake >= 1.14 - texinfo >= 5.0 -USB-based adapters depend on libusb-1.0. A compatible implementation, such as -FreeBSD's, additionally needs the corresponding .pc files. +Optional USB-based adapter drivers need libusb-1.0. -USB-Blaster, ASIX Presto and OpenJTAG interface adapter +Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter drivers need: - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php -CMSIS-DAP support needs HIDAPI library. +Optional CMSIS-DAP adapter driver needs HIDAPI library. + +Optional linuxgpiod adapter driver needs libgpiod library. + +Optional J-Link adapter driver needs libjaylink library. -Permissions delegation ----------------------- +Optional ARM disassembly needs capstone library. + +Optional development script checkpatch needs: + +- perl +- python +- python-ply + +## Permissions delegation Running OpenOCD with root/administrative permissions is strongly discouraged for security reasons. @@ -251,89 +254,81 @@ For parport adapters on Windows you need to run install_giveio.bat (it's also possible to use "ioperm" with Cygwin instead) to give ordinary users permissions for accessing the "LPT" registers directly. -Compiling OpenOCD ------------------ +## Compiling OpenOCD To build OpenOCD, use the following sequence of commands: - ./bootstrap (when building from the git repository) - ./configure [options] - make - sudo make install + ./bootstrap + ./configure [options] + make + sudo make install -The 'configure' step generates the Makefiles required to build +The `bootstrap` command is only necessary when building from the Git repository. The `configure` step generates the Makefiles required to build OpenOCD, usually with one or more options provided to it. The first 'make' step will build OpenOCD and place the final executable in -'./src/'. The final (optional) step, ``make install'', places all of +'./src/'. The final (optional) step, `make install`, places all of the files in the required location. -To see the list of all the supported options, run - ./configure --help +To see the list of all the supported options, run `./configure --help` -Cross-compiling Options ------------------------ +## Cross-compiling Options Cross-compiling is supported the standard autotools way, you just need to specify the cross-compiling target triplet in the --host option, e.g. for cross-building for Windows 32-bit with MinGW on Debian: - ./configure --host=i686-w64-mingw32 [options] + ./configure --host=i686-w64-mingw32 [options] To make pkg-config work nicely for cross-compiling, you might need an additional wrapper script as described at - https://autotools.io/pkgconfig/cross-compiling.html + https://autotools.io/pkgconfig/cross-compiling.html This is needed to tell pkg-config where to look for the target libraries that OpenOCD depends on. Alternatively, you can specify -*_CFLAGS and *_LIBS environment variables directly, see "./configure ---help" for the details. +`*_CFLAGS` and `*_LIBS` environment variables directly, see `./configure +--help` for the details. For a more or less complete script that does all this for you, see - contrib/cross-build.sh + contrib/cross-build.sh -Parallel Port Dongles ---------------------- +## Parallel Port Dongles If you want to access the parallel port using the PPDEV interface you -have to specify both --enable-parport AND --enable-parport-ppdev, since +have to specify both `--enable-parport` and `--enable-parport-ppdev`, since the later option is an option to the parport driver. -The same is true for the --enable-parport-giveio option, you have to -use both the --enable-parport AND the --enable-parport-giveio option +The same is true for the `--enable-parport-giveio` option, you have to +use both the `--enable-parport` and the `--enable-parport-giveio` option if you want to use giveio instead of ioperm parallel port access method. -========================== -Obtaining OpenOCD From GIT -========================== +# Obtaining OpenOCD From GIT You can download the current GIT version with a GIT client of your choice from the main repository: - git://git.code.sf.net/p/openocd/code + git://git.code.sf.net/p/openocd/code You may prefer to use a mirror: - http://repo.or.cz/r/openocd.git - git://repo.or.cz/openocd.git + http://repo.or.cz/r/openocd.git + git://repo.or.cz/openocd.git Using the GIT command line client, you might use the following command to set up a local copy of the current repository (make sure there is no directory called "openocd" in the current directory): - git clone git://git.code.sf.net/p/openocd/code openocd - -Then you can update that at your convenience using + git clone git://git.code.sf.net/p/openocd/code openocd - git pull +Then you can update that at your convenience using `git pull`. There is also a gitweb interface, which you can use either to browse the repository or to download arbitrary snapshots using HTTP: - http://repo.or.cz/w/openocd.git + http://repo.or.cz/w/openocd.git Snapshots are compressed tarballs of the source tree, about 1.3 MBytes each at this writing. diff --git a/README.Windows b/README.Windows index 7326a356ca..64bf5c0c6f 100644 --- a/README.Windows +++ b/README.Windows @@ -52,5 +52,5 @@ port depending on which application to use. For more information, see: - http://msdn.microsoft.com/en-us/library/windows/hardware/jj649944(v=vs.85).aspx + https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-device-specific-registry-settings http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm diff --git a/TODO b/TODO index ebb6c99808..803692d58e 100644 --- a/TODO +++ b/TODO @@ -12,14 +12,14 @@ may have evolved an idea since it was added here. Feel free to send patches to add or clarify items on this list, too. -@section thelisttcl TCL +@section thelisttcl Tcl -This section provides possible things to improve with OpenOCD's TCL support. +This section provides possible things to improve with OpenOCD's Tcl support. - Fix problem with incorrect line numbers reported for a syntax error in a reset init event. -- organize the TCL configurations: +- organize the Tcl configurations: - provide more directory structure for boards/targets? - factor configurations into layers (encapsulation and re-use) @@ -27,15 +27,15 @@ This section provides possible things to improve with OpenOCD's TCL support. parameters. Currently variables assigned through one such parameter command/script are unset before the next one is invoked. -- Isolate all TCL command support: +- Isolate all Tcl command support: - Pure C CLI implementations using --disable-builtin-tcl. - Allow developers to build new dongles using OpenOCD's JTAG core. - At first, provide only low-level JTAG support; target layer and above rely heavily on scripting event mechanisms. - - Allow full TCL support? add --with-tcl=/path/to/installed/tcl - - Move TCL support out of foo.[ch] and into foo_tcl.[ch] (other ideas?) + - Allow full Tcl support? add --with-tcl=/path/to/installed/tcl + - Move Tcl support out of foo.[ch] and into foo_tcl.[ch] (other ideas?) - See src/jtag/core.c and src/jtag/tcl.c for an example. - - allow some of these TCL command modules to be dynamically loadable? + - allow some of these Tcl command modules to be dynamically loadable? @section thelistadapter Adapter @@ -60,8 +60,6 @@ changes pending in gerrit. to replicate it in the drivers, apart in case the driver sets TRST independently - add .hla_ops to "adapter" -- HLA is a API level (.hla_ops). Transport should simply be {jtag,swd}, - not {hla_jtag,hla_swd}. @subsection thelistadapterjtagcore JTAG Core @@ -77,7 +75,7 @@ directly in minidriver API for better embedded host performance. The following tasks have been suggested for adding new core JTAG support: -- Improve autodetection of TAPs by supporting tcl escape procedures that +- Improve autodetection of TAPs by supporting Tcl escape procedures that can configure discovered TAPs based on IDCODE value ... they could: - Remove guessing for irlen - Allow non-default irmask/ircapture values @@ -135,7 +133,7 @@ TCP/IP packets handled by the server. - add BSDL support? A few possible options for the above: - -# Fake a TCL equivalent? + -# Fake a Tcl equivalent? -# Integrate an existing library? -# Write a new C implementation a la Jim? @@ -202,8 +200,6 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html - MC1322x support (JW/DE?) - integrate and test support from JW (and DE?) - get working with a known good interface (i.e. not today's jlink) -- AT91SAM92xx: - - improvements for unknown-board-atmel-at91sam9260.cfg (RD) - STR9x: (ZW) - improvements to str912.cfg to be more general purpose - AVR: (SQ) diff --git a/bootstrap b/bootstrap index cf6167fff6..0ee26d4ed3 100755 --- a/bootstrap +++ b/bootstrap @@ -3,8 +3,8 @@ # Run the autotools bootstrap sequence to create the configure script -# Abort execution on error -set -e +set -e # Abort execution on error. +set -u # Abort if you reference an undefined variable. if which libtoolize > /dev/null; then libtoolize="libtoolize" @@ -15,13 +15,23 @@ else exit 1 fi -if [ "$1" = "nosubmodule" ]; then - SKIP_SUBMODULE=1 -elif [ -n "$1" ]; then - echo "$0: Illegal argument $1" - echo "USAGE: $0 [nosubmodule]" - exit 1 -fi +WITH_SUBMODULES=0 + +case "$#" in + 0) ;; + 1) if [ "$1" = "with-submodules" ]; then + WITH_SUBMODULES=1 + elif [ "$1" = "nosubmodule" ]; then + WITH_SUBMODULES=0 + elif [ -n "$1" ]; then + echo "$0: Illegal argument $1" >&2 + echo "USAGE: $0 [with-submodules]" >&2 + exit 1 + fi;; + *) echo "$0: Wrong number of command-line arguments." >&2 + echo "USAGE: $0 [with-submodules]" >&2 + exit 1;; +esac # bootstrap the autotools ( @@ -34,12 +44,12 @@ autoheader --warnings=all automake --warnings=all --gnu --add-missing --copy ) -if [ -n "$SKIP_SUBMODULE" ]; then - echo "Skipping submodule setup" -else +if [ "$WITH_SUBMODULES" -ne 0 ]; then echo "Setting up submodules" - git submodule init - git submodule update + git submodule sync + git submodule update --init +else + echo "Skipping submodule setup" fi if [ -x src/jtag/drivers/libjaylink/autogen.sh ]; then diff --git a/config_subdir.m4 b/config_subdir.m4 index 2be590e44a..5549c760af 100644 --- a/config_subdir.m4 +++ b/config_subdir.m4 @@ -7,6 +7,6 @@ AC_DEFUN([AX_CONFIG_SUBDIR_OPTION], AC_CONFIG_SUBDIRS([$1]) m4_ifblank([$2], [rm -f $srcdir/$1/configure.gnu], -[echo -e '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"' > "$srcdir/$1/configure.gnu" +[printf '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"\n' > "$srcdir/$1/configure.gnu" ]) ]) diff --git a/configure.ac b/configure.ac index 7d0cc24698..453cbcfb5a 100644 --- a/configure.ac +++ b/configure.ac @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later AC_PREREQ([2.69]) -AC_INIT([openocd], [0.11.0+dev], +AC_INIT([openocd], [0.12.0+dev], [OpenOCD Mailing List ]) AC_CONFIG_SRCDIR([src/openocd.c]) AC_CONFIG_AUX_DIR([build-aux]) @@ -24,7 +24,6 @@ AC_LANG([C]) AC_PROG_CC # autoconf 2.70 obsoletes AC_PROG_CC_C99 and includes it in AC_PROG_CC m4_version_prereq([2.70],[],[AC_PROG_CC_C99]) -AM_PROG_CC_C_O AC_PROG_RANLIB # If macro PKG_PROG_PKG_CONFIG is not available, Autoconf generates a misleading error message, @@ -52,15 +51,22 @@ AC_SEARCH_LIBS([openpty], [util]) AC_CHECK_HEADERS([sys/socket.h]) AC_CHECK_HEADERS([elf.h]) -AC_EGREP_HEADER(Elf64_Ehdr, [elf.h], [ - AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type `Elf64_Ehdr'.]) -]) -AC_CHECK_HEADERS([dirent.h]) + +AC_CHECK_TYPE([Elf64_Ehdr], + AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type 'Elf64_Ehdr'.]), + [], [[#include ]]) + +AC_MSG_CHECKING([for glibc]) +AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include ]], [[int v = __GLIBC__;return 0;]])], + [have_glibc=yes], [have_glibc=no]) +AC_MSG_RESULT($have_glibc) + AC_CHECK_HEADERS([fcntl.h]) +AC_CHECK_HEADERS([linux/pci.h]) +AC_CHECK_HEADERS([linux/spi/spidev.h]) AC_CHECK_HEADERS([malloc.h]) AC_CHECK_HEADERS([netdb.h]) AC_CHECK_HEADERS([poll.h]) -AC_CHECK_HEADERS([pthread.h]) AC_CHECK_HEADERS([strings.h]) AC_CHECK_HEADERS([sys/ioctl.h]) AC_CHECK_HEADERS([sys/param.h]) @@ -70,7 +76,7 @@ AC_CHECK_HEADERS([sys/sysctl.h]) AC_CHECK_HEADERS([sys/time.h]) AC_CHECK_HEADERS([sys/types.h]) AC_CHECK_HEADERS([unistd.h]) -AC_CHECK_HEADERS([arpa/inet.h ifaddrs.h netinet/in.h netinet/tcp.h net/if.h], [], [], [dnl +AC_CHECK_HEADERS([arpa/inet.h netinet/in.h netinet/tcp.h], [], [], [dnl #include #ifdef STDC_HEADERS # include @@ -94,7 +100,6 @@ AC_CHECK_FUNCS([strndup]) AC_CHECK_FUNCS([strnlen]) AC_CHECK_FUNCS([gettimeofday]) AC_CHECK_FUNCS([usleep]) -AC_CHECK_FUNCS([vasprintf]) AC_CHECK_FUNCS([realpath]) # guess-rev.sh only exists in the repository, not in the released archives @@ -107,12 +112,18 @@ AS_IF([test -x "$srcdir/guess-rev.sh"], [ AC_MSG_RESULT([$build_release]) # Adapter drivers -# 1st column -- configure option -# 2nd column -- description -# 3rd column -- symbol used for both config.h and automake +# 1st column -- Basename for the configure option generated with AC_ARG_ENABLE. +# For example, "buspirate" generates options "--enable-buspirate[=yes/no]" +# and "--disable-buspirate". +# 2nd column -- Description for the configure option. For example, "Bus Pirate" +# generates "Enable building support for the Bus Pirate (default is auto)". +# 3rd column -- Basename for the config.h and Automake symbols. +# For example, basename "BUS_PIRATE" generates "BUILD_BUS_PIRATE" with AC_DEFINE +# for config.h and "BUS_PIRATE" with AM_CONDITIONAL for Automake. m4_define([ADAPTER_ARG], [m4_argn([1], $1)]) m4_define([ADAPTER_DESC], [m4_argn([2], $1)]) m4_define([ADAPTER_SYM], [m4_argn([3], $1)]) +# AC_ARG_ENABLE uses prefix "enable_" to name the corresponding option variable. m4_define([ADAPTER_VAR], [enable_[]ADAPTER_ARG($1)]) m4_define([ADAPTER_OPT], [m4_translit(ADAPTER_ARG($1), [_], [-])]) @@ -121,23 +132,24 @@ m4_define([USB1_ADAPTERS], [[stlink], [ST-Link Programmer], [HLADAPTER_STLINK]], [[ti_icdi], [TI ICDI JTAG Programmer], [HLADAPTER_ICDI]], [[ulink], [Keil ULINK JTAG Programmer], [ULINK]], + [[angie], [ANGIE Adapter], [ANGIE]], [[usb_blaster_2], [Altera USB-Blaster II Compatible], [USB_BLASTER_2]], [[ft232r], [Bitbang mode of FT232R based devices], [FT232R]], [[vsllink], [Versaloon-Link JTAG Programmer], [VSLLINK]], [[xds110], [TI XDS110 Debug Probe], [XDS110]], - [[cmsis_dap_v2], [CMSIS-DAP v2 Compliant Debugger], [CMSIS_DAP_USB]], [[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]], [[opendous], [eStick/opendous JTAG Programmer], [OPENDOUS]], [[armjtagew], [Olimex ARM-JTAG-EW Programmer], [ARMJTAGEW]], [[rlink], [Raisonance RLink JTAG Programmer], [RLINK]], [[usbprog], [USBProg JTAG Programmer], [USBPROG]], - [[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]]) + [[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]], + [[cmsis_dap_v2], [CMSIS-DAP v2 compliant dongle (USB bulk)], [CMSIS_DAP_USB]]]) -m4_define([DEPRECATED_USB1_ADAPTERS], - [[[aice], [Andes JTAG Programmer (deprecated)], [AICE]]]) +# Please keep cmsis_dap_v2 the last in USB1_ADAPTERS +# and cmsis_dap the first in HIDAPI_ADAPTERS m4_define([HIDAPI_ADAPTERS], - [[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]], + [[[cmsis_dap], [CMSIS-DAP v1 compliant dongle (HID)], [CMSIS_DAP_HID]], [[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]]) m4_define([HIDAPI_USB1_ADAPTERS], @@ -153,6 +165,15 @@ m4_define([LIBFTDI_USB1_ADAPTERS], m4_define([LIBGPIOD_ADAPTERS], [[[linuxgpiod], [Linux GPIO bitbang through libgpiod], [LINUXGPIOD]]]) +m4_define([DMEM_ADAPTER], + [[[dmem], [CoreSight Direct Memory], [DMEM]]]) + +m4_define([SYSFSGPIO_ADAPTER], + [[[sysfsgpio], [Linux GPIO bitbang through sysfs], [SYSFSGPIO]]]) + +m4_define([REMOTE_BITBANG_ADAPTER], + [[[remote_bitbang], [Remote Bitbang driver], [REMOTE_BITBANG]]]) + m4_define([LIBJAYLINK_ADAPTERS], [[[jlink], [SEGGER J-Link Programmer], [JLINK]]]) @@ -162,9 +183,41 @@ m4_define([PCIE_ADAPTERS], m4_define([SERIAL_PORT_ADAPTERS], [[[buspirate], [Bus Pirate], [BUS_PIRATE]]]) +m4_define([LINUXSPIDEV_ADAPTER], + [[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]]) +m4_define([VDEBUG_ADAPTER], + [[[vdebug], [Cadence Virtual Debug Interface], [VDEBUG]]]) + +m4_define([JTAG_DPI_ADAPTER], + [[[jtag_dpi], [JTAG DPI Adapter], [JTAG_DPI]]]) + +m4_define([JTAG_VPI_ADAPTER], + [[[jtag_vpi], [JTAG VPI Adapter], [JTAG_VPI]]]) + +m4_define([RSHIM_ADAPTER], + [[[rshim], [BlueField SoC via rshim], [RSHIM]]]) + +m4_define([AMTJTAGACCEL_ADAPTER], + [[[amtjtagaccel], [Amontec JTAG-Accelerator driver], [AMTJTAGACCEL]]]) + +m4_define([HOST_ARM_BITBANG_ADAPTERS], + [[[ep93xx], [Bitbanging on EP93xx-based SBCs], [EP93XX]], + [[at91rm9200], [Bitbanging on AT91RM9200-based SBCs], [AT91RM9200]]]) + +m4_define([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS], + [[[bcm2835gpio], [Bitbanging on BCM2835 (as found in Raspberry Pi)], [BCM2835GPIO]], + [[imx_gpio], [Bitbanging on NXP IMX processors], [IMX_GPIO]], + [[am335xgpio], [Bitbanging on AM335x (as found in Beaglebones)], [AM335XGPIO]]]) + +m4_define([DUMMY_ADAPTER], + [[[dummy], [Dummy Adapter], [DUMMY]]]) + m4_define([OPTIONAL_LIBRARIES], [[[capstone], [Use Capstone disassembly framework], []]]) +m4_define([COVERAGE], + [[[gcov], [Collect coverage using gcov], []]]) + AC_ARG_ENABLE([doxygen-html], AS_HELP_STRING([--disable-doxygen-html], [Disable building Doxygen manual as HTML.]), @@ -193,6 +246,19 @@ AC_ARG_ENABLE([werror], AS_HELP_STRING([--disable-werror], [Do not treat warnings as errors]), [gcc_werror=$enableval], [gcc_werror=$gcc_warnings]) +AC_ARG_ENABLE([gcov], + AS_HELP_STRING([--enable-gcov], [Enable runtime coverage collection via gcov]), + [enable_gcov=$enableval], [enable_gcov=no]) + +AS_IF([test "x$enable_gcov" = "xyes"], [ + AC_DEFINE([USE_GCOV], [1], [1 to enable coverage collection using gcov.]) + dnl When collecting coverage, disable optimizations. + dnl This overrides the "-O2" that autoconf uses by default: + CFLAGS+=" -O0" +], [ + AC_DEFINE([USE_GCOV], [0], [0 to leave coverage collection disabled.]) +]) + # set default verbose options, overridden by following options debug_usb_io=no debug_usb_comms=no @@ -235,24 +301,20 @@ AC_ARG_ENABLE([malloc_logging], AC_MSG_CHECKING([whether to enable malloc free space logging]); AC_MSG_RESULT([$debug_malloc]) -AS_IF([test "x$debug_malloc" = "xyes"], [ +AS_IF([test "x$debug_malloc" = "xyes" -a "x$have_glibc" = "xyes"], [ AC_DEFINE([_DEBUG_FREE_SPACE_],[1], [Include malloc free space in logging]) ]) -AC_ARG_ENABLE([dummy], - AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]), - [build_dummy=$enableval], [build_dummy=no]) - -AC_ARG_ENABLE([rshim], - AS_HELP_STRING([--enable-rshim], [Enable building the rshim driver]), - [build_rshim=$enableval], [build_rshim=no]) - m4_define([AC_ARG_ADAPTERS], [ - m4_foreach([adapter], [$1], - [AC_ARG_ENABLE(ADAPTER_OPT([adapter]), - AS_HELP_STRING([--enable-ADAPTER_OPT([adapter])], - [Enable building support for the ]ADAPTER_DESC([adapter])[ (default is $2)]), - [], [ADAPTER_VAR([adapter])=$2]) + m4_foreach([adapterTuple], [$1], + [AC_ARG_ENABLE(ADAPTER_OPT([adapterTuple]), + AS_HELP_STRING([--enable-ADAPTER_OPT([adapterTuple])[[[=yes/no/auto]]]], + [Enable building support for the ]ADAPTER_DESC([adapterTuple])[ (default is $2)]), + [case "${enableval}" in + yes|no|auto) ;; + *) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapterTuple]) has invalid value "${enableval}".]) ;; + esac], + [ADAPTER_VAR([adapterTuple])=$2]) ]) ]) @@ -261,13 +323,35 @@ AC_ARG_ADAPTERS([ HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS, - LIBFTDI_USB1_ADAPTERS + LIBFTDI_USB1_ADAPTERS, LIBGPIOD_ADAPTERS, + DMEM_ADAPTER, + SYSFSGPIO_ADAPTER, + REMOTE_BITBANG_ADAPTER, + LINUXSPIDEV_ADAPTER, SERIAL_PORT_ADAPTERS, + DUMMY_ADAPTER, + VDEBUG_ADAPTER, + JTAG_DPI_ADAPTER, + JTAG_VPI_ADAPTER, + RSHIM_ADAPTER, + PCIE_ADAPTERS, LIBJAYLINK_ADAPTERS ],[auto]) -AC_ARG_ADAPTERS([DEPRECATED_USB1_ADAPTERS],[no]) +AC_ARG_ADAPTERS([ + AMTJTAGACCEL_ADAPTER + ],[no]) + +# The following adapters use bitbanging and can actually be built on all architectures, +# which is useful to verify that they still build fine. +# We could enable them automatically only on the architectures where they actually occur: +# HOST_ARM_BITBANG_ADAPTERS: when ${host_cpu} matches arm* +# HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS: when ${host_cpu} matches arm*|aarch64 +# However, conditionally changing the meaning of 'auto' requires +# a more flexible logic around. +AC_ARG_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS],[no]) +AC_ARG_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],[no]) AC_ARG_ENABLE([parport], AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]), @@ -283,106 +367,44 @@ AC_ARG_ENABLE([parport_giveio], [Enable use of giveio for parport (for CygWin only)]), [parport_use_giveio=$enableval], [parport_use_giveio=]) -AC_ARG_ENABLE([jtag_vpi], - AS_HELP_STRING([--enable-jtag_vpi], [Enable building support for JTAG VPI]), - [build_jtag_vpi=$enableval], [build_jtag_vpi=no]) - -AC_ARG_ENABLE([vdebug], - AS_HELP_STRING([--enable-vdebug], [Enable building support for Cadence Virtual Debug Interface]), - [build_vdebug=$enableval], [build_vdebug=no]) - -AC_ARG_ENABLE([jtag_dpi], - AS_HELP_STRING([--enable-jtag_dpi], [Enable building support for JTAG DPI]), - [build_jtag_dpi=$enableval], [build_jtag_dpi=no]) - -AC_ARG_ENABLE([amtjtagaccel], - AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]), - [build_amtjtagaccel=$enableval], [build_amtjtagaccel=no]) - -AS_CASE(["${host_cpu}"], - [arm*|aarch64], [ - AC_ARG_ENABLE([bcm2835gpio], - AS_HELP_STRING([--enable-bcm2835gpio], [Enable building support for bitbanging on BCM2835 (as found in Raspberry Pi)]), - [build_bcm2835gpio=$enableval], [build_bcm2835gpio=no]) - AC_ARG_ENABLE([imx_gpio], - AS_HELP_STRING([--enable-imx_gpio], [Enable building support for bitbanging on NXP IMX processors]), - [build_imx_gpio=$enableval], [build_imx_gpio=no]) - AC_ARG_ENABLE([am335xgpio], - AS_HELP_STRING([--enable-am335xgpio], [Enable building support for bitbanging on AM335x (as found in Beaglebones)]), - [build_am335xgpio=$enableval], [build_am335xgpio=no]) - ], - [ - build_bcm2835gpio=no - build_imx_gpio=no - build_am335xgpio=no -]) - -AS_CASE(["${host_cpu}"], - [arm*], [ - AC_ARG_ENABLE([ep93xx], - AS_HELP_STRING([--enable-ep93xx], [Enable building support for EP93xx based SBCs]), - [build_ep93xx=$enableval], [build_ep93xx=no]) - - AC_ARG_ENABLE([at91rm9200], - AS_HELP_STRING([--enable-at91rm9200], [Enable building support for AT91RM9200 based SBCs]), - [build_at91rm9200=$enableval], [build_at91rm9200=no]) - ], - [ - build_ep93xx=no - build_at91rm9200=no -]) - AC_ARG_ENABLE([gw16012], AS_HELP_STRING([--enable-gw16012], [Enable building support for the Gateworks GW16012 JTAG Programmer]), [build_gw16012=$enableval], [build_gw16012=no]) -AC_ARG_ENABLE([sysfsgpio], - AS_HELP_STRING([--enable-sysfsgpio], [Enable building support for programming driven via sysfs gpios.]), - [build_sysfsgpio=$enableval], [build_sysfsgpio=no]) - -AC_ARG_ENABLE([xlnx_pcie_xvc], - AS_HELP_STRING([--enable-xlnx-pcie-xvc], [Enable building support for Xilinx XVC/PCIe.]), - [build_xlnx_pcie_xvc=$enableval], [build_xlnx_pcie_xvc=no]) +can_build_rshim=no AS_CASE([$host_os], - [linux*], [], + [linux*], [ + is_linux=yes + can_build_rshim=yes + ], [ - AS_IF([test "x$build_sysfsgpio" = "xyes"], [ - AC_MSG_ERROR([sysfsgpio is only available on linux]) - ]) - - AS_IF([test "x$enable_linuxgpiod" = "xyes"], [ - AC_MSG_ERROR([linuxgpiod is only available on linux]) - ]) - - AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [ - AC_MSG_ERROR([xlnx_pcie_xvc is only available on linux]) - ]) - - AS_CASE([$host_os], [freebsd*], [], + AS_CASE([$host_os], [freebsd*], [ + can_build_rshim=yes + ], [ - AS_IF([test "x$build_rshim" = "xyes"], [ - AC_MSG_ERROR([build_rshim is only available on linux or freebsd]) + AS_IF([test "x$enable_rshim" = "xyes"], [ + AC_MSG_ERROR([rshim is only available on linux or freebsd]) ]) ]) + + AS_IF([test "x$build_dmem" = "xyes"], [ + AC_MSG_ERROR([dmem is only available on linux]) + ]) ]) AC_ARG_ENABLE([internal-jimtcl], - AS_HELP_STRING([--disable-internal-jimtcl], [Disable building internal jimtcl]), - [use_internal_jimtcl=$enableval], [use_internal_jimtcl=yes]) + AS_HELP_STRING([--enable-internal-jimtcl], [Enable building internal jimtcl (deprecated)]), + [use_internal_jimtcl=$enableval], [use_internal_jimtcl=no]) AC_ARG_ENABLE([jimtcl-maintainer], AS_HELP_STRING([--enable-jimtcl-maintainer], [Enable maintainer mode when building internal jimtcl]), [use_internal_jimtcl_maintainer=$enableval], [use_internal_jimtcl_maintainer=no]) AC_ARG_ENABLE([internal-libjaylink], - AS_HELP_STRING([--disable-internal-libjaylink], - [Disable building internal libjaylink]), - [use_internal_libjaylink=$enableval], [use_internal_libjaylink=yes]) - -AC_ARG_ENABLE([remote-bitbang], - AS_HELP_STRING([--enable-remote-bitbang], [Enable building support for the Remote Bitbang jtag driver]), - [build_remote_bitbang=$enableval], [build_remote_bitbang=no]) + AS_HELP_STRING([--enable-internal-libjaylink], + [Enable building internal libjaylink]), + [use_internal_libjaylink=$enableval], [use_internal_libjaylink=no]) AS_CASE(["${host_cpu}"], [i?86|x86*], [], @@ -393,8 +415,10 @@ AS_CASE(["${host_cpu}"], parport_use_ppdev=yes ]) -AS_CASE([$host], - [*-cygwin*], [ +can_build_buspirate=yes + +AS_CASE([$host_os], + [cygwin*], [ is_win32=yes parport_use_ppdev=no @@ -414,7 +438,7 @@ AS_CASE([$host], ]) ]) ], - [*-mingw* | *-msys*], [ + [mingw* | msys*], [ is_mingw=yes is_win32=yes parport_use_ppdev=no @@ -424,16 +448,16 @@ AS_CASE([$host], ]) parport_use_giveio=yes - AS_IF([test "x$enable_buspirate" = "xyes"], [ - AC_MSG_ERROR([buspirate currently not supported by MinGW32 hosts]) + AS_IF([test "x$ADAPTER_VAR([buspirate])" = "xyes"], [ + AC_MSG_ERROR([The Bus Pirate adapter is currently not supported by MinGW32 hosts.]) ]) # In case enable_buspirate=auto, make sure it will not be built. - enable_buspirate=no + can_build_buspirate=no - AC_SUBST([HOST_CPPFLAGS], [-D__USE_MINGW_ANSI_STDIO]) + AC_SUBST([HOST_CPPFLAGS], ["-D__USE_MINGW_ANSI_STDIO -DFD_SETSIZE=128"]) ], - [*darwin*], [ + [darwin*], [ is_darwin=yes AS_IF([test "x$parport_use_giveio" = "xyes"], [ @@ -479,52 +503,8 @@ AS_IF([test "x$build_parport" = "xyes"], [ AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.]) ]) -AS_IF([test "x$build_rshim" = "xyes"], [ - AC_DEFINE([BUILD_RSHIM], [1], [1 if you want to debug BlueField SoC via rshim.]) -], [ - AC_DEFINE([BUILD_RSHIM], [0], [0 if you don't want to debug BlueField SoC via rshim.]) -]) - -AS_IF([test "x$build_dummy" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_DUMMY], [1], [1 if you want dummy driver.]) -], [ - AC_DEFINE([BUILD_DUMMY], [0], [0 if you don't want dummy driver.]) -]) - -AS_IF([test "x$build_ep93xx" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_EP93XX], [1], [1 if you want ep93xx.]) -], [ - AC_DEFINE([BUILD_EP93XX], [0], [0 if you don't want ep93xx.]) -]) - -AS_IF([test "x$build_at91rm9200" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_AT91RM9200], [1], [1 if you want at91rm9200.]) -], [ - AC_DEFINE([BUILD_AT91RM9200], [0], [0 if you don't want at91rm9200.]) -]) - -AS_IF([test "x$build_bcm2835gpio" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_BCM2835GPIO], [1], [1 if you want bcm2835gpio.]) -], [ - AC_DEFINE([BUILD_BCM2835GPIO], [0], [0 if you don't want bcm2835gpio.]) -]) - -AS_IF([test "x$build_imx_gpio" = "xyes"], [ +AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [ build_bitbang=yes - AC_DEFINE([BUILD_IMX_GPIO], [1], [1 if you want imx_gpio.]) -], [ - AC_DEFINE([BUILD_IMX_GPIO], [0], [0 if you don't want imx_gpio.]) -]) - -AS_IF([test "x$build_am335xgpio" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_AM335XGPIO], [1], [1 if you want am335xgpio.]) -], [ - AC_DEFINE([BUILD_AM335XGPIO], [0], [0 if you don't want am335xgpio.]) ]) AS_IF([test "x$parport_use_ppdev" = "xyes"], [ @@ -539,75 +519,32 @@ AS_IF([test "x$parport_use_giveio" = "xyes"], [ AC_DEFINE([PARPORT_USE_GIVEIO], [0], [0 if you don't want parport to use giveio.]) ]) -AS_IF([test "x$build_jtag_vpi" = "xyes"], [ - AC_DEFINE([BUILD_JTAG_VPI], [1], [1 if you want JTAG VPI.]) -], [ - AC_DEFINE([BUILD_JTAG_VPI], [0], [0 if you don't want JTAG VPI.]) -]) - -AS_IF([test "x$build_vdebug" = "xyes"], [ - AC_DEFINE([BUILD_VDEBUG], [1], [1 if you want Cadence vdebug interface.]) -], [ - AC_DEFINE([BUILD_VDEBUG], [0], [0 if you don't want Cadence vdebug interface.]) -]) - -AS_IF([test "x$build_jtag_dpi" = "xyes"], [ - AC_DEFINE([BUILD_JTAG_DPI], [1], [1 if you want JTAG DPI.]) -], [ - AC_DEFINE([BUILD_JTAG_DPI], [0], [0 if you don't want JTAG DPI.]) -]) - - -AS_IF([test "x$build_amtjtagaccel" = "xyes"], [ - AC_DEFINE([BUILD_AMTJTAGACCEL], [1], [1 if you want the Amontec JTAG-Accelerator driver.]) -], [ - AC_DEFINE([BUILD_AMTJTAGACCEL], [0], [0 if you don't want the Amontec JTAG-Accelerator driver.]) -]) - AS_IF([test "x$build_gw16012" = "xyes"], [ AC_DEFINE([BUILD_GW16012], [1], [1 if you want the Gateworks GW16012 driver.]) ], [ AC_DEFINE([BUILD_GW16012], [0], [0 if you don't want the Gateworks GW16012 driver.]) ]) -AS_IF([test "x$enable_buspirate" != "xno"], [ - AC_DEFINE([BUILD_BUSPIRATE], [1], [1 if you want the Buspirate JTAG driver.]) -], [ - AC_DEFINE([BUILD_BUSPIRATE], [0], [0 if you don't want the Buspirate JTAG driver.]) -]) - AS_IF([test "x$use_internal_jimtcl" = "xyes"], [ - AS_IF([test -f "$srcdir/jimtcl/configure.ac"], [ + AS_IF([test -f "$srcdir/jimtcl/configure"], [ AS_IF([test "x$use_internal_jimtcl_maintainer" = "xyes"], [ - jimtcl_config_options="--disable-install-jim --with-ext=json --maintainer" + jimtcl_config_options="--disable-install-jim --with-ext=json --minimal --disable-ssl --maintainer" ], [ - jimtcl_config_options="--disable-install-jim --with-ext=json" + jimtcl_config_options="--disable-install-jim --with-ext=json --minimal --disable-ssl" ]) AX_CONFIG_SUBDIR_OPTION([jimtcl], [$jimtcl_config_options]) ], [ AC_MSG_ERROR([jimtcl not found, run git submodule init and git submodule update.]) ]) -]) - -AS_IF([test "x$build_remote_bitbang" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_REMOTE_BITBANG], [1], [1 if you want the Remote Bitbang JTAG driver.]) ], [ - AC_DEFINE([BUILD_REMOTE_BITBANG], [0], [0 if you don't want the Remote Bitbang JTAG driver.]) -]) - -AS_IF([test "x$build_sysfsgpio" = "xyes"], [ - build_bitbang=yes - AC_DEFINE([BUILD_SYSFSGPIO], [1], [1 if you want the SysfsGPIO driver.]) -], [ - AC_DEFINE([BUILD_SYSFSGPIO], [0], [0 if you don't want SysfsGPIO driver.]) -]) - -AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [ - build_xlnx_pcie_xvc=yes - AC_DEFINE([BUILD_XLNX_PCIE_XVC], [1], [1 if you want the Xilinx XVC/PCIe driver.]) -], [ - AC_DEFINE([BUILD_XLNX_PCIE_XVC], [0], [0 if you don't want Xilinx XVC/PCIe driver.]) + PKG_CHECK_MODULES([JIMTCL], [jimtcl >= 0.79], [ + have_jimtcl_pkg_config=yes + ], [ + have_jimtcl_pkg_config=no + AC_CHECK_HEADER([jim.h], [], [ + AC_MSG_ERROR([jimtcl is required but not found via pkg-config and system includes]) + ]) + ]) ]) PKG_CHECK_MODULES([LIBUSB1], [libusb-1.0], [ @@ -634,7 +571,6 @@ AS_IF([test "x$enable_capstone" != xno], [ PKG_CHECK_MODULES([CAPSTONE], [capstone], [ AC_DEFINE([HAVE_CAPSTONE], [1], [1 if you have Capstone disassembly framework.]) ], [ - AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.]) if test "x$enable_capstone" != xauto; then AC_MSG_ERROR([--with-capstone was given, but test for Capstone failed]) fi @@ -642,6 +578,10 @@ AS_IF([test "x$enable_capstone" != xno], [ ]) ]) +AS_IF([test "x$enable_capstone" == xno], [ + AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.]) +]) + for hidapi_lib in hidapi hidapi-hidraw hidapi-libusb; do PKG_CHECK_MODULES([HIDAPI],[$hidapi_lib],[ use_hidapi=yes @@ -659,43 +599,98 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [ PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no]) ]) -PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [use_libgpiod=yes], [use_libgpiod=no]) +PKG_CHECK_MODULES([LIBGPIOD], [libgpiod < 2.0], [ + use_libgpiod=yes + PKG_CHECK_EXISTS([libgpiod >= 1.5], + [AC_DEFINE([HAVE_LIBGPIOD1_FLAGS_BIAS], [1], [define if libgpiod v1 has line request flags bias])]) +], [use_libgpiod=no]) PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2], [use_libjaylink=yes], [use_libjaylink=no]) +# Arg $1: An array of adapter triplets, used to derive option and variable names for each adapter. +# Arg $2: Whether the adapters can be enabled, for example, because +# their prerequisites are installed in the system. +# Arg $3: What prerequisites are missing, to be shown in an error message +# if an adapter was requested but cannot be enabled. m4_define([PROCESS_ADAPTERS], [ - m4_foreach([adapter], [$1], [ + m4_foreach([adapterTuple], [$1], [ AS_IF([test $2], [ - AS_IF([test "x$ADAPTER_VAR([adapter])" != "xno"], [ - AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [1], [1 if you want the ]ADAPTER_DESC([adapter]).) + AS_IF([test "x$ADAPTER_VAR([adapterTuple])" != "xno"], [ + AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [1], + [1 if you want the ]ADAPTER_DESC([adapterTuple]).) ], [ - AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).) + AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0], + [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).) ]) ], [ - AS_IF([test "x$ADAPTER_VAR([adapter])" = "xyes"], [ - AC_MSG_ERROR([$3 is required for the ADAPTER_DESC([adapter])]) + AS_IF([test "x$ADAPTER_VAR([adapterTuple])" = "xyes"], [ + AC_MSG_ERROR([$3 is required for [adapterTuple] "ADAPTER_DESC([adapterTuple])".]) ]) - ADAPTER_VAR([adapter])=no - AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).) + ADAPTER_VAR([adapterTuple])=no + AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0], [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).) ]) - AM_CONDITIONAL(ADAPTER_SYM([adapter]), [test "x$ADAPTER_VAR([adapter])" != "xno"]) + AM_CONDITIONAL(ADAPTER_SYM([adapterTuple]), [test "x$ADAPTER_VAR([adapterTuple])" != "xno"]) ]) ]) PROCESS_ADAPTERS([USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x]) -PROCESS_ADAPTERS([DEPRECATED_USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x]) PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi]) PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x]) PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi]) PROCESS_ADAPTERS([LIBFTDI_USB1_ADAPTERS], ["x$use_libftdi" = "xyes" -a "x$use_libusb1" = "xyes"], [libftdi and libusb-1.x]) -PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [libgpiod]) +PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [Linux libgpiod]) +PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem]) +PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs]) +PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused]) PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2]) +PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build]) +PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"], + [internal error: validation should happen beforehand]) +PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"], + [Linux spidev]) +PROCESS_ADAPTERS([VDEBUG_ADAPTER], [true], [unused]) +PROCESS_ADAPTERS([JTAG_DPI_ADAPTER], [true], [unused]) +PROCESS_ADAPTERS([JTAG_VPI_ADAPTER], [true], [unused]) +PROCESS_ADAPTERS([RSHIM_ADAPTER], ["x$can_build_rshim" = "xyes"], + [internal error: validation should happen beforehand]) +PROCESS_ADAPTERS([AMTJTAGACCEL_ADAPTER], [true], [unused]) +PROCESS_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS], [true], [unused]) +PROCESS_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS], [true], [unused]) +PROCESS_ADAPTERS([DUMMY_ADAPTER], [true], [unused]) AS_IF([test "x$enable_linuxgpiod" != "xno"], [ build_bitbang=yes ]) +AS_IF([test "x$enable_sysfsgpio" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_remote_bitbang" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_bcm2835gpio" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_imx_gpio" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_am335xgpio" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_ep93xx" != "xno"], [ + build_bitbang=yes +]) + +AS_IF([test "x$enable_at91rm9200" != "xno"], [ + build_bitbang=yes +]) + AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno" -o "x$enable_nulink" != "xno"], [ AC_DEFINE([BUILD_HLADAPTER], [1], [1 if you want the High Level JTAG driver.]) AM_CONDITIONAL([HLADAPTER], [true]) @@ -713,7 +708,7 @@ AS_IF([test "x$enable_jlink" != "xno"], [ AX_CONFIG_SUBDIR_OPTION([src/jtag/drivers/libjaylink], [--enable-subproject-build]) ], [ - AC_MSG_ERROR([Internal libjaylink not found, run either 'git submodule init' and 'git submodule update' or disable internal libjaylink with --disable-internal-libjaylink.]) + AC_MSG_ERROR([Internal libjaylink not found, run 'git submodule init' and 'git submodule update'.]) ]) ]) ]) @@ -730,24 +725,10 @@ AS_IF([test "x$enable_esp_usb_jtag" != "xno"], [ AM_CONDITIONAL([RELEASE], [test "x$build_release" = "xyes"]) AM_CONDITIONAL([PARPORT], [test "x$build_parport" = "xyes"]) -AM_CONDITIONAL([DUMMY], [test "x$build_dummy" = "xyes"]) AM_CONDITIONAL([GIVEIO], [test "x$parport_use_giveio" = "xyes"]) -AM_CONDITIONAL([EP93XX], [test "x$build_ep93xx" = "xyes"]) -AM_CONDITIONAL([AT91RM9200], [test "x$build_at91rm9200" = "xyes"]) -AM_CONDITIONAL([BCM2835GPIO], [test "x$build_bcm2835gpio" = "xyes"]) -AM_CONDITIONAL([IMX_GPIO], [test "x$build_imx_gpio" = "xyes"]) -AM_CONDITIONAL([AM335XGPIO], [test "x$build_am335xgpio" = "xyes"]) AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"]) -AM_CONDITIONAL([JTAG_VPI], [test "x$build_jtag_vpi" = "xyes"]) -AM_CONDITIONAL([VDEBUG], [test "x$build_vdebug" = "xyes"]) -AM_CONDITIONAL([JTAG_DPI], [test "x$build_jtag_dpi" = "xyes"]) AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"]) -AM_CONDITIONAL([AMTJTAGACCEL], [test "x$build_amtjtagaccel" = "xyes"]) AM_CONDITIONAL([GW16012], [test "x$build_gw16012" = "xyes"]) -AM_CONDITIONAL([REMOTE_BITBANG], [test "x$build_remote_bitbang" = "xyes"]) -AM_CONDITIONAL([BUSPIRATE], [test "x$enable_buspirate" != "xno"]) -AM_CONDITIONAL([SYSFSGPIO], [test "x$build_sysfsgpio" = "xyes"]) -AM_CONDITIONAL([XLNX_PCIE_XVC], [test "x$build_xlnx_pcie_xvc" = "xyes"]) AM_CONDITIONAL([USE_LIBUSB1], [test "x$use_libusb1" = "xyes"]) AM_CONDITIONAL([IS_CYGWIN], [test "x$is_cygwin" = "xyes"]) AM_CONDITIONAL([IS_MINGW], [test "x$is_mingw" = "xyes"]) @@ -758,12 +739,14 @@ AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"]) AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"]) AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"]) AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"]) -AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"]) AM_CONDITIONAL([HAVE_CAPSTONE], [test "x$enable_capstone" != "xno"]) AM_CONDITIONAL([INTERNAL_JIMTCL], [test "x$use_internal_jimtcl" = "xyes"]) +AM_CONDITIONAL([HAVE_JIMTCL_PKG_CONFIG], [test "x$have_jimtcl_pkg_config" = "xyes"]) AM_CONDITIONAL([INTERNAL_LIBJAYLINK], [test "x$use_internal_libjaylink" = "xyes"]) +AM_CONDITIONAL([USE_GCOV], [test "x$enable_gcov" = "xyes"]) + # Look for environ alternatives. Possibility #1: is environ in unistd.h or stdlib.h? AC_MSG_CHECKING([for environ in unistd.h and stdlib.h]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ @@ -819,23 +802,58 @@ AS_IF([test "x$gcc_warnings" = "xyes"], [ AC_SUBST(EXTRA_DIST_NEWS, ["$(echo $srcdir/NEWS-*)"]) AC_CONFIG_FILES([ - Makefile + Makefile \ + testing/Makefile \ + testing/tcl_commands/Makefile ]) AC_OUTPUT +AS_IF([test "x$enable_jlink" != "xno"], [ + AS_IF([test "x$use_internal_libjaylink" = "xyes"], [ + AC_MSG_WARN([Using the internal libjaylink is deprecated and will not be possible in the future.]) + ]]) +) + +AS_IF([test "x$use_internal_jimtcl" = "xyes"], [ + AC_MSG_WARN([Using the internal jimtcl is deprecated and will not be possible in the future.]) +]) + +AS_IF([test "x$enable_amtjtagaccel" != "xno"], [ + echo + echo + AC_MSG_WARN([Amontec JTAG-Accelerator adapter is deprecated and support will be removed in the next release!]) +]) +AS_IF([test "x$build_gw16012" = "xyes"], [ + echo + echo + AC_MSG_WARN([Gateworks GW16012 JTAG adapter is deprecated and support will be removed in the next release!]) +]) + echo echo echo OpenOCD configuration summary -echo -------------------------------------------------- -m4_foreach([adapter], [USB1_ADAPTERS, - DEPRECATED_USB1_ADAPTERS, +echo --------------------------------------------------- +m4_foreach([adapterTuple], [USB1_ADAPTERS, HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS, LIBFTDI_USB1_ADAPTERS, LIBGPIOD_ADAPTERS, + DMEM_ADAPTER, + SYSFSGPIO_ADAPTER, + REMOTE_BITBANG_ADAPTER, LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS, - OPTIONAL_LIBRARIES], - [s=m4_format(["%-40s"], ADAPTER_DESC([adapter])) - AS_CASE([$ADAPTER_VAR([adapter])], + LINUXSPIDEV_ADAPTER, + VDEBUG_ADAPTER, + JTAG_DPI_ADAPTER, + JTAG_VPI_ADAPTER, + RSHIM_ADAPTER, + AMTJTAGACCEL_ADAPTER, + HOST_ARM_BITBANG_ADAPTERS, + HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS, + DUMMY_ADAPTER, + OPTIONAL_LIBRARIES, + COVERAGE], + [s=m4_format(["%-49s"], ADAPTER_DESC([adapterTuple])) + AS_CASE([$ADAPTER_VAR([adapterTuple])], [auto], [ echo "$s"yes '(auto)' ], @@ -844,6 +862,11 @@ m4_foreach([adapter], [USB1_ADAPTERS, ], [no], [ echo "$s"no + ], + [ + AC_MSG_ERROR(m4_normalize([ + Error in [adapterTuple] "ADAPTER_ARG([adapterTuple])": Variable "ADAPTER_VAR([adapterTuple])" + has invalid value "$ADAPTER_VAR([adapterTuple])".])) ]) ]) echo diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules index 4f346a2aac..e3511f6db1 100644 --- a/contrib/60-openocd.rules +++ b/contrib/60-openocd.rules @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Copy this file to /etc/udev/rules.d/ # If rules fail to reload automatically, you can refresh udev rules # with the command "udevadm control --reload" @@ -27,6 +29,27 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev", # Original FT231XQ VID:PID ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="660", GROUP="plugdev", TAG+="uaccess" +# Original FT2233HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6040", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT4233HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6041", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT2232HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6042", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT4232HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6043", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT233HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6044", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT232HP VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6045", MODE="660", GROUP="plugdev", TAG+="uaccess" + +# Original FT4232HA VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6048", MODE="660", GROUP="plugdev", TAG+="uaccess" + # DISTORTEC JTAG-lock-pick Tiny 2 ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="660", GROUP="plugdev", TAG+="uaccess" @@ -97,6 +120,8 @@ ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", MODE="660", GROUP="plugdev", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", MODE="660", GROUP="plugdev", TAG+="uaccess" ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", MODE="660", GROUP="plugdev", TAG+="uaccess" ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3755", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3757", MODE="660", GROUP="plugdev", TAG+="uaccess" # Cypress SuperSpeed Explorer Kit ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0007", MODE="660", GROUP="plugdev", TAG+="uaccess" @@ -220,6 +245,13 @@ ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="1106", MODE="660", GROUP="plugdev", ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1001", MODE="660", GROUP="plugdev", TAG+="uaccess" ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1002", MODE="660", GROUP="plugdev", TAG+="uaccess" +# ANGIE USB-JTAG Adapter +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="414f", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="424e", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4255", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4355", MODE="660", GROUP="plugdev", TAG+="uaccess" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4a55", MODE="660", GROUP="plugdev", TAG+="uaccess" + # Marvell Sheevaplug ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="660", GROUP="plugdev", TAG+="uaccess" diff --git a/contrib/buildroot/openocd_be_defconfig b/contrib/buildroot/openocd_be_defconfig new file mode 100644 index 0000000000..49a6ec2ac4 --- /dev/null +++ b/contrib/buildroot/openocd_be_defconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +BR2_armeb=y +BR2_cortex_a7=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_PACKAGE_OPENOCD=y +BR2_PACKAGE_OPENOCD_FTDI=y +BR2_PACKAGE_OPENOCD_STLINK=y +BR2_PACKAGE_OPENOCD_TI_ICDI=y +BR2_PACKAGE_OPENOCD_ULINK=y +BR2_PACKAGE_OPENOCD_UBLASTER2=y +BR2_PACKAGE_OPENOCD_JLINK=y +BR2_PACKAGE_OPENOCD_OSDBM=y +BR2_PACKAGE_OPENOCD_OPENDOUS=y +BR2_PACKAGE_OPENOCD_VSLLINK=y +BR2_PACKAGE_OPENOCD_USBPROG=y +BR2_PACKAGE_OPENOCD_RLINK=y +BR2_PACKAGE_OPENOCD_ARMEW=y +BR2_PACKAGE_OPENOCD_XDS110=y +BR2_PACKAGE_OPENOCD_PARPORT=y +BR2_PACKAGE_OPENOCD_VPI=y +BR2_PACKAGE_OPENOCD_UBLASTER=y +BR2_PACKAGE_OPENOCD_AMTJT=y +BR2_PACKAGE_OPENOCD_GW16012=y +BR2_PACKAGE_OPENOCD_PRESTO=y +BR2_PACKAGE_OPENOCD_OPENJTAG=y +BR2_PACKAGE_OPENOCD_BUSPIRATE=y +BR2_PACKAGE_OPENOCD_SYSFS=y diff --git a/contrib/coresight-trace.txt b/contrib/coresight-trace.txt deleted file mode 100644 index 517119b6f6..0000000000 --- a/contrib/coresight-trace.txt +++ /dev/null @@ -1,68 +0,0 @@ -+OpenOCD and CoreSight Tracing -+ -Many recent ARM chips (Using e..g. Cortex-M3 and -Cortex-M4 cores) support CoreSight debug/trace. -This note sketches an approach currently planned for those cores -with OpenOCD. - - This tracing data can help debug and tune ARM software, but not -all cores support tracing. Some support more extensive tracing -other cores with trace support +should be able to use the same -approach and maybe some of the same analysis code. - -+the Cortex-M3 is assumed here to be the -+core in use, for simplicity and to reflect current OpenOCD users. - - -This note summarizes a software model to generate, collect, and -analyze such trace data . That is not fully implemented as of early -January 2011, +and thus is not *yet* usable. -+ -+ -+Some microcontroller cores support a low pin-count Single-wire trace, -with a mode where +trace data is emitted (usually to a UART. To use -this mode, +SWD must be in use. -+At this writing, OpenOCD SWD support is not yet complete either. - -(There are also multi-wire trace ports requiring more complex debug -adapters than OpenOCD currently supports, and offering richer data. -+ -+ -+* ENABLING involves activating SWD and (single wire) trace. -+ -+current expectations are that OpenOCD itself will handle enabling; -activating single wire trace involves a debug adapter interaction, and -collecting that trace data requires particular (re)wiring. -+ -+* CONFIGURATION involves setting up ITM and/or ETM modules to emit the -+desired data from the Cortex core. (This might include dumping -+event counters printf-style messages; code profiling; and more. Not all -+cores offer the same trace capabilities. -+ -+current expectations are that Tcl scripts will be used to configure these -+modules for the desired tracing, by direct writes to registers. In some -+cases (as with RTOS event tracking and similar messaging, this might -+be augmented or replaced by user code running on the ARM core. -+ -+COLLECTION involves reading that trace data, probably through UART, and -+saving it in a useful format to analyse For now, deferred analysis modes -are assumed, not than real-time or interactive ones. -+ -+ -+current expectations are to to dump data in text using contrib/itmdump.c -+or derived tools, and to post-process it into reports. Such reports might -+include program messaging (such as application data streams via ITM, maybe -+using printf type messaging; code coverage analysis or so forth. Recent -+versions of CMSIS software reserve some ITM codespace for RTOS event -tracing and include ITM messaging support. -Clearly some of that data would be valuable for interactive debugging. -+ -+Should someone get ambitious, GUI reports should be possible. GNU tools -+for simpler reports like gprof may be simpler to support at first. -+In any case, OpenOCD is not currently GUI-oriented. Accordingly, we now -+expect any such graphics to come from postprocessing. - - measurements for RTOS event timings should also be easy to collect. -+Examples include context and message switch times, as well as times -for application interactions. -+ diff --git a/contrib/cross-build.sh b/contrib/cross-build.sh index 9328c3ab64..1784d79ad1 100755 --- a/contrib/cross-build.sh +++ b/contrib/cross-build.sh @@ -1,4 +1,5 @@ #!/bin/sh +# SPDX-License-Identifier: GPL-2.0-or-later # This is an example of how to do a cross-build of OpenOCD using pkg-config. # Cross-building with pkg-config is deceptively hard and most guides and @@ -40,12 +41,16 @@ WORK_DIR=$PWD : ${HIDAPI_SRC:=/path/to/hidapi} : ${LIBFTDI_SRC:=/path/to/libftdi} : ${CAPSTONE_SRC:=/path/to/capstone} +: ${LIBJAYLINK_SRC:=/path/to/libjaylink} +: ${JIMTCL_SRC:=/path/to/jimtcl} OPENOCD_SRC=`readlink -m $OPENOCD_SRC` LIBUSB1_SRC=`readlink -m $LIBUSB1_SRC` HIDAPI_SRC=`readlink -m $HIDAPI_SRC` LIBFTDI_SRC=`readlink -m $LIBFTDI_SRC` CAPSTONE_SRC=`readlink -m $CAPSTONE_SRC` +LIBJAYLINK_SRC=`readlink -m $LIBJAYLINK_SRC` +JIMTCL_SRC=`readlink -m $JIMTCL_SRC` HOST_TRIPLET=$1 BUILD_DIR=$WORK_DIR/$HOST_TRIPLET-build @@ -53,6 +58,8 @@ LIBUSB1_BUILD_DIR=$BUILD_DIR/libusb1 HIDAPI_BUILD_DIR=$BUILD_DIR/hidapi LIBFTDI_BUILD_DIR=$BUILD_DIR/libftdi CAPSTONE_BUILD_DIR=$BUILD_DIR/capstone +LIBJAYLINK_BUILD_DIR=$BUILD_DIR/libjaylink +JIMTCL_BUILD_DIR=$BUILD_DIR/jimtcl OPENOCD_BUILD_DIR=$BUILD_DIR/openocd ## Root of host file tree @@ -157,6 +164,28 @@ libdir=${exec_prefix}/lib \ includedir=${prefix}/include/capstone\n\n;' $CAPSTONE_PC_FILE fi +# libjaylink build & install into sysroot +if [ -d $LIBJAYLINK_SRC ] ; then + mkdir -p $LIBJAYLINK_BUILD_DIR + cd $LIBJAYLINK_BUILD_DIR + $LIBJAYLINK_SRC/configure --build=`$LIBJAYLINK_SRC/config.guess` --host=$HOST_TRIPLET \ + --with-sysroot=$SYSROOT --prefix=$PREFIX \ + $LIBJAYLINK_CONFIG + make -j $MAKE_JOBS + make install DESTDIR=$SYSROOT +fi + +# jimtcl build & install into sysroot +if [ -d $JIMTCL_SRC ] ; then + mkdir -p $JIMTCL_BUILD_DIR + cd $JIMTCL_BUILD_DIR + $JIMTCL_SRC/configure --host=$HOST_TRIPLET --prefix=$PREFIX \ + $JIMTCL_CONFIG + make -j $MAKE_JOBS + # Running "make" does not create this file for static builds on Windows but "make install" still expects it + touch $JIMTCL_BUILD_DIR/build-jim-ext + make install DESTDIR=$SYSROOT +fi # OpenOCD build & install into sysroot mkdir -p $OPENOCD_BUILD_DIR diff --git a/contrib/firmware/angie/c/Makefile b/contrib/firmware/angie/c/Makefile new file mode 100644 index 0000000000..1bcc1f7d1e --- /dev/null +++ b/contrib/firmware/angie/c/Makefile @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +#**************************************************************************** +# File : Makefile * +# Contents : Code for NanoXplore USB-JTAG ANGIE adapter hardware. * +# Based on openULINK project by: Martin Schmoelzer. * +# Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * +# * +# * +# ***************************************************************************/ + +# Define the name of tools. +PREFIX = + +# Small Device C Compiler: http://sdcc.sourceforge.net/ +CC = $(PREFIX)sdcc + +# 8051 assembler, part of the SDCC software package. +AS = $(PREFIX)sdas8051 + +# SDCC produces quite messy Intel HEX files. This tool is be used to re-format +# those files. It is not required for the firmware download functionality in +# the OpenOCD driver, but the resulting file is smaller. +PACKIHX = $(PREFIX)packihx + +# GNU binutils size. Used to print the size of the IHX file generated by SDCC. +SIZE = size + +# Source and header directories. +SRC_DIR = src +INCLUDE_DIR = include + +CODE_SIZE = 0x3C00 +XRAM_LOC = 0x3C00 +XRAM_SIZE = 0x0400 + +CFLAGS = --std-sdcc99 --opt-code-size --model-small +LDFLAGS = --code-loc 0x0000 --code-size $(CODE_SIZE) --xram-loc $(XRAM_LOC) \ + --xram-size $(XRAM_SIZE) --iram-size 256 --model-small + +# list of base object files +OBJECTS = main.rel usb.rel protocol.rel jtag.rel delay.rel USBJmpTb.rel serial.rel gpif.rel i2c.rel +HEADERS = $(INCLUDE_DIR)/usb.h \ + $(INCLUDE_DIR)/protocol.h \ + $(INCLUDE_DIR)/jtag.h \ + $(INCLUDE_DIR)/delay.h \ + $(INCLUDE_DIR)/reg_ezusb.h \ + $(INCLUDE_DIR)/io.h \ + $(INCLUDE_DIR)/serial.h \ + $(INCLUDE_DIR)/fx2macros.h \ + $(INCLUDE_DIR)/msgtypes.h \ + $(INCLUDE_DIR)/i2c.h + +# Disable all built-in rules. +.SUFFIXES: + +# Targets which are executed even when identically named file is present. +.PHONY: all, clean + +all: angie_firmware.ihx + $(SIZE) angie_firmware.ihx + +angie_firmware.ihx: $(OBJECTS) + $(CC) -mmcs51 $(LDFLAGS) -o $@ $^ + +# Rebuild every C module (there are only 8 of them) if any header changes. +%.rel: $(SRC_DIR)/%.c $(HEADERS) + $(CC) -c $(CFLAGS) -mmcs51 -I$(INCLUDE_DIR) -o $@ $< + +%.rel: $(SRC_DIR)/%.a51 + $(AS) -lsgo $@ $< + +clean: + rm -f *.asm *.lst *.rel *.rst *.sym *.ihx *.lk *.map *.mem + +bin: angie_firmware.ihx + makebin -p angie_firmware.ihx angie_firmware.bin + +hex: angie_firmware.ihx + $(PACKIHX) angie_firmware.ihx > fx2.hex diff --git a/contrib/firmware/angie/c/README b/contrib/firmware/angie/c/README new file mode 100644 index 0000000000..2d41da7a40 --- /dev/null +++ b/contrib/firmware/angie/c/README @@ -0,0 +1,37 @@ +#SPDX-License-Identifier: GPL-2.0-or-later + +This is the ANGIE firmware for ANGIE USB-JTAG adapter. + +The main components of ANGIE adapter are: +- Cypress EZ-USB FX2 microcontroller +- Spartan-6 FPGA +- SRAM memory chip +- Pin headers for various JTAG pin assignments + +To compile the firmware, the SDCC compiler package is required. Most Linux +distributions include SDCC in their official package repositories. The SDCC +source code can be found at http://sdcc.sourceforge.net/ + +Simply type "make bin" in the ANGIE directory to compile the firmware. +"make clean" will remove all generated files except the BIN file +required for downloading the firmware to ANGIE. + +Note that the EZ-USB FX2 microcontroller does not have on-chip flash, +ANGIE include on-board EEPROM memory to store the firmware program of +the FX2, but we are not going to use this method. + +Instead, upon initial connection of the ANGIE adapter to the host PC +via USB, the EZ-USB FX2 core has enough intelligence to act as a +stand-alone USB device, responding to USB control requests and allowing +firmware download via a special VENDOR-type control request. Then, the +EZ-USB microcontroller simulates a disconnect and re-connect to the USB bus. +It may take up to two seconds for the host to recognize the newly connected +device before OpenOCD can proceed to execute JTAG commands. This delay is +only visible when OpenOCD first uses a blank (unconfigured) ANGIE device. + +Once the firmware downloaded, the FX2 microcontroller activate its GPIF mode, +download the Spartan-6 FPGA's bitstream, program the FPGA rapidly, and switch +back to default io mode. + +Once the user disconnects the ANGIE adapter, all its memory contents are lost +and the firmware & bitstream download process has to be executed again. diff --git a/contrib/firmware/angie/c/include/delay.h b/contrib/firmware/angie/c/include/delay.h new file mode 100644 index 0000000000..0397941fe8 --- /dev/null +++ b/contrib/firmware/angie/c/include/delay.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************** + File : delay.h * + Contents : Delays handling header file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************/ + +#ifndef __DELAY_H +#define __DELAY_H + +#include + +void syncdelay(uint8_t count); +void delay_5us(void); +void delay_1ms(void); +void delay_us(uint16_t delay); +void delay_ms(uint16_t delay); + +#ifndef _IFREQ +#define _IFREQ 48000 /* IFCLK frequency in kHz */ +#endif + +/* CFREQ can be any one of: 48000, 24000, or 12000 */ +#ifndef _CFREQ +#define _CFREQ 48000 /* CLKOUT frequency in kHz */ +#endif + +#if (_IFREQ < 5000) +#error "_IFREQ too small! Valid Range: 5000 to 48000..." +#endif + +#if (_IFREQ > 48000) +#error "_IFREQ too large! Valid Range: 5000 to 48000..." +#endif + +#if (_CFREQ != 48000) +#if (_CFREQ != 24000) +#if (_CFREQ != 12000) +#error "_CFREQ invalid! Valid values: 48000, 24000, 12000..." +#endif +#endif +#endif + +/* Synchronization Delay formula: see TRM section 15-14 */ +#define _SCYCL (3 * (_CFREQ) + 5 * (_IFREQ) - 1) / (2 * (_IFREQ)) +#endif diff --git a/contrib/firmware/angie/c/include/fx2macros.h b/contrib/firmware/angie/c/include/fx2macros.h new file mode 100644 index 0000000000..9067b56193 --- /dev/null +++ b/contrib/firmware/angie/c/include/fx2macros.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ + +/* + * This code was taken from the fx2lib project from this link: + * https://github.com/djmuhlestein/fx2lib + * + * Copyright (C) 2009 Ubixum, Inc. +*/ + +/*! \file + * Macros for simple common tasks in fx2 firmware. + * */ + +#ifndef FX2MACROS_H +#define FX2MACROS_H + +#include "reg_ezusb.h" + +typedef enum {FALSE = 0, TRUE} BOOL_VALS; + +/** + * \brief Used for getting and setting the CPU clock speed. + **/ +typedef enum {CLK_12M = 0, CLK_24M, CLK_48M} CLK_SPD; + +/** + * \brief Evaluates to a CLK_SPD enum. + **/ +#define CPUFREQ (CLK_SPD)((CPUCS & bmclkspd) >> 3) + +#endif diff --git a/contrib/firmware/angie/c/include/i2c.h b/contrib/firmware/angie/c/include/i2c.h new file mode 100644 index 0000000000..d0404923b3 --- /dev/null +++ b/contrib/firmware/angie/c/include/i2c.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : i2c.h * + Contents : i2c bit-bang library * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef __I2C_H +#define __I2C_H + +#include +#include +#include + +void start_cd(void); +void repeated_start(void); +void stop_cd(void); +void clock_cd(void); +void send_ack(void); +void send_nack(void); +bool get_ack(void); + +uint8_t get_address(uint8_t adr, uint8_t rdwr); + +void send_byte(uint8_t input); +uint8_t receive_byte(void); +#endif diff --git a/contrib/firmware/angie/c/include/io.h b/contrib/firmware/angie/c/include/io.h new file mode 100644 index 0000000000..19289d11d8 --- /dev/null +++ b/contrib/firmware/angie/c/include/io.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : io.h * + Contents : input/output declaration header file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef __IO_H +#define __IO_H + +#include "reg_ezusb.h" + +/*************************************************************************** + * JTAG Signals: * + *************************************************************************** + * TMS ....... Test Mode Select * + * TCK ....... Test Clock * + * TDI ....... Test Data Input (from device point of view, not JTAG * + * adapter point of view!) * + * TDO ....... Test Data Output (from device point of view, not JTAG * + * adapter point of view!) * + * TRST ...... Test Reset: Used to reset the TAP Finite State Machine * + * into the Test Logic Reset state * + * SRST ..... Chip Reset * + ***************************************************************************/ + +/* PORT A */ +/* PA0 Not Connected */ +/* PA1 Not Connected */ +#define PIN_RDWR_B IOA2 +#define PIN_CSI_B IOA3 +#define PIN_INIT_B IOA4 +#define PIN_PROGRAM_B IOA5 +/* PA6 Not Connected */ +/* PA7 Not Connected */ + +/* PORT B */ +#define PIN_TRST IOB0 +#define PIN_TMS IOB1 +#define PIN_TCK IOB2 +#define PIN_TDI IOB3 +#define PIN_TDO IOB4 +#define PIN_SRST IOB5 +/* PB6 Not Connected */ +/* PB7 Not Connected */ + +/* JTAG Signals with direction 'OUT' on port B */ +/* PIN_TDI - PIN_TCK - PIN_TMS - PIN_TRST - PIN_SRST */ +#define MASK_PORTB_DIRECTION_OUT (bmbit0 | bmbit1 | bmbit2 | bmbit3 | bmbit5) + +/* PORT C */ +#define PIN_T0 IOC0 +#define PIN_T1 IOC1 +#define PIN_T2 IOC2 +#define PIN_T3 IOC3 +#define PIN_T4 IOC4 +/* PC5 Not Connected */ +/* PC6 Not Connected */ +/* PC7 Not Connected */ + +/* PORT D */ +#define PIN_SDA IOD0 +#define PIN_SCL IOD1 +#define PIN_SDA_DIR IOD2 +#define PIN_SCL_DIR IOD3 +/* PD4 Not Connected */ +/* PD5 Not Connected */ +/* PD6 Not Connected */ +/* PD7 Not Connected */ + +#endif diff --git a/contrib/firmware/angie/c/include/jtag.h b/contrib/firmware/angie/c/include/jtag.h new file mode 100644 index 0000000000..6d5df64805 --- /dev/null +++ b/contrib/firmware/angie/c/include/jtag.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : jtag.h * + Contents : Jtag handling functions header file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef __JTAG_H +#define __JTAG_H + +#include + +uint16_t jtag_get_signals(void); +void jtag_configure_tck_delay(uint8_t scan_in, uint8_t scan_out, + uint8_t scan_io, uint8_t tck, uint8_t tms); +void jtag_clock_tms(uint8_t count, uint8_t sequence); +void jtag_slow_clock_tms(uint8_t count, uint8_t sequence); +void jtag_set_signals(uint8_t low, uint8_t high); +void jtag_clock_tck(uint16_t count); +void jtag_slow_clock_tck(uint16_t count); +void jtag_scan_in(uint8_t out_offset, uint8_t in_offset); +void jtag_scan_out(uint8_t out_offset); +void jtag_scan_io(uint8_t out_offset, uint8_t in_offset); +void jtag_slow_scan_in(uint8_t out_offset, uint8_t in_offset); +void jtag_slow_scan_out(uint8_t out_offset); +void jtag_slow_scan_io(uint8_t out_offset, uint8_t in_offset); +#endif diff --git a/contrib/firmware/angie/c/include/msgtypes.h b/contrib/firmware/angie/c/include/msgtypes.h new file mode 100644 index 0000000000..91116904ad --- /dev/null +++ b/contrib/firmware/angie/c/include/msgtypes.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : msgtypes.h * + Contents : Definition of the commands supported by NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +/** + * @file + * Definition of the commands supported by the ANGIE firmware. + * + * Basically, two types of commands can be distinguished: + * - Commands with fixed payload size + * - Commands with variable payload size + * + * SCAN commands (in all variations) carry payloads of variable size, all + * other commands carry payloads of fixed size. + * + * In the case of SCAN commands, the payload size (n) is calculated by + * dividing the scan_size_bits variable by 8, rounding up the result. + * + * Offset zero always contains the command ID. + * + **************************************************************************** + * CMD_SCAN_IN, CMD_SLOW_SCAN_IN: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * * + * IN: * + * offset 0..n: TDO data * + **************************************************************************** + * CMD_SCAN_OUT, CMD_SLOW_SCAN_OUT: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * offset 6..x: TDI data * + **************************************************************************** + * CMD_SCAN_IO, CMD_SLOW_SCAN_IO: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * offset 6..x: TDI data * + * * + * IN: * + * offset 0..n: TDO data * + **************************************************************************** + * CMD_CLOCK_TMS, CMD_SLOW_CLOCK_TMS: * + * * + * OUT: * + * offset 1: tms_count * + * offset 2: tms_sequence * + **************************************************************************** + * CMD_CLOCK_TCK, CMD_SLOW_CLOCK_TCK: * + * * + * OUT: * + * offset 1: low byte of tck_count * + * offset 2: high byte of tck_count * + **************************************************************************** + * CMD_CLOCK_SLEEP_US: * + * * + * OUT: * + * offset 1: low byte of sleep_us * + * offset 2: high byte of sleep_us * + **************************************************************************** + * CMD_CLOCK_SLEEP_MS: * + * * + * OUT: * + * offset 1: low byte of sleep_ms * + * offset 2: high byte of sleep_ms * + **************************************************************************** + * CMD_GET_SIGNALS: * + * * + * IN: * + * offset 0: current state of input signals * + * offset 1: current state of output signals * + **************************************************************************** + * CMD_SET_SIGNALS: * + * * + * OUT: * + * offset 1: signals that should be de-asserted * + * offset 2: signals that should be asserted * + **************************************************************************** + * CMD_CONFIGURE_TCK_FREQ: * + * * + * OUT: * + * offset 1: delay value for scan_in function * + * offset 2: delay value for scan_out function * + * offset 3: delay value for scan_io function * + * offset 4: delay value for clock_tck function * + * offset 5: delay value for clock_tms function * + **************************************************************************** + * CMD_SET_LEDS: * + * * + * OUT: * + * offset 1: LED states: * + * Bit 0: turn COM LED on * + * Bit 1: turn RUN LED on * + * Bit 2: turn COM LED off * + * Bit 3: turn RUN LED off * + * Bits 7..4: Reserved * + **************************************************************************** + * CMD_TEST: * + * * + * OUT: * + * offset 1: unused dummy value * + **************************************************************************** + */ + +#ifndef __MSGTYPES_H +#define __MSGTYPES_H + +/* + * Command IDs: + * + * Bits 7..6: Reserved, should always be zero + * Bits 5..0: Command ID. There are 62 usable IDs. Of this 63 available IDs, + * the IDs 0x00..0x1F are commands with variable payload size, + * the IDs 0x20..0x3F are commands with fixed payload size. + */ + +#define CMD_ID_MASK 0x3F + +/* Commands with variable payload size */ +#define CMD_SCAN_IN 0x00 +#define CMD_SLOW_SCAN_IN 0x01 +#define CMD_SCAN_OUT 0x02 +#define CMD_SLOW_SCAN_OUT 0x03 +#define CMD_SCAN_IO 0x04 +#define CMD_SLOW_SCAN_IO 0x05 + +/* Commands with fixed payload size */ +#define CMD_CLOCK_TMS 0x20 +#define CMD_SLOW_CLOCK_TMS 0x21 +#define CMD_CLOCK_TCK 0x22 +#define CMD_SLOW_CLOCK_TCK 0x23 +#define CMD_SLEEP_US 0x24 +#define CMD_SLEEP_MS 0x25 +#define CMD_GET_SIGNALS 0x26 +#define CMD_SET_SIGNALS 0x27 +#define CMD_CONFIGURE_TCK_FREQ 0x28 +#define CMD_SET_LEDS 0x29 +#define CMD_TEST 0x2A + +/* JTAG signal definition for jtag_get_signals() -- Input signals! */ +#define SIGNAL_TDO 1 + +/* JTAG signal definition for jtag_get_signals() -- Output signals! */ +#define SIGNAL_TDI 8 +#define SIGNAL_TMS 2 +#define SIGNAL_TCK 4 +#define SIGNAL_TRST 1 +#define SIGNAL_SRST 32 + +#endif diff --git a/contrib/firmware/angie/c/include/protocol.h b/contrib/firmware/angie/c/include/protocol.h new file mode 100644 index 0000000000..a12644b27d --- /dev/null +++ b/contrib/firmware/angie/c/include/protocol.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : protocol.h * + Contents : Jtag commands handling protocol header file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef __PROTOCOL_H +#define __PROTOCOL_H + +#include + +bool execute_command(void); +void command_loop(void); + +#endif diff --git a/contrib/firmware/angie/c/include/reg_ezusb.h b/contrib/firmware/angie/c/include/reg_ezusb.h new file mode 100644 index 0000000000..c22476a1a6 --- /dev/null +++ b/contrib/firmware/angie/c/include/reg_ezusb.h @@ -0,0 +1,656 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : reg_ezusb.h * + Contents : FX2 microcontroller registers file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef REG_EZUSB_H +#define REG_EZUSB_H + +/** + * @file + * All information in this file was taken from the EZ-USB FX2 Technical + * Reference Manual, Cypress Semiconductor, 3901 North First Street + * San Jose, CA 95134 (www.cypress.com). + * + * The EZ-USB Technical Reference Manual is called "EZ-USB FX2 TRM" hereafter. + */ + +/* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */ +#include + +/* Bit vectors */ +#define bmbit0 0x01 +#define bmbit1 0x02 +#define bmbit2 0x04 +#define bmbit3 0x08 +#define bmbit4 0x10 +#define bmbit5 0x20 +#define bmbit6 0x40 +#define bmbit7 0x80 + +/************************************************************************** + ************************ Special Function Registers ********************** + ***************************************************************************/ +SFR(IOA, 0x80); +SBIT(IOA0, 0x80, 0); +SBIT(IOA1, 0x80, 1); +SBIT(IOA2, 0x80, 2); +SBIT(IOA3, 0x80, 3); +SBIT(IOA4, 0x80, 4); +SBIT(IOA5, 0x80, 5); +SBIT(IOA6, 0x80, 6); +SBIT(IOA7, 0x80, 7); + +SFR(SP, 0x81); +SFR(DPL0, 0x82); +SFR(DPH0, 0x83); +SFR(DPL1, 0x84); +SFR(DPL2, 0x85); + +SFR(DPS, 0x86); +#define SEL bmbit0 +/* Bit 1 read-only, always reads '0' */ +/* Bit 2 read-only, always reads '0' */ +/* Bit 3 read-only, always reads '0' */ +/* Bit 4 read-only, always reads '0' */ +/* Bit 5 read-only, always reads '0' */ +/* Bit 6 read-only, always reads '0' */ +/* Bit 7 read-only, always reads '0' */ + +SFR(PCON, 0x87); +#define IDLE bmbit0 +#define STOP bmbit1 +#define GF0 bmbit2 +#define GF1 bmbit3 +/* Bit 4 read-only, always reads '1' */ +/* Bit 5 read-only, always reads '1' */ +/* Bit 6 unused */ +#define SMOD0 bmbit7 + +SFR(TCON, 0x88); +SBIT(IT0, 0x88, 0); +SBIT(IE0, 0x88, 1); +SBIT(IT1, 0x88, 2); +SBIT(IE1, 0x88, 3); +SBIT(TR0, 0x88, 4); +SBIT(TF0, 0x88, 5); +SBIT(TR1, 0x88, 6); +SBIT(TF1, 0x88, 7); + +SFR(TMOD, 0x89); +SFR(TL0, 0x8A); +SFR(TL1, 0x8B); +SFR(TH0, 0x8C); +SFR(TH1, 0x8D); + +SFR(CKCON, 0x8E); +#define MD0 bmbit0 +#define MD1 bmbit1 +#define MD2 bmbit2 +#define T0M bmbit3 +#define T1M bmbit4 +#define T2M bmbit5 +/* Bit 6 unused */ +/* Bit 7 unused */ + +SFR(SPC_FNC, 0x8F); +#define BMWRS bmbit0 +/* Bit 1 read-only, always reads '0' */ +/* Bit 2 read-only, always reads '0' */ +/* Bit 3 read-only, always reads '0' */ +/* Bit 4 read-only, always reads '0' */ +/* Bit 5 read-only, always reads '0' */ +/* Bit 6 read-only, always reads '0' */ +/* Bit 7 read-only, always reads '0' */ + +SFR(IOB, 0x90); +SBIT(IOB0, 0x90, 0); +SBIT(IOB1, 0x90, 1); +SBIT(IOB2, 0x90, 2); +SBIT(IOB3, 0x90, 3); +SBIT(IOB4, 0x90, 4); +SBIT(IOB5, 0x90, 5); +SBIT(IOB6, 0x90, 6); +SBIT(IOB7, 0x90, 7); + +SFR(EXIF, 0x91); +SBIT(USBINT, 0x91, 4); +SBIT(I2CINT, 0x91, 5); +SBIT(IE4, 0x91, 6); +SBIT(IE5, 0x91, 7); + +SFR(MPAGE, 0x92); +SFR(SCON0, 0x98); +SBIT(RI, 0x98, 0); +SBIT(TI, 0x98, 1); +SBIT(RB8, 0x98, 2); +SBIT(TB8, 0x98, 3); +SBIT(REN, 0x98, 4); +SBIT(SM2, 0x98, 5); +SBIT(SM1, 0x98, 6); +SBIT(SM0, 0x98, 7); + +SFR(SBUF0, 0x99); +SFR(AUTOPTRH1, 0x9A); +SFR(AUTOPTRL1, 0x9B); +SFR(AUTOPTRH2, 0x9D); +SFR(AUTOPTRL2, 0x9E); + +#define AUTOPTR1H AUTOPTRH1 /* for backwards compatibility with examples */ +#define AUTOPTR1L AUTOPTRL1 /* for backwards compatibility with examples */ +#define APTR1H AUTOPTRH1 /* for backwards compatibility with examples */ +#define APTR1L AUTOPTRL1 /* for backwards compatibility with examples */ + +SFR(IOC, 0xA0); +SBIT(IOC0, 0xA0, 0); +SBIT(IOC1, 0xA0, 1); +SBIT(IOC2, 0xA0, 2); +SBIT(IOC3, 0xA0, 3); +SBIT(IOC4, 0xA0, 4); +SBIT(IOC5, 0xA0, 5); +SBIT(IOC6, 0xA0, 6); +SBIT(IOC7, 0xA0, 7); + +SFR(INT2CLR, 0xA1); +SFR(INT4CLR, 0xA2); +SFR(IE, 0xA8); +SBIT(EX0, 0xA8, 0); +SBIT(ET0, 0xA8, 1); +SBIT(EX1, 0xA8, 2); +SBIT(ET1, 0xA8, 3); +SBIT(ES0, 0xA8, 4); +SBIT(ET2, 0xA8, 5); +SBIT(ES1, 0xA8, 6); +SBIT(EA, 0xA8, 7); + +SFR(EP2468STAT, 0xAA); +#define EP8F bmbit7 +#define EP8E bmbit6 +#define EP6F bmbit5 +#define EP6E bmbit4 +#define EP4F bmbit3 +#define EP4E bmbit2 +#define EP2F bmbit1 +#define EP2E bmbit0 + +SFR(EP24FIFOFLGS, 0xAB); +SFR(EP68FIFOFLGS, 0xAC); +SFR(AUTOPTRSETUP, 0xAF); +SFR(IOD, 0xB0); +SBIT(IOD0, 0xB0, 0); +SBIT(IOD1, 0xB0, 1); +SBIT(IOD2, 0xB0, 2); +SBIT(IOD3, 0xB0, 3); +SBIT(IOD4, 0xB0, 4); +SBIT(IOD5, 0xB0, 5); +SBIT(IOD6, 0xB0, 6); +SBIT(IOD7, 0xB0, 7); + +SFR(IOE, 0xB1); +SFR(OEA, 0xB2); +SFR(OEB, 0xB3); +SFR(OEC, 0xB4); +SFR(OED, 0xB5); +SFR(OEE, 0xB6); + +SFR(IP, 0xB8); +SBIT(PX0, 0xB8, 0); +SBIT(PT0, 0xB8, 1); +SBIT(PX1, 0xB8, 2); +SBIT(PT1, 0xB8, 3); +SBIT(PS0, 0xB8, 4); +SBIT(PT2, 0xB8, 5); +SBIT(PS1, 0xB8, 6); +/* Bit 7 read-only, always reads '1' */ + +SFR(EP01STAT, 0xBA); +SFR(GPIFTRIG, 0xBB); +#define BMGPIFDONE bmbit7 +#define BMGPIFREAD bmbit2 +#define GPIF_EP2 0 +#define GPIF_EP4 1 +#define GPIF_EP6 2 +#define GPIF_EP8 3 + +SFR(GPIFSGLDATH, 0xBD); +SFR(GPIFSGLDATLX, 0xBE); +SFR(GPIFSGLDATLNOX, 0xBF); + +SFR(SCON1, 0xC0); +SBIT(RI_1, 0xC0, 0); +SBIT(TI_1, 0xC0, 1); +SBIT(RB8_1, 0xC0, 2); +SBIT(TB8_1, 0xC0, 3); +SBIT(REN_1, 0xC0, 4); +SBIT(SM2_1, 0xC0, 5); +SBIT(SM1_1, 0xC0, 6); +SBIT(SM0_1, 0xC0, 7); + +SFR(SBUF1, 0xC1); +SFR(T2CON, 0xC8); +SBIT(CPRL2, 0xC8, 0); +SBIT(C_T2, 0xC8, 1); +SBIT(TR2, 0xC8, 2); +SBIT(EXEN2, 0xC8, 3); +SBIT(TCLK, 0xC8, 4); +SBIT(RCLK, 0xC8, 5); +SBIT(EXF2, 0xC8, 6); +SBIT(TF2, 0xC8, 7); + +SFR(RCAP2L, 0xCA); +SFR(RCAP2H, 0xCB); +SFR(TL2, 0xCC); +SFR(TH2, 0xCD); +SFR(PSW, 0xD0); +SBIT(P, 0xD0, 0); +SBIT(F1, 0xD0, 1); +SBIT(OV, 0xD0, 2); +SBIT(RS0, 0xD0, 3); +SBIT(RS1, 0xD0, 4); +SBIT(F0, 0xD0, 5); +SBIT(AC, 0xD0, 6); +SBIT(CY, 0xD0, 7); + +SFR(EICON, 0xD8); +/* Bit 0 read-only, always reads '0' */ +/* Bit 1 read-only, always reads '0' */ +/* Bit 2 read-only, always reads '0' */ +SBIT(INT6, 0xD8, 3); +SBIT(RESI, 0xD8, 4); +SBIT(ERESI, 0xD8, 5); +/* Bit 6 read-only, always reads '1' */ +SBIT(SMOD1, 0xD8, 7); + +SFR(ACC, 0xE0); +SFR(EIE, 0xE8); +SBIT(EUSB, 0xE8, 0); +SBIT(EI2C, 0xE8, 1); +SBIT(EX4, 0xE8, 2); +SBIT(EX5, 0xE8, 3); +SBIT(EWDI, 0xE8, 4); +/* Bit 5 read-only, always reads '1' */ +/* Bit 6 read-only, always reads '1' */ +/* Bit 7 read-only, always reads '1' */ + +SFR(B, 0xF0); +SFR(EIP, 0xF8); +SBIT(PUSB, 0xF8, 0); +SBIT(PI2C, 0xF8, 1); +SBIT(PX4, 0xF8, 2); +SBIT(PX5, 0xF8, 3); +SBIT(PX6, 0xF8, 4); +/* Bit 5 read-only, always reads '1' */ +/* Bit 6 read-only, always reads '1' */ +/* Bit 7 read-only, always reads '1' */ + +/************************************************************************** + ***************************** XDATA Registers **************************** + ***************************************************************************/ + +SFRX(GPIF_WAVE_DATA, 0xE400); +SFRX(RES_WAVEDATA_END, 0xE480); + +/* General Configuration */ +SFRX(CPUCS, 0xE600); +#define RES8051 bmbit0 +#define CLKOE bmbit1 +#define BMCLKINV bmbit2 +#define bmclkspd0 bmbit3 +#define bmclkspd1 bmbit4 +#define bmclkspd (bmbit4 | bmbit3) +#define BMPRTCSTB bmbit5 + +/* PCON register */ +#define BMSMOD0 bmbit7 + +SFRX(IFCONFIG, 0xE601); +#define BMIFCLKSRC bmbit7 +#define BM3048MHZ bmbit6 +#define BMIFCLKOE bmbit5 +#define BMIFCLKPOL bmbit4 +#define BMASYNC bmbit3 +#define BMGSTATE bmbit2 +#define BMIFCFG1 bmbit1 +#define BMIFCFG0 bmbit0 +#define BMIFCFGMASK (BMIFCFG0 | BMIFCFG1) +#define BMIFGPIF BMIFCFG1 + +SFRX(PINFLAGSAB, 0xE602); +SFRX(PINFLAGSCD, 0xE603); +SFRX(FIFORESET, 0xE604); +#define BMNAKALL bmbit7 + +SFRX(BREAKPT, 0xE605); +#define BMBREAK bmbit3 +#define BMBPPULSE bmbit2 +#define BMBPEN bmbit1 + +SFRX(BPADDRH, 0xE606); +SFRX(BPADDRL, 0xE607); +SFRX(UART230, 0xE608); +SFRX(FIFOPINPOLAR, 0xE609); +SFRX(REVID, 0xE60A); +SFRX(REVCTL, 0xE60B); +#define BMNOAUTOARM bmbit1 +#define BMSKIPCOMMIT bmbit0 + +/* Endpoint Configuration */ +SFRX(EP1OUTCFG, 0xE610); +SFRX(EP1INCFG, 0xE611); +SFRX(EP2CFG, 0xE612); +SFRX(EP4CFG, 0xE613); +SFRX(EP6CFG, 0xE614); +SFRX(EP8CFG, 0xE615); +SFRX(EP2FIFOCFG, 0xE618); +SFRX(EP4FIFOCFG, 0xE619); +SFRX(EP6FIFOCFG, 0xE61A); +SFRX(EP8FIFOCFG, 0xE61B); +#define BMINFM bmbit6 +#define BMOEP bmbit5 +#define BMAUTOOUT bmbit4 +#define BMAUTOIN bmbit3 +#define BMZEROLENIN bmbit2 +#define BMWORDWIDE bmbit0 + +SFRX(EP2AUTOINLENH, 0xE620); +SFRX(EP2AUTOINLENL, 0xE621); +SFRX(EP4AUTOINLENH, 0xE622); +SFRX(EP4AUTOINLENL, 0xE623); +SFRX(EP6AUTOINLENH, 0xE612); +SFRX(EP6AUTOINLENL, 0xE613); +SFRX(EP8AUTOINLENH, 0xE614); +SFRX(EP8AUTOINLENL, 0xE615); +SFRX(EP2FIFOPFH, 0xE630); +SFRX(EP2FIFOPFL, 0xE631); +SFRX(EP4FIFOPFH, 0xE632); +SFRX(EP4FIFOPFL, 0xE633); +SFRX(EP6FIFOPFH, 0xE634); +SFRX(EP6FIFOPFL, 0xE635); +SFRX(EP8FIFOPFH, 0xE636); +SFRX(EP8FIFOPFL, 0xE637); +SFRX(EP2ISOINPKTS, 0xE640); +SFRX(EP4ISOINPKTS, 0xE641); +SFRX(EP6ISOINPKTS, 0xE642); +SFRX(EP8ISOINPKTS, 0xE643); +SFRX(INPKTEND, 0xE648); +SFRX(OUTPKTEND, 0xE649); + +/* Interrupts */ +SFRX(EP2FIFOIE, 0xE650); +SFRX(EP2FIFOIRQ, 0xE651); +SFRX(EP4FIFOIE, 0xE652); +SFRX(EP4FIFOIRQ, 0xE653); +SFRX(EP6FIFOIE, 0xE654); +SFRX(EP6FIFOIRQ, 0xE655); +SFRX(EP8FIFOIE, 0xE656); +SFRX(EP8FIFOIRQ, 0xE657); +SFRX(IBNIE, 0xE658); +SFRX(IBNIRQ, 0xE659); +#define EP0IBN bmbit0 +#define EP1IBN bmbit1 +#define EP2IBN bmbit2 +#define EP4IBN bmbit3 +#define EP6IBN bmbit4 +#define EP8IBN bmbit5 + +SFRX(NAKIE, 0xE65A); +SFRX(NAKIRQ, 0xE65B); +#define EP8PING bmbit7 +#define EP6PING bmbit6 +#define EP4PING bmbit5 +#define EP2PING bmbit4 +#define EP1PING bmbit3 +#define EP0PING bmbit2 +#define IBN bmbit0 + +SFRX(USBIEN, 0xE65C); +SFRX(USBIRQ, 0xE65D); +#define SUDAVI bmbit0 +#define SOFI bmbit1 +#define SUTOKI bmbit2 +#define SUSPI bmbit3 +#define URESI bmbit4 +#define HSGRANT bmbit5 +#define EP0ACK bmbit6 + +SFRX(EPIE, 0xE65E); +SFRX(EPIRQ, 0xE65F); +SFRX(GPIFIE, 0xE660); +SFRX(GPIFIRQ, 0xE661); +SFRX(USBERRIE, 0xE662); +SFRX(USBERRIRQ, 0xE663); +SFRX(ERRCNTLIM, 0xE664); +SFRX(CLRERRCNT, 0xE665); +SFRX(INT2IVEC, 0xE666); +#define I2V0 bmbit2 +#define I2V1 bmbit3 +#define I2V2 bmbit4 +#define I2V3 bmbit5 +#define I2V4 bmbit6 + +SFRX(INT4IVEC, 0xE667); +SFRX(INTSETUP, 0xE668); +#define AV4EN bmbit0 +#define INT4IN bmbit1 +#define AV2EN bmbit3 + +/* Input/Output */ +SFRX(PORTACFG, 0xE670); +#define BMINT0 bmbit0 +#define BMINT1 bmbit1 +#define BMFLAGD bmbit7 + +SFRX(PORTCCFG, 0xE671); +#define BMGPIFA0 bmbit0 +#define BMGPIFA1 bmbit1 +#define BMGPIFA2 bmbit2 +#define BMGPIFA3 bmbit3 +#define BMGPIFA4 bmbit4 +#define BMGPIFA5 bmbit5 +#define BMGPIFA6 bmbit6 +#define BMGPIFA7 bmbit7 + +SFRX(PORTECFG, 0xE672); +#define BMT0OUT bmbit0 +#define BMT1OUT bmbit1 +#define BMT2OUT bmbit2 +#define BMRXD0OUT bmbit3 +#define BMRXD1OUT bmbit4 +#define BMINT6 bmbit5 +#define BMT2EX bmbit6 +#define BMGPIFA8 bmbit7 + +SFRX(I2CS, 0xE678); +#define BMDONE bmbit0 +#define BMACK bmbit1 +#define BMBERR bmbit2 +#define BMID (bmbit4 | bmbit3) +#define BMLASTRD bmbit5 +#define BMSTOP bmbit6 +#define BMSTART bmbit7 + +SFRX(I2DAT, 0xE679); +SFRX(I2CTL, 0xE67A); +#define BMSTOPIE bmbit1 +#define BM400KHZ bmbit0 + +SFRX(XAUTODAT1, 0xE67B); +SFRX(XAUTODAT2, 0xE67C); +#define EXTAUTODAT1 XAUTODAT1 +#define EXTAUTODAT2 XAUTODAT2 + +/* USB Control */ +SFRX(USBCS, 0xE680); +#define SIGRSUME bmbit0 +#define RENUM bmbit1 +#define NOSYNSOF bmbit2 +#define DISCON bmbit3 +#define HSM bmbit7 + +SFRX(SUSPEND, 0xE681); +SFRX(WAKEUPCS, 0xE682); +#define BMWU2 bmbit7 +#define BMWU bmbit6 +#define BMWU2POL bmbit5 +#define BMWUPOL bmbit4 +#define BMDPEN bmbit2 +#define BMWU2EN bmbit1 +#define BMWUEN bmbit0 + +SFRX(TOGCTL, 0xE683); +#define BMTOGCTLEPMASK bmbit3 | bmbit2 | bmbit1 | bmbit0 +#define BMRESETTOGGLE bmbit5 +#define BMSETTOGGLE bmbit6 +#define BMQUERYTOGGLE bmbit7 + +SFRX(USBFRAMEH, 0xE684); +SFRX(USBFRAMEL, 0xE685); +SFRX(MICROFRAME, 0xE686); +SFRX(FNADDR, 0xE687); + +/* Endpoints */ +SFRX(EP0BCH, 0xE68A); +SFRX(EP0BCL, 0xE68B); +SFRX(EP1OUTBC, 0xE68D); +SFRX(EP1INBC, 0xE68F); +SFRX(EP2BCH, 0xE690); +SFRX(EP2BCL, 0xE691); +SFRX(EP4BCH, 0xE694); +SFRX(EP4BCL, 0xE695); +SFRX(EP6BCH, 0xE698); +SFRX(EP6BCL, 0xE699); +SFRX(EP8BCH, 0xE69C); +SFRX(EP8BCL, 0xE69D); +SFRX(EP0CS, 0xE6A0); +#define HSNAK bmbit7 + +SFRX(EP1INCS, 0xE6A2); +SFRX(EP1OUTCS, 0xE6A1); +#define EPSTALL bmbit0 +#define EPBSY bmbit1 + +SFRX(EP2CS, 0xE6A3); +SFRX(EP4CS, 0xE6A4); +SFRX(EP6CS, 0xE6A5); +SFRX(EP8CS, 0xE6A6); +#define BMEPEMPTY bmbit2 +#define BMEPFULL bmbit3 +#define BMNPAK (bmbit6 | bmbit5 | bmbit4) + +SFRX(EP2FIFOFLGS, 0xE6A7); +SFRX(EP4FIFOFLGS, 0xE6A8); +SFRX(EP6FIFOFLGS, 0xE6A9); +SFRX(EP8FIFOFLGS, 0xE6AA); +SFRX(EP2FIFOBCH, 0xE6AB); +SFRX(EP2FIFOBCL, 0xE6AC); +SFRX(EP4FIFOBCH, 0xE6AD); +SFRX(EP4FIFOBCL, 0xE6AE); +SFRX(EP6FIFOBCH, 0xE6AF); +SFRX(EP6FIFOBCL, 0xE6B0); +SFRX(EP8FIFOBCH, 0xE6B1); +SFRX(EP8FIFOBCL, 0xE6B2); +SFRX(SUDPTRH, 0xE6B3); +SFRX(SUDPTRL, 0xE6B4); + +SFRX(SUDPTRCTL, 0xE6B5); +#define BMSDPAUTO bmbit0 + +SFRX(SETUPDAT[8], 0xE6B8); + +/* GPIF */ +SFRX(GPIFWFSELECT, 0xE6C0); +SFRX(GPIFIDLECS, 0xE6C1); +SFRX(GPIFIDLECTL, 0xE6C2); +SFRX(GPIFCTLCFG, 0xE6C3); +SFRX(GPIFADRH, 0xE6C4); +SFRX(GPIFADRL, 0xE6C5); +SFRX(GPIFTCB3, 0xE6CE); +SFRX(GPIFTCB2, 0xE6CF); +SFRX(GPIFTCB1, 0xE6D0); +SFRX(GPIFTCB0, 0xE6D1); + +#define EP2GPIFTCH GPIFTCB1 /* these are here for backwards compatibility */ +#define EP2GPIFTCL GPIFTCB0 +#define EP4GPIFTCH GPIFTCB1 /* these are here for backwards compatibility */ +#define EP4GPIFTCL GPIFTCB0 +#define EP6GPIFTCH GPIFTCB1 /* these are here for backwards compatibility */ +#define EP6GPIFTCL GPIFTCB0 +#define EP8GPIFTCH GPIFTCB1 /* these are here for backwards compatibility */ +#define EP8GPIFTCL GPIFTCB0 + +SFRX(EP2GPIFFLGSEL, 0xE6D2); +SFRX(EP2GPIFPFSTOP, 0xE6D3); +SFRX(EP2GPIFTRIG, 0xE6D4); +SFRX(EP4GPIFFLGSEL, 0xE6DA); +SFRX(EP4GPIFPFSTOP, 0xE6DB); +SFRX(EP4GPIFTRIG, 0xE6DC); +SFRX(EP6GPIFFLGSEL, 0xE6E2); +SFRX(EP6GPIFPFSTOP, 0xE6E3); +SFRX(EP6GPIFTRIG, 0xE6E4); +SFRX(EP8GPIFFLGSEL, 0xE6EA); +SFRX(EP8GPIFPFSTOP, 0xE6EB); +SFRX(EP8GPIFTRIG, 0xE6EC); +SFRX(XGPIFSGLDATH, 0xE6F0); +SFRX(XGPIFSGLDATLX, 0xE6F1); +SFRX(XGPIFSGLDATLNOX, 0xE6F2); +SFRX(GPIFREADYCFG, 0xE6F3); +SFRX(GPIFREADYSTAT, 0xE6F4); +SFRX(GPIFABORT, 0xE6F5); + +// UDMA +SFRX(FLOWSTATE, 0xE6C6); +SFRX(FLOWLOGIC, 0xE6C7); +SFRX(FLOWEQ0CTL, 0xE6C8); +SFRX(FLOWEQ1CTL, 0xE6C9); +SFRX(FLOWHOLDOFF, 0xE6CA); +SFRX(FLOWSTB, 0xE6CB); +SFRX(FLOWSTBEDGE, 0xE6CC); +SFRX(FLOWSTBHPERIOD, 0xE6CD); +SFRX(GPIFHOLDAMOUNT, 0xE60C); +SFRX(UDMACRCH, 0xE67D); +SFRX(UDMACRCL, 0xE67E); +SFRX(UDMACRCQUAL, 0xE67F); + +/* Debug/Test + * The following registers are for Cypress's internal testing purposes only. + * These registers are not documented in the datasheet or the Technical Reference + * Manual as they were not designed for end user application usage + */ +SFRX(DBUG, 0xE6F8); +SFRX(TESTCFG, 0xE6F9); +SFRX(USBTEST, 0xE6FA); +SFRX(CT1, 0xE6FB); +SFRX(CT2, 0xE6FC); +SFRX(CT3, 0xE6FD); +SFRX(CT4, 0xE6FE); + +/* Endpoint Buffers */ +SFRX(EP0BUF[64], 0xE740); +SFRX(EP1INBUF[64], 0xE7C0); +SFRX(EP1OUTBUF[64], 0xE780); +SFRX(EP2FIFOBUF[512], 0xF000); +SFRX(EP4FIFOBUF[512], 0xF400); +SFRX(EP6FIFOBUF[512], 0xF800); +SFRX(EP8FIFOBUF[512], 0xFC00); + +/* Error Correction Code (ECC) Registers (FX2LP/FX1 only) */ +SFRX(ECCCFG, 0xE628); +SFRX(ECCRESET, 0xE629); +SFRX(ECC1B0, 0xE62A); +SFRX(ECC1B1, 0xE62B); +SFRX(ECC1B2, 0xE62C); +SFRX(ECC2B0, 0xE62D); +SFRX(ECC2B1, 0xE62E); +SFRX(ECC2B2, 0xE62F); + +/* Feature Registers (FX2LP/FX1 only) */ +SFRX(GPCR2, 0xE50D); +#define BMFULLSPEEDONLY bmbit4 + +#endif diff --git a/contrib/firmware/angie/c/include/serial.h b/contrib/firmware/angie/c/include/serial.h new file mode 100644 index 0000000000..548c005603 --- /dev/null +++ b/contrib/firmware/angie/c/include/serial.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ + +/** + * This code was taken from the fx2lib project from this link: + * https://github.com/djmuhlestein/fx2lib + * + * Copyright (C) 2009 Ubixum, Inc. + **/ + +/** \file serial.h + * defines functions to print to a serial console with SIO0 + **/ + +#include "fx2macros.h" +#include +/** + * This function inits sio0 to use T2CON (timer 2) + * See TRM 14.3.4.1 (Table 14-16) + * Certain baud rates have too high an error rate to work. All baud rates are .16% + * except: + * + * 12MHZ 24MHZ + * \li 57600 -6.99% + * \li 38400 -2.34% -2.34% + * \li 19200 -2.34% + * + * Possible Baud rates: + * \li 2400 + * \li 4800 + * \li 9600 + * \li 19200 + * \li 28800 + * \li 38400 + * \li 57600 + * + * Any of these rates should work except 57600 at 12mhz. -2.34% is pushing + * most hardware specs for working. All rates at 48mhz work at .16% + **/ + +void sio0_init(uint32_t baud_rate) __critical; /* baud_rate max should be 57600 since int=2 bytes */ + +/** + * putchar('\\n') or putchar('\\r') both transmit \\r\\n + * Just use one or the other. (This makes terminal echo easy) + **/ +int putchar(char c); +int getchar(void); diff --git a/contrib/firmware/angie/c/include/usb.h b/contrib/firmware/angie/c/include/usb.h new file mode 100644 index 0000000000..ad8be787e4 --- /dev/null +++ b/contrib/firmware/angie/c/include/usb.h @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + File : usb.h * + Contents : usb communication handling header file for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#ifndef __USB_H +#define __USB_H + +#include "reg_ezusb.h" +#include +#include + +/* High and Low byte of a word (uint16_t) */ +#define HI8(word) (uint8_t)(((uint16_t)(word) >> 8) & 0xff) +#define LO8(word) (uint8_t)((uint16_t)(word) & 0xff) + +/* Convenience functions */ +#define STALL_EP0() (EP0CS |= EPSTALL) +#define CLEAR_IRQ() (USBINT = 0) + +/*********** USB descriptors. See USB 2.0 Spec **********/ + +/* USB Descriptor Types. See USB 2.0 Spec */ +#define DESCRIPTOR_TYPE_DEVICE 0x01 +#define DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define DESCRIPTOR_TYPE_STRING 0x03 +#define DESCRIPTOR_TYPE_INTERFACE 0x04 +#define DESCRIPTOR_TYPE_ENDPOINT 0x05 + +#define STR_DESCR(len, ...) { (len) * 2 + 2, DESCRIPTOR_TYPE_STRING, { __VA_ARGS__ } } + +/** USB Device Descriptor. See USB 2.0 Spec */ +struct usb_device_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< DEVICE Descriptor Type. */ + uint16_t bcdusb; /**< USB specification release number (BCD). */ + uint8_t bdeviceclass; /**< Class code. */ + uint8_t bdevicesubclass; /**< Subclass code. */ + uint8_t bdeviceprotocol; /**< Protocol code. */ + uint8_t bmaxpacketsize0; /**< Maximum packet size for EP0 (8, 16, 32, 64). */ + uint16_t idvendor; /**< USB Vendor ID. */ + uint16_t idproduct; /**< USB Product ID. */ + uint16_t bcddevice; /**< Device Release Number (BCD). */ + uint8_t imanufacturer; /**< Index of manufacturer string descriptor. */ + uint8_t iproduct; /**< Index of product string descriptor. */ + uint8_t iserialnumber; /**< Index of string descriptor containing serial #. */ + uint8_t bnumconfigurations; /**< Number of possible configurations. */ +}; + +/** USB Configuration Descriptor. See USB 2.0 Spec */ +struct usb_config_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< CONFIGURATION descriptor type. */ + uint16_t wtotallength; /**< Combined total length of all descriptors. */ + uint8_t bnuminterfaces; /**< Number of interfaces in this configuration. */ + uint8_t bconfigurationvalue; /**< Value used to select this configuration. */ + uint8_t iconfiguration; /**< Index of configuration string descriptor. */ + uint8_t bmattributes; /**< Configuration characteristics. */ + uint8_t maxpower; /**< Maximum power consumption in 2 mA units. */ +}; + +/** USB Interface association Descriptor. See USB 2.0 Spec */ +struct usb_interface_association_descriptor { + uint8_t blength; + uint8_t bdescriptortype; + uint8_t bfirstinterface; + uint8_t binterfacecount; + uint8_t bfunctionclass; + uint8_t bfunctionsubclass; + uint8_t bfunctionprotocol; + uint8_t ifunction; +}; + +/** USB Interface Descriptor. See USB 2.0 Spec */ +struct usb_interface_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< INTERFACE descriptor type. */ + uint8_t binterfacenumber; /**< Interface number. */ + uint8_t balternatesetting; /**< Value used to select alternate setting. */ + uint8_t bnumendpoints; /**< Number of endpoints used by this interface. */ + uint8_t binterfaceclass; /**< Class code. */ + uint8_t binterfacesubclass; /**< Subclass code. */ + uint8_t binterfaceprotocol; /**< Protocol code. */ + uint8_t iinterface; /**< Index of interface string descriptor. */ +}; + +/** USB Endpoint Descriptor. See USB 2.0 Spec */ +struct usb_endpoint_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< ENDPOINT descriptor type. */ + uint8_t bendpointaddress; /**< Endpoint Address: IN/OUT + EP number. */ + uint8_t bmattributes; /**< Endpoint Attributes: BULK/INTR/ISO/CTRL. */ + uint16_t wmaxpacketsize; /**< Maximum packet size for this endpoint. */ + uint8_t binterval; /**< Polling interval (in ms) for this endpoint. */ +}; + +/** USB Language Descriptor. See USB 2.0 Spec */ +struct usb_language_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< STRING descriptor type. */ + uint16_t wlangid[]; /**< LANGID codes. */ +}; + +/** USB String Descriptor. See USB 2.0 Spec */ +struct usb_string_descriptor { + uint8_t blength; /**< Size of this descriptor in bytes. */ + uint8_t bdescriptortype; /**< STRING descriptor type. */ + uint16_t bstring[]; /**< UNICODE encoded string. */ +}; + +/********************** USB Control Endpoint 0 related *********************/ + +/** USB Control Setup Data. See USB 2.0 Spec */ +struct setup_data { + uint8_t bmrequesttype; /**< Characteristics of a request. */ + uint8_t brequest; /**< Specific request. */ + uint16_t wvalue; /**< Field that varies according to request. */ + uint16_t windex; /**< Field that varies according to request. */ + uint16_t wlength; /**< Number of bytes to transfer in data stage. */ +}; + +/* External declarations for variables that need to be accessed outside of + * the USB module */ +extern volatile bool ep1_out; +extern volatile bool ep1_in; +extern volatile bool ep6_out; + +extern volatile __xdata __at 0xE6B8 struct setup_data setup_data; + +/* + * USB Request Types (bmRequestType): See USB 2.0 Spec + * + * Bit 7: Data transfer direction + * 0 = Host-to-device + * 1 = Device-to-host + * Bit 6...5: Type + * 0 = Standard + * 1 = Class + * 2 = Vendor + * 3 = Reserved + * Bit 4...0: Recipient + * 0 = Device + * 1 = Interface + * 2 = Endpoint + * 3 = Other + * 4...31 = Reserved + */ + +#define USB_DIR_OUT 0x00 +#define USB_DIR_IN 0x80 + +#define USB_REQ_TYPE_STANDARD (0x00 << 5) +#define USB_REQ_TYPE_CLASS (0x01 << 5) +#define USB_REQ_TYPE_VENDOR (0x02 << 5) +#define USB_REQ_TYPE_RESERVED (0x03 << 5) + +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* Clear Interface Request */ +#define CF_DEVICE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) +#define CF_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE) +#define CF_ENDPOINT (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT) + +/* Get Configuration Request */ +#define GC_DEVICE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) + +/* Get Descriptor Request */ +#define GD_DEVICE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) + +/* Get Interface Request */ +#define GI_INTERFACE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE) + +/* Get Status Request: See USB 1.1 spec, page 190 */ +#define GS_DEVICE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) +#define GS_INTERFACE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE) +#define GS_ENDPOINT (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT) + +/* Set Address Request is handled by EZ-USB core */ + +/* Set Configuration Request */ +#define SC_DEVICE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) + +/* Set Descriptor Request */ +#define SD_DEVICE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) + +/* Set Feature Request */ +#define SF_DEVICE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE) +#define SF_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE) +#define SF_ENDPOINT (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT) + +/* Set Interface Request */ +#define SI_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE) + +/* Synch Frame Request */ +#define SY_ENDPOINT (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT) + +/* USB Requests (bRequest): See USB 2.0 Spec */ +#define GET_STATUS 0 +#define CLEAR_FEATURE 1 +/* Value '2' is reserved for future use */ +#define SET_FEATURE 3 +/* Value '4' is reserved for future use */ +#define SET_ADDRESS 5 +#define GET_DESCRIPTOR 6 +#define SET_DESCRIPTOR 7 +#define GET_CONFIGURATION 8 +#define SET_CONFIGURATION 9 +#define GET_INTERFACE 10 +#define SET_INTERFACE 11 +#define SYNCH_FRAME 12 + +/* Standard Feature Selectors: See USB 2.0 Spec */ +#define DEVICE_REMOTE_WAKEUP 1 +#define ENDPOINT_HALT 0 + +/************************** EZ-USB specific stuff **************************/ +/** USB Interrupts. See EZ-USB FX2-TRM, for details */ +enum usb_isr { + SUDAV_ISR = 13, + SOF_ISR, + SUTOK_ISR, + SUSPEND_ISR, + USBRESET_ISR, + HIGHSPEED_ISR, + EP0ACK_ISR, + STUB_ISR, + EP0IN_ISR, + EP0OUT_ISR, + EP1IN_ISR, + EP1OUT_ISR, + EP2_ISR, + EP4_ISR, + EP6_ISR, + EP8_ISR, + IBN_ISR, + EP0PINGNAK_ISR, + EP1PINGNAK_ISR, + EP2PINGNAK_ISR, + EP4PINGNAK_ISR, + EP6PINGNAK_ISR, + EP8PINGNAK_ISR, + ERRORLIMIT_ISR, + EP2PIDERROR_ISR, + EP4PIDERROR_ISR, + EP6PIDERROR_ISR, + EP8PIDERROR_ISR, + EP2PFLAG_ISR, + EP4PFLAG_ISR, + EP6PFLAG_ISR, + EP8PFLAG_ISR, + EP2EFLAG_ISR, + EP4EFLAG_ISR, + EP6EFLAG_ISR, + EP8EFLAG_ISR, + EP2FFLAG_ISR, + EP4FFLAG_ISR, + EP6FFLAG_ISR, + EP8FFLAG_ISR, + GPIFCOMPLETE_ISR, + GPIFWAVEFORM_ISR +}; + +/*************************** Function Prototypes ***************************/ +__xdata uint8_t *usb_get_endpoint_cs_reg(uint8_t ep); +void usb_reset_data_toggle(uint8_t ep); +bool usb_handle_get_status(void); +bool usb_handle_clear_feature(void); +bool usb_handle_set_feature(void); +bool usb_handle_get_descriptor(void); +void usb_handle_set_interface(void); +void usb_handle_setup_data(void); +void usb_handle_i2c_in(void); +void usb_handle_i2c_out(void); + +void i2c_recieve(void); +void ep_init(void); +void interrupt_init(void); +void io_init(void); + +#endif diff --git a/contrib/firmware/angie/c/src/USBJmpTb.a51 b/contrib/firmware/angie/c/src/USBJmpTb.a51 new file mode 100644 index 0000000000..13b5f7218b --- /dev/null +++ b/contrib/firmware/angie/c/src/USBJmpTb.a51 @@ -0,0 +1,125 @@ +; SPDX-License-Identifier: GPL-2.0-or-later +;**************************************************************************** +; File : USBJmpTb.a51 * +; Contents : Interruptions vector configuration. * +; Based on openULINK project code by: Martin Schmoelzer. * +; Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * +; * +; * +;**************************************************************************** +.module JUMPTABLE + +.globl USB_AutoVector +.globl USB_Jump_Table + +.globl _sudav_isr, _sof_isr, _sutok_isr, _suspend_isr, _usbreset_isr, _highspeed_isr, _ep0ack_isr, _stub_isr, _ep0in_isr, _ep0out_isr, _ep1in_isr, _ep1out_isr, _ep2_isr, _ep4_isr, _ep6_isr, _ep8_isr, _ibn_isr +.globl _ep0pingnak_isr, _ep1pingnak_isr, _ep2pingnak_isr, _ep4pingnak_isr, _ep6pingnak_isr, _ep8pingnak_isr, _errorlimit_isr, _stub_isr, _stub_isr, _stub_isr, _ep2piderror_isr, _ep4piderror_isr, _ep6piderror_isr, _ep8piderror_isr +.globl _ep2pflag_isr, _ep4pflag_isr, _ep6pflag_isr, _ep8pflag_isr, _ep2eflag_isr, _ep4eflag_isr, _ep6eflag_isr, _ep8eflag_isr, _ep2fflag_isr, _ep4fflag_isr, _ep6fflag_isr, _ep8fflag_isr, _gpifcomplete_isr, _gpifwaveform_isr + +;--------------------------------------------------------------------------; +; Interrupt Vectors ; +;--------------------------------------------------------------------------; +.area USB_JV (ABS,OVR) ; Absolute, Overlay +.org 0x43 ; USB interrupt (INT2) jumps here +USB_AutoVector = #. + 2 + ljmp USB_Jump_Table ; Autovector will replace byte 45 + +;--------------------------------------------------------------------------; +; USB Jump Table ; +;--------------------------------------------------------------------------; +.area USB_JT (ABS) ; Absolute placement +.org 0x0200 ; Place jump table at 0x0200 + +USB_Jump_Table: ; autovector jump table + ljmp _sudav_isr ; (00) Setup Data Available + .db 0 + ljmp _sof_isr ; (04) Start of Frame + .db 0 + ljmp _sutok_isr ; (08) Setup Data Loading + .db 0 + ljmp _suspend_isr ; (0C) Global Suspend + .db 0 + ljmp _usbreset_isr ; (10) USB Reset + .db 0 + ljmp _highspeed_isr ; (14) Entered High Speed + .db 0 + ljmp _ep0ack_isr ; (18) EP0ACK + .db 0 + ljmp _stub_isr ; (1C) Reserved + .db 0 + ljmp _ep0in_isr ; (20) EP0 In + .db 0 + ljmp _ep0out_isr ; (24) EP0 Out + .db 0 + ljmp _ep1in_isr ; (28) EP1 In + .db 0 + ljmp _ep1out_isr ; (2C) EP1 Out + .db 0 + ljmp _ep2_isr ; (30) EP2 In/Out + .db 0 + ljmp _ep4_isr ; (34) EP4 In/Out + .db 0 + ljmp _ep6_isr ; (38) EP6 In/Out + .db 0 + ljmp _ep8_isr ; (3C) EP8 In/Out + .db 0 + ljmp _ibn_isr ; (40) IBN + .db 0 + ljmp _stub_isr ; (44) Reserved + .db 0 + ljmp _ep0pingnak_isr ; (48) EP0 PING NAK + .db 0 + ljmp _ep1pingnak_isr ; (4C) EP1 PING NAK + .db 0 + ljmp _ep2pingnak_isr ; (50) EP2 PING NAK + .db 0 + ljmp _ep4pingnak_isr ; (54) EP4 PING NAK + .db 0 + ljmp _ep6pingnak_isr ; (58) EP6 PING NAK + .db 0 + ljmp _ep8pingnak_isr ; (5C) EP8 PING NAK + .db 0 + ljmp _errorlimit_isr ; (60) Error Limit + .db 0 + ljmp _stub_isr ; (64) Reserved + .db 0 + ljmp _stub_isr ; (68) Reserved + .db 0 + ljmp _stub_isr ; (6C) Reserved + .db 0 + ljmp _ep2piderror_isr ; (70) EP2 ISO Pid Sequence Error + .db 0 + ljmp _ep4piderror_isr ; (74) EP4 ISO Pid Sequence Error + .db 0 + ljmp _ep6piderror_isr ; (78) EP6 ISO Pid Sequence Error + .db 0 + ljmp _ep8piderror_isr ; (7C) EP8 ISO Pid Sequence Error + .db 0 + ljmp _ep2pflag_isr ; (80) EP2 Programmable Flag + .db 0 + ljmp _ep4pflag_isr ; (84) EP4 Programmable Flag + .db 0 + ljmp _ep6pflag_isr ; (88) EP6 Programmable Flag + .db 0 + ljmp _ep8pflag_isr ; (8C) EP8 Programmable Flag + .db 0 + ljmp _ep2eflag_isr ; (90) EP2 Empty Flag + .db 0 + ljmp _ep4eflag_isr ; (94) EP4 Empty Flag + .db 0 + ljmp _ep6eflag_isr ; (98) EP6 Empty Flag + .db 0 + ljmp _ep8eflag_isr ; (9C) EP8 Empty Flag + .db 0 + ljmp _ep2fflag_isr ; (A0) EP2 Full Flag + .db 0 + ljmp _ep4fflag_isr ; (A4) EP4 Full Flag + .db 0 + ljmp _ep6fflag_isr ; (A8) EP6 Full Flag + .db 0 + ljmp _ep8fflag_isr ; (AC) EP8 Full Flag + .db 0 + ljmp _gpifcomplete_isr ; (B0) GPIF Operation Complete + .db 0 + ljmp _gpifwaveform_isr ; (B4) GPIF Waveform + .db 0 diff --git a/contrib/firmware/angie/c/src/delay.c b/contrib/firmware/angie/c/src/delay.c new file mode 100644 index 0000000000..471e160dd4 --- /dev/null +++ b/contrib/firmware/angie/c/src/delay.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/**************************************************************************** + File : delay.c * + Contents : Delays handling fucntions code for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "delay.h" +#include + +void syncdelay(uint8_t count) +{ + for (uint8_t i = 0; i < count; i++) + NOP(); +} + +void delay_5us(void) +{ + NOP(); +} + +void delay_1ms(void) +{ + uint16_t i; + + for (i = 0; i < 598; i++) + ; +} + +void delay_us(uint16_t delay) +{ + uint16_t i; + uint16_t maxcount = (delay / 5); + + for (i = 0; i < maxcount; i++) + delay_5us(); +} + +void delay_ms(uint16_t delay) +{ + uint16_t i; + + for (i = 0; i < delay; i++) + delay_1ms(); +} diff --git a/contrib/firmware/angie/c/src/gpif.c b/contrib/firmware/angie/c/src/gpif.c new file mode 100644 index 0000000000..f4028be400 --- /dev/null +++ b/contrib/firmware/angie/c/src/gpif.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + This program configures the General Programmable Interface (GPIF) for FX2. + Please do not modify sections of text which are marked as "DO NOT EDIT ...". +*/ + +/* GPIF Program Code */ + +#include "reg_ezusb.h" +#include "delay.h" + +/****************************** GPIF PROGRAM CODE ********************************/ +/* DO NOT EDIT ... */ +const char wavedata[128] = { +// Wave 0 +/* LenBr */ 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, +/* Output*/ 0x04, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +}; +/* END DO NOT EDIT */ + +/* DO NOT EDIT ... */ +const char flowstates[36] = { +/* Wave 0 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Wave 1 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Wave 2 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Wave 3 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +/* END DO NOT EDIT */ + +/* DO NOT EDIT ... */ +const char initdata[7] = { +/* Regs */ 0xE0, 0x00, 0x00, 0x07, 0xEE, 0xF2, 0x00 +}; +/* END DO NOT EDIT */ + +void gpif_init(void) +{ + uint8_t i; + + IFCONFIG = 0xEE; + + GPIFABORT = 0xFF; /* abort any waveforms pending */ + GPIFREADYCFG = initdata[0]; + GPIFCTLCFG = initdata[1]; + GPIFIDLECS = initdata[2]; + GPIFIDLECTL = initdata[3]; + GPIFWFSELECT = initdata[5]; + GPIFREADYSTAT = initdata[6]; + + /* use dual autopointer feature... */ + AUTOPTRSETUP = 0x07; + + /* source */ + AUTOPTRH1 = (uint8_t)(((uint16_t)(&wavedata) >> 8) & 0xff); + AUTOPTRL1 = (uint8_t)((uint16_t)(&wavedata) & 0xff); + + /* destination */ + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + /* transfer */ + for (i = 0x00; i < 128; i++) + EXTAUTODAT2 = EXTAUTODAT1; + + /* GPIF address pins update when GPIFADRH/L written */ + syncdelay(3); + GPIFADRH = 0x00; /* bits[7:1] always 0 */ + syncdelay(3); + GPIFADRL = 0x00; /* point to PERIPHERAL address 0x0000 */ + + /* Configure GPIF flowstates registers for Wave 0 of wavedata */ + FLOWSTATE = flowstates[0]; + FLOWLOGIC = flowstates[1]; + FLOWEQ0CTL = flowstates[2]; + FLOWEQ1CTL = flowstates[3]; + FLOWHOLDOFF = flowstates[4]; + FLOWSTB = flowstates[5]; + FLOWSTBEDGE = flowstates[6]; + FLOWSTBHPERIOD = flowstates[7]; +} diff --git a/contrib/firmware/angie/c/src/i2c.c b/contrib/firmware/angie/c/src/i2c.c new file mode 100644 index 0000000000..10a463bf7d --- /dev/null +++ b/contrib/firmware/angie/c/src/i2c.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/**************************************************************************** + File : i2c.cpp * + Contents : i2c bit-bang library * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "i2c.h" +#include "io.h" +#include "delay.h" +#include "reg_ezusb.h" + +void start_cd(void) +{ + PIN_SCL_DIR = 0; + PIN_SDA_DIR = 0; + delay_us(10); + PIN_SDA = 0; //SDA = 1; + delay_us(1); + PIN_SCL = 0; //SCL = 1; + delay_us(1); +} + +void repeated_start(void) +{ + PIN_SDA = 1; + delay_us(1); + PIN_SCL = 1; + delay_us(1); + PIN_SDA = 0; + delay_us(1); + PIN_SCL = 0; + delay_us(1); +} + +void stop_cd(void) +{ + PIN_SDA = 0; + delay_us(1); + PIN_SCL = 1; + delay_us(1); + PIN_SDA = 1; + delay_us(1); + PIN_SDA_DIR = 1; + delay_us(1); + PIN_SCL_DIR = 1; + delay_us(1); +} + +void clock_cd(void) +{ + PIN_SCL = 1; + delay_us(1); + PIN_SCL = 0; + delay_us(1); +} + +void send_ack(void) +{ + PIN_SDA = 0; + delay_us(1); + PIN_SCL = 1; + delay_us(1); + PIN_SCL = 0; + delay_us(1); +} + +void send_nack(void) +{ + PIN_SDA = 1; + delay_us(1); + PIN_SCL = 1; + delay_us(1); + PIN_SCL = 0; + delay_us(1); +} + +bool get_ack(void) +{ + PIN_SDA_DIR = 1; + delay_us(1); + OED = 0xFE; + PIN_SCL = 1; + delay_us(1); + bool ack = PIN_SDA; + PIN_SCL = 0; + delay_us(1); + OED = 0xFF; + PIN_SDA_DIR = 0; + delay_us(1); + return ack; +} + +/* here address(8 bits) = adr (7 bits) + type (1 bit) */ +uint8_t get_address(uint8_t adr, uint8_t rdwr) +{ + adr &= 0x7F; + adr = adr << 1; + adr |= (rdwr & 0x01); + return adr; +} + +/* here send bit after bit and clocking scl with each bit */ +void send_byte(uint8_t input) +{ + for (uint8_t i = 0; i < 8; i++) { + if ((input & 0x80)) { + PIN_SDA = 1; + delay_us(1); + clock_cd(); + } else { + PIN_SDA = 0; + delay_us(1); + clock_cd(); + } + input = input << 1; + } +} + +/* here receive bit after bit and clocking scl with each bit */ + +uint8_t receive_byte(void) +{ + PIN_SDA_DIR = 1; //FX2 <-- FPGA + OED = 0xFE; + uint8_t input = 0x00; + for (uint8_t i = 0; i < 8; i++) { + PIN_SCL = 1; + delay_us(1); + input = input << 1; + if (PIN_SDA == 1) + input |= 0x01; + else + input |= 0X00; + + PIN_SCL = 0; + delay_us(1); + } + OED = 0xFF; + PIN_SDA_DIR = 0; + return input; +} diff --git a/contrib/firmware/angie/c/src/jtag.c b/contrib/firmware/angie/c/src/jtag.c new file mode 100644 index 0000000000..9a44cd0bfc --- /dev/null +++ b/contrib/firmware/angie/c/src/jtag.c @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/**************************************************************************** + File : jtag.c * + Contents : Jtag handling functions code for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "jtag.h" +#include "io.h" +#include "msgtypes.h" +#include "reg_ezusb.h" +#include +#include +#include + +/** Delay value for SCAN_IN operations with less than maximum TCK frequency */ +uint8_t delay_scan_in; + +/** Delay value for SCAN_OUT operations with less than maximum TCK frequency */ +uint8_t delay_scan_out; + +/** Delay value for SCAN_IO operations with less than maximum TCK frequency */ +uint8_t delay_scan_io; + +/** Delay value for CLOCK_TCK operations with less than maximum frequency */ +uint8_t delay_tck; + +/** Delay value for CLOCK_TMS operations with less than maximum frequency */ +uint8_t delay_tms; + +/** + * Perform JTAG SCAN-IN operation at maximum TCK frequency. + * + * Dummy data is shifted into the JTAG chain via TDI, TDO data is sampled and + * stored in the EP2 IN buffer. + * + * Maximum achievable TCK frequency is 182 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + * @param in_offset + */ +void jtag_scan_in(uint8_t out_offset, uint8_t in_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdo_data, i, j; + + uint8_t outb_buffer; + + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_clock_tms(tms_count_start, tms_sequence_start); + + outb_buffer = IOB & ~(bmbit1 | bmbit2 | bmbit3); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdo_data = 0; + + for (j = 0; j < 8; j++) { + IOB = outb_buffer; /* TCK changes here */ + tdo_data = tdo_data >> 1; + IOB = (outb_buffer | bmbit2); + + if (PIN_TDO) + tdo_data |= 0x80; + } + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + } + tdo_data = 0; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + + IOB = outb_buffer; /* TCK changes here */ + tdo_data = tdo_data >> 1; + IOB = (outb_buffer | bmbit2); + + if (PIN_TDO) + tdo_data |= 0x80; + } + tdo_data = tdo_data >> (8 - bits_last_byte); + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_clock_tms(tms_count_end, tms_sequence_end); +} + + +/** + * Perform JTAG SCAN-IN operation at variable TCK frequency. + * + * Dummy data is shifted into the JTAG chain via TDI, TDO data is sampled and + * stored in the EP2 IN buffer. + * + * Maximum achievable TCK frequency is 113 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + * @param in_offset + */ +void jtag_slow_scan_in(uint8_t out_offset, uint8_t in_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdo_data, i, j, k; + uint8_t outb_buffer; + + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_slow_clock_tms(tms_count_start, tms_sequence_start); + + outb_buffer = IOB & ~(bmbit3 | bmbit2 | bmbit1); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdo_data = 0; + + for (j = 0; j < 8; j++) { + IOB = outb_buffer; /* TCK changes here */ + for (k = 0; k < delay_scan_in; k++) + ; + tdo_data = tdo_data >> 1; + + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_in; k++) + ; + + if (PIN_TDO) + tdo_data |= 0x80; + } + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + } + + tdo_data = 0; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + + IOB = outb_buffer; /* TCK changes here */ + for (k = 0; k < delay_scan_in; k++) + ; + tdo_data = tdo_data >> 1; + + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_in; k++) + ; + + if (PIN_TDO) + tdo_data |= 0x80; + } + tdo_data = tdo_data >> (8 - bits_last_byte); + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_slow_clock_tms(tms_count_end, tms_sequence_end); +} + + +/** + * Perform JTAG SCAN-OUT operation at maximum TCK frequency. + * + * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO + * data is not sampled. + * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state. + * + * Maximum achievable TCK frequency is 142 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + */ +void jtag_scan_out(uint8_t out_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdi_data, i, j; + uint8_t outb_buffer; + + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_clock_tms(tms_count_start, tms_sequence_start); + outb_buffer = IOB & ~(bmbit2 | bmbit1); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdi_data = EP1OUTBUF[i + out_offset + 5]; + + for (j = 0; j < 8; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + + IOB = outb_buffer; /* TDI and TCK change here */ + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + } + } + tdi_data = EP1OUTBUF[i + out_offset + 5]; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + IOB = outb_buffer; /* TDI and TCK change here */ + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + } + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_clock_tms(tms_count_end, tms_sequence_end); +} + +/** + * Perform JTAG SCAN-OUT operation at maximum TCK frequency. + * + * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO + * data is not sampled. + * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state. + * + * Maximum achievable TCK frequency is 97 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + */ +void jtag_slow_scan_out(uint8_t out_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdi_data, i, j, k; + uint8_t outb_buffer; + + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_slow_clock_tms(tms_count_start, tms_sequence_start); + outb_buffer = IOB & ~(bmbit2 | bmbit1); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdi_data = EP1OUTBUF[i + out_offset + 5]; + + for (j = 0; j < 8; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + IOB = outb_buffer; /* TDI and TCK change here */ + for (k = 0; k < delay_scan_out; k++) + ; + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_out; k++) + ; + } + } + tdi_data = EP1OUTBUF[i + out_offset + 5]; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + IOB = outb_buffer; /* TDI and TCK change here */ + for (k = 0; k < delay_scan_out; k++) + ; + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_out; k++) + ; + } + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_slow_clock_tms(tms_count_end, tms_sequence_end); +} + + +/** + * Perform bidirectional JTAG SCAN operation at maximum TCK frequency. + * + * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO + * data is sampled and stored in the EP2 IN buffer. + * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state. + * + * Maximum achievable TCK frequency is 100 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + * @param in_offset + */ +int it; +void jtag_scan_io(uint8_t out_offset, uint8_t in_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdi_data, tdo_data, i, j; + uint8_t outb_buffer; + + it++; + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_clock_tms(tms_count_start, tms_sequence_start); + outb_buffer = IOB & ~(bmbit2 | bmbit1); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdi_data = EP1OUTBUF[i + out_offset + 5]; + tdo_data = 0; + for (j = 0; j < 8; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + IOB = outb_buffer; /* TDI and TCK change here */ + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + tdo_data = tdo_data >> 1; + if (PIN_TDO) + tdo_data |= 0x80; + } + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + } + tdi_data = EP1OUTBUF[i + out_offset + 5]; + tdo_data = 0; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + IOB = outb_buffer; /* TDI and TCK change here */ + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + tdo_data = tdo_data >> 1; + if (PIN_TDO) + tdo_data |= 0x80; + } + tdo_data = tdo_data >> (8 - bits_last_byte); + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_clock_tms(tms_count_end, tms_sequence_end); +} + +/** + * Perform bidirectional JTAG SCAN operation at maximum TCK frequency. + * + * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO + * data is sampled and stored in the EP2 IN buffer. + * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state. + * + * Maximum achievable TCK frequency is 78 kHz for ANGIE clocked at 24 MHz. + * + * @param out_offset offset in EP1OUTBUF where payload data starts + * @param in_offset + */ +void jtag_slow_scan_io(uint8_t out_offset, uint8_t in_offset) +{ + uint8_t scan_size_bytes, bits_last_byte; + uint8_t tms_count_start, tms_count_end; + uint8_t tms_sequence_start, tms_sequence_end; + uint8_t tdi_data, tdo_data, i, j, k; + uint8_t outb_buffer; + + /* Get parameters from EP1OUTBUF */ + scan_size_bytes = EP1OUTBUF[out_offset]; + bits_last_byte = EP1OUTBUF[out_offset + 1]; + tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F; + tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F; + tms_sequence_start = EP1OUTBUF[out_offset + 3]; + tms_sequence_end = EP1OUTBUF[out_offset + 4]; + + if (tms_count_start > 0) + jtag_slow_clock_tms(tms_count_start, tms_sequence_start); + outb_buffer = IOB & ~(bmbit2 | bmbit1); + + /* Shift all bytes except the last byte */ + for (i = 0; i < scan_size_bytes - 1; i++) { + tdi_data = EP1OUTBUF[i + out_offset + 5]; + tdo_data = 0; + for (j = 0; j < 8; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + IOB = outb_buffer; /* TDI and TCK change here */ + for (k = 0; k < delay_scan_io; k++) + ; + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_io; k++) + ; + tdo_data = tdo_data >> 1; + if (PIN_TDO) + tdo_data |= 0x80; + } + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + } + tdi_data = EP1OUTBUF[i + out_offset + 5]; + tdo_data = 0; + + /* Shift the last byte */ + for (j = 0; j < bits_last_byte; j++) { + if (tdi_data & 0x01) + outb_buffer |= bmbit3; + else + outb_buffer &= ~bmbit3; + + /* Assert TMS signal if requested and this is the last bit */ + if (j == (bits_last_byte - 1) && tms_count_end > 0) { + outb_buffer |= bmbit1; + tms_count_end--; + tms_sequence_end = tms_sequence_end >> 1; + } + IOB = outb_buffer; /* TDI and TCK change here */ + for (k = 0; k < delay_scan_io; k++) + ; + tdi_data = tdi_data >> 1; + IOB = (outb_buffer | bmbit2); + for (k = 0; k < delay_scan_io; k++) + ; + tdo_data = tdo_data >> 1; + if (PIN_TDO) + tdo_data |= 0x80; + } + tdo_data = tdo_data >> (8 - bits_last_byte); + + /* Copy TDO data to EP1INBUF */ + EP1INBUF[i + in_offset] = tdo_data; + + /* Move to correct end state */ + if (tms_count_end > 0) + jtag_slow_clock_tms(tms_count_end, tms_sequence_end); +} + +/** + * Generate TCK clock cycles. + * + * Maximum achievable TCK frequency is 375 kHz for ANGIE clocked at 24 MHz. + * + * @param count number of TCK clock cycles to generate. + */ +void jtag_clock_tck(uint16_t count) +{ + uint16_t i; + uint8_t outb_buffer = IOB & ~(bmbit2); + + for (i = 0; i < count; i++) { + IOB = outb_buffer; + IOB = outb_buffer | bmbit2; + } +} + +/** + * Generate TCK clock cycles at variable frequency. + * + * Maximum achievable TCK frequency is 166.6 kHz for ANGIE clocked at 24 MHz. + * + * @param count number of TCK clock cycles to generate. + */ +void jtag_slow_clock_tck(uint16_t count) +{ + uint16_t i; + uint8_t j; + uint8_t outb_buffer = IOB & ~(bmbit2); + + for (i = 0; i < count; i++) { + IOB = outb_buffer; + for (j = 0; j < delay_tck; j++) + ; + IOB = outb_buffer | bmbit2; + for (j = 0; j < delay_tck; j++) + ; + } +} + +/** + * Perform TAP FSM state transitions at maximum TCK frequency. + * + * Maximum achievable TCK frequency is 176 kHz for ANGIE clocked at 24 MHz. + * + * @param count the number of state transitions to perform. + * @param sequence the TMS pin levels for each state transition, starting with + * the least-significant bit. + */ +void jtag_clock_tms(uint8_t count, uint8_t sequence) +{ + uint8_t outb_buffer = IOB & ~(bmbit2); + uint8_t i; + + for (i = 0; i < count; i++) { + /* Set TMS pin according to sequence parameter */ + if (sequence & 0x1) + outb_buffer |= bmbit1; + else + outb_buffer &= ~bmbit1; + IOB = outb_buffer; + sequence = sequence >> 1; + IOB = outb_buffer | bmbit2; + } +} + +/** + * Perform TAP-FSM state transitions at less than maximum TCK frequency. + * + * Maximum achievable TCK frequency is 117 kHz for ANGIE clocked at 24 MHz. + * + * @param count the number of state transitions to perform. + * @param sequence the TMS pin levels for each state transition, starting with + * the least-significant bit. + */ +void jtag_slow_clock_tms(uint8_t count, uint8_t sequence) +{ + uint8_t outb_buffer = IOB & ~(bmbit2); + uint8_t i, j; + + for (i = 0; i < count; i++) { + /* Set TMS pin according to sequence parameter */ + if (sequence & 0x1) + outb_buffer |= bmbit1; + else + outb_buffer &= ~bmbit1; + IOB = outb_buffer; + for (j = 0; j < delay_tms; j++) + ; + sequence = sequence >> 1; + IOB = outb_buffer | bmbit2; + for (j = 0; j < delay_tms; j++) + ; + } +} + +uint16_t jtag_get_signals(void) +{ + uint8_t input_signal_state, output_signal_state; + input_signal_state = 0; + output_signal_state = 0; + + /* Get states of input pins */ + if (PIN_TDO) + input_signal_state |= SIGNAL_TDO; + + /* Get states of output pins */ + output_signal_state = IOB & MASK_PORTB_DIRECTION_OUT; + + return ((uint16_t)input_signal_state << 8) | ((uint16_t)output_signal_state); +} + +/** + * Set state of JTAG output signals. + * + * @param low signals which should be de-asserted. + * @param high signals which should be asserted. + */ +void jtag_set_signals(uint8_t low, uint8_t high) +{ + IOB &= ~(low & MASK_PORTB_DIRECTION_OUT); + IOB |= (high & MASK_PORTB_DIRECTION_OUT); +} + +/** + * Configure TCK delay parameters. + * + * @param scan_in number of delay cycles in scan_in operations. + * @param scan_out number of delay cycles in scan_out operations. + * @param scan_io number of delay cycles in scan_io operations. + * @param tck number of delay cycles in clock_tck operations. + * @param tms number of delay cycles in clock_tms operations. + */ +void jtag_configure_tck_delay(uint8_t scan_in, uint8_t scan_out, + uint8_t scan_io, uint8_t tck, uint8_t tms) +{ + delay_scan_in = scan_in; + delay_scan_out = scan_out; + delay_scan_io = scan_io; + delay_tck = tck; + delay_tms = tms; +} diff --git a/contrib/firmware/angie/c/src/main.c b/contrib/firmware/angie/c/src/main.c new file mode 100644 index 0000000000..9290af2ab5 --- /dev/null +++ b/contrib/firmware/angie/c/src/main.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/**************************************************************************** + File : main.c * + Contents : main code for NanoXplore USB-JTAG ANGIE adapter * + hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "usb.h" +#include "delay.h" +#include "protocol.h" +#include "reg_ezusb.h" +#include +#include + +extern void sudav_isr(void)__interrupt SUDAV_ISR; +extern void sof_isr(void)__interrupt; +extern void sutok_isr(void)__interrupt; +extern void suspend_isr(void)__interrupt; +extern void usbreset_isr(void)__interrupt; +extern void highspeed_isr(void)__interrupt; +extern void ep0ack_isr(void)__interrupt; +extern void stub_isr(void)__interrupt; +extern void ep0in_isr(void)__interrupt; +extern void ep0out_isr(void)__interrupt; +extern void ep1in_isr(void)__interrupt; +extern void ep1out_isr(void)__interrupt; +extern void ep2_isr(void)__interrupt; +extern void ep4_isr(void)__interrupt; +extern void ep6_isr(void)__interrupt; +extern void ep8_isr(void)__interrupt; +extern void ibn_isr(void)__interrupt; +extern void ep0pingnak_isr(void)__interrupt; +extern void ep1pingnak_isr(void)__interrupt; +extern void ep2pingnak_isr(void)__interrupt; +extern void ep4pingnak_isr(void)__interrupt; +extern void ep6pingnak_isr(void)__interrupt; +extern void ep8pingnak_isr(void)__interrupt; +extern void errorlimit_isr(void)__interrupt; +extern void ep2piderror_isr(void)__interrupt; +extern void ep4piderror_isr(void)__interrupt; +extern void ep6piderror_isr(void)__interrupt; +extern void ep8piderror_isr(void)__interrupt; +extern void ep2pflag_isr(void)__interrupt; +extern void ep4pflag_isr(void)__interrupt; +extern void ep6pflag_isr(void)__interrupt; +extern void ep8pflag_isr(void)__interrupt; +extern void ep2eflag_isr(void)__interrupt; +extern void ep4eflag_isr(void)__interrupt; +extern void ep6eflag_isr(void)__interrupt; +extern void ep8eflag_isr(void)__interrupt; +extern void ep2fflag_isr(void)__interrupt; +extern void ep4fflag_isr(void)__interrupt; +extern void ep6fflag_isr(void)__interrupt; +extern void ep8fflag_isr(void)__interrupt; +extern void gpifcomplete_isr(void)__interrupt; +extern void gpifwaveform_isr(void)__interrupt; + +void gpif_init(void); + +int main(void) +{ + CPUCS = ((CPUCS & ~bmclkspd) | (CLK_48M << 3) | CLKOE); /* required for sio0_init */ + sio0_init(57600); /* needed for printf */ + + ep_init(); + gpif_init(); + interrupt_init(); + io_init(); + + /* Perform ReNumeration */ + USBCS |= (DISCON | RENUM); + delay_ms(250); + USBCS &= ~DISCON; + + /* Begin executing command(s). This function never returns. */ + command_loop(); + + /* Never reached, but SDCC complains about missing return statement */ + return 0; +} diff --git a/contrib/firmware/angie/c/src/protocol.c b/contrib/firmware/angie/c/src/protocol.c new file mode 100644 index 0000000000..e32808db8f --- /dev/null +++ b/contrib/firmware/angie/c/src/protocol.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/**************************************************************************** + File : protocol.c * + Contents : Jtag commands handling protocol code for NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "usb.h" +#include "protocol.h" +#include "jtag.h" +#include "delay.h" +#include "io.h" +#include "msgtypes.h" +#include "reg_ezusb.h" +#include +#include + +/** Index in EP1 Bulk-OUT data buffer that contains the current command ID */ +volatile uint8_t cmd_id_index; + +/** Number of data bytes already in EP1 Bulk-IN buffer */ +volatile uint8_t payload_index_in; + +/** + * Executes one command and updates global command indexes. + * + * @return true if this command was the last command. + * @return false if there are more commands within the current contents of the + * Bulk EP1-OUT data buffer. + */ +bool execute_command(void) +{ + uint8_t usb_out_bytecount, usb_in_bytecount; + uint16_t signal_state = 0; + uint16_t count; + + /* Most commands do not transfer IN data. To save code space, we write 0 to + * usb_in_bytecount here, then modify it in the switch statement below where + * necessary */ + usb_in_bytecount = 0; + + switch (EP1OUTBUF[cmd_id_index] /* Command ID */) { + case CMD_SCAN_IN: + usb_out_bytecount = 5; + usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1]; + jtag_scan_in((cmd_id_index + 1), payload_index_in); + break; + case CMD_SCAN_OUT: + usb_out_bytecount = EP1OUTBUF[cmd_id_index + 1] + 5; + jtag_scan_out(cmd_id_index + 1); + break; + case CMD_SCAN_IO: + usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1]; + usb_out_bytecount = usb_in_bytecount + 5; + jtag_scan_io((cmd_id_index + 1), payload_index_in); + break; + case CMD_CLOCK_TMS: + usb_out_bytecount = 2; + jtag_clock_tms(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]); + break; + case CMD_CLOCK_TCK: + usb_out_bytecount = 2; + count = (uint16_t)EP1OUTBUF[cmd_id_index + 1]; + count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8; + jtag_clock_tck(count); + break; + case CMD_SLOW_SCAN_IN: + usb_out_bytecount = 5; + usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1]; + jtag_slow_scan_in(cmd_id_index + 1, payload_index_in); + break; + case CMD_SLOW_SCAN_OUT: + usb_out_bytecount = EP1OUTBUF[cmd_id_index + 1] + 5; + jtag_slow_scan_out(cmd_id_index + 1); + break; + case CMD_SLOW_SCAN_IO: + usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1]; + usb_out_bytecount = usb_in_bytecount + 5; + jtag_slow_scan_io(cmd_id_index + 1, payload_index_in); + break; + case CMD_SLOW_CLOCK_TMS: + usb_out_bytecount = 2; + jtag_slow_clock_tms(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]); + break; + case CMD_SLOW_CLOCK_TCK: + usb_out_bytecount = 2; + count = (uint16_t)EP1OUTBUF[cmd_id_index + 1]; + count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8; + jtag_slow_clock_tck(count); + break; + case CMD_SLEEP_US: + usb_out_bytecount = 2; + count = (uint16_t)EP1OUTBUF[cmd_id_index + 1]; + count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8; + delay_us(count); + break; + case CMD_SLEEP_MS: + usb_out_bytecount = 2; + count = (uint16_t)EP1OUTBUF[cmd_id_index + 1]; + count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8; + delay_ms(count); + break; + case CMD_GET_SIGNALS: + usb_out_bytecount = 0; + usb_in_bytecount = 2; + signal_state = jtag_get_signals(); + EP1INBUF[payload_index_in] = (signal_state >> 8); + EP1INBUF[payload_index_in + 1] = (signal_state & 0xFF); + break; + case CMD_SET_SIGNALS: + usb_out_bytecount = 2; + jtag_set_signals(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]); + break; + case CMD_CONFIGURE_TCK_FREQ: + usb_out_bytecount = 5; + jtag_configure_tck_delay(EP1OUTBUF[cmd_id_index + 1], /* scan_in */ + EP1OUTBUF[cmd_id_index + 2], /* scan_out */ + EP1OUTBUF[cmd_id_index + 3], /* scan_io */ + EP1OUTBUF[cmd_id_index + 4], /* clock_tck */ + EP1OUTBUF[cmd_id_index + 5]); /* clock_tms */ + break; + case CMD_TEST: + usb_out_bytecount = 1; + /* Do nothing... This command is only used to test if the device is ready + * to accept new commands */ + break; + default: + /* Should never be reached */ + usb_out_bytecount = 0; + break; + } + + /* Update EP1 Bulk-IN data byte count */ + payload_index_in += usb_in_bytecount; + + /* Determine if this was the last command */ + if ((cmd_id_index + usb_out_bytecount + 1) >= EP1OUTBC) + return true; + + /* Not the last command, update cmd_id_index */ + cmd_id_index += (usb_out_bytecount + 1); + return false; +} + +/** + * Forever wait for commands and execute them as they arrive. + */ +void command_loop(void) +{ + bool last_command; + while (1) { + cmd_id_index = 0; + payload_index_in = 0; + + /* Wait until host sends Bulk-OUT packet */ + while ((!ep1_out) && (!ep6_out)) + ; + if (ep6_out) { + /* Execute I2C command */ + i2c_recieve(); + ep6_out = false; + } + if (ep1_out) { + ep1_out = false; + /* Execute the commands */ + last_command = false; + while (!last_command) + last_command = execute_command(); + + /* Send back EP1 Bulk-IN packet if required */ + if (payload_index_in > 0) { + EP1INBC = payload_index_in; + syncdelay(3); + + while (!ep1_in) + ; + ep1_in = false; + } + + /* Re-arm EP1-OUT after command execution */ + EP1OUTBC = 0; + syncdelay(3); + EP1OUTBC = 0; + syncdelay(3); + } + } +} diff --git a/contrib/firmware/angie/c/src/serial.c b/contrib/firmware/angie/c/src/serial.c new file mode 100644 index 0000000000..0398cb23cf --- /dev/null +++ b/contrib/firmware/angie/c/src/serial.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: LGPL-2.1-or-later + +/* + * This code was taken from the fx2lib project from this link: + * https://github.com/djmuhlestein/fx2lib + * + * Copyright (C) 2009 Ubixum, Inc. +*/ + +#include +#include +#include +#include +/** + * using the comp port implies that timer 2 will be used as + * a baud rate generator. (Don't use timer 2) + **/ +void sio0_init(uint32_t baud_rate) __critical +{ + uint16_t hl; /* hl value for reload */ + uint8_t mult; /* multiplier for clock speed */ + uint32_t tmp; /* scratch for mult/divide */ + + mult = (CPUFREQ == CLK_12M) ? 1 : ((CPUFREQ == CLK_24M) ? 2 : 4); + + /* set the clock rate */ + /* use clock 2 */ + RCLK = 1; TCLK = 1; + tmp = mult * 375000L * 2; + tmp /= baud_rate; + tmp += 1; + tmp /= 2; + hl = 0xFFFF - (uint16_t)tmp; + RCAP2H = (uint8_t)(((uint16_t)(hl) >> 8) & 0xff); + + /* seems that the 24/48mhz calculations are always one less than suggested values */ + /* trm table 14-16 */ + RCAP2L = ((uint8_t)((uint16_t)(hl) & 0xff)) + (mult > 0 ? 1 : 0); + + /* start the timer */ + TR2 = 1; + + /* set up the serial port */ + SM0 = 0; SM1 = 1; /* serial mode 1 (asyncronous) */ + SM2 = 0 ; /* has to do with receiving */ + REN = 1 ; /* to enable receiving */ + PCON |= 0x80; /* SET SMOD0, baud rate doubler */ + TI = 1; /* we send initial byte */ +} + +int getchar(void) +{ + char c; + while (!RI) + ; + c = SBUF0; + RI = 0; + return c; +} + +void _transchar(char c) +{ + while (!TI) + ; /* wait for TI=1 */ + TI = 0; + SBUF0 = c; +} + +int putchar (char c) +{ + if (c == '\n') + _transchar('\r'); /* transmit \r\n */ + _transchar(c); + if (c == '\r') + _transchar('\n'); /* transmit \r\n */ + return c; +} diff --git a/contrib/firmware/angie/c/src/usb.c b/contrib/firmware/angie/c/src/usb.c new file mode 100644 index 0000000000..ed23dcfa5a --- /dev/null +++ b/contrib/firmware/angie/c/src/usb.c @@ -0,0 +1,894 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/**************************************************************************** + File : usb.c * + Contents : usb communication handling code for NanoXplore USB-JTAG * + ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + * + * +*****************************************************************************/ + +#include "usb.h" +#include "stdint.h" +#include "delay.h" +#include "io.h" +#include "reg_ezusb.h" +#include +#include +#include +#include "i2c.h" + +/* Also update external declarations in "include/usb.h" if making changes to + * these variables! + */ +volatile bool ep1_out; +volatile bool ep1_in; +volatile bool ep6_out; + +volatile __xdata __at 0xE6B8 struct setup_data setup_data; + +/* Define number of endpoints (except Control Endpoint 0) in a central place. + * Be sure to include the necessary endpoint descriptors! + */ +#define NUM_ENDPOINTS 3 + +__code struct usb_device_descriptor device_descriptor = { + .blength = sizeof(struct usb_device_descriptor), + .bdescriptortype = DESCRIPTOR_TYPE_DEVICE, + .bcdusb = 0x0200, /* BCD: 02.00 (Version 2.0 USB spec) */ + .bdeviceclass = 0xEF, + .bdevicesubclass = 0x02, + .bdeviceprotocol = 0x01, + .bmaxpacketsize0 = 64, + .idvendor = 0x584e, + .idproduct = 0x414f, + .bcddevice = 0x0000, + .imanufacturer = 1, + .iproduct = 2, + .iserialnumber = 3, + .bnumconfigurations = 1 +}; + +/* WARNING: ALL config, interface and endpoint descriptors MUST be adjacent! */ + +__code struct usb_config_descriptor config_descriptor = { + .blength = sizeof(struct usb_config_descriptor), + .bdescriptortype = DESCRIPTOR_TYPE_CONFIGURATION, + .wtotallength = sizeof(struct usb_config_descriptor) + + 3 * sizeof(struct usb_interface_descriptor) + + ((NUM_ENDPOINTS + 2) * sizeof(struct usb_endpoint_descriptor)), + .bnuminterfaces = 2, + .bconfigurationvalue = 1, + .iconfiguration = 1, /* String describing this configuration */ + .bmattributes = 0x80, /* Only MSB set according to USB spec */ + .maxpower = 50 /* 100 mA */ +}; + +__code struct usb_interface_descriptor interface_descriptor00 = { + .blength = sizeof(struct usb_interface_descriptor), + .bdescriptortype = DESCRIPTOR_TYPE_INTERFACE, + .binterfacenumber = 0, + .balternatesetting = 0, + .bnumendpoints = NUM_ENDPOINTS, + .binterfaceclass = 0XFF, + .binterfacesubclass = 0x00, + .binterfaceprotocol = 0x00, + .iinterface = 4 +}; + +__code struct usb_endpoint_descriptor bulk_ep1_out_endpoint_descriptor = { + .blength = sizeof(struct usb_endpoint_descriptor), + .bdescriptortype = 0x05, + .bendpointaddress = (1 | USB_DIR_OUT), + .bmattributes = 0x02, + .wmaxpacketsize = 64, + .binterval = 0 +}; + +__code struct usb_endpoint_descriptor bulk_ep1_in_endpoint_descriptor = { + .blength = sizeof(struct usb_endpoint_descriptor), + .bdescriptortype = 0x05, + .bendpointaddress = (1 | USB_DIR_IN), + .bmattributes = 0x02, + .wmaxpacketsize = 64, + .binterval = 0 +}; + +__code struct usb_endpoint_descriptor bulk_ep2_endpoint_descriptor = { + .blength = sizeof(struct usb_endpoint_descriptor), + .bdescriptortype = 0x05, + .bendpointaddress = (2 | USB_DIR_OUT), + .bmattributes = 0x02, + .wmaxpacketsize = 512, + .binterval = 0 +}; + +__code struct usb_interface_descriptor interface_descriptor01 = { + .blength = sizeof(struct usb_interface_descriptor), + .bdescriptortype = DESCRIPTOR_TYPE_INTERFACE, + .binterfacenumber = 1, + .balternatesetting = 0, + .bnumendpoints = 2, + .binterfaceclass = 0x0A, + .binterfacesubclass = 0x00, + .binterfaceprotocol = 0x00, + .iinterface = 0x00 +}; + +__code struct usb_endpoint_descriptor bulk_ep6_out_endpoint_descriptor = { + .blength = sizeof(struct usb_endpoint_descriptor), + .bdescriptortype = 0x05, + .bendpointaddress = (6 | USB_DIR_OUT), + .bmattributes = 0x02, + .wmaxpacketsize = 512, + .binterval = 0 +}; + +__code struct usb_endpoint_descriptor bulk_ep8_in_endpoint_descriptor = { + .blength = sizeof(struct usb_endpoint_descriptor), + .bdescriptortype = 0x05, + .bendpointaddress = (8 | USB_DIR_IN), + .bmattributes = 0x02, + .wmaxpacketsize = 512, + .binterval = 0 +}; +__code struct usb_language_descriptor language_descriptor = { + .blength = 4, + .bdescriptortype = DESCRIPTOR_TYPE_STRING, + .wlangid = {0x0409} /* US English */ +}; + +__code struct usb_string_descriptor strmanufacturer = + STR_DESCR(16, 'N', 'a', 'n', 'o', 'X', 'p', 'l', 'o', 'r', 'e', ',', ' ', 'S', 'A', 'S', '.'); + +__code struct usb_string_descriptor strproduct = + STR_DESCR(13, 'A', 'N', 'G', 'I', 'E', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r'); + +__code struct usb_string_descriptor strserialnumber = + STR_DESCR(6, '0', '0', '0', '0', '0', '1'); + +__code struct usb_string_descriptor strconfigdescr = + STR_DESCR(12, 'J', 'T', 'A', 'G', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r'); + +/* Table containing pointers to string descriptors */ +__code struct usb_string_descriptor *__code en_string_descriptors[4] = { + &strmanufacturer, + &strproduct, + &strserialnumber, + &strconfigdescr +}; +void sudav_isr(void)__interrupt SUDAV_ISR +{ + EXIF &= ~0x10; /* Clear USBINT: Main global interrupt */ + USBIRQ = SUDAVI; + EP0CS |= HSNAK; + usb_handle_setup_data(); +} +void sof_isr(void)__interrupt SOF_ISR +{ +} +void sutok_isr(void)__interrupt SUTOK_ISR +{ +} +void suspend_isr(void)__interrupt SUSPEND_ISR +{ +} +void usbreset_isr(void)__interrupt USBRESET_ISR +{ +} +void highspeed_isr(void)__interrupt HIGHSPEED_ISR +{ +} +void ep0ack_isr(void)__interrupt EP0ACK_ISR +{ +} +void stub_isr(void)__interrupt STUB_ISR +{ +} +void ep0in_isr(void)__interrupt EP0IN_ISR +{ +} +void ep0out_isr(void)__interrupt EP0OUT_ISR +{ +} +void ep1in_isr(void)__interrupt EP1IN_ISR +{ + ep1_in = true; + EXIF &= ~0x10; /* Clear USBINT: Main global interrupt */ + EPIRQ = 0x04; /* Clear individual EP1IN IRQ */ +} +void ep1out_isr(void)__interrupt EP1OUT_ISR +{ + ep1_out = true; + EXIF &= ~0x10; /* Clear USBINT: Main global interrupt */ + EPIRQ = 0x08; /* Clear individual EP1OUT IRQ */ +} +void ep2_isr(void)__interrupt EP2_ISR +{ +} +void ep4_isr(void)__interrupt EP4_ISR +{ +} +void ep6_isr(void)__interrupt EP6_ISR +{ + ep6_out = true; + EXIF &= ~0x10; /* Clear USBINT: Main global interrupt */ + EPIRQ = 0x40; /* Clear individual EP6OUT IRQ */ + +} +void ep8_isr(void)__interrupt EP8_ISR +{ + EXIF &= ~0x10; /* Clear USBINT: Main global interrupt */ + EPIRQ = 0x80; /* Clear individual EP8IN IRQ */ +} +void ibn_isr(void)__interrupt IBN_ISR +{ +} +void ep0pingnak_isr(void)__interrupt EP0PINGNAK_ISR +{ +} +void ep1pingnak_isr(void)__interrupt EP1PINGNAK_ISR +{ +} +void ep2pingnak_isr(void)__interrupt EP2PINGNAK_ISR +{ +} +void ep4pingnak_isr(void)__interrupt EP4PINGNAK_ISR +{ +} +void ep6pingnak_isr(void)__interrupt EP6PINGNAK_ISR +{ +} +void ep8pingnak_isr(void)__interrupt EP8PINGNAK_ISR +{ +} +void errorlimit_isr(void)__interrupt ERRORLIMIT_ISR +{ +} +void ep2piderror_isr(void)__interrupt EP2PIDERROR_ISR +{ +} +void ep4piderror_isr(void)__interrupt EP4PIDERROR_ISR +{ +} +void ep6piderror_isr(void)__interrupt EP6PIDERROR_ISR +{ +} +void ep8piderror_isr(void)__interrupt EP8PIDERROR_ISR +{ +} +void ep2pflag_isr(void)__interrupt EP2PFLAG_ISR +{ +} +void ep4pflag_isr(void)__interrupt EP4PFLAG_ISR +{ +} +void ep6pflag_isr(void)__interrupt EP6PFLAG_ISR +{ +} +void ep8pflag_isr(void)__interrupt EP8PFLAG_ISR +{ +} +void ep2eflag_isr(void)__interrupt EP2EFLAG_ISR +{ +} +void ep4eflag_isr(void)__interrupt EP4EFLAG_ISR +{ +} +void ep6eflag_isr(void)__interrupt EP6EFLAG_ISR +{ +} +void ep8eflag_isr(void)__interrupt EP8EFLAG_ISR +{ +} +void ep2fflag_isr(void)__interrupt EP2FFLAG_ISR +{ +} +void ep4fflag_isr(void)__interrupt EP4FFLAG_ISR +{ +} +void ep6fflag_isr(void)__interrupt EP6FFLAG_ISR +{ +} +void ep8fflag_isr(void)__interrupt EP8FFLAG_ISR +{ +} +void gpifcomplete_isr(void)__interrupt GPIFCOMPLETE_ISR +{ +} +void gpifwaveform_isr(void)__interrupt GPIFWAVEFORM_ISR +{ +} + +/** + * Return the control/status register for an endpoint + * + * @param ep endpoint address + * @return on success: pointer to Control & Status register for endpoint + * specified in \a ep + * @return on failure: NULL + */ +__xdata uint8_t *usb_get_endpoint_cs_reg(uint8_t ep) +{ + /* Mask direction bit */ + uint8_t ep_num = ep & ~0x80; + + switch (ep_num) { + case 0: + return &EP0CS; + case 1: + return ep & 0x80 ? &EP1INCS : &EP1OUTCS; + case 2: + return &EP2CS; + case 4: + return &EP4CS; + case 6: + return &EP6CS; + case 8: + return &EP8CS; + default: + return NULL; + } +} + +void usb_reset_data_toggle(uint8_t ep) +{ + /* TOGCTL register: + +----+-----+-----+------+-----+-------+-------+-------+ + | Q | S | R | IO | EP3 | EP2 | EP1 | EP0 | + +----+-----+-----+------+-----+-------+-------+-------+ + + To reset data toggle bits, we have to write the endpoint direction (IN/OUT) + to the IO bit and the endpoint number to the EP2..EP0 bits. Then, in a + separate write cycle, the R bit needs to be set. + */ + TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x0F)); + TOGCTL |= BMRESETTOGGLE; +} + +/** + * Handle GET_STATUS request. + * + * @return on success: true + * @return on failure: false + */ +bool usb_handle_get_status(void) +{ + uint8_t *ep_cs; + switch (setup_data.bmrequesttype) { + case GS_DEVICE: + /* Two byte response: Byte 0, Bit 0 = self-powered, Bit 1 = remote wakeup. + * Byte 1: reserved, reset to zero */ + EP0BUF[0] = 0; + EP0BUF[1] = 0; + + /* Send response */ + EP0BCH = 0; + syncdelay(3); + EP0BCL = 2; + syncdelay(3); + break; + case GS_INTERFACE: + /* Always return two zero bytes according to USB 1.1 spec, p. 191 */ + EP0BUF[0] = 0; + EP0BUF[1] = 0; + + /* Send response */ + EP0BCH = 0; + syncdelay(3); + EP0BCL = 2; + syncdelay(3); + break; + case GS_ENDPOINT: + /* Get stall bit for endpoint specified in low byte of wIndex */ + ep_cs = usb_get_endpoint_cs_reg(setup_data.windex & 0xff); + + if (*ep_cs & EPSTALL) + EP0BUF[0] = 0x01; + else + EP0BUF[0] = 0x00; + + /* Second byte sent has to be always zero */ + EP0BUF[1] = 0; + + /* Send response */ + EP0BCH = 0; + syncdelay(3); + EP0BCL = 2; + syncdelay(3); + break; + default: + return false; + } + return true; +} + +/** + * Handle CLEAR_FEATURE request. + * + * @return on success: true + * @return on failure: false + */ +bool usb_handle_clear_feature(void) +{ + __xdata uint8_t *ep_cs; + + switch (setup_data.bmrequesttype) { + case CF_DEVICE: + /* Clear remote wakeup not supported: stall EP0 */ + STALL_EP0(); + break; + case CF_ENDPOINT: + if (setup_data.wvalue == 0) { + /* Unstall the endpoint specified in wIndex */ + ep_cs = usb_get_endpoint_cs_reg(setup_data.windex); + if (!ep_cs) + return false; + *ep_cs &= ~EPSTALL; + } else { + /* Unsupported feature, stall EP0 */ + STALL_EP0(); + } + break; + default: + /* Vendor commands... */ + break; + } + return true; +} + +/** + * Handle SET_FEATURE request. + * + * @return on success: true + * @return on failure: false + */ +bool usb_handle_set_feature(void) +{ + __xdata uint8_t *ep_cs; + + switch (setup_data.bmrequesttype) { + case SF_DEVICE: + if (setup_data.wvalue == 2) + return true; + break; + case SF_ENDPOINT: + if (setup_data.wvalue == 0) { + /* Stall the endpoint specified in wIndex */ + ep_cs = usb_get_endpoint_cs_reg(setup_data.windex); + if (!ep_cs) + return false; + *ep_cs |= EPSTALL; + } else { + /* Unsupported endpoint feature */ + return false; + } + break; + default: + /* Vendor commands... */ + break; + } + + return true; +} + +/** + * Handle GET_DESCRIPTOR request. + * + * @return on success: true + * @return on failure: false + */ +bool usb_handle_get_descriptor(void) +{ + __xdata uint8_t descriptor_type; + __xdata uint8_t descriptor_index; + + descriptor_type = (setup_data.wvalue & 0xff00) >> 8; + descriptor_index = setup_data.wvalue & 0x00ff; + + switch (descriptor_type) { + case DESCRIPTOR_TYPE_DEVICE: + SUDPTRH = HI8(&device_descriptor); + SUDPTRL = LO8(&device_descriptor); + break; + case DESCRIPTOR_TYPE_CONFIGURATION: + SUDPTRH = HI8(&config_descriptor); + SUDPTRL = LO8(&config_descriptor); + break; + case DESCRIPTOR_TYPE_STRING: + if (setup_data.windex == 0) { + /* Supply language descriptor */ + SUDPTRH = HI8(&language_descriptor); + SUDPTRL = LO8(&language_descriptor); + } else if (setup_data.windex == 0x0409 /* US English */) { + /* Supply string descriptor */ + SUDPTRH = HI8(en_string_descriptors[descriptor_index - 1]); + SUDPTRL = LO8(en_string_descriptors[descriptor_index - 1]); + } else { + return false; + } + break; + default: + /* Unsupported descriptor type */ + return false; + } + return true; +} + +/** + * Handle SET_INTERFACE request. + */ +void usb_handle_set_interface(void) +{ + /* Reset Data Toggle */ + usb_reset_data_toggle(USB_DIR_IN | 4); + usb_reset_data_toggle(USB_DIR_OUT | 2); + + /* Unstall & clear busy flag of all valid IN endpoints */ + EP1INCS = 0 | EPBSY; + + /* Unstall all valid OUT endpoints, reset bytecounts */ + EP1OUTCS = 0; + EP1OUTBC = 0; + syncdelay(3); +} + +/* Initialize GPIF interface transfer count */ +void set_gpif_cnt(uint32_t count) +{ + GPIFTCB3 = (uint8_t)(((uint32_t)(count) >> 24) & 0x000000ff); + syncdelay(3); + GPIFTCB2 = (uint8_t)(((uint32_t)(count) >> 16) & 0x000000ff); + syncdelay(3); + GPIFTCB1 = (uint8_t)(((uint32_t)(count) >> 8) & 0x000000ff); + syncdelay(3); + GPIFTCB0 = (uint8_t)((uint32_t)(count) & 0x000000ff); +} + +/* + * Vendor commands handling: +*/ +#define VR_CFGOPEN 0xB0 +#define VR_CFGCLOSE 0xB1 + +uint8_t ix; +uint8_t bcnt; +uint8_t __xdata *eptr; +uint16_t wcnt; +uint32_t __xdata gcnt; +bool usb_handle_send_bitstream(void) +{ + eptr = EP0BUF; /* points to EP0BUF 64-byte register */ + wcnt = setup_data.wlength; /* total transfer count */ + + /* Clear EP0BUF for OUT requests */ + if (setup_data.bmrequesttype & 0x80) { + bcnt = ((wcnt > 64) ? 64 : wcnt); + for (ix = 0; ix < bcnt; ix++) + eptr[ix] = 0; + } + + switch (setup_data.brequest) { + case VR_CFGOPEN: + /* Clear bytecount / to allow new data in / to stops NAKing */ + EP0BCH = 0; + EP0BCL = 0; + while (EP0CS & EPBSY) + ; /* wait to finish transferring in EP0BUF, until not busy */ + gcnt = ((uint32_t)(eptr[0]) << 24) | ((uint32_t)(eptr[1]) << 16) + | ((uint32_t)(eptr[2]) << 8) | (uint32_t)(eptr[3]); + /* Angie board FPGA bitstream download */ + switch ((setup_data.wvalue) & 0x00C0) { + case 0x00: + PIN_PROGRAM_B = 0; /* Apply RPGM- pulse */ + GPIFWFSELECT = 0xF2; /* Restore Config mode waveforms select */ + syncdelay(3); + EP2FIFOCFG = BMAUTOOUT; /* and Automatic 8-bit GPIF OUT mode */ + syncdelay(3); + PIN_PROGRAM_B = 1; /* Negate RPGM- pulse */ + delay_ms(10); /* FPGA init time < 10mS */ + set_gpif_cnt(gcnt); /* Initialize GPIF interface transfer count */ + PIN_RDWR_B = 0; + PIN_CSI_B = 0; + GPIFTRIG = GPIF_EP2; /* Trigger GPIF OUT transfer on EP2 */ + syncdelay(3); + break; + default: + break; + } + break; + case VR_CFGCLOSE: + ix = 10; + /* wait until GPIF transaction has been completed */ + while ((GPIFTRIG & BMGPIFDONE) == 0) { + if (ix-- == 0) { + break; + } + delay_ms(1); + } + switch ((setup_data.wvalue) & 0x00C0) { + case 0x00: + PIN_CSI_B = 1; + PIN_RDWR_B = 1; + IFCONFIG &= 0xFC; /* Exit gpif mode */ + break; + default: + break; + } + EP0BCH = 0; + EP0BCL = (uint8_t)(setup_data.wlength); /* Signal buffer is filled */ + break; + default: + return true; /* Error: unknown VR command */ + } + return false; /* no error; command handled OK */ +} + +/** + * Handle the arrival of a USB Control Setup Packet. + */ +void usb_handle_setup_data(void) +{ + switch (setup_data.brequest) { + case GET_STATUS: + if (!usb_handle_get_status()) + STALL_EP0(); + break; + case CLEAR_FEATURE: + if (!usb_handle_clear_feature()) + STALL_EP0(); + break; + case 2: case 4: + /* Reserved values */ + STALL_EP0(); + break; + case SET_FEATURE: + if (!usb_handle_set_feature()) + STALL_EP0(); + break; + case SET_ADDRESS: + /* Handled by USB core */ + break; + case SET_DESCRIPTOR: + /* Set Descriptor not supported. */ + STALL_EP0(); + break; + case GET_DESCRIPTOR: + if (!usb_handle_get_descriptor()) + STALL_EP0(); + break; + case GET_CONFIGURATION: + /* ANGIE has only one configuration, return its index */ + EP0BUF[0] = config_descriptor.bconfigurationvalue; + EP0BCH = 0; + EP0BCL = 1; + syncdelay(3); + break; + case SET_CONFIGURATION: + /* ANGIE has only one configuration -> nothing to do */ + break; + case GET_INTERFACE: + /* ANGIE only has one interface, return its number */ + EP0BUF[0] = interface_descriptor00.binterfacenumber; + EP0BCH = 0; + EP0BCL = 1; + syncdelay(3); + break; + case SET_INTERFACE: + usb_handle_set_interface(); + break; + case SYNCH_FRAME: + /* Isochronous endpoints not used -> nothing to do */ + break; + default: + /* if not Vendor command, Stall EndPoint 0 */ + if (usb_handle_send_bitstream()) + STALL_EP0(); + break; + } +} + +/** + * Handle the initialization of endpoints. + */ +void ep_init(void) +{ + EP1INCFG = 0xA0; + syncdelay(3); + EP1OUTCFG = 0xA0; + syncdelay(3); + EP2CFG = 0xA0; + syncdelay(3); + EP4CFG = 0x00; + syncdelay(3); + EP6CFG = 0xA2; + syncdelay(3); + EP8CFG = 0xE2; + syncdelay(3); + + /* arm EP1-OUT */ + EP1OUTBC = 0; + syncdelay(3); + EP1OUTBC = 0; + syncdelay(3); + + /* arm EP1-IN */ + EP1INBC = 0; + syncdelay(3); + EP1INBC = 0; + syncdelay(3); + + /* arm EP6-OUT */ + EP6BCL = 0x80; + syncdelay(3); + EP6BCL = 0x80; + syncdelay(3); + + /* Standard procedure to reset FIFOs */ + FIFORESET = BMNAKALL; /* NAK all transfers during the reset */ + syncdelay(3); + FIFORESET = 0x02; /* reset EP2 FIFO */ + syncdelay(3); + FIFORESET = 0x00; /* deactivate the NAK all */ + syncdelay(3); + EP2FIFOCFG = 0x00; + syncdelay(3); + EP2FIFOCFG = BMAUTOOUT; /* Automatic 8-bit GPIF OUT mode */ + syncdelay(3); +} + +void i2c_recieve(void) +{ + PIN_SDA_DIR = 0; + if (EP6FIFOBUF[0] == 1) { + uint8_t rdwr = EP6FIFOBUF[0]; //read + uint8_t data_count = EP6FIFOBUF[1]; //data sent count + uint8_t count = EP6FIFOBUF[2]; //requested data count + uint8_t adr = EP6FIFOBUF[3]; //address + uint8_t address = get_address(adr, rdwr); //address byte (read command) + uint8_t address_2 = get_address(adr, 0); //address byte 2 (write command) + + printf("%d\n", address - 1); + + /* start: */ + start_cd(); + /* address: */ + send_byte(address_2); //write + /* ack: */ + uint8_t ack = get_ack(); + + /* send data */ + if (data_count) { //if there is a byte reg + for (uint8_t i = 0; i < data_count; i++) { + send_byte(EP6FIFOBUF[i + 4]); + /* ack(): */ + ack = get_ack(); + } + } + + /* repeated start: */ + repeated_start(); + /* address: */ + send_byte(address); + /* get ack: */ + ack = get_ack(); + + /* receive data */ + for (uint8_t i = 0; i < count - 1; i++) { + EP8FIFOBUF[i] = receive_byte(); + + /* send ack: */ + send_ack(); + } + + EP8FIFOBUF[count - 1] = receive_byte(); + + /* send Nack: */ + send_nack(); + + /* stop */ + stop_cd(); + + EP8BCH = 0; //EP8 + syncdelay(3); + EP8BCL = count; //EP8 + + EP6BCL = 0x80; //EP6 + syncdelay(3); + EP6BCL = 0x80; //EP6 + } else { + uint8_t rdwr = EP6FIFOBUF[0]; //write + uint8_t count = EP6FIFOBUF[1]; //data count + uint8_t adr = EP6FIFOBUF[2]; //address + uint8_t address = get_address(adr, rdwr); //address byte (read command) + uint8_t ack_cnt = 0; + +/* start(): */ + start_cd(); +/* address: */ + send_byte(address); //write +/* ack(): */ + if (!get_ack()) + ack_cnt++; +/* send data */ + for (uint8_t i = 0; i < count; i++) { + send_byte(EP6FIFOBUF[i + 3]); + + /* get ack: */ + if (!get_ack()) + ack_cnt++; + } + +/* stop */ + stop_cd(); + + EP8FIFOBUF[0] = ack_cnt; + + EP8BCH = 0; //EP8 + syncdelay(3); + EP8BCL = 1; //EP8 + + EP6BCL = 0x80; //EP6 + syncdelay(3); + EP6BCL = 0x80; //EP6 + } +} + +/** + * Interrupt initialization. Configures USB interrupts. + **/ +void interrupt_init(void) +{ + /* Enable Interrupts */ + EA = 1; + + /* Enable USB interrupt (EIE register) */ + EUSB = 1; + EICON |= 0x20; + + /* Enable INT 2 & 4 Autovectoring */ + INTSETUP |= (AV2EN | AV4EN); + + /* Enable individual EP1OUT&IN & EP6&8 interrupts */ + EPIE |= 0xCC; + + /* Clear individual USB interrupt IRQ */ + EPIRQ = 0xCC; + + /* Enable SUDAV interrupt */ + USBIEN |= SUDAVI; + + /* Clear SUDAV interrupt */ + USBIRQ = SUDAVI; +} + +/** + * Handle the initialization of io ports. + */ +void io_init(void) +{ + /* PORT A */ + PORTACFG = 0x01; /* 0: normal ou 1: alternate function (each bit) */ + OEA = 0xEF; /* all OUT exept INIT_B IN */ + IOA = 0xFF; + + /* PORT B */ + OEB = 0xEF; /* all OUT exept TDO */ + IOB = 0xFF; + PIN_TRST = 1; + PIN_TMS = 0; + PIN_TCK = 0; + PIN_TDI = 0; + PIN_SRST = 1; + + /* PORT C */ + PORTCCFG = 0x00; /* 0: normal ou 1: alternate function (each bit) */ + OEC = 0xFF; + IOC = 0xFF; + + /* PORT D */ + OED = 0xFF; + IOD = 0xFF; +} diff --git a/contrib/firmware/angie/hdl/Makefile b/contrib/firmware/angie/hdl/Makefile new file mode 100644 index 0000000000..b28b650892 --- /dev/null +++ b/contrib/firmware/angie/hdl/Makefile @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2023 by NanoXplore, France - all rights reserved + +# Needed by timing test +export PROJECT := angie_bitstream +TARGET_PART := xc6slx9-2tqg144 +export TOPLEVEL := S609 + +# Detects the ROOT dir from the .git marker +sp := +sp += +_walk = $(if $1,$(wildcard /$(subst $(sp),/,$1)/$2) $(call _walk,$(wordlist 2,$(words $1),x $1),$2)) +_find = $(firstword $(call _walk,$(strip $(subst /, ,$1)),$2)) +_ROOT := $(patsubst %/.git,%,$(call _find,$(CURDIR),.git)) + +SHELL := /bin/bash +TOP_DIR := $(realpath $(_ROOT)) +HDL_DIR := $(CURDIR) +SRC_DIR := $(HDL_DIR)/src +TOOLS_DIR := $(TOP_DIR)/tools/build +COMMON_DIR := $(TOP_DIR)/common/hdl +COMMON_HDL_DIR := $(COMMON_DIR)/src +COMMON_LIBS := $(COMMON_DIR)/libs +HDL_BUILD_DIR := $(HDL_DIR)/build +OUTPUT_DIR ?= $(HDL_BUILD_DIR)/output +FINAL_OUTPUT_DIR := $(OUTPUT_DIR)/$(PROJECT) + +# Tools +MKDIR := mkdir -p +CP := cp -f + +HDL_SRC_PATH := $(addprefix $(COMMON_DIR)/ips/, $(HDL_IPS)) $(HDL_DIR) +VHDSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vhd)) +VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.v)) +VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vh)) + +CONSTRAINTS ?= $(SRC_DIR)/$(PROJECT).ucf + +COMMON_OPTS := -intstyle xflow +XST_OPTS := +NGDBUILD_OPTS := +MAP_OPTS := -mt 2 +PAR_OPTS := -mt 4 +BITGEN_OPTS := -g Binary:Yes + +XILINX_PLATFORM := lin64 +PATH := $(PATH):$(XILINX_HOME)/bin/$(XILINX_PLATFORM) + +RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \ + cd $(HDL_BUILD_DIR) && $(XILINX_HOME)/bin/$(XILINX_PLATFORM)/$(1) + +compile: $(HDL_BUILD_DIR)/$(PROJECT).bin + +install: $(HDL_BUILD_DIR)/$(PROJECT).bin + $(MKDIR) $(FINAL_OUTPUT_DIR) + $(CP) $(HDL_BUILD_DIR)/$(PROJECT).bin $(FINAL_OUTPUT_DIR) + +clean: + rm -rf $(HDL_BUILD_DIR) + +$(HDL_BUILD_DIR)/$(PROJECT).bin: $(HDL_BUILD_DIR)/$(PROJECT).ncd + $(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \ + -w $(PROJECT).ncd $(PROJECT).bit + +$(HDL_BUILD_DIR)/$(PROJECT).ncd: $(HDL_BUILD_DIR)/$(PROJECT).map.ncd + $(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \ + -w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf + +$(HDL_BUILD_DIR)/$(PROJECT).map.ncd: $(HDL_BUILD_DIR)/$(PROJECT).ngd + $(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \ + -p $(TARGET_PART) \ + -w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf + +$(HDL_BUILD_DIR)/$(PROJECT).ngd: $(HDL_BUILD_DIR)/$(PROJECT).ngc + $(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \ + -p $(TARGET_PART) -uc $(CONSTRAINTS) \ + $(PROJECT).ngc $(PROJECT).ngd + +$(HDL_BUILD_DIR)/$(PROJECT).ngc: $(HDL_BUILD_DIR)/$(PROJECT).prj $(HDL_BUILD_DIR)/$(PROJECT).scr + $(call RUN,xst) $(COMMON_OPTS) -ifn $(PROJECT).scr + +$(HDL_BUILD_DIR)/$(PROJECT).scr: | $(HDL_BUILD_DIR) + @echo "Updating $@" + @mkdir -p $(HDL_BUILD_DIR) + @rm -f $@ + @echo "run" \ + "-ifn $(PROJECT).prj" \ + "-ofn $(PROJECT).ngc" \ + "-ifmt mixed" \ + "$(XST_OPTS)" \ + "-top $(TOPLEVEL)" \ + "-ofmt NGC" \ + "-p $(TARGET_PART)" \ + > $(HDL_BUILD_DIR)/$(PROJECT).scr + +$(HDL_BUILD_DIR)/$(PROJECT).prj: | $(HDL_BUILD_DIR) + @echo "Updating $@" + @rm -f $@ + @$(foreach file,$(VSOURCE),echo "verilog work \"$(file)\"" >> $@;) + @$(foreach file,$(VHDSOURCE),echo "vhdl work \"$(file)\"" >> $@;) + @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vhd),echo "vhdl $(lib) \"$(file)\"" >> $@;)) + @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.v),echo "verilog $(lib) \"$(file)\"" >> $@;)) + @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vh),echo "verilog $(lib) \"$(file)\"" >> $@;)) + +$(HDL_BUILD_DIR): + $(MKDIR) $(HDL_BUILD_DIR) + +.PHONY: clean compile install + diff --git a/contrib/firmware/angie/hdl/README b/contrib/firmware/angie/hdl/README new file mode 100644 index 0000000000..00578ff729 --- /dev/null +++ b/contrib/firmware/angie/hdl/README @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2023 by NanoXplore, France - all rights reserved + +This is the source code of Nanoxplore USB-JTAG Adapter Angie's bitstream. +This bitstream is for the "xc6slx9-2tqg144" Spartan-6 Xilinx FPGA. + +To generate this bitstream, you need to install Xilinx ISE Webpack 14.7 +You will need to give the ISE software path : export XILINX_HOME=path/to/ise/sw +Please set the enviromnent first by executing the ". ./set_env.sh" + +All you have to do now is to write your vhd and constrains codes. + +One all is setup, you can use the make commands: + make compile : to compile your (.vhd & .ucf) files in the "src" directory + A directory named "build" will be created, which contains all the generated + files including the bitstream file. + + make clean : to delete the build directory. diff --git a/contrib/firmware/angie/hdl/set_env.sh b/contrib/firmware/angie/hdl/set_env.sh new file mode 100644 index 0000000000..60e97375b9 --- /dev/null +++ b/contrib/firmware/angie/hdl/set_env.sh @@ -0,0 +1,14 @@ +#!/bin/bash +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2023 by NanoXplore, France - all rights reserved + +[ -z "${XILINX_HOME}" ] && export XILINX_HOME=/home/software/Xilinx/ISE/14.7/ISE_DS/ISE +export PATH="$XILINX_HOME:$PATH" +echo "SET XILINX_HOME to ${XILINX_HOME}" +# This is needed for isim +XILINX_HOME_BASE=${XILINX_HOME}/.. +for part in common EDK PlanAhead ISE +do + el=${XILINX_HOME_BASE}/${part} + . ${el}/.settings64.sh ${el} +done diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.ucf b/contrib/firmware/angie/hdl/src/angie_bitstream.ucf new file mode 100644 index 0000000000..9eb0c85c39 --- /dev/null +++ b/contrib/firmware/angie/hdl/src/angie_bitstream.ucf @@ -0,0 +1,50 @@ +## SPDX-License-Identifier: BSD-3-Clause +##-------------------------------------------------------------------------- +## Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6 +## Design Name: NJTAG USB-JTAG Adapter FPGA source code +## Module Name: _angie_openocd.ucf +## Target Device: XC6SLX9-2 TQ144 +## Tool versions: ISE Webpack 13.2 -> 14.2 +## Author: Ahmed BOUDJELIDA nanoXplore SAS +##-------------------------------------------------------------------------- +# WARNING: PullUps on JTAG inputs should be enabled after configuration +# (bitgen option) since the pins are not connected. + +net TRST LOC = 'P48' ; +net TMS LOC = 'P43' ; +net TCK LOC = 'P44' ; +net TDI LOC = 'P45' ; +net TDO LOC = 'P46' ; +net SRST LOC = 'P61' ; + +net SDA LOC = 'P50' ; +net SCL LOC = 'P51' ; +net SDA_DIR LOC = 'P56' ; +net SCL_DIR LOC = 'P57' ; + +net SI_TDO LOC = 'P16' ; +net SO_TRST LOC = 'P32' ; +net SO_TMS LOC = 'P27' ; +net SO_TCK LOC = 'P30' ; +net SO_TDI LOC = 'P26' ; +net SO_SRST LOC = 'P12' ; + +net SO_SDA_OUT LOC = 'P140' ; +net SO_SDA_IN LOC = 'P1' ; +net SO_SCL LOC = 'P137'; + +net ST_0 LOC = 'P29' ; +net ST_1 LOC = 'P21' ; +net ST_2 LOC = 'P11' ; + +net ST_4 LOC = 'P134' ; +net ST_5 LOC = 'P139' ; + +net FTP<0> LOC = 'P121' ; +net FTP<1> LOC = 'P120' ; +net FTP<2> LOC = 'P119' ; +net FTP<3> LOC = 'P116' ; +net FTP<4> LOC = 'P111' ; +net FTP<5> LOC = 'P112' ; +net FTP<6> LOC = 'P115' ; +net FTP<7> LOC = 'P114' ; diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd new file mode 100644 index 0000000000..6004bf2ff5 --- /dev/null +++ b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd @@ -0,0 +1,103 @@ +-- SPDX-License-Identifier: BSD-3-Clause +---------------------------------------------------------------------------- +-- Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6 +-- Design Name: NJTAG USB-JTAG Adapter FPGA source code +-- Module Name: _angie_openocd.vhd +-- Target Device: XC6SLX9-2 TQ144 +-- Tool versions: ISE Webpack 13.2 -> 14.2 +-- Author: Ahmed BOUDJELIDA nanoXplore SAS +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VComponents.all; + +entity S609 is port( + TRST : in std_logic; + TMS : in std_logic; + TCK : in std_logic; + TDI : in std_logic; + TDO : out std_logic; + SRST : in std_logic; + + SDA : inout std_logic; + SDA_DIR : in std_logic; + SCL : in std_logic; + SCL_DIR : in std_logic; + + FTP : out std_logic_vector(7 downto 0); -- Test points + SI_TDO : in std_logic; + ST_0 : out std_logic; + ST_1 : out std_logic; + ST_2 : out std_logic; + + ST_4 : out std_logic; + ST_5 : out std_logic; + + SO_SDA_OUT : out std_logic; + SO_SDA_IN : in std_logic; + SO_SCL : out std_logic; + + SO_TRST : out std_logic; + SO_TMS : out std_logic; + SO_TCK : out std_logic; + SO_TDI : out std_logic; + SO_SRST : out std_logic +); +end S609; + +architecture A_S609 of S609 is +begin + +--Directions: +ST_0 <= '0'; +ST_1 <= '1'; + +--TDO: +TDO <= not SI_TDO; + +--TRST - TCK - TMS - TDI: +SO_TRST <= TRST; +SO_TMS <= TMS; +SO_TCK <= TCK; +SO_TDI <= TDI; +ST_2 <= SRST; +SO_SRST <= '0'; + +SO_SCL <= SCL; + +SDA <= not(SO_SDA_IN) when (SDA_DIR = '1') else 'Z'; +SO_SDA_OUT <= SDA; + +process(SDA_DIR) +begin + if(SDA_DIR = '0') then + ST_5 <= '0'; + else + ST_5 <= '1'; + end if; +end process; + +process(SCL_DIR) +begin + if(SCL_DIR = '0') then + ST_4 <= '0'; + else + ST_4 <= '1'; + end if; +end process; + +--Points de test: +FTP(0) <= SDA; +FTP(1) <= SCL; +FTP(2) <= not(SO_SDA_IN); +FTP(3) <= SDA_DIR; +FTP(5) <= SRST; +FTP(4) <= SI_TDO; +FTP(6) <= '1'; +FTP(7) <= '1'; + +end A_S609; diff --git a/contrib/gen-stellaris-part-header.pl b/contrib/gen-stellaris-part-header.pl index 68f2889b31..3f982f4ab0 100755 --- a/contrib/gen-stellaris-part-header.pl +++ b/contrib/gen-stellaris-part-header.pl @@ -1,4 +1,6 @@ #!/usr/bin/perl +# SPDX-License-Identifier: GPL-2.0-or-later + # Automatically generates the StellarisParts struct in src/flash/nor/stellaris.c # Uses the header files from TI/Luminary's StellarisWare complete Firmware Development Package # available from: http://www.luminarymicro.com/products/software_updates.html diff --git a/contrib/itmdump.c b/contrib/itmdump.c index 88099040a6..7c93a3963f 100644 --- a/contrib/itmdump.c +++ b/contrib/itmdump.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2010 by David Brownell - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or (at - * your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ +// SPDX-License-Identifier: GPL-3.0-or-later + +/* Copyright (C) 2010 by David Brownell */ /* * Simple utility to parse and dump ARM Cortex-M3 SWO trace output. Once the @@ -56,9 +43,9 @@ unsigned int dump_swit; * NOTE that this specific encoding could be space-optimized; and that * trace data streams could also be history-sensitive. */ -static void show_task(int port, unsigned data) +static void show_task(int port, unsigned int data) { - unsigned code = data >> 16; + unsigned int code = data >> 16; char buf[16]; if (dump_swit) @@ -90,7 +77,7 @@ static void show_task(int port, unsigned data) static void show_reserved(FILE *f, char *label, int c) { - unsigned i; + unsigned int i; if (dump_swit) return; @@ -109,9 +96,9 @@ static void show_reserved(FILE *f, char *label, int c) printf("\n"); } -static bool read_varlen(FILE *f, int c, unsigned *value) +static bool read_varlen(FILE *f, int c, unsigned int *value) { - unsigned size; + unsigned int size; unsigned char buf[4]; *value = 0; @@ -148,8 +135,8 @@ static bool read_varlen(FILE *f, int c, unsigned *value) static void show_hard(FILE *f, int c) { - unsigned type = c >> 3; - unsigned value; + unsigned int type = c >> 3; + unsigned int value; char *label; if (dump_swit) @@ -243,16 +230,16 @@ static void show_hard(FILE *f, int c) */ struct { int port; - void (*show)(int port, unsigned data); + void (*show)(int port, unsigned int data); } format[] = { { .port = 31, .show = show_task, }, }; static void show_swit(FILE *f, int c) { - unsigned port = c >> 3; - unsigned value = 0; - unsigned i; + unsigned int port = c >> 3; + unsigned int value = 0; + unsigned int i; if (port + 1 == dump_swit) { if (!read_varlen(f, c, &value)) @@ -285,7 +272,7 @@ static void show_swit(FILE *f, int c) static void show_timestamp(FILE *f, int c) { - unsigned counter = 0; + unsigned int counter = 0; char *label = ""; bool delayed = false; diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c index 7da78c6471..9ad633b61c 100644 --- a/contrib/libdcc/dcc_stdio.c +++ b/contrib/libdcc/dcc_stdio.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2008 by Dominic Rath * * Dominic.Rath@gmx.de * @@ -5,19 +7,6 @@ * spen@spen-soft.co.uk * * Copyright (C) 2008 by Frederik Kriewtz * * frederik@kriewitz.eu * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "dcc_stdio.h" diff --git a/contrib/libdcc/dcc_stdio.h b/contrib/libdcc/dcc_stdio.h index f4a5d7e32e..3447b8c6bd 100644 --- a/contrib/libdcc/dcc_stdio.h +++ b/contrib/libdcc/dcc_stdio.h @@ -1,21 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2008 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #ifndef DCC_STDIO_H diff --git a/contrib/libdcc/example.c b/contrib/libdcc/example.c index 99b7bf6024..7c7d93670e 100644 --- a/contrib/libdcc/example.c +++ b/contrib/libdcc/example.c @@ -1,21 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * Copyright (C) 2008 by Frederik Kriewtz * * frederik@kriewitz.eu * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "dcc_stdio.h" diff --git a/contrib/list_example.c b/contrib/list_example.c index 0f62b864b5..1f28dc2dbd 100644 --- a/contrib/list_example.c +++ b/contrib/list_example.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* Copyright (C) 2021 by Andreas Fritiofson */ /* @@ -12,7 +12,7 @@ #include #include -static LIST_HEAD(threads); +static OOCD_LIST_HEAD(threads); struct thread { int id; diff --git a/contrib/loaders/Makefile b/contrib/loaders/Makefile index 0a637aff59..ae6a5ebad7 100644 --- a/contrib/loaders/Makefile +++ b/contrib/loaders/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + .PHONY: arm clean-arm all: arm stm8 diff --git a/contrib/loaders/checksum/Makefile b/contrib/loaders/checksum/Makefile index 623e42576e..5789a0824e 100644 --- a/contrib/loaders/checksum/Makefile +++ b/contrib/loaders/checksum/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../src/helper/bin2char.sh ARM_CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/checksum/armv4_5_crc.s b/contrib/loaders/checksum/armv4_5_crc.s index 8f62dc89f9..b3ecb58472 100644 --- a/contrib/loaders/checksum/armv4_5_crc.s +++ b/contrib/loaders/checksum/armv4_5_crc.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /* diff --git a/contrib/loaders/checksum/armv7m_crc.s b/contrib/loaders/checksum/armv7m_crc.s index 923875a089..8cb7f2dc17 100644 --- a/contrib/loaders/checksum/armv7m_crc.s +++ b/contrib/loaders/checksum/armv7m_crc.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /* diff --git a/contrib/loaders/checksum/mips32.s b/contrib/loaders/checksum/mips32.s index 3073d87a34..52de547b45 100644 --- a/contrib/loaders/checksum/mips32.s +++ b/contrib/loaders/checksum/mips32.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .global main diff --git a/contrib/loaders/checksum/riscv_crc.c b/contrib/loaders/checksum/riscv_crc.c index e437b66168..9931af5ff6 100644 --- a/contrib/loaders/checksum/riscv_crc.c +++ b/contrib/loaders/checksum/riscv_crc.c @@ -1,7 +1,6 @@ -/* - * SPDX-License-Identifier: GPL-2.0-or-later - * Copyright (C) 2009-2021 Free Software Foundation, Inc. - */ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. */ /* Copied from https://github.com/gcc-mirror/gcc/blob/master/libiberty/crc32.c * and then tweaked a little. */ diff --git a/contrib/loaders/debug/xscale/Makefile b/contrib/loaders/debug/xscale/Makefile index a0455c7331..cdecd144bd 100644 --- a/contrib/loaders/debug/xscale/Makefile +++ b/contrib/loaders/debug/xscale/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/debug/xscale/debug_handler.S b/contrib/loaders/debug/xscale/debug_handler.S index 0f62d9c14d..9e1d65f93c 100644 --- a/contrib/loaders/debug/xscale/debug_handler.S +++ b/contrib/loaders/debug/xscale/debug_handler.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "protocol.h" diff --git a/contrib/loaders/debug/xscale/debug_handler.ld b/contrib/loaders/debug/xscale/debug_handler.ld index d943b13b3e..0e46cb13fb 100644 --- a/contrib/loaders/debug/xscale/debug_handler.ld +++ b/contrib/loaders/debug/xscale/debug_handler.ld @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* identify the Entry Point */ ENTRY(reset_handler) diff --git a/contrib/loaders/debug/xscale/protocol.h b/contrib/loaders/debug/xscale/protocol.h index cb01655ee1..bd29cf12fb 100644 --- a/contrib/loaders/debug/xscale/protocol.h +++ b/contrib/loaders/debug/xscale/protocol.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #define REG_R0 0 diff --git a/contrib/loaders/erase_check/Makefile b/contrib/loaders/erase_check/Makefile index 1a0fd9e3f5..d49c049c4d 100644 --- a/contrib/loaders/erase_check/Makefile +++ b/contrib/loaders/erase_check/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../src/helper/bin2char.sh ARM_CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/erase_check/armv4_5_erase_check.s b/contrib/loaders/erase_check/armv4_5_erase_check.s index 6c7d27f058..dedadaa5d3 100644 --- a/contrib/loaders/erase_check/armv4_5_erase_check.s +++ b/contrib/loaders/erase_check/armv4_5_erase_check.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /* diff --git a/contrib/loaders/erase_check/armv7m_erase_check.s b/contrib/loaders/erase_check/armv7m_erase_check.s index 3303c8778b..429b6939f0 100644 --- a/contrib/loaders/erase_check/armv7m_erase_check.s +++ b/contrib/loaders/erase_check/armv7m_erase_check.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /* diff --git a/contrib/loaders/erase_check/stm8_erase_check.s b/contrib/loaders/erase_check/stm8_erase_check.s index 04cde5b1bf..116ac59f10 100644 --- a/contrib/loaders/erase_check/stm8_erase_check.s +++ b/contrib/loaders/erase_check/stm8_erase_check.s @@ -1,20 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* -* Copyright (C) 2017 Ake Rehnman -* ake.rehnman(at)gmail.com -* -* This program is free software: you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation, either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ + * Copyright (C) 2017 Ake Rehnman + * ake.rehnman(at)gmail.com + */ ;; ;; erase check memory code ;; diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_16.s b/contrib/loaders/flash/armv4_5_cfi_intel_16.s index c35b6515f8..0c5611dc55 100644 --- a/contrib/loaders/flash/armv4_5_cfi_intel_16.s +++ b/contrib/loaders/flash/armv4_5_cfi_intel_16.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_32.s b/contrib/loaders/flash/armv4_5_cfi_intel_32.s index db477178a7..473a78234d 100644 --- a/contrib/loaders/flash/armv4_5_cfi_intel_32.s +++ b/contrib/loaders/flash/armv4_5_cfi_intel_32.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_8.s b/contrib/loaders/flash/armv4_5_cfi_intel_8.s index d50acd2ade..18f4bb811c 100644 --- a/contrib/loaders/flash/armv4_5_cfi_intel_8.s +++ b/contrib/loaders/flash/armv4_5_cfi_intel_8.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_span_16.s b/contrib/loaders/flash/armv4_5_cfi_span_16.s index 532727140f..da02037f64 100644 --- a/contrib/loaders/flash/armv4_5_cfi_span_16.s +++ b/contrib/loaders/flash/armv4_5_cfi_span_16.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s b/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s index 919f6e1647..fb7679e4ce 100644 --- a/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s +++ b/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_span_32.s b/contrib/loaders/flash/armv4_5_cfi_span_32.s index c8f87b12b0..7e377e25fc 100644 --- a/contrib/loaders/flash/armv4_5_cfi_span_32.s +++ b/contrib/loaders/flash/armv4_5_cfi_span_32.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv4_5_cfi_span_8.s b/contrib/loaders/flash/armv4_5_cfi_span_8.s index 46018e18b8..ad4ee267b9 100644 --- a/contrib/loaders/flash/armv4_5_cfi_span_8.s +++ b/contrib/loaders/flash/armv4_5_cfi_span_8.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv7m_cfi_span_16.s b/contrib/loaders/flash/armv7m_cfi_span_16.s index d4915a78c3..0a5279e3db 100644 --- a/contrib/loaders/flash/armv7m_cfi_span_16.s +++ b/contrib/loaders/flash/armv7m_cfi_span_16.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s index 5b29a3bda7..592c811bcc 100644 --- a/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s +++ b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * Copyright (C) 2010 Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/armv7m_io.s b/contrib/loaders/flash/armv7m_io.s index f6dbbe9bf9..9d8439e1a6 100644 --- a/contrib/loaders/flash/armv7m_io.s +++ b/contrib/loaders/flash/armv7m_io.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2013 by Henrik Nilsson * * henrik.nilsson@bytequest.se * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script b/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script index 85450c14c0..1099d83de9 100644 --- a/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script +++ b/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + soft_reset_halt load_image at91sam7x_ocl.bin 0x200000 resume 0x200000 diff --git a/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld b/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld index 8cb21184f8..b093523781 100644 --- a/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld +++ b/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld @@ -1,32 +1,7 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /**************************************************************************** * Copyright (c) 2006 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* **************************************************************************** * * History: diff --git a/contrib/loaders/flash/at91sam7x/crt.s b/contrib/loaders/flash/at91sam7x/crt.s index 94ed66d738..77df43ce26 100644 --- a/contrib/loaders/flash/at91sam7x/crt.s +++ b/contrib/loaders/flash/at91sam7x/crt.s @@ -1,32 +1,7 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /**************************************************************************** * Copyright (c) 2006 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* **************************************************************************** * * History: diff --git a/contrib/loaders/flash/at91sam7x/dcc.c b/contrib/loaders/flash/at91sam7x/dcc.c index a5c32e7e6c..ee95a34449 100644 --- a/contrib/loaders/flash/at91sam7x/dcc.c +++ b/contrib/loaders/flash/at91sam7x/dcc.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "dcc.h" diff --git a/contrib/loaders/flash/at91sam7x/dcc.h b/contrib/loaders/flash/at91sam7x/dcc.h index 428bf49ff4..5baca6ca1f 100644 --- a/contrib/loaders/flash/at91sam7x/dcc.h +++ b/contrib/loaders/flash/at91sam7x/dcc.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #ifndef dccH #define dccH diff --git a/contrib/loaders/flash/at91sam7x/main.c b/contrib/loaders/flash/at91sam7x/main.c index 47c9440827..a29c6e605b 100644 --- a/contrib/loaders/flash/at91sam7x/main.c +++ b/contrib/loaders/flash/at91sam7x/main.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "platform.h" diff --git a/contrib/loaders/flash/at91sam7x/makefile b/contrib/loaders/flash/at91sam7x/makefile index 39482976ec..3d101c1a0e 100644 --- a/contrib/loaders/flash/at91sam7x/makefile +++ b/contrib/loaders/flash/at91sam7x/makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ############################################################################################## # Start of default section # diff --git a/contrib/loaders/flash/at91sam7x/ocl.h b/contrib/loaders/flash/at91sam7x/ocl.h index bd8a5f7a02..e458b5864a 100644 --- a/contrib/loaders/flash/at91sam7x/ocl.h +++ b/contrib/loaders/flash/at91sam7x/ocl.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #ifndef OCL_H #define OCL_H diff --git a/contrib/loaders/flash/at91sam7x/platform.h b/contrib/loaders/flash/at91sam7x/platform.h index 3dfa4dc088..538df9b48d 100644 --- a/contrib/loaders/flash/at91sam7x/platform.h +++ b/contrib/loaders/flash/at91sam7x/platform.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #ifndef platformH #define platformH diff --git a/contrib/loaders/flash/at91sam7x/samflash.c b/contrib/loaders/flash/at91sam7x/samflash.c index 30953942ab..fcb76fbf98 100644 --- a/contrib/loaders/flash/at91sam7x/samflash.c +++ b/contrib/loaders/flash/at91sam7x/samflash.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #include "samflash.h" diff --git a/contrib/loaders/flash/at91sam7x/samflash.h b/contrib/loaders/flash/at91sam7x/samflash.h index 18973a70d8..059c2b2ea0 100644 --- a/contrib/loaders/flash/at91sam7x/samflash.h +++ b/contrib/loaders/flash/at91sam7x/samflash.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * * chromy@asix.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #ifndef samflashH #define samflashH diff --git a/contrib/loaders/flash/at91sam7x/samregs.h b/contrib/loaders/flash/at91sam7x/samregs.h index b206fd28e4..3e34a8d6d9 100644 --- a/contrib/loaders/flash/at91sam7x/samregs.h +++ b/contrib/loaders/flash/at91sam7x/samregs.h @@ -1,32 +1,8 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE - * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF - * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * For additional information see http://www.ethernut.de/ */ diff --git a/contrib/loaders/flash/bluenrg-x/Makefile b/contrib/loaders/flash/bluenrg-x/Makefile index 1a5cfc013f..81d479aa55 100644 --- a/contrib/loaders/flash/bluenrg-x/Makefile +++ b/contrib/loaders/flash/bluenrg-x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c index f09f7f58ab..3c1988f112 100644 --- a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c +++ b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* To be built with arm-none-eabi-gcc -c -mthumb -mcpu=cortex-m0 -O3 bluenrgx.c */ /* Then postprocess output of command "arm-none-eabi-objdump -d bluenrgx.o" to make a C array of bytes */ @@ -50,7 +52,7 @@ static inline __attribute__((always_inline)) uint32_t flashWrite(uint32_t addres /* Clear the IRQ flags */ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_IRQRAW)) = 0x0000003F; /* Load the flash address to write */ - *((volatile uint32_t *)(flash_regs_base + FLASH_REG_ADDRESS)) = (uint16_t)((address + index - MFB_BOTTOM) >> 2); + *((volatile uint32_t *)(flash_regs_base + FLASH_REG_ADDRESS)) = (uint32_t)((address + index - MFB_BOTTOM) >> 2); /* Prepare and load the data to flash */ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA0)) = flash_word[0]; *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA1)) = flash_word[1]; diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc index ff05634bb2..146a6bedeb 100644 --- a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc +++ b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc @@ -1,17 +1,19 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ -0x05,0x93,0x43,0x68,0x14,0x9e,0x09,0x93,0x05,0x9b,0x05,0x00,0x07,0x91,0x06,0x92, -0x01,0x24,0xb1,0x46,0x00,0x2b,0x68,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0, -0x2b,0x68,0x00,0x2b,0x61,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x5e,0xd9,0x6b,0x68, -0x07,0x9a,0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x4a,0x46,0x00,0x21,0x03,0x93,0xd1,0x60, -0x00,0x2b,0x42,0xd0,0x40,0x22,0x4a,0x44,0x90,0x46,0x44,0x22,0x4a,0x44,0x00,0x92, -0x48,0x22,0x4a,0x44,0x93,0x46,0x4c,0x22,0x27,0x4f,0x4a,0x44,0xbc,0x46,0x4e,0x46, -0x92,0x46,0x06,0x99,0x4b,0x46,0x61,0x44,0x08,0x00,0x00,0x99,0x18,0x36,0x6a,0x68, -0x08,0x95,0x8c,0x46,0x55,0x46,0xda,0x46,0xb3,0x46,0x10,0x33,0x04,0x92,0x11,0x68, -0x5e,0x46,0x00,0x91,0x51,0x68,0x97,0x68,0x01,0x91,0xd1,0x68,0x02,0x91,0x3f,0x21, -0x19,0x60,0x81,0x03,0x09,0x0c,0x31,0x60,0x46,0x46,0x00,0x99,0x31,0x60,0x66,0x46, -0x01,0x99,0x31,0x60,0x56,0x46,0x02,0x99,0x37,0x60,0x29,0x60,0xcc,0x26,0x49,0x46, -0x0e,0x60,0x19,0x68,0x0c,0x42,0xfc,0xd0,0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30, -0x51,0x1a,0x8e,0x42,0xdb,0xd8,0x08,0x9d,0x6a,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46, -0x63,0x44,0x06,0x93,0x07,0x9a,0x6b,0x68,0x9a,0x42,0x01,0xd8,0x09,0x9b,0x6b,0x60, -0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,0x96,0xd1,0x00,0xbe,0x2b,0x68,0x6a,0x68, -0x9b,0x1a,0x9f,0xd5,0x90,0xe7,0xc0,0x46,0x00,0x00,0xfc,0xef, +0x16,0x9e,0x05,0x00,0x01,0x24,0xb1,0x46,0x06,0x93,0x43,0x68,0x08,0x91,0x07,0x92, +0x09,0x93,0x06,0x9b,0x00,0x2b,0x6f,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0, +0x2b,0x68,0x00,0x2b,0x68,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x65,0xd9,0x6b,0x68, +0x08,0x9a,0xd3,0x1a,0x0b,0x93,0x0b,0x9b,0x0f,0x2b,0xea,0xdd,0x4a,0x46,0x00,0x21, +0x0b,0x9b,0xd1,0x60,0x04,0x93,0x00,0x2b,0x43,0xd0,0x31,0x4a,0x07,0x9b,0x94,0x46, +0x40,0x22,0x4a,0x44,0x90,0x46,0x44,0x22,0x4a,0x44,0x63,0x44,0x94,0x46,0x48,0x22, +0x4a,0x44,0x93,0x46,0x05,0x93,0x4c,0x22,0x4b,0x46,0x4a,0x44,0x10,0x33,0x4e,0x46, +0x92,0x46,0x00,0x93,0x2b,0x00,0x18,0x36,0x6a,0x68,0x55,0x46,0xb2,0x46,0x5e,0x46, +0x9b,0x46,0x10,0x68,0x57,0x68,0x01,0x90,0x3f,0x20,0x00,0x9b,0x02,0x97,0x97,0x68, +0x03,0x97,0xd7,0x68,0x18,0x60,0x53,0x46,0x05,0x98,0x40,0x18,0x80,0x08,0x18,0x60, +0x43,0x46,0x01,0x98,0x18,0x60,0x63,0x46,0x02,0x98,0x18,0x60,0x03,0x98,0x4b,0x46, +0x30,0x60,0xcc,0x20,0x2f,0x60,0x18,0x60,0x00,0x9b,0x18,0x68,0x04,0x42,0xfc,0xd0, +0x58,0x46,0x10,0x32,0x42,0x60,0x04,0x98,0x10,0x31,0x00,0x93,0x88,0x42,0xd8,0xd8, +0x5d,0x46,0x07,0x9a,0x0b,0x9b,0x94,0x46,0x9c,0x44,0x63,0x46,0x08,0x9a,0x07,0x93, +0x6b,0x68,0x93,0x42,0x01,0xd3,0x09,0x9b,0x6b,0x60,0x06,0x9a,0x0b,0x9b,0xd3,0x1a, +0x06,0x93,0x06,0x9b,0x00,0x2b,0x8f,0xd1,0x00,0xbe,0x2b,0x68,0x6a,0x68,0x9b,0x1a, +0x0b,0x93,0x0b,0x9b,0x00,0x2b,0x00,0xdb,0x95,0xe7,0x00,0x23,0x0b,0x93,0x92,0xe7, +0x00,0x00,0xfc,0xef, diff --git a/contrib/loaders/flash/cc26xx/Makefile b/contrib/loaders/flash/cc26xx/Makefile index 7cc1fb3c4d..550e1d098a 100644 --- a/contrib/loaders/flash/cc26xx/Makefile +++ b/contrib/loaders/flash/cc26xx/Makefile @@ -1,3 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds index 9a126fc2bc..79cbfc4fcf 100644 --- a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds +++ b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ /* Entry Point */ diff --git a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc index 2246a36706..d20d9be44a 100644 --- a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc +++ b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc @@ -1,249 +1,248 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ 0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48, -0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, -0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, -0x98,0x13,0x00,0x20,0x08,0xb5,0x07,0x4b,0x07,0x48,0x03,0x33,0x1b,0x1a,0x06,0x2b, -0x04,0xd9,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x5c,0xf8,0x08,0xbc,0x01,0xbc, -0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00, -0x08,0x48,0x09,0x49,0x09,0x1a,0x89,0x10,0x08,0xb5,0xcb,0x0f,0x59,0x18,0x49,0x10, -0x04,0xd0,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x44,0xf8,0x08,0xbc,0x01,0xbc, -0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00, -0x10,0xb5,0x08,0x4c,0x23,0x78,0x00,0x2b,0x09,0xd1,0xff,0xf7,0xcb,0xff,0x06,0x4b, +0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xff,0xf6, +0xfa,0xaf,0x00,0xf0,0x71,0xf9,0xfe,0xe7,0xe0,0x0e,0x00,0x20,0x44,0x13,0x00,0x20, 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+0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xc8,0xf1,0xff,0x7f,0x01,0x00,0x00,0x00, +0x18,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff, +0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x08,0x0f,0x00,0x20, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf4,0x11,0x00,0x20, +0x5c,0x12,0x00,0x20,0xc4,0x12,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x0e,0x00,0x20, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -307,8 +306,9 @@ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00, -0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x08,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00, +0x69,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds index fb7cc56110..2394c0cc0c 100644 --- a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds +++ b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ /* Entry Point */ diff --git a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc index 9adb919f4e..345079b08f 100644 --- a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc +++ b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc @@ -1,258 +1,257 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/contrib/loaders/flash/cc26xx/flash.c b/contrib/loaders/flash/cc26xx/flash.c index c19cb735d9..641054943f 100644 --- a/contrib/loaders/flash/cc26xx/flash.c +++ b/contrib/loaders/flash/cc26xx/flash.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include @@ -68,7 +42,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t); * ******************************************************************************/ static void issue_fsm_command(flash_state_command_t command); -static void enable_sectors_for_write(void); +static void enable_sectors_for_write(uint32_t); static uint32_t scale_cycle_values(uint32_t specified_timing, uint32_t scale_value); static void set_write_mode(void); @@ -106,42 +80,51 @@ uint32_t flash_bank_erase(bool force_precondition) uint32_t error_return; uint32_t sector_address; uint32_t reg_val; + uint32_t bank_no; + uint32_t top_bank_start_addr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; - /* Enable all sectors for erase. */ - enable_sectors_for_write(); + for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) { + /* Enable all sectors for erase. */ + enable_sectors_for_write(bank_no); - /* Clear the Status register. */ - issue_fsm_command(FAPI_CLEAR_STATUS); + /* Clear the Status register. */ + issue_fsm_command(FAPI_CLEAR_STATUS); - /* Enable erase of all sectors and enable precondition if required. */ - reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; - if (force_precondition) - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= - FLASH_FSM_ST_MACHINE_DO_PRECOND; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + /* Enable erase of all sectors and enable precondition if required. */ + reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if (force_precondition) + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - /* Issue the bank erase command to the FSM. */ - issue_fsm_command(FAPI_ERASE_BANK); + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no * top_bank_start_addr); - /* Wait for erase to finish. */ - while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY) - ; + /* Issue the bank erase command to the FSM. */ + issue_fsm_command(FAPI_ERASE_BANK); - /* Update status. */ - error_return = flash_check_fsm_for_error(); + /* Wait for erase to finish. */ + while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY) + ; - /* Disable sectors for erase. */ - flash_disable_sectors_for_write(); + /* Update status. */ + error_return = flash_check_fsm_for_error(); - /* Set configured precondition mode since it may have been forced on. */ - if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) { - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= - ~FLASH_FSM_ST_MACHINE_DO_PRECOND; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + /* Set configured precondition mode since it may have been forced on. */ + if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + if (error_return != FAPI_STATUS_SUCCESS) + break; } /* Program security data to default values in the customer configuration */ @@ -154,6 +137,9 @@ uint32_t flash_bank_erase(bool force_precondition) CCFG_SIZE_SECURITY); } + /* Disable sectors for erase. */ + flash_disable_sectors_for_write(); + /* Return status of operation. */ return error_return; } @@ -187,23 +173,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count) ******************************************************************************/ void flash_disable_sectors_for_write(void) { + uint32_t bank_no; + /* Configure flash back to read mode */ set_read_mode(); - /* Disable Level 1 Protection. */ - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) { - /* Disable all sectors for erase and programming. */ - HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + /* Select flash bank. */ + HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no; - /* Enable Level 1 Protection. */ - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + /* Disable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - /* Protect sectors from sector erase. */ - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + /* Disable all sectors for erase and programming. */ + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + /* Enable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + /* Protect sectors from sector erase. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0; } /****************************************************************************** @@ -240,7 +237,7 @@ static void issue_fsm_command(flash_state_command_t command) * the FLASH_O_FSM_SECTOR1 register. * ******************************************************************************/ -static void enable_sectors_for_write(void) +static void enable_sectors_for_write(uint32_t bank_no) { /* Trim flash module for program/erase operation. */ trim_for_write(); @@ -249,7 +246,7 @@ static void enable_sectors_for_write(void) set_write_mode(); /* Select flash bank. */ - HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no; /* Disable Level 1 Protection. */ HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h index dd0a3745a5..21df89bd63 100644 --- a/contrib/loaders/flash/cc26xx/flash.h +++ b/contrib/loaders/flash/cc26xx/flash.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H @@ -272,6 +246,46 @@ static inline uint32_t flash_check_fsm_for_ready(void) return FAPI_STATUS_FSM_READY; } +/****************************************************************************** + * + * Get the number of banks + * + * This function returns the number of bank of the flash. + * + * Returns the number of banks + * + ******************************************************************************/ +static inline uint32_t flash_bank_count(void) +{ + uint32_t bank_count; + + bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >> + FLASH_FCFG_BANK_MAIN_NUM_BANK_S; + + return bank_count; +} + +/****************************************************************************** + * + * Get the size of the bank. + * + * This function returns the size of the main bank in number of bytes. + * + * Returns the flash size in number of bytes. + * + ******************************************************************************/ +static inline uint8_t flash_bank_width(void) +{ + uint8_t bank_width; + + bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + return bank_width; +} + /****************************************************************************** * * Erase a flash sector. diff --git a/contrib/loaders/flash/cc26xx/flashloader.c b/contrib/loaders/flash/cc26xx/flashloader.c index 2eaf618647..8e9636d45b 100644 --- a/contrib/loaders/flash/cc26xx/flashloader.c +++ b/contrib/loaders/flash/cc26xx/flashloader.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/cc26xx/flashloader.h b/contrib/loaders/flash/cc26xx/flashloader.h index aec74aaa91..a6695576e7 100644 --- a/contrib/loaders/flash/cc26xx/flashloader.h +++ b/contrib/loaders/flash/cc26xx/flashloader.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h b/contrib/loaders/flash/cc26xx/hw_regs.h index 830d3af257..753db17c52 100644 --- a/contrib/loaders/flash/cc26xx/hw_regs.h +++ b/contrib/loaders/flash/cc26xx/hw_regs.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H @@ -142,6 +116,10 @@ /* FMC Sequential Pump Information */ #define FLASH_O_FSEQPMP 0x000020A8 +#define FLASH_O_FADDR 0x00002110 + +#define FLASH_O_FWPWRITE0 0x00002120 + /* FMC FSM Command */ #define FLASH_O_FSM_CMD 0x0000220C @@ -205,9 +183,14 @@ /* FMC FSM Sector Erased 2 */ #define FLASH_O_FSM_SECTOR2 0x000022C4 +#define FLASH_O_FCFG_BANK 0x00002400 + /* FMC Flash Bank 0 Starting Address */ #define FLASH_O_FCFG_B0_START 0x00002410 +/* FMC Flash Bank 1 Starting Address */ +#define FLASH_O_FCFG_B1_START 0x00002414 + /* FMC Flash Bank 0 Sector Size 0 */ #define FLASH_O_FCFG_B0_SSIZE0 0x00002430 @@ -1379,4 +1362,16 @@ * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */ #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 +/* Field: [3:0] MAIN_NUM_BANK */ +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +/* Field: [23:0] B1_START_ADDR */ +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +/* Field: [15:4] MAIN_BANK_WIDTH */ +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */ diff --git a/contrib/loaders/flash/cc26xx/main.c b/contrib/loaders/flash/cc26xx/main.c index 13204b4580..6b626a3b84 100644 --- a/contrib/loaders/flash/cc26xx/main.c +++ b/contrib/loaders/flash/cc26xx/main.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/cc26xx/startup.c b/contrib/loaders/flash/cc26xx/startup.c index 53d8ea8c75..3117eb10a1 100644 --- a/contrib/loaders/flash/cc26xx/startup.c +++ b/contrib/loaders/flash/cc26xx/startup.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/cc3220sf/Makefile b/contrib/loaders/flash/cc3220sf/Makefile index d1dcc25fda..1c745770f3 100644 --- a/contrib/loaders/flash/cc3220sf/Makefile +++ b/contrib/loaders/flash/cc3220sf/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/cc3220sf/cc3220sf.s b/contrib/loaders/flash/cc3220sf/cc3220sf.s index cffcfa0532..ea82c85a7d 100644 --- a/contrib/loaders/flash/cc3220sf/cc3220sf.s +++ b/contrib/loaders/flash/cc3220sf/cc3220sf.s @@ -1,18 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2017 by Texas Instruments, Inc. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ /* Params: diff --git a/contrib/loaders/flash/cortex-m0.S b/contrib/loaders/flash/cortex-m0.S index b4416e783c..74b071dca8 100644 --- a/contrib/loaders/flash/cortex-m0.S +++ b/contrib/loaders/flash/cortex-m0.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2014 by Angus Gratton * * Derived from stm32f1x.S: @@ -5,19 +7,6 @@ * andreas.fritiofson@gmail.com * * Copyright (C) 2013 by Roman Dmitrienko * * me@iamroman.org * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text .syntax unified diff --git a/contrib/loaders/flash/dw-spi/Makefile b/contrib/loaders/flash/dw-spi/Makefile new file mode 100644 index 0000000000..e86827882f --- /dev/null +++ b/contrib/loaders/flash/dw-spi/Makefile @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +TOOLCHAIN:=mipsel-linux-gnu- +CC:=$(TOOLCHAIN)gcc +OBJCOPY:=$(TOOLCHAIN)objcopy +CFLAGS:=-O2 -Wall -Wextra -fpic -Wno-int-to-pointer-cast +SRC=dw-spi.c +OBJ=$(patsubst %.c, %.o,$(SRC)) + +# sparx-iv +ifeq ($(TOOLCHAIN),mipsel-linux-gnu-) + CFLAGS+= -march=24kec +endif + +all: \ + $(TOOLCHAIN)transaction.inc \ + $(TOOLCHAIN)erase.inc \ + $(TOOLCHAIN)check_fill.inc \ + $(TOOLCHAIN)program.inc \ + $(TOOLCHAIN)read.inc + +$(TOOLCHAIN)%.bin: $(OBJ) + $(OBJCOPY) --dump-section .$*=$@ $< + +%.inc: %.bin + xxd -i > $@ < $< + +.PHONY: clean +clean: + rm -rf .ccls-cache + find . \( \ + -iname "*.o" \ + -o -iname "*.bin" \ + -o -iname "*.inc" \ + \) -delete diff --git a/contrib/loaders/flash/dw-spi/dw-spi.c b/contrib/loaders/flash/dw-spi/dw-spi.c new file mode 100644 index 0000000000..66b743913c --- /dev/null +++ b/contrib/loaders/flash/dw-spi/dw-spi.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/** + * @file + * Helper functions for DesignWare SPI Core driver. + * These helpers are loaded into CPU and execute Flash manipulation algorithms + * at full CPU speed. Due to inability to control nCS pin, this is the only way + * to communicate with Flash chips connected via DW SPI serial interface. + * + * In order to avoid using stack, all functions used in helpers are inlined. + * Software breakpoints are used to terminate helpers. + * + * Pushing byte to TX FIFO does not make byte immediately available in RX FIFO + * and nCS is only asserted when TX FIFO is not empty. General approach is to + * fill TX FIFO with as many bytes as possible, at the same time reading + * available bytes from RX FIFO. + * + * This file contains helper functions. + */ + +#include "dw-spi.h" + +#include "../../../../src/flash/nor/dw-spi-helper.h" + +/** + * @brief Generic flash transaction. + * + * @param[in] arg: Function arguments. + */ +__attribute__((section(".transaction"))) void +transaction(struct dw_spi_transaction *arg) +{ + register uint8_t *buffer_tx = (uint8_t *)arg->buffer; + register uint8_t *buffer_rx = buffer_tx; + register uint32_t size = arg->size; + register volatile uint8_t *status = (uint8_t *)arg->status_reg; + register volatile uint8_t *data = (uint8_t *)arg->data_reg; + + wait_tx_finish(status); + flush_rx(status, data); + + for (; size > 0; size--) { + send_u8(status, data, *buffer_tx++); + if (arg->read_flag && rx_available(status)) + *buffer_rx++ = rcv_byte(data); + } + + // Pushed all data to TX FIFO. Read bytes left in RX FIFO. + if (arg->read_flag) { + while (buffer_rx < buffer_tx) { + wait_rx_available(status); + *buffer_rx++ = rcv_byte(data); + } + } + + RETURN; +} + +/** + * @brief Check flash sectors are filled with pattern. Primary use for + * checking sector erase state. + * + * @param[in] arg: Function arguments. + */ +__attribute__((section(".check_fill"))) void +check_fill(struct dw_spi_check_fill *arg) +{ + register uint32_t tx_size; + register uint32_t rx_size; + register uint32_t dummy_count; + register uint8_t filled; + register uint8_t *fill_status_array = (uint8_t *)arg->fill_status_array; + register volatile uint8_t *status = (uint8_t *)arg->status_reg; + register volatile uint8_t *data = (uint8_t *)arg->data_reg; + + for (; arg->sector_count > 0; arg->sector_count--, + arg->address += arg->sector_size, + fill_status_array++) { + wait_tx_finish(status); + flush_rx(status, data); + + /* + * Command byte and address bytes make up for dummy_count number of + * bytes, that must be skipped in RX FIFO before actual data arrives. + */ + send_u8(status, data, arg->read_cmd); + if (arg->four_byte_mode) { + dummy_count = 1 + 4; // Command byte + 4 address bytes + send_u32(status, data, arg->address); + } else { + dummy_count = 1 + 3; // Command byte + 3 address bytes + send_u24(status, data, arg->address); + } + + for (tx_size = arg->sector_size, rx_size = arg->sector_size, filled = 1; + tx_size > 0; tx_size--) { + send_u8(status, data, 0); // Dummy write to push out read data. + if (rx_available(status)) { + if (dummy_count > 0) { + // Read data not arrived yet. + rcv_byte(data); + dummy_count--; + } else { + if (rcv_byte(data) != arg->pattern) { + filled = 0; + break; + } + rx_size--; + } + } + } + if (filled) { + for (; rx_size > 0; rx_size--) { + wait_rx_available(status); + if (rcv_byte(data) != arg->pattern) { + filled = 0; + break; + } + } + } + *fill_status_array = filled; + } + + RETURN; +} + +/** + * @brief Erase flash sectors. + * + * @param[in] arg: Function arguments. + */ +__attribute__((section(".erase"))) void +erase(struct dw_spi_erase *arg) +{ + register uint32_t address = arg->address; + register uint32_t count = arg->sector_count; + register volatile uint8_t *status = (uint8_t *)arg->status_reg; + register volatile uint8_t *data = (uint8_t *)arg->data_reg; + + for (; count > 0; count--, address += arg->sector_size) { + write_enable(status, data, arg->write_enable_cmd); + wait_write_enable(status, data, arg->read_status_cmd, + arg->write_enable_mask); + + erase_sector(status, data, arg->erase_sector_cmd, address, + arg->four_byte_mode); + wait_busy(status, data, arg->read_status_cmd, arg->busy_mask); + } + + RETURN; +} + +/** + * @brief Flash program. + * + * @param[in] arg: Function arguments. + */ +__attribute__((section(".program"))) void +program(struct dw_spi_program *arg) +{ + register uint8_t *buffer = (uint8_t *)arg->buffer; + register uint32_t buffer_size = arg->buffer_size; + register volatile uint8_t *status = (uint8_t *)arg->status_reg; + register volatile uint8_t *data = (uint8_t *)arg->data_reg; + register uint32_t page_size; + + while (buffer_size > 0) { + write_enable(status, data, arg->write_enable_cmd); + wait_write_enable(status, data, arg->read_status_cmd, + arg->write_enable_mask); + + wait_tx_finish(status); + + send_u8(status, data, arg->program_cmd); + if (arg->four_byte_mode) + send_u32(status, data, arg->address); + else + send_u24(status, data, arg->address); + + for (page_size = MIN(arg->page_size, buffer_size); page_size > 0; + page_size--, buffer_size--) { + send_u8(status, data, *buffer++); + } + arg->address += arg->page_size; + wait_busy(status, data, arg->read_status_cmd, arg->busy_mask); + } + + RETURN; +} + +/** + * @brief Read data from flash. + * + * @param[in] arg: Function arguments. + */ +__attribute__((section(".read"))) void +read(struct dw_spi_read *arg) +{ + register uint32_t tx_size = arg->buffer_size; + register uint32_t rx_size = arg->buffer_size; + register uint32_t dummy_count; + register uint8_t *buffer = (uint8_t *)arg->buffer; + register volatile uint8_t *status = (uint8_t *)arg->status_reg; + register volatile uint8_t *data = (uint8_t *)arg->data_reg; + + wait_tx_finish(status); + flush_rx(status, data); + + /* + * Command byte and address bytes make up for dummy_count number of + * bytes, that must be skipped in RX FIFO before actual data arrives. + */ + send_u8(status, data, arg->read_cmd); + if (arg->four_byte_mode) { + dummy_count = 1 + 4; // Command byte + 4 address bytes + send_u32(status, data, arg->address); + } else { + dummy_count = 1 + 3; // Command byte + 3 address bytes + send_u24(status, data, arg->address); + } + + for (; tx_size > 0; tx_size--) { + send_u8(status, data, 0); // Dummy write to push out read data. + if (rx_available(status)) { + if (dummy_count > 0) { + rcv_byte(data); + dummy_count--; + } else { + *buffer++ = rcv_byte(data); + rx_size--; + } + } + } + while (rx_size > 0) { + wait_rx_available(status); + if (dummy_count > 0) { + // Read data not arrived yet. + rcv_byte(data); + dummy_count--; + } else { + *buffer++ = rcv_byte(data); + rx_size--; + } + } + + RETURN; +} diff --git a/contrib/loaders/flash/dw-spi/dw-spi.h b/contrib/loaders/flash/dw-spi/dw-spi.h new file mode 100644 index 0000000000..9efa768e66 --- /dev/null +++ b/contrib/loaders/flash/dw-spi/dw-spi.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/** + * @file + * Helper functions for DesignWare SPI Core driver. + * These helpers are loaded into CPU and execute Flash manipulation algorithms + * at full CPU speed. Due to inability to control nCS pin, this is the only way + * to communicate with Flash chips connected via DW SPI serial interface. + * + * In order to avoid using stack, all functions used in helpers are inlined. + * Software breakpoints are used to terminate helpers. + * + * This file contains functions, common to helpers. + */ + +#ifndef _DW_SPI_H_ +#define _DW_SPI_H_ + +#include +#include + +#include "../../../../src/helper/types.h" + +/** + * @brief SI busy status bit. + * + * Set when serial transfer is in progress, cleared when master is idle or + * disabled. + */ +#define DW_SPI_STATUS_BUSY 0x01 + +/** + * @brief SI TX FIFO not full status bit. + * + * Set when TX FIFO has room for one or more data-word. + */ +#define DW_SPI_STATUS_TFNF 0x02 + +/** + * @brief SI TX FIFO empty status bit. + */ +#define DW_SPI_STATUS_TFE 0x04 + +/** + * @brief SI RX FIFO not empty status bit. + */ +#define DW_SPI_STATUS_RFNE 0x08 + +/** + * @brief Return from helper function. + */ +#define RETURN \ + do { \ + asm("sdbbp\n\t"); \ + return; \ + } while (0) + +/** + * @brief Append byte to TX FIFO. + * + * For each transferred byte, DW SPI controller receives a byte into RX FIFO. + * Slave data are read by pushing dummy bytes to TX FIFO. + * + * @param[in] dr: Pointer to DR register. + * @param[in] byte: Data to push. + */ +__attribute__((always_inline)) static inline void +_send_byte(volatile uint8_t *dr, uint8_t byte) +{ + *dr = byte; +} + +/** + * @brief Get byte from RX FIFO. + * + * Reading RX byte removes it from RX FIFO. + * + * @param[in] dr: Pointer to DR register. + * @return RX FIFO byte. + */ +__attribute__((always_inline)) static inline uint8_t +rcv_byte(volatile uint8_t *dr) +{ + return *dr; +} + +/** + * @brief Check transmission is currently in progress. + * + * @param[in] sr: Pointer to SR register. + * @retval 1: Transmission is in progress. + * @retval 0: Controller is idle or off. + */ +__attribute__((always_inline)) static inline int +tx_in_progress(volatile uint8_t *sr) +{ + return (*sr ^ DW_SPI_STATUS_TFE) & (DW_SPI_STATUS_BUSY | DW_SPI_STATUS_TFE); +} + +/** + * @brief Wait for controller to finish previous transaction. + * + * @param[in] sr: Pointer to SR register. + */ +__attribute__((always_inline)) static inline void +wait_tx_finish(volatile uint8_t *sr) +{ + while (tx_in_progress(sr)) + ; +} + +/** + * @brief Wait for room in TX FIFO. + * + * @param[in] sr: Pointer to SR register. + */ +__attribute__((always_inline)) static inline void +wait_tx_available(volatile uint8_t *sr) +{ + while (!(*sr & DW_SPI_STATUS_TFNF)) + ; +} + +/** + * @brief Check for data available in RX FIFO. + * + * @param[in] sr: Pointer to SR register. + * @retval 1: Data available. + * @retval 0: No data available. + */ +__attribute__((always_inline)) static inline int +rx_available(volatile uint8_t *sr) +{ + return *sr & DW_SPI_STATUS_RFNE; +} + +/** + * @brief Wait for data in RX FIFO. + * + * @param[in] sr: Pointer to SR register. + */ +__attribute__((always_inline)) static inline void +wait_rx_available(volatile uint8_t *sr) +{ + while (!rx_available(sr)) + ; +} + +/** + * @brief Flush RX FIFO. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + */ +__attribute__((always_inline)) static inline void +flush_rx(volatile uint8_t *sr, volatile uint8_t *dr) +{ + while (*sr & DW_SPI_STATUS_RFNE) + *dr; +} + +/** + * @brief Append variable number of bytes to TX FIFO. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] word: Data to append. + * @param[in] bytes: Number of bytes to append. + */ +__attribute__((always_inline)) static inline void +_send_bytes(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word, + int bytes) +{ + for (register int i = bytes - 1; i >= 0; i--) { + wait_tx_available(sr); + _send_byte(dr, (word >> (i * 8)) & 0xff); + } +} + +/** + * @brief Append 8 bit value to TX FIFO. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] word: Data to push. + */ +__attribute__((always_inline)) static inline void +send_u8(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t byte) +{ + wait_tx_available(sr); + _send_byte(dr, byte); +} + +/** + * @brief Append 24 bit value to TX FIFO. + * + * Used to send Flash addresses in 24 bit mode. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] word: Data to push. + */ +__attribute__((always_inline)) static inline void +send_u24(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word) +{ + _send_bytes(sr, dr, word, 3); +} + +/** + * @brief Append 32 bit value to TX FIFO. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] word: Data to push. + */ +__attribute__((always_inline)) static inline void +send_u32(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word) +{ + _send_bytes(sr, dr, word, 4); +} + +/** + * @brief Read chip status register. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] stat_cmd: Read status command. + * @return Chip status. + */ +__attribute__((always_inline)) static inline uint8_t +read_status(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd) +{ + wait_tx_finish(sr); + flush_rx(sr, dr); + /* + * Don't bother with wait_tx_available() as TX FIFO is empty + * and we only send two bytes. + */ + _send_byte(dr, stat_cmd); + _send_byte(dr, 0); // Dummy write to push out read data. + wait_rx_available(sr); + rcv_byte(dr); // Dummy read to skip command byte. + wait_rx_available(sr); + return rcv_byte(dr); +} + +/** + * @brief Enable Flash chip write. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] we_cmd: Write enable command. + */ +__attribute__((always_inline)) static inline void +write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t we_cmd) +{ + wait_tx_finish(sr); + _send_byte(dr, we_cmd); +} + +/** + * @brief Erase Flash sector. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] erase_cmd: Erase sector cmd. + * @param[in] address: Sector address. + * @param[in] four_byte_mode: Device is in 32 bit mode flag. + */ +__attribute__((always_inline)) static inline void +erase_sector(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t erase_cmd, + uint32_t address, uint8_t four_byte_mode) +{ + wait_tx_finish(sr); + _send_byte(dr, erase_cmd); + if (four_byte_mode) + send_u32(sr, dr, address); + else + send_u24(sr, dr, address); +} + +/** + * @brief Wait for write enable flag. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] stat_cmd: Read status command. + * @param[in] we_mask: Write enable status mask. + */ +__attribute__((always_inline)) static inline void +wait_write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd, + uint8_t we_mask) +{ + while (!(read_status(sr, dr, stat_cmd) & we_mask)) + ; +} + +/** + * @brief Wait while flash is busy. + * + * @param[in] sr: Pointer to SR register. + * @param[in] dr: Pointer to DR register. + * @param[in] stat_cmd: Read status command. + * @param[in] busy_mask: Flash busy mask. + */ +__attribute__((always_inline)) static inline void +wait_busy(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd, + uint8_t busy_mask) +{ + while (read_status(sr, dr, stat_cmd) & busy_mask) + ; +} + +#endif // _DW_SPI_H_ diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc new file mode 100644 index 0000000000..94c732fe5b --- /dev/null +++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc @@ -0,0 +1,39 @@ + 0x0b, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x8a, 0x88, 0x0f, 0x00, 0x83, 0x88, + 0x17, 0x00, 0x86, 0x88, 0x08, 0x00, 0x82, 0x98, 0x1c, 0x00, 0x8a, 0x98, + 0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x25, 0x38, 0x80, 0x00, + 0x54, 0x00, 0x40, 0x10, 0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x64, 0x90, + 0x05, 0x00, 0x84, 0x30, 0x04, 0x00, 0x84, 0x38, 0xfc, 0xff, 0x80, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, + 0x07, 0x00, 0x40, 0x50, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0xc2, 0x90, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90, + 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc5, 0xa0, 0x26, 0x00, 0xe2, 0x90, 0x45, 0x00, 0x40, 0x10, + 0x03, 0x00, 0xe8, 0x88, 0x00, 0x00, 0xe8, 0x98, 0x18, 0x00, 0x05, 0x24, + 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, + 0x06, 0x10, 0xa8, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24, + 0x00, 0x00, 0xc2, 0xa0, 0xf8, 0xff, 0xa9, 0x14, 0x05, 0x00, 0x0b, 0x24, + 0x07, 0x00, 0xe8, 0x88, 0x04, 0x00, 0xe8, 0x98, 0x1e, 0x00, 0x00, 0x11, + 0x25, 0x28, 0x00, 0x01, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, + 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa0, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50, + 0xff, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0x90, 0x25, 0x00, 0x60, 0x51, + 0x24, 0x00, 0xec, 0x90, 0xff, 0xff, 0x6b, 0x25, 0xff, 0xff, 0xa5, 0x24, + 0xf1, 0xff, 0xa0, 0x14, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x51, + 0x01, 0x00, 0x04, 0x24, 0x24, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90, + 0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc2, 0x90, 0xff, 0x00, 0x42, 0x30, 0x04, 0x00, 0xa2, 0x14, + 0xff, 0xff, 0x08, 0x25, 0xf7, 0xff, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x04, 0x24, 0x00, 0x00, 0x44, 0xa1, 0x0b, 0x00, 0xe2, 0x88, + 0x01, 0x00, 0x4a, 0x25, 0x08, 0x00, 0xe2, 0x98, 0xff, 0xff, 0x42, 0x24, + 0x0b, 0x00, 0xe2, 0xa8, 0x08, 0x00, 0xe2, 0xb8, 0x03, 0x00, 0xe4, 0x88, + 0x07, 0x00, 0xe5, 0x88, 0x00, 0x00, 0xe4, 0x98, 0x04, 0x00, 0xe5, 0x98, + 0x21, 0x20, 0x85, 0x00, 0x03, 0x00, 0xe4, 0xa8, 0xae, 0xff, 0x40, 0x14, + 0x00, 0x00, 0xe4, 0xb8, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03, + 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x42, 0x30, 0xed, 0xff, 0x82, 0x55, + 0x00, 0x00, 0x44, 0xa1, 0xd9, 0xff, 0x00, 0x10, 0xff, 0xff, 0x08, 0x25, + 0x00, 0x00, 0xe8, 0x98, 0x10, 0x00, 0x05, 0x24, 0x00, 0x00, 0x62, 0x90, + 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xa8, 0x00, + 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0xa0, + 0xf8, 0xff, 0xa9, 0x14, 0x04, 0x00, 0x0b, 0x24, 0xbc, 0xff, 0x00, 0x10, + 0x07, 0x00, 0xe8, 0x88 diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc new file mode 100644 index 0000000000..b72c7ea446 --- /dev/null +++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc @@ -0,0 +1,39 @@ + 0x0b, 0x00, 0x88, 0x88, 0x25, 0x28, 0x80, 0x00, 0x03, 0x00, 0x86, 0x88, + 0x0f, 0x00, 0x82, 0x88, 0x17, 0x00, 0x84, 0x88, 0x08, 0x00, 0xa8, 0x98, + 0x00, 0x00, 0xa6, 0x98, 0x0c, 0x00, 0xa2, 0x98, 0x5f, 0x00, 0x00, 0x11, + 0x14, 0x00, 0xa4, 0x98, 0xf8, 0xff, 0x07, 0x24, 0x1d, 0x00, 0xa9, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, + 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0, + 0x1c, 0x00, 0xaa, 0x90, 0x1f, 0x00, 0xa9, 0x90, 0x00, 0x00, 0x43, 0x90, + 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, + 0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0, + 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 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0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90, + 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, + 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, + 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x00, 0xa3, 0x88, 0xff, 0xff, 0x08, 0x25, 0x04, 0x00, 0xa3, 0x98, + 0xa4, 0xff, 0x00, 0x15, 0x21, 0x30, 0xc3, 0x00, 0x3f, 0x00, 0x00, 0x70, + 0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, + 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x26, 0x01, + 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0xf9, 0xff, 0x27, 0x15, + 0x00, 0x00, 0x83, 0xa0, 0xd1, 0xff, 0x00, 0x10, 0x1c, 0x00, 0xaa, 0x90 diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc new file mode 100644 index 0000000000..31500e01d8 --- /dev/null +++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc @@ -0,0 +1,51 @@ + 0x13, 0x00, 0x88, 0x88, 0x25, 0x30, 0x80, 0x00, 0x0b, 0x00, 0x85, 0x88, + 0x17, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x84, 0x88, 0x10, 0x00, 0xc8, 0x98, + 0x08, 0x00, 0xc5, 0x98, 0x14, 0x00, 0xc2, 0x98, 0x1c, 0x00, 0xc4, 0x98, + 0x78, 0x00, 0x00, 0x11, 0xf8, 0xff, 0x07, 0x24, 0x25, 0x00, 0xc9, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, + 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0, + 0x24, 0x00, 0xca, 0x90, 0x27, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90, + 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, + 0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0, + 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, + 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, + 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, + 0x26, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, + 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0, + 0x29, 0x00, 0xc3, 0x90, 0x47, 0x00, 0x60, 0x10, 0x03, 0x00, 0xca, 0x88, + 0x00, 0x00, 0xca, 0x98, 0x18, 0x00, 0x09, 0x24, 0x00, 0x00, 0x43, 0x90, + 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x2a, 0x01, + 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0x00, 0x00, 0x83, 0xa0, + 0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01, 0x07, 0x00, 0xc3, 0x88, + 0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01, 0x0a, 0x58, 0x69, 0x00, + 0x0d, 0x00, 0x60, 0x11, 0x21, 0x50, 0xab, 0x00, 0x00, 0x00, 0xa9, 0x90, + 0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, + 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0, + 0xf9, 0xff, 0xaa, 0x54, 0x00, 0x00, 0xa9, 0x90, 0x07, 0x00, 0xc3, 0x88, + 0x23, 0x40, 0x0b, 0x01, 0x04, 0x00, 0xc3, 0x98, 0x03, 0x00, 0xc9, 0x88, + 0x00, 0x00, 0xc9, 0x98, 0x21, 0x18, 0x23, 0x01, 0x03, 0x00, 0xc3, 0xa8, + 0x00, 0x00, 0xc3, 0xb8, 0x24, 0x00, 0xca, 0x90, 0x28, 0x00, 0xc9, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, + 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, + 0x08, 0x00, 0x63, 0x30, 0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, + 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, + 0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, + 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, + 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, + 0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x8b, 0xff, 0x00, 0x55, + 0x25, 0x00, 0xc9, 0x90, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x98, 0x10, 0x00, 0x09, 0x24, + 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, + 0x06, 0x18, 0x2a, 0x01, 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, + 0x00, 0x00, 0x83, 0xa0, 0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01, + 0x07, 0x00, 0xc3, 0x88, 0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01, + 0x0a, 0x58, 0x69, 0x00, 0xbb, 0xff, 0x60, 0x15, 0x21, 0x50, 0xab, 0x00, + 0xc6, 0xff, 0x00, 0x10, 0x03, 0x00, 0xc9, 0x88 diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc new file mode 100644 index 0000000000..3f18b7c2e8 --- /dev/null +++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc @@ -0,0 +1,33 @@ + 0x0f, 0x00, 0x87, 0x88, 0x07, 0x00, 0x88, 0x88, 0x13, 0x00, 0x83, 0x88, + 0x1b, 0x00, 0x85, 0x88, 0x0c, 0x00, 0x87, 0x98, 0x04, 0x00, 0x88, 0x98, + 0x10, 0x00, 0x83, 0x98, 0x18, 0x00, 0x85, 0x98, 0x00, 0x00, 0x62, 0x90, + 0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, + 0x07, 0x00, 0x40, 0x50, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0xa2, 0x90, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0x62, 0x90, + 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xa6, 0xa0, 0x21, 0x00, 0x82, 0x90, 0x35, 0x00, 0x40, 0x10, + 0x03, 0x00, 0x82, 0x88, 0x18, 0x00, 0x06, 0x24, 0xf8, 0xff, 0x09, 0x24, + 0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00, 0x00, 0x00, 0x62, 0x90, + 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xc4, 0x00, + 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24, 0xf9, 0xff, 0xc9, 0x14, + 0x00, 0x00, 0xa2, 0xa0, 0x05, 0x00, 0x06, 0x24, 0x23, 0x00, 0xe0, 0x10, + 0x25, 0x20, 0xe0, 0x00, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, + 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xa0, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50, + 0xff, 0xff, 0x84, 0x24, 0x00, 0x00, 0xa2, 0x90, 0x14, 0x00, 0xc0, 0x50, + 0x00, 0x00, 0x02, 0xa1, 0xff, 0xff, 0xc6, 0x24, 0xff, 0xff, 0x84, 0x24, + 0xf1, 0xff, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0xe0, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, + 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa2, 0x90, + 0x03, 0x00, 0xc0, 0x50, 0xff, 0xff, 0xe7, 0x24, 0xf8, 0xff, 0x00, 0x10, + 0xff, 0xff, 0xc6, 0x24, 0x06, 0x00, 0xe0, 0x10, 0x00, 0x00, 0x02, 0xa1, + 0xf4, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0xff, 0xff, 0xe7, 0x24, + 0xec, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0x3f, 0x00, 0x00, 0x70, + 0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x06, 0x24, + 0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00, + 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, + 0x06, 0x10, 0xc4, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24, + 0xf9, 0xff, 0xc9, 0x14, 0x00, 0x00, 0xa2, 0xa0, 0xcc, 0xff, 0x00, 0x10, + 0x04, 0x00, 0x06, 0x24 diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc new file mode 100644 index 0000000000..384dbadb15 --- /dev/null +++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc @@ -0,0 +1,21 @@ + 0x03, 0x00, 0x85, 0x88, 0x0b, 0x00, 0x88, 0x88, 0x0f, 0x00, 0x83, 0x88, + 0x17, 0x00, 0x86, 0x88, 0x00, 0x00, 0x85, 0x98, 0x08, 0x00, 0x88, 0x98, + 0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x00, 0x00, 0x62, 0x90, + 0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, + 0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, + 0x25, 0x38, 0xa0, 0x00, 0x21, 0x40, 0x05, 0x01, 0x00, 0x00, 0xa9, 0x90, + 0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, + 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0xa0, + 0x1c, 0x00, 0x82, 0x90, 0x08, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x04, 0x00, 0x40, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24, + 0xff, 0xff, 0xe2, 0xa0, 0xef, 0xff, 0xa8, 0x54, 0x00, 0x00, 0xa9, 0x90, + 0x1c, 0x00, 0x82, 0x90, 0x0c, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x2b, 0x10, 0xe8, 0x00, 0x09, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24, + 0xf9, 0xff, 0x07, 0x15, 0xff, 0xff, 0xe2, 0xa0, 0x3f, 0x00, 0x00, 0x70, + 0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00 diff --git a/contrib/loaders/flash/efm32.S b/contrib/loaders/flash/efm32.S index c5de55c27a..b6938512a9 100644 --- a/contrib/loaders/flash/efm32.S +++ b/contrib/loaders/flash/efm32.S @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2011 by Andreas Fritiofson * * andreas.fritiofson@gmail.com * * Copyright (C) 2013 by Roman Dmitrienko * * me@iamroman.org * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/fespi/Makefile b/contrib/loaders/flash/fespi/Makefile index edecf0a729..d63b819f62 100644 --- a/contrib/loaders/flash/fespi/Makefile +++ b/contrib/loaders/flash/fespi/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= riscv64-unknown-elf- diff --git a/contrib/loaders/flash/fespi/riscv.lds b/contrib/loaders/flash/fespi/riscv.lds index 77fe0e5582..7473128bf7 100644 --- a/contrib/loaders/flash/fespi/riscv.lds +++ b/contrib/loaders/flash/fespi/riscv.lds @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + OUTPUT_ARCH( "riscv" ) SECTIONS diff --git a/contrib/loaders/flash/fespi/riscv_fespi.c b/contrib/loaders/flash/fespi/riscv_fespi.c index b6164330d3..08fb09477f 100644 --- a/contrib/loaders/flash/fespi/riscv_fespi.c +++ b/contrib/loaders/flash/fespi/riscv_fespi.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + #include #include #include @@ -101,7 +103,7 @@ static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base); static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base); static int fespi_wip(volatile uint32_t *ctrl_base); static int fespi_write_buffer(volatile uint32_t *ctrl_base, - const uint8_t *buffer, unsigned offset, unsigned len, + const uint8_t *buffer, unsigned int offset, unsigned int len, uint32_t flash_info); /* Can set bits 3:0 in result. */ @@ -111,7 +113,7 @@ static int fespi_write_buffer(volatile uint32_t *ctrl_base, * after pprog_cmd */ int flash_fespi(volatile uint32_t *ctrl_base, uint32_t page_size, - const uint8_t *buffer, unsigned offset, uint32_t count, + const uint8_t *buffer, unsigned int offset, uint32_t count, uint32_t flash_info) { int result; @@ -161,12 +163,12 @@ int flash_fespi(volatile uint32_t *ctrl_base, uint32_t page_size, return result; } -static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned address) +static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned int address) { return ctrl_base[address / 4]; } -static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned address, uint32_t value) +static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned int address, uint32_t value) { ctrl_base[address / 4] = value; } @@ -186,7 +188,7 @@ static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base) /* Can set bits 7:4 in result. */ static int fespi_txwm_wait(volatile uint32_t *ctrl_base) { - unsigned timeout = TIMEOUT; + unsigned int timeout = TIMEOUT; while (timeout--) { uint32_t ip = fespi_read_reg(ctrl_base, FESPI_REG_IP); @@ -207,7 +209,7 @@ static void fespi_set_dir(volatile uint32_t *ctrl_base, bool dir) /* Can set bits 11:8 in result. */ static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in) { - unsigned timeout = TIMEOUT; + unsigned int timeout = TIMEOUT; while (timeout--) { uint32_t txfifo = fespi_read_reg(ctrl_base, FESPI_REG_TXFIFO); @@ -222,7 +224,7 @@ static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in) /* Can set bits 15:12 in result. */ static int fespi_rx(volatile uint32_t *ctrl_base, uint8_t *out) { - unsigned timeout = TIMEOUT; + unsigned int timeout = TIMEOUT; while (timeout--) { uint32_t value = fespi_read_reg(ctrl_base, FESPI_REG_RXFIFO); @@ -250,7 +252,7 @@ static int fespi_wip(volatile uint32_t *ctrl_base) if (result != ERROR_OK) return result | ERROR_STACK(0x20000); - unsigned timeout = TIMEOUT; + unsigned int timeout = TIMEOUT; while (timeout--) { result = fespi_tx(ctrl_base, 0); if (result != ERROR_OK) @@ -271,7 +273,7 @@ static int fespi_wip(volatile uint32_t *ctrl_base) /* Can set bits 23:20 in result. */ static int fespi_write_buffer(volatile uint32_t *ctrl_base, - const uint8_t *buffer, unsigned offset, unsigned len, + const uint8_t *buffer, unsigned int offset, unsigned int len, uint32_t flash_info) { int result = fespi_tx(ctrl_base, SPIFLASH_WRITE_ENABLE); @@ -302,7 +304,7 @@ static int fespi_write_buffer(volatile uint32_t *ctrl_base, if (result != ERROR_OK) return result | ERROR_STACK(0x600000); - for (unsigned i = 0; i < len; i++) { + for (unsigned int i = 0; i < len; i++) { result = fespi_tx(ctrl_base, buffer[i]); if (result != ERROR_OK) return result | ERROR_STACK(0x700000); diff --git a/contrib/loaders/flash/fespi/riscv_wrapper.S b/contrib/loaders/flash/fespi/riscv_wrapper.S index 4f632a76ec..4bc4fe6dd9 100644 --- a/contrib/loaders/flash/fespi/riscv_wrapper.S +++ b/contrib/loaders/flash/fespi/riscv_wrapper.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #if __riscv_xlen == 64 # define LREG ld # define SREG sd diff --git a/contrib/loaders/flash/fm4/Makefile b/contrib/loaders/flash/fm4/Makefile index 207b9d0fa4..5e6593b46e 100644 --- a/contrib/loaders/flash/fm4/Makefile +++ b/contrib/loaders/flash/fm4/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/fm4/erase.S b/contrib/loaders/flash/fm4/erase.S index 6fdf81dc2a..666487d88c 100644 --- a/contrib/loaders/flash/fm4/erase.S +++ b/contrib/loaders/flash/fm4/erase.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Spansion FM4 flash sector erase algorithm * diff --git a/contrib/loaders/flash/fm4/fm4.h b/contrib/loaders/flash/fm4/fm4.h index 603aac8762..76a4f3321b 100644 --- a/contrib/loaders/flash/fm4/fm4.h +++ b/contrib/loaders/flash/fm4/fm4.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Spansion FM4 flash macros * diff --git a/contrib/loaders/flash/fm4/write.S b/contrib/loaders/flash/fm4/write.S index a8d01cde24..0819da7c3c 100644 --- a/contrib/loaders/flash/fm4/write.S +++ b/contrib/loaders/flash/fm4/write.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Spansion FM4 flash write algorithm * diff --git a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py index 4246aa2f3a..408cfdd79f 100755 --- a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py +++ b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py @@ -1,17 +1,7 @@ #!/usr/bin/python3 -# +# SPDX-License-Identifier: GPL-2.0-or-later + # Copyright (C) 2015 Robert Jordens -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# import unittest diff --git a/contrib/loaders/flash/gd32vf103/Makefile b/contrib/loaders/flash/gd32vf103/Makefile index 2c34e08c08..812fd8acaf 100644 --- a/contrib/loaders/flash/gd32vf103/Makefile +++ b/contrib/loaders/flash/gd32vf103/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= riscv-none-embed- diff --git a/contrib/loaders/flash/gd32vf103/gd32vf103.c b/contrib/loaders/flash/gd32vf103/gd32vf103.c index 69225a0267..927014c740 100644 --- a/contrib/loaders/flash/gd32vf103/gd32vf103.c +++ b/contrib/loaders/flash/gd32vf103/gd32vf103.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #include diff --git a/contrib/loaders/flash/k1921vk01t.S b/contrib/loaders/flash/k1921vk01t.S index b8f0b53d5e..d8e3cd6fa3 100644 --- a/contrib/loaders/flash/k1921vk01t.S +++ b/contrib/loaders/flash/k1921vk01t.S @@ -1,20 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2015 by Bogdan Kolbov * * kolbov@niiet.ru * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/kinetis/Makefile b/contrib/loaders/flash/kinetis/Makefile index b240f53d44..d6c072bb4f 100644 --- a/contrib/loaders/flash/kinetis/Makefile +++ b/contrib/loaders/flash/kinetis/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/kinetis/kinetis_flash.s b/contrib/loaders/flash/kinetis/kinetis_flash.s index c8e6e05a89..5b9d3c69c9 100644 --- a/contrib/loaders/flash/kinetis/kinetis_flash.s +++ b/contrib/loaders/flash/kinetis/kinetis_flash.s @@ -1,19 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2015 by Ivan Meleca * * ivan@artekit.eu * * * * Copyright (C) 2016 by Tomas Vanek * * vanekt@fbl.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * ***************************************************************************/ /* Params: diff --git a/contrib/loaders/flash/kinetis_ke/Makefile b/contrib/loaders/flash/kinetis_ke/Makefile index 7d8dba8c73..17cbf3298b 100644 --- a/contrib/loaders/flash/kinetis_ke/Makefile +++ b/contrib/loaders/flash/kinetis_ke/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s b/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s index 1fa761336a..f082b46496 100644 --- a/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s +++ b/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2015 by Ivan Meleca * * ivan@artekit.eu * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * ***************************************************************************/ /* Params: diff --git a/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s b/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s index 289662d075..e0ff0b1f17 100644 --- a/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s +++ b/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2015 by Ivan Meleca * * ivan@artekit.eu * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/lpcspifi_erase.S b/contrib/loaders/flash/lpcspifi_erase.S index 350aa93cb8..70cdcfa28b 100644 --- a/contrib/loaders/flash/lpcspifi_erase.S +++ b/contrib/loaders/flash/lpcspifi_erase.S @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2012 by George Harris * * george@luminairecoffee.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/lpcspifi_init.S b/contrib/loaders/flash/lpcspifi_init.S index 9872892f5b..651298acef 100644 --- a/contrib/loaders/flash/lpcspifi_init.S +++ b/contrib/loaders/flash/lpcspifi_init.S @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2012 by George Harris * * george@luminairecoffee.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /*************************************************************************** diff --git a/contrib/loaders/flash/lpcspifi_write.S b/contrib/loaders/flash/lpcspifi_write.S index 8435a20453..476e143aa4 100644 --- a/contrib/loaders/flash/lpcspifi_write.S +++ b/contrib/loaders/flash/lpcspifi_write.S @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2012 by George Harris * * george@luminairecoffee.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/max32xxx/Makefile b/contrib/loaders/flash/max32xxx/Makefile index 8f3f9242e4..1565c811c1 100644 --- a/contrib/loaders/flash/max32xxx/Makefile +++ b/contrib/loaders/flash/max32xxx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/max32xxx/max32xxx.s b/contrib/loaders/flash/max32xxx/max32xxx.s index f5306d6c5d..38a4f12c32 100644 --- a/contrib/loaders/flash/max32xxx/max32xxx.s +++ b/contrib/loaders/flash/max32xxx/max32xxx.s @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2016 by Maxim Integrated * * Kevin Gillespie . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/mdr32fx.S b/contrib/loaders/flash/mdr32fx.S index 73f4b6fde6..3a25d2029b 100644 --- a/contrib/loaders/flash/mdr32fx.S +++ b/contrib/loaders/flash/mdr32fx.S @@ -1,24 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2011 by Andreas Fritiofson * * andreas.fritiofson@gmail.com * * * * Copyright (C) 2013 by Paul Fertser * * fercerpav@gmail.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/mrvlqspi_write.S b/contrib/loaders/flash/mrvlqspi_write.S index e1088e38da..5865da007b 100644 --- a/contrib/loaders/flash/mrvlqspi_write.S +++ b/contrib/loaders/flash/mrvlqspi_write.S @@ -1,24 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2014 by Mahavir Jain * * * * Adapted from (contrib/loaders/flash/lpcspifi_write.S): * * Copyright (C) 2012 by George Harris * * george@luminairecoffee.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h index d406d6003d..aad39896b1 100644 --- a/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h +++ b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H diff --git a/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h index c438097efc..b9334816dc 100644 --- a/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h +++ b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H diff --git a/contrib/loaders/flash/msp432/Makefile b/contrib/loaders/flash/msp432/Makefile index 608333140a..cb1092c66b 100644 --- a/contrib/loaders/flash/msp432/Makefile +++ b/contrib/loaders/flash/msp432/Makefile @@ -1,3 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/msp432/driverlib.c b/contrib/loaders/flash/msp432/driverlib.c index ac6dfd4541..6f483b83da 100644 --- a/contrib/loaders/flash/msp432/driverlib.c +++ b/contrib/loaders/flash/msp432/driverlib.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/msp432/driverlib.h b/contrib/loaders/flash/msp432/driverlib.h index 23ba7b520a..1a087373f3 100644 --- a/contrib/loaders/flash/msp432/driverlib.h +++ b/contrib/loaders/flash/msp432/driverlib.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H diff --git a/contrib/loaders/flash/msp432/main_msp432e4x.c b/contrib/loaders/flash/msp432/main_msp432e4x.c index 23540ac606..7974f48c77 100644 --- a/contrib/loaders/flash/msp432/main_msp432e4x.c +++ b/contrib/loaders/flash/msp432/main_msp432e4x.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/msp432/main_msp432p401x.c b/contrib/loaders/flash/msp432/main_msp432p401x.c index 7992f11686..47fb7fa476 100644 --- a/contrib/loaders/flash/msp432/main_msp432p401x.c +++ b/contrib/loaders/flash/msp432/main_msp432p401x.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/msp432/main_msp432p411x.c b/contrib/loaders/flash/msp432/main_msp432p411x.c index be1f709760..efc05a3b78 100644 --- a/contrib/loaders/flash/msp432/main_msp432p411x.c +++ b/contrib/loaders/flash/msp432/main_msp432p411x.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/msp432/msp432e4x.h b/contrib/loaders/flash/msp432/msp432e4x.h index 2a9d15511e..c0bc7b4fc3 100644 --- a/contrib/loaders/flash/msp432/msp432e4x.h +++ b/contrib/loaders/flash/msp432/msp432e4x.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H diff --git a/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds index af97458e63..2782209707 100644 --- a/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds +++ b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ MEMORY { diff --git a/contrib/loaders/flash/msp432/msp432p401x.h b/contrib/loaders/flash/msp432/msp432p401x.h index ca219fdd66..b8ccea8d9a 100644 --- a/contrib/loaders/flash/msp432/msp432p401x.h +++ b/contrib/loaders/flash/msp432/msp432p401x.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H diff --git a/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds index f9d04ed885..178eaf403f 100644 --- a/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds +++ b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ MEMORY { diff --git a/contrib/loaders/flash/msp432/msp432p411x.h b/contrib/loaders/flash/msp432/msp432p411x.h index 6482dd3331..3225fa45f2 100644 --- a/contrib/loaders/flash/msp432/msp432p411x.h +++ b/contrib/loaders/flash/msp432/msp432p411x.h @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H diff --git a/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds index 0e7aa2dee5..cec3c53f48 100644 --- a/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds +++ b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds @@ -1,35 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /****************************************************************************** * * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ MEMORY { diff --git a/contrib/loaders/flash/msp432/startup_msp432e4.c b/contrib/loaders/flash/msp432/startup_msp432e4.c index 494da46e7d..49789609fc 100644 --- a/contrib/loaders/flash/msp432/startup_msp432e4.c +++ b/contrib/loaders/flash/msp432/startup_msp432e4.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/msp432/startup_msp432p4.c b/contrib/loaders/flash/msp432/startup_msp432p4.c index 09103b0e43..350fd35e8a 100644 --- a/contrib/loaders/flash/msp432/startup_msp432p4.c +++ b/contrib/loaders/flash/msp432/startup_msp432p4.c @@ -1,35 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause + /****************************************************************************** * * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ * -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* ******************************************************************************/ #include diff --git a/contrib/loaders/flash/npcx/npcx_algo.inc b/contrib/loaders/flash/npcx/npcx_algo.inc index 4312fdb1b4..46b79d8d9c 100644 --- a/contrib/loaders/flash/npcx/npcx_algo.inc +++ b/contrib/loaders/flash/npcx/npcx_algo.inc @@ -1,60 +1,70 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ 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+/* flashloader parameter structure */ +__attribute__ ((section(".buffers.g_cfg"))) +static volatile struct npcx_flash_params g_cfg; +/* data buffer */ +__attribute__ ((section(".buffers.g_buf"))) +static uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE]; + /*---------------------------------------------------------------------------- * NPCX flash driver *----------------------------------------------------------------------------*/ +static void flash_init(void) +{ + if (g_cfg.fiu_ver == NPCX_FIU_NPCK) { + /* Set pinmux to SHD flash */ + NPCX_DEVCNT = 0x80; + NPCX_DEVALT(0) = 0xC0; + NPCX_DEVALT(4) = 0x00; + } else { + /* Avoid F_CS0 toggles while programming the internal flash. */ + NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); + } +} + static void flash_execute_cmd(uint8_t code, uint8_t cts) { /* Set UMA code */ @@ -26,11 +46,26 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts) static void flash_cs_level(uint8_t level) { + int sw_cs = 0; + + if (g_cfg.fiu_ver == NPCX_FIU_NPCX) { + sw_cs = 1; + } else if (g_cfg.fiu_ver == NPCX_FIU_NPCX_V2) { + sw_cs = 0; + } else if (g_cfg.fiu_ver == NPCX_FIU_NPCK) { + sw_cs = 1; + /* Unlock UMA before pulling down CS in NPCK series */ + if (level) + NPCX_CLEAR_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK); + else + NPCX_SET_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK); + } + /* Program chip select pin to high/low level */ if (level) - NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); + NPCX_SET_BIT(NPCX_UMA_ECTS, sw_cs); else - NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); + NPCX_CLEAR_BIT(NPCX_UMA_ECTS, sw_cs); } static void flash_set_address(uint32_t dest_addr) @@ -38,15 +73,15 @@ static void flash_set_address(uint32_t dest_addr) uint8_t *addr = (uint8_t *)&dest_addr; /* Set target flash address */ - NPCX_UMA_AB2 = addr[2]; - NPCX_UMA_AB1 = addr[1]; - NPCX_UMA_AB0 = addr[0]; + NPCX_UMA_DB0 = addr[2]; + NPCX_UMA_DB1 = addr[1]; + NPCX_UMA_DB2 = addr[0]; } -void delay(uint32_t i) +static void delay(uint32_t i) { while (i--) - ; + __asm__ volatile ("nop"); } static int flash_wait_ready(uint32_t timeout) @@ -104,7 +139,7 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes, /* Set write address */ flash_set_address(dest_addr); /* Start programming */ - flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR); + flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_3BYTE); for (uint32_t i = 0; i < bytes; i++) { flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY); data++; @@ -114,6 +149,15 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes, flash_cs_level(1); } +static void flash_get_stsreg(uint8_t *reg1, uint8_t *reg2) +{ + /* Read status register 1/2 for checking */ + flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE); + *reg1 = NPCX_UMA_DB0; + flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE); + *reg2 = NPCX_UMA_DB0; +} + /* The data to write cannot cross 256 Bytes boundary */ static int flash_program_write(uint32_t addr, uint32_t size, const uint8_t *data) @@ -126,7 +170,41 @@ static int flash_program_write(uint32_t addr, uint32_t size, return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); } -int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) +static int flash_physical_clear_stsreg(void) +{ + int status; + uint8_t reg1, reg2; + + /* Read status register 1/2 for checking */ + flash_get_stsreg(®1, ®2); + if (reg1 == 0x00 && reg2 == 0x00) + return NPCX_FLASH_STATUS_OK; + + /* Enable write */ + status = flash_write_enable(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + NPCX_UMA_DB0 = 0x0; + NPCX_UMA_DB1 = 0x0; + + /* Write status register 1/2 */ + flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE); + + /* Wait writing completed */ + status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + /* Read status register 1/2 for checking */ + flash_get_stsreg(®1, ®2); + if (reg1 != 0x00 || reg2 != 0x00) + return NPCX_FLASH_STATUS_FAILED; + + return NPCX_FLASH_STATUS_OK; +} + +static int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) { int status; uint32_t trunk_start = (offset + 0xff) & ~0xff; @@ -135,6 +213,13 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) uint32_t dest_addr = offset; uint32_t write_len = ((trunk_start - offset) > size) ? size : (trunk_start - offset); + /* Configure fiu and clear status registers if needed */ + flash_init(); + status = flash_physical_clear_stsreg(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + if (write_len) { status = flash_program_write(dest_addr, write_len, data); if (status != NPCX_FLASH_STATUS_OK) @@ -162,8 +247,16 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) return NPCX_FLASH_STATUS_OK; } -int flash_physical_erase(uint32_t offset, uint32_t size) +static int flash_physical_erase(uint32_t offset, uint32_t size) { + /* Configure fiu */ + flash_init(); + + /* clear flash status registers */ + int status = flash_physical_clear_stsreg(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE, offset += NPCX_FLASH_ERASE_SIZE) { @@ -175,7 +268,7 @@ int flash_physical_erase(uint32_t offset, uint32_t size) /* Set erase address */ flash_set_address(offset); /* Start erase */ - flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR); + flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_WR_3BYTE); /* Wait erase completed */ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); if (status != NPCX_FLASH_STATUS_OK) @@ -185,55 +278,36 @@ int flash_physical_erase(uint32_t offset, uint32_t size) return NPCX_FLASH_STATUS_OK; } -int flash_physical_erase_all(void) +static int flash_physical_erase_all(void) { - /* Enable write */ - int status = flash_write_enable(); - if (status != NPCX_FLASH_STATUS_OK) - return status; - - /* Start erase */ - flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY); + int status; - /* Wait erase completed */ - status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); + /* Configure fiu and clear status register if needed */ + flash_init(); + status = flash_physical_clear_stsreg(); if (status != NPCX_FLASH_STATUS_OK) return status; - return NPCX_FLASH_STATUS_OK; -} - -int flash_physical_clear_stsreg(void) -{ /* Enable write */ - int status = flash_write_enable(); + status = flash_write_enable(); if (status != NPCX_FLASH_STATUS_OK) return status; - NPCX_UMA_DB0 = 0x0; - NPCX_UMA_DB1 = 0x0; - - /* Write status register 1/2 */ - flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE); + /* Start erase */ + flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY); - /* Wait writing completed */ + /* Wait erase completed */ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); if (status != NPCX_FLASH_STATUS_OK) return status; - /* Read status register 1/2 for checking */ - flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return NPCX_FLASH_STATUS_FAILED; - flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return NPCX_FLASH_STATUS_FAILED; - return NPCX_FLASH_STATUS_OK; } -int flash_get_id(uint32_t *id) +static int flash_get_id(uint32_t *id) { + flash_init(); + flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE); *id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2; @@ -243,7 +317,7 @@ int flash_get_id(uint32_t *id) /*---------------------------------------------------------------------------- * flash loader function *----------------------------------------------------------------------------*/ -uint32_t flashloader_init(struct npcx_flash_params *params) +static uint32_t flashloader_init(struct npcx_flash_params *params) { /* Initialize params buffers */ memset(params, 0, sizeof(struct npcx_flash_params)); @@ -254,30 +328,13 @@ uint32_t flashloader_init(struct npcx_flash_params *params) /*---------------------------------------------------------------------------- * Functions *----------------------------------------------------------------------------*/ -/* flashloader parameter structure */ -__attribute__ ((section(".buffers.g_cfg"))) -volatile struct npcx_flash_params g_cfg; -/* data buffer */ -__attribute__ ((section(".buffers.g_buf"))) -uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE]; - -int main(void) +static int main(void) { - uint32_t id; + uint32_t id, status; /* set buffer */ flashloader_init((struct npcx_flash_params *)&g_cfg); - /* Avoid F_CS0 toggles while programming the internal flash. */ - NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); - - /* clear flash status registers */ - int status = flash_physical_clear_stsreg(); - if (status != NPCX_FLASH_STATUS_OK) { - while (1) - g_cfg.sync = status; - } - while (1) { /* wait command*/ while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT) diff --git a/contrib/loaders/flash/npcx/npcx_flash.h b/contrib/loaders/flash/npcx/npcx_flash.h index cc4f1ad506..48e5d82fd3 100644 --- a/contrib/loaders/flash/npcx/npcx_flash.h +++ b/contrib/loaders/flash/npcx/npcx_flash.h @@ -80,6 +80,7 @@ #define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032) #define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033) #define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034) +#define NPCX_FIU_MSR_IE_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x043) /* FIU register fields */ #define NPCX_RESP_CFG_IAD_EN 0 @@ -93,6 +94,7 @@ #define NPCX_UMA_ECTS_SW_CS1 1 #define NPCX_UMA_ECTS_SEC_CS 2 #define NPCX_UMA_ECTS_UMA_LOCK 3 +#define NPCX_FIU_MSR_IE_CFG_UMA_BLOCK 3 /* Flash UMA commands for npcx internal SPI flash */ #define NPCX_CMD_READ_ID 0x9F @@ -130,7 +132,6 @@ #define NPCX_SPI_FLASH_SR1_BUSY (1 << 0) #define NPCX_MASK_CMD_ONLY (0xC0) -#define NPCX_MASK_CMD_ADR (0xC0 | 0x08) #define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01) #define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01) #define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02) @@ -143,10 +144,12 @@ #define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20) #define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01) #define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02) -#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08) +#define NPCX_MASK_CMD_WR_3BYTE (0xC0 | 0x20 | 0x10 | 0x03) +#define NPCX_MASK_CMD_WR_4BYTE (0xC0 | 0x20 | 0x10 | 0x04) /* Flash loader parameters */ struct __attribute__((__packed__)) npcx_flash_params { + uint32_t fiu_ver; /* Flash controller unit version */ uint32_t addr; /* Address in flash */ uint32_t len; /* Number of bytes */ uint32_t cmd; /* Command */ @@ -176,4 +179,10 @@ enum npcx_flash_status { NPCX_FLASH_STATUS_FAILED_TIMEOUT, }; +enum npcx_fiu_ver { + NPCX_FIU_NPCX = 0, + NPCX_FIU_NPCX_V2, + NPCX_FIU_NPCK, +}; + #endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */ diff --git a/contrib/loaders/flash/npcx/npcx_flash_config.h b/contrib/loaders/flash/npcx/npcx_flash_config.h index 9ec1c5e331..4abd23e348 100644 --- a/contrib/loaders/flash/npcx/npcx_flash_config.h +++ b/contrib/loaders/flash/npcx/npcx_flash_config.h @@ -18,7 +18,7 @@ /* NPCX flash loader information */ #define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000 #define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR -#define NPCX_FLASH_LOADER_PARAMS_SIZE 16 +#define NPCX_FLASH_LOADER_PARAMS_SIZE 20 #define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR + NPCX_FLASH_LOADER_PARAMS_SIZE) #define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE #define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR + NPCX_FLASH_LOADER_BUFFER_SIZE) diff --git a/contrib/loaders/flash/nrf5/Makefile b/contrib/loaders/flash/nrf5/Makefile index 67390b9bdb..254ccd7da6 100644 --- a/contrib/loaders/flash/nrf5/Makefile +++ b/contrib/loaders/flash/nrf5/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/nrf5/nrf5.S b/contrib/loaders/flash/nrf5/nrf5.S index 12b1d92b5a..4115b0311e 100644 --- a/contrib/loaders/flash/nrf5/nrf5.S +++ b/contrib/loaders/flash/nrf5/nrf5.S @@ -1,20 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2014 Angus Gratton * * gus@projectgus.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/numicro/Makefile b/contrib/loaders/flash/numicro/Makefile new file mode 100644 index 0000000000..e4f44417c1 --- /dev/null +++ b/contrib/loaders/flash/numicro/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- + +CC=$(CROSS_COMPILE)gcc +OBJCOPY=$(CROSS_COMPILE)objcopy +OBJDUMP=$(CROSS_COMPILE)objdump + + +AFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL + +all: numicro_m0.inc numicro_m4.inc + +.PHONY: clean + +%.elf: %.S + $(CC) $(AFLAGS) $< -o $@ + +%.lst: %.elf + $(OBJDUMP) -S $< > $@ + +%.bin: %.elf + $(OBJCOPY) -Obinary $< $@ + +%.inc: %.bin + $(BIN2C) < $< > $@ + +clean: + -rm -f *.elf *.lst *.bin *.inc diff --git a/contrib/loaders/flash/numicro/numicro_m0.S b/contrib/loaders/flash/numicro/numicro_m0.S new file mode 100644 index 0000000000..37d4355324 --- /dev/null +++ b/contrib/loaders/flash/numicro/numicro_m0.S @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2015 Nemui Trinomius * + * nemuisan_kawausogasuki@live.jp * + * * + * Copyright (C) 2017 Zale Yu * + * CYYU@nuvoton.com * + * * + * Copyright (C) 2022 Jian-Hong Pan * + * chienhung.pan@gmail.com * + ***************************************************************************/ + + .text + .cpu cortex-m0 + .thumb + + /* Params: + * r0 - workarea buffer / result + * r1 - target address + * r2 - wordcount + * Clobbered: + * r4 - tmp + * r5 - tmp + * r6 - tmp + * r7 - tmp + */ + +.L1: + /* for(register uint32_t i=0;i $@ + +%.bin: %.elf + $(OBJCOPY) -Obinary $< $@ + +%.inc: %.bin + $(BIN2C) < $< > $@ + +clean: + -rm -f *.elf *.lst *.bin *.inc diff --git a/contrib/loaders/flash/rsl10/rom_launcher.S b/contrib/loaders/flash/rsl10/rom_launcher.S new file mode 100644 index 0000000000..aafedfb462 --- /dev/null +++ b/contrib/loaders/flash/rsl10/rom_launcher.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Toms StÅ«rmanis * + * toms.sturmanis@gmail.com * + ***************************************************************************/ + + .text + .syntax unified + .cpu cortex-m4 + .thumb + .align 8 + +/* + * Params : + * r0-r2 = arguments + * r3 = target address in rom + */ + + .thumb_func + .global _start +_start: +launch_program_in_rom: + // variables are already set, address to jump is in r3 + blx r3 +exit: + // Wait for OpenOCD + bkpt #0x00 diff --git a/contrib/loaders/flash/rsl10/rom_launcher.inc b/contrib/loaders/flash/rsl10/rom_launcher.inc new file mode 100644 index 0000000000..795c8e0d92 --- /dev/null +++ b/contrib/loaders/flash/rsl10/rom_launcher.inc @@ -0,0 +1,2 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x98,0x47,0x00,0xbe, diff --git a/contrib/loaders/flash/sh_qspi/Makefile b/contrib/loaders/flash/sh_qspi/Makefile index 2bfbad1b00..a7e0aea4ec 100644 --- a/contrib/loaders/flash/sh_qspi/Makefile +++ b/contrib/loaders/flash/sh_qspi/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + CROSS_COMPILE=arm-linux-gnueabihf- BIN2C = ../../../../src/helper/bin2char.sh diff --git a/contrib/loaders/flash/sh_qspi/sh_qspi.S b/contrib/loaders/flash/sh_qspi/sh_qspi.S index 78eb1e8187..b46514a487 100644 --- a/contrib/loaders/flash/sh_qspi/sh_qspi.S +++ b/contrib/loaders/flash/sh_qspi/sh_qspi.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SH QSPI (Quad SPI) driver * Copyright (C) 2019 Marek Vasut diff --git a/contrib/loaders/flash/sh_qspi/sh_qspi.ld b/contrib/loaders/flash/sh_qspi/sh_qspi.ld index 2683c520b5..71cc3e380d 100644 --- a/contrib/loaders/flash/sh_qspi/sh_qspi.ld +++ b/contrib/loaders/flash/sh_qspi/sh_qspi.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) diff --git a/contrib/loaders/flash/sim3x.s b/contrib/loaders/flash/sim3x.s index cdb3ef6811..6031f0c31f 100644 --- a/contrib/loaders/flash/sim3x.s +++ b/contrib/loaders/flash/sim3x.s @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2014 by Ladislav Bábel * * ladababel@seznam.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * ***************************************************************************/ #define INITIAL_UNLOCK 0x5A diff --git a/contrib/loaders/flash/stellaris.s b/contrib/loaders/flash/stellaris.s index 6e1ed69cd1..0f2d0f59e9 100644 --- a/contrib/loaders/flash/stellaris.s +++ b/contrib/loaders/flash/stellaris.s @@ -1,24 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stm32/Makefile b/contrib/loaders/flash/stm32/Makefile index cee282aa3e..5a97e7bb9c 100644 --- a/contrib/loaders/flash/stm32/Makefile +++ b/contrib/loaders/flash/stm32/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/stm32/stm32f1x.S b/contrib/loaders/flash/stm32/stm32f1x.S index 7b64c67aa3..fb214da31e 100644 --- a/contrib/loaders/flash/stm32/stm32f1x.S +++ b/contrib/loaders/flash/stm32/stm32f1x.S @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2011 by Andreas Fritiofson * * andreas.fritiofson@gmail.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stm32/stm32f2x.S b/contrib/loaders/flash/stm32/stm32f2x.S index f6f5b30a49..95e5e384fb 100644 --- a/contrib/loaders/flash/stm32/stm32f2x.S +++ b/contrib/loaders/flash/stm32/stm32f2x.S @@ -1,24 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * * * * Copyright (C) 2011 Øyvind Harboe * * oyvind.harboe@zylin.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stm32/stm32h7x.S b/contrib/loaders/flash/stm32/stm32h7x.S index 8ef42a4cf9..e4a172a166 100644 --- a/contrib/loaders/flash/stm32/stm32h7x.S +++ b/contrib/loaders/flash/stm32/stm32h7x.S @@ -1,19 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2017 by STMicroelectronics * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stm32/stm32l4x.c b/contrib/loaders/flash/stm32/stm32l4x.c index 54c88a3355..b657ec9aea 100644 --- a/contrib/loaders/flash/stm32/stm32l4x.c +++ b/contrib/loaders/flash/stm32/stm32l4x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /** * Copyright (C) 2021 Tarek BOCHKATI diff --git a/contrib/loaders/flash/stm32/stm32lx.S b/contrib/loaders/flash/stm32/stm32lx.S index 7cfe485452..fc90847b1b 100644 --- a/contrib/loaders/flash/stm32/stm32lx.S +++ b/contrib/loaders/flash/stm32/stm32lx.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * @@ -10,16 +12,6 @@ * * * Copyright (C) 2017 Armin van der Togt * * armin@otheruse.nl * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/Makefile b/contrib/loaders/flash/stmqspi/Makefile index 810c7e87c1..b07d452a82 100644 --- a/contrib/loaders/flash/stmqspi/Makefile +++ b/contrib/loaders/flash/stmqspi/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh SRCS=stmqspi_erase_check.S stmqspi_crc32.S stmqspi_read.S stmqspi_write.S \ diff --git a/contrib/loaders/flash/stmqspi/gpio_conf_stm32.pl b/contrib/loaders/flash/stmqspi/gpio_conf_stm32.pl index b7538640ed..49b15c2022 100755 --- a/contrib/loaders/flash/stmqspi/gpio_conf_stm32.pl +++ b/contrib/loaders/flash/stmqspi/gpio_conf_stm32.pl @@ -1,4 +1,6 @@ #!/usr/bin/perl +# SPDX-License-Identifier: GPL-2.0-or-later + # # Helper for generating GPIO setup for STM32F0, F4, F7, H7, L0, L1, L4, L4+ # and F1 (for 'stmqspi' and 'cmspi' drivers). diff --git a/contrib/loaders/flash/stmqspi/stmoctospi_crc32.S b/contrib/loaders/flash/stmqspi/stmoctospi_crc32.S index 941ea42c63..338fba370b 100644 --- a/contrib/loaders/flash/stmqspi/stmoctospi_crc32.S +++ b/contrib/loaders/flash/stmqspi/stmoctospi_crc32.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S b/contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S index 3af82d4d8a..6593a8edea 100644 --- a/contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S +++ b/contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmoctospi_read.S b/contrib/loaders/flash/stmqspi/stmoctospi_read.S index fb5ff1ff9c..8cc786ed6f 100644 --- a/contrib/loaders/flash/stmqspi/stmoctospi_read.S +++ b/contrib/loaders/flash/stmqspi/stmoctospi_read.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmoctospi_write.S b/contrib/loaders/flash/stmqspi/stmoctospi_write.S index 867a024830..245b99c559 100644 --- a/contrib/loaders/flash/stmqspi/stmoctospi_write.S +++ b/contrib/loaders/flash/stmqspi/stmoctospi_write.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2018 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmqspi_crc32.S b/contrib/loaders/flash/stmqspi/stmqspi_crc32.S index bfb2662ca3..4dd5671cae 100644 --- a/contrib/loaders/flash/stmqspi/stmqspi_crc32.S +++ b/contrib/loaders/flash/stmqspi/stmqspi_crc32.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmqspi_erase_check.S b/contrib/loaders/flash/stmqspi/stmqspi_erase_check.S index d011103a2f..5fddbcbb9c 100644 --- a/contrib/loaders/flash/stmqspi/stmqspi_erase_check.S +++ b/contrib/loaders/flash/stmqspi/stmqspi_erase_check.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmqspi_read.S b/contrib/loaders/flash/stmqspi/stmqspi_read.S index b84d4ebd72..f6bf87633f 100644 --- a/contrib/loaders/flash/stmqspi/stmqspi_read.S +++ b/contrib/loaders/flash/stmqspi/stmqspi_read.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/stmqspi/stmqspi_write.S b/contrib/loaders/flash/stmqspi/stmqspi_write.S index 40953acf68..9991d346ea 100644 --- a/contrib/loaders/flash/stmqspi/stmqspi_write.S +++ b/contrib/loaders/flash/stmqspi/stmqspi_write.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2016 - 2018 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/str7x.s b/contrib/loaders/flash/str7x.s index cd19013be1..8630bb7872 100644 --- a/contrib/loaders/flash/str7x.s +++ b/contrib/loaders/flash/str7x.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/str9x.s b/contrib/loaders/flash/str9x.s index 279b175036..53d385698a 100644 --- a/contrib/loaders/flash/str9x.s +++ b/contrib/loaders/flash/str9x.s @@ -1,21 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ .text diff --git a/contrib/loaders/flash/xmc1xxx/Makefile b/contrib/loaders/flash/xmc1xxx/Makefile index b97c602d03..0bda5b72ab 100644 --- a/contrib/loaders/flash/xmc1xxx/Makefile +++ b/contrib/loaders/flash/xmc1xxx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../../src/helper/bin2char.sh CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/flash/xmc1xxx/erase.S b/contrib/loaders/flash/xmc1xxx/erase.S index e5a4808fcc..9d3d9925c1 100644 --- a/contrib/loaders/flash/xmc1xxx/erase.S +++ b/contrib/loaders/flash/xmc1xxx/erase.S @@ -1,11 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Infineon XMC1000 flash sectors erase * * Copyright (c) 2016 Andreas Färber * * Based on XMC1100 AA-Step Reference Manual - * - * License: GPL-2.0+ */ #include "xmc1xxx.S" diff --git a/contrib/loaders/flash/xmc1xxx/erase_check.S b/contrib/loaders/flash/xmc1xxx/erase_check.S index 6c993443a9..311c2044d2 100644 --- a/contrib/loaders/flash/xmc1xxx/erase_check.S +++ b/contrib/loaders/flash/xmc1xxx/erase_check.S @@ -1,11 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Infineon XMC1000 flash sector erase check * * Copyright (c) 2016 Andreas Färber * * Based on XMC1100 AA-Step Reference Manual - * - * License: GPL-2.0+ */ #include "xmc1xxx.S" diff --git a/contrib/loaders/flash/xmc1xxx/write.S b/contrib/loaders/flash/xmc1xxx/write.S index 640f6ca960..1754252445 100644 --- a/contrib/loaders/flash/xmc1xxx/write.S +++ b/contrib/loaders/flash/xmc1xxx/write.S @@ -1,11 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Infineon XMC1000 flash write * * Copyright (c) 2016 Andreas Färber * * Based on XMC1100 AA-Step Reference Manual - * - * License: GPL-2.0+ */ #include "xmc1xxx.S" diff --git a/contrib/loaders/flash/xmc1xxx/xmc1xxx.S b/contrib/loaders/flash/xmc1xxx/xmc1xxx.S index dfe7d3f41e..5be141d6df 100644 --- a/contrib/loaders/flash/xmc1xxx/xmc1xxx.S +++ b/contrib/loaders/flash/xmc1xxx/xmc1xxx.S @@ -1,11 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Infineon XMC1000 flash * * Copyright (c) 2016 Andreas Färber * * Based on XMC1100 AA-Step Reference Manual - * - * License: GPL-2.0+ */ .text diff --git a/contrib/loaders/reset/espressif/common.mk b/contrib/loaders/reset/espressif/common.mk index 4623583aa6..f77efe6769 100644 --- a/contrib/loaders/reset/espressif/common.mk +++ b/contrib/loaders/reset/espressif/common.mk @@ -1,18 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ESP32 Makefile to compile the SoC reset program # Copyright (C) 2022 Espressif Systems Ltd. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see # Pass V=1 to see the commands being executed by make ifneq ("$(V)","1") diff --git a/contrib/loaders/reset/espressif/esp32/Makefile b/contrib/loaders/reset/espressif/esp32/Makefile index 3551b6a5ea..a63178065f 100644 --- a/contrib/loaders/reset/espressif/esp32/Makefile +++ b/contrib/loaders/reset/espressif/esp32/Makefile @@ -1,18 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ESP32 Makefile to compile the SoC reset program # Copyright (C) 2022 Espressif Systems Ltd. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see # Prefix for ESP32 cross compilers (can include a directory path) CROSS ?= xtensa-esp32-elf- diff --git a/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S index 1132545568..506d41e85c 100644 --- a/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S +++ b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Reset stub used by esp32 target * * Copyright (C) 2017 Espressif Systems Ltd. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #define RTC_CNTL_RESET_STATE_REG 0x3ff48034 diff --git a/contrib/loaders/reset/espressif/esp32s3/Makefile b/contrib/loaders/reset/espressif/esp32s3/Makefile index 4dab161fd0..37d5f82815 100644 --- a/contrib/loaders/reset/espressif/esp32s3/Makefile +++ b/contrib/loaders/reset/espressif/esp32s3/Makefile @@ -1,18 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ESP32 Makefile to compile the SoC reset program # Copyright (C) 2022 Espressif Systems Ltd. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see # Prefix for ESP32 cross compilers (can include a directory path) CROSS ?= xtensa-esp32s3-elf- diff --git a/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S index e70ac9ca7b..5fc635725f 100644 --- a/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S +++ b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Reset stub used by esp32s3 target * * Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ #define RTC_CNTL_RESET_STATE_REG 0x60008038 diff --git a/contrib/loaders/trampoline/espressif/xtensa/Makefile b/contrib/loaders/trampoline/espressif/xtensa/Makefile new file mode 100644 index 0000000000..bd1f630449 --- /dev/null +++ b/contrib/loaders/trampoline/espressif/xtensa/Makefile @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Espressif Xtensa Makefile to compile flasher stub wrapper +# Copyright (C) 2023 Espressif Systems Ltd. + +# Prefix for Espressif xtensa cross compilers (can include a directory path) +CROSS ?= xtensa-esp32-elf- + +APP_ARCH := xtensa +APP_CHIP_PATH := $(shell pwd) +SRCS := $(APP_CHIP_PATH)/esp_xtensa_stub_tramp_win.S + +BIN2C = ../../../../../src/helper/bin2char.sh +BUILD_DIR = build + +APP = esp_xtensa_stub_tramp_win +APP_OBJ = $(BUILD_DIR)/$(APP).o +APP_BIN = $(BUILD_DIR)/$(APP).bin +APP_CODE = $(APP).inc + +.PHONY: all clean + +all: $(BUILD_DIR) $(APP_OBJ) $(APP_CODE) + +$(BUILD_DIR): + $(Q) mkdir $@ + +$(APP_OBJ): $(SRCS) + @echo " CC $^ -> $@" + $(Q) $(CROSS)gcc -c $(CFLAGS) -o $@ $^ + +$(APP_CODE): $(APP_OBJ) + @echo " CC $^ -> $@" + $(Q) $(CROSS)objcopy -O binary -j.text $^ $(APP_BIN) + $(Q) $(BIN2C) < $(APP_BIN) > $@ + +clean: + $(Q) rm -rf $(BUILD_DIR) diff --git a/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.S b/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.S new file mode 100644 index 0000000000..e0c827d9f3 --- /dev/null +++ b/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.S @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Xtensa flasher stub wrapper * + * Copyright (C) 2017 Espressif Systems Ltd. * + ***************************************************************************/ + +/* + * Expects : + * a0 = zero + * a1 = stack_base + stack_size - 16, 16 bytes aligned + * a8 = address of the function to call + * Params : + * a2 = command arg0, result (out) + * a3 = command arg1 + * a4 = command arg2 + * a5 = command arg3 + * a6 = command arg4 + * Maximum 5 user args + */ + .text + + .align 4 +_stub_enter: + /* initialize initial stack frame for callx8 */ + addi a9, sp, 32 /* point 16 past extra save area */ + s32e a9, sp, -12 /* access to extra save area */ + /* prepare args */ + mov a10, a2 + mov a11, a3 + mov a12, a4 + mov a13, a5 + mov a14, a6 + /* call stub */ + callx8 a8 + /* prepare return value */ + mov a2, a10 + break 0,0 + +_idle_loop: + j _idle_loop diff --git a/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.inc b/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.inc new file mode 100644 index 0000000000..1657223e1b --- /dev/null +++ b/contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.inc @@ -0,0 +1,3 @@ +/* Autogenerated with ../../../../../src/helper/bin2char.sh */ +0x92,0xc1,0x20,0x90,0xd1,0x49,0xad,0x02,0xbd,0x03,0xcd,0x04,0xdd,0x05,0x60,0xe6, +0x20,0xe0,0x08,0x00,0x2d,0x0a,0x00,0x40,0x00,0x06,0xff,0xff, diff --git a/contrib/loaders/watchdog/Makefile b/contrib/loaders/watchdog/Makefile index ed6d8f4e55..2da9c32eca 100644 --- a/contrib/loaders/watchdog/Makefile +++ b/contrib/loaders/watchdog/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + BIN2C = ../../../src/helper/bin2char.sh ARM_CROSS_COMPILE ?= arm-none-eabi- diff --git a/contrib/loaders/watchdog/armv7m_kinetis_wdog.s b/contrib/loaders/watchdog/armv7m_kinetis_wdog.s index 2a7eb89842..d4e78ea030 100644 --- a/contrib/loaders/watchdog/armv7m_kinetis_wdog.s +++ b/contrib/loaders/watchdog/armv7m_kinetis_wdog.s @@ -1,20 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2015 Tomas Vanek * * vanekt@fbl.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc. * ***************************************************************************/ /* diff --git a/contrib/loaders/watchdog/armv7m_kinetis_wdog32.s b/contrib/loaders/watchdog/armv7m_kinetis_wdog32.s index 1284ab0a2f..2d96346bab 100644 --- a/contrib/loaders/watchdog/armv7m_kinetis_wdog32.s +++ b/contrib/loaders/watchdog/armv7m_kinetis_wdog32.s @@ -1,20 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2017 Tomas Vanek * * vanekt@fbl.cz * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc. * ***************************************************************************/ /* diff --git a/contrib/remote_bitbang/remote_bitbang_sysfsgpio.c b/contrib/remote_bitbang/remote_bitbang_sysfsgpio.c index 6cf30c3bc4..1588eb9a3c 100644 --- a/contrib/remote_bitbang/remote_bitbang_sysfsgpio.c +++ b/contrib/remote_bitbang/remote_bitbang_sysfsgpio.c @@ -1,41 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** + * Copyright (C) 2021 by Manuel Wick * * Copyright (C) 2013 Paul Fertser * * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see . * ***************************************************************************/ /* - This is a test application to be used as a remote bitbang server for - the OpenOCD remote_bitbang interface driver. - - To compile run: - gcc -Wall -ansi -pedantic -std=c99 -o remote_bitbang_sysfsgpio remote_bitbang_sysfsgpio.c - - - Usage example: - - On Raspberry Pi run: - socat TCP6-LISTEN:7777,fork EXEC:"sudo ./remote_bitbang_sysfsgpio tck 11 tms 25 tdo 9 tdi 10" - - On host run: - openocd -c "interface remote_bitbang; remote_bitbang host raspberrypi; remote_bitbang port 7777" \ - -f target/stm32f1x.cfg - - Or if you want to test UNIX sockets, run both on Raspberry Pi: - socat UNIX-LISTEN:/tmp/remotebitbang-socket,fork EXEC:"sudo ./remote_bitbang_sysfsgpio tck 11 tms 25 tdo 9 tdi 10" - openocd -c "interface remote_bitbang; remote_bitbang host /tmp/remotebitbang-socket" -f target/stm32f1x.cfg + * This is a test application to be used as a remote bitbang server for + * the OpenOCD remote_bitbang interface driver. + * + * To compile run: + * gcc -Wall -ansi -pedantic -std=c99 -o remote_bitbang_sysfsgpio remote_bitbang_sysfsgpio.c + * + * + * Usage example: + * + * On Raspberry Pi run: + * socat TCP6-LISTEN:7777,fork EXEC:"sudo ./remote_bitbang_sysfsgpio tck 11 tms 25 tdo 9 tdi 10" + * + * On host run: + * openocd -c "adapter driver remote_bitbang; remote_bitbang host raspberrypi; remote_bitbang port 7777" \ + * -f target/stm32f1x.cfg + * + * Or if you want to test UNIX sockets, run both on Raspberry Pi: + * socat UNIX-LISTEN:/tmp/remotebitbang-socket,fork EXEC:"sudo ./remote_bitbang_sysfsgpio tck 11 tms 25 tdo 9 tdi 10" + * openocd -c "adapter driver remote_bitbang; remote_bitbang host /tmp/remotebitbang-socket" -f target/stm32f1x.cfg */ #include @@ -108,11 +98,14 @@ static void unexport_sysfs_gpio(int gpio) * If the gpio is an output, it is initialized according to init_high, * otherwise it is ignored. * + * When open_rw is set, the file descriptor will be open as read and write, + * e.g. for SWDIO (TMS) that is used as input and output. + * * If the gpio is already exported we just show a warning and continue; if * openocd happened to crash (or was killed by user) then the gpios will not * have been cleaned up. */ -static int setup_sysfs_gpio(int gpio, int is_output, int init_high) +static int setup_sysfs_gpio(int gpio, int is_output, int init_high, int open_rw) { char buf[40]; char gpiostr[4]; @@ -143,7 +136,9 @@ static int setup_sysfs_gpio(int gpio, int is_output, int init_high) } snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/value", gpio); - if (is_output) + if (open_rw) + ret = open(buf, O_RDWR | O_NONBLOCK | O_SYNC); + else if (is_output) ret = open(buf, O_WRONLY | O_NONBLOCK | O_SYNC); else ret = open(buf, O_RDONLY | O_NONBLOCK | O_SYNC); @@ -154,6 +149,37 @@ static int setup_sysfs_gpio(int gpio, int is_output, int init_high) return ret; } +/* + * Change direction for gpio. + */ +static int change_dir_sysfs_gpio(int gpio, int is_output, int init_high) +{ + char buf[40]; + int ret; + + if (!is_gpio_valid(gpio)) + return ERROR_OK; + + snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/direction", gpio); + ret = open_write_close(buf, is_output ? (init_high ? "high" : "low") : "in"); + if (ret < 0) { + LOG_ERROR("Couldn't set direction for gpio %d", gpio); + perror("sysfsgpio: "); + unexport_sysfs_gpio(gpio); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +/* gpio numbers for each gpio. Negative values are invalid */ +static int tck_gpio = -1; +static int tms_gpio = -1; +static int tdi_gpio = -1; +static int tdo_gpio = -1; +static int trst_gpio = -1; +static int srst_gpio = -1; + /* * file descriptors for /sys/class/gpio/gpioXX/value * Set up during init. @@ -165,6 +191,15 @@ static int tdo_fd = -1; static int trst_fd = -1; static int srst_fd = -1; +/* + * GPIO state of /sys/class/gpio/gpioXX/value + */ +static int last_tck = -1; +static int last_tms = -1; +static int last_tms_drive = -1; +static int last_tdi = -1; +static int last_initialized = -1; + /* * Bitbang interface read of TDO * @@ -190,26 +225,22 @@ static int sysfsgpio_read(void) /* * Bitbang interface write of TCK, TMS, TDI * - * Seeing as this is the only function where the outputs are changed, - * we can cache the old value to avoid needlessly writing it. + * Output states are changed here and in sysfsgpio_write_swd, + * which are not used simultaneously, so we can cache the old + * value to avoid needlessly writing it. */ static void sysfsgpio_write(int tck, int tms, int tdi) { const char one[] = "1"; const char zero[] = "0"; - static int last_tck; - static int last_tms; - static int last_tdi; - - static int first_time; size_t bytes_written; - if (!first_time) { + if (!last_initialized) { last_tck = !tck; last_tms = !tms; last_tdi = !tdi; - first_time = 1; + last_initialized = 1; } if (tdi != last_tdi) { @@ -262,13 +293,81 @@ static void sysfsgpio_reset(int trst, int srst) } } -/* gpio numbers for each gpio. Negative values are invalid */ -static int tck_gpio = -1; -static int tms_gpio = -1; -static int tdi_gpio = -1; -static int tdo_gpio = -1; -static int trst_gpio = -1; -static int srst_gpio = -1; +/* + * Bitbang interface set direction of SWDIO (TMS) + */ +static void sysfsgpio_swdio_drive(int is_output) +{ + int ret; + + if (is_output != 0 && last_tms == -1) + last_tms = 0; + + ret = change_dir_sysfs_gpio(tms_gpio, (is_output != 0) ? 1 : 0, last_tms); + if (ret != ERROR_OK) + LOG_WARNING("Failed to change SWDIO (TMS) direction to output"); + else + last_tms_drive = (is_output != 0) ? 1 : 0; +} + +/* + * Bitbang interface read of SWDIO (TMS) + * + * The sysfs value will read back either '0' or '1'. The trick here is to call + * lseek to bypass buffering in the sysfs kernel driver. + */ +static int sysfsgpio_swdio_read(void) +{ + char buf[1]; + + /* important to seek to signal sysfs of new read */ + lseek(tms_fd, 0, SEEK_SET); + int ret = read(tms_fd, &buf, sizeof(buf)); + + if (ret < 0) { + LOG_WARNING("reading swdio (tms) failed"); + return 0; + } + + return buf[0]; +} + +/* + * Bitbang interface write of SWCLK (TCK) and SWDIO (TMS) + * + * Output states are changed here and in sysfsgpio_write, which + * are not used simultaneously, so we can cache the old value + * to avoid needlessly writing it. + */ +static void sysfsgpio_swd_write(int swclk, int swdio) +{ + static const char one[] = "1"; + static const char zero[] = "0"; + + size_t bytes_written; + + if (!last_initialized) { + last_tck = !swclk; + last_tms = !swdio; + last_initialized = 1; + } + + if (last_tms_drive == 1 && swdio != last_tms) { + bytes_written = write(tms_fd, swdio ? &one : &zero, 1); + if (bytes_written != 1) + LOG_WARNING("writing swdio (tms) failed"); + } + + /* write clk last */ + if (swclk != last_tck) { + bytes_written = write(tck_fd, swclk ? &one : &zero, 1); + if (bytes_written != 1) + LOG_WARNING("writing swclk (tck) failed"); + } + + last_tms = swdio; + last_tck = swclk; +} /* helper func to close and cleanup files only if they were valid/ used */ static void cleanup_fd(int fd, int gpio) @@ -304,13 +403,21 @@ static void process_remote_protocol(void) char d = c - 'r'; sysfsgpio_reset(!!(d & 2), (d & 1)); - } else if (c >= '0' && c <= '0' + 7) {/* Write */ + } else if (c >= '0' && c <= '0' + 7) { /* Write */ char d = c - '0'; sysfsgpio_write(!!(d & 4), !!(d & 2), (d & 1)); } else if (c == 'R') putchar(sysfsgpio_read()); + else if (c == 'c') /* SWDIO read */ + putchar(sysfsgpio_swdio_read()); + else if (c == 'o' || c == 'O') /* SWDIO drive */ + sysfsgpio_swdio_drive(c == 'o' ? 0 : 1); + else if (c >= 'd' && c <= 'g') { /* SWD write */ + char d = c - 'd'; + sysfsgpio_swd_write((d & 2), (d & 1)); + } else LOG_ERROR("Unknown command '%c' received", c); } @@ -318,7 +425,7 @@ static void process_remote_protocol(void) int main(int argc, char *argv[]) { - LOG_WARNING("SysfsGPIO remote_bitbang JTAG driver\n"); + LOG_WARNING("SysfsGPIO remote_bitbang JTAG+SWD driver\n"); for (int i = 1; i < argc; i++) { if (!strcmp(argv[i], "tck")) @@ -360,36 +467,39 @@ int main(int argc, char *argv[]) * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high. */ - tck_fd = setup_sysfs_gpio(tck_gpio, 1, 0); + tck_fd = setup_sysfs_gpio(tck_gpio, 1, 0, 0); if (tck_fd < 0) goto out_error; - tms_fd = setup_sysfs_gpio(tms_gpio, 1, 1); + tms_fd = setup_sysfs_gpio(tms_gpio, 1, 1, 1); if (tms_fd < 0) goto out_error; + last_tms_drive = 0; - tdi_fd = setup_sysfs_gpio(tdi_gpio, 1, 0); + tdi_fd = setup_sysfs_gpio(tdi_gpio, 1, 0, 0); if (tdi_fd < 0) goto out_error; - tdo_fd = setup_sysfs_gpio(tdo_gpio, 0, 0); + tdo_fd = setup_sysfs_gpio(tdo_gpio, 0, 0, 0); if (tdo_fd < 0) goto out_error; /* assume active low */ if (trst_gpio > 0) { - trst_fd = setup_sysfs_gpio(trst_gpio, 1, 1); + trst_fd = setup_sysfs_gpio(trst_gpio, 1, 1, 0); if (trst_fd < 0) goto out_error; } /* assume active low */ if (srst_gpio > 0) { - srst_fd = setup_sysfs_gpio(srst_gpio, 1, 1); + srst_fd = setup_sysfs_gpio(srst_gpio, 1, 1, 0); if (srst_fd < 0) goto out_error; } + last_initialized = 0; + LOG_WARNING("SysfsGPIO nums: tck = %d, tms = %d, tdi = %d, tdo = %d", tck_gpio, tms_gpio, tdi_gpio, tdo_gpio); LOG_WARNING("SysfsGPIO num: srst = %d", srst_gpio); diff --git a/contrib/rpc_examples/ocd_rpc_example.py b/contrib/rpc_examples/ocd_rpc_example.py index e6146f6179..53e3e2afcf 100755 --- a/contrib/rpc_examples/ocd_rpc_example.py +++ b/contrib/rpc_examples/ocd_rpc_example.py @@ -1,4 +1,6 @@ #!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-3.0-or-later + """ OpenOCD RPC example, covered by GNU GPLv3 or later Copyright (C) 2014 Andreas Ortmann (ortmann@finf.uni-hannover.de) diff --git a/contrib/rpc_examples/ocdrpc.hs b/contrib/rpc_examples/ocdrpc.hs index 859864131d..6a92366b7a 100644 --- a/contrib/rpc_examples/ocdrpc.hs +++ b/contrib/rpc_examples/ocdrpc.hs @@ -1,4 +1,6 @@ --- OpenOCD RPC example, covered by GNU GPLv3 or later +-- SPDX-License-Identifier: GPL-3.0-or-later + +-- OpenOCD RPC example -- Copyright (C) 2014 Paul Fertser -- -- Example output: diff --git a/contrib/rtos-helpers/FreeRTOS-openocd.c b/contrib/rtos-helpers/FreeRTOS-openocd.c index 81a3ab77ab..5f82ac7a2c 100644 --- a/contrib/rtos-helpers/FreeRTOS-openocd.c +++ b/contrib/rtos-helpers/FreeRTOS-openocd.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: CC0-1.0 + /* * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer * present in the kernel, so it has to be supplied by other means for diff --git a/contrib/rtos-helpers/uCOS-III-openocd.c b/contrib/rtos-helpers/uCOS-III-openocd.c index 5a37bd4c52..ff2789e0ab 100644 --- a/contrib/rtos-helpers/uCOS-III-openocd.c +++ b/contrib/rtos-helpers/uCOS-III-openocd.c @@ -1,3 +1,14 @@ +// SPDX-License-Identifier: Apache-2.0 + +/* + * The original version of this file did not reported any license nor + * copyright, but the author clearly stated that: + * "This file should be linked along with the [uC/OS-III user's] project + * to enable RTOS support for uC/OS-III." + * Such statement implies the willing to have this file's license compatible + * with the license Apache 2.0 of uC/OS-III. + */ + /* * uC/OS-III does not provide a fixed layout for OS_TCB, which makes it * impossible to determine the appropriate offsets within the structure diff --git a/contrib/xsvf_tools/svf2xsvf.py b/contrib/xsvf_tools/svf2xsvf.py index 6da7ff4a82..abbac20362 100644 --- a/contrib/xsvf_tools/svf2xsvf.py +++ b/contrib/xsvf_tools/svf2xsvf.py @@ -1,27 +1,9 @@ #!/usr/bin/python3.0 +# SPDX-License-Identifier: GPL-2.0-or-later # Copyright 2008, SoftPLC Corporation http://softplc.com # Dick Hollenbeck dick@softplc.com - -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# as published by the Free Software Foundation; either version 2 -# of the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, you may find one here: -# http://www.gnu.org/licenses/old-licenses/gpl-2.0.html -# or you may search the http://www.gnu.org website for the version 2 license, -# or you may write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - - # A python program to convert an SVF file to an XSVF file. There is an # option to include comments containing the source file line number from the origin # SVF file before each outputted XSVF statement. diff --git a/contrib/xsvf_tools/xsvfdump.py b/contrib/xsvf_tools/xsvfdump.py index 0e00ca05ce..3ed4009bdf 100644 --- a/contrib/xsvf_tools/xsvfdump.py +++ b/contrib/xsvf_tools/xsvfdump.py @@ -1,25 +1,9 @@ #!/usr/bin/python3.0 +# SPDX-License-Identifier: GPL-2.0-or-later # Copyright 2008, SoftPLC Corporation http://softplc.com # Dick Hollenbeck dick@softplc.com -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# as published by the Free Software Foundation; either version 2 -# of the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, you may find one here: -# http://www.gnu.org/licenses/old-licenses/gpl-2.0.html -# or you may search the http://www.gnu.org website for the version 2 license, -# or you may write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - # Dump an Xilinx XSVF file to stdout # This program is written for python 3.0, and it is not easy to change this diff --git a/doc/Makefile.am b/doc/Makefile.am index 67592038d5..17d051ff87 100644 --- a/doc/Makefile.am +++ b/doc/Makefile.am @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + info_TEXINFOS += %D%/openocd.texi %C%_openocd_TEXINFOS = %D%/fdl.texi diff --git a/doc/checkpatch.rst b/doc/checkpatch.rst new file mode 100644 index 0000000000..b52452bc29 --- /dev/null +++ b/doc/checkpatch.rst @@ -0,0 +1,1249 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +========== +Checkpatch +========== + +Checkpatch (scripts/checkpatch.pl) is a perl script which checks for trivial +style violations in patches and optionally corrects them. Checkpatch can +also be run on file contexts and without the kernel tree. + +Checkpatch is not always right. Your judgement takes precedence over checkpatch +messages. If your code looks better with the violations, then its probably +best left alone. + + +Options +======= + +This section will describe the options checkpatch can be run with. + +Usage:: + + ./scripts/checkpatch.pl [OPTION]... [FILE]... + +Available options: + + - -q, --quiet + + Enable quiet mode. + + - -v, --verbose + Enable verbose mode. Additional verbose test descriptions are output + so as to provide information on why that particular message is shown. + + - --no-tree + + Run checkpatch without the kernel tree. + + - --no-signoff + + Disable the 'Signed-off-by' line check. The sign-off is a simple line at + the end of the explanation for the patch, which certifies that you wrote it + or otherwise have the right to pass it on as an open-source patch. + + Example:: + + Signed-off-by: Random J Developer + + Setting this flag effectively stops a message for a missing signed-off-by + line in a patch context. + + - --patch + + Treat FILE as a patch. This is the default option and need not be + explicitly specified. + + - --emacs + + Set output to emacs compile window format. This allows emacs users to jump + from the error in the compile window directly to the offending line in the + patch. + + - --terse + + Output only one line per report. + + - --showfile + + Show the diffed file position instead of the input file position. + + - -g, --git + + Treat FILE as a single commit or a git revision range. + + Single commit with: + + - + - ^ + - ~n + + Multiple commits with: + + - .. + - ... + - - + + - -f, --file + + Treat FILE as a regular source file. This option must be used when running + checkpatch on source files in the kernel. + + - --subjective, --strict + + Enable stricter tests in checkpatch. By default the tests emitted as CHECK + do not activate by default. Use this flag to activate the CHECK tests. + + - --list-types + + Every message emitted by checkpatch has an associated TYPE. Add this flag + to display all the types in checkpatch. + + Note that when this flag is active, checkpatch does not read the input FILE, + and no message is emitted. Only a list of types in checkpatch is output. + + - --types TYPE(,TYPE2...) + + Only display messages with the given types. + + Example:: + + ./scripts/checkpatch.pl mypatch.patch --types EMAIL_SUBJECT,BRACES + + - --ignore TYPE(,TYPE2...) + + Checkpatch will not emit messages for the specified types. + + Example:: + + ./scripts/checkpatch.pl mypatch.patch --ignore EMAIL_SUBJECT,BRACES + + - --show-types + + By default checkpatch doesn't display the type associated with the messages. + Set this flag to show the message type in the output. + + - --max-line-length=n + + Set the max line length (default 100). If a line exceeds the specified + length, a LONG_LINE message is emitted. + + + The message level is different for patch and file contexts. For patches, + a WARNING is emitted. While a milder CHECK is emitted for files. So for + file contexts, the --strict flag must also be enabled. + + - --min-conf-desc-length=n + + Set the Kconfig entry minimum description length, if shorter, warn. + + - --tab-size=n + + Set the number of spaces for tab (default 8). + + - --root=PATH + + PATH to the kernel tree root. + + This option must be specified when invoking checkpatch from outside + the kernel root. + + - --no-summary + + Suppress the per file summary. + + - --mailback + + Only produce a report in case of Warnings or Errors. Milder Checks are + excluded from this. + + - --summary-file + + Include the filename in summary. + + - --debug KEY=[0|1] + + Turn on/off debugging of KEY, where KEY is one of 'values', 'possible', + 'type', and 'attr' (default is all off). + + - --fix + + This is an EXPERIMENTAL feature. If correctable errors exists, a file + .EXPERIMENTAL-checkpatch-fixes is created which has the + automatically fixable errors corrected. + + - --fix-inplace + + EXPERIMENTAL - Similar to --fix but input file is overwritten with fixes. + + DO NOT USE this flag unless you are absolutely sure and you have a backup + in place. + + - --ignore-perl-version + + Override checking of perl version. Runtime errors maybe encountered after + enabling this flag if the perl version does not meet the minimum specified. + + - --codespell + + Use the codespell dictionary for checking spelling errors. + + - --codespellfile + + Use the specified codespell file. + Default is '/usr/share/codespell/dictionary.txt'. + + - --typedefsfile + + Read additional types from this file. + + - --color[=WHEN] + + Use colors 'always', 'never', or only when output is a terminal ('auto'). + Default is 'auto'. + + - --kconfig-prefix=WORD + + Use WORD as a prefix for Kconfig symbols (default is `CONFIG_`). + + - -h, --help, --version + + Display the help text. + +Message Levels +============== + +Messages in checkpatch are divided into three levels. The levels of messages +in checkpatch denote the severity of the error. They are: + + - ERROR + + This is the most strict level. Messages of type ERROR must be taken + seriously as they denote things that are very likely to be wrong. + + - WARNING + + This is the next stricter level. Messages of type WARNING requires a + more careful review. But it is milder than an ERROR. + + - CHECK + + This is the mildest level. These are things which may require some thought. + +Type Descriptions +================= + +This section contains a description of all the message types in checkpatch. + +.. Types in this section are also parsed by checkpatch. +.. The types are grouped into subsections based on use. + + +Allocation style +---------------- + + **ALLOC_ARRAY_ARGS** + The first argument for kcalloc or kmalloc_array should be the + number of elements. sizeof() as the first argument is generally + wrong. + + See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html + + **ALLOC_SIZEOF_STRUCT** + The allocation style is bad. In general for family of + allocation functions using sizeof() to get memory size, + constructs like:: + + p = alloc(sizeof(struct foo), ...) + + should be:: + + p = alloc(sizeof(*p), ...) + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#allocating-memory + + **ALLOC_WITH_MULTIPLY** + Prefer kmalloc_array/kcalloc over kmalloc/kzalloc with a + sizeof multiply. + + See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html + + +API usage +--------- + + **ARCH_DEFINES** + Architecture specific defines should be avoided wherever + possible. + + **ARCH_INCLUDE_LINUX** + Whenever asm/file.h is included and linux/file.h exists, a + conversion can be made when linux/file.h includes asm/file.h. + However this is not always the case (See signal.h). + This message type is emitted only for includes from arch/. + + **AVOID_BUG** + BUG() or BUG_ON() should be avoided totally. + Use WARN() and WARN_ON() instead, and handle the "impossible" + error condition as gracefully as possible. + + See: https://www.kernel.org/doc/html/latest/process/deprecated.html#bug-and-bug-on + + **CONSIDER_KSTRTO** + The simple_strtol(), simple_strtoll(), simple_strtoul(), and + simple_strtoull() functions explicitly ignore overflows, which + may lead to unexpected results in callers. The respective kstrtol(), + kstrtoll(), kstrtoul(), and kstrtoull() functions tend to be the + correct replacements. + + See: https://www.kernel.org/doc/html/latest/process/deprecated.html#simple-strtol-simple-strtoll-simple-strtoul-simple-strtoull + + **CONSTANT_CONVERSION** + Use of __constant_ form is discouraged for the following functions:: + + __constant_cpu_to_be[x] + __constant_cpu_to_le[x] + __constant_be[x]_to_cpu + __constant_le[x]_to_cpu + __constant_htons + __constant_ntohs + + Using any of these outside of include/uapi/ is not preferred as using the + function without __constant_ is identical when the argument is a + constant. + + In big endian systems, the macros like __constant_cpu_to_be32(x) and + cpu_to_be32(x) expand to the same expression:: + + #define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x)) + #define __cpu_to_be32(x) ((__force __be32)(__u32)(x)) + + In little endian systems, the macros __constant_cpu_to_be32(x) and + cpu_to_be32(x) expand to __constant_swab32 and __swab32. __swab32 + has a __builtin_constant_p check:: + + #define __swab32(x) \ + (__builtin_constant_p((__u32)(x)) ? \ + ___constant_swab32(x) : \ + __fswab32(x)) + + So ultimately they have a special case for constants. + Similar is the case with all of the macros in the list. Thus + using the __constant_... forms are unnecessarily verbose and + not preferred outside of include/uapi. + + See: https://lore.kernel.org/lkml/1400106425.12666.6.camel@joe-AO725/ + + **DEPRECATED_API** + Usage of a deprecated RCU API is detected. It is recommended to replace + old flavourful RCU APIs by their new vanilla-RCU counterparts. + + The full list of available RCU APIs can be viewed from the kernel docs. + + See: https://www.kernel.org/doc/html/latest/RCU/whatisRCU.html#full-list-of-rcu-apis + + **DEPRECATED_VARIABLE** + EXTRA_{A,C,CPP,LD}FLAGS are deprecated and should be replaced by the new + flags added via commit f77bf01425b1 ("kbuild: introduce ccflags-y, + asflags-y and ldflags-y"). + + The following conversion scheme maybe used:: + + EXTRA_AFLAGS -> asflags-y + EXTRA_CFLAGS -> ccflags-y + EXTRA_CPPFLAGS -> cppflags-y + EXTRA_LDFLAGS -> ldflags-y + + See: + + 1. https://lore.kernel.org/lkml/20070930191054.GA15876@uranus.ravnborg.org/ + 2. https://lore.kernel.org/lkml/1313384834-24433-12-git-send-email-lacombar@gmail.com/ + 3. https://www.kernel.org/doc/html/latest/kbuild/makefiles.html#compilation-flags + + **DEVICE_ATTR_FUNCTIONS** + The function names used in DEVICE_ATTR is unusual. + Typically, the store and show functions are used with _store and + _show, where is a named attribute variable of the device. + + Consider the following examples:: + + static DEVICE_ATTR(type, 0444, type_show, NULL); + static DEVICE_ATTR(power, 0644, power_show, power_store); + + The function names should preferably follow the above pattern. + + See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes + + **DEVICE_ATTR_RO** + The DEVICE_ATTR_RO(name) helper macro can be used instead of + DEVICE_ATTR(name, 0444, name_show, NULL); + + Note that the macro automatically appends _show to the named + attribute variable of the device for the show method. + + See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes + + **DEVICE_ATTR_RW** + The DEVICE_ATTR_RW(name) helper macro can be used instead of + DEVICE_ATTR(name, 0644, name_show, name_store); + + Note that the macro automatically appends _show and _store to the + named attribute variable of the device for the show and store methods. + + See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes + + **DEVICE_ATTR_WO** + The DEVICE_AATR_WO(name) helper macro can be used instead of + DEVICE_ATTR(name, 0200, NULL, name_store); + + Note that the macro automatically appends _store to the + named attribute variable of the device for the store method. + + See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes + + **DUPLICATED_SYSCTL_CONST** + Commit d91bff3011cf ("proc/sysctl: add shared variables for range + check") added some shared const variables to be used instead of a local + copy in each source file. + + Consider replacing the sysctl range checking value with the shared + one in include/linux/sysctl.h. The following conversion scheme may + be used:: + + &zero -> SYSCTL_ZERO + &one -> SYSCTL_ONE + &int_max -> SYSCTL_INT_MAX + + See: + + 1. https://lore.kernel.org/lkml/20190430180111.10688-1-mcroce@redhat.com/ + 2. https://lore.kernel.org/lkml/20190531131422.14970-1-mcroce@redhat.com/ + + **ENOSYS** + ENOSYS means that a nonexistent system call was called. + Earlier, it was wrongly used for things like invalid operations on + otherwise valid syscalls. This should be avoided in new code. + + See: https://lore.kernel.org/lkml/5eb299021dec23c1a48fa7d9f2c8b794e967766d.1408730669.git.luto@amacapital.net/ + + **ENOTSUPP** + ENOTSUPP is not a standard error code and should be avoided in new patches. + EOPNOTSUPP should be used instead. + + See: https://lore.kernel.org/netdev/20200510182252.GA411829@lunn.ch/ + + **EXPORT_SYMBOL** + EXPORT_SYMBOL should immediately follow the symbol to be exported. + + **IN_ATOMIC** + in_atomic() is not for driver use so any such use is reported as an ERROR. + Also in_atomic() is often used to determine if sleeping is permitted, + but it is not reliable in this use model. Therefore its use is + strongly discouraged. + + However, in_atomic() is ok for core kernel use. + + See: https://lore.kernel.org/lkml/20080320201723.b87b3732.akpm@linux-foundation.org/ + + **LOCKDEP** + The lockdep_no_validate class was added as a temporary measure to + prevent warnings on conversion of device->sem to device->mutex. + It should not be used for any other purpose. + + See: https://lore.kernel.org/lkml/1268959062.9440.467.camel@laptop/ + + **MALFORMED_INCLUDE** + The #include statement has a malformed path. This has happened + because the author has included a double slash "//" in the pathname + accidentally. + + **USE_LOCKDEP** + lockdep_assert_held() annotations should be preferred over + assertions based on spin_is_locked() + + See: https://www.kernel.org/doc/html/latest/locking/lockdep-design.html#annotations + + **UAPI_INCLUDE** + No #include statements in include/uapi should use a uapi/ path. + + **USLEEP_RANGE** + usleep_range() should be preferred over udelay(). The proper way of + using usleep_range() is mentioned in the kernel docs. + + See: https://www.kernel.org/doc/html/latest/timers/timers-howto.html#delays-information-on-the-various-kernel-delay-sleep-mechanisms + + +Comments +-------- + + **BLOCK_COMMENT_STYLE** + The comment style is incorrect. The preferred style for multi- + line comments is:: + + /* + * This is the preferred style + * for multi line comments. + */ + + The networking comment style is a bit different, with the first line + not empty like the former:: + + /* This is the preferred comment style + * for files in net/ and drivers/net/ + */ + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting + + **C99_COMMENTS** + C99 style single line comments (//) should not be used. + Prefer the block comment style instead. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting + + **DATA_RACE** + Applications of data_race() should have a comment so as to document the + reasoning behind why it was deemed safe. + + See: https://lore.kernel.org/lkml/20200401101714.44781-1-elver@google.com/ + + **FSF_MAILING_ADDRESS** + Kernel maintainers reject new instances of the GPL boilerplate paragraph + directing people to write to the FSF for a copy of the GPL, since the + FSF has moved in the past and may do so again. + So do not write paragraphs about writing to the Free Software Foundation's + mailing address. + + See: https://lore.kernel.org/lkml/20131006222342.GT19510@leaf/ + + +Commit message +-------------- + + **BAD_SIGN_OFF** + The signed-off-by line does not fall in line with the standards + specified by the community. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1 + + **BAD_STABLE_ADDRESS_STYLE** + The email format for stable is incorrect. + Some valid options for stable address are:: + + 1. stable@vger.kernel.org + 2. stable@kernel.org + + For adding version info, the following comment style should be used:: + + stable@vger.kernel.org # version info + + **COMMIT_COMMENT_SYMBOL** + Commit log lines starting with a '#' are ignored by git as + comments. To solve this problem addition of a single space + infront of the log line is enough. + + **COMMIT_MESSAGE** + The patch is missing a commit description. A brief + description of the changes made by the patch should be added. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes + + **EMAIL_SUBJECT** + Naming the tool that found the issue is not very useful in the + subject line. A good subject line summarizes the change that + the patch brings. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes + + **FROM_SIGN_OFF_MISMATCH** + The author's email does not match with that in the Signed-off-by: + line(s). This can be sometimes caused due to an improperly configured + email client. + + This message is emitted due to any of the following reasons:: + + - The email names do not match. + - The email addresses do not match. + - The email subaddresses do not match. + - The email comments do not match. + + **MISSING_SIGN_OFF** + The patch is missing a Signed-off-by line. A signed-off-by + line should be added according to Developer's certificate of + Origin. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin + + **NO_AUTHOR_SIGN_OFF** + The author of the patch has not signed off the patch. It is + required that a simple sign off line should be present at the + end of explanation of the patch to denote that the author has + written it or otherwise has the rights to pass it on as an open + source patch. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin + + **DIFF_IN_COMMIT_MSG** + Avoid having diff content in commit message. + This causes problems when one tries to apply a file containing both + the changelog and the diff because patch(1) tries to apply the diff + which it found in the changelog. + + See: https://lore.kernel.org/lkml/20150611134006.9df79a893e3636019ad2759e@linux-foundation.org/ + + **GERRIT_CHANGE_ID** + To be picked up by gerrit, the footer of the commit message might + have a Change-Id like:: + + Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b + Signed-off-by: A. U. Thor + + The Change-Id line must be removed before submitting. + + **GIT_COMMIT_ID** + The proper way to reference a commit id is: + commit <12+ chars of sha1> ("") + + An example may be:: + + Commit e21d2170f36602ae2708 ("video: remove unnecessary + platform_set_drvdata()") removed the unnecessary + platform_set_drvdata(), but left the variable "dev" unused, + delete it. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes + + +Comparison style +---------------- + + **ASSIGN_IN_IF** + Do not use assignments in if condition. + Example:: + + if ((foo = bar(...)) < BAZ) { + + should be written as:: + + foo = bar(...); + if (foo < BAZ) { + + **BOOL_COMPARISON** + Comparisons of A to true and false are better written + as A and !A. + + See: https://lore.kernel.org/lkml/1365563834.27174.12.camel@joe-AO722/ + + **COMPARISON_TO_NULL** + Comparisons to NULL in the form (foo == NULL) or (foo != NULL) + are better written as (!foo) and (foo). + + **CONSTANT_COMPARISON** + Comparisons with a constant or upper case identifier on the left + side of the test should be avoided. + + +Indentation and Line Breaks +--------------------------- + + **CODE_INDENT** + Code indent should use tabs instead of spaces. + Outside of comments, documentation and Kconfig, + spaces are never used for indentation. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation + + **DEEP_INDENTATION** + Indentation with 6 or more tabs usually indicate overly indented + code. + + It is suggested to refactor excessive indentation of + if/else/for/do/while/switch statements. + + See: https://lore.kernel.org/lkml/1328311239.21255.24.camel@joe2Laptop/ + + **SWITCH_CASE_INDENT_LEVEL** + switch should be at the same indent as case. + Example:: + + switch (suffix) { + case 'G': + case 'g': + mem <<= 30; + break; + case 'M': + case 'm': + mem <<= 20; + break; + case 'K': + case 'k': + mem <<= 10; + fallthrough; + default: + break; + } + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation + + **LONG_LINE** + The line has exceeded the specified maximum length. + To use a different maximum line length, the --max-line-length=n option + may be added while invoking checkpatch. + + Earlier, the default line length was 80 columns. Commit bdc48fa11e46 + ("checkpatch/coding-style: deprecate 80-column warning") increased the + limit to 100 columns. This is not a hard limit either and it's + preferable to stay within 80 columns whenever possible. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings + + **LONG_LINE_STRING** + A string starts before but extends beyond the maximum line length. + To use a different maximum line length, the --max-line-length=n option + may be added while invoking checkpatch. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings + + **LONG_LINE_COMMENT** + A comment starts before but extends beyond the maximum line length. + To use a different maximum line length, the --max-line-length=n option + may be added while invoking checkpatch. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings + + **SPLIT_STRING** + Quoted strings that appear as messages in userspace and can be + grepped, should not be split across multiple lines. + + See: https://lore.kernel.org/lkml/20120203052727.GA15035@leaf/ + + **MULTILINE_DEREFERENCE** + A single dereferencing identifier spanned on multiple lines like:: + + struct_identifier->member[index]. + member = <foo>; + + is generally hard to follow. It can easily lead to typos and so makes + the code vulnerable to bugs. + + If fixing the multiple line dereferencing leads to an 80 column + violation, then either rewrite the code in a more simple way or if the + starting part of the dereferencing identifier is the same and used at + multiple places then store it in a temporary variable, and use that + temporary variable only at all the places. For example, if there are + two dereferencing identifiers:: + + member1->member2->member3.foo1; + member1->member2->member3.foo2; + + then store the member1->member2->member3 part in a temporary variable. + It not only helps to avoid the 80 column violation but also reduces + the program size by removing the unnecessary dereferences. + + But if none of the above methods work then ignore the 80 column + violation because it is much easier to read a dereferencing identifier + on a single line. + + **TRAILING_STATEMENTS** + Trailing statements (for example after any conditional) should be + on the next line. + Statements, such as:: + + if (x == y) break; + + should be:: + + if (x == y) + break; + + +Macros, Attributes and Symbols +------------------------------ + + **ARRAY_SIZE** + The ARRAY_SIZE(foo) macro should be preferred over + sizeof(foo)/sizeof(foo[0]) for finding number of elements in an + array. + + The macro is defined in include/linux/kernel.h:: + + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + + **AVOID_EXTERNS** + Function prototypes don't need to be declared extern in .h + files. It's assumed by the compiler and is unnecessary. + + **AVOID_L_PREFIX** + Local symbol names that are prefixed with `.L` should be avoided, + as this has special meaning for the assembler; a symbol entry will + not be emitted into the symbol table. This can prevent `objtool` + from generating correct unwind info. + + Symbols with STB_LOCAL binding may still be used, and `.L` prefixed + local symbol names are still generally usable within a function, + but `.L` prefixed local symbol names should not be used to denote + the beginning or end of code regions via + `SYM_CODE_START_LOCAL`/`SYM_CODE_END` + + **BIT_MACRO** + Defines like: 1 << <digit> could be BIT(digit). + The BIT() macro is defined via include/linux/bits.h:: + + #define BIT(nr) (1UL << (nr)) + + **CONST_READ_MOSTLY** + When a variable is tagged with the __read_mostly annotation, it is a + signal to the compiler that accesses to the variable will be mostly + reads and rarely(but NOT never) a write. + + const __read_mostly does not make any sense as const data is already + read-only. The __read_mostly annotation thus should be removed. + + **DATE_TIME** + It is generally desirable that building the same source code with + the same set of tools is reproducible, i.e. the output is always + exactly the same. + + The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros, + and enables warnings if they are used as they can lead to + non-deterministic builds. + + See: https://www.kernel.org/doc/html/latest/kbuild/reproducible-builds.html#timestamps + + **DEFINE_ARCH_HAS** + The ARCH_HAS_xyz and ARCH_HAVE_xyz patterns are wrong. + + For big conceptual features use Kconfig symbols instead. And for + smaller things where we have compatibility fallback functions but + want architectures able to override them with optimized ones, we + should either use weak functions (appropriate for some cases), or + the symbol that protects them should be the same symbol we use. + + See: https://lore.kernel.org/lkml/CA+55aFycQ9XJvEOsiM3txHL5bjUc8CeKWJNR_H+MiicaddB42Q@mail.gmail.com/ + + **DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON** + do {} while(0) macros should not have a trailing semicolon. + + **INIT_ATTRIBUTE** + Const init definitions should use __initconst instead of + __initdata. + + Similarly init definitions without const require a separate + use of const. + + **INLINE_LOCATION** + The inline keyword should sit between storage class and type. + + For example, the following segment:: + + inline static int example_function(void) + { + ... + } + + should be:: + + static inline int example_function(void) + { + ... + } + + **MISPLACED_INIT** + It is possible to use section markers on variables in a way + which gcc doesn't understand (or at least not the way the + developer intended):: + + static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = { + + does not put exynos4_plls in the .initdata section. The __initdata + marker can be virtually anywhere on the line, except right after + "struct". The preferred location is before the "=" sign if there is + one, or before the trailing ";" otherwise. + + See: https://lore.kernel.org/lkml/1377655732.3619.19.camel@joe-AO722/ + + **MULTISTATEMENT_MACRO_USE_DO_WHILE** + Macros with multiple statements should be enclosed in a + do - while block. Same should also be the case for macros + starting with `if` to avoid logic defects:: + + #define macrofun(a, b, c) \ + do { \ + if (a == 5) \ + do_this(b, c); \ + } while (0) + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#macros-enums-and-rtl + + **PREFER_FALLTHROUGH** + Use the `fallthrough;` pseudo keyword instead of + `/* fallthrough */` like comments. + + **TRAILING_SEMICOLON** + Macro definition should not end with a semicolon. The macro + invocation style should be consistent with function calls. + This can prevent any unexpected code paths:: + + #define MAC do_something; + + If this macro is used within a if else statement, like:: + + if (some_condition) + MAC; + + else + do_something; + + Then there would be a compilation error, because when the macro is + expanded there are two trailing semicolons, so the else branch gets + orphaned. + + See: https://lore.kernel.org/lkml/1399671106.2912.21.camel@joe-AO725/ + + **SINGLE_STATEMENT_DO_WHILE_MACRO** + For the multi-statement macros, it is necessary to use the do-while + loop to avoid unpredictable code paths. The do-while loop helps to + group the multiple statements into a single one so that a + function-like macro can be used as a function only. + + But for the single statement macros, it is unnecessary to use the + do-while loop. Although the code is syntactically correct but using + the do-while loop is redundant. So remove the do-while loop for single + statement macros. + + **WEAK_DECLARATION** + Using weak declarations like __attribute__((weak)) or __weak + can have unintended link defects. Avoid using them. + + +Functions and Variables +----------------------- + + **CAMELCASE** + Avoid CamelCase Identifiers. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#naming + + **CONST_CONST** + Using `const <type> const *` is generally meant to be + written `const <type> * const`. + + **CONST_STRUCT** + Using const is generally a good idea. Checkpatch reads + a list of frequently used structs that are always or + almost always constant. + + The existing structs list can be viewed from + `scripts/const_structs.checkpatch`. + + See: https://lore.kernel.org/lkml/alpine.DEB.2.10.1608281509480.3321@hadrien/ + + **EMBEDDED_FUNCTION_NAME** + Embedded function names are less appropriate to use as + refactoring can cause function renaming. Prefer the use of + "%s", __func__ to embedded function names. + + Note that this does not work with -f (--file) checkpatch option + as it depends on patch context providing the function name. + + **FUNCTION_ARGUMENTS** + This warning is emitted due to any of the following reasons: + + 1. Arguments for the function declaration do not follow + the identifier name. Example:: + + void foo + (int bar, int baz) + + This should be corrected to:: + + void foo(int bar, int baz) + + 2. Some arguments for the function definition do not + have an identifier name. Example:: + + void foo(int) + + All arguments should have identifier names. + + **FUNCTION_WITHOUT_ARGS** + Function declarations without arguments like:: + + int foo() + + should be:: + + int foo(void) + + **GLOBAL_INITIALISERS** + Global variables should not be initialized explicitly to + 0 (or NULL, false, etc.). Your compiler (or rather your + loader, which is responsible for zeroing out the relevant + sections) automatically does it for you. + + **INITIALISED_STATIC** + Static variables should not be initialized explicitly to zero. + Your compiler (or rather your loader) automatically does + it for you. + + **MULTIPLE_ASSIGNMENTS** + Multiple assignments on a single line makes the code unnecessarily + complicated. So on a single line assign value to a single variable + only, this makes the code more readable and helps avoid typos. + + **RETURN_PARENTHESES** + return is not a function and as such doesn't need parentheses:: + + return (bar); + + can simply be:: + + return bar; + + +Permissions +----------- + + **DEVICE_ATTR_PERMS** + The permissions used in DEVICE_ATTR are unusual. + Typically only three permissions are used - 0644 (RW), 0444 (RO) + and 0200 (WO). + + See: https://www.kernel.org/doc/html/latest/filesystems/sysfs.html#attributes + + **EXECUTE_PERMISSIONS** + There is no reason for source files to be executable. The executable + bit can be removed safely. + + **EXPORTED_WORLD_WRITABLE** + Exporting world writable sysfs/debugfs files is usually a bad thing. + When done arbitrarily they can introduce serious security bugs. + In the past, some of the debugfs vulnerabilities would seemingly allow + any local user to write arbitrary values into device registers - a + situation from which little good can be expected to emerge. + + See: https://lore.kernel.org/linux-arm-kernel/cover.1296818921.git.segoon@openwall.com/ + + **NON_OCTAL_PERMISSIONS** + Permission bits should use 4 digit octal permissions (like 0700 or 0444). + Avoid using any other base like decimal. + + **SYMBOLIC_PERMS** + Permission bits in the octal form are more readable and easier to + understand than their symbolic counterparts because many command-line + tools use this notation. Experienced kernel developers have been using + these traditional Unix permission bits for decades and so they find it + easier to understand the octal notation than the symbolic macros. + For example, it is harder to read S_IWUSR|S_IRUGO than 0644, which + obscures the developer's intent rather than clarifying it. + + See: https://lore.kernel.org/lkml/CA+55aFw5v23T-zvDZp-MmD_EYxF8WbafwwB59934FV7g21uMGQ@mail.gmail.com/ + + +Spacing and Brackets +-------------------- + + **ASSIGNMENT_CONTINUATIONS** + Assignment operators should not be written at the start of a + line but should follow the operand at the previous line. + + **BRACES** + The placement of braces is stylistically incorrect. + The preferred way is to put the opening brace last on the line, + and put the closing brace first:: + + if (x is true) { + we do y + } + + This applies for all non-functional blocks. + However, there is one special case, namely functions: they have the + opening brace at the beginning of the next line, thus:: + + int function(int x) + { + body of function + } + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **BRACKET_SPACE** + Whitespace before opening bracket '[' is prohibited. + There are some exceptions: + + 1. With a type on the left:: + + int [] a; + + 2. At the beginning of a line for slice initialisers:: + + [0...10] = 5, + + 3. Inside a curly brace:: + + = { [0...10] = 5 } + + **CONCATENATED_STRING** + Concatenated elements should have a space in between. + Example:: + + printk(KERN_INFO"bar"); + + should be:: + + printk(KERN_INFO "bar"); + + **ELSE_AFTER_BRACE** + `else {` should follow the closing block `}` on the same line. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **LINE_SPACING** + Vertical space is wasted given the limited number of lines an + editor window can display when multiple blank lines are used. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **OPEN_BRACE** + The opening brace should be following the function definitions on the + next line. For any non-functional block it should be on the same line + as the last construct. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **POINTER_LOCATION** + When using pointer data or a function that returns a pointer type, + the preferred use of * is adjacent to the data name or function name + and not adjacent to the type name. + Examples:: + + char *linux_banner; + unsigned long long memparse(char *ptr, char **retptr); + char *match_strdup(substring_t *s); + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **SPACING** + Whitespace style used in the kernel sources is described in kernel docs. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **TRAILING_WHITESPACE** + Trailing whitespace should always be removed. + Some editors highlight the trailing whitespace and cause visual + distractions when editing files. + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **UNNECESSARY_PARENTHESES** + Parentheses are not required in the following cases: + + 1. Function pointer uses:: + + (foo->bar)(); + + could be:: + + foo->bar(); + + 2. Comparisons in if:: + + if ((foo->bar) && (foo->baz)) + if ((foo == bar)) + + could be:: + + if (foo->bar && foo->baz) + if (foo == bar) + + 3. addressof/dereference single Lvalues:: + + &(foo->bar) + *(foo->bar) + + could be:: + + &foo->bar + *foo->bar + + **WHILE_AFTER_BRACE** + while should follow the closing bracket on the same line:: + + do { + ... + } while(something); + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + +Others +------ + + **CONFIG_DESCRIPTION** + Kconfig symbols should have a help text which fully describes + it. + + **CORRUPTED_PATCH** + The patch seems to be corrupted or lines are wrapped. + Please regenerate the patch file before sending it to the maintainer. + + **CVS_KEYWORD** + Since linux moved to git, the CVS markers are no longer used. + So, CVS style keywords ($Id$, $Revision$, $Log$) should not be + added. + + **DEFAULT_NO_BREAK** + switch default case is sometimes written as "default:;". This can + cause new cases added below default to be defective. + + A "break;" should be added after empty default statement to avoid + unwanted fallthrough. + + **DOS_LINE_ENDINGS** + For DOS-formatted patches, there are extra ^M symbols at the end of + the line. These should be removed. + + **DT_SCHEMA_BINDING_PATCH** + DT bindings moved to a json-schema based format instead of + freeform text. + + See: https://www.kernel.org/doc/html/latest/devicetree/bindings/writing-schema.html + + **DT_SPLIT_BINDING_PATCH** + Devicetree bindings should be their own patch. This is because + bindings are logically independent from a driver implementation, + they have a different maintainer (even though they often + are applied via the same tree), and it makes for a cleaner history in the + DT only tree created with git-filter-branch. + + See: https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters + + **EMBEDDED_FILENAME** + Embedding the complete filename path inside the file isn't particularly + useful as often the path is moved around and becomes incorrect. + + **FILE_PATH_CHANGES** + Whenever files are added, moved, or deleted, the MAINTAINERS file + patterns can be out of sync or outdated. + + So MAINTAINERS might need updating in these cases. + + **MEMSET** + The memset use appears to be incorrect. This may be caused due to + badly ordered parameters. Please recheck the usage. + + **NOT_UNIFIED_DIFF** + The patch file does not appear to be in unified-diff format. Please + regenerate the patch file before sending it to the maintainer. + + **PRINTF_0XDECIMAL** + Prefixing 0x with decimal output is defective and should be corrected. + + **SPDX_LICENSE_TAG** + The source file is missing or has an improper SPDX identifier tag. + The Linux kernel requires the precise SPDX identifier in all source files, + and it is thoroughly documented in the kernel docs. + + See: https://www.kernel.org/doc/html/latest/process/license-rules.html + + **TYPO_SPELLING** + Some words may have been misspelled. Consider reviewing them. diff --git a/doc/manual/config_files.txt b/doc/manual/config_files.txt new file mode 100644 index 0000000000..db1cc14191 --- /dev/null +++ b/doc/manual/config_files.txt @@ -0,0 +1,117 @@ +/** @page config_files Configuration Files + +This page gives an overview of the different configuration files, what purpose they serve and how they are structured. +The goal of this guide is to ensure well-structured and consistent configuration files. + +All configuration files are stored in the @c tcl directory of the project directory. +These files must follow the @ref styletcl and @ref naming_convention. +There are different types of configuration files: + +- @ref interface_configs +- @ref target_configs +- @ref board_configs + +@note This guideline must be followed for new configuration files. +There may be configuration files that do not comply with this guide for legacy reasons. + + +@section interface_configs Interface + +This configuration file represents a debug (interface) adapter. +This is usually a USB device that provides an interface to one or more transports such as JTAG or SWD. +Other interfaces like ethernet or parallel port are also represented. + +A debug adapter configuration file must use the following scheme: + +@verbatim +tcl/interface/[vendor]/<adapter name>.cfg +@endverbatim + +The `vendor` directory for debug adapters is often omitted because multiple adapters from the same vendor can be represented by a common configuration file. +One counter example are FTDI-based debug adapters. +There are various devices, either standalone or development boards which use FTDI chips but use different chip models or settings. +Their corresponding configuration files are stored in the `ftdi` folder. + +The name of the `vendor` folder can also be a more generic term such as `parport` as it is used for parallel port based debug adapters. + +If it is foreseeable that new configuration files will be added in the future, create a `vendor` directory even if there is only a single file at the moment. +This prevents that files have to be moved in the future. + +@section target_configs Target + +This configuration file represents an actual chip. +For example, a microcontroller, FPGA, CPLD, or system on chip (SoC). +A target configuration file always represents an entire device series or family. + +A target configuration file must use the following scheme: + +@verbatim +tcl/target/<vendor>/<target name>.cfg +@endverbatim + +Use the device series or family as `target name`. +For example, the configuration file for the nRF54L series from Nordic Semiconductor is located here: + +@verbatim +tcl/target/nordic/nrf54l.cfg +@endverbatim + +If there are many similarities between different targets, use a common file to share large pieces of code. +Do not use a single file to represent multiple device series or families. + +@section board_configs Board + +This configuration file represents a circuit board, for example, a development board. +A board may also contain an on-board debug adapter. + +A board configuration file includes existing target and, if available, interface configuration files, since a target is used on many boards. + +Reuse existing target and interface configuration files whenever possible. +If a board needs an external debug adapter, do @b not write adapter specific configuration files. + + +A board configuration file must use the following scheme: + +@verbatim +tcl/board/<vendor>/<board name>[-suffix].cfg +@endverbatim + +For example, the board configuration file for the NUCLEO-U083RC from STMicroelectronics is located here: + +@verbatim +tcl/board/st/nucleo-u083rc.cfg +@endverbatim + +In case a board supports different features, a `suffix` can be used to indicate this. +Make sure that the suffix is short and meaningful. + +For example, the on-board debug adapter of the FRDM-KV11Z development board can be flashed with a SEGGER J-Link compatible firmware. +Hence, there is the following configuration file: + +@verbatim +tcl/board/nxp/frdm-kv11z-jlink.cfg +@endverbatim + +The use of a suffix should be chosen carefully. +In many cases it is sufficient to make a certain feature accessible via a variable. + +Use a single configuration file for each board. +If there are many similarities between different boards, use a common file to share large pieces of code. + + +@section naming_convention Naming Convention + + +The following naming conventions for configuration files and directories must be used: + +- Use only lower-case letters and digits for directory and filenames +- Use hyphen characters between consecutive words in identifiers (e.g. `more-than-one-word`) + +- Use a common abbreviation for the vendor name, such as + - @c ti for Texas Instruments + - @c st for STMicroelectronics + - @c silabs for Silicon Labs + +An extensive list of abbreviations for vendor names can be found [here](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/vendor-prefixes.yaml). + + */ diff --git a/doc/manual/endianness.txt b/doc/manual/endianness.txt new file mode 100644 index 0000000000..bba2116b5f --- /dev/null +++ b/doc/manual/endianness.txt @@ -0,0 +1,197 @@ +/** @page endianness About endianness + +OpenOCD has to potentially deal with different endianness between: +- the host PC endianness; +- the data endianness during communication between host and adapter; +- the target CPU endianness. + +The whole OpenOCD code should be written to handle any endianness +mismatch and should run on either little and big endian hosts. + +Big-endian host PC are becoming less and less common since Apple™ has +switched away from big-endian PowerPC™ in favor of little-endian intel +X86™. + +The lack of commercial big-endian hosts makes hard testing OpenOCD correctness +on big-endian hosts. Running OpenOCD on low-cost commercial routers based on +big-endian MIPS is possible, but it's tricky to properly setup the system and +the cross-compiling environment. + +In next sections there are two example on how to compile and test OpenOCD in an +emulated big-endian environment. + + +@section endianness_helpers OpenOCD API for handling endianness + +Use the following OpenOCD API to handle endianness conversions: +- host endianness to/from little endian: + - le_to_h_u64(), le_to_h_u32(), le_to_h_u16(); + - h_u64_to_le(), h_u32_to_le(), h_u16_to_le(); + - buf_get_u32(), buf_get_u64(); + - buf_set_u32(), buf_set_u64(); +- host endianness to/from big endian: + - be_to_h_u64(), be_to_h_u32(), be_to_h_u16(); + - h_u64_to_be(), h_u32_to_be(), h_u16_to_be(); +- host endianness to/from target endianness: + - target_read_u64(), target_read_u32(), target_read_u16(); + - target_write_u64(), target_write_u32(), target_write_u16(); + - target_write_phys_u64(), target_write_phys_u32(), target_write_phys_u16(); + - target_buffer_get_u64(), target_buffer_get_u32(), target_buffer_get_u24(), target_buffer_get_u16(); + - target_buffer_set_u64(), target_buffer_set_u32(), target_buffer_set_u24(), target_buffer_set_u16(); +- byte swap: + - buf_bswap32(), buf_bswap16(). + + +@section endianness_docker Use dockers to run different endianness + + +Docker can run a full Linux image that includes the toolchain through QEMU +emulator. +By selecting a big-endian image, it's possible to compile and execute OpenOCD +in big-endian. +There are, so far, not many options for big-endian images; s390x is one of the +few available. + +To be expanded. + +User should: +- install docker; +- download the big-endian image; +- run the image in docker; +- download, in the image, the OpenOCD code to test; +- recompile OpenOCD code in the image; +- run OpenOCD binary in the image. + +From https://github.com/multiarch/qemu-user-static + + @code{.unparsed} + docker run --rm -t s390x/ubuntu bash + @endcode + + +@section endianness_qemu Use buildroot and QEMU to run different endianness + +QEMU User Mode Emulation is an efficient method to launch, on host's CPU, +applications compiled for another CPU and/or for different endianness. +It works either on Linux and BSD. More info available on +https://www.qemu.org/docs/master/user/index.html + +With QEMU User Mode Emulation is thus possible running, on a commonly available +little-endian X86 Linux host, OpenOCD compiled for a big-endian host. + +The following example will show how to use buildroot to: +- build big-endian toolchain and libraries; +- compile OpenOCD for big-endian; +- run the big-endian OpenOCD on little-endian Linux PC. + +The example will use ARM Cortex-A7 big-endian only because I personally feel +comfortable reading ARM assembly during debug. User can select other CPU +architectures, as this does not impact the result. + +A similar method can be used to test OpenOCD compiled for 32 vs 64 bit host. + +@note +- the version of autotools locally installer in your Linux host can be + incompatible with the version of autotools used by buildroot. This can cause + the build to fail if buildroot has to run its autotools on a partially + configured OpenOCD folder. Use either a clean copy of OpenOCD code in 2., or + run "./bootstrap" in OpenOCD folder to prevent buildroot from using its own + autotools; +- the configuration tool in 4. and 5. matches the version of OpenOCD used by + buildroot. Some new driver could be not listed in. OpenOCD will build every + driver that is not disabled and with satisfied dependencies. If the driver + you plan to use is not listed, try a first build and check OpenOCD with + command "adapter list", then try to hack the buildroot files Config.in and + openocd.mk in folder package/openocd/ and use "make openocd-reconfigure" to + rerun the build starting with configuration; +- using pre-built toolchains, you need 2GB of disk space for buildroot build. + To also rebuild the toolchains you will need ~5GB and much longer time for + the first build (it takes ~2 hour on my crap 10+ years old laptop); +- you need to install few tools for buildroot dependency, listed in + https://buildroot.org/downloads/manual/manual.html#requirement ; +- you need to install qemu-armeb. On Arch Linux it's in package qemu-arch-extra; + on Ubuntu/debian it's packaged in qemu-user. + Buildroot can also be configured to build qemu for the host, if you prefer, + by enabling BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE, but this takes longer + compile time; +- don't use qemu-system-arm, as it emulates a complete system and requires a + fully bootable ARM image; +- while QEMU User Mode Emulation is available for both Linux and BSD, buildroot + only builds binaries for Linux target. This example can only be used with + Linux hosts emulating the Linux target. + + +Steps to run big-endian OpenOCD on little-endian host Linux PC: + +1. Get buildroot source. Today's latest version is "2022.02": + @code{.unparsed} + wget https://buildroot.org/downloads/buildroot-2022.02.tar.xz + tar xf buildroot-2022.02.tar.xz + cd buildroot-2022.02 + @endcode + +2. Override the source repo for OpenOCD in order to build your own code version + in place of the default OpenOCD release version: + @code{.unparsed} + echo OPENOCD_OVERRIDE_SRCDIR=/home/me/openocd.git >> local.mk + @endcode + +3. Copy default config for OpenOCD big-endian. This used: + - ARM Cortex-A7 big-endian target, + - external Linaro armeb toolchain (to speed up first build), + - OpenOCD all configure options enabled. + + @code{.unparsed} + cp $OPENOCD_OVERRIDE_SRCDIR/contrib/buildroot/openocd_be_defconfig configs/ + @endcode + +4. Configure buildroot with default config for OpenOCD big-endian: + @code{.unparsed} + make openocd_be_defconfig + @endcode + +5. Optional, change buildroot configuration: + @code{.unparsed} + make menuconfig + @endcode + These are the options selected with default config for OpenOCD big-endian: + @code{.unparsed} + Target options ---> + Target Architecture ---> + ARM (big endian) + Target Architecture Variant ---> + cortex-A7 + Toolchain ---> + Toolchain type ---> + External toolchain + Toolchain ---> + Linaro armeb 2018.05 + Toolchain origin ---> + Toolchain to be downloaded and installed + Target packages ---> + Hardware handling ---> + openocd + All adapters selected + @endcode + Save and exit + +6. Build (and take a long coffee break ...): + @code{.unparsed} + make openocd + @endcode + +7. Execute big-endian OpenOCD: + @code{.unparsed} + cd output/target + qemu-armeb -cpu cortex-a7 -L . usr/bin/openocd -s usr/share/openocd/scripts/ -f board/st_nucleo_f4.cfg + @endcode + +8. Optional, to rebuild after any source code modification in ${OPENOCD_OVERRIDE_SRCDIR}: + @code{.unparsed} + make openocd-rebuild + @endcode + + */ +/** @file +This file contains the @ref endianness page. + */ diff --git a/doc/manual/helper.txt b/doc/manual/helper.txt index d5710ddde8..29e84e6f0b 100644 --- a/doc/manual/helper.txt +++ b/doc/manual/helper.txt @@ -21,7 +21,7 @@ portability API. /** @page helperjim OpenOCD Jim API -The Jim API provides access to a small-footprint TCL implementation. +The Jim API provides access to a small-footprint Tcl implementation. Visit http://jim.tcl.tk/ for more information on Jim. @@ -79,6 +79,8 @@ command handlers and helpers: - @c CMD_NAME - invoked command name - @c CMD_ARGC - the number of command arguments - @c CMD_ARGV - array of command argument strings +- @c CMD_JIMTCL_ARGV - array containing the Jim_Obj equivalent of command + argument in @c CMD_ARGV. @section helpercmdregister Command Registration @@ -95,18 +97,6 @@ registration, while the @c unregister_command() and These may be called at any time, allowing the command set to change in response to system actions. -@subsection helpercmdjim Jim Command Registration - -The command_registration structure provides support for registering -native Jim command handlers (@c jim_handler) too. For these handlers, -the module can provide help and usage support; however, this mechanism -allows Jim handlers to be called as sub-commands of other commands. -These commands may be registered with a private data value (@c -jim_handler_data) that will be available when called, as with low-level -Jim command registration. - -A command may have a normal @c handler or a @c jim_handler, but not both. - @subsection helpercmdregisterchains Command Chaining When using register_commands(), the array of commands may reference diff --git a/doc/manual/jtag.txt b/doc/manual/jtag.txt index 2653fc78f5..5eb945013b 100644 --- a/doc/manual/jtag.txt +++ b/doc/manual/jtag.txt @@ -15,7 +15,7 @@ asynchronous transactions. - used by other modules - @subpage jtagtcl - - @b private TCL handling routines + - @b private Tcl handling routines - defined in @c src/jtag/tcl.c - registers and handles Jim commands that configure and use the JTAG core @@ -47,7 +47,7 @@ This section needs to be expanded. */ -/** @page jtagtcl JTAG TCL API +/** @page jtagtcl JTAG Tcl API This section needs to be expanded. diff --git a/doc/manual/jtag/drivers/remote_bitbang.txt b/doc/manual/jtag/drivers/remote_bitbang.txt index f394d736af..8316cb0dd5 100644 --- a/doc/manual/jtag/drivers/remote_bitbang.txt +++ b/doc/manual/jtag/drivers/remote_bitbang.txt @@ -1,15 +1,19 @@ /** @remote_bitbangpage OpenOCD Developer's Guide -The remote_bitbang JTAG driver is used to drive JTAG from a remote process. The -remote_bitbang driver communicates via TCP or UNIX sockets with some remote -process using an ASCII encoding of the bitbang interface. The remote process -presumably then drives the JTAG however it pleases. The remote process should -act as a server, listening for connections from the openocd remote_bitbang -driver. +The remote_bitbang JTAG+SWD driver is used to drive JTAG and/or SWD from a +remote process. The remote_bitbang driver communicates via TCP or UNIX +sockets with some remote process using an ASCII encoding of the bitbang +interface. The remote process presumably then drives the JTAG/SWD however +it pleases. The remote process should act as a server, listening for +connections from the openocd remote_bitbang driver. The remote bitbang driver is useful for debugging software running on processors which are being simulated. +There also is an implementation of the server-side protocol for the +Glasgow Debug Tool (https://github.com/glasgowEmbedded/Glasgow) through +the jtag-openocd applet. + The bitbang interface consists of the following functions. blink on @@ -24,12 +28,25 @@ write tck tms tdi reset trst srst Set the value of trst, srst. +swdio_drive + Set the output enable of the bidirectional swdio (tms) pin + +swdio_read + Sample the value of swdio (tms). + +swd_write + Set the value of swclk (tck) and swdio (tms). + +(optional) sleep + Instructs the remote host to sleep/idle for some period of time before + executing the next request + An additional function, quit, is added to the remote_bitbang interface to indicate there will be no more requests and the connection with the remote driver should be closed. -These five functions are encoded in ASCII by assigning a single character to -each possible request. The assignments are: +The eight mandatory functions are encoded in ASCII by assigning a single +character to each possible request. The assignments are: B - Blink on b - Blink off @@ -47,7 +64,25 @@ each possible request. The assignments are: s - Reset 0 1 t - Reset 1 0 u - Reset 1 1 + O - SWDIO drive 1 + o - SWDIO drive 0 + c - SWDIO read request + d - SWD write 0 0 + e - SWD write 0 1 + f - SWD write 1 0 + g - SWD write 1 1 + +The read responses are encoded in ASCII as either digit 0 or 1. + +If the use_remote_sleep option is set to 'yes', two additional requests may +be sent: + + Z - Sleep for 1 millisecond + z - Sleep for 1 microsecond + +NOTE: Previously these were specified as 'D' and 'd', which conflicts with the +"SWD write 0 0" command defined above. Adapters that implement Dd for remote +sleep must be updated to work with Zz. -The read response is encoded in ASCII as either digit 0 or 1. */ diff --git a/doc/manual/main.txt b/doc/manual/main.txt index 14c64c2e76..9da546b6d2 100644 --- a/doc/manual/main.txt +++ b/doc/manual/main.txt @@ -19,6 +19,10 @@ check the mailing list archives to find the status of your feature (or bug). - The @subpage bugs page contains the content of the BUGS file, which provides instructions for submitting bug reports to the maintainers. - The @subpage releases page describes the project's release process. +- The @subpage endianness provides hints about writing and testing + endianness independent code for OpenOCD. +- The @subpage config_files page provides a guide for writing configuration files + for OpenOCD. @ref primer provide introductory materials for new developers on various specific topics. diff --git a/doc/manual/primer/docs.txt b/doc/manual/primer/docs.txt index b1c0531375..1aefa17e6d 100644 --- a/doc/manual/primer/docs.txt +++ b/doc/manual/primer/docs.txt @@ -6,7 +6,7 @@ OpenOCD presently produces several kinds of documentation: - The User's Guide: - Focuses on using the OpenOCD software. - Details the installation, usage, and customization. - - Provides descriptions of public Jim/TCL script commands. + - Provides descriptions of public Jim Tcl script commands. - Written using GNU texinfo. - Created with 'make pdf' or 'make html'. - See @subpage primertexinfo and @ref styletexinfo. diff --git a/doc/manual/primer/tcl.txt b/doc/manual/primer/tcl.txt index eba2f552d0..6874f5566c 100644 --- a/doc/manual/primer/tcl.txt +++ b/doc/manual/primer/tcl.txt @@ -1,6 +1,6 @@ -/** @page primertcl OpenOCD TCL Primer +/** @page primertcl OpenOCD Tcl Primer -The @subpage scripting page provides additional TCL Primer material. +The @subpage scripting page provides additional Tcl Primer material. @verbatim @@ -8,15 +8,15 @@ The @subpage scripting page provides additional TCL Primer material. **************************************** This is a short introduction to 'un-scare' you about the language -known as TCL. It is structured as a guided tour through the files +known as Tcl. It is structured as a guided tour through the files written by me [Duane Ellis] - in early July 2008 for OpenOCD. Which uses the "JIM" embedded Tcl clone-ish language. -Thing described here are *totally* TCL generic... not Jim specific. +Thing described here are *totally* Tcl generic... not Jim specific. The goal of this document is to encourage you to add your own set of -chips to the TCL package - and most importantly you should know where +chips to the Tcl package - and most importantly you should know where you should put them - so they end up in an organized way. --Duane Ellis. @@ -57,14 +57,14 @@ Definition: Open: at91sam7x256.tcl === TCL TOUR === -A walk through --- For those who are new to TCL. +A walk through --- For those who are new to Tcl. Examine the file: at91sam7x256.tcl It starts with: source [find path/filename.tcl] -In TCL - this is very important. +In Tcl - this is very important. Rule #1 Everything is a string. Rule #2 If you think other wise See #1. @@ -130,7 +130,7 @@ First, there is a "for" loop - at level 0 This means it is evaluated when the file is parsed. == SIDEBAR: About The FOR command == -In TCL, "FOR" is a funny thing, it is not what you think it is. +In Tcl, "FOR" is a funny thing, it is not what you think it is. Syntactically - FOR is a just a command, it is not language construct like for(;;) in C... @@ -191,7 +191,7 @@ proc create_mask { MSB LSB } { Like "for" - PROC is really just a command that takes 3 parameters. The (1) NAME of the function, a (2) LIST of parameters, and a (3) BODY -Again, this is at "level 0" so it is a global function. (Yes, TCL +Again, this is at "level 0" so it is a global function. (Yes, Tcl supports local functions, you put them inside of a function} You'll see in some cases, I nest [brackets] a lot and in others I'm @@ -257,7 +257,7 @@ For example - 'show_mmr32_reg' is given the NAME of the register to display. The assumption is - the NAME is a global variable holding the address of that MMR. -The code does some tricks. The [set [set NAME]] is the TCL way +The code does some tricks. The [set [set NAME]] is the Tcl way of doing double variable interpolation - like makefiles... In a makefile or shell script you may have seen this: @@ -272,7 +272,7 @@ In a makefile or shell script you may have seen this: #BUILD = mac FOO = ${FOO_${BUILD}} -The "double [set] square bracket" thing is the TCL way, nothing more. +The "double [set] square bracket" thing is the Tcl way, nothing more. ---- @@ -352,7 +352,7 @@ tricks with interpretors. Function: show_mmr32_bits() -In this case, we use the special TCL command "upvar" which tcl's way +In this case, we use the special Tcl command "upvar" which is the Tcl way of passing things by reference. In this case, we want to reach up into the callers lexical scope and find the array named "NAMES" @@ -373,7 +373,7 @@ are basically identical... Second - there can be many of them. -In this case - I do some more TCL tricks to dynamically +In this case - I do some more Tcl tricks to dynamically create functions out of thin air. Some assumptions: @@ -409,7 +409,7 @@ And - declare that variable as GLOBAL so the world can find it. Then - we dynamically create a function - based on the register name. Look carefully at how that is done. You'll notice the FUNCTION BODY is -a string - not something in {braces}. Why? This is because we need TCL +a string - not something in {braces}. Why? This is because we need Tcl to evaluate the contents of that string "*NOW*" - when $vn exists not later, when the function "show_FOO" is invoked. diff --git a/doc/manual/scripting.txt b/doc/manual/scripting.txt index f8764e2d7c..48ba99bdaa 100644 --- a/doc/manual/scripting.txt +++ b/doc/manual/scripting.txt @@ -4,11 +4,11 @@ The scripting support is intended for developers of OpenOCD. It is not the intention that normal OpenOCD users will -use tcl scripting extensively, write lots of clever scripts, +use Tcl scripting extensively, write lots of clever scripts, or contribute back to OpenOCD. Target scripts can contain new procedures that end users may -tinker to their needs without really understanding tcl. +tinker to their needs without really understanding Tcl. Since end users are not expected to mess with the scripting language, the choice of language is not terribly important @@ -38,16 +38,16 @@ Default implementation of procedures in tcl/procedures.tcl. and will have no externally visible consequences. Tcl has an advantage in that it's syntax is backwards compatible with the current OpenOCD syntax. -- external scripting. Low level tcl functions will be defined - that return machine readable output. These low level tcl - functions constitute the tcl api. flash_banks is such - a low level tcl proc. "flash banks" is an example of +- external scripting. Low level Tcl functions will be defined + that return machine readable output. These low level Tcl + functions constitute the Tcl api. flash_banks is such + a low level Tcl proc. "flash banks" is an example of a command that has human readable output. The human readable output is expected to change in between versions of OpenOCD. The output from flash_banks may not be in the preferred form for the client. The client then has two choices a) parse the output from flash_banks - or b) write a small piece of tcl to output the + or b) write a small piece of Tcl to output the flash_banks output to a more suitable form. The latter may be simpler. diff --git a/doc/manual/server.txt b/doc/manual/server.txt index 8041c3df3d..20e48c1f43 100644 --- a/doc/manual/server.txt +++ b/doc/manual/server.txt @@ -43,7 +43,7 @@ with a script language: What follows hopefully shows how the plans to solve these problems materialized and help to explain the grand roadmap plan. -@subsection serverdocsjim Why JimTCL? The Internal Script Language +@subsection serverdocsjim Why Jim Tcl? The Internal Script Language At the time, the existing "command context schema" was proving itself insufficient. However, the problem was also considered from another @@ -57,14 +57,14 @@ OpenOCD. Yuck. OpenOCD already has a complex enough build system, why make it worse? The goal was to add a simple language that would be moderately easy to -work with and be self-contained. JimTCL is a single C and single H +work with and be self-contained. Jim Tcl is a single C and single H file, allowing OpenOCD to avoid the spider web of dependent packages. -@section serverdocstcl TCL Server Port +@section serverdocstcl Tcl Server Port -The TCL Server port was added in mid-2008. With embedded TCL, we can +The Tcl Server port was added in mid-2008. With embedded Tcl, we can write scripts internally to help things, or we can write "C" code that -interfaces well with TCL. +interfaces well with Tcl. From there, the developers wanted to create an external front-end that would be @a very usable and that @a any language could utilize, @@ -78,7 +78,7 @@ also support a high degree of interoperability with multiple systems. They are not human-centric protocols; more correctly, they are rigid, terse, simple ASCII protocols that are easily parsable by a script. -Thus, the TCL server -- a 'machine' type socket interface -- was added +Thus, the Tcl server -- a 'machine' type socket interface -- was added with the hope was it would output simple "name-value" pair type data. At the time, simple name/value pairs seemed reasonably easier to do at the time, though Maybe it should output JSON; @@ -107,7 +107,7 @@ What works easier and is less work is what is already present in every platform? The answer: A web browser. In other words, OpenOCD could serve out embedded web pages via "localhost" to your browser. -Long before OpenOCD had a TCL command line, Zylin AS built their ZY1000 +Long before OpenOCD had a Tcl command line, Zylin AS built their ZY1000 device with a built-in HTTP server. Later, they were willing to both contribute and integrate most of that work into the main tree. @@ -128,8 +128,8 @@ every language has it's own set of wack-ness, parameter marshaling is painful. What about "callbacks" and structures, and other mess. Imagine -debugging that system. When JimTCL was introduced Spencer Oliver had -quite a few well-put concerns (Summer 2008) about the idea of "TCL" +debugging that system. When Jim Tcl was introduced Spencer Oliver had +quite a few well-put concerns (Summer 2008) about the idea of "Tcl" taking over OpenOCD. His concern is and was: how do you debug something written in 2 different languages? A "SWIG" front-end is unlikely to help that situation. @@ -143,7 +143,7 @@ to Localhost or remote host, however one might want to make it work. A socket interface is very simple. One could write a Java application and serve it out via the embedded web server, could it - or something -like it talk to the built in TCL server? Yes, absolutely! We are on to +like it talk to the built in Tcl server? Yes, absolutely! We are on to something here. @subsection serverdocplatforms Platform Permutations @@ -167,9 +167,9 @@ the Socket Approach is used. @subsection serverdocfuture Development Scale Out -During 2008, Duane Ellis created some TCL scripts to display peripheral -register contents. For example, look at the sam7 TCL scripts, and the -stm32 TCL scripts. The hope was others would create more. +During 2008, Duane Ellis created some Tcl scripts to display peripheral +register contents. For example, look at the sam7 Tcl scripts, and the +stm32 Tcl scripts. The hope was others would create more. A good example of this is display/view the peripheral registers on @@ -208,7 +208,7 @@ upon it, sometimes that is the only scheme available. As a small group of developers, supporting all the platforms and targets in the debugger will be difficult, as there are enough problem with the plethora of Adapters, Chips, and different target boards. -Yes, the TCL interface might be suitable, but it has not received much +Yes, the Tcl interface might be suitable, but it has not received much love or attention. Perhaps it will after you read and understand this. One reason might be, this adds one more host side requirement to make @@ -247,8 +247,8 @@ Altogether, it provides a universally accessible GUI for OpenOCD. @section serverdocshtml Simple HTML Pages -There is (or could be) a simple "Jim TCL" function to read a memory -location. If that can be tied into a TCL script that can modify the +There is (or could be) a simple "Jim Tcl" function to read a memory +location. If that can be tied into a Tcl script that can modify the HTTP text, then we have a simple script-based web server with a JTAG engine under the hood. @@ -275,7 +275,7 @@ bit-banging JTAG Adapter serving web pages. @subsection serverdocshtmladv Advanced HTML Pages -Java or JavaScript could be used to talk back to the TCL port. One +Java or JavaScript could be used to talk back to the Tcl port. One could write a Java, AJAX, FLASH, or some other developer friendly toolbox and get a real cross-platform GUI interface. Sure, the interface is not native - but it is 100% cross-platform! diff --git a/doc/manual/style.txt b/doc/manual/style.txt index 58f39807e2..f7a12988fc 100644 --- a/doc/manual/style.txt +++ b/doc/manual/style.txt @@ -27,12 +27,12 @@ providing documentation, either as part of the C code or stand-alone. Feedback would be welcome to improve the OpenOCD guidelines. */ -/** @page styletcl TCL Style Guide +/** @page styletcl Tcl Style Guide -OpenOCD needs to expand its Jim/TCL Style Guide. +OpenOCD needs to expand its Jim Tcl Style Guide. Many of the guidelines listed on the @ref stylec page should apply to -OpenOCD's Jim/TCL code as well. +OpenOCD's Jim Tcl code as well. */ /** @page stylec C Style Guide @@ -97,6 +97,21 @@ OpenOCD project. x = 0; } @endcode +- on <tt> if </tt> statements where the condition is split among multiple + lines, increase the indentation of the condition to prevent it to match + to the indentation of the <tt> then </tt> block due to length of 'if (' + being same of the TAB width of 4 characters. Use: + @code + if (CMD_ARGC < 3 + || CMD_ARGC > 8) + return ERROR_COMMAND_SYNTAX_ERROR; + @endcode + instead of: + @code + if (CMD_ARGC < 3 || + CMD_ARGC > 8) + return ERROR_COMMAND_SYNTAX_ERROR; + @endcode Finally, try to avoid lines of code that are longer than 72-80 columns: @@ -111,8 +126,8 @@ Finally, try to avoid lines of code that are longer than 72-80 columns: @section stylenames Naming Rules - most identifiers must use lower-case letters (and digits) only. - - macros must use upper-case letters (and digits) only. - - OpenOCD identifiers should NEVER use @c MixedCaps. + - macros and enumerators must use upper-case letters (and digits) only. + - OpenOCD identifiers should NEVER use @c MixedCaps, aka @c CamelCase. - @c typedef names must end with the '_t' suffix. - This should be reserved for types that should be passed by value. - Do @b not mix the typedef keyword with @c struct. @@ -210,6 +225,21 @@ if (!buf) { } @endcode +@section stylelogging Logging + +Logging is intended to provide human-readable information to users. +Do not confuse logging with the output of commands. +The latter is intended for the result of a command and should be able to be processed by Tcl scripts. + + - Use one of the following functions to generate log messages, never use `printf()` or similar functions. + - Use `LOG_ERROR()` to provide information in case an operation failed in an unrecoverable way. For example, if necessary memory cannot be allocated. + - Use `LOG_WARNING()` to inform the user of about an unexpected behavior that can be handled and the intended operation is still be performed. For example, in case a command is deprecated but is nevertheless executed. + - Use `LOG_INFO()` to provide insightful or necessary information to the user. For example, features or capabilities of a discovered target. + - Use `LOG_DEBUG()` to provide information for troubleshooting. For example, detailed information which makes it easier to debug a specific operation. Try to avoid flooding the log with frequently generated messages. For example, do not use LOG_DEBUG() in operations used for polling the target. Use LOG_DEBUG_IO() for such frequent messages. + - Use `LOG_DEBUG_IO()` to provide I/O related information for troubleshooting. For example, details about the communication between OpenOCD and a debug adapter. + - If the log message is related to a target, use the corresponding `LOG_TARGET_xxx()` functions. + - Do not use a period or exclamation mark at the end of a message. + */ /** @page styledoxygen Doxygen Style Guide diff --git a/doc/openocd.1 b/doc/openocd.1 index 4278486e5d..34ec7617d1 100644 --- a/doc/openocd.1 +++ b/doc/openocd.1 @@ -1,24 +1,21 @@ -.TH "OPENOCD" "1" "November 24, 2009" +.TH "OPENOCD" "1" "June 18, 2024" .SH "NAME" openocd \- A free and open on\-chip debugging, in\-system programming and -boundary\-scan testing tool for ARM and MIPS systems +boundary\-scan testing tool for microcontrollers and other embedded devices .SH "SYNOPSIS" -.B openocd \fR[\fB\-fsdlcphv\fR] [\fB\-\-file\fR <filename>] [\fB\-\-search\fR <dirname>] [\fB\-\-debug\fR <debuglevel>] [\fB\-\-log_output\fR <filename>] [\fB\-\-command\fR <cmd>] [\fB\-\-pipe\fR] [\fB\-\-help\fR] [\fB\-\-version\fR] +.B openocd \fR[\fB\-fsdlchv\fR] [\fB\-\-file\fR <filename>] [\fB\-\-search\fR <dirname>] [\fB\-\-debug\fR <debuglevel>] [\fB\-\-log_output\fR <filename>] [\fB\-\-command\fR <cmd>] [\fB\-\-help\fR] [\fB\-\-version\fR] .SH "DESCRIPTION" .B OpenOCD is an on\-chip debugging, in\-system programming and boundary\-scan -testing tool for various ARM and MIPS systems. +testing tool for various microcontrollers and other embedded devices. .PP -The debugger uses an IEEE 1149\-1 compliant JTAG TAP bus master to access -on\-chip debug functionality available on ARM based microcontrollers or -system-on-chip solutions. For MIPS systems the EJTAG interface is supported. +Various different types of debug adapters as well as transport protocols like +JTAG and SWD are supported by OpenOCD, please check the \fIopenocd\fR info page +for the complete list. .PP User interaction is realized through a telnet command line interface, a gdb (the GNU debugger) remote protocol server, and a simplified RPC connection that can be used to interface with OpenOCD's Jim Tcl engine. -.PP -OpenOCD supports various different types of JTAG interfaces/programmers, -please check the \fIopenocd\fR info page for the complete list. .SH "OPTIONS" .TP .B "\-f, \-\-file <filename>" @@ -68,8 +65,6 @@ Note that you will need to explicitly invoke .I init if the command requires access to a target or flash. .TP -.B "\-p, \-\-pipe" -Use pipes when talking to gdb. .TP .B "\-h, \-\-help" Show a help text and exit. @@ -82,8 +77,6 @@ Please report any bugs on the mailing list at .SH "LICENCE" .B OpenOCD is covered by the GNU General Public License (GPL), version 2 or later. -.SH "SEE ALSO" -.BR jtag (1) .PP The full documentation for .B openocd diff --git a/doc/openocd.texi b/doc/openocd.texi index b213798c31..6d607d697f 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -19,7 +19,7 @@ dated @value{UPDATED}, of the Open On-Chip Debugger (OpenOCD). @itemize @bullet -@item Copyright @copyright{} 2008 The OpenOCD Project +@item Copyright @copyright{} 2008-2022 The OpenOCD Project @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk} @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com} @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com} @@ -62,7 +62,7 @@ Documentation License''. * About:: About OpenOCD * Developers:: OpenOCD Developer Resources * Debug Adapter Hardware:: Debug Adapter Hardware -* About Jim-Tcl:: About Jim-Tcl +* About Jim Tcl:: About Jim Tcl * Running:: Running OpenOCD * OpenOCD Project Setup:: OpenOCD Project Setup * Config File Guidelines:: Config File Guidelines @@ -399,8 +399,7 @@ to be available anymore as of April 2012. @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based @item @b{GW16042} -@* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64} -FT2232H-based +@* Link: @url{https://www.gateworks.com/} FT2232H-based @end itemize @section USB-JTAG / Altera USB-Blaster compatibles @@ -442,7 +441,7 @@ SWD and not JTAG, thus not supported. @itemize @bullet @item @b{Raisonance RLink} -@* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html} +@* Link: @url{https://www.raisonance.com/rlink.html} @item @b{STM32 Primer} @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php} @item @b{STM32 Primer2} @@ -463,6 +462,12 @@ They only work with STMicroelectronics chips, notably STM32 and STM8. @item @b{STLINK-V3} @* This is available standalone and as part of some kits. @* Link: @url{http://www.st.com/stlink-v3} +@item @b{STLINK-V3PWR} +@* This is available standalone. +Beside the debugger functionality, the probe includes a SMU (source +measurement unit) aimed at analyzing power consumption during code +execution. The SMU is not supported by OpenOCD. +@* Link: @url{http://www.st.com/stlink-v3pwr} @end itemize For info the original ST-LINK enumerates using the mass storage usb class; however, @@ -502,6 +507,9 @@ debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/ @item @b{ARM-JTAG-EW} @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html} +@item @b{angie} +@* Link: @url{https://nanoxplore.org/} + @item @b{Buspirate} @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/} @@ -594,8 +602,8 @@ produced, PDF schematics are easily found and it is easy to make. @item @b{vdebug} @* A driver for Cadence virtual Debug Interface to emulated or simulated targets. It implements a client connecting to the vdebug server, which in turn communicates -with the emulated or simulated RTL model through a transactor. The current version -supports only JTAG as a transport, but other virtual transports, like DAP are planned. +with the emulated or simulated RTL model through a transactor. The driver supports +JTAG and DAP-level transports. @item @b{jtag_dpi} @* A JTAG driver acting as a client for the SystemVerilog Direct Programming @@ -606,6 +614,9 @@ emulation model of target hardware. @item @b{xlnx_pcie_xvc} @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface. +@item @b{linuxspidev} +@* A SPI based SWD driver using Linux SPI devices. + @item @b{linuxgpiod} @* A bitbang JTAG driver using Linux GPIO through library libgpiod. @@ -618,43 +629,43 @@ This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}. @end itemize -@node About Jim-Tcl -@chapter About Jim-Tcl -@cindex Jim-Tcl +@node About Jim Tcl +@chapter About Jim Tcl +@cindex Jim Tcl @cindex tcl -OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl. +OpenOCD uses a small ``Tcl Interpreter'' known as Jim Tcl. This programming language provides a simple and extensible command interpreter. -All commands presented in this Guide are extensions to Jim-Tcl. +All commands presented in this Guide are extensions to Jim Tcl. You can use them as simple commands, without needing to learn much of anything about Tcl. Alternatively, you can write Tcl programs with them. You can learn more about Jim at its website, @url{http://jim.tcl.tk}. There is an active and responsive community, get on the mailing list -if you have any questions. Jim-Tcl maintainers also lurk on the +if you have any questions. Jim Tcl maintainers also lurk on the OpenOCD mailing list. @itemize @bullet @item @b{Jim vs. Tcl} -@* Jim-Tcl is a stripped down version of the well known Tcl language, -which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far -fewer features. Jim-Tcl is several dozens of .C files and .H files and +@* Jim Tcl is a stripped down version of the well known Tcl language, +which can be found here: @url{http://www.tcl.tk}. Jim Tcl has far +fewer features. Jim Tcl is several dozens of .C files and .H files and implements the basic Tcl command set. In contrast: Tcl 8.6 is a 4.2 MB .zip file containing 1540 files. @item @b{Missing Features} @* Our practice has been: Add/clone the real Tcl feature if/when -needed. We welcome Jim-Tcl improvements, not bloat. Also there -are a large number of optional Jim-Tcl features that are not +needed. We welcome Jim Tcl improvements, not bloat. Also there +are a large number of optional Jim Tcl features that are not enabled in OpenOCD. @item @b{Scripts} -@* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's +@* OpenOCD configuration scripts are Jim Tcl Scripts. OpenOCD's command interpreter today is a mixture of (newer) -Jim-Tcl commands, and the (older) original command interpreter. +Jim Tcl commands, and the (older) original command interpreter. @item @b{Commands} @* At the OpenOCD telnet command line (or via the GDB monitor command) one @@ -663,10 +674,10 @@ Some of the commands documented in this guide are implemented as Tcl scripts, from a @file{startup.tcl} file internal to the server. @item @b{Historical Note} -@* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010, -before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl -as a Git submodule, which greatly simplified upgrading Jim-Tcl -to benefit from new features and bugfixes in Jim-Tcl. +@* Jim Tcl was introduced to OpenOCD in spring 2008. Fall 2010, +before OpenOCD 0.5 release, OpenOCD switched to using Jim Tcl +as a Git submodule, which greatly simplified upgrading Jim Tcl +to benefit from new features and bugfixes in Jim Tcl. @item @b{Need a crash course in Tcl?} @*@xref{Tcl Crash Course}. @@ -785,7 +796,7 @@ those channels. If you are having problems, you can enable internal debug messages via the @option{-d} option. -Also it is possible to interleave Jim-Tcl commands w/config scripts using the +Also it is possible to interleave Jim Tcl commands w/config scripts using the @option{-c} command line switch. To enable debug output (when reporting problems or working on OpenOCD @@ -922,8 +933,8 @@ a board with an Atmel AT91SAM7X256 microcontroller: source [find interface/ftdi/signalyzer.cfg] # GDB can also flash my flash! -gdb_memory_map enable -gdb_flash_program enable +gdb memory_map enable +gdb flash_program enable source [find target/sam7x256.cfg] @end example @@ -932,8 +943,8 @@ Here is the command line equivalent of that configuration: @example openocd -f interface/ftdi/signalyzer.cfg \ - -c "gdb_memory_map enable" \ - -c "gdb_flash_program enable" \ + -c "gdb memory_map enable" \ + -c "gdb flash_program enable" \ -f target/sam7x256.cfg @end example @@ -951,7 +962,7 @@ that can be tested in a later script. @end quotation Here we will focus on the simpler solution: one user config -file, including basic configuration plus any TCL procedures +file, including basic configuration plus any Tcl procedures to simplify your work. @section User Config Files @@ -1371,11 +1382,11 @@ Read the OpenOCD source code (and Developer's Guide) if you have a new kind of hardware interface and need to provide a driver for it. -@deffn {Command} {find} 'filename' +@deffn {Command} {find} filename Prints full path to @var{filename} according to OpenOCD search rules. @end deffn -@deffn {Command} {ocd_find} 'filename' +@deffn {Command} {ocd_find} filename Prints full path to @var{filename} according to OpenOCD search rules. This is a low level function used by the @command{find}. Usually you want to use @command{find}, instead. @@ -1421,7 +1432,7 @@ In addition to target-specific utility code, another way that board and target config files communicate is by following a convention on how to use certain variables. -The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not. +The full Tcl/Tk language supports ``namespaces'', but Jim Tcl does not. Thus the rule we follow in OpenOCD is this: Variables that begin with a leading underscore are temporary in nature, and can be modified and used at will within a target configuration file. @@ -1541,7 +1552,7 @@ configuration files for other JTAG tools Some of this code could probably be shared between different boards. For example, setting up a DRAM controller often doesn't differ by much except the bus width (16 bits or 32?) and memory timings, so a -reusable TCL procedure loaded by the @file{target.cfg} file might take +reusable Tcl procedure loaded by the @file{target.cfg} file might take those as parameters. Similarly with oscillator, PLL, and clock setup; and disabling the watchdog. @@ -1785,7 +1796,6 @@ $_TARGETNAME configure -work-area-phys 0x00200000 \ -work-area-size 0x4000 -work-area-backup 0 @end example -@anchor{definecputargetsworkinginsmp} @subsection Define CPU targets working in SMP @cindex SMP After setting targets, you can define a list of targets working in SMP. @@ -1939,7 +1949,6 @@ For an example of this scheme see LPC2000 target config files. The @code{init_boards} procedure is a similar concept concerning board config files (@xref{theinitboardprocedure,,The init_board procedure}.) -@anchor{theinittargeteventsprocedure} @subsection The init_target_events procedure @cindex init_target_events procedure @@ -2128,7 +2137,7 @@ corresponding subsystems: @end deffn At last, @command{init} executes all the commands that are specified in -the TCL list @var{post_init_commands}. The commands are executed in the +the Tcl list @var{post_init_commands}. The commands are executed in the same order they occupy in the list. If one of the commands fails, then the error is propagated and OpenOCD fails too. @example @@ -2173,15 +2182,16 @@ only during configuration (before those ports are opened). For reasons including security, you may wish to prevent remote access using one or more of these ports. In such cases, just specify the relevant port number as "disabled". -If you disable all access through TCP/IP, you will need to -use the command line @option{-pipe} option. -@anchor{gdb_port} -@deffn {Config Command} {gdb_port} [number] +You can request the operating system to select one of the available +ports for the server by specifying the relevant port number as "0". + +@anchor{gdb port} +@deffn {Config Command} {gdb port} [number] @cindex GDB server Normally gdb listens to a TCP/IP port, but GDB can also communicate via pipes(stdin/out or named pipes). The name -"gdb_port" stuck because it covers probably more than 90% of +"gdb port" stuck because it covers probably more than 90% of the normal use cases. No arguments reports GDB port. "pipe" means listen to stdin @@ -2196,7 +2206,7 @@ Output pipe is the same name as input pipe, but with 'o' appended, e.g. /var/gdb, /var/gdbo. The GDB port for the first target will be the base port, the -second target will listen on gdb_port + 1, and so on. +second target will listen on port + 1, and so on. When not specified during the configuration stage, the port @var{number} defaults to 3333. When @var{number} is not a numeric value, incrementing it to compute @@ -2205,14 +2215,14 @@ the next port number does not work. In this case, specify the proper commands @command{target create} or @command{$target_name configure}. @xref{gdbportoverride,,option -gdb-port}. -Note: when using "gdb_port pipe", increasing the default remote timeout in +Note: when using "gdb port pipe", increasing the default remote timeout in gdb (with 'set remotetimeout') is recommended. An insufficient timeout may cause initialization to fail with "Unknown remote qXfer reply: OK". @end deffn -@deffn {Config Command} {tcl_port} [number] +@deffn {Config Command} {tcl port} [number] Specify or query the port used for a simplified RPC -connection that can be used by clients to issue TCL commands and get the +connection that can be used by clients to issue Tcl commands and get the output from the Tcl engine. Intended as a machine interface. When not specified during the configuration stage, @@ -2220,10 +2230,10 @@ the port @var{number} defaults to 6666. When specified as "disabled", this service is not activated. @end deffn -@deffn {Config Command} {telnet_port} [number] +@deffn {Config Command} {telnet port} [number] Specify or query the port on which to listen for incoming telnet connections. -This port is intended for interaction with one human through TCL commands. +This port is intended for interaction with one human through Tcl commands. When not specified during the configuration stage, the port @var{number} defaults to 4444. When specified as "disabled", this service is not activated. @@ -2239,7 +2249,7 @@ The ones listed here are static and global. @xref{targetevents,,Target Events}, about configuring target-specific event handling. @anchor{gdbbreakpointoverride} -@deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}] +@deffn {Command} {gdb breakpoint_override} [@option{hard}|@option{soft}|@option{disable}] Force breakpoint type for gdb @command{break} commands. This option supports GDB GUIs which don't distinguish hard versus soft breakpoints, if the default OpenOCD and @@ -2248,41 +2258,41 @@ breakpoints if the memory map has been set up for flash regions. @end deffn @anchor{gdbflashprogram} -@deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable}) +@deffn {Config Command} {gdb flash_program} (@option{enable}|@option{disable}) Set to @option{enable} to cause OpenOCD to program the flash memory when a vFlash packet is received. The default behaviour is @option{enable}. @end deffn -@deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable}) +@deffn {Config Command} {gdb memory_map} (@option{enable}|@option{disable}) Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when requested. GDB will then know when to set hardware breakpoints, and program flash -using the GDB load command. @command{gdb_flash_program enable} must also be enabled +using the GDB load command. @command{gdb flash_program enable} must also be enabled for flash programming to work. Default behaviour is @option{enable}. -@xref{gdbflashprogram,,gdb_flash_program}. +@xref{gdbflashprogram,,gdb flash_program}. @end deffn -@deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable}) +@deffn {Config Command} {gdb report_data_abort} (@option{enable}|@option{disable}) Specifies whether data aborts cause an error to be reported by GDB memory read packets. The default behaviour is @option{disable}; use @option{enable} see these errors reported. @end deffn -@deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable}) +@deffn {Config Command} {gdb report_register_access_error} (@option{enable}|@option{disable}) Specifies whether register accesses requested by GDB register read/write packets report errors or not. The default behaviour is @option{disable}; use @option{enable} see these errors reported. @end deffn -@deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable}) +@deffn {Config Command} {gdb target_description} (@option{enable}|@option{disable}) Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet. The default behaviour is @option{enable}. @end deffn -@deffn {Command} {gdb_save_tdesc} +@deffn {Command} {gdb save_tdesc} Saves the target description file to the local file system. The file name is @i{target_name}.xml. @@ -2294,7 +2304,7 @@ The file name is @i{target_name}.xml. Hardware debuggers are parts of asynchronous systems, where significant events can happen at any time. The OpenOCD server needs to detect some of these events, -so it can report them to through TCL command line +so it can report them to through Tcl command line or to GDB. Examples of such events include: @@ -2335,7 +2345,7 @@ specific information about the current state is printed. An optional parameter allows background polling to be enabled and disabled. -You could use this from the TCL command shell, or +You could use this from the Tcl command shell, or from GDB using @command{monitor poll} command. Leave background polling enabled while you're using GDB. @example @@ -2404,21 +2414,75 @@ target. @deffn {Command} {adapter list} List the debug adapter drivers that have been built into the running copy of OpenOCD. + +The output is formatted as a Tcl dictionary indexed by the adapter name +and containing the transports in a Tcl list. +@example +dummy @{ jtag @} +ftdi @{ jtag swd @} +@end example +This format is easily handled by Tcl scripts: +@example +dict get [adapter list] ftdi +@end example @end deffn -@deffn {Config Command} {adapter transports} transport_name+ -Specifies the transports supported by this debug adapter. -The adapter driver builds-in similar knowledge; use this only -when external configuration (such as jumpering) changes what -the hardware can support. -@end deffn +@anchor{adapter gpio} +@deffn {Config Command} {adapter gpio [ @ + @option{tdo} | @option{tdi} | @option{tms} | @option{tck} | @option{trst} | @ + @option{swdio} | @option{swdio_dir} | @option{swclk} | @option{srst} | @ + @option{led} @ + [ @ + gpio_number | @option{-chip} chip_number | @ + @option{-active-high} | @option{-active-low} | @ + @option{-push-pull} | @option{-open-drain} | @option{-open-source} | @ + @option{-pull-none} | @option{-pull-up} | @option{-pull-down} | @ + @option{-init-inactive} | @option{-init-active} | @option{-init-input} @ + ] ]} + +Define the GPIO mapping that the adapter will use. The following signals can be +defined: + +@itemize @minus +@item @option{tdo}, @option{tdi}, @option{tms}, @option{tck}, @option{trst}: +JTAG transport signals +@item @option{swdio}, @option{swclk}: SWD transport signals +@item @option{swdio_dir}: optional swdio buffer control signal +@item @option{srst}: system reset signal +@item @option{led}: optional activity led + +@end itemize +Some adapters require that the GPIO chip number is set in addition to the GPIO +number. The configuration options enable signals to be defined as active-high or +active-low. The output drive mode can be set to push-pull, open-drain or +open-source. Most adapters will have to emulate open-drain or open-source drive +modes by switching between an input and output. Input and output signals can be +instructed to use a pull-up or pull-down resistor, assuming it is supported by +the adaptor driver and hardware. The initial state of outputs may also be set, +"active" state means 1 for active-high outputs and 0 for active-low outputs. +Bidirectional signals may also be initialized as an input. If the swdio signal +is buffered the buffer direction can be controlled with the swdio_dir signal; +the active state means that the buffer should be set as an output with respect +to the adapter. The command options are cumulative with later commands able to +override settings defined by earlier ones. The two commands @command{gpio led 7 +-active-high} and @command{gpio led -chip 1 -active-low} sent sequentially are +equivalent to issuing the single command @command{gpio led 7 -chip 1 +-active-low}. It is not permissible to set the drive mode or initial state for +signals which are inputs. The drive mode for the srst and trst signals must be +set with the @command{adapter reset_config} command. It is not permissible to +set the initial state of swdio_dir as it is derived from the initial state of +swdio. The command @command{adapter gpio} prints the current configuration for +all GPIOs while the command @command{adapter gpio gpio_name} prints the current +configuration for gpio_name. Not all adapters support this generic GPIO mapping, +some require their own commands to define the GPIOs used. Adapters that support +the generic mapping may not support all of the listed options. +@end deffn @deffn {Command} {adapter name} Returns the name of the debug adapter driver being used. @end deffn -@anchor{adapter_usb_location} @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...] Displays or specifies the physical USB port of the adapter to use. The path roots at @var{bus} and walks down the physical ports, with each @@ -2433,8 +2497,11 @@ This command is only available if your libusb1 is at least version 1.0.16. Specifies the @var{serial_string} of the adapter to use. If this command is not specified, serial strings are not checked. Only the following adapter drivers use the serial string from this command: -aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus, +arm-jtag-ew, cmsis_dap, esp_usb_jtag, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus, openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110. + +For jlink adapters, the @var{serial_string} is also compared +against the adapter's nickname. @end deffn @section Interface Drivers @@ -2444,6 +2511,8 @@ enabled when OpenOCD is configured, in order to be made available at run time. @deffn {Interface Driver} {amt_jtagaccel} +@b{Note: This adapter is deprecated and support will be removed in the next release!} + Amontec Chameleon in its JTAG Accelerator configuration, connected to a PC's EPP mode parallel port. This defines some driver-specific commands: @@ -2459,6 +2528,10 @@ Optionally sets that option first. @end deffn @end deffn +@deffn {Interface Driver} {angie} +This is the NanoXplore's ANGIE USB-JTAG Adapter. +@end deffn + @deffn {Interface Driver} {arm-jtag-ew} Olimex ARM-JTAG-EW USB adapter This has one driver-specific command: @@ -2480,32 +2553,44 @@ and a specific set of GPIOs is used. ARM CMSIS-DAP compliant based adapter v1 (USB HID based) or v2 (USB bulk). -@deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+ +@deffn {Config Command} {cmsis-dap vid_pid} [vid pid]+ The vendor ID and product ID of the CMSIS-DAP device. If not specified the driver will attempt to auto detect the CMSIS-DAP device. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g. @example -cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204 +cmsis-dap vid_pid 0xc251 0xf001 0x0d28 0x0204 @end example @end deffn -@deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}] +@deffn {Config Command} {cmsis-dap backend} [@option{auto}|@option{usb_bulk}|@option{hid}] Specifies how to communicate with the adapter: @itemize @minus @item @option{hid} Use HID generic reports - CMSIS-DAP v1 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1. -This is the default if @command{cmsis_dap_backend} is not specified. +This is the default if @command{cmsis-dap backend} is not specified. @end itemize @end deffn -@deffn {Config Command} {cmsis_dap_usb interface} [number] +@deffn {Config Command} {cmsis-dap usb interface} [number] Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk). In most cases need not to be specified and interfaces are searched by interface string or for user class interface. @end deffn +@deffn {Command} {cmsis-dap quirk} [@option{enable}|@option{disable}] +Enables or disables the following workarounds of known CMSIS-DAP adapter +quirks: +@itemize @minus +@item disconnect and re-connect before sending a switch sequence +@item packets pipelining is suppressed, only one packet at a time is +submitted to the adapter +@end itemize +The quirk workarounds are disabled by default. +The command without a parameter displays current setting. +@end deffn + @deffn {Command} {cmsis-dap info} Display various device information, like hardware version, firmware version, current bus status. @end deffn @@ -2747,9 +2832,9 @@ If not specified, default 0xFFFF is used. @end deffn @deffn {Interface Driver} {remote_bitbang} -Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection -with a remote process and sends ASCII encoded bitbang requests to that process -instead of directly driving JTAG. +Drive JTAG and SWD from a remote process. This sets up a UNIX or TCP socket +connection with a remote process and sends ASCII encoded bitbang requests to +that process instead of directly driving JTAG and SWD. The remote_bitbang driver is useful for debugging software running on processors which are being simulated. @@ -2764,6 +2849,15 @@ Specifies the hostname of the remote process to connect to using TCP, or the name of the UNIX socket to use if remote_bitbang port is 0. @end deffn +@deffn {Config Command} {remote_bitbang use_remote_sleep} (on|off) +If this option is enabled, delays will not be executed locally but instead +forwarded to the remote host. This is useful if the remote host performs its +own request queuing rather than executing requests immediately. + +This is disabled by default. This option must only be enabled if the given +remote_bitbang host supports receiving the delay information. +@end deffn + For example, to connect remotely via TCP to the host foobar you might have something like: @@ -2773,6 +2867,15 @@ remote_bitbang port 3335 remote_bitbang host foobar @end example +And if you also wished to enable remote sleeping: + +@example +adapter driver remote_bitbang +remote_bitbang port 3335 +remote_bitbang host foobar +remote_bitbang use_remote_sleep on +@end example + To connect to another process running locally via UNIX sockets with socket named mysocket: @@ -2829,6 +2932,8 @@ image. To be used with USB-Blaster II only. @end deffn @deffn {Interface Driver} {gw16012} +@b{Note: This adapter is deprecated and support will be removed in the next release!} + Gateworks GW16012 JTAG programmer. This has one driver-specific command: @@ -2868,6 +2973,11 @@ Display free device internal memory. Set the JTAG command version to be used. Without argument, show the actual JTAG command version. @end deffn +@deffn {Command} {jlink targetpower} [@option{0}|@option{1}|@option{on}|@option{off}] +Switch the 5@ V target power supply on or off. +Without argument, show the state of the target power supply. +The target power supply is usually connected to pin 19 of the 20-pin connector. +@end deffn @deffn {Command} {jlink config} Display the device configuration. @end deffn @@ -2928,7 +3038,7 @@ This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device families, but it is possible to use it with some other devices. If you are using this adapter with a PSoC or a PRoC, you may need to add -@command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your +@command{kitprog init_acquire_psoc} or @command{kitprog acquire_psoc} to your configuration script. Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP @@ -2949,14 +3059,14 @@ versions only implement "SWD line reset". Second, due to a firmware quirk, an SWD sequence must be sent after every target reset in order to re-establish communications with the target. @item Due in part to the limitation above, KitProg devices with firmware below -version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to +version 2.14 will need to use @command{kitprog init_acquire_psoc} in order to communicate with PSoC 5LP devices. This is because, assuming debug is not disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD" could only be sent with an acquisition sequence. @end itemize -@deffn {Config Command} {kitprog_init_acquire_psoc} +@deffn {Config Command} {kitprog init_acquire_psoc} Indicate that a PSoC acquisition sequence needs to be run during adapter init. Please be aware that the acquisition sequence hard-resets the target. @end deffn @@ -3102,24 +3212,27 @@ that OpenOCD would normally use to access the target. Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI and Nuvoton Nu-Link. + ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier versions of firmware where serial number is reset after first use. Suggest using ST firmware update utility to upgrade ST-LINK firmware even if current version reported is V2.J21.S4. +The ST-LINK firmware update utility is available for download from +@url{https://www.st.com/en/development-tools/stsw-link007.html, ST website}. -@deffn {Config Command} {hla_device_desc} description +@deffn {Config Command} {hla device_desc} description Currently Not Supported. @end deffn -@deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink}) +@deffn {Config Command} {hla layout} (@option{stlink}|@option{icdi}|@option{nulink}) Specifies the adapter layout to use. @end deffn -@deffn {Config Command} {hla_vid_pid} [vid pid]+ +@deffn {Config Command} {hla vid_pid} [vid pid]+ Pairs of vendor IDs and product IDs of the device. @end deffn -@deffn {Config Command} {hla_stlink_backend} (usb | tcp [port]) +@deffn {Config Command} {hla stlink_backend} (usb | tcp [port]) @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or 'shared' mode using ST-Link TCP server (the default port is 7184). @@ -3128,7 +3241,7 @@ available from @url{https://www.st.com/en/development-tools/st-link-server.html, ST-LINK server software module}. @end deffn -@deffn {Command} {hla_command} command +@deffn {Command} {hla command} command Execute a custom adapter-specific command. The @var{command} string is passed as is to the underlying adapter layout handler. @end deffn @@ -3137,9 +3250,17 @@ passed as is to the underlying adapter layout handler. @anchor{st_link_dap_interface} @deffn {Interface Driver} {st-link} This is a driver that supports STMicroelectronics adapters ST-LINK/V2 -(from firmware V2J24) and STLINK-V3, thanks to a new API that provides +(from 2015 firmware V2J24), STLINK-V3 and STLINK-V3PWR, thanks to a new API that provides directly access the arm ADIv5 DAP. +The older API that requires HLA transport is deprecated and will be dropped +from OpenOCD. In mean time it's still available by using @file{interface/stlink-hla.cfg}. +The HLA interface file can be put as first command line argument to +force using is in place of the default DAP API. +@example +openocd -f interface/stlink-hla.cfg -f board/st_nucleo_f4.cfg +@end example + The new API provide access to multiple AP on the same DAP, but the maximum number of the AP port is limited by the specific firmware version (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8). @@ -3232,8 +3353,10 @@ The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1". @end deffn @deffn {Interface Driver} {bcm2835gpio} -This SoC is present in Raspberry Pi which is a cheap single-board computer -exposing some GPIOs on its expansion header. +This GPIO interface is present in Raspberry Pi 0-4 which is a cheap +single-board computer exposing some GPIOs on its expansion header. + +@emph{Note:} for Raspberry Pi 5, use @b{linuxgpiod} not this driver. The driver accesses memory-mapped GPIO peripheral registers directly for maximum performance, but the only possible race condition is for @@ -3242,76 +3365,37 @@ able to coexist nicely with both sysfs bitbanging and various peripherals' kernel drivers. The driver restores the previous configuration on exit. -GPIO numbers >= 32 can't be used for performance reasons. +GPIO numbers >= 32 can't be used for performance reasons. GPIO configuration is +handled by the generic command @ref{adapter gpio, @command{adapter gpio}}. See @file{interface/raspberrypi-native.cfg} for a sample config and -pinout. - -@deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo} -Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). -Must be specified to enable JTAG transport. These pins can also be specified -individually. -@end deffn - -@deffn {Config Command} {bcm2835gpio tck_num} @var{tck} -Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{bcm2835gpio jtag_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio tms_num} @var{tms} -Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{bcm2835gpio jtag_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo} -Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{bcm2835gpio jtag_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi} -Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{bcm2835gpio jtag_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio} -Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be -specified to enable SWD transport. These pins can also be specified individually. -@end deffn - -@deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk} -Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be -specified using the configuration command @command{bcm2835gpio swd_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio} -Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be -specified using the configuration command @command{bcm2835gpio swd_nums}. -@end deffn - -@deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir} -Set SWDIO direction control pin GPIO number. If specified, this pin can be used -to control the direction of an external buffer on the SWDIO pin (set=output -mode, clear=input mode). If not specified, this feature is disabled. -@end deffn - -@deffn {Config Command} {bcm2835gpio srst_num} @var{srst} -Set SRST GPIO number. Must be specified to enable SRST. -@end deffn - -@deffn {Config Command} {bcm2835gpio trst_num} @var{trst} -Set TRST GPIO number. Must be specified to enable TRST. -@end deffn +@file{interface/raspberrypi-gpio-connector.cfg} for pinout. @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset} Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified, speed_coeff defaults to 113714, and speed_offset defaults to 28. @end deffn +@deffn {Config Command} {bcm2835gpio peripheral_mem_dev} @var{device} +Set the device path for access to the memory mapped GPIO control registers. +Uses @file{/dev/gpiomem} by default, this is also the preferred option with +respect to system security. +If overridden to @file{/dev/mem}: +@itemize @minus +@item OpenOCD needs @code{cap_sys_rawio} or run as root to open @file{/dev/mem}. +Please be aware of security issues imposed by running OpenOCD with +elevated user rights and by @file{/dev/mem} itself. +@item correct @command{peripheral_base} must be configured. +@item GPIO 0-27 pads are set to the limited slew rate +and drive strength is reduced to 4 mA (2 mA on RPi 4). +@end itemize + +@end deffn + @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base} -Set the peripheral base register address to access GPIOs. For the RPi1, use -0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full -list can be found in the -@uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}. +Set the peripheral base register address to access GPIOs. +Ignored if @file{/dev/gpiomem} is used. For the RPi1, use +0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. @end deffn @end deffn @@ -3337,171 +3421,92 @@ registers directly. The memory mapping requires read and write permission to kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will be used. The driver restores the GPIO state on exit. -All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO port -0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on. - -See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file. - -@deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo} -Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). -Must be specified to enable JTAG transport. These pins can also be specified -individually. -@end deffn - -@deffn {Config Command} {am335xgpio tck_num} @var{tck} -Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{am335xgpio jtag_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio tms_num} @var{tms} -Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{am335xgpio jtag_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio tdo_num} @var{tdo} -Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{am335xgpio jtag_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio tdi_num} @var{tdi} -Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be -specified using the configuration command @command{am335xgpio jtag_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio} -Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be -specified to enable SWD transport. These pins can also be specified individually. -@end deffn - -@deffn {Config Command} {am335xgpio swclk_num} @var{swclk} -Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be -specified using the configuration command @command{am335xgpio swd_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio swdio_num} @var{swdio} -Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be -specified using the configuration command @command{am335xgpio swd_nums}. -@end deffn - -@deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio_dir} -Set SWDIO direction control pin GPIO number. If specified, this pin can be used -to control the direction of an external buffer on the SWDIO pin. The direction -control state can be set with the command @command{am335xgpio -swdio_dir_output_state}. If not specified this feature is disabled. -@end deffn - -@deffn {Config Command} {am335xgpio swdio_dir_output_state} @var{output_state} -Set the state required for an external SWDIO buffer to be an output. Valid -values are @option{on} (default) and @option{off}. -@end deffn - -@deffn {Config Command} {am335xgpio srst_num} @var{srst} -Set SRST GPIO number. Must be specified to enable SRST. -@end deffn - -@deffn {Config Command} {am335xgpio trst_num} @var{trst} -Set TRST GPIO number. Must be specified to enable TRST. -@end deffn - -@deffn {Config Command} {am335xgpio led_num} @var{led} -Set activity LED GPIO number. If not specified an activity LED is not enabled. -@end deffn - -@deffn {Config Command} {am335xgpio led_on_state} @var{on_state} -Set required logic level for the LED to be on. Valid values are @option{on} -(default) and @option{off}. -@end deffn +All four GPIO ports are available. GPIO configuration is handled by the generic +command @ref{adapter gpio, @command{adapter gpio}}. @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset} Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified speed_coeff defaults to 600000 and speed_offset defaults to 575. @end deffn -@end deffn - +See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file. -@deffn {Interface Driver} {linuxgpiod} -Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6. -The driver emulates either JTAG or SWD transport through bitbanging. +@end deffn -See @file{interface/dln-2-gpiod.cfg} for a sample config. +@deffn {Interface Driver} {linuxspidev} +Linux provides userspace access to SPI through spidev. Full duplex SPI +transactions are used to simultaneously read and write to/from the target to +emulate the SWD transport. -@deffn {Config Command} {linuxgpiod gpiochip} @var{chip} -Set the GPIO chip number for all GPIOs used by linuxgpiod. If GPIOs use -different GPIO chips then the individual GPIO configuration commands (i.e., not -@command{linuxgpiod jtag_nums} or @command{linuxgpiod swd_nums}) can be used to -set chip numbers independently for each GPIO. +@deffn {Config Command} {spidev path} path +Specifies the path to the spidev device. @end deffn -@deffn {Config Command} {linuxgpiod jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo} -Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). Must -be specified to enable JTAG transport. These pins can also be specified -individually. +@deffn {Config Command} {spidev mode} value +Set the mode of the spi port with optional bit flags (default=3). +See /usr/include/linux/spi/spidev.h for all of the SPI mode options. @end deffn -@deffn {Config Command} {linuxgpiod tck_num} [@var{chip}] @var{tck} -Set TCK GPIO number, and optionally TCK chip number. Must be specified to enable -JTAG transport. Can also be specified using the configuration command -@command{linuxgpiod jtag_nums}. +@deffn {Config Command} {spidev queue_entries} value +Set the maximum number of queued transactions per spi exchange (default=64). +More queued transactions may offer greater performance when the target doesn't +need to wait. On the contrary higher numbers will reduce performance when the +target requests a wait as all queued transactions will need to be exchanged +before spidev can see the wait request. @end deffn -@deffn {Config Command} {linuxgpiod tms_num} [@var{chip}] @var{tms} -Set TMS GPIO number, and optionally TMS chip number. Must be specified to enable -JTAG transport. Can also be specified using the configuration command -@command{linuxgpiod jtag_nums}. -@end deffn +See @file{tcl/interface/spidev_example.cfg} for a sample configuration file. -@deffn {Config Command} {linuxgpiod tdo_num} [@var{chip}] @var{tdo} -Set TDO GPIO number, and optionally TDO chip number. Must be specified to enable -JTAG transport. Can also be specified using the configuration command -@command{linuxgpiod jtag_nums}. -@end deffn +Electrical connections: +@example ++--------------+ +--------------+ +| | 1K | | +| MOSI|---/\/\/\---+ | | +| Host | | | Target | +| MISO|------------+---|SWDIO | +| | | | +| SCK|----------------|SWDCLK | +| | | | ++--------------+ +--------------+ +@end example -@deffn {Config Command} {linuxgpiod tdi_num} [@var{chip}] @var{tdi} -Set TDI GPIO number, and optionally TDI chip number. Must be specified to enable -JTAG transport. Can also be specified using the configuration command -@command{linuxgpiod jtag_nums}. -@end deffn +The 1K resistor works well with most MCUs up to 3 MHz. A lower resistance +could be used to achieve higher speeds granted that the target SWDIO pin has +enough drive strength to pull the signal high while being pulled low by this +resistor. -@deffn {Config Command} {linuxgpiod trst_num} [@var{chip}] @var{trst} -Set TRST GPIO number, and optionally TRST chip number. Must be specified to -enable TRST. -@end deffn +If you are having trouble here are some tips: -@deffn {Config Command} {linuxgpiod swd_nums} @var{swclk} @var{swdio} -Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be -specified to enable SWD transport. These pins can also be specified -individually. -@end deffn +@itemize @bullet -@deffn {Config Command} {linuxgpiod swclk_num} [@var{chip}] @var{swclk} -Set SWCLK GPIO number, and optionally SWCLK chip number. Must be specified to -enable SWD transport. Can also be specified using the configuration command -@command{linuxgpiod swd_nums}. -@end deffn +@item @b{Make sure MISO and MOSI are tied together with a 1K resistor.} +MISO should be attached to the target. -@deffn {Config Command} {linuxgpiod swdio_num} [@var{chip}] @var{swdio} -Set SWDIO GPIO number, and optionally SWDIO chip number. Must be specified to -enable SWD transport. Can also be specified using the configuration command -@command{linuxgpiod swd_nums}. -@end deffn +@item @b{Make sure that your host and target are using the same I/O voltage} +(for example both are using 3.3 volts). -@deffn {Config Command} {linuxgpiod swdio_dir_num} [@var{chip}] @var{swdio_dir} -Set SWDIO direction control GPIO number, and optionally SWDIO direction control -chip number. If specified, this GPIO can be used to control the direction of an -external buffer connected to the SWDIO GPIO (set=output mode, clear=input mode). -@end deffn +@item @b{Your host's SPI port may not idle low.} +This will lead to an additional clock edge being sent to the target, causing +the host and target being 1 clock off from each other. Try setting +SPI_MOSI_IDLE_LOW in spi_mode. Try using a different spi_mode (0 - 3). -@deffn {Config Command} {linuxgpiod srst_num} [@var{chip}] @var{srst} -Set SRST GPIO number, and optionally SRST chip number. Must be specified to -enable SRST. -@end deffn +@item @b{Your target may pull SWDIO and/or SWDCLK high.} +This will create an extra edge when the host releases control of the SPI port +at the end of a transaction. You'll need to confirm this with a scope or meter. +Try installing 10K resistors on SWDIO and SWDCLK to ground to stop this. -@deffn {Config Command} {linuxgpiod led_num} [@var{chip}] @var{led} -Set activity LED GPIO number, and optionally activity LED chip number. If not -specified an activity LED is not enabled. +@end itemize @end deffn +@deffn {Interface Driver} {linuxgpiod} +Linux provides userspace access to GPIO through libgpiod since Linux kernel +version v4.6. The driver emulates either JTAG or SWD transport through +bitbanging. There are no driver-specific commands, all GPIO configuration is +handled by the generic command @ref{adapter gpio, @command{adapter gpio}}. This +driver supports the resistor pull options provided by the @command{adapter gpio} +command but the underlying hardware may not be able to support them. + +See @file{interface/dln-2-gpiod.cfg} for a sample configuration file. @end deffn @@ -3532,6 +3537,15 @@ Currently valid @var{variant} values include: The USB device description string of the adapter. This value is only used with the standard variant. @end deffn + +@deffn {Config Command} {openjtag vid_pid} vid pid +The USB vendor ID and product ID of the adapter. If not specified, default +0x0403:0x6001 is used. +This value is only used with the standard variant. +@example +openjtag vid_pid 0x403 0x6014 +@end example +@end deffn @end deffn @@ -3651,11 +3665,11 @@ Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB B These chips have built-in JTAG circuitry and can be debugged without any additional hardware. Only an USB cable connected to the D+/D- pins is necessary. -@deffn {Config Command} {espusbjtag tdo} +@deffn {Command} {espusbjtag tdo} Returns the current state of the TDO line @end deffn -@deffn {Config Command} {espusbjtag setio} setio +@deffn {Command} {espusbjtag setio} setio Manually set the status of the output lines with the order of (tdi tms tck trst srst) @example espusbjtag setio 0 1 0 1 0 @@ -3685,6 +3699,79 @@ espusbjtag chip_id 1 @end deffn +@deffn {Interface Driver} {dmem} Direct Memory access debug interface + +The Texas Instruments K3 SoC family provides memory access to DAP +and coresight control registers. This allows control over the +microcontrollers directly from one of the processors on the SOC +itself. + +For maximum performance, the driver accesses the debug registers +directly over the SoC memory map. The memory mapping requires read +and write permission to kernel memory via "/dev/mem" and assumes that +the system firewall configurations permit direct access to the debug +memory space. + +@verbatim ++-----------+ +| OpenOCD | SoC mem map (/dev/mem) +| on +--------------+ +| Cortex-A53| | ++-----------+ | + | ++-----------+ +-----v-----+ +|Cortex-M4F <--------+ | ++-----------+ | | + | DebugSS | ++-----------+ | | +|Cortex-M4F <--------+ | ++-----------+ +-----------+ +@end verbatim + +NOTE: Firewalls are configurable in K3 SoC and depending on various types of +device configuration, this function may be blocked out. Typical behavior +observed in such cases is a firewall exception report on the security +controller and armv8 processor reporting a system error. + +See @file{tcl/interface/ti_k3_am625-swd-native.cfg} for a sample configuration +file. + +@deffn {Command} {dmem info} +Print the DAPBUS dmem configuration. +@end deffn + +@deffn {Config Command} {dmem device} device_path +Set the DAPBUS memory access device (default: /dev/mem). +@end deffn + +@deffn {Config Command} {dmem base_address} base_address +Set the DAPBUS base address which is used to access CoreSight +compliant Access Ports (APs) directly. +@end deffn + +@deffn {Config Command} {dmem ap_address_offset} offset_address +Set the address offset between Access Ports (APs). +@end deffn + +@deffn {Config Command} {dmem max_aps} n +Set the maximum number of valid access ports on the SoC. +@end deffn + +@deffn {Config Command} {dmem emu_ap_list} n +Set the list of Access Ports (APs) that need to be emulated. This +emulation mode supports software translation of an AP request into an +address mapped transaction that does not rely on physical AP hardware. +This maybe needed if the AP is either denied access via memory map or +protected using other SoC mechanisms. +@end deffn + +@deffn {Config Command} {dmem emu_base_address_range} base_address address_window_size +Set the emulated address and address window size. Both of these +parameters must be aligned to page size. +@end deffn + +@end deffn + @section Transport Configuration @cindex Transport As noted earlier, depending on the version of OpenOCD you use, @@ -3696,20 +3783,18 @@ displays the names of the transports supported by this version of OpenOCD. @end deffn -@deffn {Command} {transport select} @option{transport_name} +@deffn {Command} {transport select} [transport_name] Select which of the supported transports to use in this OpenOCD session. When invoked with @option{transport_name}, attempts to select the named -transport. The transport must be supported by the debug adapter +transport. The transport must be supported by the debug adapter hardware and by the version of OpenOCD you are using (including the adapter's driver). - -If no transport has been selected and no @option{transport_name} is -provided, @command{transport select} auto-selects the first transport -supported by the debug adapter. - -@command{transport select} always returns the name of the session's selected -transport, if any. +When invoked with no transport name: +@itemize @minus +@item if no transport has been selected yet, it auto-selects the first transport supported by the debug adapter +@item it returns the name of the session's selected transport +@end itemize @end deffn @subsection JTAG Transport @@ -3722,10 +3807,8 @@ JTAG supports both debugging and boundary scan testing. Flash programming support is built on top of debug support. JTAG transport is selected with the command @command{transport select -jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface -driver} (in which case the command is @command{transport select hla_jtag}) -or @ref{st_link_dap_interface,the st-link interface driver} (in which case -the command is @command{transport select dapdirect_jtag}). +jtag}. This command has to be used also for @ref{hla_interface,the hla interface +driver} and @ref{st_link_dap_interface,the st-link interface driver}. @subsection SWD Transport @cindex SWD @@ -3738,10 +3821,8 @@ Flash programming support is built on top of debug support. (Some processors support both JTAG and SWD.) SWD transport is selected with the command @command{transport select -swd}. Unless your adapter uses either @ref{hla_interface,the hla interface -driver} (in which case the command is @command{transport select hla_swd}) -or @ref{st_link_dap_interface,the st-link interface driver} (in which case -the command is @command{transport select dapdirect_swd}). +swd}. This command has to be used also for @ref{hla_interface,the hla interface +driver} and @ref{st_link_dap_interface,the st-link interface driver}. @deffn {Config Command} {swd newdap} ... Declares a single DAP which uses SWD transport. @@ -3760,13 +3841,6 @@ Not all adapters and adapter drivers support SWD multi-drop. Only the following adapter drivers are SWD multi-drop capable: cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based. -@subsection SPI Transport -@cindex SPI -@cindex Serial Peripheral Interface -The Serial Peripheral Interface (SPI) is a general purpose transport -which uses four wire signaling. Some processors use it as part of a -solution for flash programming. - @anchor{swimtransport} @subsection SWIM Transport @cindex SWIM @@ -4438,6 +4512,10 @@ there seems to be no problems with JTAG scan chain operations. register during initial examination and when checking the sticky error bit. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some devices do not set the ack bit until sometime later. +@item @code{-ir-bypass} @var{NUMBER} +@*Vendor specific bypass instruction, required by some hierarchical JTAG +routers where the normal BYPASS instruction bypasses the whole router and +a vendor specific bypass instruction is required to access child nodes. @end itemize @end deffn @@ -4456,7 +4534,7 @@ mechanism for debugger targets.) See the next section for information about the available events. The @code{configure} subcommand assigns an event handler, -a TCL string which is evaluated when the event is triggered. +a Tcl string which is evaluated when the event is triggered. The @code{cget} subcommand returns that handler. @end deffn @@ -4715,7 +4793,7 @@ The instance number is in bits 28..31 of DLPIDR value. @deffn {Command} {dap names} This command returns a list of all registered DAP objects. It it useful mainly -for TCL scripting. +for Tcl scripting. @end deffn @deffn {Command} {dap info} [@var{num}|@option{root}] @@ -4836,6 +4914,10 @@ Set/get quirks mode for TI TMS450/TMS570 processors Disabled by default @end deffn +@deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}] +Set/get quirks mode for Nuvoton NPCX/NPCD MCU families +Disabled by default +@end deffn @node CPU Configuration @chapter CPU Configuration @@ -4971,9 +5053,6 @@ specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will be emulated to comply to GDB remote protocol. @item @code{mips_m4k} -- a MIPS core. @item @code{mips_mips64} -- a MIPS64 core. -@item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0). -@item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0). -@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0). @item @code{or1k} -- this is an OpenRISC 1000 core. The current implementation supports three JTAG TAP cores: @itemize @minus @@ -4995,6 +5074,7 @@ And two debug interfaces cores: @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD. @item @code{xscale} -- this is actually an architecture, not a CPU type. It is based on the ARMv5 architecture. +@item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core. @end itemize @end deffn @@ -5145,10 +5225,10 @@ The value should normally correspond to a static mapping for the @anchor{rtostype} @item @code{-rtos} @var{rtos_type} -- enable rtos support for target, -@var{rtos_type} can be one of @option{auto}, @option{eCos}, +@var{rtos_type} can be one of @option{auto}, @option{none}, @option{eCos}, @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS}, @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}, -@option{RIOT}, @option{Zephyr} +@option{RIOT}, @option{Zephyr}, @option{rtkernel} @xref{gdbrtossupport,,RTOS Support}. @item @code{-defer-examine} -- skip target examination at initial JTAG chain @@ -5161,6 +5241,38 @@ On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is con Use this option with systems where multiple, independent cores are connected to separate access ports of the same DAP. +@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the +debug controller. +This is ignored and not required for target types that have the debug controller +at fixed addresses, like @code{cortex_m}. +On DAP based SoC, OpenOCD can parse the ROM table in the DAP access port to +identify the base address of the debug controller, but the parsing can be slow +on devices with big ROM tables. +While using @code{-dbgbase} is suggested to speed up the target examination, +it is often the only viable solution for devices with incorrect ROM table +content or with ROM table partially not accessible due to clock gating or +power management. + +@item @code{-coreid} @var{coreid} -- set an index to identify the CPU or its +debug controller. + +@itemize @minus +@item When @code{-dbgbase} option is not provided on devices with multiple +CPUs on the same DAP access port +(e.g. @code{cortex_a}, @code{cortex_r4}, @code{aarch64} and @code{armv8r}), +this option specifies that the ROM table parsing should select the CPU in +position @var{coreid}. + +@item On target type @code{riscv}, @var{coreid} specifies the hart +(HARdware Threads) on the DM (Debug Module). It is used on multi-hart +devices to index a specific hart ID. +When not present, it's default value is zero. + +@item This value @var{coreid} is currently also used in other contexts as a +general CPU index, e.g. in SMP nodes or to select a specific CPU in a chip. +To avoid confusion, these additional use cases are going to be dropped. +@end itemize + @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected to the target. Currently, only the @code{aarch64} target makes use of this option, where it is a mandatory configuration for the target run control. @@ -5168,11 +5280,11 @@ where it is a mandatory configuration for the target run control. for instruction on how to declare and control a CTI instance. @anchor{gdbportoverride} -@item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the +@item @code{-gdb-port} @var{number} -- @xref{gdb port,,command gdb port}, for the possible values of the parameter @var{number}, which are not only numeric values. Use this option to override, for this target only, the global parameter set with -command @command{gdb_port}. -@xref{gdb_port,,command gdb_port}. +command @command{gdb port}. +@xref{gdb port,,command gdb port}. @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum number of GDB connections that are allowed for the target. Default is 1. @@ -5334,10 +5446,23 @@ Displays the current target state: @code{debug-running}, @code{halted}, @code{reset}, -@code{running}, or @code{unknown}. +@code{running}, +@code{unavailable} or @code{unknown}. (Also, @pxref{eventpolling,,Event Polling}.) @end deffn +@deffn {Command} {$target_name debug_reason} +Displays the current debug reason: +@code{debug-request}, +@code{breakpoint}, +@code{watchpoint}, +@code{watchpoint-and-breakpoint}, +@code{single-step}, +@code{target-not-halted}, +@code{program-exit}, +@code{exception-catch} or @code{undefined}. +@end deffn + @deffn {Command} {$target_name eventlist} Displays a table listing all event handlers currently associated with this target. @@ -5658,7 +5783,7 @@ until the programming session is finished. If you use @ref{programmingusinggdb,,Programming using GDB}, the target is prepared automatically in the event gdb-flash-erase-start -The jimtcl script @command{program} calls @command{reset init} explicitly. +The Tcl script @command{program} calls @command{reset init} explicitly. @section Erasing, Reading, Writing to Flash @cindex flash erasing @@ -5752,6 +5877,24 @@ The flash bank to use is inferred from the @var{address} of each block, and the specified length must stay within that bank. @end deffn +@deffn {Command} {flash read_memory} address width count +This function provides an efficient way to read flash memory from a Tcl script. +A Tcl list containing the requested memory elements is returned by this function. + +@itemize +@item @var{address} ... flash memory address +@item @var{width} ... memory access bit size, can be 8, 16, 32 or 64 +@item @var{count} ... number of elements to read +@end itemize + +For example, the following command reads two 32 bit words from the flash +memory at address 0x08000000: + +@example +flash read_memory 0x08000000 32 2 +@end example +@end deffn + @deffn {Command} {flash write_bank} num filename [offset] Write the binary @file{filename} to flash bank @var{num}, starting at @var{offset} bytes from the beginning of the bank. If @var{offset} @@ -5942,24 +6085,42 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME @c "cfi part_id" disabled @end deffn +@anchor{jtagspi} @deffn {Flash Driver} {jtagspi} @cindex Generic JTAG2SPI driver @cindex SPI @cindex jtagspi @cindex bscan_spi Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a -SPI flash connected to them. To access this flash from the host, the device -is first programmed with a special proxy bitstream that -exposes the SPI flash on the device's JTAG interface. The flash can then be -accessed through JTAG. +SPI flash connected to them. To access this flash from the host, some FPGA +device provides dedicated JTAG instructions, while other FPGA devices should +be programmed with a special proxy bitstream that exposes the SPI flash on +the device's JTAG interface. The flash can then be accessed through JTAG. -Since signaling between JTAG and SPI is compatible, all that is required for +Since signalling between JTAG and SPI is compatible, all that is required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate -the flash chip select when the JTAG state machine is in SHIFT-DR. Such -a bitstream for several Xilinx FPGAs can be found in +the flash chip select when the JTAG state machine is in SHIFT-DR. + +Such a bitstream for several Xilinx FPGAs can be found in @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build. +This mechanism with a proxy bitstream can also be used for FPGAs from Intel and +Efinix. FPGAs from Lattice and Cologne Chip have dedicated JTAG instructions +and procedure to connect the JTAG to the SPI signals and don't need a proxy +bitstream. Support for these devices with dedicated procedure is provided by +the pld drivers. For convenience the PLD drivers will provide the USERx code +for FPGAs with a proxy bitstream. Currently the following PLD drivers are able +to support jtagspi: +@itemize +@item Efinix: proxy-bitstream +@item Gatemate: dedicated procedure +@item Intel/Altera: proxy-bitstream +@item Lattice: dedicated procedure supporting ECP2, ECP3, ECP5, Certus and Certus Pro devices +@item AMD/Xilinx: proxy-bitstream +@end itemize + + This flash bank driver requires a target on a JTAG tap and will access that tap directly. Since no support from the target is needed, the target can be a "testee" dummy. Since the target does not expose the flash memory @@ -5977,14 +6138,25 @@ command, see below. @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR. For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the @var{USER1} instruction. -@end itemize +@example +target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap +set _USER1_INSTR_CODE 0x02 +flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \ + $_TARGETNAME $_USER1_INSTR_CODE +@end example + +@item The option @option{-pld} @var{name} is used to have support from the +PLD driver of pld device @var{name}. The name is the name of the pld device +given during creation of the pld device. +Pld device names are shown by the @command{pld devices} command. @example -target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga -set _XILINX_USER1 0x02 -flash bank $_FLASHNAME spi 0x0 0 0 0 \ - $_TARGETNAME $_XILINX_USER1 +target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap +set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld +flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \ + $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID @end example +@end itemize @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd Sets flash parameters: @var{name} human readable string, @var{total_size} @@ -6286,6 +6458,75 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME @end example @end deffn +@deffn {Flash Driver} {dw-spi} +@cindex DesignWare SPI controller driver +@cindex DW-SPI +Driver for SPI NOR flash chips connected via DesignWare SPI Core, used +in number of MCUs. +Currently, only MIPS M4K CPU architecture is supported. + +The flash size is autodetected based on the table of known JEDEC IDs hardcoded +in the OpenOCD sources. When flash size is set to @var{0}, probed Flash +size is used. + +This driver requires configuring DRAM controller first, setting up a +working area big enough to hold read/write buffers and switching Flash +chip to 32bit mode via Tcl commands. + +@quotation Note +If chip contains Boot controller, its 24/32bit setting must match +Flash chip. If Flash chip's reset line is not connected to JTAG adapter, +CPU reset may cause these configurations to be out of sync. +@end quotation + + +Mandatory driver's arguments are + +@itemize +@item @var{-freq} ... core frequency in Hz, used in communication speed +calculation. +@item @var{-simc} ... @var{SIMC} register block absolute address. +This value is the same as for Linux's driver device tree register field. +@item @var{-spi_mst} ... @var{SPI_MST} register address. When available, +it is used for switching between SPI Boot and Master controllers. This +value is the same as for Linux's driver device tree register field +second argument. Set to @var{0} if SPI Boot controller not available. +@item @var{-if_owner_offset} ... offset of @var{if_owner} field inside +@var{SPI_MST} register. Set to @var{0} if SPI Boot controller not available. +@end itemize + +Optional driver's arguments are + +@itemize +@item @var{-speed} ... SPI device communication speed in Hz. Minimal +speed depends on the @var{-freq} variable and has the value of +@var{freq/0xfffe}. The default value is @var{1000000}. +@item @var{-chip_select} ... Chip select pin. The default value +is @var{0}. +@item @var{-timeout} ... flash communication timeout in +seconds. The default value is @var{600}. +@end itemize + +For some SoCs there are shortcuts for mandatory arguments + +@itemize +@item @var{-jaguar2} ... configuration for MSCC Jaguar2 SoC family. +@item @var{-ocelot} ... configuration for MSCC Ocelot SoC family. +@end itemize + +Driver provides shortcut arguments for MSCC @var{-jaguar2} and +@var{-ocelot} network switch SOCs, which set the correct values for @var{-freq}, +@var{-simc}, @var{-spi_mst} and @var{-if_owner_offset} arguments. + +Example of equivalent configurations for Jaguar2 SoC + +@example +flash bank $_FLASHNAME dw-spi 0x40000000 0x02000000 4 4 $_TARGETNAME -freq 250000000 -simc 0x70101000 -spi_mst 0x70000024 -if_owner_offset 6 -speed 3000000 +flash bank $_FLASHNAME dw-spi 0x40000000 0x02000000 4 4 $_TARGETNAME -jaguar2 -speed 3000000 +@end example + +@end deffn + @subsection Internal Flash (Microcontrollers) @deffn {Flash Driver} {aduc702x} @@ -6347,7 +6588,6 @@ the flash. @end deffn @end deffn -@anchor{at91samd} @deffn {Flash Driver} {at91samd} @cindex at91samd All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller @@ -6735,6 +6975,24 @@ Note that in order for this command to take effect, the target needs to be reset supported.} @end deffn +@deffn {Flash Driver} {eneispif} +All versions of the KB1200 microcontrollers from ENE include internal +flash. The eneispif flash driver supports the KB1200 family of devices. The driver +automatically recognizes the specific version's flash parameters and +autoconfigures itself. The flash bank starts at address 0x60000000. An optional additional +parameter sets the address of eneispif controller, with the default address is 0x50101000. + +@example + +flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME \ + 0x50101000 + +# Address defaults to 0x50101000 +flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME + +@end example +@end deffn + @deffn {Flash Driver} {esirisc} Members of the eSi-RISC family may optionally include internal flash programmed via the eSi-TSMC Flash interface. Additional parameters are required to @@ -6792,16 +7050,23 @@ nor is Chip Erase (only Sector Erase is implemented).} @deffn {Flash Driver} {kinetis} @cindex kinetis -Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family -from NXP (former Freescale) include -internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically +Several microcontrollers from NXP (former Freescale), including +Kx, KLx, KVx and KE1x members of the Kinetis family, +and S32K11x/S32K14x microcontrollers, include +internal flash and use ARM Cortex-M0+ or M4 cores. +Kinetis and S32K1 families use incompatible +identification registers, so the driver assumes Kinetis and requires +a driver option to indicate S32K1 is to be used. +Within the familiy, the driver automatically recognizes flash size and a number of flash banks (1-4) using the chip identification register, and autoconfigures itself. Use kinetis_ke driver for KE0x and KEAx devices. The @var{kinetis} driver defines option: @itemize -@item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted. +@item -s32k select S32K11x/S32K14x microcontroller flash support. + +@item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries known locations if option is omitted. @end itemize @example @@ -6850,6 +7115,7 @@ command completes. @deffn {Command} {kinetis nvm_partition} For FlexNVM devices only (KxxDX and KxxFX). +Not supported (yet) on S32K1 devices. Command shows or sets data flash or EEPROM backup size in kilobytes, sets two EEPROM blocks sizes in bytes and enables/disables loading of EEPROM contents to FlexRAM during reset. @@ -7172,6 +7438,76 @@ msp432 bsl lock @end deffn @end deffn +@deffn {Flash Driver} {mspm0} + +All Arm Cortex-M0+ MSPM0 microcontroller versions from Texas Instruments +include internal flash. The mspm0 flash driver automatically recognizes the +specific version's flash parameters and autoconfigures itself. The main +program flash starts at address 0x0. Non-main flash starts at 0x41c00000. +If present on the device, the optional region called "Data" starts at +0x41d00000. + +@b{Warning}: + +@itemize @bullet +@item @b{Reset while MCU operation:} When erasing all of MAIN memory, if the +MCU is still executing from MAIN memory do not reset the device as it could +cause a double hard-fault due to the missing interrupt vector table at the +start of memory. To recover from such scenario reset or power-cycle the MCU. + +@item @b{No explicit protection support:} MSPM0 flash controller auto-protect +themselves after every flash operation. As a result of this, OpenOCD does not +explicitly provide any protection function and automatically un-protects +required sections as flash operations are requested. +@end itemize + +@b{Examples}: + +@itemize @bullet + +@item @b{Flash bank description:} +@example +flash bank $_FLASHNAME mspm0 0 0 0 0 $_TARGETNAME +@end example + +@item @b{To erase and program the MAIN region:} +@example +halt +flash erase_sector 0 0 last +flash write_image MAIN.bin 0x0 +mspm0_board_reset +@end example + +@item @b{To erase and program the NONMAIN region:} +@example +halt +flash erase_sector 1 0 last +flash write_image NONMAIN.bin 0x41C00000 +mspm0_board_reset +@end example + +@end itemize + +@deffn {Tcl proc} {mspm0_board_reset} +Performs an nRST toggle on the device. +@end deffn + +@deffn {Tcl proc} {mspm0_mass_erase} +Sends the mass erase command to the SEC-AP mailbox and then performs +an nRST toggle. Once the command has been fully processed by the ROM, +all MAIN memory will be erased. NOTE: This command is not supported +on MSPM0C* family of devices. +@end deffn + +@deffn {Tcl proc} {mspm0_factory_reset} +Sends the factory reset command to the SEC-AP mailbox and then performs +an nRST toggle. Once the command has been fully processed by the ROM, +all MAIN memory will be erased and NONMAIN will be reset to its default +values. +@end deffn + +@end deffn + @deffn {Flash Driver} {niietcm4} This drivers handles the integrated NOR flash on NIIET Cortex-M4 based controllers. Flash size and sector layout are auto-configured by the driver. @@ -7236,20 +7572,27 @@ Show information about flash driver. All versions of the NPCX microcontroller families from Nuvoton include internal flash. The NPCX flash driver supports the NPCX family of devices. The driver automatically recognizes the specific version's flash parameters and -autoconfigures itself. The flash bank starts at address 0x64000000. +autoconfigures itself. The flash bank starts at address 0x64000000. An optional additional +parameter sets the FIU version for the bank, with the default FIU is @var{npcx.fiu}. @example + +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu + +# FIU defaults to npcx.fiu flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME + @end example @end deffn @deffn {Flash Driver} {nrf5} -All members of the nRF51 microcontroller families from Nordic Semiconductor -include internal flash and use ARM Cortex-M0 core. nRF52 family powered -by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported -including BPROT flash protection scheme. nRF52833 and nRF52840 devices are -supported with the exception of security extensions (flash access control list -- ACL). +Supports all members of the nRF51, nRF52 and nRF53 microcontroller families from +Nordic Semiconductor. nRF91 family is supported too. One driver handles both +the main flash and the UICR area. + +Flash protection is handled on nRF51 family and nRF52805, nRF52810, nRF52811, +nRF52832 devices. Flash access control list (ACL) protection scheme of the newer +devices is not supported. @example flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME @@ -7264,10 +7607,6 @@ works only for chips that do not have factory pre-programmed region 0 code. @end deffn -@deffn {Command} {nrf5 info} -Decodes and shows information from FICR and UICR registers. -@end deffn - @end deffn @deffn {Flash Driver} {ocl} @@ -7459,7 +7798,7 @@ flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \ psoc6-specific commands @deffn {Command} {psoc6 reset_halt} -Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts. +Command can be used to simulate broken Vector Catch from gdbinit or Tcl scripts. When invoked for CM0+ target, it will set break point at application entry point and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used @@ -7473,15 +7812,164 @@ Note: only Main and Work flash regions support Erase operation. @end deffn @end deffn -@deffn {Flash Driver} {rp2040} -Supports RP2040 "Raspberry Pi Pico" microcontroller. -RP2040 is a dual-core device with two CM0+ cores. Both cores share the same -Flash/RAM/MMIO address space. Non-volatile storage is achieved with an -external QSPI flash; a Boot ROM provides helper functions. +@deffn {Flash Driver} {qn908x} +The NXP QN908x microcontrollers feature a Cortex-M4F with integrated Bluetooth +LE 5 support and an internal flash of up to 512 KiB. These chips only support +the SWD interface. + +The @var{qn908x} driver uses the internal "Flash Memory Controller" block via +SWD to erase, program and read the internal flash. This driver does not +support the ISP (In-System Programming) mode which is an alternate way to +program the flash via UART, SPI or USB. + +The internal flash is 512 KiB in size in all released chips and it starts at +the address 0x01000000, although it can be mapped to address 0 and it is +aliased to other addresses. This driver only recognizes the bank starting at +address 0x01000000. + +The internal bootloader stored in ROM is in charge of loading and verifying +the image from flash, or enter ISP mode. The programmed image must start at +the beginning of the flash and contain a valid header and a matching CRC32 +checksum. Additionally, the image header contains a "Code Read Protection" +(CRP) word which indicates whether SWD access is enabled, as well as whether +ISP mode is enabled. Therefore, it is possible to program an image that +disables SWD and ISP making it impossible to program another image in the +future through these interfaces, or even debug the current image. While this is +a valid use case for production deployments where the chips are locked down, by +default this driver doesn't allow such images that disable the SWD interface. +To program such images see the @command{qn908x allow_brick} command. + +Apart from the CRP field which is located in the image header, the last page +of the flash memory contains a "Flash lock and protect" descriptor which allows +to individually protect each 2 KiB page, as well as disabling SWD access to the +flash and RAM. If this access is disabled it is not possible to read, erase or +program individual pages from the SWD interface or even access the read-only +"Flash information page" with information about the bootloader version and +flash size. However when this protection is in place, it is still possible to +mass erase the whole chip and then program a new image, for which you can use +the @command{qn908x mass_erase}. + +Example: +@example +flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum +@end example + +Parameters: +@itemize +@item @option{calc_checksum} optional parameter to compute the required +checksum of the first bytes in the vector table. +@quotation Note +If the checksum in the header of your image is invalid and you don't provide the +@option{calc_checksum} option the boot ROM will not boot your image and it may +render the flash inaccessible. On the other hand, if you use this option to +compute the checksum keep in mind that @command{verify_image} will fail on +those four bytes of the checksum since those bytes in the flash will have the +updated checksum. +@end quotation +@end itemize + +@deffn {Command} {qn908x allow_brick} +Allow the qn908x driver to program images with a "Code Read Protection" byte +that disables the SWD access. Programming such image will cause OpenOCD to +not be able to reach the target over SWD anymore after the new image is +programmed and its configuration takes effect, e.g. after a reboot. After +executing @command{qn908x allow_brick} these images will be allowed to be +programmed when writing to the flash. +@end deffn + +@deffn {Command} {qn908x disable_wdog} +Disable the watchdog timer (WDT) by resetting its CTRL field. The WDT starts +enabled after a @command{reset halt} and it doesn't run while the target is +halted. However, the verification process in this driver uses the generic +Cortex-M verification process which executes a payload in RAM and thus +requires the watchdog to be disabled before running @command{verify_image} +after a reset halt or any other condition where the watchdog is running. +Note that this is not done automatically and you must run this command in +those scenarios. +@end deffn + +@deffn {Command} {qn908x mass_erase} +Erases the complete flash using the mass_erase method. Mass erase is only +allowed if enabled in the Lock Status Register 8 (LOCK_STAT_8) which is read +from the last sector of the flash on boot. However, this mass_erase lock +protection can be bypassed and this command does so automatically. + +In the same LOCK_STAT_8 the flash and RAM access from SWD can be disabled by +setting two bits in this register. After a mass_erase, all the bits of the +flash would be set, making it the default to restrict SWD access to the flash +and RAM regions. This new after erase LOCK_STAT_8 value only takes effect after +being read from flash on the next reboot for example. After a mass_erase the +LOCK_STAT_8 register is changed by the hardware to allow access to flash and +RAM regardless of the value on flash, but only right after a mass_erase and +until the next boot. Therefore it is possible to perform a mass_erase, program +a new image, verify it and then reboot to a valid image that's locked from the +SWD access. + +The @command{qn908x mass_erase} command clears the bits that would be loaded +from the flash into LOCK_STAT_8 after erasing the whole chip to allow SWD +access for debugging or re-flashing an image without a mass_erase by default. +If the image being programmed also programs the last page of the flash with its +own settings, this mass_erase behavior will interfere with that write since a +new erase of at least the last page would need to be performed before writing +to it again. For this reason the optional @option{keep_lock} argument can be +used to leave the flash and RAM lock set. For development environments, the +default behavior is desired. + +The mass erase locking mechanism is independent from the individual page +locking bits, so it is possible that you can't erase a given page that is +locked and you can't unprotect that page because the locking bits are also +locked, but can still mass erase the whole flash. +@end deffn +@end deffn + +@deffn {Flash Driver} {rp2xxx} +Supports RP2040 "Raspberry Pi Pico" microcontroller and RP2350 Pico 2 +RP2040 is a dual-core device with two CM0+ cores. +RP2350 is a dual-core device with two slots switched to either Cortex-M33 +or Hazard3 RISC-V core. +Both cores share the same Flash/RAM/MMIO address space. +Non-volatile storage is achieved with an external QSPI flash; +a Boot ROM provides helper functions. @example -flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME +flash bank $_FLASHNAME rp2xxx $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME @end example + +@deffn {Command} {rp2xxx rom_api_call} fc [p0 [p1 [p2 [p3]]]] +A utility for calling ROM API function with two characters lookup code +@var{fc} and up to 4 optional parameters @var{p0 p1 p2 p3}. +The call is supported on the target where the flash bank is configured +(core0). +@end deffn + +@deffn {Command} {rp2xxx _switch_target} old_target new_target +A command used internally by rp2350.cfg when the core type is switched. +@end deffn +@end deffn + +@deffn {Flash Driver} {rsl10} +Supports Onsemi RSL10 microcontroller flash memory. Uses functions +stored in ROM to control flash memory interface. + +@example +flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME +@end example + +@deffn {Command} {rsl10 lock} key1 key2 key3 key4 +Writes @var{key1 key2 key3 key4} words to @var{0x81044 0x81048 0x8104c +0x8050}. Locks debug port by writing @var{0x4C6F634B} to @var{0x81040}. + +To unlock use the @command{rsl10 unlock key1 key2 key3 key4} command. +@end deffn + +@deffn {Command} {rsl10 unlock} key1 key2 key3 key4 +Unlocks debug port, by writing @var{key1 key2 key3 key4} words to +registers through DAP, and clears @var{0x81040} address in flash to 0x1. +@end deffn + +@deffn {Command} {rsl10 mass_erase} +Erases all unprotected flash sectors. +@end deffn @end deffn @deffn {Flash Driver} {sim3x} @@ -7534,12 +8022,10 @@ applied to all of them. @end deffn @deffn {Flash Driver} {stm32f1x} -All members of the STM32F0, STM32F1 and STM32F3 microcontroller families -from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller -families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores. -The driver also works with GD32VF103 powered by RISC-V core. -The driver automatically recognizes a number of these chips using -the chip identification register, and autoconfigures itself. +This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics. +The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice. +The driver also supports the APM32F0 and APM32F1 series from Geehy Semiconductor. +The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @example flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME @@ -7600,6 +8086,7 @@ The @var{num} parameter is a value shown by @command{flash banks}. @deffn {Flash Driver} {stm32f2x} All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M3/M4/M7 cores. +The driver also works for the APM32F4 series from Geehy Semiconductor. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @@ -7771,7 +8258,7 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @deffn {Flash Driver} {stm32l4x} -All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL +All members of the STM32 C0, G0, G4, L4, L4+, L5, U0, U5, WB and WL microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M0+, M4 and M33 cores. The driver automatically recognizes a number of these chips using @@ -7839,7 +8326,7 @@ The above example will read out the FLASH_OPTR register which contains the RDP option byte, Watchdog configuration, BOR level etc. @end deffn -@deffn {Command} {stm32l4x option_write} num reg_offset reg_mask +@deffn {Command} {stm32l4x option_write} num reg_offset value [reg_mask] Write an option byte register of the stm32l4x device. The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset} is the register offset of the Option byte to write, and @var{reg_mask} is the mask @@ -8526,7 +9013,7 @@ OpenOCD implements numerous ways to program the target flash, whether internal o Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB}, or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}. -@*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage. +@*To simplify using the flash commands directly a Tcl script is available that handles the programming and verify stage. OpenOCD will program/verify/reset the target and optionally shutdown. The script is executed as follows and by default the following actions will be performed. @@ -8570,47 +9057,175 @@ Accordingly, both are called PLDs here. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND), OpenOCD maintains a list of PLDs available for use in various commands. -Also, each such PLD requires a driver. +Also, each such PLD requires a driver. PLD drivers may also be needed to program +SPI flash connected to the FPGA to store the bitstream (@xref{jtagspi} for details). -They are referenced by the number shown by the @command{pld devices} command, -and new PLDs are defined by @command{pld device driver_name}. +They are referenced by the name which was given when the pld was created or +the number shown by the @command{pld devices} command. +New PLDs are defined by @command{pld create pld_name driver_name -chain-position tap_name [driver_options]}. -@deffn {Config Command} {pld device} driver_name tap_name [driver_options] -Defines a new PLD device, supported by driver @var{driver_name}, -using the TAP named @var{tap_name}. -The driver may make use of any @var{driver_options} to configure its -behavior. +@deffn {Config Command} {pld create} pld_name driver_name -chain-position tap_name [driver_options] +Creates a new PLD device, supported by driver @var{driver_name}, +assigning @var{pld_name} for further reference. +@code{-chain-position} @var{tap_name} names the TAP +used to access this target. +The driver may make use of any @var{driver_options} to configure its behavior. @end deffn @deffn {Command} {pld devices} -Lists the PLDs and their numbers. +List the known PLDs with their name. @end deffn -@deffn {Command} {pld load} num filename -Loads the file @file{filename} into the PLD identified by @var{num}. +@deffn {Command} {pld load} pld_name filename +Loads the file @file{filename} into the PLD identified by @var{pld_name}. The file format must be inferred by the driver. @end deffn @section PLD/FPGA Drivers, Options, and Commands -Drivers may support PLD-specific options to the @command{pld device} -definition command, and may also define commands usable only with +Drivers may support PLD-specific options to the @command{pld create} +command, and may also define commands usable only with that particular type of PLD. -@deffn {FPGA Driver} {virtex2} [no_jstart] +@deffn {FPGA Driver} {virtex2} [@option{-no_jstart}] Virtex-II is a family of FPGAs sold by Xilinx. +This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices. It supports the IEEE 1532 standard for In-System Configuration (ISC). -If @var{no_jstart} is non-zero, the JSTART instruction is not used after +If @var{-no_jstart} is given, the JSTART instruction is not used after loading the bitstream. While required for Series2, Series3, and Series6, it breaks bitstream loading on Series7. -@deffn {Command} {virtex2 read_stat} num +@example +openocd -f board/digilent_zedboard.cfg -c "init" \ + -c "pld load 0 zedboard_bitstream.bit" +@end example + + +@deffn {Command} {virtex2 read_stat} pld_name Reads and displays the Virtex-II status register (STAT) -for FPGA @var{num}. +for FPGA @var{pld_name}. +@end deffn + +@deffn {Command} {virtex2 set_instr_codes} pld_name cfg_out cfg_in jprogb jstart jshutdown [user1 [user2 [user3 [user4]]]] +Change values for boundary scan instructions. Default are values for Virtex 2, devices Virtex 4/5/6 and +SSI devices are using different values. +@var{pld_name} is the name of the pld device. +@var{cfg_out} is the value used to select CFG_OUT instruction. +@var{cfg_in} is the value used to select CFG_IN instruction. +@var{jprogb} is the value used to select JPROGRAM instruction. +@var{jstart} is the value used to select JSTART instruction. +@var{jshutdown} is the value used to select JSHUTDOWN instruction. +@var{user1} to @var{user4} are the intruction used to select the user registers USER1 to USER4. +@end deffn + +@deffn {Command} {virtex2 set_user_codes} pld_name user1 [user2 [user3 [user4]]] +Change values for boundary scan instructions selecting the registers USER1 to USER4. +Description of the arguments can be found at command @command{virtex2 set_instr_codes}. +@end deffn + +@deffn {Command} {virtex2 refresh} pld_name +Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. program. +@end deffn +@end deffn + + + +@deffn {FPGA Driver} {lattice} [@option{-family} <name>] +The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice are supported. +This driver can be used to load the bitstream into the FPGA or read the status register and read/write the usercode register. + +For the option @option{-family} @var{name} is one of @var{ecp2 ecp3 ecp5 certus}. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices). + +@deffn {Command} {lattice read_status} pld_name +Reads and displays the status register +for FPGA @var{pld_name}. +@end deffn + +@deffn {Command} {lattice read_user} pld_name +Reads and displays the user register +for FPGA @var{pld_name}. +@end deffn + +@deffn {Command} {lattice write_user} pld_name val +Writes the user register. +for FPGA @var{pld_name} with value @var{val}. @end deffn + +@deffn {Command} {lattice set_preload} pld_name length +Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices). +The load command for the FPGA @var{pld_name} will use a length for the preload of @var{length}. +@end deffn + +@deffn {Command} {lattice refresh} pld_name +Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a program. +@end deffn +@end deffn + + +@deffn {FPGA Driver} {efinix} [@option{-family} <name>] +Both families (Trion and Titanium) sold by Efinix are supported as both use the same protocol for In-System Configuration. +This driver can be used to load the bitstream into the FPGA. +For the option @option{-family} @var{name} is one of @var{trion|titanium}. +@end deffn + + +@deffn {FPGA Driver} {intel} @option{-family} <name> +This driver can be used to load the bitstream into Intel (former Altera) FPGAs. +The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10 and Arria II are supported. +@c Arria V and Arria 10, MAX II, MAX V, MAX10) + +The option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}. + +As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated +from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|} + +Creates a new PLD device, an FPGA of the Cyclone III family, using the TAP named @verb{|cycloneiii.tap|}: +@example +pld create cycloneiii.pld intel -chain-position cycloneiii.tap -family cycloneiii +@end example + +@deffn {Command} {intel set_bscan} pld_name len +Set boundary scan register length of FPGA @var{pld_name} to @var{len}. This is needed because the +length can vary between chips with the same JTAG ID. @end deffn +@deffn {Command} {intel set_check_pos} pld_name pos +Selects the position @var{pos} in the boundary-scan register. The bit at this +position is checked after loading the bitstream and must be '1', which is the case when no error occurred. +With a value of -1 for @var{pos} the check will be omitted. +@end deffn +@end deffn + + +@deffn {FPGA Driver} {gowin} +This driver can be used to load the bitstream into FPGAs from Gowin. +It is possible to program the SRAM. Programming the flash is not supported. +The files @verb{|.fs|} and @verb{|.bin|} generated by Gowin FPGA Designer are supported. + +@deffn {Command} {gowin read_status} pld_name +Reads and displays the status register +for FPGA @var{pld_name}. +@end deffn + +@deffn {Command} {gowin read_user} pld_name +Reads and displays the user register +for FPGA @var{pld_name}. +@end deffn + +@deffn {Command} {gowin refresh} pld_name +Load the bitstream from external memory for +FPGA @var{pld_name}. A.k.a. reload. +@end deffn +@end deffn + + +@deffn {FPGA Driver} {gatemate} +This driver can be used to load the bitstream into GateMate FPGAs form CologneChip. +The files @verb{|.bit|} and @verb{|.cfg|} both generated by p_r tool from CologneChip are supported. +@end deffn + + @node General Commands @chapter General Commands @cindex commands @@ -8636,7 +9251,7 @@ command. All output is relayed through the GDB session. @item @b{Machine Interface} The Tcl interface's intent is to be a machine interface. The default Tcl -port is 5555. +port is 6666. @end itemize @@ -8680,7 +9295,7 @@ non-zero exit code to the parent process. If user types CTRL-C or kills OpenOCD, the command @command{shutdown} will be automatically executed to cause OpenOCD to exit. -It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a +It is possible to specify, in the Tcl list @var{pre_shutdown_commands} , a set of commands to be automatically executed before @command{shutdown} , e.g.: @example lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@} @@ -8717,12 +9332,13 @@ echo "Downloading kernel -- please wait" @end example @end deffn -@deffn {Command} {log_output} [filename | "default"] -Redirect logging to @var{filename} or set it back to default output; -the default log output channel is stderr. +@deffn {Command} {log_output} [filename | 'default'] +Redirect logging to @var{filename}. If used without an argument or +@var{filename} is set to 'default' log output channel is set to +stderr. @end deffn -@deffn {Command} {add_script_search_dir} [directory] +@deffn {Command} {add_script_search_dir} directory Add @var{directory} to the file/script search path. @end deffn @@ -8858,6 +9474,18 @@ read_memory 0x20000000 32 2 @end example @end deffn +@deffn {Command} {debug_reason} +Displays the current debug reason: +@code{debug-request}, +@code{breakpoint}, +@code{watchpoint}, +@code{watchpoint-and-breakpoint}, +@code{single-step}, +@code{target-not-halted}, +@code{program-exit}, +@code{exception-catch} or @code{undefined}. +@end deffn + @deffn {Command} {halt} [ms] @deffnx {Command} {wait_halt} [ms] The @command{halt} command first sends a halt request to the target, @@ -8896,12 +9524,19 @@ power consumption (because the CPU is needlessly clocked). @deffn {Command} {resume} [address] Resume the target at its current code position, or the optional @var{address} if it is provided. -OpenOCD will wait 5 seconds for the target to resume. + +@b{NOTE:} targets are expected to temporary disable breakpoints +if they match the address of the current code position +or the @var{address} provided by user. @end deffn @deffn {Command} {step} [address] Single-step the target at its current code position, or the optional @var{address} if it is provided. + +@b{NOTE:} targets are expected to temporary disable breakpoints +if they match the address of the current code position +or the @var{address} provided by user. @end deffn @anchor{resetcommand} @@ -9028,7 +9663,7 @@ Loads an image stored in memory by @command{fast_load_image} to the current target. Must be preceded by fast_load_image. @end deffn -@deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}] +@deffn {Command} {fast_load_image} filename [address [@option{bin}|@option{ihex}|@option{elf}|@option{s19} [@option{min_addr} [@option{max_length}]]]] Normally you should be using @command{load_image} or GDB load. However, for testing purposes or when I/O overhead is significant(OpenOCD running on an embedded host), storing the image in memory and uploading the image to the target @@ -9039,8 +9674,10 @@ target programming performance as I/O and target programming can easily be profi separately. @end deffn -@deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}] -Load image from file @var{filename} to target memory offset by @var{address} from its load address. +@deffn {Command} {load_image} filename [address [@option{bin}|@option{ihex}|@option{elf}|@option{s19} [@option{min_addr} [@option{max_length}]]]] +Load image from file @var{filename} to target memory. +If an @var{address} is specified, it is used as an offset to the file format +defined addressing (e.g. @option{bin} file is loaded at that address). The file format may optionally be specified (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}). In addition the following arguments may be specified: @@ -9064,15 +9701,21 @@ The file format may optionally be specified (@option{bin}, @option{ihex}, or @option{elf}) @end deffn -@deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}] -Verify @var{filename} against target memory starting at @var{address}. +@deffn {Command} {verify_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]] +Verify @var{filename} against target memory. +If an @var{address} is specified, it is used as an offset to the file format +defined addressing (e.g. @option{bin} file is compared against memory starting +at that address). The file format may optionally be specified (@option{bin}, @option{ihex}, or @option{elf}) This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare. @end deffn -@deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}] -Verify @var{filename} against target memory starting at @var{address}. +@deffn {Command} {verify_image_checksum} filename [address [@option{bin}|@option{ihex}|@option{elf}]] +Verify @var{filename} against target memory. +If an @var{address} is specified, it is used as an offset to the file format +defined addressing (e.g. @option{bin} file is compared against memory starting +at that address). The file format may optionally be specified (@option{bin}, @option{ihex}, or @option{elf}) This perform a comparison using a CRC checksum only @@ -9088,12 +9731,14 @@ hardware support for a handful of code breakpoints and data watchpoints. In addition, CPUs almost always support software breakpoints. -@deffn {Command} {bp} [address len [@option{hw}]] +@deffn {Command} {bp} [address [asid] len [@option{hw} | @option{hw_ctx}]] With no parameters, lists all active breakpoints. Else sets a breakpoint on code execution starting at @var{address} for @var{length} bytes. -This is a software breakpoint, unless @option{hw} is specified -in which case it will be a hardware breakpoint. +This is a software breakpoint, unless @option{hw} or @option{hw_ctx} +is specified in which case it will be a hardware, context or hybrid breakpoint. +The context and hybrid breakpoints require an additional parameter @var{asid}: +address space identifier. (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch}, for similar mechanisms that do not consume hardware breakpoints.) @@ -9103,11 +9748,11 @@ for similar mechanisms that do not consume hardware breakpoints.) Remove the breakpoint at @var{address} or all breakpoints. @end deffn -@deffn {Command} {rwp} address -Remove data watchpoint on @var{address} +@deffn {Command} {rwp} @option{all} | address +Remove data watchpoint on @var{address} or all watchpoints. @end deffn -@deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]] +@deffn {Command} {wp} [address length [(@option{r}|@option{w}|@option{a}) [value [mask]]]] With no parameters, lists all active watchpoints. Else sets a data watchpoint on data from @var{address} for @var{length} bytes. The watch point is an "access" watchpoint unless @@ -9149,11 +9794,12 @@ Channels are exposed via raw TCP/IP connections. One or more RTT servers can be assigned to each channel to make them accessible to an unlimited number of TCP/IP connections. -@deffn {Command} {rtt setup} address size ID +@deffn {Command} {rtt setup} address size [ID] Configure RTT for the currently selected target. Once RTT is started, OpenOCD searches for a control block with the identifier @var{ID} starting at the memory address @var{address} within the next @var{size} bytes. +ID defaults to the string "SEGGER RTT" @end deffn @deffn {Command} {rtt start} @@ -9181,8 +9827,9 @@ Return a list of all channels and their properties as Tcl list. The list can be manipulated easily from within scripts. @end deffn -@deffn {Command} {rtt server start} port channel -Start a TCP server on @var{port} for the channel @var{channel}. +@deffn {Command} {rtt server start} port channel [message] +Start a TCP server on @var{port} for the channel @var{channel}. When +@var{message} is not empty, it will be sent to a client when it connects. @end deffn @deffn {Command} {rtt server stop} port @@ -9195,7 +9842,7 @@ on the target device. @example resume -rtt setup 0x20000000 2048 "SEGGER RTT" +rtt setup 0x20000000 2048 rtt start rtt server start 9090 0 @@ -9212,13 +9859,15 @@ TCP/IP port 9090. @deffn {Command} {profile} seconds filename [start end] Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling. -Saves up to 10000 samples in @file{filename} using ``gmon.out'' +Saves up to 1000000 samples in @file{filename} using ``gmon.out'' format. Optional @option{start} and @option{end} parameters allow to limit the address range. @end deffn -@deffn {Command} {version} -Displays a string identifying the version of this OpenOCD server. +@deffn {Command} {version} [git] +Returns a string identifying the version of this OpenOCD server. +With option @option{git}, it returns the git version obtained at compile time +through ``git describe''. @end deffn @deffn {Command} {virt2phys} virtual_address @@ -9226,14 +9875,20 @@ Requests the current target to map the specified @var{virtual_address} to its corresponding physical address, and displays the result. @end deffn -@deffn {Command} {add_help_text} 'command_name' 'help-string' +@deffn {Command} {add_help_text} command_name help_string Add or replace help text on the given @var{command_name}. @end deffn -@deffn {Command} {add_usage_text} 'command_name' 'help-string' +@deffn {Command} {add_usage_text} command_name help_string Add or replace usage text on the given @var{command_name}. @end deffn +@deffn {Command} {ms} +Returns current time since the Epoch in ms +(See: @url{https://en.wikipedia.org/wiki/Epoch_(computing)}). +Useful to compute delays in Tcl. +@end deffn + @node Architecture and Core Commands @chapter Architecture and Core Commands @cindex Architecture Specific Commands @@ -9548,7 +10203,7 @@ of the CTI. @deffn {Command} {cti names} Prints a list of names of all CTI objects created. This command is mainly -useful in TCL scripting. +useful in Tcl scripting. @end deffn @section Generic ARM @@ -9619,14 +10274,14 @@ requests by using a special SVC instruction that is trapped at the Supervisor Call vector by OpenOCD. @end deffn -@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port> -[@option{debug}|@option{stdio}|@option{all}) +@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port> [@option{debug}|@option{stdio}|@option{all}]) @cindex ARM semihosting Redirect semihosting messages to a specified TCP port. This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE) semihosting operations to the specified TCP port. The command allows to select which type of operations to redirect (debug, stdio, all (default)). + Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected. @end deffn @@ -10083,10 +10738,6 @@ Display/set the current core displayed in GDB Selects whether interrupts will be processed when single stepping @end deffn -@deffn {Command} {cache_config l2x} [base way] -configure l2x cache -@end deffn - @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]] Dump the MMU translation table from TTB0 or TTB1 register, or from physical memory location @var{address}. When dumping the table from @var{address}, print at most @@ -10192,7 +10843,7 @@ protocol used for trace data: @end itemize @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler, -a TCL string which is evaluated when the event is triggered. The events +a Tcl string which is evaluated when the event is triggered. The events @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable} are defined for TPIU/SWO. A typical use case for the event @code{pre-enable} is to enable the trace clock @@ -10204,7 +10855,7 @@ the destination of the trace data: @item @option{external} -- configure TPIU/SWO to let user capture trace output externally, either with an additional UART or with a logic analyzer (default); @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data -and forward it to @command{tcl_trace} command; +and forward it to @command{tcl trace} command; @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather trace data, open a TCP server at port @var{port} and send the trace data to each connected client; @@ -10275,7 +10926,7 @@ baud with our custom divisor to get 12MHz) @item OpenOCD invocation line: @example openocd -f interface/stlink.cfg \ --c "transport select hla_swd" \ +-c "transport select swd" \ -f target/stm32l1.cfg \ -c "stm32l1.tpiu configure -protocol uart" \ -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \ @@ -10413,6 +11064,16 @@ the target, the exception catch must be disabled again with @command{$target_nam Issuing the command without options prints the current configuration. @end deffn +@deffn {Command} {$target_name pauth} [@option{off}|@option{on}] +Enable or disable pointer authentication features. +When pointer authentication is used on ARM cores, GDB asks GDB servers for an 8-bytes mask to remove signature bits added by pointer authentication. +If this feature is enabled, OpenOCD provides GDB with an 8-bytes mask. +Pointer authentication feature is broken until gdb 12.1, going to be fixed. +Consider using a newer version of gdb if you want to enable pauth feature. +The default configuration is @option{off}. +@end deffn + + @section EnSilica eSi-RISC Architecture eSi-RISC is a highly configurable microprocessor architecture for embedded systems @@ -10668,6 +11329,78 @@ addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system @end deffn +@section MIPS Architecture +@cindex microMIPS +@cindex MIPS32 +@cindex MIPS64 + +@uref{http://mips.com/, MIPS} is a simple, streamlined, highly scalable RISC +architecture. The architecture is evolving over time, from MIPS I~V to +MIPS release 1~6 iterations, the architecture is now able to handle various tasks +with different ASEs, including SIMD(MSA), DSP, VZ, MT and more. +MIPS32 supports 32-bit programs while MIPS64 can support both 32-bit and 64-bit programs. + +@subsection MIPS Terminology + +The term ASE means Application-Specific Extension, ASEs provide features that +improve the efficiency and performance of certain workloads, such as +digital signal processing(DSP), Virtualization(VZ), Multi-Threading(MT), +SIMD(MSA) and more. + +MIPS Cores use Coprocessors(CPx) to configure their behaviour or to let software +know the capabilities of current CPU, the main Coprocessor is CP0, containing 32 +registers with a maximum select number of 7. + +@subsection MIPS FPU & Vector Registers + +MIPS processors does not all comes with FPU co-processor, and when it does, the FPU +appears as Coprocessor 1 whereas the Coprocessor 0 is for the main processor. + +Most of MIPS FPUs are 64 bits, IEEE 754 standard, and they provides both 32-bit +single precision and 64-bit double precision calculations. Fixed point format +calculations are also provided with both 32 and 64-bit modes. + +The MIPS SIMD Architecture(MSA) operates on 32 128-bit wide vector registers. +If both MSA and the scalar floating-point unit (FPU) are present, the 128-bit MSA +vector registers extend and share the 64-bit FPU registers. MSA and FPU can not be +both present, unless the FPU has 64-bit floating-point register. + +@subsection MIPS Configuration Commands + +@deffn {Command} {mips32 cpuinfo} +Displays detailed information about current CPU core. This includes core type, +vendor, instruction set, cache size, and other relevant details. +@end deffn + +@deffn {Config Command} {mips32 scan_delay} [nanoseconds] +Display or set scan delay in nano seconds. A value below 2_000_000 will set the +scan delay into legacy mode. +@end deffn + +@deffn {Config Command} {mips32 cp0} [[reg_name|regnum select] [value]] +Displays or sets coprocessor 0 register by register number and select or their name. +This command shows all available cp0 register if no arguments are provided. + +For common MIPS Coprocessor 0 registers, you can find the definitions of them +on MIPS Privileged Resource Architecture Documents(MIPS Document MD00090). + +For core specific cp0 registers, you can find the definitions of them on Core +Specific Software User's Manual(SUM), for example, MIPS M5150 Software User Manual +(MD00980). +@end deffn + +@deffn {Command} {mips32 ejtag_reg} +Reads EJTAG Registers for inspection. + +EJTAG Register Specification could be found in MIPS Document MD00047F, for +core specific EJTAG Register definition, please check Core Specific SUM manual. +@end deffn + +@deffn {Command} {mips32 dsp} [[register_name] [value]] +Displays all DSP registers' contents or get/set value by register name. Will display +an error if current CPU does not support DSP. +@end deffn + @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG @@ -10770,6 +11503,16 @@ $_TARGETNAME expose_custom 32=myregister @end example @end deffn +@deffn {Command} {riscv info} +Displays some information OpenOCD detected about the target. +@end deffn + +@deffn {Command} {riscv reset_delays} [wait] +OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid +encountering the target being busy. This command resets those learned values +after `wait` scans. It's only useful for testing OpenOCD itself. +@end deffn + @deffn {Command} {riscv set_command_timeout_sec} [seconds] Set the wall-clock timeout (in seconds) for individual commands. The default should work fine for all but the slowest targets (eg. simulators). @@ -10780,12 +11523,7 @@ Set the maximum time to wait for a hart to come out of reset after reset is deasserted. @end deffn -@deffn {Command} {riscv set_scratch_ram} none|[address] -Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'. -This is used to access 64-bit floating point registers on 32-bit targets. -@end deffn - -@deffn Command {riscv set_mem_access} method1 [method2] [method3] +@deffn {Command} {riscv set_mem_access} method1 [method2] [method3] Specify which RISC-V memory access method(s) shall be used, and in which order of priority. At least one method must be specified. @@ -10837,9 +11575,35 @@ When utilizing version 0.11 of the RISC-V Debug Specification, and DBUS registers, respectively. @end deffn +@deffn {Command} {riscv smp} [on|off] +Display, enable or disable SMP handling mode. This command is needed only if +user wants to temporary @b{disable} SMP handling for an existing SMP group +(see @code{aarch64 smp} for additional information). To define an SMP +group the command @code{target smp} should be used. +@end deffn + +@deffn {Command} {riscv smp_gdb} [core_id] +Display/set the current core displayed in GDB. This is needed only if +@code{riscv smp} was used. +@end deffn + @deffn {Command} {riscv use_bscan_tunnel} value -Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of -the DM transport TAP's instruction register to enable. Supply a value of 0 to disable. +Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the +width of the DM transport TAP's instruction register to enable. Supply a +value of 0 to disable. + +This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement +it, but currently there is no good documentation on it. In a nutshell, this +feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming +hardware is present and it is hooked up to the Xilinx USER4 IR) and +encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A +tunneled DR scan consists of: +@enumerate +@item 1 bit that selects IR when 0, or DR when 1 +@item 7 bits that encode the width of the desired tunneled scan +@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain. +@item 3 bits of zero that the tunnel uses to go back to idle state. +@end enumerate @end deffn @deffn {Command} {riscv set_ebreakm} on|off @@ -10903,7 +11667,7 @@ capabilities than most of the other processors and in addition there is an extension interface that allows SoC designers to add custom registers and instructions. For the OpenOCD that mostly means that set of core and AUX registers in target will vary and is not fixed for a particular processor -model. To enable extensibility several TCL commands are provided that allow to +model. To enable extensibility several Tcl commands are provided that allow to describe those optional registers in OpenOCD configuration files. Moreover those commands allow for a dynamic target features discovery. @@ -11024,33 +11788,157 @@ OpenOCD supports debugging STM8 through the STMicroelectronics debug protocol SWIM, @pxref{swimtransport,,SWIM}. @section Xtensa Architecture -Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture -that can easily scale from a tiny, cache-less controller or task engine to a high-performance -SIMD/VLIW DSP provided by Cadence. -@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}. -OpenOCD supports generic Xtensa processors implementation which can be customized by -simply providing vendor-specific core configuration which controls every configurable +Xtensa is a highly-customizable, user-extensible microprocessor and DSP +architecture for complex embedded systems provided by Cadence Design +Systems, Inc. See the +@uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP} +website for additional information and documentation. + +OpenOCD supports generic Xtensa processor implementations which can be customized by +providing a core-specific configuration file which describes every enabled Xtensa architecture option, e.g. number of address registers, exceptions, reduced -size instructions support, memory banks configuration etc. Also OpenOCD supports SMP -configurations for Xtensa processors with any number of cores and allows to configure -their debug signals interconnection (so-called "break/stall networks") which control how -debug signals are distributed among cores. Xtensa "break networks" are compatible with -ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD -uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of +size instructions support, memory banks configuration etc. OpenOCD also supports SMP +configurations for Xtensa processors with any number of cores and allows configuring +their debug interconnect (termed "break/stall networks"), which control how debug +signals are distributed among cores. Xtensa "break networks" are compatible with +ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets +as well as several Espressif Xtensa-based chips from the @uref{https://www.espressif.com/en/products/socs, ESP32 family}. -@subsection General Xtensa Commands +OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa +Debug Module (XDM), which provides external connectivity either through a +traditional JTAG interface or an ARM DAP interface. If used, the DAP interface +can control Xtensa targets through JTAG or SWD probes. + +@subsection Xtensa Core Configuration + +Due to the high level of configurability in Xtensa cores, the Xtensa target +configuration comprises two categories: + +@enumerate +@item Base Xtensa support common to all core configurations, and +@item Core-specific support as configured for individual cores. +@end enumerate + +All common Xtensa support is built into the OpenOCD Xtensa target layer and +is enabled through a combination of Tcl scripts: the target-specific +@file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg}, +similar to other target architectures. + +Importantly, core-specific configuration information must be provided by +the user, and takes the form of an @file{xtensa-core-XXX.cfg} Tcl script that +defines the core's configurable features through a series of Xtensa +configuration commands (detailed below). + +This core-specific @file{xtensa-core-XXX.cfg} file is typically either: + +@itemize @bullet +@item Located within the Xtensa core configuration build as +@file{src/config/xtensa-core-openocd.cfg}, or +@item Generated by running the command @code{xt-gdb --dump-oocd-config} +from the Xtensa processor tool-chain's command-line tools. +@end itemize + +NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware +connected to OpenOCD. + +Some example Xtensa configurations are bundled with OpenOCD for reference: +@enumerate +@item Cadence Palladium VDebug emulation target. The user can combine their +@file{xtensa-core-XXX.cfg} with the provided +@file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design. +@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are: +@itemize @bullet +@item @file{board/xtensa-rt685-ext.cfg} +@item @file{target/xtensa-core-nxp_rt600.cfg} +@end itemize +Additional information is available by searching for "i.MX RT600 Evaluation Kit" +on @url{https://www.nxp.com}. +@end enumerate + +@subsection Xtensa Configuration Commands + +@deffn {Config Command} {xtensa xtdef} (@option{LX}|@option{NX}) +Configure the Xtensa target architecture to LX or NX. Currently, Xtensa LX support +is limited to LX6 and newer cores. +@end deffn + +@deffn {Config Command} {xtensa xtopt} option value +Configure Xtensa target options that are relevant to the debug subsystem. +@var{option} is one of: @option{arnum}, @option{windowed}, +@option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints}, +@option{excmlevel}, @option{intlevels}, @option{debuglevel}, +@option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with +the exact range determined by each particular option. + +NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while +others may be common to both but have different valid ranges. +@end deffn + +@deffn {Config Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes +Configure Xtensa target memory. Memory type determines access rights, +where RAMs are read/write while ROMs are read-only. @var{baseaddr} and +@var{bytes} are both integers, typically hexadecimal and decimal, respectively. + +NOTE: Some Xtensa memory types, such as system RAM/ROM or MMIO/device regions, +can be added or modified after the Xtensa core has been generated. Additional +@code{xtensa xtmem} definitions should be manually added to xtensa-core-XXX.cfg +to keep OpenOCD's target address map consistent with the Xtensa configuration. +@end deffn + +@deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback] +Configure Xtensa processor cache. All parameters are required except for +the optional @option{writeback} parameter; all are integers. +@end deffn + +@deffn {Config Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly +Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access +and/or control cacheability of specific address ranges, but are lighter-weight +than a full traditional MMU. All parameters are required; all are integers. +@end deffn + +@deffn {Config Command} {xtensa xtmmu} numirefillentries numdrefillentries +(Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both +parameters are required; both are integers. +@end deffn + +@deffn {Config Command} {xtensa xtregs} numregs +Configure the total number of registers for the Xtensa core. Configuration +logic expects to subsequently process this number of @code{xtensa xtreg} +definitions. @var{numregs} is an integer. +@end deffn + +@deffn {Config Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general] +Configure the type of register map used by GDB to access the Xtensa core. +Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while +Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an +additional, optional integer parameter @option{numgregs}, which specifies the number +of general registers used in handling g/G packets. +@end deffn + +@deffn {Config Command} {xtensa xtreg} name offset +Configure an Xtensa core register. All core registers are 32 bits wide, +while TIE and user registers may have variable widths. @var{name} is a +character string identifier while @var{offset} is a hexadecimal integer. +@end deffn + +@subsection Xtensa Operation Commands + +@deffn {Command} {xtensa maskisr} (@option{on}|@option{off}) +(Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step. +When masked, an interrupt that occurs during a step operation is handled and +its ISR is executed, with the user's debug session returning after potentially +executing many instructions. When unmasked, a triggered interrupt will result +in execution progressing the requested number of instructions into the relevant +vector/ISR code. +@end deffn @deffn {Command} {xtensa set_permissive} (0|1) By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check. When set to (1), skips access controls and address range check before read/write memory. @end deffn -@deffn {Command} {xtensa maskisr} (on|off) -Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off). -@end deffn - @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut] Configures debug signals connection ("break network") for currently selected core. @itemize @bullet @@ -11074,6 +11962,20 @@ This feature is not well implemented and tested yet. @end itemize @end deffn +@deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes> +Execute one arbitrary instruction provided as an ascii string. The string represents an integer +number of instruction bytes, thus its length must be even. The instruction can be of any width +that is valid for the Xtensa core configuration. +@end deffn + +@deffn {Command} {xtensa dm} (address) [value] +Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads +and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified +only for write accesses. +@end deffn + +@subsection Xtensa Performance Monitor Configuration + @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel] Enable and start performance counter. @itemize @bullet @@ -11093,6 +11995,8 @@ whether to count. Dump performance counter value. If no argument specified, dumps all counters. @end deffn +@subsection Xtensa Trace Configuration + @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]] Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution. This command also allows to specify the amount of data to capture after stop trigger activation. @@ -11111,6 +12015,80 @@ Stop current trace as started by the tracestart command. Dump trace memory to a file. @end deffn +@section Espressif Specific Commands + +@deffn {Command} {esp apptrace} (start <destination> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]]) +Starts +@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}. +Data will be stored to specified destination. Available destinations are: +@itemize @bullet +@item @code{file://<outfile>} - Save trace logs into file. +@item @code{tcp://<host>:<port>} - Send trace logs to tcp port on specified host. OpenOCD will act as a tcp client. +@item @code{con:} - Print trace logs to the stdout. +@end itemize +Other parameters will be same for each destination. +@itemize @bullet +@item @code{poll_period} - trace data polling period in ms. +@item @code{trace_size} - maximum trace data size. +Tracing will be stopped automatically when that amount is reached. +Use "-1" to disable the limitation. +@item @code{stop_tmo} - Data reception timeout in ms. +Tracing will be stopped automatically when no data is received within that period. +@item @code{wait4halt} - if non-zero then wait for target to be halted before tracing start. +@item @code{skip_size} - amount of tracing data to be skipped before writing it to destination. +@end itemize +@end deffn + +@deffn {Command} {esp apptrace} (stop) +Stops tracing started with above command. +@end deffn + +@deffn {Command} {esp apptrace} (status) +Requests ongoing tracing status. +@end deffn + +@deffn {Command} {esp apptrace} (dump file://<outfile>) +Dumps tracing data from target buffer. It can be useful to dump the latest data +buffered on target for post-mortem analysis. For example when target starts tracing automatically +w/o OpenOCD command and keeps only the latest data window which fit into the buffer. +@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}. +Data will be stored to specified destination. +@end deffn + +@deffn {Command} {esp sysview} (start file://<outfile1> [file://<outfile2>] [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]]) +Starts @uref{https://www.segger.com/products/development-tools/systemview/, SEGGER SystemView} +compatible tracing. Data will be stored to specified destination. +For dual-core chips traces from every core will be saved to separate files. +Resulting files can be open in "SEGGER SystemView" application. +@url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options} +The meaning of the arguments is identical to @command{esp apptrace start}. +@end deffn + +@deffn {Command} {esp sysview} (stop) +Stops SystremView compatible tracing started with above command. +@url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options} +@end deffn + +@deffn {Command} {esp sysview} (status) +Requests ongoing SystremView compatible tracing status. +@url{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#openocd-systemview-tracing-command-options} +@end deffn + +@deffn {Command} {esp sysview_mcore} (start file://<outfile> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]]) +This command is identical to @command{esp sysview start}, but uses Espressif multi-core extension to +@uref{https://www.segger.com/products/development-tools/systemview/, SEGGER SystemView} data format. +Data will be stored to specified destination. Tracing data from all cores are saved in the same file. +The meaning of the arguments is identical to @command{esp sysview start}. +@end deffn + +@deffn {Command} {esp sysview_mcore} (stop) +Stops Espressif multi-core SystremView tracing started with above command. +@end deffn + +@deffn {Command} {esp sysview_mcore} (status) +Requests ongoing Espressif multi-core SystremView tracing status. +@end deffn + @anchor{softwaredebugmessagesandtracing} @section Software Debug Messages and Tracing @cindex Linux-ARM DCC support @@ -11407,8 +12385,9 @@ way to represent JTAG test patterns in text files. In a debug session using JTAG for its transport protocol, OpenOCD supports running such test files. -@deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @ - [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}] +@deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{-quiet}] @ + [@option{-nil}] [@option{-progress}] [@option{-ignore_error}] @ + [@option{-noreset}] [@option{-addcycles @var{cyclecount}}] This issues a JTAG reset (Test-Logic-Reset) and then runs the SVF script from @file{filename}. @@ -11421,12 +12400,16 @@ Command options: specified by the SVF file with HIR, TIR, HDR and TDR commands; instead, calculate them automatically according to the current JTAG chain configuration, targeting @var{tapname}; -@item @option{[-]quiet} do not log every command before execution; -@item @option{[-]nil} ``dry run'', i.e., do not perform any operations +@item @option{-quiet} do not log every command before execution; +@item @option{-nil} ``dry run'', i.e., do not perform any operations on the real interface; -@item @option{[-]progress} enable progress indication; -@item @option{[-]ignore_error} continue execution despite TDO check +@item @option{-progress} enable progress indication; +@item @option{-ignore_error} continue execution despite TDO check errors. +@item @option{-noreset} omit JTAG reset (Test-Logic-Reset) before executing +content of the SVF file; +@item @option{-addcycles @var{cyclecount}} inject @var{cyclecount} number of +additional TCLK cycles after each SDR scan instruction; @end itemize @end deffn @@ -11485,40 +12468,103 @@ waveform generator. These are synthesize-able hardware descriptions of logic circuits in addition to software for control, visualization and further analysis. In a session using JTAG for its transport protocol, OpenOCD supports the function of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the -control-software. For more details see @url{http://ipdbg.org}. +control-software. The JTAG-Hub is the circuit which transfers the data from JTAG to the +different tools connected to the Hub. Hub implementations for most major FPGA vendors/families +are provided. For more details see @url{http://ipdbg.org}. -@deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}] -Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order. +@deffn {Command} {ipdbg create-hub} @var{hub_name} @option{-tap @var{tapname}} @option{-ir @var{ir_value} [@var{dr_length}]} [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}] +@deffnx {Command} {ipdbg create-hub} @var{hub_name} @option{-pld @var{pld_name} [@var{user}]} [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}] +Creates a IPDBG JTAG Hub. The created hub is later used to start, stop and configure IPDBG JTAG Host servers. +The first argument @var{hub_name} is the name of the created hub. It can be used later as a reference. + +The pld drivers are able to provide the tap and ir_value for the IPDBG JTAG-Host server. This will be used with the second variant with option @option{-pld}. Command options: @itemize @bullet -@item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start). +@item @var{hub_name} the name of the IPDBG hub. +This name is also used to create the object's command, referred to here +as @command{$hub_name}, and in other places where the Hub needs to be identified. + @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}. -@item @option{-hub @var{ir_value}} states that the JTAG hub is -reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}. -@item @option{-port @var{number}} tcp port number where the JTAG-Host is listening. -@item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub. -@item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a -specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an + +@item @option{-ir @var{ir_value}} states that the JTAG hub is +reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}. Also known as @verb{|USERx|} instructions. +The optional @var{dr_length} is the length of the dr. +Current JTAG-Hub implementation only supports dr_length=13, which is also the default value. + +@item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} To support more Hubs than USER registers in a single FPGA it is possible to +use a mechanism known as virtual-ir where the user data-register is reachable if there is a specific value in a second dr. +This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to shift data through vir can be configured. + +@item @option{-pld @var{pld_name} [@var{user}]} The defined driver for the pld @var{pld_name} is used to get the tap and user instruction. +The pld devices names can be shown by the command @command{pld devices}. With [@var{user}] one can select a different @verb{|USERx|}-Instruction. +If the IPDBG JTAG-Hub is used without modification the default value of 1 which selects the first @verb{|USERx|} instruction is adequate. +The @verb{|USERx|} instructions are vendor specific and don't change between families of the same vendor. +So if there's a pld driver for your vendor it should work with your FPGA even when the driver is not compatible with your device for the remaining features. +If your device/vendor is not supported you have to use the first variant. + +@end itemize + +@end deffn + +@deffn {Command} {$hub_name ipdbg start} @option{-tool @var{number}} @option{-port @var{number}} +Starts a IPDBG JTAG-Host server. The remaining arguments can be specified in any order. + +Command options: +@itemize @bullet +@item @option{-port @var{number}} tcp port number where the JTAG-Host will listen. The default is 4242 which is used when the option is not given. +@item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub. The default is 1 which is used when the option is not given. +@end itemize +@end deffn + +@deffn {Command} {$hub_name ipdbg stop} @option{-tool @var{number}} +Stops a IPDBG JTAG-Host server. +Command options: +@itemize @bullet +@item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub. The default is 1 which is used when the option is not given. @end itemize @end deffn Examples: @example -ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4 +ipdbg create-hub xc6s.ipdbghub -tap xc6s.tap -hub 0x02 +xc6s.ipdbghub ipdbg start -port 4242 -tool 4 @end example -Starts a server listening on tcp-port 4242 which connects to tool 4. +Creates a IPDBG Hub and starts a server listening on tcp-port 4242 which connects to tool 4. The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board). @example -ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1 +ipdbg create-hub max10m50.ipdbghub -tap max10m50.tap -hub 0x00C -vir +max10m50.ipdbghub ipdbg start -tool 1 -port 60000 @end example Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1). The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5). +@example +ipdbg create-hub xc7.ipdbghub -pld xc7.pld +xc7.ipdbghub ipdbg start -port 5555 -tool 0 +@end example +Starts a server listening on tcp-port 5555 which connects to tool 0 (data_up_0/data_down_0). +The TAP and ir value used to reach the JTAG Hub is given by the pld driver. + +@deffn {Command} {$hub_name queuing} @option{-size @var{size}} +Configure the queuing between IPDBG JTAG-Host and Hub. +The maximum possible queue size is 1024 which is also the default. + +@itemize @bullet +@item @option{-size @var{size}} max number of transfers in the queue. +@end itemize +@end deffn + +@example +bitbang.ibdbghub queuing -size 32 +@end example +Send a maximum of 32 transfers to the queue before executing them. + + @node Utility Commands @chapter Utility Commands @cindex Utility Commands @@ -11638,7 +12684,7 @@ target remote localhost:3333 A pipe connection is typically started as follows: @example target extended-remote | \ - openocd -c "gdb_port pipe; log_output openocd.log" + openocd -c "gdb port pipe; log_output openocd.log" @end example This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout). Using this method has the advantage of GDB starting/stopping OpenOCD for the debug @@ -11722,7 +12768,7 @@ using @command{gdb -x filename}. By default the target memory map is sent to GDB. This can be disabled by the following OpenOCD configuration option: @example -gdb_memory_map disable +gdb memory_map disable @end example For this to function correctly a valid flash configuration must also be set in OpenOCD. For faster performance you should also configure a valid @@ -11730,8 +12776,8 @@ working area. Informing GDB of the memory map of the target will enable GDB to protect any flash areas of the target and use hardware breakpoints by default. This means -that the OpenOCD option @command{gdb_breakpoint_override} is not required when -using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}. +that the OpenOCD option @command{gdb breakpoint_override} is not required when +using a memory map. @xref{gdbbreakpointoverride,,gdb breakpoint_override}. To view the configured memory map in GDB, use the GDB command @option{info mem}. All other unassigned addresses within GDB are treated as RAM. @@ -11742,7 +12788,7 @@ This can be changed to the old behaviour by using the following GDB command set mem inaccessible-by-default off @end example -If @command{gdb_flash_program enable} is also used, GDB will be able to +If @command{gdb flash_program enable} is also used, GDB will be able to program any flash memory using the vFlash interface. GDB will look at the target memory map when a load command is given, if any @@ -11781,9 +12827,9 @@ $_TARGETNAME configure -event gdb-attach @{@} @end example If any of installed flash banks does not support probe on running target, -switch off gdb_memory_map: +switch off gdb memory_map: @example -gdb_memory_map disable +gdb memory_map disable @end example Ensure GDB is configured without interrupt-on-connect. @@ -11792,7 +12838,7 @@ Some GDB versions set it by default, some does not. set remote interrupt-on-connect off @end example -If you switched gdb_memory_map off, you may want to setup GDB memory map +If you switched gdb memory_map off, you may want to setup GDB memory map manually or issue @command{set mem inaccessible-by-default off} Now you can issue GDB command @command{target extended-remote ...} and inspect memory @@ -11842,8 +12888,14 @@ Currently supported rtos's include: @item @option{RIOT} @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.) @item @option{Zephyr} +@item @option{rtkernel} @end itemize +At any time, it's possible to drop the selected RTOS using: +@example +$_TARGETNAME configure -rtos none +@end example + Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot be used by OpenOCD. Below is a list of the required symbols for each supported RTOS. @@ -11856,7 +12908,7 @@ _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count. @raggedright pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2, pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList, -uxCurrentNumberOfTasks, uxTopUsedPriority. +uxCurrentNumberOfTasks, uxTopUsedPriority, xSchedulerRunning. @end raggedright @item linux symbols init_task. @@ -11878,6 +12930,8 @@ _tcb_name_offset. @end raggedright @item Zephyr symbols _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size +@item rtkernel symbols +Multiple struct offsets. @end table For most RTOS supported the above symbols will be exported by default. However for @@ -11970,7 +13024,7 @@ Return information about the flash banks @item @b{capture} <@var{command}> Run <@var{command}> and return full log output that was produced during -its execution. Example: +its execution together with the command output. Example: @example > capture "reset init" @@ -11989,7 +13043,7 @@ OpenOCD provides a simple RPC server that allows to run arbitrary Tcl commands and receive the results. To access it, your application needs to connect to a configured TCP port -(see @command{tcl_port}). Then it can pass any string to the +(see @command{tcl port}). Then it can pass any string to the interpreter terminating it with @code{0x1a} and wait for the return value (it will be terminated with @code{0x1a} as well). This can be repeated as many times as desired without reopening the connection. @@ -12015,7 +13069,7 @@ type target_state state [state-name] type target_reset mode [reset-mode] @end verbatim -@deffn {Command} {tcl_notifications} [on/off] +@deffn {Command} {tcl notifications} [on/off] Toggle output of target notifications to the current Tcl RPC server. Only available from the Tcl RPC server. Defaults to off. @@ -12034,7 +13088,7 @@ Target trace data is emitted as a Tcl associative array in the following format. type target_trace data [trace-data-hex-encoded] @end verbatim -@deffn {Command} {tcl_trace} [on/off] +@deffn {Command} {tcl trace} [on/off] Toggle output of target trace data to the current Tcl RPC server. Only available from the Tcl RPC server. Defaults to off. @@ -12346,7 +13400,7 @@ learning Tcl, the intent of this chapter is to give you some idea of how the Tcl scripts work. This chapter is written with two audiences in mind. (1) OpenOCD users -who need to understand a bit more of how Jim-Tcl works so they can do +who need to understand a bit more of how Jim Tcl works so they can do something useful, and (2) those that want to add a new command to OpenOCD. @@ -12506,7 +13560,7 @@ Often many of those parameters are in @{curly-braces@} - thus the variables inside are not expanded or replaced until later. Remember that every Tcl command looks like the classic ``main( argc, -argv )'' function in C. In JimTCL - they actually look like this: +argv )'' function in C. In Jim Tcl - they actually look like this: @example int diff --git a/doc/usb_adapters/angie/584e_414f_angie.txt b/doc/usb_adapters/angie/584e_414f_angie.txt new file mode 100644 index 0000000000..6c25f43b3f --- /dev/null +++ b/doc/usb_adapters/angie/584e_414f_angie.txt @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +Bus 002 Device 105: ID 584e:414f NanoXplore, SAS. ANGIE Adapter +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x584e + idProduct 0x414f + bcdDevice 0.00 + iManufacturer 1 NanoXplore, SAS. + iProduct 2 ANGIE Adapter + iSerial 3 000001 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0047 + bNumInterfaces 2 + bConfigurationValue 1 + iConfiguration 1 NanoXplore, SAS. + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 JTAG Adapter + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x88 EP 8 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 diff --git a/doc/usb_adapters/cmsis_dap/03eb_2111_atmel_edbg.txt b/doc/usb_adapters/cmsis_dap/03eb_2111_atmel_edbg.txt new file mode 100644 index 0000000000..e4dd6cee0d --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/03eb_2111_atmel_edbg.txt @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Optional comment + +Bus 001 Device 006: ID 03eb:2111 Atmel Corp. Xplained Pro board debugger and programmer +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x03eb Atmel Corp. + idProduct 0x2111 Xplained Pro board debugger and programmer + bcdDevice 1.01 + iManufacturer 1 Atmel Corp. + iProduct 2 EDBG CMSIS-DAP + iSerial 3 ATMLxxxxxxxxxxxxxxxx + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0082 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 EDBG CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 35 + Report Descriptor: (length is 35) + Item(Global): Usage Page, data= [ 0x00 0xff ] 65280 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x00 0x02 ] 512 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x00 0x02 ] 512 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x04 ] 4 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Feature, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 6 EDBG Virtual COM Port + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + CDC Call Management: + bmCapabilities 0x03 + call management + use DataInterface + bDataInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 8 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 EDBG Data Gateway + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x87 EP 7 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 255 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 255 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/03eb_2169_atmel_edbg.txt b/doc/usb_adapters/cmsis_dap/03eb_2169_atmel_edbg.txt new file mode 100644 index 0000000000..1f7f26efd9 --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/03eb_2169_atmel_edbg.txt @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Optional comment + +Bus 001 Device 005: ID 03eb:2169 Atmel Corp. EDBG CMSIS-DAP +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x03eb Atmel Corp. + idProduct 0x2169 + bcdDevice 1.01 + iManufacturer 1 Atmel Corp. + iProduct 2 EDBG CMSIS-DAP + iSerial 3 ATMLxxxxxxxxxxxxxxxx + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0082 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 EDBG CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 35 + Report Descriptor: (length is 35) + Item(Global): Usage Page, data= [ 0x00 0xff ] 65280 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x00 0x02 ] 512 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x00 0x02 ] 512 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x04 ] 4 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Feature, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 6 EDBG Virtual COM Port + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + CDC Call Management: + bmCapabilities 0x03 + call management + use DataInterface + bDataInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 8 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x87 EP 7 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/04b4_f155_cypress_kitprog3.txt b/doc/usb_adapters/cmsis_dap/04b4_f155_cypress_kitprog3.txt new file mode 100644 index 0000000000..3109c6912a --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/04b4_f155_cypress_kitprog3.txt @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# KitProg3 Firmware 1.01 +# Has inconsistent class code 0 for CMSIS-DAP interface + +Bus 002 Device 017: ID 04b4:f155 Cypress Semiconductor Corp. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 ? + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 8 + idVendor 0x04b4 Cypress Semiconductor Corp. + idProduct 0xf155 + bcdDevice 1.01 + iManufacturer 1 Cypress Semiconductor + iProduct 6 KitProg3 CMSIS-DAP + iSerial 128 102015B003137400 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 130 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 11 KitProg3 CMSIS-DAP + bmAttributes 0x80 + (Bus Powered) + MaxPower 400mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 0 (Defined at Interface level) + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 6 KitProg3 CMSIS-DAP + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 No Subclass + bInterfaceProtocol 0 None + iInterface 12 KitProg3 bridge + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 43 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x07 EP 7 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 2 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 0 None + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 15 KitProg3 USBUART + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x02 + line coding and serial state + CDC Union: + bMasterInterface 2 + bSlaveInterface 3 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 3 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0008 1x 8 bytes + bInterval 2 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 Unused + bInterfaceProtocol 0 + iInterface 4 KitProg3 USBUART + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/0d28_0204_nxp_daplink.txt b/doc/usb_adapters/cmsis_dap/0d28_0204_nxp_daplink.txt new file mode 100644 index 0000000000..5141a1b6b8 --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/0d28_0204_nxp_daplink.txt @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: NXP FRDM-K64F + +Bus 001 Device 006: ID 0d28:0204 NXP ARM mbed +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0d28 NXP + idProduct 0x0204 ARM mbed + bcdDevice 10.00 + iManufacturer 1 ARM + iProduct 2 DAPLink CMSIS-DAP + iSerial 3 0240000031754e45002f00199485002b6461000097969900 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0082 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 7 USB_MSC + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 6 CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.00 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 33 + Report Descriptor: (length is 33) + Item(Global): Usage Page, data= [ 0x00 0xff ] 65280 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x01 ] 1 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Feature, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 4 mbed Serial Port + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 4 mbed Serial Port + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x03 + call management + use DataInterface + bDataInterface 2 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0010 1x 16 bytes + bInterval 32 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 5 mbed Serial Port + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/1a6a_2000_spansion_sk_fm4.txt b/doc/usb_adapters/cmsis_dap/1a6a_2000_spansion_sk_fm4.txt new file mode 100644 index 0000000000..368ec2a2b8 --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/1a6a_2000_spansion_sk_fm4.txt @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://en.opensuse.org/User:A_faerber/SK-FM4-176L-S6E2CC + +Bus 002 Device 009: ID 1a6a:2000 Spansion Inc. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.01 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x1a6a Spansion Inc. + idProduct 0x2000 + bcdDevice 1.60 + iManufacturer 1 Spansion + iProduct 2 Spansion CMSIS-DAP + COM Port + iSerial 0 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 107 + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x00 + (Missing must-be-set bit!) + (Bus Powered) + MaxPower 62mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 No Subclass + bInterfaceProtocol 0 None + iInterface 4 Spansion CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 29 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 5 Spansion USB Serial Port + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 10.01 + CDC ACM: + bmCapabilities 0x00 + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 255 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 Unused + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/2a86_8011_wch_link.txt b/doc/usb_adapters/cmsis_dap/2a86_8011_wch_link.txt new file mode 100644 index 0000000000..f27d9932fa --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/2a86_8011_wch_link.txt @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://github.com/pyocd/pyOCD/issues/1395 + +Bus 003 Device 118: ID 2a86:8011 wch.cn WCH-Link +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 8 + idVendor 0x2a86 + idProduct 0x8011 + bcdDevice 1.00 + iManufacturer 1 wch.cn + iProduct 2 WCH-Link + iSerial 3 0001A0000001 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x006b + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 0 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 4 QYF CMSIS-DAP + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 0 + iInterface 4 QYF CMSIS-DAP + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 1 + CDC ACM: + bmCapabilities 0x02 + line coding and serial state + CDC Union: + bMasterInterface 0 + bSlaveInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 2 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 5 (error) + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 6 QYF CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.00 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 33 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/c251_2722_keil_ulink2.txt b/doc/usb_adapters/cmsis_dap/c251_2722_keil_ulink2.txt new file mode 100644 index 0000000000..65903b3533 --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/c251_2722_keil_ulink2.txt @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Standalone adapter + +Bus 001 Device 010: ID c251:2722 Keil Software, Inc. Keil ULINK2 CMSIS-DAP +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0xc251 Keil Software, Inc. + idProduct 0x2722 + bcdDevice 1.00 + iManufacturer 1 Keil Software + iProduct 2 Keil ULINK2 CMSIS-DAP + iSerial 3 V0022U9E + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0029 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.00 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 33 + Report Descriptor: (length is 33) + Item(Global): Usage Page, data= [ 0x00 0xff ] 65280 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x01 ] 1 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Feature, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/c251_2723_keil_ulink_me.txt b/doc/usb_adapters/cmsis_dap/c251_2723_keil_ulink_me.txt new file mode 100644 index 0000000000..df2b9243ef --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/c251_2723_keil_ulink_me.txt @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://stackoverflow.com/questions/27087281/jtag-adapter-ulink-me-and-openocd-on-archlinux + +Bus 005 Device 026: ID c251:2723 Keil Software, Inc. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0xc251 Keil Software, Inc. + idProduct 0x2723 + bcdDevice 1.00 + iManufacturer 1 Keil Software + iProduct 2 Keil ULINK-ME CMSIS-DAP + iSerial 3 M0489MAE + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 41 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 No Subclass + bInterfaceProtocol 0 None + iInterface 4 CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.00 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 33 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/c251_2750_keil_ulinkplus.txt b/doc/usb_adapters/cmsis_dap/c251_2750_keil_ulinkplus.txt new file mode 100644 index 0000000000..4504ef0eb5 --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/c251_2750_keil_ulinkplus.txt @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# firmware 2.0.11 + +Bus 001 Device 005: ID c251:2750 Keil Software, Inc. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0xc251 Keil Software, Inc. + idProduct 0x2750 + bcdDevice 1.00 + iManufacturer 1 KEIL - Tools By ARM + iProduct 2 Keil ULINKplus + iSerial 3 L78440715A + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 101 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 ULINKplus CMSIS-DAP + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 5 ULINKplus Digital I/O + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 6 ULINKplus Analog I/O + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 7 ULINKplus Power Probe + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/cmsis_dap/c251_f001_jixin.pro.txt b/doc/usb_adapters/cmsis_dap/c251_f001_jixin.pro.txt new file mode 100644 index 0000000000..c08f679a6a --- /dev/null +++ b/doc/usb_adapters/cmsis_dap/c251_f001_jixin.pro.txt @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://sourceforge.net/p/openocd/tickets/368/ + +Bus 001 Device 008: ID c251:f001 Keil Software, Inc. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 ? + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0xc251 Keil Software, Inc. + idProduct 0xf001 + bcdDevice 1.00 + iManufacturer 1 jixin.pro + iProduct 2 CMSIS-DAP_LU + iSerial 3 LU_2022_8888 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 107 + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 0 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 4 CMSIS-DAP CDC + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 0 None + iInterface 4 CMSIS-DAP CDC + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 1 + CDC ACM: + bmCapabilities 0x02 + line coding and serial state + CDC Union: + bMasterInterface 0 + bSlaveInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 2 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 Unused + bInterfaceProtocol 0 + iInterface 5 CMSIS-DAP DCI + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 No Subclass + bInterfaceProtocol 0 None + iInterface 6 CMSIS-DAP_LU + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.00 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 33 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/dump.sh b/doc/usb_adapters/dump.sh new file mode 100755 index 0000000000..557ef7f4c9 --- /dev/null +++ b/doc/usb_adapters/dump.sh @@ -0,0 +1,42 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-or-later + +hid_unavailable_report() { + a=$(echo $1 | tr '[:lower:]' '[:upper:]') + b=$(basename $(dirname $(ls -d /sys/bus/usb/drivers/usbhid/*/*:$a.*))) + + echo "" + echo "ATTENTION!" + echo "Unable to read completely the USB descriptors." + echo "Please run the following command(s) and then run this script again" + for i in $b; do + echo " sudo sh -c \"echo -n $i > /sys/bus/usb/drivers/usbhid/unbind\"" + done + echo "" + echo "Please notice that the USB device will not function after the above" + echo "operations; you should unplug and replug it to get it working again." +} + +devs=$(lsusb -d $1:$2 | wc -l) +case "$devs" in + 0 ) + echo "Error: USB device $1:$2 not found" > /dev/stderr + exit 1 + ;; + 1 ) + echo "Dumping $(lsusb -d $1:$2)" > /dev/stderr + ;; + * ) + echo "Error: Multiple matches for 'lsusb -d $1:$2'" > /dev/stderr + exit 1 + ;; +esac + +# break SPDX tag to hide it to checkpatch +echo '# SPDX-''License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later' +echo '' +echo '# Optional comment' + +lsusb -v -d $1:$2 | sed 's/ *$//' + +lsusb -v -d $1:$2 2>&1 | grep -Fq '** UNAVAILABLE **' && (hid_unavailable_report $1:$2 > /dev/stderr) diff --git a/doc/usb_adapters/esp_usb_jtag/303a_1001_esp_usb_jtag.txt b/doc/usb_adapters/esp_usb_jtag/303a_1001_esp_usb_jtag.txt new file mode 100644 index 0000000000..8da58e5812 --- /dev/null +++ b/doc/usb_adapters/esp_usb_jtag/303a_1001_esp_usb_jtag.txt @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Optional comment + +Bus 002 Device 035: ID 303a:1001 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x303a + idProduct 0x1001 + bcdDevice 1.01 + iManufacturer 1 Espressif + iProduct 2 USB JTAG/serial debug unit + iSerial 3 7C:DF:A1:A2:8F:38 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0062 + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0xc0 + Self Powered + MaxPower 500mA + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 0 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 0 + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 0 + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x02 + line coding and serial state + CDC Union: + bMasterInterface 0 + bSlaveInterface 1 + CDC Call Management: + bmCapabilities 0x03 + call management + use DataInterface + bDataInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 2 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 1 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 +Device Status: 0x0001 + Self Powered diff --git a/doc/usb_adapters/ft232r/0403_6001_ft232r.txt b/doc/usb_adapters/ft232r/0403_6001_ft232r.txt new file mode 100644 index 0000000000..8bfb058fde --- /dev/null +++ b/doc/usb_adapters/ft232r/0403_6001_ft232r.txt @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: FT232RL +# Chip: FT232RL + +Bus 001 Device 005: ID 0403:6001 Future Technology Devices International, Ltd FT232 Serial (UART) IC +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 8 + idVendor 0x0403 Future Technology Devices International, Ltd + idProduct 0x6001 FT232 Serial (UART) IC + bcdDevice 6.00 + iManufacturer 1 FTDI + iProduct 2 FT232R USB UART + iSerial 3 A50285BI + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0xa0 + (Bus Powered) + Remote Wakeup + MaxPower 90mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 FT232R USB UART + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/ftdi/0403_6010_ft2232h.txt b/doc/usb_adapters/ftdi/0403_6010_ft2232h.txt new file mode 100644 index 0000000000..8bb33e6e52 --- /dev/null +++ b/doc/usb_adapters/ftdi/0403_6010_ft2232h.txt @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: Steppenprobe +# Link: https://github.com/diegoherranz/steppenprobe +# Chip: FT2232HL + +Bus 001 Device 012: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0403 Future Technology Devices International, Ltd + idProduct 0x6010 FT2232C/D/H Dual UART/FIFO IC + bcdDevice 7.00 + iManufacturer 1 FTDI + iProduct 2 Dual RS232-HS + iSerial 0 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0037 + bNumInterfaces 2 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 Dual RS232-HS + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 Dual RS232-HS + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/ftdi/0403_6014_digilent_hs2.txt b/doc/usb_adapters/ftdi/0403_6014_digilent_hs2.txt new file mode 100644 index 0000000000..68fc119e18 --- /dev/null +++ b/doc/usb_adapters/ftdi/0403_6014_digilent_hs2.txt @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://sourceforge.net/p/openocd/tickets/357/ + +Bus 001 Device 084: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0403 Future Technology Devices International, Ltd + idProduct 0x6014 FT232H Single HS USB-UART/FIFO IC + bcdDevice 9.00 + iManufacturer 1 Digilent + iProduct 2 Digilent USB Device + iSerial 3 210249AFCD0B + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 Digilent USB Device + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/ftdi/0403_cff8_amontec_jtagkey2.txt b/doc/usb_adapters/ftdi/0403_cff8_amontec_jtagkey2.txt new file mode 100644 index 0000000000..f056502ad5 --- /dev/null +++ b/doc/usb_adapters/ftdi/0403_cff8_amontec_jtagkey2.txt @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Link: http://www.amontec.com +# Casing: Hi-Speed JTAGkey-2 (c) 2009, Amontec +# PCB: Amontec JTAGkey2 v5.3 +# Chip: FT2232HQ + +Bus 001 Device 017: ID 0403:cff8 Future Technology Devices International, Ltd Amontec JTAGkey +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0403 Future Technology Devices International, Ltd + idProduct 0xcff8 Amontec JTAGkey + bcdDevice 7.00 + iManufacturer 1 Amontec + iProduct 2 Amontec JTAGkey-2 + iSerial 3 53U2ML49 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0037 + bNumInterfaces 2 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 Amontec JTAGkey-2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 Amontec JTAGkey-2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/ftdi/09fb_6001_altera_blaster.txt b/doc/usb_adapters/ftdi/09fb_6001_altera_blaster.txt new file mode 100644 index 0000000000..25f43a416d --- /dev/null +++ b/doc/usb_adapters/ftdi/09fb_6001_altera_blaster.txt @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Clone www.terasic.com "USB Blaster" +# PCB reports: "USB Blaster-B", "FOR ALTERA ONLY" +# Chip: FT245BL + +Bus 001 Device 005: ID 09fb:6001 Altera Blaster +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.10 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 8 + idVendor 0x09fb Altera + idProduct 0x6001 Blaster + bcdDevice 4.00 + iManufacturer 1 Altera + iProduct 2 USB-Blaster + iSerial 3 91f28492 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 150mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 USB-Blaster + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/ftdi/9e88_9e8f_sheevaplug_jtagkey.txt b/doc/usb_adapters/ftdi/9e88_9e8f_sheevaplug_jtagkey.txt new file mode 100644 index 0000000000..c610443356 --- /dev/null +++ b/doc/usb_adapters/ftdi/9e88_9e8f_sheevaplug_jtagkey.txt @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=837989 + +Bus 003 Device 002: ID 9e88:9e8f +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 8 + idVendor 0x9e88 + idProduct 0x9e8f + bcdDevice 5.00 + iManufacturer 1 FTDI + iProduct 2 SheevaPlug JTAGKey FT2232D B + iSerial 3 FTU85Z4Y + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 55 + bNumInterfaces 2 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0xc0 + Self Powered + MaxPower 0mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 SheevaPlug JTAGKey FT2232D B + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 2 SheevaPlug JTAGKey FT2232D B + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/icdi/1cbe_00fd_ti_icdi.txt b/doc/usb_adapters/icdi/1cbe_00fd_ti_icdi.txt new file mode 100644 index 0000000000..14fc86fd63 --- /dev/null +++ b/doc/usb_adapters/icdi/1cbe_00fd_ti_icdi.txt @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: TI Tiva C Series TM4C1294 Connected LaunchPad +# ICDI firmware update to add OpenOCD support + +Bus 001 Device 016: ID 1cbe:00fd Luminary Micro Inc. In-Circuit Debug Interface +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.10 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x1cbe Luminary Micro Inc. + idProduct 0x00fd In-Circuit Debug Interface + bcdDevice 1.00 + iManufacturer 1 Texas Instruments + iProduct 2 In-Circuit Debug Interface + iSerial 3 0F00CAC2 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0074 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 250mA + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 0 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 0 + bSlaveInterface 1 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0010 1x 16 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 0 + bInterfaceClass 254 Application Specific Interface + bInterfaceSubClass 1 Device Firmware Update + bInterfaceProtocol 1 + iInterface 0 + Device Firmware Upgrade Interface Descriptor: + bLength 9 + bDescriptorType 33 + bmAttributes 15 + Will Detach + Manifestation Tolerant + Upload Supported + Download Supported + wDetachTimeout 65535 milliseconds + wTransferSize 1024 bytes + bcdDFUVersion 1.10 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/jlink/1366_0101_segger_jlink.txt b/doc/usb_adapters/jlink/1366_0101_segger_jlink.txt new file mode 100644 index 0000000000..8fa4e7d29a --- /dev/null +++ b/doc/usb_adapters/jlink/1366_0101_segger_jlink.txt @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in https://forums.gentoo.org/viewtopic-t-781442-start-0.html + +Bus 002 Device 002: ID 1366:0101 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.10 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 8 + idVendor 0x1366 + idProduct 0x0101 + bcdDevice 0.01 + iManufacturer 1 SEGGER + iProduct 2 J-Link + iSerial 3 123456 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 32 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0xc0 + Self Powered + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0001 + Self Powered diff --git a/doc/usb_adapters/jlink/1366_0101_segger_jlink_plus_10_1.txt b/doc/usb_adapters/jlink/1366_0101_segger_jlink_plus_10_1.txt new file mode 100644 index 0000000000..fd31e9c789 --- /dev/null +++ b/doc/usb_adapters/jlink/1366_0101_segger_jlink_plus_10_1.txt @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Standalone adapter, original Segger, HW version 10.1 + +Bus 001 Device 005: ID 1366:0101 SEGGER J-Link PLUS +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x1366 SEGGER + idProduct 0x0101 J-Link PLUS + bcdDevice 1.00 + iManufacturer 1 SEGGER + iProduct 2 J-Link + iSerial 3 123456 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 4 Configuration + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 BULK interface + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 1 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/kitprog/04b4_f139_cypress_kitprog.txt b/doc/usb_adapters/kitprog/04b4_f139_cypress_kitprog.txt new file mode 100644 index 0000000000..e3430d87e2 --- /dev/null +++ b/doc/usb_adapters/kitprog/04b4_f139_cypress_kitprog.txt @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Reported in http://false.ekta.is/tag/unboxing/ + +Bus 003 Device 011: ID 04b4:f139 Cypress Semiconductor Corp. +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 ? + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 8 + idVendor 0x04b4 Cypress Semiconductor Corp. + idProduct 0xf139 + bcdDevice 2.0b + iManufacturer 1 Cypress Semiconductor + iProduct 2 Cypress KitProg + iSerial 128 1C210338012E4400 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 130 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 2 Cypress KitProg + bmAttributes 0x80 + (Bus Powered) + MaxPower 400mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 No Subclass + bInterfaceProtocol 0 None + iInterface 3 KitBridge + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 43 + Report Descriptors: + ** UNAVAILABLE ** + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 5 KitProg Programmer + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 2 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 0 + bFunctionProtocol 0 + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 0 None + iInterface 4 KitProg USBUART + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x02 + line coding and serial state + CDC Union: + bMasterInterface 2 + bSlaveInterface 1 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0008 1x 8 bytes + bInterval 2 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 Unused + bInterfaceProtocol 0 + iInterface 4 KitProg USBUART + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x07 EP 7 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/nulink/0416_511d_nuvoton_nulink.txt b/doc/usb_adapters/nulink/0416_511d_nuvoton_nulink.txt new file mode 100644 index 0000000000..2ac9a44a0d --- /dev/null +++ b/doc/usb_adapters/nulink/0416_511d_nuvoton_nulink.txt @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: nuvoTon NuMaker-PFM-M2351 +# Adapter: ICE V3.0 + +Bus 001 Device 013: ID 0416:511d Winbond Electronics Corp. Nuvoton Nu-Link1 ICE/VCOM +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.10 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0416 Winbond Electronics Corp. + idProduct 0x511d Nuvoton Nu-Link1 ICE/VCOM + bcdDevice 1.00 + iManufacturer 1 Nuvoton + iProduct 2 Nu-Link + iSerial 0 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x006b + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.10 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 28 + Report Descriptor: (length is 28) + Item(Global): Usage Page, data= [ 0x01 ] 1 + Generic Desktop Controls + Item(Local ): Usage, data= [ 0x00 ] 0 + Undefined + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Local ): Usage Minimum, data= [ 0x00 ] 0 + Undefined + Item(Local ): Usage Maximum, data= [ 0x00 ] 0 + Undefined + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Local ): Usage Minimum, data= [ 0x00 ] 0 + Undefined + Item(Local ): Usage Maximum, data= [ 0x00 ] 0 + Undefined + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 2 Nu-Link + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 1 + CDC ACM: + bmCapabilities 0x00 + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0008 1x 8 bytes + bInterval 255 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/nulink/0416_5200_nuvoton_nulink.txt b/doc/usb_adapters/nulink/0416_5200_nuvoton_nulink.txt new file mode 100644 index 0000000000..5735d3bd2f --- /dev/null +++ b/doc/usb_adapters/nulink/0416_5200_nuvoton_nulink.txt @@ -0,0 +1,238 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: nuvoTon NuMaker-M483KG V1.1 +# Adapter: Nu-Link2-Me V1.0 + +Bus 001 Device 014: ID 0416:5200 Winbond Electronics Corp. Nuvoton Nu-Link2-ME ICE/MSC/VCOM +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0416 Winbond Electronics Corp. + idProduct 0x5200 Nuvoton Nu-Link2-ME ICE/MSC/VCOM + bcdDevice 0.00 + iManufacturer 1 Nuvoton + iProduct 9 Nu-Link2 + iSerial 6 13010000AAAAAAAAAAAAAAAAAAAAAAAA + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0099 + bNumInterfaces 5 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 2 Nu-Link2 Bulk + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 3 Nu-Link2 VCOM + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 1 + CDC ACM: + bmCapabilities 0x00 + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0100 1x 256 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0100 1x 256 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 4 Nu-Link2 HID + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.10 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 35 + Report Descriptor: (length is 35) + Item(Global): Usage Page, data= [ 0x06 0xff ] 65286 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Global): Logical Minimum, data= [ 0x00 ] 0 + Item(Global): Logical Maximum, data= [ 0xff 0x00 ] 255 + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x00 0x04 ] 1024 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x00 0x04 ] 1024 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Global): Report Count, data= [ 0x08 ] 8 + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Feature, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0400 1x 1024 bytes + bInterval 4 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x07 EP 7 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0400 1x 1024 bytes + bInterval 4 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 4 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 5 Nu-Link2 MSC + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x88 EP 8 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x09 EP 9 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/readme.txt b/doc/usb_adapters/readme.txt new file mode 100644 index 0000000000..19df4cf70f --- /dev/null +++ b/doc/usb_adapters/readme.txt @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +This folder contains a collection of dumps of USB descriptors, obtained through +Linux lsusb command, of several USB adapters supported by OpenOCD. +This collection should help maintaining adapter drivers even if the developer +doesn't have access to all the devices supported by the driver. + +To add a new file, run: + + ./doc/usb_adapters/dump.sh ${vid} ${pid} \ + > doc/usb_adapters/${driver}/${vid}_${pid}_${short_description}.txt + +eventually edit the file to add some extra comment, then submit the file to +OpenOCD gerrit, as explained in HACKING. + +The dumps are organized in subfolders corresponding to OpenOCD drivers: +- cmsis_dap; +- esp_usb_jtag; +- ft232r; +- ftdi; +- icdi; +- jlink; +- kitprog; +- nulink; +- stlink; +- xds110. + +The script above assumes the user has granted access permissions to the USB +device file in + /dev/bus/usb/<n>/<m> +This is usually the case when the device is listed in + contrib/60-openocd.rules +and this udev rules file is properly installed in the host machine. +If the user has no proper access permissions, the script has to be run as +root or through 'sudo'. + +Old versions of 'lsusb -v' dump cryptic errors like: + can't get device qualifier: Resource temporarily unavailable + can't get debug descriptor: Resource temporarily unavailable +when some optional descriptor is not present. +This is fixed in usbutils v014. +If you get such messages simply ignore them. They are printed on stderr, so +will not be included in the generated file as the redirection '>' does only +redirects stdout. diff --git a/doc/usb_adapters/stlink/0483_3744_stlinkv1.txt b/doc/usb_adapters/stlink/0483_3744_stlinkv1.txt new file mode 100644 index 0000000000..b887f7971c --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3744_stlinkv1.txt @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Standalone adapter + +Bus 001 Device 009: ID 0483:3744 STMicroelectronics ST-LINK/V1 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3744 ST-LINK/V1 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 STLink + iSerial 3 0000001 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 4 ST Link + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_3748_stlinkv2.txt b/doc/usb_adapters/stlink/0483_3748_stlinkv2.txt new file mode 100644 index 0000000000..ac6dfc7f63 --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3748_stlinkv2.txt @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# ST-Link/V2 standalone or ST-Link/V2 in firmware update mode + +Bus 001 Device 006: ID 0483:3748 STMicroelectronics ST-LINK/V2 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3748 ST-LINK/V2 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 STLink + iSerial 3 0668FF323637414257071827 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0027 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 4 ST Link + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_374b_stlinkv2.txt b/doc/usb_adapters/stlink/0483_374b_stlinkv2.txt new file mode 100644 index 0000000000..cc0156d74d --- /dev/null +++ b/doc/usb_adapters/stlink/0483_374b_stlinkv2.txt @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: ST Nucleo F411 + +Bus 001 Device 007: ID 0483:374b STMicroelectronics ST-LINK/V2.1 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x374b ST-LINK/V2.1 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 STLink + iSerial 3 066EFF373535503457062922 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0080 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 4 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0020 1x 32 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 5 ST-Link mass storage + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 2 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 6 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 6 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 3 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 2 + bSlaveInterface 3 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0002 1x 2 bytes + bInterval 255 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 7 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0008 1x 8 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0010 1x 16 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_374d_stlinkv3.txt b/doc/usb_adapters/stlink/0483_374d_stlinkv3.txt new file mode 100644 index 0000000000..e964872c34 --- /dev/null +++ b/doc/usb_adapters/stlink/0483_374d_stlinkv3.txt @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# ST-Link/V3 in firmware update mode + +Bus 001 Device 009: ID 0483:374d STMicroelectronics STLINK-V3 Loader +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x374d STLINK-V3 Loader + bcdDevice 2.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 ST-LINK/V3 + iSerial 3 003500463137510239383538 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 4 DFU Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-LINK/V3 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0001 + Self Powered diff --git a/doc/usb_adapters/stlink/0483_374e_stlinkv3.txt b/doc/usb_adapters/stlink/0483_374e_stlinkv3.txt new file mode 100644 index 0000000000..55c968ccee --- /dev/null +++ b/doc/usb_adapters/stlink/0483_374e_stlinkv3.txt @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: ST Nucleo-H745AI-Q + +Bus 001 Device 008: ID 0483:374e STMicroelectronics STLINK-V3 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x374e STLINK-V3 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STLINK-V3 + iSerial 3 005100313137511039383538 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0080 + bNumInterfaces 4 + bConfigurationValue 1 + iConfiguration 4 Default Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 6 ST-Link mass storage + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 2 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 7 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 7 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 3 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 2 + bSlaveInterface 3 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 8 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_374f_stlinkv3.txt b/doc/usb_adapters/stlink/0483_374f_stlinkv3.txt new file mode 100644 index 0000000000..1974001c7c --- /dev/null +++ b/doc/usb_adapters/stlink/0483_374f_stlinkv3.txt @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Standalone adapter + +Bus 001 Device 008: ID 0483:374f STMicroelectronics STLINK-V3 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x374f STLINK-V3 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STLINK-V3 + iSerial 3 003500463137510239383538 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0097 + bNumInterfaces 5 + bConfigurationValue 1 + iConfiguration 4 Default Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 8 Mass Storage + bInterfaceSubClass 6 SCSI + bInterfaceProtocol 80 Bulk-Only + iInterface 6 ST-Link mass storage + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 2 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 7 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 7 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 3 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 2 + bSlaveInterface 3 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 8 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 4 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 9 ST-Link Bridge + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_3752_stlinkv2.txt b/doc/usb_adapters/stlink/0483_3752_stlinkv2.txt new file mode 100644 index 0000000000..798b5276e8 --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3752_stlinkv2.txt @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: ST STM32MP157f-DK2 + +Bus 001 Device 005: ID 0483:3752 STMicroelectronics ST-LINK/V2.1 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3752 ST-LINK/V2.1 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 STLink + iSerial 3 0668FF323637414257071827 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0069 + bNumInterfaces 3 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 300mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 4 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0020 1x 32 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 6 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 6 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 2 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0008 1x 8 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 7 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_3753_stlinkv3.txt b/doc/usb_adapters/stlink/0483_3753_stlinkv3.txt new file mode 100644 index 0000000000..e3a951f99e --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3753_stlinkv3.txt @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board STM32MP135F-DK + +Bus 001 Device 011: ID 0483:3753 STMicroelectronics STLINK-V3 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3753 STLINK-V3 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STLINK-V3 + iSerial 3 001000294741500120383733 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x00c2 + bNumInterfaces 6 + bConfigurationValue 1 + iConfiguration 4 Default Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 300mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 7 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 7 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 2 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 8 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 9 ST-Link Bridge + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 4 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 10 ST-Link VCP2 Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 4 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 10 ST-Link VCP2 Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 5 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 4 + bSlaveInterface 5 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 5 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 11 ST-Link VCP2 Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x07 EP 7 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x87 EP 7 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_3755_stlinkv3pwr.txt b/doc/usb_adapters/stlink/0483_3755_stlinkv3pwr.txt new file mode 100644 index 0000000000..6c7cd6fbf3 --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3755_stlinkv3pwr.txt @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# STLINK-V3PWR standalone in firmware update mode + +Bus 003 Device 054: ID 0483:3755 STMicroelectronics USB2.0 Hub +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3755 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STLINK-V3PWR + iSerial 3 123456780000 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x0020 + bNumInterfaces 1 + bConfigurationValue 1 + iConfiguration 4 DFU Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 100mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-Link Usbloader + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt b/doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt new file mode 100644 index 0000000000..0cfd6cf588 --- /dev/null +++ b/doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# STLINK-V3PWR standalone + +Bus 003 Device 053: ID 0483:3757 STMicroelectronics USB2.0 Hub +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3757 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STLINK-V3PWR + iSerial 3 123456780000 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x00c2 + bNumInterfaces 6 + bConfigurationValue 1 + iConfiguration 4 Default Config + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 3 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 5 ST-Link Debug + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 1 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 6 ST-Link VCP Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 6 ST-Link VCP Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 2 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 1 + bSlaveInterface 2 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 7 ST-Link VCP Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 255 Vendor Specific Subclass + bInterfaceProtocol 255 Vendor Specific Protocol + iInterface 8 ST-Link Bridge + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x06 EP 6 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 4 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 9 ST-Link VCP-PWR Ctrl + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 4 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 9 ST-Link VCP-PWR Ctrl + CDC Header: + bcdCDC 1.10 + CDC Call Management: + bmCapabilities 0x00 + bDataInterface 5 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 4 + bSlaveInterface 5 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x87 EP 7 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x000a 1x 10 bytes + bInterval 16 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 5 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 10 ST-Link VCP-PWR Data + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0200 1x 512 bytes + bInterval 0 +Device Qualifier (for other device speed): + bLength 10 + bDescriptorType 6 + bcdUSB 2.00 + bDeviceClass 0 + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + bNumConfigurations 1 +Device Status: 0x0000 + (Bus Powered) diff --git a/doc/usb_adapters/xds110/0451_bef3_ti_xds110.txt b/doc/usb_adapters/xds110/0451_bef3_ti_xds110.txt new file mode 100644 index 0000000000..628b529e2a --- /dev/null +++ b/doc/usb_adapters/xds110/0451_bef3_ti_xds110.txt @@ -0,0 +1,296 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +# Board: TI CC2650 LaunchPad + +Bus 001 Device 005: ID 0451:bef3 Texas Instruments, Inc. CC1352R1 Launchpad +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 1.10 + bDeviceClass 239 Miscellaneous Device + bDeviceSubClass 2 + bDeviceProtocol 1 Interface Association + bMaxPacketSize0 64 + idVendor 0x0451 Texas Instruments, Inc. + idProduct 0xbef3 CC1352R1 Launchpad + bcdDevice 1.00 + iManufacturer 1 Texas Instruments + iProduct 2 XDS110 (03.00.00.13) Embed with CMSIS-DAP + iSerial 3 L1002566 + bNumConfigurations 1 + Configuration Descriptor: + bLength 9 + bDescriptorType 2 + wTotalLength 0x00db + bNumInterfaces 7 + bConfigurationValue 1 + iConfiguration 0 + bmAttributes 0x80 + (Bus Powered) + MaxPower 500mA + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 0 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 0 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 0 + bSlaveInterface 1 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x81 EP 1 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0010 1x 16 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 1 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x82 EP 2 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x01 EP 1 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 2 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x02 EP 2 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x83 EP 3 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Association: + bLength 8 + bDescriptorType 11 + bFirstInterface 3 + bInterfaceCount 2 + bFunctionClass 2 Communications + bFunctionSubClass 2 Abstract (modem) + bFunctionProtocol 1 AT-commands (v.25ter) + iFunction 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 3 + bAlternateSetting 0 + bNumEndpoints 1 + bInterfaceClass 2 Communications + bInterfaceSubClass 2 Abstract (modem) + bInterfaceProtocol 1 AT-commands (v.25ter) + iInterface 0 + CDC Header: + bcdCDC 1.10 + CDC ACM: + bmCapabilities 0x06 + sends break + line coding and serial state + CDC Union: + bMasterInterface 3 + bSlaveInterface 4 + CDC Call Management: + bmCapabilities 0x01 + call management + bDataInterface 4 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x84 EP 4 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0010 1x 16 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 4 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 10 CDC Data + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x85 EP 5 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x03 EP 3 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 5 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 3 Human Interface Device + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 6 XDS110 CMSIS-DAP + HID Device Descriptor: + bLength 9 + bDescriptorType 33 + bcdHID 1.11 + bCountryCode 0 Not supported + bNumDescriptors 1 + bDescriptorType 34 Report + wDescriptorLength 24 + Report Descriptor: (length is 24) + Item(Global): Usage Page, data= [ 0x00 0xff ] 65280 + (null) + Item(Local ): Usage, data= [ 0x01 ] 1 + (null) + Item(Main ): Collection, data= [ 0x01 ] 1 + Application + Item(Local ): Usage, data= [ 0x03 ] 3 + (null) + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Main ): Input, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Local ): Usage, data= [ 0x04 ] 4 + (null) + Item(Global): Report Size, data= [ 0x08 ] 8 + Item(Global): Report Count, data= [ 0x40 ] 64 + Item(Main ): Output, data= [ 0x02 ] 2 + Data Variable Absolute No_Wrap Linear + Preferred_State No_Null_Position Non_Volatile Bitfield + Item(Main ): End Collection, data=none + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x86 EP 6 IN + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x04 EP 4 OUT + bmAttributes 3 + Transfer Type Interrupt + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 1 + Interface Descriptor: + bLength 9 + bDescriptorType 4 + bInterfaceNumber 6 + bAlternateSetting 0 + bNumEndpoints 2 + bInterfaceClass 255 Vendor Specific Class + bInterfaceSubClass 0 + bInterfaceProtocol 0 + iInterface 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x05 EP 5 OUT + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 + Endpoint Descriptor: + bLength 7 + bDescriptorType 5 + bEndpointAddress 0x87 EP 7 IN + bmAttributes 2 + Transfer Type Bulk + Synch Type None + Usage Type Data + wMaxPacketSize 0x0040 1x 64 bytes + bInterval 0 +Device Status: 0x0000 + (Bus Powered) diff --git a/jimtcl b/jimtcl index a77ef1a621..f160866171 160000 --- a/jimtcl +++ b/jimtcl @@ -1 +1 @@ -Subproject commit a77ef1a6218fad4c928ddbdc03c1aedc41007e70 +Subproject commit f160866171457474f7c4d6ccda70f9b77524407e diff --git a/src/Makefile.am b/src/Makefile.am index 6d79cd6311..4dbe93feea 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -17,8 +17,12 @@ bin_PROGRAMS += %D%/openocd if INTERNAL_JIMTCL %C%_openocd_LDADD += $(top_builddir)/jimtcl/libjim.a else +if HAVE_JIMTCL_PKG_CONFIG +%C%_openocd_LDADD += $(JIMTCL_LIBS) +else %C%_openocd_LDADD += -ljim endif +endif %C%_libopenocd_la_CPPFLAGS = @@ -30,7 +34,10 @@ if RELEASE else %C%_libopenocd_la_CPPFLAGS += -DRELSTR=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\" %C%_libopenocd_la_CPPFLAGS += -DGITVERSION=\"`cd $(top_srcdir) && git describe`\" -%C%_libopenocd_la_CPPFLAGS += -DPKGBLDDATE=\"`date +%F-%R`\" +%C%_libopenocd_la_CPPFLAGS += -DPKGBLDDATE=\"`DATE_FMT=+%F-%R; \ + SOURCE_DATE_EPOCH="$${SOURCE_DATE_EPOCH:-$$(date +%s)}"; \ + date -u -d "@$$SOURCE_DATE_EPOCH" "$$DATE_FMT" 2>/dev/null || \ + date -u -r "$$SOURCE_DATE_EPOCH" "$$DATE_FMT" 2>/dev/null || date -u "$$DATE_FMT"`\" endif # add default CPPFLAGS diff --git a/src/flash/common.c b/src/flash/common.c index dfd6aca80c..9f40a3a6f8 100644 --- a/src/flash/common.c +++ b/src/flash/common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Zachary T Welch <zw@superlucidity.net> * @@ -11,14 +11,14 @@ #include "common.h" #include <helper/log.h> -unsigned get_flash_name_index(const char *name) +unsigned int get_flash_name_index(const char *name) { const char *name_index = strrchr(name, '.'); if (!name_index) return 0; if (name_index[1] < '0' || name_index[1] > '9') return ~0U; - unsigned requested; + unsigned int requested; int retval = parse_uint(name_index + 1, &requested); /* detect parsing error by forcing past end of bank list */ return (retval == ERROR_OK) ? requested : ~0U; @@ -26,7 +26,7 @@ unsigned get_flash_name_index(const char *name) bool flash_driver_name_matches(const char *name, const char *expected) { - unsigned blen = strlen(name); + unsigned int blen = strlen(name); /* only match up to the length of the driver name... */ if (strncmp(name, expected, blen) != 0) return false; diff --git a/src/flash/common.h b/src/flash/common.h index 15aea5b810..6ceaa8d3c7 100644 --- a/src/flash/common.h +++ b/src/flash/common.h @@ -17,7 +17,7 @@ * name provides a suffix but it does not parse as an unsigned integer, * the routine returns ~0U. This will prevent further matching. */ -unsigned get_flash_name_index(const char *name); +unsigned int get_flash_name_index(const char *name); /** * Attempt to match the @c expected name with the @c name of a driver. * @param name The name of the driver (from the bank's device structure). diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c index cc6a880a06..dd012e161a 100644 --- a/src/flash/nand/arm_io.c +++ b/src/flash/nand/arm_io.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009 by Marvell Semiconductors, Inc. @@ -31,12 +31,12 @@ * @return Success or failure of the operation */ static int arm_code_to_working_area(struct target *target, - const uint32_t *code, unsigned code_size, - unsigned additional, struct working_area **area) + const uint32_t *code, unsigned int code_size, + unsigned int additional, struct working_area **area) { uint8_t code_buf[code_size]; int retval; - unsigned size = code_size + additional; + unsigned int size = code_size + additional; /* REVISIT this assumes size doesn't ever change. * That's usually correct; but there are boards with diff --git a/src/flash/nand/arm_io.h b/src/flash/nand/arm_io.h index 10f0e661c1..760dc7e6f3 100644 --- a/src/flash/nand/arm_io.h +++ b/src/flash/nand/arm_io.h @@ -27,7 +27,7 @@ struct arm_nand_data { struct working_area *copy_area; /** The chunk size is the page size or ECC chunk. */ - unsigned chunk_size; + unsigned int chunk_size; /** Where data is read from or written to. */ uint32_t data; diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c index 59345ee347..41cb07bc90 100644 --- a/src/flash/nand/at91sam9.c +++ b/src/flash/nand/at91sam9.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009 by Dean Glazeski @@ -389,9 +389,8 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page, uint32_t bit = parity & 0x0F; data[word] ^= (0x1) << bit; - LOG_INFO("Data word %d, bit %d corrected.", - (unsigned) word, - (unsigned) bit); + LOG_INFO("Data word %" PRIu32 ", bit %" PRIu32 " corrected.", + word, bit); } } @@ -533,7 +532,7 @@ COMMAND_HANDLER(handle_at91sam9_cle_command) { struct nand_device *nand = NULL; struct at91sam9_nand *info = NULL; - unsigned num, address_line; + unsigned int num, address_line; if (CMD_ARGC != 2) { command_print(CMD, "incorrect number of arguments for 'at91sam9 cle' command"); @@ -563,7 +562,7 @@ COMMAND_HANDLER(handle_at91sam9_ale_command) { struct nand_device *nand = NULL; struct at91sam9_nand *info = NULL; - unsigned num, address_line; + unsigned int num, address_line; if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; @@ -591,7 +590,7 @@ COMMAND_HANDLER(handle_at91sam9_rdy_busy_command) { struct nand_device *nand = NULL; struct at91sam9_nand *info = NULL; - unsigned num, base_pioc, pin_num; + unsigned int num, base_pioc, pin_num; if (CMD_ARGC != 3) return ERROR_COMMAND_SYNTAX_ERROR; @@ -622,7 +621,7 @@ COMMAND_HANDLER(handle_at91sam9_ce_command) { struct nand_device *nand = NULL; struct at91sam9_nand *info = NULL; - unsigned num, base_pioc, pin_num; + unsigned int num, base_pioc, pin_num; if (CMD_ARGC != 3) return ERROR_COMMAND_SYNTAX_ERROR; diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c index 2720bc67d3..c5430aeb05 100644 --- a/src/flash/nand/core.c +++ b/src/flash/nand/core.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -165,8 +165,8 @@ static struct nand_ecclayout nand_oob_8 = { */ static struct nand_device *get_nand_device_by_name(const char *name) { - unsigned requested = get_flash_name_index(name); - unsigned found = 0; + unsigned int requested = get_flash_name_index(name); + unsigned int found = 0; struct nand_device *nand; for (nand = nand_devices; nand; nand = nand->next) { @@ -194,7 +194,7 @@ struct nand_device *get_nand_device_by_num(int num) return NULL; } -COMMAND_HELPER(nand_command_get_device, unsigned name_index, +COMMAND_HELPER(nand_command_get_device, unsigned int name_index, struct nand_device **nand) { const char *str = CMD_ARGV[name_index]; @@ -202,7 +202,7 @@ COMMAND_HELPER(nand_command_get_device, unsigned name_index, if (*nand) return ERROR_OK; - unsigned num; + unsigned int num; COMMAND_PARSE_NUMBER(uint, str, num); *nand = get_nand_device_by_num(num); if (!*nand) { diff --git a/src/flash/nand/core.h b/src/flash/nand/core.h index 19c53d1da4..4286e11832 100644 --- a/src/flash/nand/core.h +++ b/src/flash/nand/core.h @@ -179,6 +179,7 @@ enum oob_formats { NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */ }; +extern struct nand_device *nand_devices; struct nand_device *get_nand_device_by_num(int num); @@ -202,11 +203,13 @@ int nand_calculate_ecc(struct nand_device *nand, const uint8_t *dat, uint8_t *ecc_code); int nand_calculate_ecc_kw(struct nand_device *nand, const uint8_t *dat, uint8_t *ecc_code); +int nand_correct_data(struct nand_device *nand, u_char *dat, + u_char *read_ecc, u_char *calc_ecc); int nand_register_commands(struct command_context *cmd_ctx); /** helper for parsing a nand device command argument string */ -COMMAND_HELPER(nand_command_get_device, unsigned name_index, +COMMAND_HELPER(nand_command_get_device, unsigned int name_index, struct nand_device **nand); diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c index 28e31f2a45..17040fe172 100644 --- a/src/flash/nand/davinci.c +++ b/src/flash/nand/davinci.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by David Brownell * @@ -379,7 +379,7 @@ static int davinci_writepage_tail(struct nand_device *nand, static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { - unsigned oob_offset; + unsigned int oob_offset; struct davinci_nand *info = nand->controller_priv; struct target *target = nand->target; const uint32_t fcr_addr = info->aemif + NANDFCR; diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c index 4655606b72..eda033b5b7 100644 --- a/src/flash/nand/driver.c +++ b/src/flash/nand/driver.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -10,50 +10,32 @@ #ifdef HAVE_CONFIG_H #include <config.h> #endif + +#include <helper/types.h> #include "core.h" #include "driver.h" -/* NAND flash controller - */ -extern struct nand_flash_controller nonce_nand_controller; -extern struct nand_flash_controller davinci_nand_controller; -extern struct nand_flash_controller lpc3180_nand_controller; -extern struct nand_flash_controller lpc32xx_nand_controller; -extern struct nand_flash_controller orion_nand_controller; -extern struct nand_flash_controller s3c2410_nand_controller; -extern struct nand_flash_controller s3c2412_nand_controller; -extern struct nand_flash_controller s3c2440_nand_controller; -extern struct nand_flash_controller s3c2443_nand_controller; -extern struct nand_flash_controller s3c6400_nand_controller; -extern struct nand_flash_controller mxc_nand_flash_controller; -extern struct nand_flash_controller imx31_nand_flash_controller; -extern struct nand_flash_controller at91sam9_nand_controller; -extern struct nand_flash_controller nuc910_nand_controller; - -/* extern struct nand_flash_controller boundary_scan_nand_controller; */ - static struct nand_flash_controller *nand_flash_controllers[] = { - &nonce_nand_controller, + // Keep in alphabetic order the list of drivers + &at91sam9_nand_controller, &davinci_nand_controller, + &imx31_nand_flash_controller, &lpc3180_nand_controller, &lpc32xx_nand_controller, + &mxc_nand_flash_controller, + &nonce_nand_controller, + &nuc910_nand_controller, &orion_nand_controller, &s3c2410_nand_controller, &s3c2412_nand_controller, &s3c2440_nand_controller, &s3c2443_nand_controller, &s3c6400_nand_controller, - &mxc_nand_flash_controller, - &imx31_nand_flash_controller, - &at91sam9_nand_controller, - &nuc910_nand_controller, -/* &boundary_scan_nand_controller, */ - NULL }; struct nand_flash_controller *nand_driver_find_by_name(const char *name) { - for (unsigned i = 0; nand_flash_controllers[i]; i++) { + for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) { struct nand_flash_controller *controller = nand_flash_controllers[i]; if (strcmp(name, controller->name) == 0) return controller; @@ -62,7 +44,7 @@ struct nand_flash_controller *nand_driver_find_by_name(const char *name) } int nand_driver_walk(nand_driver_walker_t f, void *x) { - for (unsigned i = 0; nand_flash_controllers[i]; i++) { + for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) { int retval = (*f)(nand_flash_controllers[i], x); if (retval != ERROR_OK) return retval; diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h index a874cc890a..d26e77c75b 100644 --- a/src/flash/nand/driver.h +++ b/src/flash/nand/driver.h @@ -89,4 +89,20 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *); */ int nand_driver_walk(nand_driver_walker_t f, void *x); +// Keep in alphabetic order the list of drivers +extern struct nand_flash_controller at91sam9_nand_controller; +extern struct nand_flash_controller davinci_nand_controller; +extern struct nand_flash_controller imx31_nand_flash_controller; +extern struct nand_flash_controller lpc3180_nand_controller; +extern struct nand_flash_controller lpc32xx_nand_controller; +extern struct nand_flash_controller mxc_nand_flash_controller; +extern struct nand_flash_controller nonce_nand_controller; +extern struct nand_flash_controller nuc910_nand_controller; +extern struct nand_flash_controller orion_nand_controller; +extern struct nand_flash_controller s3c2410_nand_controller; +extern struct nand_flash_controller s3c2412_nand_controller; +extern struct nand_flash_controller s3c2440_nand_controller; +extern struct nand_flash_controller s3c2443_nand_controller; +extern struct nand_flash_controller s3c6400_nand_controller; + #endif /* OPENOCD_FLASH_NAND_DRIVER_H */ diff --git a/src/flash/nand/ecc.c b/src/flash/nand/ecc.c index c6ef20b4cf..20b8ba85dc 100644 --- a/src/flash/nand/ecc.c +++ b/src/flash/nand/ecc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later WITH eCos-exception-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later WITH eCos-exception-2.0 /* * This file contains an ECC algorithm from Toshiba that allows for detection diff --git a/src/flash/nand/ecc_kw.c b/src/flash/nand/ecc_kw.c index beaeb121b2..cea1a5a0ab 100644 --- a/src/flash/nand/ecc_kw.c +++ b/src/flash/nand/ecc_kw.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Reed-Solomon ECC handling for the Marvell Kirkwood SOC diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c index 2bfbd69830..613ae3cb32 100644 --- a/src/flash/nand/fileio.c +++ b/src/flash/nand/fileio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -107,7 +107,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, { nand_fileio_init(state); - unsigned minargs = need_size ? 4 : 3; + unsigned int minargs = need_size ? 4 : 3; if (minargs > CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; @@ -131,7 +131,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, } if (minargs < CMD_ARGC) { - for (unsigned i = minargs; i < CMD_ARGC; i++) { + for (unsigned int i = minargs; i < CMD_ARGC; i++) { if (!strcmp(CMD_ARGV[i], "oob_raw")) state->oob_format |= NAND_OOB_RAW; else if (!strcmp(CMD_ARGV[i], "oob_only")) diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c index 5b7cc1a9a5..d221c34d9e 100644 --- a/src/flash/nand/lpc3180.c +++ b/src/flash/nand/lpc3180.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -890,8 +890,7 @@ static int lpc3180_read_page(struct nand_device *nand, if (mlc_isr & 0x8) { if (mlc_isr & 0x40) { - LOG_ERROR("uncorrectable error detected: 0x%2.2x", - (unsigned)mlc_isr); + LOG_ERROR("uncorrectable error detected: 0x%2.2" PRIx32, mlc_isr); free(page_buffer); free(oob_buffer); return ERROR_NAND_OPERATION_FAILED; @@ -1275,7 +1274,7 @@ COMMAND_HANDLER(handle_lpc3180_select_command) if ((CMD_ARGC < 1) || (CMD_ARGC > 3)) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned num; + unsigned int num; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct nand_device *nand = get_nand_device_by_num(num); if (!nand) { diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index ea282ba2bf..c67f2aa303 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -24,8 +24,6 @@ static int lpc32xx_reset(struct nand_device *nand); static int lpc32xx_controller_ready(struct nand_device *nand, int timeout); static int lpc32xx_tc_ready(struct nand_device *nand, int timeout); -extern int nand_correct_data(struct nand_device *nand, u_char *dat, - u_char *read_ecc, u_char *calc_ecc); /* These are offset with the working area in IRAM when using DMA to * read/write data to the SLC controller. @@ -1029,7 +1027,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, " "data_size=%" PRIu32 ", oob_size=%" PRIu32, - page, data != 0, oob != 0, data_size, oob_size); + page, !!data, !!oob, data_size, oob_size); target_mem_base = pworking_area->address; /* @@ -1388,8 +1386,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, if (mlc_isr & 0x8) { if (mlc_isr & 0x40) { - LOG_ERROR("uncorrectable error detected: " - "0x%2.2x", (unsigned)mlc_isr); + LOG_ERROR("uncorrectable error detected: 0x%2.2" PRIx32, mlc_isr); return ERROR_NAND_OPERATION_FAILED; } @@ -1745,7 +1742,7 @@ COMMAND_HANDLER(handle_lpc32xx_select_command) if ((CMD_ARGC < 1) || (CMD_ARGC > 3)) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned num; + unsigned int num; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct nand_device *nand = get_nand_device_by_num(num); if (!nand) { diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c index d2670bd5d1..86e94685b7 100644 --- a/src/flash/nand/mx3.c +++ b/src/flash/nand/mx3.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** diff --git a/src/flash/nand/mx3.h b/src/flash/nand/mx3.h index b272962b4c..648cd86ccc 100644 --- a/src/flash/nand/mx3.h +++ b/src/flash/nand/mx3.h @@ -86,10 +86,10 @@ enum mx_nf_finalize_action { }; struct mx3_nf_flags { - unsigned target_little_endian:1; - unsigned nand_readonly:1; - unsigned one_kb_sram:1; - unsigned hw_ecc_enabled:1; + unsigned int target_little_endian:1; + unsigned int nand_readonly:1; + unsigned int one_kb_sram:1; + unsigned int hw_ecc_enabled:1; }; struct mx3_nf_controller { diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c index 715e1cbbb8..845a3bb9a6 100644 --- a/src/flash/nand/mxc.c +++ b/src/flash/nand/mxc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Alexei Babich * diff --git a/src/flash/nand/mxc.h b/src/flash/nand/mxc.h index ae2c03a758..e9dc0a2f3d 100644 --- a/src/flash/nand/mxc.h +++ b/src/flash/nand/mxc.h @@ -138,11 +138,11 @@ enum mxc_nf_finalize_action { }; struct mxc_nf_flags { - unsigned target_little_endian:1; - unsigned nand_readonly:1; - unsigned one_kb_sram:1; - unsigned hw_ecc_enabled:1; - unsigned biswap_enabled:1; + unsigned int target_little_endian:1; + unsigned int nand_readonly:1; + unsigned int one_kb_sram:1; + unsigned int hw_ecc_enabled:1; + unsigned int biswap_enabled:1; }; struct mxc_nf_controller { diff --git a/src/flash/nand/nonce.c b/src/flash/nand/nonce.c index db908686d9..bce4ed0f99 100644 --- a/src/flash/nand/nonce.c +++ b/src/flash/nand/nonce.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> * diff --git a/src/flash/nand/nuc910.c b/src/flash/nand/nuc910.c index 4ec7f16fcb..d7f69e6ae0 100644 --- a/src/flash/nand/nuc910.c +++ b/src/flash/nand/nuc910.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c index b2710e64cd..7b19cbd241 100644 --- a/src/flash/nand/orion.c +++ b/src/flash/nand/orion.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Marvell Semiconductors, Inc. * diff --git a/src/flash/nand/s3c2410.c b/src/flash/nand/s3c2410.c index 721ed9dd2b..98268ebcc4 100644 --- a/src/flash/nand/s3c2410.c +++ b/src/flash/nand/s3c2410.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007, 2008 by Ben Dooks * diff --git a/src/flash/nand/s3c2412.c b/src/flash/nand/s3c2412.c index f673689138..0eec35f509 100644 --- a/src/flash/nand/s3c2412.c +++ b/src/flash/nand/s3c2412.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007, 2008 by Ben Dooks * diff --git a/src/flash/nand/s3c2440.c b/src/flash/nand/s3c2440.c index 424d6d2415..789144cbda 100644 --- a/src/flash/nand/s3c2440.c +++ b/src/flash/nand/s3c2440.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007, 2008 by Ben Dooks * diff --git a/src/flash/nand/s3c2443.c b/src/flash/nand/s3c2443.c index fcd904011c..7166702ab1 100644 --- a/src/flash/nand/s3c2443.c +++ b/src/flash/nand/s3c2443.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007, 2008 by Ben Dooks * diff --git a/src/flash/nand/s3c24xx.c b/src/flash/nand/s3c24xx.c index f2311ccaa0..5c2f2bc3fc 100644 --- a/src/flash/nand/s3c24xx.c +++ b/src/flash/nand/s3c24xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007, 2008 by Ben Dooks * diff --git a/src/flash/nand/s3c6400.c b/src/flash/nand/s3c6400.c index bca068e850..aebe0443b5 100644 --- a/src/flash/nand/s3c6400.c +++ b/src/flash/nand/s3c6400.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Peter Korsgaard <jacmet@sunsite.dk> * diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c index 79a386eed1..67a62770fb 100644 --- a/src/flash/nand/tcl.c +++ b/src/flash/nand/tcl.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -17,9 +17,6 @@ #include "fileio.h" #include <target/target.h> -/* to be removed */ -extern struct nand_device *nand_devices; - COMMAND_HANDLER(handle_nand_list_command) { struct nand_device *p; diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am index 5761913c36..e6f420834f 100644 --- a/src/flash/nor/Makefile.am +++ b/src/flash/nor/Makefile.am @@ -24,8 +24,10 @@ NOR_DRIVERS = \ %D%/cc26xx.c \ %D%/cfi.c \ %D%/dsp5680xx_flash.c \ + %D%/dw-spi.c \ %D%/efm32.c \ %D%/em357.c \ + %D%/eneispif.c \ %D%/esirisc_flash.c \ %D%/faux.c \ %D%/fespi.c \ @@ -41,6 +43,7 @@ NOR_DRIVERS = \ %D%/max32xxx.c \ %D%/mdr.c \ %D%/msp432.c \ + %D%/mspm0.c \ %D%/mrvlqspi.c \ %D%/niietcm4.c \ %D%/non_cfi.c \ @@ -52,8 +55,10 @@ NOR_DRIVERS = \ %D%/psoc4.c \ %D%/psoc5lp.c \ %D%/psoc6.c \ + %D%/qn908x.c \ %D%/renesas_rpchf.c \ - %D%/rp2040.c \ + %D%/rp2xxx.c \ + %D%/rsl10.c \ %D%/sfdp.c \ %D%/sh_qspi.c \ %D%/sim3x.c \ @@ -87,6 +92,7 @@ NORHEADERS = \ %D%/cc26xx.h \ %D%/cfi.h \ %D%/driver.h \ + %D%/dw-spi-helper.h \ %D%/imp.h \ %D%/non_cfi.h \ %D%/ocl.h \ diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c index af846c2b46..ea7f5e3730 100644 --- a/src/flash/nor/aduc702x.c +++ b/src/flash/nor/aduc702x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Kevin McGuire * diff --git a/src/flash/nor/aducm360.c b/src/flash/nor/aducm360.c index ffa1bbaf44..aa573acded 100644 --- a/src/flash/nor/aducm360.c +++ b/src/flash/nor/aducm360.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Ivan Buliev * @@ -79,7 +79,7 @@ static int aducm360_build_sector_list(struct flash_bank *bank) /* sector size is 512 */ bank->num_sectors = bank->size / FLASH_SECTOR_SIZE; bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); - for (unsigned i = 0; i < bank->num_sectors; ++i) { + for (unsigned int i = 0; i < bank->num_sectors; ++i) { bank->sectors[i].offset = offset; bank->sectors[i].size = FLASH_SECTOR_SIZE; offset += bank->sectors[i].size; diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c index 4c4a642d5f..67cc6b68a7 100644 --- a/src/flash/nor/ambiqmicro.c +++ b/src/flash/nor/ambiqmicro.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ +// SPDX-License-Identifier: BSD-3-Clause /****************************************************************************** * @@ -124,7 +124,7 @@ FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command) if (CMD_ARGC < 6) return ERROR_COMMAND_SYNTAX_ERROR; - ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1); + ambiqmicro_info = calloc(1, sizeof(struct ambiqmicro_flash_bank)); bank->driver_priv = ambiqmicro_info; @@ -309,9 +309,9 @@ static int ambiqmicro_exec_command(struct target *target, */ target_poll(target); alive_sleep(100); - LOG_DEBUG("state = %d", target->state); } else { - LOG_ERROR("Target not halted or running %d", target->state); + LOG_ERROR("Target not halted or running (state is %s)", + target_state_name(target)); break; } } diff --git a/src/flash/nor/at32qspi.c b/src/flash/nor/at32qspi.c index 1a39e3dc05..cd5dae22a0 100644 --- a/src/flash/nor/at32qspi.c +++ b/src/flash/nor/at32qspi.c @@ -200,7 +200,7 @@ QSPI_OPERATE_MODE_114, 8, 0x32, QSPI_XIP_ADDRLEN_3_BYTE, -QSPI_XIP_ADDRLEN_3_BYTE, +QSPI_OPERATE_MODE_111, 0, QSPI_XIPW_SEL_MODED, 0x7F, diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 431e2a3a06..b86a18da75 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) */ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) /* * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com> @@ -67,8 +67,6 @@ #define OFFSET_EFC_FSR 8 #define OFFSET_EFC_FRR 12 -extern const struct flash_driver at91sam3_flash; - static float _tomhz(uint32_t freq_hz) { float f; @@ -156,15 +154,15 @@ struct sam3_bank_private { struct sam3_chip *chip; /* so we can find the original bank pointer */ struct flash_bank *bank; - unsigned bank_number; + unsigned int bank_number; uint32_t controller_address; uint32_t base_address; uint32_t flash_wait_states; bool present; - unsigned size_bytes; - unsigned nsectors; - unsigned sector_size; - unsigned page_size; + unsigned int size_bytes; + unsigned int nsectors; + unsigned int sector_size; + unsigned int page_size; }; struct sam3_chip_details { @@ -178,12 +176,12 @@ struct sam3_chip_details { uint32_t chipid_cidr; const char *name; - unsigned n_gpnvms; + unsigned int n_gpnvms; #define SAM3_N_NVM_BITS 3 - unsigned gpnvm[SAM3_N_NVM_BITS]; - unsigned total_flash_size; - unsigned total_sram_size; - unsigned n_banks; + unsigned int gpnvm[SAM3_N_NVM_BITS]; + unsigned int total_flash_size; + unsigned int total_sram_size; + unsigned int n_banks; #define SAM3_MAX_FLASH_BANKS 2 /* these are "initialized" from the global const data */ struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS]; @@ -2031,7 +2029,7 @@ static int efc_get_result(struct sam3_bank_private *private, uint32_t *v) } static int efc_start_command(struct sam3_bank_private *private, - unsigned command, unsigned argument) + unsigned int command, unsigned int argument) { uint32_t n, v; int r; @@ -2053,7 +2051,7 @@ static int efc_start_command(struct sam3_bank_private *private, case AT91C_EFC_FCMD_CLB: n = (private->size_bytes / private->page_size); if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n)); + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); break; case AT91C_EFC_FCMD_SFB: @@ -2126,8 +2124,8 @@ static int efc_start_command(struct sam3_bank_private *private, * @param status - put command status bits here */ static int efc_perform_command(struct sam3_bank_private *private, - unsigned command, - unsigned argument, + unsigned int command, + unsigned int argument, uint32_t *status) { @@ -2222,7 +2220,7 @@ static int flashd_erase_entire_bank(struct sam3_bank_private *private) * @param puthere - result stored here. */ /* ------------------------------------------------------------------------------ */ -static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere) +static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere) { uint32_t v; int r; @@ -2263,10 +2261,10 @@ static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, u * @param gpnvm GPNVM index. * @returns 0 if successful; otherwise returns an error code. */ -static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm) +static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; LOG_DEBUG("Here"); if (private->bank_number != 0) { @@ -2295,10 +2293,10 @@ static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm) * @param private info about the bank * @param gpnvm GPNVM index. */ -static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm) +static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; if (private->bank_number != 0) { LOG_ERROR("GPNVM only works with Bank0"); @@ -2348,8 +2346,8 @@ static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v) */ static int flashd_unlock(struct sam3_bank_private *private, - unsigned start_sector, - unsigned end_sector) + unsigned int start_sector, + unsigned int end_sector) { int r; uint32_t status; @@ -2378,8 +2376,8 @@ static int flashd_unlock(struct sam3_bank_private *private, * @param end_sector - last sector (inclusive) to lock */ static int flashd_lock(struct sam3_bank_private *private, - unsigned start_sector, - unsigned end_sector) + unsigned int start_sector, + unsigned int end_sector) { uint32_t status; uint32_t pg; @@ -2407,8 +2405,8 @@ static int flashd_lock(struct sam3_bank_private *private, static uint32_t sam3_reg_fieldname(struct sam3_chip *chip, const char *regname, uint32_t value, - unsigned shift, - unsigned width) + unsigned int shift, + unsigned int width) { uint32_t v; int hwidth, dwidth; @@ -2493,7 +2491,7 @@ static const char *const sramsize[] = { }; -static const struct archnames { unsigned value; const char *name; } archnames[] = { +static const struct archnames { unsigned int value; const char *name; } archnames[] = { { 0x19, "AT91SAM9xx Series" }, { 0x29, "AT91SAM9XExx Series" }, { 0x34, "AT91x34 Series" }, @@ -2869,8 +2867,8 @@ static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here) r = target_read_u32(chip->target, reg->address, goes_here); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d", - reg->name, (unsigned)(reg->address), r); + LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Err: %d", + reg->name, reg->address, r); } return r; } @@ -2885,8 +2883,8 @@ static int sam3_read_all_regs(struct sam3_chip *chip) r = sam3_read_this_reg(chip, sam3_get_reg_ptr(&(chip->cfg), reg)); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d", - reg->name, ((unsigned)(reg->address)), r); + LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Error: %d", + reg->name, reg->address, r); return r; } reg++; @@ -2953,7 +2951,7 @@ static int sam3_protect_check(struct flash_bank *bank) { int r; uint32_t v = 0; - unsigned x; + unsigned int x; struct sam3_bank_private *private; LOG_DEBUG("Begin"); @@ -3073,7 +3071,7 @@ static int sam3_get_details(struct sam3_bank_private *private) const struct sam3_chip_details *details; struct sam3_chip *chip; struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS]; - unsigned x; + unsigned int x; LOG_DEBUG("Begin"); details = all_sam3_details; @@ -3266,7 +3264,7 @@ static int sam3_protect(struct flash_bank *bank, int set, unsigned int first, } -static int sam3_page_read(struct sam3_bank_private *private, unsigned pagenum, uint8_t *buf) +static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf) { uint32_t adr; int r; @@ -3285,7 +3283,7 @@ static int sam3_page_read(struct sam3_bank_private *private, unsigned pagenum, u return r; } -static int sam3_page_write(struct sam3_bank_private *private, unsigned pagenum, const uint8_t *buf) +static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf) { uint32_t adr; uint32_t status; @@ -3349,10 +3347,10 @@ static int sam3_write(struct flash_bank *bank, uint32_t count) { int n; - unsigned page_cur; - unsigned page_end; + unsigned int page_cur; + unsigned int page_end; int r; - unsigned page_offset; + unsigned int page_offset; struct sam3_bank_private *private; uint8_t *pagebuffer; @@ -3499,7 +3497,7 @@ COMMAND_HANDLER(sam3_handle_info_command) if (!chip) return ERROR_OK; - unsigned x; + unsigned int x; int r; /* bank0 must exist before we can do anything */ @@ -3551,7 +3549,7 @@ COMMAND_HANDLER(sam3_handle_info_command) COMMAND_HANDLER(sam3_handle_gpnvm_command) { - unsigned x, v; + unsigned int x, v; int r, who; struct sam3_chip *chip; diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 556484adf2..26a803784d 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) */ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) /* * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com> @@ -62,8 +62,6 @@ #define OFFSET_EFC_FSR 8 #define OFFSET_EFC_FRR 12 -extern const struct flash_driver at91sam4_flash; - static float _tomhz(uint32_t freq_hz) { float f; @@ -136,15 +134,15 @@ struct sam4_bank_private { struct sam4_chip *chip; /* so we can find the original bank pointer */ struct flash_bank *bank; - unsigned bank_number; + unsigned int bank_number; uint32_t controller_address; uint32_t base_address; uint32_t flash_wait_states; bool present; - unsigned size_bytes; - unsigned nsectors; - unsigned sector_size; - unsigned page_size; + unsigned int size_bytes; + unsigned int nsectors; + unsigned int sector_size; + unsigned int page_size; }; struct sam4_chip_details { @@ -158,12 +156,12 @@ struct sam4_chip_details { uint32_t chipid_cidr; const char *name; - unsigned n_gpnvms; + unsigned int n_gpnvms; #define SAM4_N_NVM_BITS 3 - unsigned gpnvm[SAM4_N_NVM_BITS]; - unsigned total_flash_size; - unsigned total_sram_size; - unsigned n_banks; + unsigned int gpnvm[SAM4_N_NVM_BITS]; + unsigned int total_flash_size; + unsigned int total_sram_size; + unsigned int n_banks; #define SAM4_MAX_FLASH_BANKS 2 /* these are "initialized" from the global const data */ struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS]; @@ -1481,7 +1479,7 @@ static int efc_get_result(struct sam4_bank_private *private, uint32_t *v) } static int efc_start_command(struct sam4_bank_private *private, - unsigned command, unsigned argument) + unsigned int command, unsigned int argument) { uint32_t n, v; int r; @@ -1503,7 +1501,7 @@ static int efc_start_command(struct sam4_bank_private *private, case AT91C_EFC_FCMD_CLB: n = (private->size_bytes / private->page_size); if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n)); + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); break; case AT91C_EFC_FCMD_SFB: @@ -1576,8 +1574,8 @@ static int efc_start_command(struct sam4_bank_private *private, * @param status - put command status bits here */ static int efc_perform_command(struct sam4_bank_private *private, - unsigned command, - unsigned argument, + unsigned int command, + unsigned int argument, uint32_t *status) { @@ -1718,7 +1716,7 @@ static int flashd_erase_pages(struct sam4_bank_private *private, * @param puthere - result stored here. */ /* ------------------------------------------------------------------------------ */ -static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere) +static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm, unsigned int *puthere) { uint32_t v; int r; @@ -1759,10 +1757,10 @@ static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, u * @param gpnvm GPNVM index. * @returns 0 if successful; otherwise returns an error code. */ -static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm) +static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; LOG_DEBUG("Here"); if (private->bank_number != 0) { @@ -1791,10 +1789,10 @@ static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm) * @param private info about the bank * @param gpnvm GPNVM index. */ -static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm) +static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; if (private->bank_number != 0) { LOG_ERROR("GPNVM only works with Bank0"); @@ -1848,8 +1846,8 @@ static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v) */ static int flashd_unlock(struct sam4_bank_private *private, - unsigned start_sector, - unsigned end_sector) + unsigned int start_sector, + unsigned int end_sector) { int r; uint32_t status; @@ -1878,8 +1876,8 @@ static int flashd_unlock(struct sam4_bank_private *private, * @param end_sector - last sector (inclusive) to lock */ static int flashd_lock(struct sam4_bank_private *private, - unsigned start_sector, - unsigned end_sector) + unsigned int start_sector, + unsigned int end_sector) { uint32_t status; uint32_t pg; @@ -1907,8 +1905,8 @@ static int flashd_lock(struct sam4_bank_private *private, static uint32_t sam4_reg_fieldname(struct sam4_chip *chip, const char *regname, uint32_t value, - unsigned shift, - unsigned width) + unsigned int shift, + unsigned int width) { uint32_t v; int hwidth, dwidth; @@ -1993,7 +1991,7 @@ static const char *const sramsize[] = { }; -static const struct archnames { unsigned value; const char *name; } archnames[] = { +static const struct archnames { unsigned int value; const char *name; } archnames[] = { { 0x19, "AT91SAM9xx Series" }, { 0x29, "AT91SAM9XExx Series" }, { 0x34, "AT91x34 Series" }, @@ -2376,8 +2374,8 @@ static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here) r = target_read_u32(chip->target, reg->address, goes_here); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d", - reg->name, (unsigned)(reg->address), r); + LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08" PRIx32 ", Err: %d", + reg->name, reg->address, r); } return r; } @@ -2392,8 +2390,8 @@ static int sam4_read_all_regs(struct sam4_chip *chip) r = sam4_read_this_reg(chip, sam4_get_reg_ptr(&(chip->cfg), reg)); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d", - reg->name, ((unsigned)(reg->address)), r); + LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08" PRIx32 ", Error: %d", + reg->name, reg->address, r); return r; } reg++; @@ -2446,7 +2444,7 @@ static int sam4_protect_check(struct flash_bank *bank) { int r; uint32_t v[4] = {0}; - unsigned x; + unsigned int x; struct sam4_bank_private *private; LOG_DEBUG("Begin"); @@ -2559,7 +2557,7 @@ static int sam4_get_details(struct sam4_bank_private *private) const struct sam4_chip_details *details; struct sam4_chip *chip; struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS]; - unsigned x; + unsigned int x; LOG_DEBUG("Begin"); details = all_sam4_details; @@ -2798,7 +2796,7 @@ static int sam4_protect(struct flash_bank *bank, int set, unsigned int first, } -static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf) +static int sam4_page_read(struct sam4_bank_private *private, unsigned int pagenum, uint8_t *buf) { uint32_t adr; int r; @@ -2843,7 +2841,7 @@ static int sam4_set_wait(struct sam4_bank_private *private) return r; } -static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf) +static int sam4_page_write(struct sam4_bank_private *private, unsigned int pagenum, const uint8_t *buf) { uint32_t adr; uint32_t status; @@ -2893,10 +2891,10 @@ static int sam4_write(struct flash_bank *bank, uint32_t count) { int n; - unsigned page_cur; - unsigned page_end; + unsigned int page_cur; + unsigned int page_end; int r; - unsigned page_offset; + unsigned int page_offset; struct sam4_bank_private *private; uint8_t *pagebuffer; @@ -3047,7 +3045,7 @@ COMMAND_HANDLER(sam4_handle_info_command) if (!chip) return ERROR_OK; - unsigned x; + unsigned int x; int r; /* bank0 must exist before we can do anything */ @@ -3099,7 +3097,7 @@ COMMAND_HANDLER(sam4_handle_info_command) COMMAND_HANDLER(sam4_handle_gpnvm_command) { - unsigned x, v; + unsigned int x, v; int r, who; struct sam4_chip *chip; diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c index 99e289f3fe..ddf42a8c5f 100644 --- a/src/flash/nor/at91sam4l.c +++ b/src/flash/nor/at91sam4l.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Andrey Yurovsky * diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c index fac8bb3787..86c80765fc 100644 --- a/src/flash/nor/at91sam7.c +++ b/src/flash/nor/at91sam7.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin * @@ -560,12 +560,22 @@ static int at91sam7_read_part_info(struct flash_bank *bank) if (bnk > 0) { if (!t_bank->next) { /* create a new flash bank element */ - struct flash_bank *fb = malloc(sizeof(struct flash_bank)); + struct flash_bank *fb = calloc(1, sizeof(struct flash_bank)); + if (!fb) { + LOG_ERROR("No memory for flash bank"); + return ERROR_FAIL; + } fb->target = target; fb->driver = bank->driver; + fb->default_padded_value = 0xff; + fb->erased_value = 0xff; fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank)); - fb->name = "sam7_probed"; - fb->next = NULL; + if (!fb->driver_priv) { + free(fb); + LOG_ERROR("No memory for flash driver priv"); + return ERROR_FAIL; + } + fb->name = strdup("sam7_probed"); /* link created bank in 'flash_banks' list */ t_bank->next = fb; @@ -576,8 +586,6 @@ static int at91sam7_read_part_info(struct flash_bank *bank) t_bank->bank_number = bnk; t_bank->base = base_address + bnk * bank_size; t_bank->size = bank_size; - t_bank->chip_width = 0; - t_bank->bus_width = 4; t_bank->num_sectors = sectors_num; /* allocate sectors */ @@ -691,8 +699,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command) uint32_t bank_size; uint32_t ext_freq = 0; - unsigned int chip_width; - unsigned int bus_width; unsigned int banks_num; unsigned int num_sectors; @@ -716,9 +722,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[3], chip_width); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[4], bus_width); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], banks_num); COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], num_sectors); COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector); @@ -732,7 +735,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command) at91sam7_info->ext_freq = ext_freq; } - if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) || + if ((banks_num == 0) || (num_sectors == 0) || (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0)) { at91sam7_info->flash_autodetection = 1; return ERROR_OK; @@ -745,12 +748,22 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command) if (bnk > 0) { if (!t_bank->next) { /* create a new bank element */ - struct flash_bank *fb = malloc(sizeof(struct flash_bank)); + struct flash_bank *fb = calloc(1, sizeof(struct flash_bank)); + if (!fb) { + LOG_ERROR("No memory for flash bank"); + return ERROR_FAIL; + } fb->target = target; fb->driver = bank->driver; + fb->default_padded_value = 0xff; + fb->erased_value = 0xff; fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank)); - fb->name = "sam7_probed"; - fb->next = NULL; + if (!fb->driver_priv) { + free(fb); + LOG_ERROR("No memory for flash driver priv"); + return ERROR_FAIL; + } + fb->name = strdup("sam7_probed"); /* link created bank in 'flash_banks' list */ t_bank->next = fb; @@ -761,8 +774,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command) t_bank->bank_number = bnk; t_bank->base = base_address + bnk * bank_size; t_bank->size = bank_size; - t_bank->chip_width = chip_width; - t_bank->bus_width = bus_width; t_bank->num_sectors = num_sectors; /* allocate sectors */ diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c index dd7c5f54f6..0f7b0bb300 100644 --- a/src/flash/nor/at91samd.c +++ b/src/flash/nor/at91samd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Andrey Yurovsky * @@ -12,6 +12,7 @@ #include "imp.h" #include "helper/binarybuffer.h" +#include <helper/time_support.h> #include <jtag/jtag.h> #include <target/cortex_m.h> @@ -31,7 +32,7 @@ #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */ #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */ #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */ -#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interrupt Flag Status & Clear */ +#define SAMD_NVMCTRL_INTFLAG 0x14 /* NVM Interrupt Flag Status & Clear */ #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */ #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */ #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */ @@ -55,6 +56,9 @@ /* NVMCTRL bits */ #define SAMD_NVM_CTRLB_MANW 0x80 +/* NVMCTRL_INTFLAG bits */ +#define SAMD_NVM_INTFLAG_READY 0x01 + /* Known identifiers */ #define SAMD_PROCESSOR_M0 0x01 #define SAMD_FAMILY_D 0x00 @@ -74,7 +78,7 @@ #define SAMD_GET_DEVSEL(id) (id & 0xFF) /* Bits to mask out lockbits in user row */ -#define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF) +#define NVMUSERROW_LOCKBIT_MASK 0x0000FFFFFFFFFFFFULL struct samd_part { uint8_t id; @@ -239,8 +243,12 @@ static const struct samd_part saml21_parts[] = { { 0x1F, "SAMR30E18A", 256, 32 }, /* SAMR34/R35 parts have integrated SAML21 with a lora radio */ - { 0x28, "SAMR34J18", 256, 32 }, - { 0x2B, "SAMR35J18", 256, 32 }, + { 0x28, "SAMR34J18", 256, 40 }, + { 0x29, "SAMR34J17", 128, 24 }, + { 0x2A, "SAMR34J16", 64, 12 }, + { 0x2B, "SAMR35J18", 256, 40 }, + { 0x2C, "SAMR35J17", 128, 24 }, + { 0x2D, "SAMR35J16", 64, 12 }, }; /* Known SAML22 parts. */ @@ -308,31 +316,31 @@ struct samd_family { static const struct samd_family samd_families[] = { { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20, samd20_parts, ARRAY_SIZE(samd20_parts), - (uint64_t)0xFFFF01FFFE01FF77 }, + 0xFFFF01FFFE01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21, samd21_parts, ARRAY_SIZE(samd21_parts), - (uint64_t)0xFFFF01FFFE01FF77 }, + 0xFFFF01FFFE01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09, samd09_parts, ARRAY_SIZE(samd09_parts), - (uint64_t)0xFFFF01FFFE01FF77 }, + 0xFFFF01FFFE01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10, samd10_parts, ARRAY_SIZE(samd10_parts), - (uint64_t)0xFFFF01FFFE01FF77 }, + 0xFFFF01FFFE01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11, samd11_parts, ARRAY_SIZE(samd11_parts), - (uint64_t)0xFFFF01FFFE01FF77 }, + 0xFFFF01FFFE01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21, saml21_parts, ARRAY_SIZE(saml21_parts), - (uint64_t)0xFFFF03FFFC01FF77 }, + 0xFFFF03FFFC01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22, saml22_parts, ARRAY_SIZE(saml22_parts), - (uint64_t)0xFFFF03FFFC01FF77 }, + 0xFFFF03FFFC01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20, samc20_parts, ARRAY_SIZE(samc20_parts), - (uint64_t)0xFFFF03FFFC01FF77 }, + 0xFFFF03FFFC01FF77ULL }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21, samc21_parts, ARRAY_SIZE(samc21_parts), - (uint64_t)0xFFFF03FFFC01FF77 }, + 0xFFFF03FFFC01FF77ULL }, }; struct samd_info { @@ -357,7 +365,7 @@ static const struct samd_family *samd_find_family(uint32_t id) uint8_t family = SAMD_GET_FAMILY(id); uint8_t series = SAMD_GET_SERIES(id); - for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(samd_families); i++) { if (samd_families[i].processor == processor && samd_families[i].series == series && samd_families[i].family == family) @@ -379,7 +387,7 @@ static const struct samd_part *samd_find_part(uint32_t id) if (!family) return NULL; - for (unsigned i = 0; i < family->num_parts; i++) { + for (unsigned int i = 0; i < family->num_parts; i++) { if (family->parts[i].id == devsel) return &family->parts[i]; } @@ -497,7 +505,27 @@ static int samd_probe(struct flash_bank *bank) static int samd_check_error(struct target *target) { int ret, ret2; + uint8_t intflag; uint16_t status; + int timeout_ms = 1000; + int64_t ts_start = timeval_ms(); + + do { + ret = target_read_u8(target, + SAMD_NVMCTRL + SAMD_NVMCTRL_INTFLAG, &intflag); + if (ret != ERROR_OK) { + LOG_ERROR("Can't read NVM intflag"); + return ret; + } + if (intflag & SAMD_NVM_INTFLAG_READY) + break; + keep_alive(); + } while (timeval_ms() - ts_start < timeout_ms); + + if (!(intflag & SAMD_NVM_INTFLAG_READY)) { + LOG_ERROR("SAMD: NVM programming timed out"); + return ERROR_FLASH_OPERATION_FAILED; + } ret = target_read_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status); @@ -543,7 +571,8 @@ static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd) } /* Issue the NVM command */ - res = target_write_u16(target, + /* 32-bit write is used to ensure atomic operation on ST-Link */ + res = target_write_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd)); if (res != ERROR_OK) return res; diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c index ff8b1bcd38..7ce42b2da7 100644 --- a/src/flash/nor/ath79.c +++ b/src/flash/nor/ath79.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Tobias Diedrich * @@ -513,7 +513,7 @@ static int ath79_erase(struct flash_bank *bank, unsigned int first, if (ath79_info->dev->erase_cmd == 0x00) return ERROR_FLASH_OPER_UNSUPPORTED; - for (unsigned sector = first; sector <= last; sector++) { + for (unsigned int sector = first; sector <= last; sector++) { if (bank->sectors[sector].is_protected) { LOG_ERROR("Flash sector %u protected", sector); return ERROR_FAIL; diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c index 163d142e32..f34958fdb9 100644 --- a/src/flash/nor/atsame5.c +++ b/src/flash/nor/atsame5.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Tomas Vanek * @@ -85,6 +85,9 @@ #define SAME_SERIES_51 0x01 #define SAME_SERIES_53 0x03 #define SAME_SERIES_54 0x04 +#define PIC32CXSG_SERIES_41 0x07 +#define PIC32CXSG_SERIES_60 0x00 +#define PIC32CXSG_SERIES_61 0x02 /* Device ID macros */ #define SAMD_GET_PROCESSOR(id) (id >> 28) @@ -93,7 +96,7 @@ #define SAMD_GET_DEVSEL(id) (id & 0xFF) /* Bits to mask user row */ -#define NVMUSERROW_SAM_E5_D5_MASK ((uint64_t)0x7FFF00FF3C007FFF) +#define NVMUSERROW_SAM_E5_D5_MASK 0x7FFF00FF3C007FFFULL struct samd_part { uint8_t id; @@ -148,6 +151,27 @@ static const struct samd_part same54_parts[] = { { 0x03, "SAME54N19A", 512, 192 }, }; +/* See PIC32CX SG41/SG60/SG61 Family Silicon Errata and Datasheet Clarifications + * DS80000985G */ +/* Known PIC32CX-SG41 parts. */ +static const struct samd_part pic32cxsg41_parts[] = { + { 0x00, "PIC32CX1025SG41128", 1024, 256 }, + { 0x01, "PIC32CX1025SG41100", 1024, 256 }, + { 0x02, "PIC32CX1025SG41064", 1024, 256 }, +}; + +/* Known PIC32CX-SG60 parts. */ +static const struct samd_part pic32cxsg60_parts[] = { + { 0x00, "PIC32CX1025SG60128", 1024, 256 }, + { 0x01, "PIC32CX1025SG60100", 1024, 256 }, +}; + +/* Known PIC32CX-SG61 parts. */ +static const struct samd_part pic32cxsg61_parts[] = { + { 0x00, "PIC32CX1025SG61128", 1024, 256 }, + { 0x01, "PIC32CX1025SG61100", 1024, 256 }, +}; + /* Each family of parts contains a parts table in the DEVSEL field of DID. The * processor ID, family ID, and series ID are used to determine which exact * family this is and then we can use the corresponding table. */ @@ -169,6 +193,12 @@ static const struct samd_family samd_families[] = { same53_parts, ARRAY_SIZE(same53_parts) }, { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, SAME_SERIES_54, same54_parts, ARRAY_SIZE(same54_parts) }, + { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, PIC32CXSG_SERIES_41, + pic32cxsg41_parts, ARRAY_SIZE(pic32cxsg41_parts) }, + { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, PIC32CXSG_SERIES_60, + pic32cxsg60_parts, ARRAY_SIZE(pic32cxsg60_parts) }, + { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, PIC32CXSG_SERIES_61, + pic32cxsg61_parts, ARRAY_SIZE(pic32cxsg61_parts) }, }; struct samd_info { @@ -194,7 +224,7 @@ static const struct samd_family *samd_find_family(uint32_t id) uint8_t family = SAMD_GET_FAMILY(id); uint8_t series = SAMD_GET_SERIES(id); - for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(samd_families); i++) { if (samd_families[i].processor == processor && samd_families[i].series == series && samd_families[i].family == family) @@ -216,7 +246,7 @@ static const struct samd_part *samd_find_part(uint32_t id) if (!family) return NULL; - for (unsigned i = 0; i < family->num_parts; i++) { + for (unsigned int i = 0; i < family->num_parts; i++) { if (family->parts[i].id == devsel) return &family->parts[i]; } diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index 857ad584b6..d6d8938b67 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) */ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code) /* * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com> @@ -53,12 +53,10 @@ #define SAMV_PAGE_SIZE 512 #define SAMV_FLASH_BASE 0x00400000 -extern const struct flash_driver atsamv_flash; - struct samv_flash_bank { bool probed; - unsigned size_bytes; - unsigned gpnvm[SAMV_NUM_GPNVM_BITS]; + unsigned int size_bytes; + unsigned int gpnvm[SAMV_NUM_GPNVM_BITS]; }; /* The actual sector size of the SAMV7 flash memory is 128K bytes. @@ -84,7 +82,7 @@ static int samv_efc_get_result(struct target *target, uint32_t *v) } static int samv_efc_start_command(struct target *target, - unsigned command, unsigned argument) + unsigned int command, unsigned int argument) { uint32_t v; samv_efc_get_status(target, &v); @@ -102,7 +100,7 @@ static int samv_efc_start_command(struct target *target, } static int samv_efc_perform_command(struct target *target, - unsigned command, unsigned argument, uint32_t *status) + unsigned int command, unsigned int argument, uint32_t *status) { int r; uint32_t v; @@ -168,7 +166,7 @@ static int samv_erase_pages(struct target *target, first_page | erase_pages, status); } -static int samv_get_gpnvm(struct target *target, unsigned gpnvm, unsigned *out) +static int samv_get_gpnvm(struct target *target, unsigned int gpnvm, unsigned int *out) { uint32_t v; int r; @@ -192,10 +190,10 @@ static int samv_get_gpnvm(struct target *target, unsigned gpnvm, unsigned *out) return r; } -static int samv_clear_gpnvm(struct target *target, unsigned gpnvm) +static int samv_clear_gpnvm(struct target *target, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; if (gpnvm >= SAMV_NUM_GPNVM_BITS) { LOG_ERROR("invalid gpnvm %d, max: %d", gpnvm, SAMV_NUM_GPNVM_BITS); @@ -211,10 +209,10 @@ static int samv_clear_gpnvm(struct target *target, unsigned gpnvm) return r; } -static int samv_set_gpnvm(struct target *target, unsigned gpnvm) +static int samv_set_gpnvm(struct target *target, unsigned int gpnvm) { int r; - unsigned v; + unsigned int v; if (gpnvm >= SAMV_NUM_GPNVM_BITS) { LOG_ERROR("invalid gpnvm %d, max: %d", gpnvm, SAMV_NUM_GPNVM_BITS); return ERROR_FAIL; @@ -233,7 +231,7 @@ static int samv_set_gpnvm(struct target *target, unsigned gpnvm) } static int samv_flash_unlock(struct target *target, - unsigned start_sector, unsigned end_sector) + unsigned int start_sector, unsigned int end_sector) { int r; uint32_t status; @@ -253,7 +251,7 @@ static int samv_flash_unlock(struct target *target, } static int samv_flash_lock(struct target *target, - unsigned start_sector, unsigned end_sector) + unsigned int start_sector, unsigned int end_sector) { uint32_t status; uint32_t pg; @@ -421,7 +419,7 @@ static int samv_protect(struct flash_bank *bank, int set, unsigned int first, } static int samv_page_read(struct target *target, - unsigned page_num, uint8_t *buf) + unsigned int page_num, uint8_t *buf) { uint32_t addr = SAMV_FLASH_BASE + page_num * SAMV_PAGE_SIZE; int r = target_read_memory(target, addr, 4, SAMV_PAGE_SIZE / 4, buf); @@ -432,7 +430,7 @@ static int samv_page_read(struct target *target, } static int samv_page_write(struct target *target, - unsigned pagenum, const uint8_t *buf) + unsigned int pagenum, const uint8_t *buf) { uint32_t status; const uint32_t addr = SAMV_FLASH_BASE + pagenum * SAMV_PAGE_SIZE; @@ -620,7 +618,7 @@ COMMAND_HANDLER(samv_handle_gpnvm_command) return ERROR_COMMAND_SYNTAX_ERROR; } - unsigned v = 0; + unsigned int v = 0; if (!strcmp("show", CMD_ARGV[0])) { if (who == -1) { showall: diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c index 900d8806ae..1d317a10c6 100644 --- a/src/flash/nor/avrf.c +++ b/src/flash/nor/avrf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Simon Qian * @@ -64,6 +64,7 @@ static const struct avrf_type avft_chips_info[] = { {"atmega324pa", 0x9511, 128, 256, 4, 256}, {"atmega644p", 0x960a, 256, 256, 8, 256}, {"atmega1284p", 0x9705, 256, 512, 8, 512}, + {"atmega32u4", 0x9587, 128, 256, 4, 256}, }; /* avr program functions */ diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c index d4fb5e972b..ccbbcc66eb 100644 --- a/src/flash/nor/bluenrg-x.c +++ b/src/flash/nor/bluenrg-x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Michele Sardo * @@ -19,6 +19,7 @@ #define BLUENRG2_JTAG_REG (flash_priv_data_2.jtag_idcode_reg) #define BLUENRGLP_JTAG_REG (flash_priv_data_lp.jtag_idcode_reg) +#define BLUENRGLPF_JTAG_REG (flash_priv_data_lpf.jtag_idcode_reg) #define DIE_ID_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->die_id_reg) #define JTAG_IDCODE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->jtag_idcode_reg) @@ -63,7 +64,7 @@ static const struct flash_ctrl_priv_data flash_priv_data_lp = { .flash_regs_base = 0x40001000, .flash_page_size = 2048, .jtag_idcode = 0x0201E041, - .part_name = "BLUENRG-LP", + .part_name = "STM32WB07 (BLUENRG-LP)", }; static const struct flash_ctrl_priv_data flash_priv_data_lps = { @@ -73,7 +74,17 @@ static const struct flash_ctrl_priv_data flash_priv_data_lps = { .flash_regs_base = 0x40001000, .flash_page_size = 2048, .jtag_idcode = 0x02028041, - .part_name = "BLUENRG-LPS", + .part_name = "STM32WB05 (BLUENRG-LPS)", +}; + +static const struct flash_ctrl_priv_data flash_priv_data_lpf = { + .die_id_reg = 0x40000000, + .jtag_idcode_reg = 0x40000004, + .flash_base = 0x10040000, + .flash_regs_base = 0x40001000, + .flash_page_size = 2048, + .jtag_idcode = 0x02032041, + .part_name = "STM32WB09 (BLUENRG-LPF)", }; struct bluenrgx_flash_bank { @@ -86,7 +97,9 @@ static const struct flash_ctrl_priv_data *flash_ctrl[] = { &flash_priv_data_1, &flash_priv_data_2, &flash_priv_data_lp, - &flash_priv_data_lps}; + &flash_priv_data_lps, + &flash_priv_data_lpf +}; /* flash_bank bluenrg-x 0 0 0 0 <target#> */ FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command) @@ -130,8 +143,45 @@ static inline int bluenrgx_write_flash_reg(struct flash_bank *bank, uint32_t reg return target_write_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value); } -static int bluenrgx_erase(struct flash_bank *bank, unsigned int first, - unsigned int last) +static int bluenrgx_wait_for_interrupt(struct flash_bank *bank, uint32_t interrupt_flag) +{ + bool flag_raised = false; + for (unsigned int j = 0; j < 100; j++) { + uint32_t value; + if (bluenrgx_read_flash_reg(bank, FLASH_REG_IRQRAW, &value) != ERROR_OK) { + LOG_ERROR("Register read failed"); + return ERROR_FAIL; + } + + if (value & interrupt_flag) { + flag_raised = true; + break; + } + } + + /* clear the interrupt */ + if (flag_raised) { + if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, interrupt_flag) != ERROR_OK) { + LOG_ERROR("Cannot clear interrupt flag"); + return ERROR_FAIL; + } + + return ERROR_OK; + } + + LOG_ERROR("Erase command failed (timeout)"); + return ERROR_TIMEOUT_REACHED; +} + +static inline int bluenrgx_wait_for_command(struct flash_bank *bank) +{ + if (bluenrgx_wait_for_interrupt(bank, FLASH_INT_CMDSTART) == ERROR_OK) + return bluenrgx_wait_for_interrupt(bank, FLASH_INT_CMDDONE); + + return ERROR_FAIL; +} + +static int bluenrgx_erase(struct flash_bank *bank, unsigned int first, unsigned int last) { int retval = ERROR_OK; struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv; @@ -173,19 +223,8 @@ static int bluenrgx_erase(struct flash_bank *bank, unsigned int first, return ERROR_FAIL; } - for (unsigned int i = 0; i < 100; i++) { - uint32_t value; - if (bluenrgx_read_flash_reg(bank, FLASH_REG_IRQRAW, &value)) { - LOG_ERROR("Register write failed"); - return ERROR_FAIL; - } - if (value & FLASH_INT_CMDDONE) - break; - if (i == 99) { - LOG_ERROR("Mass erase command failed (timeout)"); - retval = ERROR_FAIL; - } - } + if (bluenrgx_wait_for_command(bank) != ERROR_OK) + return ERROR_FAIL; } else { command = FLASH_CMD_ERASE_PAGE; @@ -209,19 +248,8 @@ static int bluenrgx_erase(struct flash_bank *bank, unsigned int first, return ERROR_FAIL; } - for (unsigned int j = 0; j < 100; j++) { - uint32_t value; - if (bluenrgx_read_flash_reg(bank, FLASH_REG_IRQRAW, &value)) { - LOG_ERROR("Register write failed"); - return ERROR_FAIL; - } - if (value & FLASH_INT_CMDDONE) - break; - if (j == 99) { - LOG_ERROR("Erase command failed (timeout)"); - retval = ERROR_FAIL; - } - } + if (bluenrgx_wait_for_command(bank) != ERROR_OK) + return ERROR_FAIL; } } @@ -229,14 +257,14 @@ static int bluenrgx_erase(struct flash_bank *bank, unsigned int first, } -static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, +static int bluenrgx_write_with_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv; struct target *target = bank->target; uint32_t buffer_size = 16384 + 8; struct working_area *write_algorithm; - struct working_area *write_algorithm_sp; + struct working_area *write_algorithm_stack; struct working_area *source; uint32_t address = bank->base + offset; struct reg_param reg_params[5]; @@ -251,22 +279,6 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, #include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc" }; - /* check preconditions */ - if (!bluenrgx_info->probed) - return ERROR_FLASH_BANK_NOT_PROBED; - - if ((offset + count) > bank->size) { - LOG_ERROR("Requested write past beyond of flash size: (offset+count) = %" PRIu32 ", size=%" PRIu32, - (offset + count), - bank->size); - return ERROR_FLASH_DST_OUT_OF_BANK; - } - - if (bank->target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if (target_alloc_working_area(target, sizeof(bluenrgx_flash_write_code), &write_algorithm) != ERROR_OK) { LOG_WARNING("no working area available, can't do block memory writes"); @@ -285,10 +297,10 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - /* Stack pointer area */ + /* Stack area */ if (target_alloc_working_area(target, 128, - &write_algorithm_sp) != ERROR_OK) { - LOG_DEBUG("no working area for write code stack pointer"); + &write_algorithm_stack) != ERROR_OK) { + LOG_DEBUG("no working area for target algorithm stack"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -300,8 +312,19 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, init_reg_param(®_params[2], "r2", 32, PARAM_OUT); init_reg_param(®_params[3], "r3", 32, PARAM_OUT); init_reg_param(®_params[4], "sp", 32, PARAM_OUT); - /* Put the parameter at the first available stack location */ - init_mem_param(&mem_params[0], write_algorithm_sp->address + 80, 32, PARAM_OUT); + /* Put the 4th parameter at the location in the stack frame of target write() function. + * See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.lst + * 34 ldr r6, [sp, #88] + * ^^^ offset + */ + init_mem_param(&mem_params[0], write_algorithm_stack->address + 88, 32, PARAM_OUT); + /* Stack for target write algorithm - target write() function has + * __attribute__((naked)) so it does not setup the new stack frame. + * Therefore the stack frame uses the area from SP upwards! + * Interrupts are disabled and no subroutines are called from write() + * so no need to allocate stack below SP. + * TODO: remove __attribute__((naked)) and use similar parameter passing as stm32l4x */ + buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_stack->address); /* FIFO start address (first two words used for write and read pointers) */ buf_set_u32(reg_params[0].value, 0, 32, source->address); @@ -311,14 +334,12 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, buf_set_u32(reg_params[2].value, 0, 32, address); /* Number of bytes */ buf_set_u32(reg_params[3].value, 0, 32, count); - /* Stack pointer for program working area */ - buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address); /* Flash register base address */ buf_set_u32(mem_params[0].value, 0, 32, bluenrgx_info->flash_ptr->flash_regs_base); LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address); LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size); - LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address); + LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address); LOG_DEBUG("address = %08" PRIx32, address); LOG_DEBUG("count = %08" PRIx32, count); @@ -344,6 +365,7 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, if (error != 0) LOG_ERROR("flash write failed = %08" PRIx32, error); } + if (retval == ERROR_OK) { uint32_t rp; /* Read back rp and check that is valid */ @@ -355,9 +377,10 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, } } } + target_free_working_area(target, source); target_free_working_area(target, write_algorithm); - target_free_working_area(target, write_algorithm_sp); + target_free_working_area(target, write_algorithm_stack); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -369,6 +392,80 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, return retval; } +static int bluenrgx_write_without_loader(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct target *target = bank->target; + unsigned int data_count = count / FLASH_DATA_WIDTH; + + while (data_count--) { + /* clear flags */ + if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) { + LOG_ERROR("Register write failed"); + return ERROR_FAIL; + } + + if (bluenrgx_write_flash_reg(bank, FLASH_REG_ADDRESS, offset >> 2) != ERROR_OK) { + LOG_ERROR("Register write failed"); + return ERROR_FAIL; + } + + if (target_write_memory(target, bluenrgx_get_flash_reg(bank, FLASH_REG_DATA0), + FLASH_WORD_LEN, FLASH_DATA_WIDTH_W, buffer) != ERROR_OK) { + LOG_ERROR("Failed to write data"); + return ERROR_FAIL; + } + + if (bluenrgx_write_flash_reg(bank, FLASH_REG_COMMAND, FLASH_CMD_BURSTWRITE) != ERROR_OK) { + LOG_ERROR("Failed"); + return ERROR_FAIL; + } + + if (bluenrgx_wait_for_command(bank) != ERROR_OK) + return ERROR_FAIL; + + /* increment offset, and buffer */ + offset += FLASH_DATA_WIDTH; + buffer += FLASH_DATA_WIDTH; + } + + return ERROR_OK; +} + +static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv; + int retval = ERROR_OK; + + /* check preconditions */ + if (!bluenrgx_info->probed) + return ERROR_FLASH_BANK_NOT_PROBED; + + if ((offset + count) > bank->size) { + LOG_ERROR("Requested write past beyond of flash size: (offset+count) = %" PRIu32 ", size=%" PRIu32, + (offset + count), + bank->size); + return ERROR_FLASH_DST_OUT_OF_BANK; + } + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + assert(offset % FLASH_WORD_LEN == 0); + assert(count % FLASH_WORD_LEN == 0); + + retval = bluenrgx_write_with_loader(bank, buffer, offset, count); + /* if resources are not available write without a loader */ + if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { + LOG_WARNING("falling back to programming without a flash loader (slower)"); + retval = bluenrgx_write_without_loader(bank, buffer, offset, count); + } + return retval; +} + static int bluenrgx_probe(struct flash_bank *bank) { struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv; @@ -378,7 +475,8 @@ static int bluenrgx_probe(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - if ((idcode != flash_priv_data_lp.jtag_idcode) && (idcode != flash_priv_data_lps.jtag_idcode)) { + if (idcode != flash_priv_data_lp.jtag_idcode && idcode != flash_priv_data_lps.jtag_idcode + && idcode != flash_priv_data_lpf.jtag_idcode) { retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode); if (retval != ERROR_OK) return retval; @@ -405,7 +503,7 @@ static int bluenrgx_probe(struct flash_bank *bank) return retval; bank->size = (size_info + 1) * FLASH_WORD_LEN; - bank->num_sectors = bank->size/FLASH_PAGE_SIZE(bluenrgx_info); + bank->num_sectors = bank->size / FLASH_PAGE_SIZE(bluenrgx_info); bank->sectors = realloc(bank->sectors, sizeof(struct flash_sector) * bank->num_sectors); for (unsigned int i = 0; i < bank->num_sectors; i++) { diff --git a/src/flash/nor/bluenrg-x.h b/src/flash/nor/bluenrg-x.h index 720cb6e618..03c66cd81a 100644 --- a/src/flash/nor/bluenrg-x.h +++ b/src/flash/nor/bluenrg-x.h @@ -28,7 +28,12 @@ #define FLASH_CMD_WRITE 0x33 #define FLASH_CMD_BURSTWRITE 0xCC #define FLASH_INT_CMDDONE 0x01 +#define FLASH_INT_CMDSTART 0x02 +/* Flash Controller constants */ #define FLASH_WORD_LEN 4 +#define FLASH_DATA_WIDTH_W 4 +#define FLASH_DATA_WIDTH 16 + #endif /* OPENOCD_FLASH_NOR_BLUENRGX_H */ diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c index b8d18a7d99..54d61421ce 100644 --- a/src/flash/nor/cc26xx.c +++ b/src/flash/nor/cc26xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Texas Instruments, Inc. * @@ -34,6 +34,16 @@ struct cc26xx_bank { uint32_t params_addr[2]; }; +/* Flash helper algorithm for CC26x0 Chameleon targets */ +static const uint8_t cc26x0_algo[] = { +#include "../../../contrib/loaders/flash/cc26xx/cc26x0_algo.inc" +}; + +/* Flash helper algorithm for CC26x2 Agama targets */ +static const uint8_t cc26x2_algo[] = { +#include "../../../contrib/loaders/flash/cc26xx/cc26x2_algo.inc" +}; + static int cc26xx_auto_probe(struct flash_bank *bank); static uint32_t cc26xx_device_type(uint32_t icepick_id, uint32_t user_id) @@ -251,7 +261,6 @@ FLASH_BANK_COMMAND_HANDLER(cc26xx_flash_bank_command) /* Finish initialization of bank */ bank->driver_priv = cc26xx_bank; - bank->next = NULL; return ERROR_OK; } diff --git a/src/flash/nor/cc26xx.h b/src/flash/nor/cc26xx.h index fdba73939a..83fc94024a 100644 --- a/src/flash/nor/cc26xx.h +++ b/src/flash/nor/cc26xx.h @@ -77,14 +77,4 @@ struct cc26xx_algo_params { uint8_t status[4]; }; -/* Flash helper algorithm for CC26x0 Chameleon targets */ -const uint8_t cc26x0_algo[] = { -#include "../../../contrib/loaders/flash/cc26xx/cc26x0_algo.inc" -}; - -/* Flash helper algorithm for CC26x2 Agama targets */ -const uint8_t cc26x2_algo[] = { -#include "../../../contrib/loaders/flash/cc26xx/cc26x2_algo.inc" -}; - #endif /* OPENOCD_FLASH_NOR_CC26XX_H */ diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c index b639bd1093..74cb7aea57 100644 --- a/src/flash/nor/cc3220sf.c +++ b/src/flash/nor/cc3220sf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Texas Instruments, Inc. * @@ -22,6 +22,11 @@ struct cc3220sf_bank { struct armv7m_algorithm armv7m_info; }; +/* Flash helper algorithm for CC3220SF */ +static const uint8_t cc3220sf_algo[] = { +#include "../../../contrib/loaders/flash/cc3220sf/cc3220sf.inc" +}; + static int cc3220sf_mass_erase(struct flash_bank *bank) { struct target *target = bank->target; @@ -91,7 +96,6 @@ FLASH_BANK_COMMAND_HANDLER(cc3220sf_flash_bank_command) /* Finish initialization of flash bank */ bank->driver_priv = cc3220sf_bank; - bank->next = NULL; return ERROR_OK; } diff --git a/src/flash/nor/cc3220sf.h b/src/flash/nor/cc3220sf.h index 7e935f23ab..eb2a6c6480 100644 --- a/src/flash/nor/cc3220sf.h +++ b/src/flash/nor/cc3220sf.h @@ -26,9 +26,4 @@ #define FMC_ERASE_VALUE (FMC_DEFAULT_VALUE | FMC_ERASE_BIT) #define FMC_MERASE_VALUE (FMC_DEFAULT_VALUE | FMC_MERASE_BIT) -/* Flash helper algorithm for CC3220SF */ -const uint8_t cc3220sf_algo[] = { -#include "../../../contrib/loaders/flash/cc3220sf/cc3220sf.inc" -}; - #endif /* OPENOCD_FLASH_NOR_CC3220SF_H */ diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index affbcae23d..2a15e49132 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * @@ -806,7 +806,7 @@ int cfi_flash_bank_cmd(struct flash_bank *bank, unsigned int argc, const char ** } bank->driver_priv = cfi_info; - for (unsigned i = 6; i < argc; i++) { + for (unsigned int i = 6; i < argc; i++) { if (strcmp(argv[i], "x16_as_x8") == 0) cfi_info->x16_as_x8 = true; else if (strcmp(argv[i], "data_swap") == 0) @@ -2219,8 +2219,7 @@ static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, u uint8_t current_word[CFI_MAX_BUS_WIDTH]; int retval; - LOG_DEBUG("reading buffer of %i byte at 0x%8.8x", - (int)count, (unsigned)offset); + LOG_DEBUG("reading buffer of %" PRIi32 " byte at 0x%8.8" PRIx32, count, offset); if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h index ec7f47403a..3a76d98ef2 100644 --- a/src/flash/nor/cfi.h +++ b/src/flash/nor/cfi.h @@ -58,10 +58,10 @@ struct cfi_flash_bank { void *alt_ext; /* calculated timeouts */ - unsigned word_write_timeout; - unsigned buf_write_timeout; - unsigned block_erase_timeout; - unsigned chip_erase_timeout; + unsigned int word_write_timeout; + unsigned int buf_write_timeout; + unsigned int block_erase_timeout; + unsigned int chip_erase_timeout; /* memory accessors */ int (*write_mem)(struct flash_bank *bank, target_addr_t addr, diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c index ec4ca05db0..5c4f2accaf 100644 --- a/src/flash/nor/core.c +++ b/src/flash/nor/core.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -164,7 +164,7 @@ int default_flash_verify(struct flash_bank *bank, void flash_bank_add(struct flash_bank *bank) { /* put flash bank in linked list */ - unsigned bank_num = 0; + unsigned int bank_num = 0; if (flash_banks) { /* find last flash bank */ struct flash_bank *p = flash_banks; @@ -242,8 +242,8 @@ void flash_free_all_banks(void) struct flash_bank *get_flash_bank_by_name_noprobe(const char *name) { - unsigned requested = get_flash_name_index(name); - unsigned found = 0; + unsigned int requested = get_flash_name_index(name); + unsigned int found = 0; struct flash_bank *bank; for (bank = flash_banks; bank; bank = bank->next) { diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h index 0c09e98751..f8cf5e2698 100644 --- a/src/flash/nor/core.h +++ b/src/flash/nor/core.h @@ -20,8 +20,6 @@ struct image; -#define FLASH_MAX_ERROR_STR (128) - /** * Describes the geometry and status of a single flash sector * within a flash bank. A single bank typically consists of multiple @@ -34,18 +32,18 @@ struct flash_sector { uint32_t size; /** * Indication of erasure status: 0 = not erased, 1 = erased, - * other = unknown. Set by @c flash_driver_s::erase_check only. + * other = unknown. Set by @c flash_driver::erase_check only. * * This information must be considered stale immediately. - * Don't set it in flash_driver_s::erase or a device mass_erase - * Don't clear it in flash_driver_s::write + * Don't set it in flash_driver::erase or a device mass_erase + * Don't clear it in flash_driver::write * The flag is not used in a protection block */ int is_erased; /** * Indication of protection status: 0 = unprotected/unlocked, * 1 = protected/locked, other = unknown. Set by - * @c flash_driver_s::protect_check. + * @c flash_driver::protect_check. * * This information must be considered stale immediately. * A million things could make it stale: power cycle, @@ -69,7 +67,7 @@ struct flash_sector { * a major interface. * * This structure will be passed as a parameter to the callbacks in the - * flash_driver_s structure, some of which may modify the contents of + * flash_driver structure, some of which may modify the contents of * this structure of the area of flash that it defines. Driver writers * may use the @c driver_priv member to store additional data on a * per-bank basis, if required. @@ -252,8 +250,21 @@ int get_flash_bank_by_num(unsigned int num, struct flash_bank **bank); * @param bank On output, contains a pointer to the bank or NULL. * @returns ERROR_OK on success, or an error indicating the problem. */ -COMMAND_HELPER(flash_command_get_bank, unsigned name_index, +COMMAND_HELPER(flash_command_get_bank, unsigned int name_index, struct flash_bank **bank); +/** + * Retrieves @a bank from a command argument, reporting errors parsing + * the bank identifier or retrieving the specified bank. The bank + * may be identified by its bank number or by @c name.instance, where + * @a instance is driver-specific. + * @param name_index The index to the string in args containing the + * bank identifier. + * @param bank On output, contains a pointer to the bank or NULL. + * @param do_probe Does auto-probing when set, otherwise without probing. + * @returns ERROR_OK on success, or an error indicating the problem. + */ +COMMAND_HELPER(flash_command_get_bank_probe_optional, unsigned int name_index, + struct flash_bank **bank, bool do_probe); /** * Returns the flash bank like get_flash_bank_by_num(), without probing. * @param num The flash bank number. diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h index 931f79421f..f0d095f060 100644 --- a/src/flash/nor/driver.h +++ b/src/flash/nor/driver.h @@ -29,7 +29,7 @@ struct flash_bank; * flash bank DRIVERNAME ...parameters... * @endcode * - * OpenOCD will search for the driver with a @c flash_driver_s::name + * OpenOCD will search for the driver with a @c flash_driver::name * that matches @c DRIVERNAME. * * The flash subsystem calls some of the other drivers routines a using @@ -170,7 +170,7 @@ struct flash_driver { /** * Check the erasure status of a flash bank. * When called, the driver routine must perform the required - * checks and then set the @c flash_sector_s::is_erased field + * checks and then set the @c flash_sector::is_erased field * for each of the flash banks's sectors. * * @param bank The bank to check @@ -182,7 +182,7 @@ struct flash_driver { * Determine if the specific bank is "protected" or not. * When called, the driver routine must must perform the * required protection check(s) and then set the @c - * flash_sector_s::is_protected field for each of the flash + * flash_sector::is_protected field for each of the flash * bank's sectors. * * If protection is not implemented, set method to NULL @@ -204,7 +204,7 @@ struct flash_driver { int (*info)(struct flash_bank *bank, struct command_invocation *cmd); /** - * A more gentle flavor of flash_driver_s::probe, performing + * A more gentle flavor of flash_driver::probe, performing * setup with less noise. Generally, driver routines should test * to see if the bank has already been probed; if it has, the * driver probably should not perform its probe a second time. @@ -237,4 +237,92 @@ struct flash_driver { */ const struct flash_driver *flash_driver_find_by_name(const char *name); +// Keep in alphabetic order this list of drivers +extern const struct flash_driver aduc702x_flash; +extern const struct flash_driver aducm360_flash; +extern const struct flash_driver ambiqmicro_flash; +extern const struct flash_driver at32f403xx_flash; +extern const struct flash_driver at32f413xx_flash; +extern const struct flash_driver at32f415xx_flash; +extern const struct flash_driver at32f403axx_flash; +extern const struct flash_driver at32f407xx_flash; +extern const struct flash_driver at32wb415xx_flash; +extern const struct flash_driver at32f421xx_flash; +extern const struct flash_driver at32f425xx_flash; +extern const struct flash_driver at32f435xx_flash; +extern const struct flash_driver at32f437xx_flash; +extern const struct flash_driver at32f423xx_flash; +extern const struct flash_driver at32f4xx_flash; +extern const struct flash_driver at91sam3_flash; +extern const struct flash_driver at91sam4_flash; +extern const struct flash_driver at91sam4l_flash; +extern const struct flash_driver at91sam7_flash; +extern const struct flash_driver at91samd_flash; +extern const struct flash_driver ath79_flash; +extern const struct flash_driver atsame5_flash; +extern const struct flash_driver atsamv_flash; +extern const struct flash_driver avr_flash; +extern const struct flash_driver bluenrgx_flash; +extern const struct flash_driver cc26xx_flash; +extern const struct flash_driver cc3220sf_flash; +extern const struct flash_driver cfi_flash; +extern const struct flash_driver dsp5680xx_flash; +extern const struct flash_driver dw_spi_flash; +extern const struct flash_driver efm32_flash; +extern const struct flash_driver em357_flash; +extern const struct flash_driver eneispif_flash; +extern const struct flash_driver esirisc_flash; +extern const struct flash_driver faux_flash; +extern const struct flash_driver fespi_flash; +extern const struct flash_driver fm3_flash; +extern const struct flash_driver fm4_flash; +extern const struct flash_driver jtagspi_flash; +extern const struct flash_driver kinetis_flash; +extern const struct flash_driver kinetis_ke_flash; +extern const struct flash_driver lpc2000_flash; +extern const struct flash_driver lpc288x_flash; +extern const struct flash_driver lpc2900_flash; +extern const struct flash_driver lpcspifi_flash; +extern const struct flash_driver max32xxx_flash; +extern const struct flash_driver mdr_flash; +extern const struct flash_driver mrvlqspi_flash; +extern const struct flash_driver msp432_flash; +extern const struct flash_driver mspm0_flash; +extern const struct flash_driver niietcm4_flash; +extern const struct flash_driver npcx_flash; +extern const struct flash_driver nrf51_flash; +extern const struct flash_driver nrf5_flash; +extern const struct flash_driver numicro_flash; +extern const struct flash_driver ocl_flash; +extern const struct flash_driver pic32mx_flash; +extern const struct flash_driver psoc4_flash; +extern const struct flash_driver psoc5lp_eeprom_flash; +extern const struct flash_driver psoc5lp_flash; +extern const struct flash_driver psoc5lp_nvl_flash; +extern const struct flash_driver psoc6_flash; +extern const struct flash_driver qn908x_flash; +extern const struct flash_driver renesas_rpchf_flash; +extern const struct flash_driver rp2xxx_flash; +extern const struct flash_driver rsl10_flash; +extern const struct flash_driver sh_qspi_flash; +extern const struct flash_driver sim3x_flash; +extern const struct flash_driver stellaris_flash; +extern const struct flash_driver stm32f1x_flash; +extern const struct flash_driver stm32f2x_flash; +extern const struct flash_driver stm32h7x_flash; +extern const struct flash_driver stm32l4x_flash; +extern const struct flash_driver stm32lx_flash; +extern const struct flash_driver stmqspi_flash; +extern const struct flash_driver stmsmi_flash; +extern const struct flash_driver str7x_flash; +extern const struct flash_driver str9x_flash; +extern const struct flash_driver str9xpec_flash; +extern const struct flash_driver swm050_flash; +extern const struct flash_driver tms470_flash; +extern const struct flash_driver virtual_flash; +extern const struct flash_driver w600_flash; +extern const struct flash_driver xcf_flash; +extern const struct flash_driver xmc1xxx_flash; +extern const struct flash_driver xmc4xxx_flash; + #endif /* OPENOCD_FLASH_NOR_DRIVER_H */ diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c index 0cc6e857a2..7718b06768 100644 --- a/src/flash/nor/drivers.c +++ b/src/flash/nor/drivers.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> * * * @@ -18,102 +20,31 @@ #ifdef HAVE_CONFIG_H #include "config.h" #endif -#include "imp.h" - -extern const struct flash_driver aduc702x_flash; -extern const struct flash_driver aducm360_flash; -extern const struct flash_driver ambiqmicro_flash; -extern const struct flash_driver at91sam3_flash; -extern const struct flash_driver at91sam4_flash; -extern const struct flash_driver at91sam4l_flash; -extern const struct flash_driver at91sam7_flash; -extern const struct flash_driver at91samd_flash; -extern const struct flash_driver ath79_flash; -extern const struct flash_driver atsame5_flash; -extern const struct flash_driver atsamv_flash; -extern const struct flash_driver avr_flash; -extern const struct flash_driver bluenrgx_flash; -extern const struct flash_driver cc3220sf_flash; -extern const struct flash_driver cc26xx_flash; -extern const struct flash_driver cfi_flash; -extern const struct flash_driver dsp5680xx_flash; -extern const struct flash_driver efm32_flash; -extern const struct flash_driver em357_flash; -extern const struct flash_driver esirisc_flash; -extern const struct flash_driver faux_flash; -extern const struct flash_driver fm3_flash; -extern const struct flash_driver fm4_flash; -extern const struct flash_driver fespi_flash; -extern const struct flash_driver jtagspi_flash; -extern const struct flash_driver kinetis_flash; -extern const struct flash_driver kinetis_ke_flash; -extern const struct flash_driver lpc2000_flash; -extern const struct flash_driver lpc288x_flash; -extern const struct flash_driver lpc2900_flash; -extern const struct flash_driver lpcspifi_flash; -extern const struct flash_driver max32xxx_flash; -extern const struct flash_driver mdr_flash; -extern const struct flash_driver mrvlqspi_flash; -extern const struct flash_driver msp432_flash; -extern const struct flash_driver niietcm4_flash; -extern const struct flash_driver npcx_flash; -extern const struct flash_driver nrf5_flash; -extern const struct flash_driver nrf51_flash; -extern const struct flash_driver numicro_flash; -extern const struct flash_driver ocl_flash; -extern const struct flash_driver pic32mx_flash; -extern const struct flash_driver psoc4_flash; -extern const struct flash_driver psoc5lp_flash; -extern const struct flash_driver psoc5lp_eeprom_flash; -extern const struct flash_driver psoc5lp_nvl_flash; -extern const struct flash_driver psoc6_flash; -extern const struct flash_driver renesas_rpchf_flash; -extern const struct flash_driver rp2040_flash; -extern const struct flash_driver sh_qspi_flash; -extern const struct flash_driver sim3x_flash; -extern const struct flash_driver stellaris_flash; -extern const struct flash_driver stm32f1x_flash; -extern const struct flash_driver stm32f2x_flash; -extern const struct flash_driver stm32lx_flash; -extern const struct flash_driver stm32l4x_flash; -extern const struct flash_driver stm32h7x_flash; -extern const struct flash_driver stmqspi_flash; -extern const struct flash_driver stmsmi_flash; -extern const struct flash_driver str7x_flash; -extern const struct flash_driver str9x_flash; -extern const struct flash_driver str9xpec_flash; -extern const struct flash_driver swm050_flash; -extern const struct flash_driver tms470_flash; -extern const struct flash_driver virtual_flash; -extern const struct flash_driver w600_flash; -extern const struct flash_driver xcf_flash; -extern const struct flash_driver xmc1xxx_flash; -extern const struct flash_driver xmc4xxx_flash; - -extern const struct flash_driver at32f403xx_flash; -extern const struct flash_driver at32f413xx_flash; -extern const struct flash_driver at32f415xx_flash; -extern const struct flash_driver at32f403axx_flash; -extern const struct flash_driver at32f407xx_flash; -extern const struct flash_driver at32wb415xx_flash; - -extern const struct flash_driver at32f421xx_flash; -extern const struct flash_driver at32f425xx_flash; -extern const struct flash_driver at32f435xx_flash; -extern const struct flash_driver at32f437xx_flash; -extern const struct flash_driver at32f423xx_flash; -extern const struct flash_driver at32f4xx_flash; -extern const struct flash_driver at32qspi_flash; +#include <helper/types.h> +#include "imp.h" /** * The list of built-in flash drivers. * @todo Make this dynamically extendable with loadable modules. */ static const struct flash_driver * const flash_drivers[] = { + // Keep in alphabetic order the list of drivers &aduc702x_flash, &aducm360_flash, &ambiqmicro_flash, + &at32f403xx_flash, + &at32f413xx_flash, + &at32f415xx_flash, + &at32f403axx_flash, + &at32f407xx_flash, + &at32wb415xx_flash, + &at32f421xx_flash, + &at32f425xx_flash, + &at32f435xx_flash, + &at32f437xx_flash, + &at32f423xx_flash, + &at32f4xx_flash, &at91sam3_flash, &at91sam4_flash, &at91sam4l_flash, @@ -124,17 +55,19 @@ static const struct flash_driver * const flash_drivers[] = { &atsamv_flash, &avr_flash, &bluenrgx_flash, - &cc3220sf_flash, &cc26xx_flash, + &cc3220sf_flash, &cfi_flash, &dsp5680xx_flash, + &dw_spi_flash, &efm32_flash, &em357_flash, + &eneispif_flash, &esirisc_flash, &faux_flash, + &fespi_flash, &fm3_flash, &fm4_flash, - &fespi_flash, &jtagspi_flash, &kinetis_flash, &kinetis_ke_flash, @@ -146,60 +79,48 @@ static const struct flash_driver * const flash_drivers[] = { &mdr_flash, &mrvlqspi_flash, &msp432_flash, + &mspm0_flash, &niietcm4_flash, &npcx_flash, - &nrf5_flash, &nrf51_flash, + &nrf5_flash, &numicro_flash, &ocl_flash, &pic32mx_flash, &psoc4_flash, - &psoc5lp_flash, &psoc5lp_eeprom_flash, + &psoc5lp_flash, &psoc5lp_nvl_flash, &psoc6_flash, + &qn908x_flash, &renesas_rpchf_flash, - &rp2040_flash, + &rp2xxx_flash, + &rsl10_flash, &sh_qspi_flash, &sim3x_flash, &stellaris_flash, &stm32f1x_flash, &stm32f2x_flash, - &stm32lx_flash, - &stm32l4x_flash, &stm32h7x_flash, - &stmsmi_flash, + &stm32l4x_flash, + &stm32lx_flash, &stmqspi_flash, + &stmsmi_flash, &str7x_flash, &str9x_flash, &str9xpec_flash, &swm050_flash, &tms470_flash, &virtual_flash, + &w600_flash, &xcf_flash, &xmc1xxx_flash, &xmc4xxx_flash, - &w600_flash, - - &at32f403xx_flash, - &at32f413xx_flash, - &at32f415xx_flash, - &at32f403axx_flash, - &at32f407xx_flash, - &at32wb415xx_flash, - &at32f421xx_flash, - &at32f425xx_flash, - &at32f435xx_flash, - &at32f437xx_flash, - &at32f423xx_flash, - &at32f4xx_flash, - &at32qspi_flash, - NULL, }; const struct flash_driver *flash_driver_find_by_name(const char *name) { - for (unsigned i = 0; flash_drivers[i]; i++) { + for (size_t i = 0; i < ARRAY_SIZE(flash_drivers); i++) { if (strcmp(name, flash_drivers[i]->name) == 0) return flash_drivers[i]; } diff --git a/src/flash/nor/dsp5680xx_flash.c b/src/flash/nor/dsp5680xx_flash.c index d04b0d651d..b1625f11f0 100644 --- a/src/flash/nor/dsp5680xx_flash.c +++ b/src/flash/nor/dsp5680xx_flash.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Rodrigo L. Rosa * diff --git a/src/flash/nor/dw-spi-helper.h b/src/flash/nor/dw-spi-helper.h new file mode 100644 index 0000000000..d3537557b6 --- /dev/null +++ b/src/flash/nor/dw-spi-helper.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/** + * @file + * Driver for SPI NOR flash chips connected via DesignWare SPI Core. + * + * In order to avoid using stack, all helper function arguments are packed + * into a single struct, passed by pointer. + * + * Pointers are represented by 64 bit integers to make structs compatible + * with 64 bit targets. + * + * This file contains helper function argument structures. + */ + +#ifndef OPENOCD_FLASH_NOR_DW_SPI_HELPER_H +#define OPENOCD_FLASH_NOR_DW_SPI_HELPER_H + +#include <stdint.h> + +/** + * @brief Arguments for transaction helper function. + */ +struct dw_spi_transaction { + uint64_t buffer; + ///< Pointer to data buffer to send over SPI. + ///< Return values are stored in place of output data when + ///< dw_spi_transaction::read_flag is 1. + uint32_t size; ///< Size of dw_spi_transaction::buffer. + uint64_t status_reg; ///< Pointer to SR register. + uint64_t data_reg; ///< Pointer to DR register. + uint8_t read_flag; + ///< When 1, store RX FIFO data to dw_spi_transaction::buffer. +} __attribute__((packed)); + +/** + * @brief Arguments for check_fill helper function. + */ +struct dw_spi_check_fill { + uint32_t address; ///< Starting address. Sector aligned. + uint32_t sector_size; ///< Sector size. + uint32_t sector_count; ///< Number of sectors to check. + uint64_t status_reg; ///< Pointer to SR register. + uint64_t data_reg; ///< Pointer to DR register. + uint64_t fill_status_array; + ///< Pointer to array describing sectors fill status. + ///< 1 if filled, 0 if not filled. + uint8_t pattern; ///< Fill pattern. + uint8_t read_cmd; ///< Read data command. + uint8_t four_byte_mode; ///< Four byte addressing mode flag. +} __attribute__((packed)); + +/** + * @brief Arguments for erase helper function. + */ +struct dw_spi_erase { + uint32_t address; ///< First sector address. Sector aligned. + uint32_t sector_size; ///< Sector size. + uint32_t sector_count; ///< Number of sectors to erase. + uint64_t status_reg; ///< Pointer to SR register. + uint64_t data_reg; ///< Pointer to DR register. + uint8_t read_status_cmd; ///< Read status command. + uint8_t write_enable_cmd; ///< Write enable command. + uint8_t erase_sector_cmd; ///< Erase sector command. + uint8_t write_enable_mask; ///< Write enable mask. + uint8_t busy_mask; ///< Busy mask. + uint8_t four_byte_mode; ///< Four byte addressing mode flag. +} __attribute__((packed)); + +/** + * @brief Arguments for program helper function. + */ +struct dw_spi_program { + uint32_t address; + ///< First page address. Page aligned when write is crossing + ///< the page boundary. + uint32_t page_size; ///< Page size. + uint64_t buffer; ///< Data buffer pointer. + uint32_t buffer_size; ///< Size of dw_spi_program::buffer. + uint64_t status_reg; ///< Pointer to SR register. + uint64_t data_reg; ///< Pointer to DR register. + uint8_t read_status_cmd; ///< Read status command. + uint8_t write_enable_cmd; ///< Write enable command. + uint8_t program_cmd; ///< Program command. + uint8_t write_enable_mask; ///< Write enable mask. + uint8_t busy_mask; ///< Busy mask. + uint8_t four_byte_mode; ///< Four byte addressing mode flag. +} __attribute__((packed)); + +/** + * @brief Arguments for read helper function. + */ +struct dw_spi_read { + uint32_t address; ///< First sector address. + uint64_t buffer; ///< Data buffer pointer. + uint32_t buffer_size; ///< Size of dw_spi_read::buffer. + uint64_t status_reg; ///< Pointer to SR register. + uint64_t data_reg; ///< Pointer to DR register. + uint8_t read_cmd; ///< Read data command. + uint8_t four_byte_mode; ///< Four byte addressing mode flag. +} __attribute__((packed)); + +#endif /* OPENOCD_FLASH_NOR_DW_SPI_HELPER_H */ diff --git a/src/flash/nor/dw-spi.c b/src/flash/nor/dw-spi.c new file mode 100644 index 0000000000..e1965477e1 --- /dev/null +++ b/src/flash/nor/dw-spi.c @@ -0,0 +1,1608 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/** + * @file + * Driver for SPI NOR flash chips connected via DesignWare SPI Core. + * Controller's Linux driver is located at drivers/spi/spi-dw-mmio.c. + * DW-SPI is used in a number of processors, including Microsemi Jaguar2 and + * Ocelot switch chips. + * + * Serial interface (SI) nCS0 pin, which is usually connected to the external + * flash, cannot be controlled via GPIO controller: it is asserted only when + * TX FIFO is not empty. Since JTAG is not fast enough to fill TX FIFO and + * collect data from RX FIFO at the same time even on the slowest SPI clock + * speeds, driver can only operate using functions, loaded in target's memory. + * Therefore, it requires the user to set up DRAM controller and provide + * work-area. + * + * In Microsemi devices, serial interface pins may be governed either + * by Boot or Master controller. For these devices, additional configuration of + * spi_mst address is required to switch between the two. + * + * Currently supported devices typically have much more RAM then NOR Flash + * (Jaguar2 reference design has 256MB RAM and 32MB NOR Flash), so supporting + * work-area sizes smaller then transfer buffer seems like the unnecessary + * complication. + * + * This code was tested on Jaguar2 VSC7448 connected to Macronix MX25L25635F. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "dw-spi-helper.h" +#include "imp.h" +#include "spi.h" + +#include <helper/bits.h> +#include <helper/time_support.h> +#include <target/algorithm.h> +#include <target/breakpoints.h> +#include <target/mips32.h> +#include <target/target_type.h> + +/** + * @brief IP block placement map. + * + * Used for dynamic definition of the register map. + * + * IP block is used on different chips and placed in different locations. + * This structure defines some implementation specific variables. + */ +struct dw_spi_regmap { + uint32_t freq; ///< Clock frequency. + target_addr_t simc; ///< Absolute offset of SIMC register block. + target_addr_t spi_mst; + ///< Absolute offset of ICPU_CFG:SPI_MST register. 0 if not available. + uint8_t si_if_owner_offset; + ///< Offset of \ref si_mode bits in ICPU_CFG:SPI_MST. +}; + +/** + * @brief Register map for Jaguar2 switch devices. + */ +static const struct dw_spi_regmap jaguar2_regmap = { + .freq = 250000000UL, + .simc = 0x70101000UL, + .spi_mst = 0x70000024UL, + .si_if_owner_offset = 6, +}; + +/** + * @brief Register map for Ocelot switch devices. + */ +static const struct dw_spi_regmap ocelot_regmap = { + .freq = 250000000UL, + .simc = 0x70101000UL, + .spi_mst = 0x70000024UL, + .si_if_owner_offset = 4, +}; + +#define DW_SPI_IF_OWNER_WIDTH 2 ///< IF owner register field width. + +/** + * @brief Owner of the SI interface. + */ +enum dw_spi_si_mode { + DW_SPI_SI_MODE_BOOT = 1, + ///< Boot controller maps contents of SPI Flash to memory in read-only mode. + DW_SPI_SI_MODE_MASTER = 2, + ///< SPI controller mode for reading/writing SPI Flash. +}; + +#define DW_SPI_REG_CTRLR0 0x00 ///< General configuration register. +#define DW_SPI_REG_SIMCEN 0x08 ///< Master controller enable register. +#define DW_SPI_REG_SER 0x10 ///< Slave select register. +#define DW_SPI_REG_BAUDR 0x14 ///< Baud rate configuration register. +#define DW_SPI_REG_SR 0x28 ///< Status register. +#define DW_SPI_REG_IMR 0x2c ///< Interrupt configuration register. +#define DW_SPI_REG_DR 0x60 ///< Data register. + +#define DW_SPI_REG_CTRLR0_DFS(x) ((x) & GENMASK(3, 0)) ///< Data frame size. +#define DW_SPI_REG_CTRLR0_FRF(x) (((x) << 4) & GENMASK(5, 4)) ///< SI protocol. +#define DW_SPI_REG_CTRLR0_SCPH(x) ((!!(x)) << 6) ///< Probe position. +#define DW_SPI_REG_CTRLR0_SCPOL(x) ((!!(x)) << 7) ///< Probe polarity. +#define DW_SPI_REG_CTRLR0_TMOD(x) (((x) << 8) & GENMASK(9, 8)) ///< SI mode. +#define DW_SPI_REG_SIMCEN_SIMCEN(x) (!!(x)) ///< Controller enable. +#define DW_SPI_REG_SER_SER(x) ((x) & GENMASK(15, 0)) ///< Slave select bitmask. +#define DW_SPI_REG_BAUDR_SCKDV(x) ((x) & GENMASK(15, 0)) ///< Clock divisor. + +/** + * @brief Driver private state. + */ +struct dw_spi_driver { + bool probed; ///< Bank is probed. + uint32_t id; ///< Chip ID. + unsigned int speed; ///< Flash speed. + unsigned int timeout; ///< Flash timeout in milliseconds. + uint8_t chip_select_bitmask; ///< Chip select bitmask. + bool four_byte_mode; ///< Flash chip is in 32bit address mode. + enum dw_spi_si_mode saved_ctrl_mode; + ///< Previously selected controller mode. + struct dw_spi_regmap regmap; ///< SI controller regmap. + const struct flash_device *spi_flash; ///< SPI flash device info. +}; + +/** + * @brief Register used to pass argument struct to helper functions. + */ +#define DW_SPI_ARG_REG "r4" + +/** + * @brief Default timeout value in ms for flash transaction jobs. + */ +#define DW_SPI_TIMEOUT_DEFAULT (600 * 1000) + +/** + * @brief Timeout value in ms for short flash transactions, + * e.g. reading flash ID and status register. + */ +#define DW_SPI_TIMEOUT_TRANSACTION 1000 + +/** + * @brief Select SI interface owner. + * + * Mode selection is skipped if Boot controller not available on target + * (i.e. spi_mst command argument is not configured). + * + * @param[in] bank: Flash bank. + * @param[in] mode: New controller mode. + * @return Command execution status. + */ +static int +dw_spi_ctrl_mode(const struct flash_bank *const bank, enum dw_spi_si_mode mode) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + if (!regmap->spi_mst) + return ERROR_OK; + + uint32_t ctrl; + int ret = target_read_u32(target, regmap->spi_mst, &ctrl); + if (ret) { + LOG_ERROR("DW SPI SPI:MST register read error"); + return ret; + } + ctrl &= ~GENMASK(DW_SPI_IF_OWNER_WIDTH + driver->regmap.si_if_owner_offset, + driver->regmap.si_if_owner_offset); + ctrl |= mode << driver->regmap.si_if_owner_offset; + + ret = target_write_u32(target, regmap->spi_mst, ctrl); + if (ret) + LOG_ERROR("DW SPI controller mode configuration error"); + + return ret; +} + +/** + * @brief Select master controller as SI interface owner. + * + * Previous interface owner is restored via dw_spi_ctrl_mode_restore() function. + * Mode selection is skipped if Boot controller not available on target + * (i.e. spi_mst command argument is not configured). + * + * @param[in] bank: Flash bank. + * @param[in] mode: New controller mode. + * @return Command execution status. + */ +static int +dw_spi_ctrl_mode_configure(const struct flash_bank *const bank, + enum dw_spi_si_mode mode) +{ + struct target *const target = bank->target; + struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + if (!regmap->spi_mst) + return ERROR_OK; + + uint32_t ctrl; + int ret = target_read_u32(target, regmap->spi_mst, &ctrl); + if (ret) { + LOG_ERROR("DW SPI controller mode query error"); + return ret; + } + driver->saved_ctrl_mode = + (enum dw_spi_si_mode)((ctrl >> driver->regmap.si_if_owner_offset) & + GENMASK(DW_SPI_IF_OWNER_WIDTH, 0)); + + return dw_spi_ctrl_mode(bank, mode); +} + +/** + * @brief Restore SI controller mode. + * + * Restore initially configured SI controller mode. Undo configuration done by + * dw_spi_ctrl_mode_configure() function. + * Mode selection is skipped if Boot controller not available on target + * (i.e. spi_mst command argument is not configured). + * + * @param[in] bank: Flash bank. + * @return Command execution status. + */ +static int +dw_spi_ctrl_mode_restore(const struct flash_bank *const bank) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + + return dw_spi_ctrl_mode(bank, driver->saved_ctrl_mode); +} + +/** + * @brief Enable master controller. + * + * Configuration of the master controller must be done when it is disabled. + * + * @param[in] bank: Flash bank. + * @param[in] value: New enable state. + * @return Command execution status. + */ +static int +dw_spi_master_ctrl_enable(const struct flash_bank *const bank, bool value) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_SIMCEN, + DW_SPI_REG_SIMCEN_SIMCEN(value)); + if (ret) + LOG_ERROR("DW SPI master controller enable flag configuration error"); + + return ret; +} + +/** + * @brief Configure SI transfer mode. + * + * @param[in] bank: Flash bank. + * @return Command execution status. + */ +static int +dw_spi_ctrl_configure_si(const struct flash_bank *const bank) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + // 8 bit frame; Motorola protocol; middle lo probe; TX RX mode + const uint32_t mode = DW_SPI_REG_CTRLR0_DFS(0x7) | + DW_SPI_REG_CTRLR0_FRF(0) | + DW_SPI_REG_CTRLR0_SCPH(0) | + DW_SPI_REG_CTRLR0_SCPOL(0) | + DW_SPI_REG_CTRLR0_TMOD(0); + + int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_CTRLR0, mode); + if (ret) { + LOG_ERROR("DW SPI master controller configuration query error"); + return ret; + } + + ret = target_write_u32(target, regmap->simc + DW_SPI_REG_SER, + DW_SPI_REG_SER_SER(driver->chip_select_bitmask)); + if (ret) + LOG_ERROR("DW SPI slave select configuration error"); + + return ret; +} + +/** + * @brief Configure SI transfer speed. + * + * @param[in] bank: Flash bank. + * @return Command execution status. + */ +static int +dw_spi_ctrl_configure_speed(const struct flash_bank *const bank) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + // divisor LSB must be zero + const uint16_t div = MIN((regmap->freq / driver->speed), 0xfffe) & 0xfffe; + + int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_BAUDR, + DW_SPI_REG_BAUDR_SCKDV(div)); + if (ret) { + LOG_ERROR("DW SPI speed configuration error"); + return ret; + } + + unsigned int speed = regmap->freq / div; + LOG_DEBUG("DW SPI setting NOR controller speed to %u kHz", speed / 1000); + + return ret; +} + +/** + * @brief Disable SI master controller interrupts. + * + * @param[in] bank: Flash bank. + * @return Command execution status. + */ +static int +dw_spi_ctrl_disable_interrupts(const struct flash_bank *const bank) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_IMR, 0); + if (ret) + LOG_ERROR("DW SPI disable interrupts error"); + + return ret; +} + +/** + * @brief Do data transaction. + * + * Buffer data are sent and replaced with received data. Total buffer size + * is a sum of TX and RX messages. RX portion of the buffer is initially + * filled with dummy values, which get replaced by the message. + * + * @param[in] bank: Flash bank. + * @param[in,out] buffer: Data buffer. If \p read flag is set, buffer is + * filled with received data. + * @param[in] size: \p buffer size. + * @param[in] read: The read flag. If set to true, read values will override + * \p buffer. + * @return Command execution status. + */ +static int +dw_spi_ctrl_transaction(const struct flash_bank *const bank, + uint8_t *const buffer, size_t size, bool read) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + static const uint8_t target_code[] = { +#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc" + }; + const size_t target_code_size = sizeof(target_code); + const size_t total_working_area_size = + target_code_size + sizeof(struct dw_spi_transaction) + size; + + // allocate working area, memory args and data buffer + struct working_area *helper; + int ret = target_alloc_working_area(target, target_code_size, &helper); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper; + } + + struct working_area *helper_args; + ret = target_alloc_working_area(target, sizeof(struct dw_spi_transaction), + &helper_args); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper_args; + } + + struct working_area *target_buffer; + ret = target_alloc_working_area(target, size, &target_buffer); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_target_buffer; + } + + // write algorithm code and buffer to working areas + ret = target_write_buffer(target, helper->address, target_code_size, + target_code); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + ret = target_write_buffer(target, target_buffer->address, size, buffer); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + // prepare helper execution + struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC, + .isa_mode = MIPS32_ISA_MIPS32 }; + + struct reg_param reg_param; + init_reg_param(®_param, DW_SPI_ARG_REG, 32, PARAM_OUT); + struct mem_param mem_param; + init_mem_param(&mem_param, helper_args->address, helper_args->size, + PARAM_OUT); + + // Set the arguments for the helper + buf_set_u32(reg_param.value, 0, 32, helper_args->address); + + struct dw_spi_transaction *helper_args_val = + (struct dw_spi_transaction *)mem_param.value; + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer, + target_buffer->address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->size, size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg, + regmap->simc + DW_SPI_REG_SR); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg, + regmap->simc + DW_SPI_REG_DR); + helper_args_val->read_flag = read; + + ret = target_run_algorithm(target, 1, &mem_param, 1, ®_param, + helper->address, 0, DW_SPI_TIMEOUT_TRANSACTION, + &mips32_algo); + + if (ret) { + LOG_ERROR("DW SPI flash algorithm error"); + goto cleanup; + } + + if (read) { + ret = target_read_buffer(target, target_buffer->address, size, buffer); + if (ret) + LOG_ERROR("DW SPI target buffer read error"); + } + +cleanup: + destroy_reg_param(®_param); + destroy_mem_param(&mem_param); + +err_write_buffer: + target_free_working_area(target, target_buffer); +err_target_buffer: + target_free_working_area(target, helper_args); +err_helper_args: + target_free_working_area(target, helper); +err_helper: + + return ret; +} + +/** + * @brief Check that selected region is filled with pattern. + * + * This function is used for Flash erase checking. + * + * @param[in] bank: Flash bank. + * @param[in] address: Starting address. Sector aligned. + * @param[in] sector_size: Size of sector. + * @param[in] sector_count: Number of sectors. + * @param[in] pattern: Fill pattern. + * @param[in] read_cmd: Flash read command. + * @param[out] buffer: Filled flag array. Must hold \p sector_count number + * of entries. + * @return Command execution status. + */ +static int +dw_spi_ctrl_check_sectors_fill(const struct flash_bank *const bank, + uint32_t address, size_t sector_size, + size_t sector_count, uint8_t pattern, + uint8_t read_cmd, uint8_t *buffer) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + static const uint8_t target_code[] = { +#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc" + }; + const size_t target_code_size = sizeof(target_code); + const size_t total_working_area_size = + target_code_size + sizeof(struct dw_spi_check_fill) + sector_count; + + // allocate working area, memory args and data buffer + struct working_area *helper; + int ret = target_alloc_working_area(target, target_code_size, &helper); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper; + } + + struct working_area *helper_args; + ret = target_alloc_working_area(target, sizeof(struct dw_spi_check_fill), + &helper_args); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper_args; + } + + struct working_area *target_buffer; + ret = target_alloc_working_area(target, sector_count, &target_buffer); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_target_buffer; + } + + // write algorithm code and buffer to working areas + ret = target_write_buffer(target, helper->address, target_code_size, + target_code); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + // prepare helper execution + struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC, + .isa_mode = MIPS32_ISA_MIPS32 }; + + struct reg_param reg_param; + init_reg_param(®_param, DW_SPI_ARG_REG, 32, PARAM_OUT); + struct mem_param mem_param; + init_mem_param(&mem_param, helper_args->address, helper_args->size, + PARAM_OUT); + + // Set the arguments for the helper + buf_set_u32(reg_param.value, 0, 32, helper_args->address); + + struct dw_spi_check_fill *helper_args_val = + (struct dw_spi_check_fill *)mem_param.value; + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->address, + address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_size, + sector_size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_count, + sector_count); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg, + regmap->simc + DW_SPI_REG_SR); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg, + regmap->simc + DW_SPI_REG_DR); + target_buffer_set_u32(target, + (uint8_t *)&helper_args_val->fill_status_array, + target_buffer->address); + helper_args_val->pattern = pattern; + helper_args_val->read_cmd = read_cmd; + helper_args_val->four_byte_mode = driver->four_byte_mode; + + ret = target_run_algorithm(target, 1, &mem_param, 1, ®_param, + helper->address, 0, driver->timeout, + &mips32_algo); + + if (ret) { + LOG_ERROR("DW SPI flash algorithm error"); + goto cleanup; + } + + ret = target_read_buffer(target, target_buffer->address, sector_count, + buffer); + if (ret) + LOG_ERROR("DW SPI target buffer read error"); + +cleanup: + destroy_reg_param(®_param); + destroy_mem_param(&mem_param); + +err_write_buffer: + target_free_working_area(target, target_buffer); +err_target_buffer: + target_free_working_area(target, helper_args); +err_helper_args: + target_free_working_area(target, helper); +err_helper: + + return ret; +} + +/** + * @brief Write flash region. + * + * @param[in] bank: Flash bank. + * @param[in] address: First page address. Page aligned when write is crossing + * the page boundary. + * @param[in] buffer: Data buffer. + * @param[in] buffer_size: \p buffer size. + * @param[in] page_size: Size of flash page. + * @param[in] stat_cmd: Flash command to read chip status. + * @param[in] we_cmd: Flash command to enable write. + * @param[in] program_cmd: Flash command to program chip. + * @param[in] we_mask: Status byte write enable mask. + * @param[in] busy_mask: Status byte write busy mask. + * @return Command execution status. + */ +static int +dw_spi_ctrl_program(const struct flash_bank *const bank, uint32_t address, + const uint8_t *const buffer, size_t buffer_size, + uint32_t page_size, uint8_t stat_cmd, uint8_t we_cmd, + uint8_t program_cmd, uint8_t we_mask, uint8_t busy_mask) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + static const uint8_t target_code[] = { +#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc" + }; + const size_t target_code_size = sizeof(target_code); + const size_t total_working_area_size = + target_code_size + sizeof(struct dw_spi_program) + buffer_size; + + // allocate working area, memory args and data buffer + struct working_area *helper; + int ret = target_alloc_working_area(target, target_code_size, &helper); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper; + } + + struct working_area *helper_args; + ret = target_alloc_working_area(target, sizeof(struct dw_spi_program), + &helper_args); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper_args; + } + + struct working_area *target_buffer; + ret = target_alloc_working_area(target, buffer_size, &target_buffer); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_target_buffer; + } + + // write algorithm code and buffer to working areas + ret = target_write_buffer(target, helper->address, target_code_size, + target_code); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + ret = target_write_buffer(target, target_buffer->address, buffer_size, + buffer); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + // prepare helper execution + struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC, + .isa_mode = MIPS32_ISA_MIPS32 }; + + struct reg_param reg_param; + init_reg_param(®_param, DW_SPI_ARG_REG, 32, PARAM_OUT); + struct mem_param mem_param; + init_mem_param(&mem_param, helper_args->address, helper_args->size, + PARAM_OUT); + + // Set the arguments for the helper + buf_set_u32(reg_param.value, 0, 32, helper_args->address); + struct dw_spi_program *helper_args_val = + (struct dw_spi_program *)mem_param.value; + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->address, + address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->page_size, + page_size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer, + target_buffer->address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer_size, + buffer_size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg, + regmap->simc + DW_SPI_REG_SR); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg, + regmap->simc + DW_SPI_REG_DR); + helper_args_val->read_status_cmd = stat_cmd; + helper_args_val->write_enable_cmd = we_cmd; + helper_args_val->program_cmd = program_cmd; + helper_args_val->write_enable_mask = we_mask; + helper_args_val->busy_mask = busy_mask; + helper_args_val->four_byte_mode = driver->four_byte_mode; + + ret = target_run_algorithm(target, 1, &mem_param, 1, ®_param, + helper->address, 0, driver->timeout, + &mips32_algo); + if (ret) + LOG_ERROR("DW SPI flash algorithm error"); + + destroy_reg_param(®_param); + destroy_mem_param(&mem_param); + +err_write_buffer: + target_free_working_area(target, target_buffer); +err_target_buffer: + target_free_working_area(target, helper_args); +err_helper_args: + target_free_working_area(target, helper); +err_helper: + + return ret; +} + +/** + * @brief Erase sectors. + * + * @param[in] bank: Flash bank. + * @param[in] address: Flash address. Must be sector aligned. + * @param[in] sector_size: Size of flash sector. + * @param[in] sector_count: Number of sectors to erase. + * @param[in] stat_cmd: Flash command to read chip status. + * @param[in] we_cmd: Flash command to set enable write. + * @param[in] erase_sector_cmd: Flash command to set erase sector. + * @param[in] we_mask: Status byte write enable mask. + * @param[in] busy_mask: Status byte write busy mask. + * @return Command execution status. + */ +static int +dw_spi_ctrl_erase_sectors(const struct flash_bank *const bank, uint32_t address, + uint32_t sector_size, size_t sector_count, + uint8_t stat_cmd, uint8_t we_cmd, + uint8_t erase_sector_cmd, uint8_t we_mask, + uint8_t busy_mask) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + static const uint8_t target_code[] = { +#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc" + }; + const size_t target_code_size = sizeof(target_code); + const size_t total_working_area_size = + target_code_size + sizeof(struct dw_spi_erase); + + // allocate working area and memory args + struct working_area *helper; + int ret = target_alloc_working_area(target, target_code_size, &helper); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper; + } + + struct working_area *helper_args; + ret = target_alloc_working_area(target, sizeof(struct dw_spi_erase), + &helper_args); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper_args; + } + + // write algorithm code to working area + ret = target_write_buffer(target, helper->address, target_code_size, + target_code); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + // prepare helper execution + struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC, + .isa_mode = MIPS32_ISA_MIPS32 }; + + struct reg_param reg_param; + init_reg_param(®_param, DW_SPI_ARG_REG, 32, PARAM_OUT); + struct mem_param mem_param; + init_mem_param(&mem_param, helper_args->address, helper_args->size, + PARAM_OUT); + + // Set the arguments for the helper + buf_set_u32(reg_param.value, 0, 32, helper_args->address); + struct dw_spi_erase *helper_args_val = + (struct dw_spi_erase *)mem_param.value; + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->address, + address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_size, + sector_size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_count, + sector_count); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg, + regmap->simc + DW_SPI_REG_SR); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg, + regmap->simc + DW_SPI_REG_DR); + helper_args_val->read_status_cmd = stat_cmd; + helper_args_val->write_enable_cmd = we_cmd; + helper_args_val->erase_sector_cmd = erase_sector_cmd; + helper_args_val->write_enable_mask = we_mask; + helper_args_val->busy_mask = busy_mask; + helper_args_val->four_byte_mode = driver->four_byte_mode; + + ret = target_run_algorithm(target, 1, &mem_param, 1, ®_param, + helper->address, 0, driver->timeout, + &mips32_algo); + if (ret) + LOG_ERROR("DW SPI flash algorithm error"); + + destroy_reg_param(®_param); + destroy_mem_param(&mem_param); + +err_write_buffer: + target_free_working_area(target, helper_args); +err_helper_args: + target_free_working_area(target, helper); +err_helper: + + return ret; +} + +/** + * @brief Read flash data. + * + * @param[in] bank: Flash bank. + * @param[in] address: Flash address. + * @param[out] buffer: Data buffer. + * @param[in] buffer_size: \p buffer size. + * @param[in] read_cmd: Flash command to read data from flash. + * @return Command execution status. + */ +static int +dw_spi_ctrl_read(const struct flash_bank *const bank, uint32_t address, + uint8_t *buffer, size_t buffer_size, uint8_t read_cmd) +{ + struct target *const target = bank->target; + const struct dw_spi_driver *const driver = bank->driver_priv; + const struct dw_spi_regmap *const regmap = &driver->regmap; + + static const uint8_t target_code[] = { +#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc" + }; + const size_t target_code_size = sizeof(target_code); + const size_t total_working_area_size = + target_code_size + sizeof(struct dw_spi_read) + buffer_size; + + // allocate working area and memory args + struct working_area *helper; + int ret = target_alloc_working_area(target, target_code_size, &helper); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper; + } + + struct working_area *helper_args; + ret = target_alloc_working_area(target, sizeof(struct dw_spi_read), + &helper_args); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_helper_args; + } + + struct working_area *target_buffer; + ret = target_alloc_working_area(target, buffer_size, &target_buffer); + if (ret) { + LOG_ERROR("DW SPI could not allocate working area. Need %zx", + total_working_area_size); + goto err_target_buffer; + } + + // write algorithm code to working area + ret = target_write_buffer(target, helper->address, target_code_size, + target_code); + if (ret) { + LOG_ERROR("DW SPI writing to working area error"); + goto err_write_buffer; + } + + // prepare helper execution + struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC, + .isa_mode = MIPS32_ISA_MIPS32 }; + + struct reg_param reg_param; + init_reg_param(®_param, DW_SPI_ARG_REG, 32, PARAM_OUT); + struct mem_param mem_param; + init_mem_param(&mem_param, helper_args->address, helper_args->size, + PARAM_OUT); + + // Set the arguments for the helper + buf_set_u32(reg_param.value, 0, 32, helper_args->address); + struct dw_spi_read *helper_args_val = (struct dw_spi_read *)mem_param.value; + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->address, + address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer, + target_buffer->address); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer_size, + buffer_size); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg, + regmap->simc + DW_SPI_REG_SR); + target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg, + regmap->simc + DW_SPI_REG_DR); + helper_args_val->read_cmd = read_cmd; + helper_args_val->four_byte_mode = driver->four_byte_mode; + + ret = target_run_algorithm(target, 1, &mem_param, 1, ®_param, + helper->address, 0, driver->timeout, + &mips32_algo); + if (ret) { + LOG_ERROR("DW SPI flash algorithm error"); + goto cleanup; + } + + ret = + target_read_buffer(target, target_buffer->address, buffer_size, buffer); + if (ret) + LOG_ERROR("DW SPI target buffer read error"); + +cleanup: + destroy_reg_param(®_param); + destroy_mem_param(&mem_param); + +err_write_buffer: + target_free_working_area(target, target_buffer); +err_target_buffer: + target_free_working_area(target, helper_args); +err_helper_args: + target_free_working_area(target, helper); +err_helper: + + return ret; +} + +/** + * @brief Read Flash device ID. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_read_id(const struct flash_bank *const bank) +{ + struct dw_spi_driver *const driver = bank->driver_priv; + + const size_t buffer_size = 1 + 3 + 1; + uint8_t buffer[buffer_size]; + + memset(buffer, 0, buffer_size); + buffer[0] = SPIFLASH_READ_ID; + + int ret = dw_spi_ctrl_transaction(bank, buffer, buffer_size, true); + if (ret) { + LOG_ERROR("DW SPI flash ID read error"); + return ret; + } + + buffer[buffer_size - 1] = 0; + // use le_to_h_u32 to decode flash ID as per JEDEC SFDP + driver->id = le_to_h_u32(buffer + 1); + LOG_DEBUG("DW SPI read flash ID %" PRIx32, driver->id); + + return ERROR_OK; +} + +/** + * @brief Read Flash device status. + * + * @param[in] bank: Flash bank handle. + * @param[out] status: The status byte. + * @return Command execution status. + */ +static int +dw_spi_read_status(const struct flash_bank *const bank, uint8_t *const status) +{ + const int buffer_size = 2; + uint8_t buffer[buffer_size]; + + memset(buffer, 0, buffer_size); + buffer[0] = SPIFLASH_READ_STATUS; + + int ret = dw_spi_ctrl_transaction(bank, buffer, buffer_size, true); + if (ret) { + LOG_ERROR("DW SPI flash status read error"); + return ret; + } + + *status = buffer[1]; + + return ERROR_OK; +} + +/** + * @brief Wait for Flash command to finish. + * + * @param[in] bank: Flash bank handle. + * @param[in] timeout: The timeout in ms. + * @return Command execution status. + */ +static int +dw_spi_wait_finish(const struct flash_bank *const bank, unsigned int timeout) +{ + const int64_t end_time = timeval_ms() + timeout; + while (timeval_ms() <= end_time) { + uint8_t status; + int ret = dw_spi_read_status(bank, &status); + if (ret) { + LOG_ERROR("DW SPI status query error"); + return ret; + } + if (!(status & SPIFLASH_BSY_BIT)) + return ERROR_OK; + + alive_sleep(1); + } + + LOG_ERROR("DW SPI process timeout"); + return ERROR_TIMEOUT_REACHED; +} + +/** + * @brief Flash device write enable. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_write_enable(const struct flash_bank *const bank) +{ + const int buffer_size = 1; + uint8_t buffer[buffer_size]; + + memset(buffer, 0, buffer_size); + buffer[0] = SPIFLASH_WRITE_ENABLE; + + int ret = dw_spi_ctrl_transaction(bank, buffer, buffer_size, false); + if (ret) { + LOG_ERROR("DW SPI flash write enable error"); + return ret; + } + + uint8_t status; + ret = dw_spi_read_status(bank, &status); + if (ret) + return ret; + + return status & SPIFLASH_WE_BIT ? ERROR_OK : ERROR_FAIL; +} + +/** + * @brief Erase Flash chip. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_erase_chip(const struct flash_bank *const bank) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + + const int buffer_size = 1; + uint8_t buffer[buffer_size]; + + int ret = dw_spi_write_enable(bank); + if (ret) + return ret; + + memset(buffer, 0, buffer_size); + buffer[0] = driver->spi_flash->chip_erase_cmd; + + ret = dw_spi_ctrl_transaction(bank, buffer, buffer_size, false); + if (ret) { + LOG_ERROR("DW SPI erase flash error"); + return ret; + } + + ret = dw_spi_wait_finish(bank, driver->timeout); + if (ret) { + LOG_ERROR("DW SPI erase flash timeout"); + return ret; + } + + return ERROR_OK; +} + +/** + * @brief Flash device erase sectors. + * + * @param[in] bank: Flash bank handle. + * @param[in] first: The first sector to erase. + * @param[in] last: The last sector to erase. + * @return Command execution status. + */ +static int +dw_spi_erase_sectors(const struct flash_bank *const bank, unsigned int first, + unsigned int last) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + + if (first == 0 && last >= (bank->num_sectors - 1)) { + // full erase + int ret = dw_spi_erase_chip(bank); + if (ret) + return ret; + } else { + // partial erase + int ret = dw_spi_ctrl_erase_sectors(bank, bank->sectors[first].offset, + driver->spi_flash->sectorsize, + last - first + 1, + SPIFLASH_READ_STATUS, + SPIFLASH_WRITE_ENABLE, + driver->spi_flash->erase_cmd, + SPIFLASH_WE_BIT, SPIFLASH_BSY_BIT); + if (ret) { + LOG_ERROR("DW SPI flash erase sectors error"); + return ret; + } + } + + return ERROR_OK; +} + +/** + * @brief Flash bank blank check. + */ +static int +dw_spi_blank_check(struct flash_bank *bank, size_t sector_count, + uint8_t pattern) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + + uint8_t *erased = malloc(sector_count); + if (!erased) { + LOG_ERROR("could not allocate memory"); + return ERROR_FAIL; + } + + // set initial erased value to unknown + memset(erased, 2, sector_count); + for (unsigned int sector_idx = 0; sector_idx < sector_count; sector_idx++) + bank->sectors[sector_idx].is_erased = 2; + + int ret = dw_spi_ctrl_check_sectors_fill(bank, 0, bank->sectors[0].size, + sector_count, pattern, + driver->spi_flash->read_cmd, + erased); + if (!ret) { + for (unsigned int sector_idx = 0; sector_idx < sector_count; + sector_idx++) + bank->sectors[sector_idx].is_erased = erased[sector_idx]; + } else { + LOG_ERROR("DW SPI flash erase check error"); + } + + free(erased); + + return ret; +} + +/** + * @brief Write buffer to Flash. + * + * @param[in] bank: Flash bank handle. + * @param[in] buffer: Data buffer. + * @param[in] offset: Flash address offset. + * @param[in] count: \p buffer size. + * @return Command execution status. + */ +static int +dw_spi_write_buffer(const struct flash_bank *const bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + const size_t page_size = driver->spi_flash->pagesize; + + // Write unaligned first sector separately as helper function does + // not handle this case well. + struct { + uint32_t address; + const uint8_t *buffer; + size_t count; + } chunks[2] = { + { .address = offset, .buffer = buffer, .count = 0 }, + { .address = offset, .buffer = buffer, .count = count }, + }; + + if (offset % page_size) { + // start is not aligned + chunks[0].count = MIN(page_size - (offset % page_size), count); + chunks[1].count -= chunks[0].count; + chunks[1].address += chunks[0].count; + chunks[1].buffer += chunks[0].count; + } + + for (unsigned int chunk_idx = 0; chunk_idx < ARRAY_SIZE(chunks); + chunk_idx++) { + if (chunks[chunk_idx].count > 0) { + int ret = dw_spi_ctrl_program(bank, chunks[chunk_idx].address, + chunks[chunk_idx].buffer, + chunks[chunk_idx].count, page_size, + SPIFLASH_READ_STATUS, + SPIFLASH_WRITE_ENABLE, + driver->spi_flash->pprog_cmd, + SPIFLASH_WE_BIT, SPIFLASH_BSY_BIT); + if (ret) { + LOG_ERROR("DW SPI flash write error"); + return ret; + } + } + } + + return ERROR_OK; +} + +/** + * @brief Search for Flash chip info. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_spiflash_search(const struct flash_bank *const bank) +{ + struct dw_spi_driver *const driver = bank->driver_priv; + + int ret = dw_spi_read_id(bank); + if (ret) + return ret; + + unsigned int idx = 0; + while (flash_devices[idx].name) { + if (flash_devices[idx].device_id == driver->id) { + driver->spi_flash = &flash_devices[idx]; + return ERROR_OK; + } + idx++; + } + + LOG_ERROR("DW SPI could not find Flash with ID %" PRIx32 + " in SPI Flash table: either Flash device is not supported " + "or communication speed is too high", + driver->id); + return ERROR_FAIL; +} + +/** + * @brief Handle flash bank command. + * + * @param[in] CMD_ARGC: Number of arguments. + * @param[in] CMD_ARGV: Command arguments. + * @return Command execution status. + */ +FLASH_BANK_COMMAND_HANDLER(dw_spi_flash_bank_command) +{ + unsigned int speed = 1000000; + unsigned int timeout = DW_SPI_TIMEOUT_DEFAULT; + uint8_t chip_select_bitmask = BIT(0); + struct dw_spi_regmap regmap = { 0 }; + + if (CMD_ARGC < 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int idx = 6; idx < CMD_ARGC; idx++) { + if (strcmp(CMD_ARGV[idx], "-jaguar2") == 0) { + // Fast config for Jaguar2 chips. + memcpy(®map, &jaguar2_regmap, sizeof(jaguar2_regmap)); + } else if (strcmp(CMD_ARGV[idx], "-ocelot") == 0) { + // Fast config for Ocelot chips. + memcpy(®map, &ocelot_regmap, sizeof(ocelot_regmap)); + } else if (strcmp(CMD_ARGV[idx], "-freq") == 0) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[++idx], regmap.freq); + } else if (strcmp(CMD_ARGV[idx], "-simc") == 0) { + COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[++idx], regmap.simc); + } else if (strcmp(CMD_ARGV[idx], "-spi_mst") == 0) { + COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[++idx], regmap.spi_mst); + } else if (strcmp(CMD_ARGV[idx], "-if_owner_offset") == 0) { + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[++idx], + regmap.si_if_owner_offset); + } else if (strcmp(CMD_ARGV[idx], "-speed") == 0) { + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[++idx], speed); + } else if (strcmp(CMD_ARGV[idx], "-timeout") == 0) { + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[++idx], timeout); + timeout *= 1000; // convert to ms + } else if (strcmp(CMD_ARGV[idx], "-chip_select") == 0) { + unsigned int cs_bit; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[++idx], cs_bit); + chip_select_bitmask = BIT(cs_bit); + } else { + LOG_WARNING("DW SPI unknown argument %s", CMD_ARGV[idx]); + } + } + + if (!regmap.simc) { + LOG_ERROR("DW SPI cannot use boot controller with unconfigured simc"); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + bank->driver_priv = malloc(sizeof(struct dw_spi_driver)); + if (!bank->driver_priv) { + LOG_ERROR("could not allocate memory"); + return ERROR_FAIL; + } + + struct dw_spi_driver *driver = bank->driver_priv; + memset(driver, 0, sizeof(struct dw_spi_driver)); + driver->speed = speed; + driver->timeout = timeout; + driver->chip_select_bitmask = chip_select_bitmask; + driver->four_byte_mode = true; // 24bit commands not provided by spi.h + memcpy(&driver->regmap, ®map, sizeof(regmap)); + + return ERROR_OK; +} + +/** + * @brief Assert target is halted. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_assert_halted(const struct flash_bank *const bank) +{ + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + return ERROR_OK; +} + +/** + * @brief Prepare master controller for transaction. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_master_ctrl_configure(struct flash_bank *bank) +{ + int ret = dw_spi_assert_halted(bank); + if (ret) + return ret; + ret = dw_spi_ctrl_mode_configure(bank, DW_SPI_SI_MODE_MASTER); + if (ret) { + LOG_ERROR("DW SPI switch to master controller mode error"); + return ret; + } + ret = dw_spi_master_ctrl_enable(bank, false); + if (ret) { + LOG_ERROR("DW SPI disable master controller error"); + return ret; + } + ret = dw_spi_ctrl_configure_speed(bank); + if (ret) { + LOG_ERROR("DW SPI speed configuration error"); + return ret; + } + ret = dw_spi_ctrl_disable_interrupts(bank); + if (ret) { + LOG_ERROR("DW SPI disable SPI interrupts error"); + return ret; + } + ret = dw_spi_ctrl_configure_si(bank); + if (ret) { + LOG_ERROR("DW SPI controller configuration error"); + return ret; + } + ret = dw_spi_master_ctrl_enable(bank, true); + if (ret) { + LOG_ERROR("DW SPI enable master controller error"); + return ret; + } + + return ERROR_OK; +} + +/** + * @brief Restore SI controller selection. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_master_ctrl_restore(struct flash_bank *bank) +{ + int ret = dw_spi_master_ctrl_enable(bank, false); + if (ret) { + LOG_ERROR("DW SPI disable master controller error"); + return ret; + } + ret = dw_spi_ctrl_mode_restore(bank); + if (ret) { + LOG_ERROR("DW SPI controller restore error"); + return ret; + } + + return ret; +} + +/** + * @brief Flash bank probe. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_probe(struct flash_bank *bank) +{ + struct dw_spi_driver *const driver = bank->driver_priv; + + if (!driver) + return ERROR_FAIL; + + if (strcmp(bank->target->type->name, mips_m4k_target.name) != 0 || + bank->target->endianness != TARGET_LITTLE_ENDIAN) { + LOG_ERROR("DW SPI currently only supports " + "little endian mips_m4k target"); + return ERROR_TARGET_INVALID; + } + + int ret = dw_spi_master_ctrl_configure(bank); + if (ret) + return ret; + + ret = dw_spi_spiflash_search(bank); + if (ret) + goto err; + + bank->write_start_alignment = 0; + bank->write_end_alignment = 0; + + uint32_t flash_size = driver->spi_flash->size_in_bytes; + if (!bank->size) { + bank->size = flash_size; + LOG_INFO("DW SPI probed flash size 0x%" PRIx32, flash_size); + } else { + if (flash_size > bank->size) + LOG_WARNING("DW SPI probed flash size 0x%" PRIx32 + " is greater then declared 0x%" PRIx32, + flash_size, bank->size); + if (flash_size < bank->size) { + LOG_ERROR("DW SPI probed flash size 0x%" PRIx32 + " is smaller then declared 0x%" PRIx32, + flash_size, bank->size); + ret = ERROR_FLASH_BANK_INVALID; + goto err; + } + } + bank->num_sectors = bank->size / driver->spi_flash->sectorsize; + + // free previously allocated in case of reprobing + free(bank->sectors); + + bank->sectors = + alloc_block_array(0, driver->spi_flash->sectorsize, bank->num_sectors); + + if (!bank->sectors) { + LOG_ERROR("could not allocate memory"); + ret = ERROR_FAIL; + goto err; + } + + driver->probed = true; + +err: + dw_spi_master_ctrl_restore(bank); + return ret; +} + +/** + * @brief Flash bank erase sectors. + * + * @param[in] bank: Flash bank handle. + * @param[in] first: The first sector to erase. + * @param[in] last: The last sector to erase. + * @return Command execution status. + */ +static int +dw_spi_erase(struct flash_bank *bank, unsigned int first, unsigned int last) +{ + int ret = dw_spi_master_ctrl_configure(bank); + if (ret) + return ret; + + ret = dw_spi_erase_sectors(bank, first, last); + dw_spi_master_ctrl_restore(bank); + return ret; +} + +/** + * @brief Flash bank write data. + * + * @param[in] bank: Flash bank handle. + * @param[in] buffer: Data buffer. + * @param[in] offset: Flash address offset. + * @param[in] count: \p buffer size. + * @return Command execution status. + */ +static int +dw_spi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, + uint32_t count) +{ + int ret = dw_spi_master_ctrl_configure(bank); + if (ret) + return ret; + + ret = dw_spi_write_buffer(bank, buffer, offset, count); + dw_spi_master_ctrl_restore(bank); + return ret; +} + +/** + * @brief Flash bank read data using master controller. + * + * @param[in] bank: Flash bank handle. + * @param[out] buffer: Data buffer. + * @param[in] offset: Flash address offset. + * @param[in] count: \p buffer size. + * @return Command execution status. + */ +static int +dw_spi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, + uint32_t count) +{ + struct dw_spi_driver *const driver = bank->driver_priv; + + int ret = dw_spi_master_ctrl_configure(bank); + if (ret) + return ret; + + ret = dw_spi_ctrl_read(bank, offset, buffer, count, + driver->spi_flash->read_cmd); + dw_spi_master_ctrl_restore(bank); + return ret; +} + +/** + * @brief Flash bank erase check. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_erase_check(struct flash_bank *bank) +{ + int ret = dw_spi_master_ctrl_configure(bank); + if (ret) + return ret; + + ret = dw_spi_blank_check(bank, bank->num_sectors, bank->erased_value); + + dw_spi_master_ctrl_restore(bank); + return ret; +} + +/** + * @brief Flash bank info. + * + * @param[in] bank: Flash bank handle. + * @param[in,out] cmd Command invocation. + * @return Command execution status. + */ +static int +dw_spi_info(struct flash_bank *bank, struct command_invocation *cmd) +{ + const struct dw_spi_driver *const driver = bank->driver_priv; + command_print(cmd, "model %s", driver->spi_flash->name); + command_print(cmd, "ID 0x%" PRIx32, driver->id); + command_print_sameline(cmd, "size 0x%" PRIx32, bank->size); + return ERROR_OK; +} + +/** + * @brief Autoprobe driver. + * + * @param[in] bank: Flash bank handle. + * @return Command execution status. + */ +static int +dw_spi_auto_probe(struct flash_bank *bank) +{ + struct dw_spi_driver *driver = bank->driver_priv; + if (!driver) + return ERROR_FAIL; + if (!driver->probed) + return dw_spi_probe(bank); + return ERROR_OK; +} + +/** + * @brief DW-SPI NOR flash functions. + */ +const struct flash_driver dw_spi_flash = { + .name = "dw-spi", + .flash_bank_command = dw_spi_flash_bank_command, + .erase = dw_spi_erase, + .write = dw_spi_write, + .read = dw_spi_read, + .probe = dw_spi_probe, + .auto_probe = dw_spi_auto_probe, + .erase_check = dw_spi_erase_check, + .info = dw_spi_info, + .verify = default_flash_verify, + .free_driver_priv = default_flash_free_driver_priv, +}; diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index 54fdbd8cbd..f8e0886570 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -251,18 +251,6 @@ static int efm32x_read_info(struct flash_bank *bank) memset(efm32_info, 0, sizeof(struct efm32_info)); - const struct cortex_m_common *cortex_m = target_to_cm(bank->target); - - switch (cortex_m->core_info->partno) { - case CORTEX_M3_PARTNO: - case CORTEX_M4_PARTNO: - case CORTEX_M0P_PARTNO: - break; - default: - LOG_ERROR("Target is not Cortex-Mx Device"); - return ERROR_FAIL; - } - ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib)); if (ret != ERROR_OK) return ret; @@ -1075,8 +1063,8 @@ static int efm32x_probe(struct flash_bank *bank) LOG_INFO("detected part: %s Gecko, rev %d", efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev); - LOG_INFO("flash size = %dkbytes", efm32_mcu_info->flash_sz_kib); - LOG_INFO("flash page size = %dbytes", efm32_mcu_info->page_size); + LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib); + LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size); assert(efm32_mcu_info->page_size != 0); diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c index d73194bc6f..207346f10d 100644 --- a/src/flash/nor/em357.c +++ b/src/flash/nor/em357.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -709,7 +709,7 @@ static int em357_probe(struct flash_bank *bank) em357_info->ppage_size = 4; - LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024); + LOG_INFO("flash size = %d KiB", num_pages * page_size / 1024); free(bank->sectors); diff --git a/src/flash/nor/eneispif.c b/src/flash/nor/eneispif.c new file mode 100644 index 0000000000..6572b8c25b --- /dev/null +++ b/src/flash/nor/eneispif.c @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * Copyright (c) 2024 ENE Technology Inc. + * steven@ene.com.tw +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/time_support.h> +#include <helper/bits.h> +#include <target/target.h> +#include <flash/nor/core.h> +#include <flash/nor/driver.h> +#include <flash/nor/spi.h> + +#define ISPICFG 0x0000 +#define ISPISTS 0x0004 +#define ISPIADDR 0x0008 +#define ISPICMD 0x000C +#define ISPIDAT 0x0100 + +#define ISPISTS_BUSY BIT(0) +#define STATUS1_QE BIT(1) + +#define CFG_READ 0x372 +#define CFG_WRITE 0x371 + +#define ISPI_CTRL_BASE 0x50101000 + +/* name read qread page erase chip device_id page erase flash + * _cmd _cmd _prog _cmd* _erase size size* size + * _cmd _cmd + */ +struct flash_device ene_flash_device = + FLASH_ID("ISPI flash", 0x03, 0x00, 0x02, 0x20, 0x60, 0x00132085, 0x100, 0x1000, 0x80000); + +struct eneispif_flash_bank { + bool probed; + target_addr_t ctrl_base; + uint32_t dev_id; + const struct flash_device *dev; +}; + +FLASH_BANK_COMMAND_HANDLER(eneispif_flash_bank_command) +{ + struct eneispif_flash_bank *eneispif_info; + + LOG_DEBUG("%s", __func__); + + if (CMD_ARGC < 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + eneispif_info = malloc(sizeof(struct eneispif_flash_bank)); + if (!eneispif_info) { + LOG_ERROR("not enough memory"); + return ERROR_FAIL; + } + + bank->driver_priv = eneispif_info; + eneispif_info->probed = false; + eneispif_info->ctrl_base = ISPI_CTRL_BASE; + if (CMD_ARGC >= 7) { + COMMAND_PARSE_ADDRESS(CMD_ARGV[6], eneispif_info->ctrl_base); + LOG_INFO("ASSUMING ISPI device at ctrl_base = " TARGET_ADDR_FMT, + eneispif_info->ctrl_base); + } + + return ERROR_OK; +} + +static int eneispif_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address) +{ + struct target *target = bank->target; + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + + int result = target_read_u32(target, eneispif_info->ctrl_base + address, value); + if (result != ERROR_OK) { + LOG_ERROR("%s error at " TARGET_ADDR_FMT, __func__, + eneispif_info->ctrl_base + address); + return result; + } + LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32, + eneispif_info->ctrl_base + address, *value); + return ERROR_OK; +} + +static int eneispif_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value) +{ + struct target *target = bank->target; + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + + LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32, + eneispif_info->ctrl_base + address, value); + int result = target_write_u32(target, eneispif_info->ctrl_base + address, value); + if (result != ERROR_OK) { + LOG_ERROR("%s error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT, __func__, + value, eneispif_info->ctrl_base + address); + return result; + } + return ERROR_OK; +} + +static int eneispif_wait(struct flash_bank *bank) +{ + int64_t start = timeval_ms(); + + while (1) { + uint32_t status; + + if (eneispif_read_reg(bank, &status, ISPISTS) != ERROR_OK) + return ERROR_FAIL; + + if (!(status & ISPISTS_BUSY)) + break; + + int64_t now = timeval_ms(); + if (now - start > 1000) { + LOG_ERROR("Busy more than 1000ms."); + return ERROR_TARGET_TIMEOUT; + } + } + + return ERROR_OK; +} + +static int eneispi_erase_sector(struct flash_bank *bank, int sector) +{ + int retval = ERROR_OK; + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + uint32_t offset; + uint32_t conf; + + retval = eneispif_read_reg(bank, &conf, ISPICFG); + if (retval != ERROR_OK) + return retval; + + offset = bank->sectors[sector].offset; + retval = eneispif_write_reg(bank, ISPIADDR, offset); /* Address */ + if (retval != ERROR_OK) + goto done; + + eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */ + eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */ + retval = eneispif_write_reg(bank, ISPICMD, eneispif_info->dev->erase_cmd); /* Erase page */ + if (retval != ERROR_OK) + goto done; + + retval = eneispif_wait(bank); + if (retval != ERROR_OK) + goto done; + +done: + eneispif_write_reg(bank, ISPICFG, conf); /* restore */ + return retval; +} + +static int eneispif_erase(struct flash_bank *bank, unsigned int first, unsigned int last) +{ + struct target *target = bank->target; + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + int retval = ERROR_OK; + + LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last); + + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (last < first || last >= bank->num_sectors) { + LOG_ERROR("Flash sector invalid"); + return ERROR_FLASH_SECTOR_INVALID; + } + + if (!(eneispif_info->probed)) { + LOG_ERROR("Flash bank not probed"); + return ERROR_FLASH_BANK_NOT_PROBED; + } + + for (unsigned int sector = first; sector <= last; sector++) { + if (bank->sectors[sector].is_protected) { + LOG_ERROR("Flash sector %u protected", sector); + return ERROR_FAIL; + } + } + + if (eneispif_info->dev->erase_cmd == 0x00) + return ERROR_FLASH_OPER_UNSUPPORTED; + + for (unsigned int sector = first; sector <= last; sector++) { + retval = eneispi_erase_sector(bank, sector); + if (retval != ERROR_OK) + break; + } + + return retval; +} + +static int eneispif_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last) +{ + for (unsigned int sector = first; sector <= last; sector++) + bank->sectors[sector].is_protected = set; + + return ERROR_OK; +} + +static int eneispif_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, + uint32_t count) +{ + struct target *target = bank->target; + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + uint32_t page_size; + uint32_t conf; + int retval = ERROR_OK; + + LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32, bank->size, offset, + count); + + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (offset + count > eneispif_info->dev->size_in_bytes) { + LOG_WARNING("Write past end of flash. Extra data discarded."); + count = eneispif_info->dev->size_in_bytes - offset; + } + + /* Check sector protection */ + for (unsigned int sector = 0; sector < bank->num_sectors; sector++) { + /* Start offset in or before this sector? */ + /* End offset in or behind this sector? */ + if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) && + ((offset + count - 1) >= bank->sectors[sector].offset) && + bank->sectors[sector].is_protected) { + LOG_ERROR("Flash sector %u protected", sector); + return ERROR_FAIL; + } + } + + retval = eneispif_read_reg(bank, &conf, ISPICFG); + if (retval != ERROR_OK) + return retval; + + eneispif_write_reg(bank, ISPICFG, CFG_WRITE); // Cmmmand enable + + /* If no valid page_size, use reasonable default. */ + page_size = + eneispif_info->dev->pagesize ? eneispif_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE; + uint32_t page_offset = offset % page_size; + + while (count > 0) { + uint32_t cur_count; + + /* clip block at page boundary */ + if (page_offset + count > page_size) + cur_count = page_size - page_offset; + else + cur_count = count; + + eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */ + target_write_buffer(target, eneispif_info->ctrl_base + ISPIDAT, cur_count, buffer); + eneispif_write_reg(bank, ISPIADDR, offset); + retval = eneispif_write_reg(bank, ISPICMD, + (cur_count << 16) | eneispif_info->dev->pprog_cmd); + if (retval != ERROR_OK) + goto err; + + page_offset = 0; + buffer += cur_count; + offset += cur_count; + count -= cur_count; + retval = eneispif_wait(bank); + if (retval != ERROR_OK) + goto err; + } + +err: + eneispif_write_reg(bank, ISPICFG, conf); /* restore */ + return retval; +} + +/* Return ID of flash device */ +/* On exit, SW mode is kept */ +static int eneispif_read_flash_id(struct flash_bank *bank, uint32_t *id) +{ + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + struct target *target = bank->target; + int retval; + uint32_t conf, value; + uint8_t buffer[4]; + + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + retval = eneispif_read_reg(bank, &conf, ISPICFG); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("ISPCFG = (0x%08" PRIx32 ")", conf); + + /* read ID from Receive Register */ + eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */ + retval = eneispif_write_reg(bank, ISPICMD, (3 << 16) | SPIFLASH_READ_ID); + if (retval != ERROR_OK) + goto done; + + retval = eneispif_wait(bank); + if (retval != ERROR_OK) + goto done; + + retval = target_read_buffer(target, eneispif_info->ctrl_base + ISPIDAT, 3, buffer); + if (retval != ERROR_OK) + goto done; + value = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0]; + LOG_DEBUG("ISPDAT = (0x%08" PRIx32 ")", value); + + *id = value; +done: + eneispif_write_reg(bank, ISPICFG, conf); // restore + return retval; +} + +static int eneispif_probe(struct flash_bank *bank) +{ + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + struct flash_sector *sectors; + uint32_t id; + int retval; + uint32_t sectorsize; + + if (eneispif_info->probed) + free(bank->sectors); + + eneispif_info->probed = false; + + LOG_INFO("Assuming ISPI flash at address " TARGET_ADDR_FMT + " with controller at " TARGET_ADDR_FMT, + bank->base, eneispif_info->ctrl_base); + + eneispif_write_reg(bank, ISPICFG, CFG_READ); /* RAM map enable */ + + retval = eneispif_read_flash_id(bank, &id); + if (retval != ERROR_OK) + return retval; + + eneispif_info->dev_id = id; + eneispif_info->dev = &ene_flash_device; + + LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")", eneispif_info->dev->name, + eneispif_info->dev_id); + + /* Set correct size value */ + bank->size = eneispif_info->dev->size_in_bytes; + + if (bank->size <= (1UL << 16)) + LOG_WARNING("device needs 2-byte addresses - not implemented"); + + /* if no sectors, treat whole bank as single sector */ + sectorsize = eneispif_info->dev->sectorsize ? eneispif_info->dev->sectorsize + : eneispif_info->dev->size_in_bytes; + + /* create and fill sectors array */ + bank->num_sectors = eneispif_info->dev->size_in_bytes / sectorsize; + sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); + if (!sectors) { + LOG_ERROR("not enough memory"); + return ERROR_FAIL; + } + + for (unsigned int sector = 0; sector < bank->num_sectors; sector++) { + sectors[sector].offset = sector * sectorsize; + sectors[sector].size = sectorsize; + sectors[sector].is_erased = -1; + sectors[sector].is_protected = 0; + } + + bank->sectors = sectors; + eneispif_info->probed = true; + return ERROR_OK; +} + +static int eneispif_auto_probe(struct flash_bank *bank) +{ + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + if (eneispif_info->probed) + return ERROR_OK; + return eneispif_probe(bank); +} + +static int eneispif_protect_check(struct flash_bank *bank) +{ + /* Nothing to do. Protection is only handled in SW. */ + return ERROR_OK; +} + +static int get_eneispif_info(struct flash_bank *bank, struct command_invocation *cmd) +{ + struct eneispif_flash_bank *eneispif_info = bank->driver_priv; + + if (!(eneispif_info->probed)) { + command_print(cmd, "ENE ISPI flash bank not probed yet."); + return ERROR_OK; + } + + command_print(cmd, + "ENE ISPI flash information:\n" + " Device \'%s\' (ID 0x%08" PRIx32 ")", + eneispif_info->dev->name, eneispif_info->dev_id); + + return ERROR_OK; +} + +const struct flash_driver eneispif_flash = { + .name = "eneispif", + .usage = "flash bank <name> 'eneispif' <base_address> <size> 0 0 <target> <ctrl_base>", + .flash_bank_command = eneispif_flash_bank_command, + .erase = eneispif_erase, + .protect = eneispif_protect, + .write = eneispif_write, + .read = default_flash_read, + .probe = eneispif_probe, + .auto_probe = eneispif_auto_probe, + .erase_check = default_flash_blank_check, + .protect_check = eneispif_protect_check, + .info = get_eneispif_info, + .free_driver_priv = default_flash_free_driver_priv, +}; diff --git a/src/flash/nor/esirisc_flash.c b/src/flash/nor/esirisc_flash.c index c30eba894f..938d0f6afa 100644 --- a/src/flash/nor/esirisc_flash.c +++ b/src/flash/nor/esirisc_flash.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Square, Inc. * diff --git a/src/flash/nor/faux.c b/src/flash/nor/faux.c index 542a574589..e76dc493fe 100644 --- a/src/flash/nor/faux.c +++ b/src/flash/nor/faux.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 Øyvind Harboe * diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c index d33c5260c7..395722cb5d 100644 --- a/src/flash/nor/fespi.c +++ b/src/flash/nor/fespi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> * @@ -512,6 +512,12 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer, } } + struct riscv_info *riscv = riscv_info(target); + if (!is_riscv(riscv)) { + LOG_ERROR("Unexpected target type"); + return ERROR_FAIL; + } + unsigned int xlen = riscv_xlen(target); struct working_area *algorithm_wa = NULL; struct working_area *data_wa = NULL; @@ -525,7 +531,7 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer, bin_size = sizeof(riscv64_bin); } - unsigned data_wa_size = 0; + unsigned int data_wa_size = 0; if (target_alloc_working_area(target, bin_size, &algorithm_wa) == ERROR_OK) { retval = target_write_buffer(target, algorithm_wa->address, bin_size, bin); @@ -745,9 +751,9 @@ static int fespi_probe(struct flash_bank *bank) target_device->name, bank->base); } else { - LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT - " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base, - bank->base); + LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT + " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base, + bank->base); } /* read and decode flash ID; returns in SW mode */ diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c index 99fa02cc33..48f4493ab6 100644 --- a/src/flash/nor/fm3.c +++ b/src/flash/nor/fm3.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Marc Willam, Holger Wech * diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c index 2881f1201f..2db79ef502 100644 --- a/src/flash/nor/fm4.c +++ b/src/flash/nor/fm4.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Spansion FM4 flash @@ -107,7 +107,7 @@ static int fm4_flash_erase(struct flash_bank *bank, unsigned int first, struct working_area *workarea; struct reg_param reg_params[4]; struct armv7m_algorithm armv7m_algo; - unsigned i; + unsigned int i; int retval; const uint8_t erase_sector_code[] = { #include "../../../contrib/loaders/flash/fm4/erase.inc" @@ -207,7 +207,7 @@ static int fm4_flash_write(struct flash_bank *bank, const uint8_t *buffer, struct armv7m_algorithm armv7m_algo; uint32_t halfword_count = DIV_ROUND_UP(byte_count, 2); uint32_t result; - unsigned i; + unsigned int i; int retval, retval2 = ERROR_OK; const uint8_t write_block_code[] = { #include "../../../contrib/loaders/flash/fm4/write.inc" @@ -688,24 +688,8 @@ FLASH_BANK_COMMAND_HANDLER(fm4_flash_bank_command) return ret; } -static const struct command_registration fm4_exec_command_handlers[] = { - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration fm4_command_handlers[] = { - { - .name = "fm4", - .mode = COMMAND_ANY, - .help = "fm4 flash command group", - .usage = "", - .chain = fm4_exec_command_handlers, - }, - COMMAND_REGISTRATION_DONE -}; - const struct flash_driver fm4_flash = { .name = "fm4", - .commands = fm4_command_handlers, .flash_bank_command = fm4_flash_bank_command, .info = fm4_get_info_command, .probe = fm4_probe, diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c index ba1160ad51..4b975390be 100644 --- a/src/flash/nor/jtagspi.c +++ b/src/flash/nor/jtagspi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 Robert Jordens <jordens@gmail.com> * @@ -12,6 +12,7 @@ #include <jtag/jtag.h> #include <flash/nor/spi.h> #include <helper/time_support.h> +#include <pld/pld.h> #define JTAGSPI_MAX_TIMEOUT 3000 @@ -21,19 +22,44 @@ struct jtagspi_flash_bank { struct flash_device dev; char devname[32]; bool probed; - bool always_4byte; /* use always 4-byte address except for basic read 0x03 */ - uint32_t ir; - unsigned int addr_len; /* address length in bytes */ + bool always_4byte; /* use always 4-byte address except for basic read 0x03 */ + unsigned int addr_len; /* address length in bytes */ + struct pld_device *pld_device; /* if not NULL, the PLD has special instructions for JTAGSPI */ + uint32_t ir; /* when !pld_device, this instruction code is used in + jtagspi_set_user_ir to connect through a proxy bitstream */ }; FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command) { - struct jtagspi_flash_bank *info; - if (CMD_ARGC < 7) return ERROR_COMMAND_SYNTAX_ERROR; - info = malloc(sizeof(struct jtagspi_flash_bank)); + unsigned int ir = 0; + struct pld_device *device = NULL; + if (strcmp(CMD_ARGV[6], "-pld") == 0) { + if (CMD_ARGC < 8) + return ERROR_COMMAND_SYNTAX_ERROR; + device = get_pld_device_by_name_or_numstr(CMD_ARGV[7]); + if (device) { + bool has_jtagspi_instruction = false; + int retval = pld_has_jtagspi_instruction(device, &has_jtagspi_instruction); + if (retval != ERROR_OK) + return retval; + if (!has_jtagspi_instruction) { + retval = pld_get_jtagspi_userircode(device, &ir); + if (retval != ERROR_OK) + return retval; + device = NULL; + } + } else { + LOG_ERROR("pld device '#%s' is out of bounds or unknown", CMD_ARGV[7]); + return ERROR_FAIL; + } + } else { + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], ir); + } + + struct jtagspi_flash_bank *info = calloc(1, sizeof(struct jtagspi_flash_bank)); if (!info) { LOG_ERROR("no memory for flash bank info"); return ERROR_FAIL; @@ -41,20 +67,25 @@ FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command) bank->sectors = NULL; bank->driver_priv = info; - info->tap = NULL; + if (!bank->target->tap) { + LOG_ERROR("Target has no JTAG tap"); + return ERROR_FAIL; + } + info->tap = bank->target->tap; info->probed = false; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir); + + info->ir = ir; + info->pld_device = device; return ERROR_OK; } -static void jtagspi_set_ir(struct flash_bank *bank) +static void jtagspi_set_user_ir(struct jtagspi_flash_bank *info) { - struct jtagspi_flash_bank *info = bank->driver_priv; struct scan_field field; uint8_t buf[4] = { 0 }; - LOG_DEBUG("loading jtagspi ir"); + LOG_DEBUG("loading jtagspi ir(0x%" PRIx32 ")", info->ir); buf_set_u32(buf, 0, info->tap->ir_length, info->ir); field.num_bits = info->tap->ir_length; field.out_value = buf; @@ -75,6 +106,7 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd, assert(data_buffer || data_len == 0); struct scan_field fields[6]; + struct jtagspi_flash_bank *info = bank->driver_priv; LOG_DEBUG("cmd=0x%02x write_len=%d data_len=%d", cmd, write_len, data_len); @@ -83,22 +115,34 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd, if (is_read) data_len = -data_len; + unsigned int facing_read_bits = 0; + unsigned int trailing_write_bits = 0; + + if (info->pld_device) { + int retval = pld_get_jtagspi_stuff_bits(info->pld_device, &facing_read_bits, &trailing_write_bits); + if (retval != ERROR_OK) + return retval; + } + int n = 0; const uint8_t marker = 1; - fields[n].num_bits = 1; - fields[n].out_value = ▮ - fields[n].in_value = NULL; - n++; - - /* transfer length = cmd + address + read/write, - * -1 due to the counter implementation */ uint8_t xfer_bits[4]; - h_u32_to_be(xfer_bits, ((sizeof(cmd) + write_len + data_len) * CHAR_BIT) - 1); - flip_u8(xfer_bits, xfer_bits, sizeof(xfer_bits)); - fields[n].num_bits = sizeof(xfer_bits) * CHAR_BIT; - fields[n].out_value = xfer_bits; - fields[n].in_value = NULL; - n++; + if (!info->pld_device) { /* mode == JTAGSPI_MODE_PROXY_BITSTREAM */ + facing_read_bits = jtag_tap_count_enabled(); + fields[n].num_bits = 1; + fields[n].out_value = ▮ + fields[n].in_value = NULL; + n++; + + /* transfer length = cmd + address + read/write, + * -1 due to the counter implementation */ + h_u32_to_be(xfer_bits, ((sizeof(cmd) + write_len + data_len) * CHAR_BIT) - 1); + flip_u8(xfer_bits, xfer_bits, sizeof(xfer_bits)); + fields[n].num_bits = sizeof(xfer_bits) * CHAR_BIT; + fields[n].out_value = xfer_bits; + fields[n].in_value = NULL; + n++; + } flip_u8(&cmd, &cmd, sizeof(cmd)); fields[n].num_bits = sizeof(cmd) * CHAR_BIT; @@ -116,10 +160,12 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd, if (data_len > 0) { if (is_read) { - fields[n].num_bits = jtag_tap_count_enabled(); - fields[n].out_value = NULL; - fields[n].in_value = NULL; - n++; + if (facing_read_bits) { + fields[n].num_bits = facing_read_bits; + fields[n].out_value = NULL; + fields[n].in_value = NULL; + n++; + } fields[n].out_value = NULL; fields[n].in_value = data_buffer; @@ -131,16 +177,33 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd, fields[n].num_bits = data_len * CHAR_BIT; n++; } + if (!is_read && trailing_write_bits) { + fields[n].num_bits = trailing_write_bits; + fields[n].out_value = NULL; + fields[n].in_value = NULL; + n++; + } + + if (info->pld_device) { + int retval = pld_connect_spi_to_jtag(info->pld_device); + if (retval != ERROR_OK) + return retval; + } else { + jtagspi_set_user_ir(info); + } - jtagspi_set_ir(bank); /* passing from an IR scan to SHIFT-DR clears BYPASS registers */ - struct jtagspi_flash_bank *info = bank->driver_priv; jtag_add_dr_scan(info->tap, n, fields, TAP_IDLE); int retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (is_read) flip_u8(data_buffer, data_buffer, data_len); - return retval; + + if (info->pld_device) + return pld_disconnect_spi_from_jtag(info->pld_device); + return ERROR_OK; } COMMAND_HANDLER(jtagspi_handle_set) @@ -161,7 +224,12 @@ COMMAND_HANDLER(jtagspi_handle_set) return ERROR_COMMAND_SYNTAX_ERROR; } - retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + /* calling flash_command_get_bank without probing because handle_set is used + to set device parameters if not autodetected. So probing would fail + anyhow. + */ + retval = CALL_COMMAND_HANDLER(flash_command_get_bank_probe_optional, 0, + &bank, false); if (ERROR_OK != retval) return retval; info = bank->driver_priv; @@ -292,52 +360,50 @@ COMMAND_HANDLER(jtagspi_handle_set) COMMAND_HANDLER(jtagspi_handle_cmd) { struct flash_bank *bank; - unsigned int index = 1; - const int max = 21; - uint8_t num_write, num_read, write_buffer[max], read_buffer[1 << CHAR_BIT]; - uint8_t data, *ptr; - char temp[4], output[(2 + max + (1 << CHAR_BIT)) * 3 + 8]; - int retval; + const unsigned int max = 20; + uint8_t cmd_byte, num_read, write_buffer[max], read_buffer[1 << CHAR_BIT]; LOG_DEBUG("%s", __func__); - if (CMD_ARGC < 3) { - command_print(CMD, "jtagspi: not enough arguments"); + if (CMD_ARGC < 3) return ERROR_COMMAND_SYNTAX_ERROR; - } - num_write = CMD_ARGC - 2; + uint8_t num_write = CMD_ARGC - 3; if (num_write > max) { - LOG_ERROR("at most %d bytes may be send", max); - return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "at most %d bytes may be send", max); + return ERROR_COMMAND_ARGUMENT_INVALID; } - retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + /* calling flash_command_get_bank without probing because we like to be + able to send commands before auto-probing occurred. For example sending + "release from power down" is needed before probing when flash is in + power down mode. + */ + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_probe_optional, 0, + &bank, false); + if (retval != ERROR_OK) return retval; - COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], num_read); + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], num_read); + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte); - snprintf(output, sizeof(output), "spi: "); - for (ptr = &write_buffer[0] ; index < CMD_ARGC; index++) { - COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index], data); - *ptr++ = data; - snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data); - strncat(output, temp, sizeof(output) - strlen(output) - 1); - } - strncat(output, "-> ", sizeof(output) - strlen(output) - 1); + for (unsigned int i = 0; i < num_write; i++) + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[i + 3], write_buffer[i]); /* process command */ - ptr = &read_buffer[0]; - jtagspi_cmd(bank, write_buffer[0], &write_buffer[1], num_write - 1, ptr, -num_read); + retval = jtagspi_cmd(bank, cmd_byte, write_buffer, num_write, read_buffer, -num_read); if (retval != ERROR_OK) return retval; - for ( ; num_read > 0; num_read--) { - snprintf(temp, sizeof(temp), "%02" PRIx8 " ", *ptr++); - strncat(output, temp, sizeof(output) - strlen(output) - 1); - } - command_print(CMD, "%s", output); + command_print_sameline(CMD, "spi: %02" PRIx8, cmd_byte); + + for (unsigned int i = 0; i < num_write; i++) + command_print_sameline(CMD, " %02" PRIx8, write_buffer[i]); + + command_print_sameline(CMD, " ->"); + + for (unsigned int i = 0; i < num_read; i++) + command_print_sameline(CMD, " %02" PRIx8, read_buffer[i]); return ERROR_OK; } @@ -381,12 +447,6 @@ static int jtagspi_probe(struct flash_bank *bank) } info->probed = false; - if (!bank->target->tap) { - LOG_ERROR("Target has no JTAG tap"); - return ERROR_FAIL; - } - info->tap = bank->target->tap; - jtagspi_cmd(bank, SPIFLASH_READ_ID, NULL, 0, in_buf, -3); /* the table in spi.c has the manufacturer byte (first) as the lsb */ id = le_to_h_u24(in_buf); @@ -518,7 +578,7 @@ static int jtagspi_bulk_erase(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - jtagspi_cmd(bank, info->dev.chip_erase_cmd, NULL, 0, NULL, 0); + retval = jtagspi_cmd(bank, info->dev.chip_erase_cmd, NULL, 0, NULL, 0); if (retval != ERROR_OK) return retval; diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c index 6adc4ef73f..85c306bd44 100644 --- a/src/flash/nor/kinetis.c +++ b/src/flash/nor/kinetis.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * @@ -80,6 +80,7 @@ #define FLEXRAM 0x14000000 #define MSCM_OCMDR0 0x40001400 +#define MSCM_OCMDR1 0x40001404 #define FMC_PFB01CR 0x4001f004 #define FTFX_FSTAT 0x40020000 #define FTFX_FCNFG 0x40020001 @@ -97,6 +98,8 @@ #define SMC_PMSTAT 0x4007E003 #define SMC32_PMCTRL 0x4007E00C #define SMC32_PMSTAT 0x4007E014 +#define PMC_REGSC 0x4007D002 +#define MC_PMCTRL 0x4007E003 #define MCM_PLACR 0xF000300C /* Offsets */ @@ -188,6 +191,9 @@ #define KINETIS_K_SDID_K60_M150 0x000001C0 #define KINETIS_K_SDID_K70_M150 0x000001D0 +#define KINETIS_K_REVID_MASK 0x0000F000 +#define KINETIS_K_REVID_SHIFT 12 + #define KINETIS_SDID_SERIESID_MASK 0x00F00000 #define KINETIS_SDID_SERIESID_K 0x00000000 #define KINETIS_SDID_SERIESID_KL 0x00100000 @@ -225,10 +231,32 @@ #define KINETIS_SDID_PROJECTID_KE1XF 0x00000080 #define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100 +/* The S32K series uses a different, incompatible SDID layout : + * Bit 31-28 : GENERATION + * Bit 27-24 : SUBSERIES + * Bit 23-20 : DERIVATE + * Bit 19-16 : RAMSIZE + * Bit 15-12 : REVID + * Bit 11-8 : PACKAGE + * Bit 7-0 : FEATURES + */ + +#define KINETIS_SDID_S32K_SERIES_MASK 0xFF000000 /* GENERATION + SUBSERIES */ +#define KINETIS_SDID_S32K_SERIES_K11X 0x11000000 +#define KINETIS_SDID_S32K_SERIES_K14X 0x14000000 + +#define KINETIS_SDID_S32K_DERIVATE_MASK 0x00F00000 +#define KINETIS_SDID_S32K_DERIVATE_KXX2 0x00200000 +#define KINETIS_SDID_S32K_DERIVATE_KXX3 0x00300000 +#define KINETIS_SDID_S32K_DERIVATE_KXX4 0x00400000 +#define KINETIS_SDID_S32K_DERIVATE_KXX5 0x00500000 +#define KINETIS_SDID_S32K_DERIVATE_KXX6 0x00600000 +#define KINETIS_SDID_S32K_DERIVATE_KXX8 0x00800000 + struct kinetis_flash_bank { struct kinetis_chip *k_chip; bool probed; - unsigned bank_number; /* bank number in particular chip */ + unsigned int bank_number; /* bank number in particular chip */ struct flash_bank *bank; uint32_t sector_size; @@ -257,9 +285,9 @@ struct kinetis_chip { uint32_t fcfg2_maxaddr0_shifted; uint32_t fcfg2_maxaddr1_shifted; - unsigned num_pflash_blocks, num_nvm_blocks; - unsigned pflash_sector_size, nvm_sector_size; - unsigned max_flash_prog_size; + unsigned int num_pflash_blocks, num_nvm_blocks; + unsigned int pflash_sector_size, nvm_sector_size; + unsigned int max_flash_prog_size; uint32_t pflash_base; uint32_t pflash_size; @@ -270,6 +298,11 @@ struct kinetis_chip { uint32_t progr_accel_ram; uint32_t sim_base; + enum { + CT_KINETIS = 0, + CT_S32K, + } chip_type; + enum { FS_PROGRAM_SECTOR = 1, FS_PROGRAM_LONGWORD = 2, @@ -285,6 +318,7 @@ struct kinetis_chip { KINETIS_CACHE_K, /* invalidate using FMC->PFB0CR/PFB01CR */ KINETIS_CACHE_L, /* invalidate using MCM->PLACR */ KINETIS_CACHE_MSCM, /* devices like KE1xF, invalidate MSCM->OCMDR0 */ + KINETIS_CACHE_MSCM2, /* devices like S32K, invalidate MSCM->OCMDR0 and MSCM->OCMDR1 */ } cache_type; enum { @@ -298,11 +332,12 @@ struct kinetis_chip { enum { KINETIS_SMC, KINETIS_SMC32, + KINETIS_MC, } sysmodectrlr_type; char name[40]; - unsigned num_banks; + unsigned int num_banks; struct kinetis_flash_bank banks[KINETIS_MAX_BANKS]; }; @@ -386,10 +421,11 @@ const struct flash_driver kinetis_flash; static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count); static int kinetis_probe_chip(struct kinetis_chip *k_chip); +static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip); static int kinetis_auto_probe(struct flash_bank *bank); -static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value) +static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned int reg, uint32_t value) { LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value); @@ -417,7 +453,7 @@ static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint3 return ERROR_OK; } -static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result) +static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned int reg, uint32_t *result) { struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP); if (!ap) { @@ -443,7 +479,7 @@ static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32 return ERROR_OK; } -static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg, +static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value, uint32_t timeout_ms) { uint32_t val; @@ -871,6 +907,8 @@ static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const cha if (strcmp(argv[i], "-sim-base") == 0) { if (i + 1 < argc) k_chip->sim_base = strtoul(argv[++i], NULL, 0); + } else if (strcmp(argv[i], "-s32k") == 0) { + k_chip->chip_type = CT_S32K; } else LOG_ERROR("Unsupported flash bank option %s", argv[i]); } @@ -892,7 +930,7 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command) k_chip = kinetis_get_chip(target); if (!k_chip) { - k_chip = calloc(sizeof(struct kinetis_chip), 1); + k_chip = calloc(1, sizeof(struct kinetis_chip)); if (!k_chip) { LOG_ERROR("No memory"); return ERROR_FAIL; @@ -939,10 +977,10 @@ static void kinetis_free_driver_priv(struct flash_bank *bank) static int kinetis_create_missing_banks(struct kinetis_chip *k_chip) { - unsigned num_blocks; + unsigned int num_blocks; struct kinetis_flash_bank *k_bank; struct flash_bank *bank; - char base_name[69], name[80], num[4]; + char base_name[69], name[87], num[11]; char *class, *p; num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks; @@ -993,13 +1031,14 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip) bank_idx - k_chip->num_pflash_blocks); } - bank = calloc(sizeof(struct flash_bank), 1); + bank = calloc(1, sizeof(struct flash_bank)); if (!bank) return ERROR_FAIL; bank->target = k_chip->target; bank->driver = &kinetis_flash; bank->default_padded_value = bank->erased_value = 0xff; + bank->minimal_write_gap = FLASH_WRITE_GAP_SECTOR; snprintf(name, sizeof(name), "%s.%s%s", base_name, class, num); @@ -1134,7 +1173,13 @@ static int kinetis_disable_wdog(struct kinetis_chip *k_chip) int retval; if (!k_chip->probed) { - retval = kinetis_probe_chip(k_chip); + switch (k_chip->chip_type) { + case CT_S32K: + retval = kinetis_probe_chip_s32k(k_chip); + break; + default: + retval = kinetis_probe_chip(k_chip); + } if (retval != ERROR_OK) return retval; } @@ -1418,7 +1463,7 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf) uint32_t fprot = 0xffffffff; uint8_t fsec = 0xfe; /* set MCU unsecure */ uint8_t fdprot = 0xff; - unsigned num_blocks; + unsigned int num_blocks; uint32_t pflash_bit; uint8_t dflash_bit; struct flash_bank *bank_iter; @@ -1444,7 +1489,22 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf) kinetis_auto_probe(bank_iter); - assert(bank_iter->prot_blocks); + if (bank_iter->num_prot_blocks == 0) { + if (k_bank->flash_class == FC_PFLASH) { + LOG_ERROR("BUG: PFLASH bank %u has no protection blocks", + bank_idx); + } else { + LOG_DEBUG("skipping FLEX_NVM bank %u with no prot blocks (EE bkp only)", + bank_idx); + } + continue; + } + + if (!bank_iter->prot_blocks) { + LOG_ERROR("BUG: bank %u has NULL protection blocks array", + bank_idx); + continue; + } if (k_bank->flash_class == FC_PFLASH) { for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) { @@ -1537,6 +1597,17 @@ static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat) if (result == ERROR_OK) *pmstat = stat32 & 0xff; return result; + + case KINETIS_MC: + /* emulate SMC by reading PMC_REGSC bit 3 (VLPRS) */ + result = target_read_u8(target, PMC_REGSC, pmstat); + if (result == ERROR_OK) { + if (*pmstat & 0x08) + *pmstat = PM_STAT_VLPR; + else + *pmstat = PM_STAT_RUN; + } + return result; } return ERROR_FAIL; } @@ -1577,6 +1648,10 @@ static int kinetis_check_run_mode(struct kinetis_chip *k_chip) case KINETIS_SMC32: result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN); break; + + case KINETIS_MC: + result = target_write_u32(target, MC_PMCTRL, PM_CTRL_RUNM_RUN); + break; } if (result != ERROR_OK) return result; @@ -1618,6 +1693,12 @@ static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip) /* disable data prefetch and flash speculate */ break; + case KINETIS_CACHE_MSCM2: + target_write_u32(target, MSCM_OCMDR0, 0x30); + target_write_u32(target, MSCM_OCMDR1, 0x30); + /* disable data prefetch and flash speculate */ + break; + default: break; } @@ -2027,6 +2108,174 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer, } +static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip) +{ + int result; + uint8_t fcfg1_eesize, fcfg1_depart; + uint32_t ee_size = 0; + uint32_t pflash_size_k, nvm_size_k, dflash_size_k; + unsigned int generation = 0, subseries = 0, derivate = 0; + + struct target *target = k_chip->target; + k_chip->probed = false; + k_chip->pflash_sector_size = 0; + k_chip->pflash_base = 0; + k_chip->nvm_base = 0x10000000; + k_chip->progr_accel_ram = FLEXRAM; + k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR; + k_chip->watchdog_type = KINETIS_WDOG32_KE1X; + + if (k_chip->sim_base == 0) + k_chip->sim_base = SIM_BASE; + + result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid); + if (result != ERROR_OK) + return result; + + generation = (k_chip->sim_sdid) >> 28 & 0x0f; + subseries = (k_chip->sim_sdid) >> 24 & 0x0f; + derivate = (k_chip->sim_sdid) >> 20 & 0x0f; + + switch (k_chip->sim_sdid & KINETIS_SDID_S32K_SERIES_MASK) { + case KINETIS_SDID_S32K_SERIES_K11X: + k_chip->cache_type = KINETIS_CACHE_L; + k_chip->num_pflash_blocks = 1; + k_chip->num_nvm_blocks = 1; + /* Non-interleaved */ + k_chip->max_flash_prog_size = 512; + + switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) { + case KINETIS_SDID_S32K_DERIVATE_KXX6: + /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 128 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX8: + /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 256 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + } + break; + + case KINETIS_SDID_S32K_SERIES_K14X: + k_chip->cache_type = KINETIS_CACHE_MSCM2; + k_chip->num_pflash_blocks = 1; + k_chip->num_nvm_blocks = 1; + /* Non-interleaved */ + k_chip->max_flash_prog_size = 512; + switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) { + case KINETIS_SDID_S32K_DERIVATE_KXX2: + case KINETIS_SDID_S32K_DERIVATE_KXX3: + /* S32K142/S32K142W CPU 80Mhz Flash 256KB+64KB RAM 32KB+4KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 256 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 64 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX4: + case KINETIS_SDID_S32K_DERIVATE_KXX5: + /* S32K144/S32K144W CPU 80Mhz Flash 512KB+64KB RAM 64KB+4KB */ + /* Interleaved */ + k_chip->pflash_size = 512 << 10; + k_chip->pflash_sector_size = 4 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 64 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX6: + /* S32K146 CPU 80Mhz Flash 1024KB+64KB RAM 128KB+4KB */ + /* Interleaved */ + k_chip->pflash_size = 1024 << 10; + k_chip->pflash_sector_size = 4 << 10; + k_chip->num_pflash_blocks = 2; + /* Non-Interleaved */ + k_chip->nvm_size = 64 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX8: + /* S32K148 CPU 80Mhz Flash 1536KB+512KB RAM 256KB+4KB */ + /* Interleaved */ + k_chip->pflash_size = 1536 << 10; + k_chip->pflash_sector_size = 4 << 10; + k_chip->num_pflash_blocks = 3; + /* Interleaved */ + k_chip->nvm_size = 512 << 10; + k_chip->nvm_sector_size = 4 << 10; + /* Interleaved */ + k_chip->max_flash_prog_size = 1 << 10; + break; + } + break; + + default: + LOG_ERROR("Unsupported S32K1xx-series"); + } + + if (k_chip->pflash_sector_size == 0) { + LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + + result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1); + if (result != ERROR_OK) + return result; + k_chip->sim_fcfg2 = 0; /* S32K1xx does not implement FCFG2 register. */ + + fcfg1_depart = (k_chip->sim_fcfg1 >> 12) & 0x0f; + fcfg1_eesize = (k_chip->sim_fcfg1 >> 16) & 0x0f; + if (fcfg1_eesize <= 9) + ee_size = (16 << (10 - fcfg1_eesize)); + if ((fcfg1_depart & 0x8) == 0) { + /* Binary 0xxx values encode the amount reserved for EEPROM emulation. */ + if (fcfg1_depart) + k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart); + else + k_chip->dflash_size = k_chip->nvm_size; + } else { + /* Binary 1xxx valued encode the DFlash size. */ + if (fcfg1_depart & 0x7) + k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7); + else + k_chip->dflash_size = 0; + } + + snprintf(k_chip->name, sizeof(k_chip->name), "S32K%u%u%u", + generation, subseries, derivate); + + pflash_size_k = k_chip->pflash_size / 1024; + dflash_size_k = k_chip->dflash_size / 1024; + + LOG_INFO("%s detected: %u flash blocks", k_chip->name, k_chip->num_pflash_blocks + k_chip->num_nvm_blocks); + LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k); + + nvm_size_k = k_chip->nvm_size / 1024; + + if (k_chip->num_nvm_blocks) { + LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %" + PRIu32 " bytes FlexRAM", + k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size); + } + + k_chip->probed = true; + + if (create_banks) + kinetis_create_missing_banks(k_chip); + + return ERROR_OK; +} + + static int kinetis_probe_chip(struct kinetis_chip *k_chip) { int result; @@ -2035,12 +2284,12 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip) uint32_t ee_size = 0; uint32_t pflash_size_k, nvm_size_k, dflash_size_k; uint32_t pflash_size_m; - unsigned num_blocks = 0; - unsigned maxaddr_shift = 13; + unsigned int num_blocks = 0; + unsigned int maxaddr_shift = 13; struct target *target = k_chip->target; - unsigned familyid = 0, subfamid = 0; - unsigned cpu_mhz = 120; + unsigned int familyid = 0, subfamid = 0; + unsigned int cpu_mhz = 120; bool use_nvm_marking = false; char flash_marking[12], nvm_marking[2]; char name[40]; @@ -2143,6 +2392,24 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip) } } + /* first revision of some devices has no SMC */ + switch (mcu_type) { + case KINETIS_K_SDID_K10_M100: + case KINETIS_K_SDID_K20_M100: + case KINETIS_K_SDID_K30_M100: + case KINETIS_K_SDID_K40_M100: + case KINETIS_K_SDID_K60_M100: + { + uint32_t revid = (k_chip->sim_sdid & KINETIS_K_REVID_MASK) >> KINETIS_K_REVID_SHIFT; + /* highest bit set corresponds to rev 2.x */ + if (revid <= 7) { + k_chip->sysmodectrlr_type = KINETIS_MC; + strcat(name, " Rev 1.x"); + } + } + break; + } + } else { /* Newer K-series or KL series MCU */ familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT; @@ -2623,12 +2890,12 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip) snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking); LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks); - LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k); + LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k); if (k_chip->num_nvm_blocks) { nvm_size_k = k_chip->nvm_size / 1024; dflash_size_k = k_chip->dflash_size / 1024; - LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM", - k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size); + LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %" + PRIu32 " bytes FlexRAM", k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size); } k_chip->probed = true; @@ -2643,7 +2910,7 @@ static int kinetis_probe(struct flash_bank *bank) { int result; uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1; - unsigned num_blocks, first_nvm_bank; + unsigned int num_blocks, first_nvm_bank; uint32_t size_k; struct kinetis_flash_bank *k_bank = bank->driver_priv; struct kinetis_chip *k_chip; @@ -2654,7 +2921,13 @@ static int kinetis_probe(struct flash_bank *bank) k_bank->probed = false; if (!k_chip->probed) { - result = kinetis_probe_chip(k_chip); + switch (k_chip->chip_type) { + case CT_S32K: + result = kinetis_probe_chip_s32k(k_chip); + break; + default: + result = kinetis_probe_chip(k_chip); + } if (result != ERROR_OK) return result; } @@ -2682,7 +2955,7 @@ static int kinetis_probe(struct flash_bank *bank) } else if (k_bank->bank_number < num_blocks) { /* nvm, banks start at address 0x10000000 */ - unsigned nvm_ord = k_bank->bank_number - first_nvm_bank; + unsigned int nvm_ord = k_bank->bank_number - first_nvm_bank; uint32_t limit; k_bank->flash_class = FC_FLEX_NVM; @@ -2726,23 +2999,26 @@ static int kinetis_probe(struct flash_bank *bank) return ERROR_FLASH_BANK_INVALID; } - fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01); - fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f); - fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f); + /* S32K1xx does not implement FCFG2 register. Skip checks. */ + if (k_chip->chip_type != CT_S32K) { + fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01); + fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f); + fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f); - if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size) - LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed," - " please report to OpenOCD mailing list", fcfg2_maxaddr0); + if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size) + LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed," + " please report to OpenOCD mailing list", fcfg2_maxaddr0); - if (fcfg2_pflsh) { - if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size) - LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed," - " please report to OpenOCD mailing list", fcfg2_maxaddr1); - } else { - if (k_bank->bank_number == first_nvm_bank - && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size) - LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed," - " please report to OpenOCD mailing list", fcfg2_maxaddr1); + if (fcfg2_pflsh) { + if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size) + LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed," + " please report to OpenOCD mailing list", fcfg2_maxaddr1); + } else { + if (k_bank->bank_number == first_nvm_bank + && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size) + LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed," + " please report to OpenOCD mailing list", fcfg2_maxaddr1); + } } free(bank->sectors); @@ -2878,8 +3154,8 @@ static int kinetis_blank_check(struct flash_bank *bank) COMMAND_HANDLER(kinetis_nvm_partition) { int result; - unsigned bank_idx; - unsigned num_blocks, first_nvm_bank; + unsigned int bank_idx; + unsigned int num_blocks, first_nvm_bank; unsigned long par, log2 = 0, ee1 = 0, ee2 = 0; enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO; bool enable; @@ -2893,6 +3169,11 @@ COMMAND_HANDLER(kinetis_nvm_partition) k_chip = kinetis_get_chip(target); + if (k_chip->chip_type == CT_S32K) { + LOG_ERROR("NVM partition not supported on S32K1xx (yet)."); + return ERROR_FAIL; + } + if (CMD_ARGC >= 2) { if (strcmp(CMD_ARGV[0], "dataflash") == 0) sz_type = DF_SIZE; diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c index 14e53f15d9..8207504b5f 100644 --- a/src/flash/nor/kinetis_ke.c +++ b/src/flash/nor/kinetis_ke.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Ivan Meleca * @@ -134,7 +134,7 @@ struct kinetis_ke_flash_bank { #define MDM_ACCESS_TIMEOUT 3000 /* iterations */ -static int kinetis_ke_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value) +static int kinetis_ke_mdm_write_register(struct adiv5_dap *dap, unsigned int reg, uint32_t value) { LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value); @@ -161,7 +161,7 @@ static int kinetis_ke_mdm_write_register(struct adiv5_dap *dap, unsigned reg, ui return ERROR_OK; } -static int kinetis_ke_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result) +static int kinetis_ke_mdm_read_register(struct adiv5_dap *dap, unsigned int reg, uint32_t *result) { struct adiv5_ap *ap = dap_get_ap(dap, 1); if (!ap) { @@ -187,7 +187,7 @@ static int kinetis_ke_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uin return ERROR_OK; } -static int kinetis_ke_mdm_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value) +static int kinetis_ke_mdm_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value) { uint32_t val; int retval; @@ -1005,7 +1005,7 @@ static int kinetis_ke_write(struct flash_bank *bank, const uint8_t *buffer, result = kinetis_ke_stop_watchdog(bank->target); if (result != ERROR_OK) - return result; + return result; result = kinetis_ke_prepare_flash(bank); if (result != ERROR_OK) diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 473df06ef5..09d35f604a 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -272,7 +272,7 @@ #define LPC11XX_REG_SECTORS 24 -typedef enum { +enum lpc2000_variant { LPC2000_V1, LPC2000_V2, LPC1700, @@ -282,10 +282,10 @@ typedef enum { LPC1500, LPC54100, LPC_AUTO, -} lpc2000_variant; +}; struct lpc2000_flash_bank { - lpc2000_variant variant; + enum lpc2000_variant variant; uint32_t cclk; int cmd51_dst_boundary; int calc_checksum; diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c index e1cc38fb3e..3006db1cbf 100644 --- a/src/flash/nor/lpc288x.c +++ b/src/flash/nor/lpc288x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by * diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c index 494fd66c78..948def9829 100644 --- a/src/flash/nor/lpc2900.c +++ b/src/flash/nor/lpc2900.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by * @@ -1132,9 +1132,9 @@ static int lpc2900_write(struct flash_bank *bank, const uint8_t *buffer, * reduced size if that fails. */ struct working_area *warea; uint32_t buffer_size = lpc2900_info->max_ram_block - 1 * KiB; - while ((retval = target_alloc_working_area_try(target, + while (target_alloc_working_area_try(target, buffer_size + target_code_size, - &warea)) != ERROR_OK) { + &warea) != ERROR_OK) { /* Try a smaller buffer now, and stop if it's too small. */ buffer_size -= 1 * KiB; if (buffer_size < 2 * KiB) { diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c index 734730484c..f950f21db7 100644 --- a/src/flash/nor/lpcspifi.c +++ b/src/flash/nor/lpcspifi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2012 by George Harris * diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c index 83eb57e687..267fd43120 100644 --- a/src/flash/nor/max32xxx.c +++ b/src/flash/nor/max32xxx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Maxim Integrated * @@ -87,7 +87,7 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) return ERROR_FLASH_BANK_INVALID; } - info = calloc(sizeof(struct max32xxx_flash_bank), 1); + info = calloc(1, sizeof(struct max32xxx_flash_bank)); COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], info->flash_size); COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], info->flc_base); COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], info->sector_size); @@ -202,14 +202,14 @@ static int max32xxx_protect_check(struct flash_bank *bank) return ERROR_FLASH_BANK_NOT_PROBED; if (!info->max326xx) { - for (unsigned i = 0; i < bank->num_sectors; i++) + for (unsigned int i = 0; i < bank->num_sectors; i++) bank->sectors[i].is_protected = -1; return ERROR_FLASH_OPER_UNSUPPORTED; } /* Check the protection */ - for (unsigned i = 0; i < bank->num_sectors; i++) { + for (unsigned int i = 0; i < bank->num_sectors; i++) { if (i%32 == 0) target_read_u32(target, info->flc_base + FLSH_PROT + ((i/32)*4), &temp_reg); @@ -360,7 +360,7 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; /* power of two, and multiple of word size */ - static const unsigned buf_min = 128; + static const unsigned int buf_min = 128; /* for small buffers it's faster not to download an algorithm */ if (wcount * 4 < buf_min) @@ -388,8 +388,8 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)", - target_name(target), (unsigned) buffer_size); + LOG_DEBUG("retry target_alloc_working_area(%s, size=%" PRIu32 ")", + target_name(target), buffer_size); } target_write_buffer(target, write_algorithm->address, sizeof(write_code), @@ -903,7 +903,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_check_command) } LOG_WARNING("s:<sector number> a:<address> p:<protection bit>"); - for (unsigned i = 0; i < bank->num_sectors; i += 4) { + for (unsigned int i = 0; i < bank->num_sectors; i += 4) { LOG_WARNING("s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d", (i+0), (i+0)*info->sector_size, bank->sectors[(i+0)].is_protected, (i+1), (i+1)*info->sector_size, bank->sectors[(i+1)].is_protected, diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c index c144b14b68..f6285de5b8 100644 --- a/src/flash/nor/mdr.c +++ b/src/flash/nor/mdr.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/flash/nor/mrvlqspi.c b/src/flash/nor/mrvlqspi.c index f896c5a3ba..4eb6522bea 100644 --- a/src/flash/nor/mrvlqspi.c +++ b/src/flash/nor/mrvlqspi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> * diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c index 931c4ff667..b5e2b0bf86 100644 --- a/src/flash/nor/msp432.c +++ b/src/flash/nor/msp432.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Texas Instruments, Inc. * @@ -45,6 +45,21 @@ struct msp432_bank { struct armv7m_algorithm armv7m_info; }; +/* Flash helper algorithm for MSP432P401x targets */ +static const uint8_t msp432p401x_algo[] = { +#include "../../../contrib/loaders/flash/msp432/msp432p401x_algo.inc" +}; + +/* Flash helper algorithm for MSP432P411x targets */ +static const uint8_t msp432p411x_algo[] = { +#include "../../../contrib/loaders/flash/msp432/msp432p411x_algo.inc" +}; + +/* Flash helper algorithm for MSP432E4x targets */ +static const uint8_t msp432e4x_algo[] = { +#include "../../../contrib/loaders/flash/msp432/msp432e4x_algo.inc" +}; + static int msp432_auto_probe(struct flash_bank *bank); static int msp432_device_type(uint32_t family_type, uint32_t device_id, @@ -360,7 +375,7 @@ static int msp432_init(struct flash_bank *bank) buf_set_u32(reg_params[0].value, 0, 32, ALGO_STACK_POINTER_ADDR); /* Begin executing the flash helper algorithm */ - retval = target_start_algorithm(target, 0, 0, 1, reg_params, + retval = target_start_algorithm(target, 0, NULL, 1, reg_params, algo_entry_addr, 0, &msp432_bank->armv7m_info); destroy_reg_param(®_params[0]); if (retval != ERROR_OK) { @@ -922,7 +937,7 @@ static int msp432_probe(struct flash_bank *bank) if (is_main && MSP432P4 == msp432_bank->family_type) { /* Create the info flash bank needed by MSP432P4 variants */ - struct flash_bank *info = calloc(sizeof(struct flash_bank), 1); + struct flash_bank *info = calloc(1, sizeof(struct flash_bank)); if (!info) return ERROR_FAIL; diff --git a/src/flash/nor/msp432.h b/src/flash/nor/msp432.h index 504e7a8ec2..d0a62c4884 100644 --- a/src/flash/nor/msp432.h +++ b/src/flash/nor/msp432.h @@ -101,19 +101,4 @@ struct msp432_algo_params { uint8_t unlock_bsl[4]; }; -/* Flash helper algorithm for MSP432P401x targets */ -const uint8_t msp432p401x_algo[] = { -#include "../../../contrib/loaders/flash/msp432/msp432p401x_algo.inc" -}; - -/* Flash helper algorithm for MSP432P411x targets */ -const uint8_t msp432p411x_algo[] = { -#include "../../../contrib/loaders/flash/msp432/msp432p411x_algo.inc" -}; - -/* Flash helper algorithm for MSP432E4x targets */ -const uint8_t msp432e4x_algo[] = { -#include "../../../contrib/loaders/flash/msp432/msp432e4x_algo.inc" -}; - #endif /* OPENOCD_FLASH_NOR_MSP432_H */ diff --git a/src/flash/nor/mspm0.c b/src/flash/nor/mspm0.c new file mode 100644 index 0000000000..4731c89ccf --- /dev/null +++ b/src/flash/nor/mspm0.c @@ -0,0 +1,1131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * NOR flash driver for MSPM0L and MSPM0G class of uC from Texas Instruments. + * + * See: + * https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "imp.h" +#include <helper/bits.h> +#include <helper/time_support.h> + +/* MSPM0 Region memory map */ +#define MSPM0_FLASH_BASE_NONMAIN 0x41C00000 +#define MSPM0_FLASH_END_NONMAIN 0x41C00400 +#define MSPM0_FLASH_BASE_MAIN 0x0 +#define MSPM0_FLASH_BASE_DATA 0x41D00000 + +/* MSPM0 FACTORYREGION registers */ +#define MSPM0_FACTORYREGION 0x41C40000 +#define MSPM0_TRACEID (MSPM0_FACTORYREGION + 0x000) +#define MSPM0_DID (MSPM0_FACTORYREGION + 0x004) +#define MSPM0_USERID (MSPM0_FACTORYREGION + 0x008) +#define MSPM0_SRAMFLASH (MSPM0_FACTORYREGION + 0x018) + +/* MSPM0 FCTL registers */ +#define FLASH_CONTROL_BASE 0x400CD000 +#define FCTL_REG_DESC (FLASH_CONTROL_BASE + 0x10FC) +#define FCTL_REG_CMDEXEC (FLASH_CONTROL_BASE + 0x1100) +#define FCTL_REG_CMDTYPE (FLASH_CONTROL_BASE + 0x1104) +#define FCTL_REG_CMDADDR (FLASH_CONTROL_BASE + 0x1120) +#define FCTL_REG_CMDBYTEN (FLASH_CONTROL_BASE + 0x1124) +#define FCTL_REG_CMDDATA0 (FLASH_CONTROL_BASE + 0x1130) +#define FCTL_REG_CMDWEPROTA (FLASH_CONTROL_BASE + 0x11D0) +#define FCTL_REG_CMDWEPROTB (FLASH_CONTROL_BASE + 0x11D4) +#define FCTL_REG_CMDWEPROTNM (FLASH_CONTROL_BASE + 0x1210) +#define FCTL_REG_STATCMD (FLASH_CONTROL_BASE + 0x13D0) + +/* FCTL_STATCMD[CMDDONE] Bits */ +#define FCTL_STATCMD_CMDDONE_MASK 0x00000001 +#define FCTL_STATCMD_CMDDONE_STATDONE 0x00000001 + +/* FCTL_STATCMD[CMDPASS] Bits */ +#define FCTL_STATCMD_CMDPASS_MASK 0x00000002 +#define FCTL_STATCMD_CMDPASS_STATPASS 0x00000002 + +/* + * FCTL_CMDEXEC Bits + * FCTL_CMDEXEC[VAL] Bits + */ +#define FCTL_CMDEXEC_VAL_EXECUTE 0x00000001 + +/* FCTL_CMDTYPE[COMMAND] Bits */ +#define FCTL_CMDTYPE_COMMAND_PROGRAM 0x00000001 +#define FCTL_CMDTYPE_COMMAND_ERASE 0x00000002 + +/* FCTL_CMDTYPE[SIZE] Bits */ +#define FCTL_CMDTYPE_SIZE_ONEWORD 0x00000000 +#define FCTL_CMDTYPE_SIZE_SECTOR 0x00000040 + +/* FCTL_FEATURE_VER_B minimum */ +#define FCTL_FEATURE_VER_B 0xA + +#define MSPM0_MAX_PROTREGS 3 + +#define MSPM0_FLASH_TIMEOUT_MS 8000 +#define ERR_STRING_MAX 255 + +/* SYSCTL BASE */ +#define SYSCTL_BASE 0x400AF000 +#define SYSCTL_SECCFG_SECSTATUS (SYSCTL_BASE + 0x00003048) + +/* TI manufacturer ID */ +#define TI_MANUFACTURER_ID 0x17 + +/* Defines for probe status */ +#define MSPM0_NO_ID_FOUND 0 +#define MSPM0_DEV_ID_FOUND 1 +#define MSPM0_DEV_PART_ID_FOUND 2 + +struct mspm0_flash_bank { + /* chip id register */ + uint32_t did; + /* Device Unique ID register */ + uint32_t traceid; + unsigned char version; + + const char *name; + + /* Decoded flash information */ + unsigned int data_flash_size_kb; + unsigned int main_flash_size_kb; + unsigned int main_flash_num_banks; + unsigned int sector_size; + /* Decoded SRAM information */ + unsigned int sram_size_kb; + + /* Flash word size: 64 bit = 8, 128bit = 16 bytes */ + unsigned char flash_word_size_bytes; + + /* Protection register stuff */ + unsigned int protect_reg_base; + unsigned int protect_reg_count; + + /* Flashctl version: A - CMDWEPROTA/B, B- CMDWEPROTB */ + unsigned char flash_version; +}; + +struct mspm0_part_info { + const char *part_name; + unsigned short part; + unsigned char variant; +}; + +struct mspm0_family_info { + const char *family_name; + unsigned short part_num; + unsigned char part_count; + const struct mspm0_part_info *part_info; +}; + +/* https://www.ti.com/lit/ds/symlink/mspm0l1346.pdf Table 8-13 and so on */ +static const struct mspm0_part_info mspm0l_parts[] = { + { "MSPM0L1105TDGS20R", 0x51DB, 0x16 }, + { "MSPM0L1105TDGS28R", 0x51DB, 0x83 }, + { "MSPM0L1105TDYYR", 0x51DB, 0x54 }, + { "MSPM0L1105TRGER", 0x51DB, 0x86 }, + { "MSPM0L1105TRHBR", 0x51DB, 0x68 }, + { "MSPM0L1106TDGS20R", 0x5552, 0x4B }, + { "MSPM0L1106TDGS28R", 0x5552, 0x98 }, + { "MSPM0L1106TDYYR", 0x5552, 0x9D }, + { "MSPM0L1106TRGER", 0x5552, 0x90 }, + { "MSPM0L1106TRHBR", 0x5552, 0x53 }, + { "MSPM0L1303SRGER", 0xef0, 0x17 }, + { "MSPM0L1303TRGER", 0xef0, 0xe2 }, + { "MSPM0L1304QDGS20R", 0xd717, 0x91 }, + { "MSPM0L1304QDGS28R", 0xd717, 0xb6 }, + { "MSPM0L1304QDYYR", 0xd717, 0xa0 }, + { "MSPM0L1304QRHBR", 0xd717, 0xa9 }, + { "MSPM0L1304SDGS20R", 0xd717, 0xfa }, + { "MSPM0L1304SDGS28R", 0xd717, 0x73 }, + { "MSPM0L1304SDYYR", 0xd717, 0xb7 }, + { "MSPM0L1304SRGER", 0xd717, 0x26 }, + { "MSPM0L1304SRHBR", 0xd717, 0xe4 }, + { "MSPM0L1304TDGS20R", 0xd717, 0x33 }, + { "MSPM0L1304TDGS28R", 0xd717, 0xa8 }, + { "MSPM0L1304TDYYR", 0xd717, 0xf9 }, + { "MSPM0L1304TRGER", 0xd717, 0xb7 }, + { "MSPM0L1304TRHBR", 0xd717, 0x5a }, + { "MSPM0L1305QDGS20R", 0x4d03, 0xb7 }, + { "MSPM0L1305QDGS28R", 0x4d03, 0x74 }, + { "MSPM0L1305QDYYR", 0x4d03, 0xec }, + { "MSPM0L1305QRHBR", 0x4d03, 0x78 }, + { "MSPM0L1305SDGS20R", 0x4d03, 0xc7 }, + { "MSPM0L1305SDGS28R", 0x4d03, 0x64 }, + { "MSPM0L1305SDYYR", 0x4d03, 0x91 }, + { "MSPM0L1305SRGER", 0x4d03, 0x73 }, + { "MSPM0L1305SRHBR", 0x4d03, 0x2d }, + { "MSPM0L1305TDGS20R", 0x4d03, 0xa0 }, + { "MSPM0L1305TDGS28R", 0x4d03, 0xfb }, + { "MSPM0L1305TDYYR", 0x4d03, 0xde }, + { "MSPM0L1305TRGER", 0x4d03, 0xea }, + { "MSPM0L1305TRHBR", 0x4d03, 0x85 }, + { "MSPM0L1306QDGS20R", 0xbb70, 0x59 }, + { "MSPM0L1306QDGS28R", 0xbb70, 0xf7 }, + { "MSPM0L1306QDYYR", 0xbb70, 0x9f }, + { "MSPM0L1306QRHBR", 0xbb70, 0xc2 }, + { "MSPM0L1306SDGS20R", 0xbb70, 0xf4 }, + { "MSPM0L1306SDGS28R", 0xbb70, 0x5 }, + { "MSPM0L1306SDYYR", 0xbb70, 0xe }, + { "MSPM0L1306SRGER", 0xbb70, 0x7f }, + { "MSPM0L1306SRHBR", 0xbb70, 0x3c }, + { "MSPM0L1306TDGS20R", 0xbb70, 0xa }, + { "MSPM0L1306TDGS28R", 0xbb70, 0x63 }, + { "MSPM0L1306TDYYR", 0xbb70, 0x35 }, + { "MSPM0L1306TRGER", 0xbb70, 0xaa }, + { "MSPM0L1306TRHBR", 0xbb70, 0x52 }, + { "MSPM0L1343TDGS20R", 0xb231, 0x2e }, + { "MSPM0L1344TDGS20R", 0x40b0, 0xd0 }, + { "MSPM0L1345TDGS28R", 0x98b4, 0x74 }, + { "MSPM0L1346TDGS28R", 0xf2b5, 0xef }, +}; + +/* https://www.ti.com/lit/ds/symlink/mspm0g3506.pdf Table 8-20 */ +static const struct mspm0_part_info mspm0g_parts[] = { + { "MSPM0G1105TPTR", 0x8934, 0xD }, + { "MSPM0G1105TRGZR", 0x8934, 0xFE }, + { "MSPM0G1106TPMR", 0x477B, 0xD4 }, + { "MSPM0G1106TPTR", 0x477B, 0x71 }, + { "MSPM0G1106TRGZR", 0x477B, 0xBB }, + { "MSPM0G1106TRHBR", 0x477B, 0x0 }, + { "MSPM0G1107TDGS28R", 0x807B, 0x82 }, + { "MSPM0G1107TPMR", 0x807B, 0xB3 }, + { "MSPM0G1107TPTR", 0x807B, 0x32 }, + { "MSPM0G1107TRGER", 0x807B, 0x79 }, + { "MSPM0G1107TRGZR", 0x807B, 0x20 }, + { "MSPM0G1107TRHBR", 0x807B, 0xBC }, + { "MSPM0G1505SDGS28R", 0x13C4, 0x73 }, + { "MSPM0G1505SPMR", 0x13C4, 0x53 }, + { "MSPM0G1505SPTR", 0x13C4, 0x3E }, + { "MSPM0G1505SRGER", 0x13C4, 0x47 }, + { "MSPM0G1505SRGZR", 0x13C4, 0x34 }, + { "MSPM0G1505SRHBR", 0x13C4, 0x30 }, + { "MSPM0G1506SDGS28R", 0x5AE0, 0x3A }, + { "MSPM0G1506SPMR", 0x5AE0, 0xF6 }, + { "MSPM0G1506SRGER", 0x5AE0, 0x67 }, + { "MSPM0G1506SRGZR", 0x5AE0, 0x75 }, + { "MSPM0G1506SRHBR", 0x5AE0, 0x57 }, + { "MSPM0G1507SDGS28R", 0x2655, 0x6D }, + { "MSPM0G1507SPMR", 0x2655, 0x97 }, + { "MSPM0G1507SRGER", 0x2655, 0x83 }, + { "MSPM0G1507SRGZR", 0x2655, 0xD3 }, + { "MSPM0G1507SRHBR", 0x2655, 0x4D }, + { "MSPM0G3105SDGS20R", 0x4749, 0x21 }, + { "MSPM0G3105SDGS28R", 0x4749, 0xDD }, + { "MSPM0G3105SRHBR", 0x4749, 0xBE }, + { "MSPM0G3106SDGS20R", 0x54C7, 0xD2 }, + { "MSPM0G3106SDGS28R", 0x54C7, 0xB9 }, + { "MSPM0G3106SRHBR", 0x54C7, 0x67 }, + { "MSPM0G3107SDGS20R", 0xAB39, 0x5C }, + { "MSPM0G3107SDGS28R", 0xAB39, 0xCC }, + { "MSPM0G3107SRHBR", 0xAB39, 0xB7 }, + { "MSPM0G3505SDGS28R", 0xc504, 0x8e }, + { "MSPM0G3505SPMR", 0xc504, 0x1d }, + { "MSPM0G3505SPTR", 0xc504, 0x93 }, + { "MSPM0G3505SRGZR", 0xc504, 0xc7 }, + { "MSPM0G3505SRHBR", 0xc504, 0xe7 }, + { "MSPM0G3505TDGS28R", 0xc504, 0xdf }, + { "MSPM0G3506SDGS28R", 0x151f, 0x8 }, + { "MSPM0G3506SPMR", 0x151f, 0xd4 }, + { "MSPM0G3506SPTR", 0x151f, 0x39 }, + { "MSPM0G3506SRGZR", 0x151f, 0xfe }, + { "MSPM0G3506SRHBR", 0x151f, 0xb5 }, + { "MSPM0G3507SDGS28R", 0xae2d, 0xca }, + { "MSPM0G3507SPMR", 0xae2d, 0xc7 }, + { "MSPM0G3507SPTR", 0xae2d, 0x3f }, + { "MSPM0G3507SRGZR", 0xae2d, 0xf7 }, + { "MSPM0G3507SRHBR", 0xae2d, 0x4c }, + { "M0G3107QPMRQ1", 0x4e2f, 0x51 }, + { "M0G3107QPTRQ1", 0x4e2f, 0xc7}, + { "M0G3107QRGZRQ1", 0x4e2f, 0x8a }, + { "M0G3107QRHBRQ1", 0x4e2f, 0x9a}, + { "M0G3107QDGS28RQ1", 0x4e2f, 0xd5}, + { "M0G3107QDGS28RQ1", 0x4e2f, 0x67}, + { "M0G3107QDGS20RQ1", 0x4e2f, 0xfd}, + { "M0G3106QPMRQ1", 0x54C7, 0x08}, + { "M0G3105QDGS32RQ1", 0x1349, 0x08}, + { "M0G3106QPTRQ1", 0x54C7, 0x3F}, + { "M0G3105QDGS28RQ1", 0x1349, 0x1B}, + { "M0G3106QRGZRQ1", 0x94AD, 0xE6}, + { "M0G3105QDGS20RQ1", 0x1349, 0xFB}, + { "M0G3106QRHBRQ1", 0x94AD, 0x20}, + { "M0G3106QDGS32RQ1", 0x94AD, 0x8D}, + { "M0G3106QDGS28RQ1", 0x94AD, 0x03}, + { "M0G3106QDGS20RQ1", 0x94AD, 0x6F}, + { "M0G3105QPMRQ1", 0x1349, 0xD0}, + { "M0G3105QPTRQ1", 0x1349, 0xEF}, + { "M0G3105QRGZRQ1", 0x1349, 0x70}, + { "M0G3105QRHBRQ1", 0x1349, 0x01}, +}; + +/* https://www.ti.com/lit/gpn/mspm0c1104 Table 8-12 and so on */ +static const struct mspm0_part_info mspm0c_parts[] = { + { "MSPS003F4SPW20R", 0x57b3, 0x70}, + { "MSPM0C1104SDGS20R", 0x57b3, 0x71}, + { "MSPM0C1104SRUKR", 0x57b3, 0x73}, + { "MSPM0C1104SDYYR", 0x57b3, 0x75}, + { "MSPM0C1104SDDFR", 0x57b3, 0x77}, + { "MSPM0C1104SDSGR", 0x57b3, 0x79}, +}; + +/* https://www.ti.com/lit/gpn/MSPM0L2228 Table 8-16 and so on */ +static const struct mspm0_part_info mspm0lx22x_parts[] = { + { "MSPM0L1227SRGER", 0x7C32, 0xF1}, + { "MSPM0L1227SPTR", 0x7C32, 0xC9}, + { "MSPM0L1227SPMR", 0x7C32, 0x1C}, + { "MSPM0L1227SPNAR", 0x7C32, 0x91}, + { "MSPM0L1227SPNR", 0x7C32, 0x39}, + { "MSPM0L1228SRGER", 0x33F7, 0x13}, + { "MSPM0L1228SRHBR", 0x33F7, 0x3A}, + { "MSPM0L1228SRGZR", 0x33F7, 0xBC}, + { "MSPM0L1228SPTR", 0x33F7, 0xF8}, + { "MSPM0L1228SPMR", 0x33F7, 0xCE}, + { "MSPM0L1228SPNAR", 0x33F7, 0x59}, + { "MSPM0L1228SPNR", 0x33F7, 0x7}, + { "MSPM0L2227SRGZR", 0x5E8F, 0x90}, + { "MSPM0L2227SPTR", 0x5E8F, 0xA}, + { "MSPM0L2227SPMR", 0x5E8F, 0x6D}, + { "MSPM0L2227SPNAR", 0x5E8F, 0x24}, + { "MSPM0L2227SPNR", 0x5E8F, 0x68}, + { "MSPM0L2228SRGZR", 0x2C38, 0xB8}, + { "MSPM0L2228SPTR", 0x2C38, 0x25}, + { "MSPM0L2228SPMR", 0x2C38, 0x6E}, + { "MSPM0L2228SPNAR", 0x2C38, 0x63}, + { "MSPM0L2228SPNR", 0x2C38, 0x3C}, +}; + +static const struct mspm0_family_info mspm0_finf[] = { + { "MSPM0L", 0xbb82, ARRAY_SIZE(mspm0l_parts), mspm0l_parts }, + { "MSPM0Lx22x", 0xbb9f, ARRAY_SIZE(mspm0lx22x_parts), mspm0lx22x_parts }, + { "MSPM0G", 0xbb88, ARRAY_SIZE(mspm0g_parts), mspm0g_parts }, + { "MSPM0C", 0xbba1, ARRAY_SIZE(mspm0c_parts), mspm0c_parts }, +}; + +/* + * OpenOCD command interface + */ + +/* + * flash_bank mspm0 <base> <size> 0 0 <target#> + */ +FLASH_BANK_COMMAND_HANDLER(mspm0_flash_bank_command) +{ + struct mspm0_flash_bank *mspm0_info; + + switch (bank->base) { + case MSPM0_FLASH_BASE_NONMAIN: + case MSPM0_FLASH_BASE_MAIN: + case MSPM0_FLASH_BASE_DATA: + break; + default: + LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base); + return ERROR_FAIL; + } + + mspm0_info = calloc(1, sizeof(struct mspm0_flash_bank)); + if (!mspm0_info) { + LOG_ERROR("%s: Out of memory for mspm0_info!", __func__); + return ERROR_FAIL; + } + + bank->driver_priv = mspm0_info; + + mspm0_info->sector_size = 0x400; + + return ERROR_OK; +} + +/* + * Chip identification and status + */ +static int get_mspm0_info(struct flash_bank *bank, struct command_invocation *cmd) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + + if (mspm0_info->did == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + + command_print_sameline(cmd, + "\nTI MSPM0 information: Chip is " + "%s rev %d Device Unique ID: 0x%" PRIu32 "\n", + mspm0_info->name, mspm0_info->version, + mspm0_info->traceid); + command_print_sameline(cmd, + "main flash: %uKiB in %u bank(s), sram: %uKiB, data flash: %uKiB", + mspm0_info->main_flash_size_kb, + mspm0_info->main_flash_num_banks, mspm0_info->sram_size_kb, + mspm0_info->data_flash_size_kb); + + return ERROR_OK; +} + +/* Extract a bitfield helper */ +static unsigned int mspm0_extract_val(unsigned int var, unsigned char hi, unsigned char lo) +{ + return (var & GENMASK(hi, lo)) >> lo; +} + +static int mspm0_read_part_info(struct flash_bank *bank) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + struct target *target = bank->target; + const struct mspm0_family_info *minfo = NULL; + + /* Read and parse chip identification and flash version register */ + uint32_t did; + int retval = target_read_u32(target, MSPM0_DID, &did); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read device ID"); + return retval; + } + retval = target_read_u32(target, MSPM0_TRACEID, &mspm0_info->traceid); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read trace ID"); + return retval; + } + uint32_t userid; + retval = target_read_u32(target, MSPM0_USERID, &userid); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read user ID"); + return retval; + } + uint32_t flashram; + retval = target_read_u32(target, MSPM0_SRAMFLASH, &flashram); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read sramflash register"); + return retval; + } + uint32_t flashdesc; + retval = target_read_u32(target, FCTL_REG_DESC, &flashdesc); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read flashctl description register"); + return retval; + } + + unsigned char version = mspm0_extract_val(did, 31, 28); + unsigned short pnum = mspm0_extract_val(did, 27, 12); + unsigned char variant = mspm0_extract_val(userid, 23, 16); + unsigned short part = mspm0_extract_val(userid, 15, 0); + unsigned short manufacturer = mspm0_extract_val(did, 11, 1); + + /* + * Valid DIE and manufacturer ID? + * Check the ALWAYS_1 bit to be 1 and manufacturer to be 0x17. All MSPM0 + * devices within the Device ID field of the factory constants will + * always read 0x17 as it is TI's JEDEC bank and company code. If 1 + * and 0x17 is not read from their respective registers then it truly + * is not a MSPM0 device so we will return an error instead of + * going any further. + */ + if (!(did & BIT(0)) || !(manufacturer & TI_MANUFACTURER_ID)) { + LOG_WARNING("Unknown Device ID[0x%" PRIx32 "], cannot identify target", + did); + LOG_DEBUG("did 0x%" PRIx32 ", traceid 0x%" PRIx32 ", userid 0x%" PRIx32 + ", flashram 0x%" PRIx32 "", did, mspm0_info->traceid, userid, + flashram); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* Initialize master index selector and probe status*/ + unsigned char minfo_idx = 0xff; + unsigned char probe_status = MSPM0_NO_ID_FOUND; + + /* Check if we at least know the family of devices */ + for (unsigned int i = 0; i < ARRAY_SIZE(mspm0_finf); i++) { + if (mspm0_finf[i].part_num == pnum) { + minfo_idx = i; + minfo = &mspm0_finf[i]; + probe_status = MSPM0_DEV_ID_FOUND; + break; + } + } + + /* Initialize part index selector*/ + unsigned char pinfo_idx = 0xff; + + /* + * If we can identify the part number then we will attempt to identify + * the specific chip. Otherwise, if we do not know the part number then + * it would be useless to identify the specific chip. + */ + if (probe_status == MSPM0_DEV_ID_FOUND) { + /* Can we specifically identify the chip */ + for (unsigned int i = 0; i < minfo->part_count; i++) { + if (minfo->part_info[i].part == part + && minfo->part_info[i].variant == variant) { + pinfo_idx = i; + probe_status = MSPM0_DEV_PART_ID_FOUND; + break; + } + } + } + + /* + * We will check the status of our probe within this switch-case statement + * using these three scenarios. + * + * 1) Device, part, and variant ID is unknown. + * 2) Device ID is known but the part/variant ID is unknown. + * 3) Device ID and part/variant ID is known + * + * For scenario 1, we allow the user to continue because if the + * manufacturer matches TI's JEDEC value and ALWAYS_1 from the device ID + * field is correct then the assumption the user is using an MSPM0 device + * can be made. + */ + switch (probe_status) { + case MSPM0_NO_ID_FOUND: + mspm0_info->name = "mspm0x"; + LOG_INFO("Unidentified PART[0x%x]/variant[0x%x" + "], unknown DeviceID[0x%x" + "]. Attempting to proceed as %s.", part, variant, pnum, + mspm0_info->name); + break; + case MSPM0_DEV_ID_FOUND: + mspm0_info->name = mspm0_finf[minfo_idx].family_name; + LOG_INFO("Unidentified PART[0x%x]/variant[0x%x" + "], known DeviceID[0x%x" + "]. Attempting to proceed as %s.", part, variant, pnum, + mspm0_info->name); + break; + case MSPM0_DEV_PART_ID_FOUND: + default: + mspm0_info->name = mspm0_finf[minfo_idx].part_info[pinfo_idx].part_name; + LOG_DEBUG("Part: %s detected", mspm0_info->name); + break; + } + + mspm0_info->did = did; + mspm0_info->version = version; + mspm0_info->data_flash_size_kb = mspm0_extract_val(flashram, 31, 26); + mspm0_info->main_flash_size_kb = mspm0_extract_val(flashram, 11, 0); + mspm0_info->main_flash_num_banks = mspm0_extract_val(flashram, 13, 12) + 1; + mspm0_info->sram_size_kb = mspm0_extract_val(flashram, 25, 16); + mspm0_info->flash_version = mspm0_extract_val(flashdesc, 15, 12); + + /* + * Hardcode flash_word_size unless we find some other pattern + * See section 7.7 (Foot note mentions the flash word size). + * almost all values seem to be 8 bytes, but if there are variance, + * then we should update mspm0_part_info structure with this info. + */ + mspm0_info->flash_word_size_bytes = 8; + + LOG_DEBUG("Detected: main flash: %uKb in %u banks, sram: %uKb, data flash: %uKb", + mspm0_info->main_flash_size_kb, mspm0_info->main_flash_num_banks, + mspm0_info->sram_size_kb, mspm0_info->data_flash_size_kb); + + return ERROR_OK; +} + +/* + * Decode error values + */ +static const struct { + const unsigned char bit_offset; + const char *fail_string; +} mspm0_fctl_fail_decode_strings[] = { + { 2, "CMDINPROGRESS" }, + { 4, "FAILWEPROT" }, + { 5, "FAILVERIFY" }, + { 6, "FAILILLADDR" }, + { 7, "FAILMODE" }, + { 12, "FAILMISC" }, +}; + +static const char *mspm0_fctl_translate_ret_err(unsigned int return_code) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(mspm0_fctl_fail_decode_strings); i++) { + if (return_code & BIT(mspm0_fctl_fail_decode_strings[i].bit_offset)) + return mspm0_fctl_fail_decode_strings[i].fail_string; + } + + /* If unknown error notify the user*/ + return "FAILUNKNOWN"; +} + +static int mspm0_fctl_get_sector_reg(struct flash_bank *bank, unsigned int addr, + unsigned int *reg, unsigned int *sector_mask) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + struct target *target = bank->target; + int ret = ERROR_OK; + unsigned int sector_num = (addr >> 10); + unsigned int sector_in_bank = sector_num; + unsigned int phys_sector_num = sector_num; + uint32_t sysctl_sec_status; + unsigned int exec_upper_bank; + + /* + * If the device has dual banks we will need to check if it is configured + * to execute from the upper bank. In the scenario that we are executing + * from upper bank then we will need to protect it using CMDWEPROTA rather + * than CMDWEPROTB. We also need to take into account what sector + * we're using when going between banks. + */ + if (mspm0_info->main_flash_num_banks > 1 && + bank->base == MSPM0_FLASH_BASE_MAIN) { + ret = target_read_u32(target, SYSCTL_SECCFG_SECSTATUS, &sysctl_sec_status); + if (ret != ERROR_OK) + return ret; + exec_upper_bank = mspm0_extract_val(sysctl_sec_status, 12, 12); + if (exec_upper_bank) { + if (sector_num > (mspm0_info->main_flash_size_kb / 2)) { + phys_sector_num = + sector_num - (mspm0_info->main_flash_size_kb / 2); + } else { + phys_sector_num = + sector_num + (mspm0_info->main_flash_size_kb / 2); + } + } + sector_in_bank = + sector_num % (mspm0_info->main_flash_size_kb / + mspm0_info->main_flash_num_banks); + } + + /* + * NOTE: MSPM0 devices of version A will use CMDWEPROTA and CMDWEPROTB + * for MAIN flash. CMDWEPROTC is included in the TRM/DATASHEET but for + * all practical purposes, it is considered reserved. If the flash + * version on the device is version B, then we will only use + * CMDWEPROTB for MAIN and DATA flash if the device has it. + */ + switch (bank->base) { + case MSPM0_FLASH_BASE_MAIN: + case MSPM0_FLASH_BASE_DATA: + if (mspm0_info->flash_version < FCTL_FEATURE_VER_B) { + /* Use CMDWEPROTA */ + if (phys_sector_num < 32) { + *sector_mask = BIT(phys_sector_num); + *reg = FCTL_REG_CMDWEPROTA; + } + + /* Use CMDWEPROTB */ + if (phys_sector_num >= 32 && sector_in_bank < 256) { + /* Dual bank system */ + if (mspm0_info->main_flash_num_banks > 1) + *sector_mask = BIT(sector_in_bank / 8); + else /* Single bank system */ + *sector_mask = BIT((sector_in_bank - 32) / 8); + *reg = FCTL_REG_CMDWEPROTB; + } + } else { + *sector_mask = BIT((sector_in_bank / 8) % 32); + *reg = FCTL_REG_CMDWEPROTB; + } + break; + case MSPM0_FLASH_BASE_NONMAIN: + *sector_mask = BIT(sector_num % 32); + *reg = FCTL_REG_CMDWEPROTNM; + break; + default: + /* + * Not expected to reach here due to check in mspm0_address_check() + * but adding it as another layer of safety. + */ + ret = ERROR_FLASH_DST_OUT_OF_BANK; + break; + } + + if (ret != ERROR_OK) + LOG_ERROR("Unable to map sector protect reg for address 0x%08x", addr); + + return ret; +} + +static int mspm0_address_check(struct flash_bank *bank, unsigned int addr) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + unsigned int flash_main_size = mspm0_info->main_flash_size_kb * 1024; + unsigned int flash_data_size = mspm0_info->data_flash_size_kb * 1024; + int ret = ERROR_FLASH_SECTOR_INVALID; + + /* + * Before unprotecting any memory lets make sure that the address and + * bank given is a known bank and whether or not the address falls under + * the proper bank. + */ + switch (bank->base) { + case MSPM0_FLASH_BASE_MAIN: + if (addr <= (MSPM0_FLASH_BASE_MAIN + flash_main_size)) + ret = ERROR_OK; + break; + case MSPM0_FLASH_BASE_NONMAIN: + if (addr >= MSPM0_FLASH_BASE_NONMAIN && addr <= MSPM0_FLASH_END_NONMAIN) + ret = ERROR_OK; + break; + case MSPM0_FLASH_BASE_DATA: + if (addr >= MSPM0_FLASH_BASE_DATA && + addr <= (MSPM0_FLASH_BASE_DATA + flash_data_size)) + ret = ERROR_OK; + break; + default: + ret = ERROR_FLASH_DST_OUT_OF_BANK; + break; + } + + return ret; +} + +static int mspm0_fctl_unprotect_sector(struct flash_bank *bank, unsigned int addr) +{ + struct target *target = bank->target; + unsigned int reg = 0x0; + uint32_t sector_mask = 0x0; + int ret; + + ret = mspm0_address_check(bank, addr); + switch (ret) { + case ERROR_FLASH_SECTOR_INVALID: + LOG_ERROR("Unable to map sector protect reg for address 0x%08x", addr); + break; + case ERROR_FLASH_DST_OUT_OF_BANK: + LOG_ERROR("Unable to determine which bank to use 0x%08x", addr); + break; + default: + mspm0_fctl_get_sector_reg(bank, addr, ®, §or_mask); + ret = target_write_u32(target, reg, ~sector_mask); + break; + } + + return ret; +} + +static int mspm0_fctl_cfg_command(struct flash_bank *bank, + uint32_t addr, + uint32_t cmd, + uint32_t byte_en) +{ + struct target *target = bank->target; + + /* + * Configure the flash operation within the CMDTYPE register, byte_en + * bits if needed, and then set the address where the flash operation + * will execute. + */ + int retval = target_write_u32(target, FCTL_REG_CMDTYPE, cmd); + if (retval != ERROR_OK) + return retval; + if (byte_en != 0) { + retval = target_write_u32(target, FCTL_REG_CMDBYTEN, byte_en); + if (retval != ERROR_OK) + return retval; + } + + return target_write_u32(target, FCTL_REG_CMDADDR, addr); +} + +static int mspm0_fctl_wait_cmd_ok(struct flash_bank *bank) +{ + struct target *target = bank->target; + uint32_t return_code = 0; + int64_t start_ms; + int64_t elapsed_ms; + + start_ms = timeval_ms(); + while ((return_code & FCTL_STATCMD_CMDDONE_MASK) != FCTL_STATCMD_CMDDONE_STATDONE) { + int retval = target_read_u32(target, FCTL_REG_STATCMD, &return_code); + if (retval != ERROR_OK) + return retval; + + elapsed_ms = timeval_ms() - start_ms; + if (elapsed_ms > 500) + keep_alive(); + if (elapsed_ms > MSPM0_FLASH_TIMEOUT_MS) + break; + } + + if ((return_code & FCTL_STATCMD_CMDPASS_MASK) != FCTL_STATCMD_CMDPASS_STATPASS) { + LOG_ERROR("Flash command failed: %s", mspm0_fctl_translate_ret_err(return_code)); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +static int mspm0_fctl_sector_erase(struct flash_bank *bank, uint32_t addr) +{ + struct target *target = bank->target; + + /* + * TRM Says: + * Note that the CMDWEPROTx registers are reset to a protected state + * at the end of all program and erase operations. These registers + * must be re-configured by software before a new operation is + * initiated. + * + * This means that as we start erasing sector by sector, the protection + * registers are reset and need to be unprotected *again* for the next + * erase operation. Unfortunately, this means that we cannot do a unitary + * unprotect operation independent of flash erase operation + */ + int retval = mspm0_fctl_unprotect_sector(bank, addr); + if (retval != ERROR_OK) { + LOG_ERROR("Unprotecting sector of memory at address 0x%08" PRIx32 + " failed", addr); + return retval; + } + + /* Actual erase operation */ + retval = mspm0_fctl_cfg_command(bank, addr, + (FCTL_CMDTYPE_COMMAND_ERASE | FCTL_CMDTYPE_SIZE_SECTOR), 0); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, FCTL_REG_CMDEXEC, FCTL_CMDEXEC_VAL_EXECUTE); + if (retval != ERROR_OK) + return retval; + + return mspm0_fctl_wait_cmd_ok(bank); +} + +static int mspm0_protect_check(struct flash_bank *bank) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + + if (mspm0_info->did == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + + /* + * TRM Says: + * Note that the CMDWEPROTx registers are reset to a protected state + * at the end of all program and erase operations. These registers + * must be re-configured by software before a new operation is + * initiated. + * + * This means that when any flash operation is performed at a block level, + * the block is locked back again. This prevents usage where we can set a + * protection level once at the flash level and then do erase / write + * operation without touching the protection register (since it is + * reset by hardware automatically). In effect, we cannot use the hardware + * defined protection scheme in openOCD. + * + * To deal with this protection scheme, the CMDWEPROTx register that + * correlates to the sector is modified at the time of operation and as far + * openOCD is concerned, the flash operates as completely un-protected + * flash. + */ + for (unsigned int i = 0; i < bank->num_sectors; i++) + bank->sectors[i].is_protected = 0; + + return ERROR_OK; +} + +static int mspm0_erase(struct flash_bank *bank, unsigned int first, unsigned int last) +{ + struct target *target = bank->target; + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + int retval = ERROR_OK; + uint32_t protect_reg_cache[MSPM0_MAX_PROTREGS]; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Please halt target for erasing flash"); + return ERROR_TARGET_NOT_HALTED; + } + + if (mspm0_info->did == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + + /* Pick a copy of the current protection config for later restoration */ + for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) { + retval = target_read_u32(target, + mspm0_info->protect_reg_base + (i * 4), + &protect_reg_cache[i]); + if (retval != ERROR_OK) { + LOG_ERROR("Failed saving flashctl protection status"); + return retval; + } + } + + switch (bank->base) { + case MSPM0_FLASH_BASE_MAIN: + for (unsigned int csa = first; csa <= last; csa++) { + unsigned int addr = csa * mspm0_info->sector_size; + retval = mspm0_fctl_sector_erase(bank, addr); + if (retval != ERROR_OK) + LOG_ERROR("Sector erase on MAIN failed at address 0x%08x " + "(sector: %u)", addr, csa); + } + break; + case MSPM0_FLASH_BASE_NONMAIN: + retval = mspm0_fctl_sector_erase(bank, MSPM0_FLASH_BASE_NONMAIN); + if (retval != ERROR_OK) + LOG_ERROR("Sector erase on NONMAIN failed"); + break; + case MSPM0_FLASH_BASE_DATA: + for (unsigned int csa = first; csa <= last; csa++) { + unsigned int addr = (MSPM0_FLASH_BASE_DATA + + (csa * mspm0_info->sector_size)); + retval = mspm0_fctl_sector_erase(bank, addr); + if (retval != ERROR_OK) + LOG_ERROR("Sector erase on DATA bank failed at address 0x%08x " + "(sector: %u)", addr, csa); + } + break; + default: + LOG_ERROR("Invalid memory region access"); + retval = ERROR_FLASH_BANK_INVALID; + break; + } + + /* If there were any issues in our checks, return the error */ + if (retval != ERROR_OK) + return retval; + + /* + * TRM Says: + * Note that the CMDWEPROTx registers are reset to a protected state + * at the end of all program and erase operations. These registers + * must be re-configured by software before a new operation is + * initiated + * Let us just Dump the protection registers back to the system. + * That way we retain the protection status as requested by the user + */ + for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) { + retval = target_write_u32(target, mspm0_info->protect_reg_base + (i * 4), + protect_reg_cache[i]); + if (retval != ERROR_OK) { + LOG_ERROR("Failed re-applying protection status of flashctl"); + return retval; + } + } + + return retval; +} + +static int mspm0_write(struct flash_bank *bank, const unsigned char *buffer, + unsigned int offset, unsigned int count) +{ + struct target *target = bank->target; + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + uint32_t protect_reg_cache[MSPM0_MAX_PROTREGS]; + int retval; + + /* + * XXX: TRM Says: + * The number of program operations applied to a given word line must be + * monitored to ensure that the maximum word line program limit before + * erase is not violated. + * + * There is no reasonable way we can maintain that state in OpenOCD. So, + * Let the manufacturing path figure this out. + */ + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Please halt target for programming flash"); + return ERROR_TARGET_NOT_HALTED; + } + + if (mspm0_info->did == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + + /* + * Pick a copy of the current protection config for later restoration + * We need to restore these regs after every write, so instead of trying + * to figure things out on the fly, we just context save and restore + */ + for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) { + retval = target_read_u32(target, + mspm0_info->protect_reg_base + (i * 4), + &protect_reg_cache[i]); + if (retval != ERROR_OK) { + LOG_ERROR("Failed saving flashctl protection status"); + return retval; + } + } + + /* Add proper memory offset for bank being written to */ + unsigned int addr = bank->base + offset; + + while (count) { + unsigned int num_bytes_to_write; + uint32_t bytes_en; + + /* + * If count is not 64 bit aligned, we will do byte wise op to keep things simple + * Usually this might mean we need to additional write ops towards + * trailing edge, but that is a tiny penalty for image downloads. + * NOTE: we are going to assume the device does not support multi-word + * programming - there does not seem to be discoverability! + */ + if (count < mspm0_info->flash_word_size_bytes) + num_bytes_to_write = count; + else + num_bytes_to_write = mspm0_info->flash_word_size_bytes; + + /* Data bytes to write */ + bytes_en = (1 << num_bytes_to_write) - 1; + /* ECC chunks to write */ + switch (mspm0_info->flash_word_size_bytes) { + case 8: + bytes_en |= BIT(8); + break; + case 16: + bytes_en |= BIT(16); + bytes_en |= (num_bytes_to_write > 8) ? BIT(17) : 0; + break; + default: + LOG_ERROR("Invalid flash_word_size_bytes %d", + mspm0_info->flash_word_size_bytes); + return ERROR_FAIL; + } + + retval = mspm0_fctl_cfg_command(bank, addr, + (FCTL_CMDTYPE_COMMAND_PROGRAM | FCTL_CMDTYPE_SIZE_ONEWORD), + bytes_en); + if (retval != ERROR_OK) + return retval; + + retval = mspm0_fctl_unprotect_sector(bank, addr); + if (retval != ERROR_OK) + return retval; + + retval = target_write_buffer(target, FCTL_REG_CMDDATA0, num_bytes_to_write, buffer); + if (retval != ERROR_OK) + return retval; + + addr += num_bytes_to_write; + buffer += num_bytes_to_write; + count -= num_bytes_to_write; + + retval = target_write_u32(target, FCTL_REG_CMDEXEC, FCTL_CMDEXEC_VAL_EXECUTE); + if (retval != ERROR_OK) + return retval; + + retval = mspm0_fctl_wait_cmd_ok(bank); + if (retval != ERROR_OK) + return retval; + } + + /* + * TRM Says: + * Note that the CMDWEPROTx registers are reset to a protected state + * at the end of all program and erase operations. These registers + * must be re-configured by software before a new operation is + * initiated + * Let us just Dump the protection registers back to the system. + * That way we retain the protection status as requested by the user + */ + for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) { + retval = target_write_u32(target, + mspm0_info->protect_reg_base + (i * 4), + protect_reg_cache[i]); + if (retval != ERROR_OK) { + LOG_ERROR("Failed re-applying protection status of flashctl"); + return retval; + } + } + + return ERROR_OK; +} + +static int mspm0_probe(struct flash_bank *bank) +{ + struct mspm0_flash_bank *mspm0_info = bank->driver_priv; + + /* + * If this is a mspm0 chip, it has flash; probe() is just + * to figure out how much is present. Only do it once. + */ + if (mspm0_info->did != 0) + return ERROR_OK; + + /* + * mspm0_read_part_info() already handled error checking and + * reporting. Note that it doesn't write, so we don't care about + * whether the target is halted or not. + */ + int retval = mspm0_read_part_info(bank); + if (retval != ERROR_OK) + return retval; + + if (bank->sectors) { + free(bank->sectors); + bank->sectors = NULL; + } + + bank->write_start_alignment = 4; + bank->write_end_alignment = 4; + + switch (bank->base) { + case MSPM0_FLASH_BASE_NONMAIN: + bank->size = 1024; + bank->num_sectors = 0x1; + mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTNM; + mspm0_info->protect_reg_count = 1; + break; + case MSPM0_FLASH_BASE_MAIN: + bank->size = (mspm0_info->main_flash_size_kb * 1024); + bank->num_sectors = bank->size / mspm0_info->sector_size; + /* + * If the feature version bit read from the FCTL_REG_DESC is + * greater than or equal to 0xA then it means that the device + * will exclusively use CMDWEPROTB ONLY for MAIN memory protection + */ + if (mspm0_info->flash_version >= FCTL_FEATURE_VER_B) { + mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTB; + mspm0_info->protect_reg_count = 1; + } else { + mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTA; + mspm0_info->protect_reg_count = 3; + } + break; + case MSPM0_FLASH_BASE_DATA: + if (!mspm0_info->data_flash_size_kb) { + LOG_INFO("Data region NOT available!"); + bank->size = 0x0; + bank->num_sectors = 0x0; + return ERROR_OK; + } + /* + * Any MSPM0 device containing data bank will have a flashctl + * feature version of 0xA or higher. Since data bank is treated + * like MAIN memory, it will also exclusively use CMDWEPROTB for + * protection. + */ + bank->size = (mspm0_info->data_flash_size_kb * 1024); + bank->num_sectors = bank->size / mspm0_info->sector_size; + mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTB; + mspm0_info->protect_reg_count = 1; + break; + default: + LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, + bank->base); + return ERROR_FAIL; + } + + bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector)); + if (!bank->sectors) { + LOG_ERROR("Out of memory for sectors!"); + return ERROR_FAIL; + } + for (unsigned int i = 0; i < bank->num_sectors; i++) { + bank->sectors[i].offset = i * mspm0_info->sector_size; + bank->sectors[i].size = mspm0_info->sector_size; + bank->sectors[i].is_erased = -1; + } + + return ERROR_OK; +} + +const struct flash_driver mspm0_flash = { + .name = "mspm0", + .flash_bank_command = mspm0_flash_bank_command, + .erase = mspm0_erase, + .protect = NULL, + .write = mspm0_write, + .read = default_flash_read, + .probe = mspm0_probe, + .auto_probe = mspm0_probe, + .erase_check = default_flash_blank_check, + .protect_check = mspm0_protect_check, + .info = get_mspm0_info, + .free_driver_priv = default_flash_free_driver_priv, +}; diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c index 00a4a17640..aaf0726550 100644 --- a/src/flash/nor/niietcm4.c +++ b/src/flash/nor/niietcm4.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Bogdan Kolbov * @@ -311,7 +311,7 @@ static int niietcm4_uflash_page_erase(struct flash_bank *bank, int page_num, int /* status check */ retval = niietcm4_uopstatus_check(bank); if (retval != ERROR_OK) - return retval; + return retval; return retval; } @@ -394,7 +394,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command) uint32_t uflash_data; if (strcmp("info", CMD_ARGV[0]) == 0) - uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB; + uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB; else if (strcmp("main", CMD_ARGV[0]) == 0) uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ; else @@ -539,7 +539,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_erase_command) int mem_type; if (strcmp("info", CMD_ARGV[0]) == 0) - mem_type = 1; + mem_type = 1; else if (strcmp("main", CMD_ARGV[0]) == 0) mem_type = 0; else diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c index 5c05fb3b7e..f096ba69c3 100644 --- a/src/flash/nor/non_cfi.c +++ b/src/flash/nor/non_cfi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * diff --git a/src/flash/nor/npcx.c b/src/flash/nor/npcx.c index a4d639524b..8309630d7c 100644 --- a/src/flash/nor/npcx.c +++ b/src/flash/nor/npcx.c @@ -1,9 +1,10 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2020 by Nuvoton Technology Corporation * Mulin Chao <mlchao@nuvoton.com> * Wealian Liao <WHLIAO@nuvoton.com> + * Luca Hung <YCHUNG0@nuvoton.com> */ #ifdef HAVE_CONFIG_H @@ -17,12 +18,11 @@ #include "../../../contrib/loaders/flash/npcx/npcx_flash.h" /* NPCX flash loader */ -const uint8_t npcx_algo[] = { +static const uint8_t npcx_algo[] = { #include "../../../contrib/loaders/flash/npcx/npcx_algo.inc" }; #define NPCX_FLASH_TIMEOUT_MS 8000 -#define NPCX_FLASH_BASE_ADDR 0x64000000 /* flash list */ enum npcx_flash_device_index { @@ -33,7 +33,6 @@ enum npcx_flash_device_index { }; struct npcx_flash_bank { - const char *family_name; uint32_t sector_length; bool probed; enum npcx_flash_device_index flash; @@ -44,6 +43,7 @@ struct npcx_flash_bank { uint32_t algo_working_size; uint32_t buffer_addr; uint32_t params_addr; + uint32_t fiu_ver; }; struct npcx_flash_info { @@ -90,7 +90,7 @@ static int npcx_init(struct flash_bank *bank) /* Confirm the defined working address is the area we need to use */ if (npcx_bank->working_area->address != NPCX_FLASH_LOADER_WORKING_ADDR) { - LOG_ERROR("%s: Invalid working address", npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Invalid working address"); LOG_INFO("Hint: Use '-work-area-phys 0x%" PRIx32 "' in your target configuration", NPCX_FLASH_LOADER_WORKING_ADDR); target_free_working_area(target, npcx_bank->working_area); @@ -102,8 +102,7 @@ static int npcx_init(struct flash_bank *bank) retval = target_write_buffer(target, NPCX_FLASH_LOADER_PROGRAM_ADDR, npcx_bank->algo_size, npcx_bank->algo_code); if (retval != ERROR_OK) { - LOG_ERROR("%s: Failed to load flash helper algorithm", - npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Failed to load flash helper algorithm"); target_free_working_area(target, npcx_bank->working_area); npcx_bank->working_area = NULL; return retval; @@ -118,8 +117,7 @@ static int npcx_init(struct flash_bank *bank) NPCX_FLASH_LOADER_PROGRAM_ADDR, 0, &npcx_bank->armv7m_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: Failed to start flash helper algorithm", - npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Failed to start flash helper algorithm"); target_free_working_area(target, npcx_bank->working_area); npcx_bank->working_area = NULL; return retval; @@ -154,7 +152,6 @@ static int npcx_quit(struct flash_bank *bank) static int npcx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) { struct target *target = bank->target; - struct npcx_flash_bank *npcx_bank = bank->driver_priv; uint32_t status_addr = params_addr + offsetof(struct npcx_flash_params, sync); uint32_t status; int64_t start_ms = timeval_ms(); @@ -172,9 +169,7 @@ static int npcx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) } while (status == NPCX_FLASH_LOADER_EXECUTE); if (status != NPCX_FLASH_LOADER_WAIT) { - LOG_ERROR("%s: Flash operation failed, status=0x%" PRIx32, - npcx_bank->family_name, - status); + LOG_TARGET_ERROR(target, "Flash operation failed, status (%0x" PRIX32 ") ", status); return ERROR_FAIL; } @@ -197,6 +192,7 @@ static enum npcx_flash_device_index npcx_get_flash_id(struct flash_bank *bank, u return retval; /* Set up algorithm parameters for get flash ID command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_GET_FLASH_ID); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -250,6 +246,7 @@ static int npcx_probe(struct flash_bank *bank) npcx_bank->buffer_addr = NPCX_FLASH_LOADER_BUFFER_ADDR; npcx_bank->params_addr = NPCX_FLASH_LOADER_PARAMS_ADDR; + int retval = npcx_get_flash_id(bank, &flash_id); if (retval != ERROR_OK) return retval; @@ -264,7 +261,6 @@ static int npcx_probe(struct flash_bank *bank) return ERROR_FAIL; } - bank->base = NPCX_FLASH_BASE_ADDR; bank->num_sectors = num_sectors; bank->size = num_sectors * sector_length; bank->write_start_alignment = 0; @@ -300,7 +296,7 @@ FLASH_BANK_COMMAND_HANDLER(npcx_flash_bank_command) { struct npcx_flash_bank *npcx_bank; - if (CMD_ARGC < 6) + if (CMD_ARGC < 6 || CMD_ARGC > 7) return ERROR_COMMAND_SYNTAX_ERROR; npcx_bank = calloc(1, sizeof(struct npcx_flash_bank)); @@ -309,13 +305,32 @@ FLASH_BANK_COMMAND_HANDLER(npcx_flash_bank_command) return ERROR_FAIL; } + const char *fiu; + if (CMD_ARGC == 6) { + LOG_WARNING("No FIU is selection, using default."); + npcx_bank->fiu_ver = NPCX_FIU_NPCX; + } + + if (CMD_ARGC == 7) { + fiu = CMD_ARGV[6]; + if (strcmp(fiu, "npcx.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCX; + } else if (strcmp(fiu, "npcx_v2.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCX_V2; + } else if (strcmp(fiu, "npck.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCK; + } else { + LOG_ERROR("%s is not a valid fiu", fiu); + free(npcx_bank); + return ERROR_TARGET_INVALID; + } + } + /* Initialize private flash information */ - npcx_bank->family_name = "npcx"; npcx_bank->sector_length = NPCX_FLASH_ERASE_SIZE; /* Finish initialization of bank */ bank->driver_priv = npcx_bank; - bank->next = NULL; return ERROR_OK; } @@ -341,6 +356,7 @@ static int npcx_chip_erase(struct flash_bank *bank) return retval; /* Set up algorithm parameters for chip erase command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_ALL); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -397,6 +413,7 @@ static int npcx_erase(struct flash_bank *bank, unsigned int first, return retval; /* Set up algorithm parameters for erase command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address); target_buffer_set_u32(target, (uint8_t *)&algo_params.len, length); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_SECTORS); @@ -464,6 +481,7 @@ static int npcx_write(struct flash_bank *bank, const uint8_t *buffer, } /* Update algo parameters for flash write */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address); target_buffer_set_u32(target, (uint8_t *)&algo_params.len, size); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -502,7 +520,7 @@ static int npcx_info(struct flash_bank *bank, struct command_invocation *cmd) struct npcx_flash_bank *npcx_bank = bank->driver_priv; command_print_sameline(cmd, "%s flash: %s\n", - npcx_bank->family_name, + target_name(bank->target), flash_info[npcx_bank->flash].name); return ERROR_OK; diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c index 23b221cb33..5cb552aa94 100644 --- a/src/flash/nor/nrf5.c +++ b/src/flash/nor/nrf5.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 Synapse Product Development * @@ -17,9 +17,9 @@ #include <target/armv7m.h> #include <helper/types.h> #include <helper/time_support.h> +#include <helper/bits.h> -/* Both those values are constant across the current spectrum ofr nRF5 devices */ -#define WATCHDOG_REFRESH_REGISTER 0x40010600 +/* The refresh code is constant across the current spectrum of nRF5 devices */ #define WATCHDOG_REFRESH_VALUE 0x6e524635 enum { @@ -27,12 +27,9 @@ enum { }; enum nrf5_ficr_registers { - NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */ + NRF51_52_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */ -#define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset) - - NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010), - NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014), +#define NRF5_FICR_REG(offset) (NRF51_52_FICR_BASE + (offset)) NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028), NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C), @@ -41,65 +38,23 @@ enum nrf5_ficr_registers { NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C), NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040), NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044), - - NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C), - NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060), - NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064), - NRF5_FICR_ER0 = NRF5_FICR_REG(0x080), - NRF5_FICR_ER1 = NRF5_FICR_REG(0x084), - NRF5_FICR_ER2 = NRF5_FICR_REG(0x088), - NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C), - NRF5_FICR_IR0 = NRF5_FICR_REG(0x090), - NRF5_FICR_IR1 = NRF5_FICR_REG(0x094), - NRF5_FICR_IR2 = NRF5_FICR_REG(0x098), - NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C), - NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0), - NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4), - NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8), - - NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC), - NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0), - NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4), - NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8), - NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC), - NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0), - NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC), - NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0), - NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4), - NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8), - NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC), - - /* Following registers are available on nRF52 and on nRF51 since rev 3 */ - NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100), - NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104), - NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108), - NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C), - NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110), }; enum nrf5_uicr_registers { - NRF5_UICR_BASE = 0x10001000, /* User Information + NRF51_52_UICR_BASE = 0x10001000, /* User Information * Configuration Registers */ -#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset) +#define NRF5_UICR_REG(offset) (NRF51_52_UICR_BASE + (offset)) NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000), - NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004), - NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008), - NRF51_UICR_FWID = NRF5_UICR_REG(0x010), }; enum nrf5_nvmc_registers { - NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory - * Controller Registers */ - -#define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset) - - NRF5_NVMC_READY = NRF5_NVMC_REG(0x400), - NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504), - NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508), - NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C), - NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514), + NRF5_NVMC_READY = 0x400, + NRF5_NVMC_CONFIG = 0x504, + NRF5_NVMC_ERASEPAGE = 0x508, + NRF5_NVMC_ERASEALL = 0x50C, + NRF5_NVMC_ERASEUICR = 0x514, NRF5_BPROT_BASE = 0x40000000, }; @@ -120,10 +75,13 @@ struct nrf52_ficr_info { }; enum nrf5_features { - NRF5_FEATURE_SERIES_51 = 1 << 0, - NRF5_FEATURE_SERIES_52 = 1 << 1, - NRF5_FEATURE_BPROT = 1 << 2, - NRF5_FEATURE_ACL_PROT = 1 << 3, + NRF5_FEATURE_SERIES_51 = BIT(0), + NRF5_FEATURE_SERIES_52 = BIT(1), + NRF5_FEATURE_BPROT = BIT(2), + NRF5_FEATURE_ACL_PROT = BIT(3), + NRF5_FEATURE_SERIES_53 = BIT(4), + NRF5_FEATURE_SERIES_91 = BIT(5), + NRF5_FEATURE_ERASE_BY_FLASH_WR = BIT(6), }; struct nrf5_device_spec { @@ -135,23 +93,52 @@ struct nrf5_device_spec { enum nrf5_features features; }; +/* FICR registers offsets */ +struct nrf5_ficr_map { + uint32_t codepagesize; + uint32_t codesize; + uint32_t configid; + uint32_t info_part; + uint32_t info_variant; + uint32_t info_package; + uint32_t info_ram; + uint32_t info_flash; +}; + +/* Map of device */ +struct nrf5_map { + uint32_t flash_base; + uint32_t ficr_base; + uint32_t uicr_base; + uint32_t nvmc_base; + + uint32_t watchdog_refresh_addr; +}; + struct nrf5_info { - uint32_t refcount; + unsigned int refcount; + bool chip_probed; struct nrf5_bank { struct nrf5_info *chip; bool probed; } bank[2]; + struct target *target; - /* chip identification stored in nrf5_probe() for use in nrf5_info() */ + /* chip identification stored in nrf5_probe_chip() + * for use in nrf5_info() and nrf5_setup_bank() */ bool ficr_info_valid; struct nrf52_ficr_info ficr_info; const struct nrf5_device_spec *spec; uint16_t hwid; enum nrf5_features features; - unsigned int flash_size_kb; + uint32_t flash_page_size; + uint32_t flash_num_sectors; unsigned int ram_size_kb; + + const struct nrf5_map *map; + const struct nrf5_ficr_map *ficr_offsets; }; #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \ @@ -164,26 +151,20 @@ struct nrf5_info { .features = NRF5_FEATURE_SERIES_51, \ } -#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \ -{ \ -.hwid = (id), \ -.part = pt, \ -.variant = var, \ -.build_code = bcode, \ -.flash_size_kb = (fsize), \ -.features = features, \ -} - -/* The known devices table below is derived from the "nRF5x series - * compatibility matrix" documents, which can be found in the "DocLib" of - * nordic: +/* + * The table maps known HWIDs to the part numbers, variant + * build code and some other info. For nRF51 rev 1 and 2 devices + * this is the only way how to get the part number and variant. + * + * All tested nRF51 rev 3 devices have FICR INFO fields + * but the fields are not documented in RM so we keep HWIDs in + * this table. + * + * nRF52 and newer devices have FICR INFO documented, the autodetection + * can rely on it and HWIDs table is not used. * - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview - * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview + * The known devices table below is derived from the "nRF5x series + * compatibility matrix" documents. * * Up to date with Matrix v2.0, plus some additional HWIDs. * @@ -248,19 +229,6 @@ static const struct nrf5_device_spec nrf5_known_devices_table[] = { /* The driver fully autodetects nRF52 series devices by FICR INFO, * no need for nRF52xxx HWIDs in this table */ -#if 0 - /* nRF52810 Devices */ - NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT), - NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT), - - /* nRF52832 Devices */ - NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT), - NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT), - NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT), - - /* nRF52840 Devices */ - NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT), -#endif }; struct nrf5_device_package { @@ -270,39 +238,137 @@ struct nrf5_device_package { /* Newer devices have FICR INFO.PACKAGE. * This table converts its value to two character code */ -static const struct nrf5_device_package nrf5_packages_table[] = { +static const struct nrf5_device_package nrf52_packages_table[] = { { 0x2000, "QF" }, { 0x2001, "CH" }, { 0x2002, "CI" }, + { 0x2003, "QC" }, + { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */ { 0x2005, "CK" }, + { 0x2007, "QD" }, + { 0x2008, "CJ" }, + { 0x2009, "CF" }, +}; + +static const struct nrf5_ficr_map nrf51_52_ficr_offsets = { + .codepagesize = 0x10, + .codesize = 0x14, + + /* CONFIGID is documented on nRF51 series only. + * On nRF52 is present but not documented */ + .configid = 0x5c, + + /* Following registers are available on nRF52 and on nRF51 since rev 3 */ + .info_part = 0x100, + .info_variant = 0x104, + .info_package = 0x108, + .info_ram = 0x10c, + .info_flash = 0x110, +}; + +static const struct nrf5_map nrf51_52_map = { + .flash_base = NRF5_FLASH_BASE, + .ficr_base = NRF51_52_FICR_BASE, + .uicr_base = NRF51_52_UICR_BASE, + .nvmc_base = 0x4001E000, + + .watchdog_refresh_addr = 0x40010600, +}; + + +/* Third generation devices (nRF53, nRF91) */ + +static const struct nrf5_ficr_map nrf53_91_ficr_offsets = { + .codepagesize = 0x220, + .codesize = 0x224, + .configid = 0x200, + .info_part = 0x20c, + .info_variant = 0x210, + .info_package = 0x214, + .info_ram = 0x218, + .info_flash = 0x21c, }; +/* Since nRF9160 Product Specification v2.1 there is + * a new UICR field SIPINFO, which should be preferred. + * The original INFO fields describe just a part of the chip + * (PARTNO=9120 at nRF9161) + */ +static const struct nrf5_ficr_map nrf91new_ficr_offsets = { + .codepagesize = 0x220, + .codesize = 0x224, + .configid = 0x200, + .info_part = 0x140, /* SIPINFO.PARTNO */ + .info_variant = 0x148, /* SIPINFO.VARIANT */ + .info_package = 0x214, + .info_ram = 0x218, + .info_flash = 0x21c, +}; + +enum { + NRF53APP_91_FICR_BASE = 0x00FF0000, + NRF53APP_91_UICR_BASE = 0x00FF8000, + NRF53NET_FLASH_BASE = 0x01000000, + NRF53NET_FICR_BASE = 0x01FF0000, + NRF53NET_UICR_BASE = 0x01FF8000, +}; + +static const struct nrf5_map nrf53app_91_map = { + .flash_base = NRF5_FLASH_BASE, + .ficr_base = NRF53APP_91_FICR_BASE, + .uicr_base = NRF53APP_91_UICR_BASE, + .nvmc_base = 0x50039000, + + .watchdog_refresh_addr = 0x50018600, +}; + +/* nRF53 duality: + * SoC consists of two Cortex-M33 cores: + * - application core with security extensions + * - network core + * Each core has its own RAM, flash, FICR and UICR + * The flash driver probes and handles flash and UICR of one core + * independently of those dedicated to the other core. + */ +static const struct nrf5_map nrf53net_map = { + .flash_base = NRF53NET_FLASH_BASE, + .ficr_base = NRF53NET_FICR_BASE, + .uicr_base = NRF53NET_UICR_BASE, + .nvmc_base = 0x41080000, + + .watchdog_refresh_addr = 0x41080000, +}; + + const struct flash_driver nrf5_flash, nrf51_flash; static bool nrf5_bank_is_probed(const struct flash_bank *bank) { struct nrf5_bank *nbank = bank->driver_priv; - - assert(nbank); - return nbank->probed; } -static int nrf5_probe(struct flash_bank *bank); -static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip) +static bool nrf5_chip_is_probed(const struct flash_bank *bank) { - if (bank->target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - struct nrf5_bank *nbank = bank->driver_priv; - *chip = nbank->chip; + struct nrf5_info *chip = nbank->chip; + return chip->chip_probed; +} - if (nrf5_bank_is_probed(bank)) - return ERROR_OK; +static bool nrf5_bank_is_uicr(const struct nrf5_bank *nbank) +{ + struct nrf5_info *chip = nbank->chip; + return nbank == &chip->bank[1]; +} + +static int nrf5_nvmc_read_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t *value) +{ + return target_read_u32(chip->target, chip->map->nvmc_base + reg_offset, value); +} - return nrf5_probe(bank); +static int nrf5_nvmc_write_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t value) +{ + return target_write_u32(chip->target, chip->map->nvmc_base + reg_offset, value); } static int nrf5_wait_for_nvmc(struct nrf5_info *chip) @@ -313,7 +379,13 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip) int64_t ts_start = timeval_ms(); do { - res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready); + res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready); + if (res == ERROR_WAIT) { + /* The adapter does not handle SWD WAIT properly, + * add some delay to reduce number of error messages */ + alive_sleep(10); + continue; + } if (res != ERROR_OK) { LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)"); return res; @@ -333,7 +405,7 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip) static int nrf5_nvmc_erase_enable(struct nrf5_info *chip) { int res; - res = target_write_u32(chip->target, + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_CONFIG, NRF5_NVMC_CONFIG_EEN); @@ -356,7 +428,7 @@ static int nrf5_nvmc_erase_enable(struct nrf5_info *chip) static int nrf5_nvmc_write_enable(struct nrf5_info *chip) { int res; - res = target_write_u32(chip->target, + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_CONFIG, NRF5_NVMC_CONFIG_WEN); @@ -379,12 +451,12 @@ static int nrf5_nvmc_write_enable(struct nrf5_info *chip) static int nrf5_nvmc_read_only(struct nrf5_info *chip) { int res; - res = target_write_u32(chip->target, + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_CONFIG, NRF5_NVMC_CONFIG_REN); if (res != ERROR_OK) { - LOG_ERROR("Failed to enable read-only operation"); + LOG_ERROR("Failed to disable write/erase operation"); return res; } /* @@ -398,44 +470,15 @@ static int nrf5_nvmc_read_only(struct nrf5_info *chip) return res; } -static int nrf5_nvmc_generic_erase(struct nrf5_info *chip, - uint32_t erase_register, uint32_t erase_value) -{ - int res; - - res = nrf5_nvmc_erase_enable(chip); - if (res != ERROR_OK) - goto error; - - res = target_write_u32(chip->target, - erase_register, - erase_value); - if (res != ERROR_OK) - goto set_read_only; - - res = nrf5_wait_for_nvmc(chip); - if (res != ERROR_OK) - goto set_read_only; - - return nrf5_nvmc_read_only(chip); - -set_read_only: - nrf5_nvmc_read_only(chip); -error: - LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32, - erase_register, erase_value); - return ERROR_FAIL; -} - -static int nrf5_protect_check_clenr0(struct flash_bank *bank) +/* nRF51 series only */ +static int nrf51_protect_check_clenr0(struct flash_bank *bank) { int res; uint32_t clenr0; + struct nrf5_bank *nbank = bank->driver_priv; struct nrf5_info *chip = nbank->chip; - assert(chip); - res = target_read_u32(chip->target, NRF51_FICR_CLENR0, &clenr0); if (res != ERROR_OK) { @@ -459,13 +502,12 @@ static int nrf5_protect_check_clenr0(struct flash_bank *bank) return ERROR_OK; } -static int nrf5_protect_check_bprot(struct flash_bank *bank) +/* nRF52 series only */ +static int nrf52_protect_check_bprot(struct flash_bank *bank) { struct nrf5_bank *nbank = bank->driver_priv; struct nrf5_info *chip = nbank->chip; - assert(chip); - static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 }; uint32_t bprot_reg = 0; int res; @@ -488,30 +530,30 @@ static int nrf5_protect_check_bprot(struct flash_bank *bank) static int nrf5_protect_check(struct flash_bank *bank) { - /* UICR cannot be write protected so just return early */ - if (bank->base == NRF5_UICR_BASE) - return ERROR_OK; - struct nrf5_bank *nbank = bank->driver_priv; struct nrf5_info *chip = nbank->chip; - assert(chip); + /* UICR cannot be write protected so just return early */ + if (nrf5_bank_is_uicr(nbank)) + return ERROR_OK; if (chip->features & NRF5_FEATURE_BPROT) - return nrf5_protect_check_bprot(bank); + return nrf52_protect_check_bprot(bank); if (chip->features & NRF5_FEATURE_SERIES_51) - return nrf5_protect_check_clenr0(bank); + return nrf51_protect_check_clenr0(bank); LOG_WARNING("Flash protection of this nRF device is not supported"); return ERROR_FLASH_OPER_UNSUPPORTED; } -static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first, +/* nRF51 series only */ +static int nrf51_protect_clenr0(struct flash_bank *bank, int set, unsigned int first, unsigned int last) { int res; uint32_t clenr0, ppfc; + struct nrf5_bank *nbank = bank->driver_priv; struct nrf5_info *chip = nbank->chip; @@ -570,32 +612,38 @@ static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int fi static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last) { - int res; - struct nrf5_info *chip; + struct nrf5_bank *nbank = bank->driver_priv; + struct nrf5_info *chip = nbank->chip; /* UICR cannot be write protected so just bail out early */ - if (bank->base == NRF5_UICR_BASE) { + if (nrf5_bank_is_uicr(nbank)) { LOG_ERROR("UICR page does not support protection"); return ERROR_FLASH_OPER_UNSUPPORTED; } - res = nrf5_get_probed_chip_if_halted(bank, &chip); - if (res != ERROR_OK) - return res; + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } if (chip->features & NRF5_FEATURE_SERIES_51) - return nrf5_protect_clenr0(bank, set, first, last); + return nrf51_protect_clenr0(bank, set, first, last); LOG_ERROR("Flash protection setting is not supported on this nRF5 device"); return ERROR_FLASH_OPER_UNSUPPORTED; } -static bool nrf5_info_variant_to_str(uint32_t variant, char *bf) +static bool nrf5_info_variant_to_str(uint32_t variant, char *bf, bool swap) { uint8_t b[4]; - h_u32_to_be(b, variant); - if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) { + if (swap) + h_u32_to_le(b, variant); + else + h_u32_to_be(b, variant); + + if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && + (isalnum(b[3]) || b[3] == 0)) { memcpy(bf, b, 4); bf[4] = 0; return true; @@ -607,14 +655,14 @@ static bool nrf5_info_variant_to_str(uint32_t variant, char *bf) static const char *nrf5_decode_info_package(uint32_t package) { - for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) { - if (nrf5_packages_table[i].package == package) - return nrf5_packages_table[i].code; + for (size_t i = 0; i < ARRAY_SIZE(nrf52_packages_table); i++) { + if (nrf52_packages_table[i].package == package) + return nrf52_packages_table[i].code; } return "xx"; } -static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size) +static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size) { int res; if (chip->spec) { @@ -622,11 +670,19 @@ static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsig chip->spec->part, chip->spec->variant, chip->spec->build_code); } else if (chip->ficr_info_valid) { char variant[5]; - nrf5_info_variant_to_str(chip->ficr_info.variant, variant); - res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)", - chip->ficr_info.part, - nrf5_decode_info_package(chip->ficr_info.package), - variant, &variant[2]); + + nrf5_info_variant_to_str(chip->ficr_info.variant, variant, + chip->features & NRF5_FEATURE_SERIES_91); + + if (chip->features & (NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_SERIES_91)) { + res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s", + chip->ficr_info.part, variant); + } else { + res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)", + chip->ficr_info.part, + nrf5_decode_info_package(chip->ficr_info.package), + variant, &variant[2]); + } } else { res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid); } @@ -645,81 +701,107 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd) struct nrf5_info *chip = nbank->chip; char chip_type_str[256]; - if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK) + if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK) return ERROR_FAIL; + unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024; command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM", - chip_type_str, chip->flash_size_kb, chip->ram_size_kb); + chip_type_str, flash_size_kb, chip->ram_size_kb); return ERROR_OK; } -static int nrf5_read_ficr_info(struct nrf5_info *chip) +static int nrf5_read_ficr_info_part(struct nrf5_info *chip, const struct nrf5_map *map, + const struct nrf5_ficr_map *ficr_offsets) { - int res; struct target *target = chip->target; + uint32_t ficr_base = map->ficr_base; - chip->ficr_info_valid = false; - - res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part); - if (res != ERROR_OK) { + int res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part); + if (res != ERROR_OK) LOG_DEBUG("Couldn't read FICR INFO.PART register"); - return res; - } + + return res; +} + +static int nrf51_52_partno_check(struct nrf5_info *chip) +{ uint32_t series = chip->ficr_info.part & 0xfffff000; switch (series) { case 0x51000: chip->features = NRF5_FEATURE_SERIES_51; - break; + return ERROR_OK; case 0x52000: chip->features = NRF5_FEATURE_SERIES_52; switch (chip->ficr_info.part) { + case 0x52805: case 0x52810: + case 0x52811: case 0x52832: chip->features |= NRF5_FEATURE_BPROT; break; + case 0x52820: + case 0x52833: case 0x52840: chip->features |= NRF5_FEATURE_ACL_PROT; break; } - break; + return ERROR_OK; default: LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08" - PRIx32, chip->ficr_info.part); + PRIx32, chip->ficr_info.part); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } +} - /* Now we know the device has FICR INFO filled by something relevant: - * Although it is not documented, the tested nRF51 rev 3 devices - * have FICR INFO.PART, RAM and FLASH of the same format as nRF52. - * VARIANT and PACKAGE coding is unknown for a nRF51 device. - * nRF52 devices have FICR INFO documented and always filled. */ +static int nrf53_91_partno_check(struct nrf5_info *chip) +{ + uint32_t series = chip->ficr_info.part & 0xffffff00; + switch (series) { + case 0x5300: + chip->features = NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_ERASE_BY_FLASH_WR; + return ERROR_OK; - res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant); - if (res != ERROR_OK) - return res; + case 0x9100: + chip->features = NRF5_FEATURE_SERIES_91 | NRF5_FEATURE_ERASE_BY_FLASH_WR; + return ERROR_OK; + + default: + LOG_DEBUG("Invalid FICR INFO PART value 0x%08" + PRIx32, chip->ficr_info.part); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } +} + +static int nrf5_read_ficr_more_info(struct nrf5_info *chip) +{ + int res; + struct target *target = chip->target; + const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets; + uint32_t ficr_base = chip->map->ficr_base; - res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package); + res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant); if (res != ERROR_OK) return res; - res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram); + res = target_read_u32(target, ficr_base + ficr_offsets->info_package, &chip->ficr_info.package); if (res != ERROR_OK) return res; - res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash); + res = target_read_u32(target, ficr_base + ficr_offsets->info_ram, &chip->ficr_info.ram); if (res != ERROR_OK) return res; - chip->ficr_info_valid = true; - return ERROR_OK; + res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash); + return res; } -static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size) +/* nRF51 series only */ +static int nrf51_get_ram_size(struct target *target, uint32_t *ram_size) { int res; @@ -752,31 +834,108 @@ static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size) return res; } -static int nrf5_probe(struct flash_bank *bank) +static int nrf5_probe_chip(struct flash_bank *bank) { - int res; + int res = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + struct nrf5_bank *nbank = bank->driver_priv; struct nrf5_info *chip = nbank->chip; struct target *target = chip->target; - uint32_t configid; - res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid); + chip->spec = NULL; + chip->ficr_info_valid = false; + + /* First try to detect nRF53/91 */ + switch (bank->base) { + case NRF5_FLASH_BASE: + case NRF53APP_91_UICR_BASE: + res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf91new_ficr_offsets); + if (res == ERROR_OK) { + res = nrf53_91_partno_check(chip); + if (res == ERROR_OK) { + chip->map = &nrf53app_91_map; + chip->ficr_offsets = &nrf91new_ficr_offsets; + break; + } + } + + res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf53_91_ficr_offsets); + if (res != ERROR_OK) + break; + + res = nrf53_91_partno_check(chip); + if (res != ERROR_OK) + break; + + chip->map = &nrf53app_91_map; + chip->ficr_offsets = &nrf53_91_ficr_offsets; + break; + + case NRF53NET_FLASH_BASE: + case NRF53NET_UICR_BASE: + res = nrf5_read_ficr_info_part(chip, &nrf53net_map, &nrf53_91_ficr_offsets); + if (res != ERROR_OK) + break; + + res = nrf53_91_partno_check(chip); + if (res != ERROR_OK) + break; + + chip->map = &nrf53net_map; + chip->ficr_offsets = &nrf53_91_ficr_offsets; + break; + + default: + break; + } + + /* If nRF53/91 is not detected, try nRF51/52 */ if (res != ERROR_OK) { - LOG_ERROR("Couldn't read CONFIGID register"); - return res; + /* Guess a nRF51 series if the device has no FICR INFO and we don't know HWID */ + chip->features = NRF5_FEATURE_SERIES_51; + chip->map = &nrf51_52_map; + chip->ficr_offsets = &nrf51_52_ficr_offsets; + + /* Don't bail out on error for the case that some old engineering + * sample has FICR INFO registers unreadable. We can proceed anyway. */ + res = nrf5_read_ficr_info_part(chip, chip->map, chip->ficr_offsets); + if (res == ERROR_OK) + res = nrf51_52_partno_check(chip); } - /* HWID is stored in the lower two bytes of the CONFIGID register */ - chip->hwid = configid & 0xFFFF; + if (res == ERROR_OK) { + /* Now we know the device has FICR INFO filled by something relevant: + * Although it is not documented, the tested nRF51 rev 3 devices + * have FICR INFO.PART, RAM and FLASH of the same format as nRF52. + * VARIANT and PACKAGE coding is unknown for a nRF51 device. + * nRF52 devices have FICR INFO documented and always filled. */ + res = nrf5_read_ficr_more_info(chip); + if (res == ERROR_OK) { + chip->ficr_info_valid = true; + } else if (chip->features & NRF5_FEATURE_SERIES_51) { + LOG_DEBUG("Couldn't read some of FICR INFO registers"); + } else { + LOG_ERROR("Couldn't read some of FICR INFO registers"); + return res; + } + } + + const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets; + uint32_t ficr_base = chip->map->ficr_base; + uint32_t configid = 0; + res = target_read_u32(target, ficr_base + ficr_offsets->configid, &configid); + if (res != ERROR_OK) { + if (chip->features & NRF5_FEATURE_SERIES_51) { + LOG_ERROR("Couldn't read FICR CONFIGID register"); + return res; + } - /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */ - chip->features = NRF5_FEATURE_SERIES_51; + LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO"); + } - /* Don't bail out on error for the case that some old engineering - * sample has FICR INFO registers unreadable. We can proceed anyway. */ - (void)nrf5_read_ficr_info(chip); + /* HWID is stored in the lower two bytes of the CONFIGID register */ + chip->hwid = configid & 0xFFFF; - chip->spec = NULL; for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) { if (chip->hwid == nrf5_known_devices_table[i].hwid) { chip->spec = &nrf5_known_devices_table[i]; @@ -794,94 +953,114 @@ static int nrf5_probe(struct flash_bank *bank) if (chip->ficr_info_valid) { chip->ram_size_kb = chip->ficr_info.ram; - } else { + } else if (chip->features & NRF5_FEATURE_SERIES_51) { uint32_t ram_size; - nrf5_get_ram_size(target, &ram_size); + nrf51_get_ram_size(target, &ram_size); chip->ram_size_kb = ram_size / 1024; + } else { + chip->ram_size_kb = 0; } - /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */ - uint32_t flash_page_size; - res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE, - &flash_page_size); + /* The value stored in FICR CODEPAGESIZE is the number of bytes in one page of FLASH. */ + res = target_read_u32(chip->target, ficr_base + ficr_offsets->codepagesize, + &chip->flash_page_size); if (res != ERROR_OK) { LOG_ERROR("Couldn't read code page size"); return res; } /* Note the register name is misleading, - * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */ - uint32_t num_sectors; - res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors); + * FICR CODESIZE is the number of pages in flash memory, not the number of bytes! */ + res = target_read_u32(chip->target, ficr_base + ficr_offsets->codesize, + &chip->flash_num_sectors); if (res != ERROR_OK) { LOG_ERROR("Couldn't read code memory size"); return res; } - chip->flash_size_kb = num_sectors * flash_page_size / 1024; + char chip_type_str[256]; + if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK) + return ERROR_FAIL; - if (!chip->bank[0].probed && !chip->bank[1].probed) { - char chip_type_str[256]; - if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK) - return ERROR_FAIL; - const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid); - LOG_INFO("%s%s %ukB Flash, %ukB RAM", - device_is_unknown ? "Unknown device: " : "", - chip_type_str, - chip->flash_size_kb, - chip->ram_size_kb); - } + unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024; + const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid); + LOG_INFO("%s%s %ukB Flash, %ukB RAM", + device_is_unknown ? "Unknown device: " : "", + chip_type_str, + flash_size_kb, + chip->ram_size_kb); + + chip->chip_probed = true; + return ERROR_OK; +} - free(bank->sectors); +static int nrf5_setup_bank(struct flash_bank *bank) +{ + struct nrf5_bank *nbank = bank->driver_priv; + struct nrf5_info *chip = nbank->chip; - if (bank->base == NRF5_FLASH_BASE) { + if (bank->base == chip->map->flash_base) { + unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024; /* Sanity check */ - if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb) + if (chip->spec && flash_size_kb != chip->spec->flash_size_kb) LOG_WARNING("Chip's reported Flash capacity does not match expected one"); - if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash) + if (chip->ficr_info_valid && flash_size_kb != chip->ficr_info.flash) LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH"); - bank->num_sectors = num_sectors; - bank->size = num_sectors * flash_page_size; + bank->num_sectors = chip->flash_num_sectors; + bank->size = chip->flash_num_sectors * chip->flash_page_size; - bank->sectors = alloc_block_array(0, flash_page_size, num_sectors); + bank->sectors = alloc_block_array(0, chip->flash_page_size, bank->num_sectors); if (!bank->sectors) return ERROR_FAIL; chip->bank[0].probed = true; - } else { + } else if (bank->base == chip->map->uicr_base) { + /* UICR bank */ bank->num_sectors = 1; - bank->size = flash_page_size; + bank->size = chip->flash_page_size; - bank->sectors = alloc_block_array(0, flash_page_size, num_sectors); + bank->sectors = alloc_block_array(0, chip->flash_page_size, bank->num_sectors); if (!bank->sectors) return ERROR_FAIL; bank->sectors[0].is_protected = 0; chip->bank[1].probed = true; + } else { + LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base); + return ERROR_FLASH_BANK_INVALID; } return ERROR_OK; } +static int nrf5_probe(struct flash_bank *bank) +{ + /* probe always reads actual info from the device */ + int res = nrf5_probe_chip(bank); + if (res != ERROR_OK) + return res; + + return nrf5_setup_bank(bank); +} + static int nrf5_auto_probe(struct flash_bank *bank) { if (nrf5_bank_is_probed(bank)) return ERROR_OK; - return nrf5_probe(bank); -} + if (!nrf5_chip_is_probed(bank)) { + int res = nrf5_probe_chip(bank); + if (res != ERROR_OK) + return res; + } -static int nrf5_erase_all(struct nrf5_info *chip) -{ - LOG_DEBUG("Erasing all non-volatile memory"); - return nrf5_nvmc_generic_erase(chip, - NRF5_NVMC_ERASEALL, - 0x00000001); + return nrf5_setup_bank(bank); } + static int nrf5_erase_page(struct flash_bank *bank, struct nrf5_info *chip, struct flash_sector *sector) @@ -890,7 +1069,7 @@ static int nrf5_erase_page(struct flash_bank *bank, LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset); - if (bank->base == NRF5_UICR_BASE) { + if (bank->base == chip->map->uicr_base) { if (chip->features & NRF5_FEATURE_SERIES_51) { uint32_t ppfc; res = target_read_u32(chip->target, NRF51_FICR_PPFC, @@ -912,17 +1091,37 @@ static int nrf5_erase_page(struct flash_bank *bank, } } - res = nrf5_nvmc_generic_erase(chip, - NRF5_NVMC_ERASEUICR, - 0x00000001); - + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEUICR, 0x00000001); + + } else if (chip->features & NRF5_FEATURE_ERASE_BY_FLASH_WR) { + res = target_write_u32(chip->target, bank->base + sector->offset, 0xffffffff); + /* nRF9160 errata [2] NVMC: CPU code execution from RAM halted during + * flash page erase operation + * https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF9160_Rev1%2FERR%2FnRF9160%2FRev1%2Flatest%2Fanomaly_160_2.html + * affects also erasing by debugger MEM-AP write: + * + * Write to a flash address stalls the bus for 87 ms until + * page erase finishes! This makes problems if the adapter does not + * handle SWD WAIT properly or does not wait long enough. + * Using a target algo would not help, AP gets unresponsive too. + * Neither sending AP ABORT helps, the next AP access stalls again. + * Simply wait long enough before accessing AP again... + * + * The same errata was observed in nRF9161 + */ + if (chip->features & NRF5_FEATURE_SERIES_91) + alive_sleep(90); } else { - res = nrf5_nvmc_generic_erase(chip, - NRF5_NVMC_ERASEPAGE, - sector->offset); + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE, sector->offset); } + if (res != ERROR_OK) { + /* caller logs the error */ + return res; + } + + res = nrf5_wait_for_nvmc(chip); return res; } @@ -999,7 +1198,7 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size); buf_set_u32(reg_params[3].value, 0, 32, address); buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE); - buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER); + buf_set_u32(reg_params[5].value, 0, 32, chip->map->watchdog_refresh_addr); retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4, 0, NULL, @@ -1024,11 +1223,15 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { - struct nrf5_info *chip; + int res; - int res = nrf5_get_probed_chip_if_halted(bank, &chip); - if (res != ERROR_OK) - return res; + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + struct nrf5_bank *nbank = bank->driver_priv; + struct nrf5_info *chip = nbank->chip; assert(offset % 4 == 0); assert(count % 4 == 0); @@ -1043,7 +1246,7 @@ static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer, * is protected. */ if (chip->features & NRF5_FEATURE_SERIES_51) { - res = nrf5_protect_check_clenr0(bank); + res = nrf51_protect_check_clenr0(bank); if (res != ERROR_OK) return res; @@ -1081,11 +1284,14 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first, unsigned int last) { int res; - struct nrf5_info *chip; - res = nrf5_get_probed_chip_if_halted(bank, &chip); - if (res != ERROR_OK) - return res; + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + struct nrf5_bank *nbank = bank->driver_priv; + struct nrf5_info *chip = nbank->chip; /* UICR CLENR0 based protection used on nRF51 prevents erase * absolutely silently. NVMC has no flag to indicate the protection @@ -1095,18 +1301,23 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first, * is protected. */ if (chip->features & NRF5_FEATURE_SERIES_51) { - res = nrf5_protect_check_clenr0(bank); + res = nrf51_protect_check_clenr0(bank); if (res != ERROR_OK) return res; } + res = nrf5_nvmc_erase_enable(chip); + if (res != ERROR_OK) + goto error; + /* For each sector to be erased */ - for (unsigned int s = first; s <= last && res == ERROR_OK; s++) { + for (unsigned int s = first; s <= last; s++) { if (chip->features & NRF5_FEATURE_SERIES_51 && bank->sectors[s].is_protected == 1) { LOG_ERROR("Flash sector %d is protected", s); - return ERROR_FLASH_PROTECTED; + res = ERROR_FLASH_PROTECTED; + break; } res = nrf5_erase_page(bank, chip, &bank->sectors[s]); @@ -1116,7 +1327,9 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first, } } - return ERROR_OK; +error: + nrf5_nvmc_read_only(chip); + return res; } static void nrf5_free_driver_priv(struct flash_bank *bank) @@ -1160,13 +1373,19 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command) struct nrf5_info *chip; struct nrf5_bank *nbank = NULL; + if (bank->driver == &nrf51_flash) + LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead."); + switch (bank->base) { case NRF5_FLASH_BASE: - case NRF5_UICR_BASE: + case NRF53NET_FLASH_BASE: + case NRF51_52_UICR_BASE: + case NRF53APP_91_UICR_BASE: + case NRF53NET_UICR_BASE: break; default: - LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base); - return ERROR_FAIL; + LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base); + return ERROR_FLASH_BANK_INVALID; } chip = nrf5_get_chip(bank->target); @@ -1181,9 +1400,12 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command) switch (bank->base) { case NRF5_FLASH_BASE: + case NRF53NET_FLASH_BASE: nbank = &chip->bank[0]; break; - case NRF5_UICR_BASE: + case NRF51_52_UICR_BASE: + case NRF53APP_91_UICR_BASE: + case NRF53NET_UICR_BASE: nbank = &chip->bank[1]; break; } @@ -1208,13 +1430,13 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command) if (res != ERROR_OK) return res; - assert(bank); - - struct nrf5_info *chip; + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } - res = nrf5_get_probed_chip_if_halted(bank, &chip); - if (res != ERROR_OK) - return res; + struct nrf5_bank *nbank = bank->driver_priv; + struct nrf5_info *chip = nbank->chip; if (chip->features & NRF5_FEATURE_SERIES_51) { uint32_t ppfc; @@ -1232,151 +1454,33 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command) } } - res = nrf5_erase_all(chip); - if (res == ERROR_OK) { - LOG_INFO("Mass erase completed."); - if (chip->features & NRF5_FEATURE_SERIES_51) - LOG_INFO("A reset or power cycle is required if the flash was protected before."); - - } else { - LOG_ERROR("Failed to erase the chip"); - } - - return res; -} - -COMMAND_HANDLER(nrf5_handle_info_command) -{ - int res; - struct flash_bank *bank = NULL; - struct target *target = get_current_target(CMD_CTX); - - res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank); + res = nrf5_nvmc_erase_enable(chip); if (res != ERROR_OK) - return res; - - assert(bank); + goto error; - struct nrf5_info *chip; + res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEALL, 0x00000001); + if (res != ERROR_OK) { + LOG_ERROR("Mass erase failed"); + goto error; + } - res = nrf5_get_probed_chip_if_halted(bank, &chip); + res = nrf5_wait_for_nvmc(chip); if (res != ERROR_OK) - return res; + LOG_ERROR("Mass erase did not complete"); - static struct { - const uint32_t address; - uint32_t value; - } ficr[] = { - { .address = NRF5_FICR_CODEPAGESIZE }, - { .address = NRF5_FICR_CODESIZE }, - { .address = NRF51_FICR_CLENR0 }, - { .address = NRF51_FICR_PPFC }, - { .address = NRF51_FICR_NUMRAMBLOCK }, - { .address = NRF51_FICR_SIZERAMBLOCK0 }, - { .address = NRF51_FICR_SIZERAMBLOCK1 }, - { .address = NRF51_FICR_SIZERAMBLOCK2 }, - { .address = NRF51_FICR_SIZERAMBLOCK3 }, - { .address = NRF5_FICR_CONFIGID }, - { .address = NRF5_FICR_DEVICEID0 }, - { .address = NRF5_FICR_DEVICEID1 }, - { .address = NRF5_FICR_ER0 }, - { .address = NRF5_FICR_ER1 }, - { .address = NRF5_FICR_ER2 }, - { .address = NRF5_FICR_ER3 }, - { .address = NRF5_FICR_IR0 }, - { .address = NRF5_FICR_IR1 }, - { .address = NRF5_FICR_IR2 }, - { .address = NRF5_FICR_IR3 }, - { .address = NRF5_FICR_DEVICEADDRTYPE }, - { .address = NRF5_FICR_DEVICEADDR0 }, - { .address = NRF5_FICR_DEVICEADDR1 }, - { .address = NRF51_FICR_OVERRIDEN }, - { .address = NRF51_FICR_NRF_1MBIT0 }, - { .address = NRF51_FICR_NRF_1MBIT1 }, - { .address = NRF51_FICR_NRF_1MBIT2 }, - { .address = NRF51_FICR_NRF_1MBIT3 }, - { .address = NRF51_FICR_NRF_1MBIT4 }, - { .address = NRF51_FICR_BLE_1MBIT0 }, - { .address = NRF51_FICR_BLE_1MBIT1 }, - { .address = NRF51_FICR_BLE_1MBIT2 }, - { .address = NRF51_FICR_BLE_1MBIT3 }, - { .address = NRF51_FICR_BLE_1MBIT4 }, - }, uicr[] = { - { .address = NRF51_UICR_CLENR0, }, - { .address = NRF51_UICR_RBPCONF }, - { .address = NRF51_UICR_XTALFREQ }, - { .address = NRF51_UICR_FWID }, - }; - - for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) { - res = target_read_u32(chip->target, ficr[i].address, - &ficr[i].value); - if (res != ERROR_OK) { - LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address); - return res; - } - } +error: + nrf5_nvmc_read_only(chip); - for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) { - res = target_read_u32(chip->target, uicr[i].address, - &uicr[i].value); - if (res != ERROR_OK) { - LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address); - return res; - } + if (res == ERROR_OK) { + LOG_INFO("Mass erase completed."); + if (chip->features & NRF5_FEATURE_SERIES_51) + LOG_INFO("A reset or power cycle is required if the flash was protected before."); } - command_print(CMD, - "\n[factory information control block]\n\n" - "code page size: %"PRIu32"B\n" - "code memory size: %"PRIu32"kB\n" - "code region 0 size: %"PRIu32"kB\n" - "pre-programmed code: %s\n" - "number of ram blocks: %"PRIu32"\n" - "ram block 0 size: %"PRIu32"B\n" - "ram block 1 size: %"PRIu32"B\n" - "ram block 2 size: %"PRIu32"B\n" - "ram block 3 size: %"PRIu32 "B\n" - "config id: %" PRIx32 "\n" - "device id: 0x%"PRIx32"%08"PRIx32"\n" - "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n" - "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n" - "device address type: 0x%"PRIx32"\n" - "device address: 0x%"PRIx32"%08"PRIx32"\n" - "override enable: %"PRIx32"\n" - "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n" - "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n" - "\n[user information control block]\n\n" - "code region 0 size: %"PRIu32"kB\n" - "read back protection configuration: %"PRIx32"\n" - "reset value for XTALFREQ: %"PRIx32"\n" - "firmware id: 0x%04"PRIx32, - ficr[0].value, - (ficr[1].value * ficr[0].value) / 1024, - (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024, - ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present", - ficr[4].value, - ficr[5].value, - (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value, - (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value, - (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value, - ficr[9].value, - ficr[10].value, ficr[11].value, - ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value, - ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value, - ficr[20].value, - ficr[21].value, ficr[22].value, - ficr[23].value, - ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value, - ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value, - (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024, - uicr[1].value & 0xFFFF, - uicr[2].value & 0xFF, - uicr[3].value & 0xFFFF); - - return ERROR_OK; + return res; } + static const struct command_registration nrf5_exec_command_handlers[] = { { .name = "mass_erase", @@ -1385,13 +1489,6 @@ static const struct command_registration nrf5_exec_command_handlers[] = { .help = "Erase all flash contents of the chip.", .usage = "", }, - { - .name = "info", - .handler = nrf5_handle_info_command, - .mode = COMMAND_EXEC, - .help = "Show FICR and UICR info.", - .usage = "", - }, COMMAND_REGISTRATION_DONE }; diff --git a/src/flash/nor/numicro.c b/src/flash/nor/numicro.c index a533c4103e..a0c6e0c815 100644 --- a/src/flash/nor/numicro.c +++ b/src/flash/nor/numicro.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by James K. Larson * @@ -12,6 +12,12 @@ * * * Copyright (C) 2015 Nemui Trinomius * * nemuisan_kawausogasuki@live.jp * + * * + * Copyright (C) 2017 Zale Yu * + * CYYU@nuvoton.com * + * * + * Copyright (C) 2022 Jian-Hong Pan * + * chienhung.pan@gmail.com * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -114,1008 +120,412 @@ struct numicro_cpu_type { struct numicro_flash_bank_type bank[NUMICRO_MAX_FLASH_BANKS]; }; -/* TODO : Support variable DataFlash region for 128kB Flash model */ -#define NUMICRO_BANKS_NUC100(aprom_size) \ - .n_banks = 4, \ - { {NUMICRO_APROM_BASE, (aprom_size)}, {NUMICRO_DATA_BASE, 4*1024}, {NUMICRO_LDROM_BASE, 4*1024}, \ - {NUMICRO_CONFIG_BASE, 1024} } - -#define NUMICRO_BANKS_M051(aprom_size) \ - .n_banks = 4, \ - { {NUMICRO_APROM_BASE, (aprom_size)}, {NUMICRO_DATA_BASE, 4*1024}, {NUMICRO_LDROM_BASE, 4*1024}, \ - {NUMICRO_CONFIG_BASE, 1024} } - -#define NUMICRO_BANKS_MINI51(aprom_size) \ - .n_banks = 3, \ - { {NUMICRO_APROM_BASE, (aprom_size)}, {NUMICRO_LDROM_BASE, 2*1024}, {NUMICRO_CONFIG_BASE, 512} } - -#define NUMICRO_BANKS_NANO(aprom_size) \ +/* If DataFlash size equals zero, it means the actual size depends on config settings. */ +#define NUMICRO_BANKS_GENERAL(aprom_size, data_size, ldrom_size, config_size) \ .n_banks = 4, \ - { {NUMICRO_APROM_BASE, (aprom_size)}, {NUMICRO_DATA_BASE, 4*1024}, {NUMICRO_LDROM_BASE, 4*1024}, \ - {NUMICRO_CONFIG_BASE, 1024} } - -#define NUMICRO_BANKS_NUC400(aprom_size) \ - .n_banks = 4, \ - { {NUMICRO_APROM_BASE, (aprom_size)}, {NUMICRO_DATA_BASE, 4*1024}, {NUMICRO_LDROM_BASE, 16*1024}, \ - {NUMICRO_CONFIG_BASE, 1024} } - + {{NUMICRO_APROM_BASE, (aprom_size)}, \ + {NUMICRO_DATA_BASE, (data_size)}, \ + {NUMICRO_LDROM_BASE, (ldrom_size)}, \ + {NUMICRO_CONFIG_BASE, (config_size)}} static const struct numicro_cpu_type numicro_parts[] = { /*PART NO*/ /*PART ID*/ /*Banks*/ - /* NUC100 Version B */ - {"NUC100LD2BN", 0x10010004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD1BN", 0x10010005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD0BN", 0x10010027, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LC2BN", 0x10010007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC1BN", 0x10010008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC0BN", 0x10010028, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LB2BN", 0x10010029, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100LB1BN", 0x10010030, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100LB0BN", 0x10010031, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100LA2BN", 0x10010032, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC100LA1BN", 0x10010033, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC100LA0BN", 0x10010034, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC100RD2BN", 0x10010013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD1BN", 0x10010014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD0BN", 0x10010035, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RC2BN", 0x10010016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC1BN", 0x10010017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC0BN", 0x10010036, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RB2BN", 0x10010037, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100RB1BN", 0x10010038, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100RB0BN", 0x10010039, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC100RA2BN", 0x10010040, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC100RA1BN", 0x10010041, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC100RA0BN", 0x10010042, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC100 Version C */ - {"NUC100LE3CN", 0x20010000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LE2CN", 0x20010001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LE1CN", 0x20010002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LD3CN", 0x20010003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD2CN", 0x20010004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD1CN", 0x20010005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LC3CN", 0x20010006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC2CN", 0x20010007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC1CN", 0x20010008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RE3CN", 0x20010009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RE2CN", 0x20010010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RE1CN", 0x20010011, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RD3CN", 0x20010012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD2CN", 0x20010013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD1CN", 0x20010014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RC3CN", 0x20010015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC2CN", 0x20010016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC1CN", 0x20010017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VE3CN", 0x20010018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VE2CN", 0x20010019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VE1CN", 0x20010020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VD3CN", 0x20010021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VD2CN", 0x20010022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VD1CN", 0x20010023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VC3CN", 0x20010024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VC2CN", 0x20010025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VC1CN", 0x20010026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC100 Version B */ - {"NUC101YD2BN", 0x10010143, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101YD1BN", 0x10010144, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101YD0BN", 0x10010145, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101YC2BN", 0x10010146, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101YC1BN", 0x10010147, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101YC0BN", 0x10010148, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101YB2BN", 0x10010149, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101YB1BN", 0x10010150, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101YB0BN", 0x10010151, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101YA2BN", 0x10010152, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101YA1BN", 0x10010153, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101YA0BN", 0x10010154, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC101LD2BN", 0x10010104, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD1BN", 0x10010105, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD0BN", 0x10010127, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LC2BN", 0x10010107, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC1BN", 0x10010108, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC0BN", 0x10010128, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LB2BN", 0x10010129, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101LB1BN", 0x10010130, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101LB0BN", 0x10010131, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101LA2BN", 0x10010132, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101LA1BN", 0x10010133, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101LA0BN", 0x10010134, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC101RD2BN", 0x10010113, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD1BN", 0x10010114, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD0BN", 0x10010135, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RC2BN", 0x10010116, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC1BN", 0x10010117, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC0BN", 0x10010136, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RB2BN", 0x10010137, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101RB1BN", 0x10010138, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101RB0BN", 0x10010139, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC101RA2BN", 0x10010140, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101RA1BN", 0x10010141, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC101RA0BN", 0x10010142, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC101 Version C */ - {"NUC101LE3CN", 0x20010100, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LE2CN", 0x20010101, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LE1CN", 0x20010102, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LD3CN", 0x20010103, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD2CN", 0x20010104, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD1CN", 0x20010105, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LC3CN", 0x20010106, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC2CN", 0x20010107, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC1CN", 0x20010108, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RE3CN", 0x20010109, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101RE2CN", 0x20010110, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101RE1CN", 0x20010111, NUMICRO_BANKS_NUC100(128*1024)}, - - {"NUC101RD3CN", 0x20010112, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD2CN", 0x20010113, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD1CN", 0x20010114, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RC3CN", 0x20010115, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC2CN", 0x20010116, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC1CN", 0x20010117, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VE3CN", 0x20010118, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VE2CN", 0x20010119, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VE1CN", 0x20010120, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VD3CN", 0x20010121, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VD2CN", 0x20010122, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VD1CN", 0x20010123, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VC3CN", 0x20010124, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VC2CN", 0x20010125, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VC1CN", 0x20010126, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC102 Version A */ - {"NUC102ZD2AN", 0x00010231, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC102ZC1AN", 0x00010235, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC102LD2AN", 0x00010204, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC102LC1AN", 0x00010208, NUMICRO_BANKS_NUC100(32*1024)}, - - {"NUC102RB3AN", 0x00010248, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102RB2AN", 0x00010249, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102RB1AN", 0x00010250, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102RA3AN", 0x00010251, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102RA2AN", 0x00010252, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102RA1AN", 0x00010253, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102VB3AN", 0x00010254, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102VB2AN", 0x00010255, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102VB1AN", 0x00010256, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102VA3AN", 0x00010257, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102VA2AN", 0x00010258, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102VA1AN", 0x00010259, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102LA0AN", 0x00010260, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102LB0AN", 0x00010261, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102LC0AN", 0x00010262, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC102LD0AN", 0x00010263, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC102RA0AN", 0x00010264, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102RB0AN", 0x00010265, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102RC0AN", 0x00010266, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC102RD0AN", 0x00010267, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC102VA0AN", 0x00010268, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102VB0AN", 0x00010269, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102VC0AN", 0x00010270, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC102VD0AN", 0x00010271, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC102ZA0AN", 0x00010272, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC102ZB0AN", 0x00010273, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC102ZC0AN", 0x00010274, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC102ZD0AN", 0x00010275, NUMICRO_BANKS_NUC100(64*1024)}, - - /* NUC102 Version A */ - {"NUC122LD2AN", 0x00012204, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122LD1AN", 0x00012205, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122LC2AN", 0x00012207, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122LC1AN", 0x00012208, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122RD2AN", 0x00012213, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122RD1AN", 0x00012214, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122RC2AN", 0x00012216, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122RC1AN", 0x00012217, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122SD2AN", 0x00012222, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122SD1AN", 0x00012223, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122SC2AN", 0x00012225, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122SC1AN", 0x00012226, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122ZD2AN", 0x00012231, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122ZD1AN", 0x00012232, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122ZC2AN", 0x00012234, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122ZC1AN", 0x00012235, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122ZB2AN", 0x00012237, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122ZB1AN", 0x00012238, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122ZA2AN", 0x00012240, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122ZA1AN", 0x00012241, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122LB2AN", 0x00012243, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122LB1AN", 0x00012244, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122LA2AN", 0x00012246, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122LA1AN", 0x00012247, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122RB2AN", 0x00012249, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122RB1AN", 0x00012250, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122RA2AN", 0x00012252, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122RA1AN", 0x00012253, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122SB2AN", 0x00012255, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122SB1AN", 0x00012256, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122SA2AN", 0x00012258, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122SA1AN", 0x00012259, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122LA0AN", 0x00012260, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122LB0AN", 0x00012261, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122LC0AN", 0x00012262, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122LD0AN", 0x00012263, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122RA0AN", 0x00012264, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122RB0AN", 0x00012265, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122RC0AN", 0x00012266, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122RD0AN", 0x00012267, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122SA0AN", 0x00012268, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122SB0AN", 0x00012269, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122SC0AN", 0x00012270, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122SD0AN", 0x00012271, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122ZA0AN", 0x00012272, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122ZB0AN", 0x00012273, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122ZC0AN", 0x00012274, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122ZD0AN", 0x00012275, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122YD2AN", 0x00012277, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122YD1AN", 0x00012278, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122YD0AN", 0x00012279, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC122YC2AN", 0x00012281, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122YC1AN", 0x00012282, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122YC0AN", 0x00012283, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC122YB2AN", 0x00012285, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122YB1AN", 0x00012286, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122YB0AN", 0x00012287, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC122YA2AN", 0x00012289, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122YA1AN", 0x00012290, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC122YA0AN", 0x00012291, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC120 Version C */ - {"NUC120LD2BN", 0x10012004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD1BN", 0x10012005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD0BN", 0x10012027, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LC2BN", 0x10012007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC1BN", 0x10012008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC0BN", 0x10012028, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LB2BN", 0x10012029, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120LB1BN", 0x10012030, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120LB0BN", 0x10012031, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120LA2BN", 0x10012032, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC120LA1BN", 0x10012033, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC120LA0BN", 0x10012034, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC120RD2BN", 0x10012013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD1BN", 0x10012014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD0BN", 0x10012035, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RC2BN", 0x10012016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC1BN", 0x10012017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC0BN", 0x10012036, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RB2BN", 0x10012037, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120RB1BN", 0x10012038, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120RB0BN", 0x10012039, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC120RA2BN", 0x10012040, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC120RA1BN", 0x10012041, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC120RA0BN", 0x10012042, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC120 Version C */ - {"NUC120LE3CN", 0x20012000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LE2CN", 0x20012001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LE1CN", 0x20012002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LD3CN", 0x20012003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD2CN", 0x20012004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD1CN", 0x20012005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LC3CN", 0x20012006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC2CN", 0x20012007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC1CN", 0x20012008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RE3CN", 0x20012009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RE2CN", 0x20012010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RE1CN", 0x20012011, NUMICRO_BANKS_NUC100(128*1024)}, - - {"NUC120RD3CN", 0x20012012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD2CN", 0x20012013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD1CN", 0x20012014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RC3CN", 0x20012015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC2CN", 0x20012016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC1CN", 0x20012017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VE3CN", 0x20012018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VE2CN", 0x20012019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VE1CN", 0x20012020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VD3CN", 0x20012021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VD2CN", 0x20012022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VD1CN", 0x20012023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VC3CN", 0x20012024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VC2CN", 0x20012025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VC1CN", 0x20012026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC120 Version B */ - {"NUC130LD2BN", 0x10013004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD1BN", 0x10013005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD0BN", 0x10013027, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LC2BN", 0x10013007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC1BN", 0x10013008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC0BN", 0x10013028, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LB2BN", 0x10013029, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130LB1BN", 0x10013030, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130LB0BN", 0x10013031, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130LA2BN", 0x10013032, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC130LA1BN", 0x10013033, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC130LA0BN", 0x10013034, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC130RD2BN", 0x10013013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD1BN", 0x10013014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD0BN", 0x10013035, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RC2BN", 0x10013016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC1BN", 0x10013017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC0BN", 0x10013036, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RB2BN", 0x10013037, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130RB1BN", 0x10013038, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130RB0BN", 0x10013039, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC130RA2BN", 0x10013040, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC130RA1BN", 0x10013041, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC130RA0BN", 0x10013042, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC130 Version C */ - {"NUC130LE3CN", 0x20013000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LE2CN", 0x20013001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LE1CN", 0x20013002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LD3CN", 0x20013003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD2CN", 0x20013004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD1CN", 0x20013005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LC3CN", 0x20013006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC2CN", 0x20013007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC1CN", 0x20013008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RE3CN", 0x20013009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RE2CN", 0x20013010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RE1CN", 0x20013011, NUMICRO_BANKS_NUC100(128*1024)}, - - {"NUC130RD3CN", 0x20013012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD2CN", 0x20013013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD1CN", 0x20013014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RC3CN", 0x20013015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC2CN", 0x20013016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC1CN", 0x20013017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VE3CN", 0x20013018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VE2CN", 0x20013019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VE1CN", 0x20013020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VD3CN", 0x20013021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VD2CN", 0x20013022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VD1CN", 0x20013023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VC3CN", 0x20013024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VC2CN", 0x20013025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VC1CN", 0x20013026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC140 Version B */ - {"NUC140LD2BN", 0x10014004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD1BN", 0x10014005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD0BN", 0x10014027, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LC2BN", 0x10014007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC1BN", 0x10014008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC0BN", 0x10014028, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LB2BN", 0x10014029, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140LB1BN", 0x10014030, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140LB0BN", 0x10014031, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140LA2BN", 0x10014032, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC140LA1BN", 0x10014033, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC140LA0BN", 0x10014034, NUMICRO_BANKS_NUC100(8*1024)}, - - {"NUC140RD2BN", 0x10014013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD1BN", 0x10014014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD0BN", 0x10014035, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RC2BN", 0x10014016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC1BN", 0x10014017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC0BN", 0x10014036, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RB2BN", 0x10014037, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140RB1BN", 0x10014038, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140RB0BN", 0x10014039, NUMICRO_BANKS_NUC100(16*1024)}, - {"NUC140RA2BN", 0x10014040, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC140RA1BN", 0x10014041, NUMICRO_BANKS_NUC100(8*1024)}, - {"NUC140RA0BN", 0x10014042, NUMICRO_BANKS_NUC100(8*1024)}, - - /* NUC140 Version C */ - {"NUC140LE3CN", 0x20014000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LE2CN", 0x20014001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LE1CN", 0x20014002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LD3CN", 0x20014003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD2CN", 0x20014004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD1CN", 0x20014005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LC3CN", 0x20014006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC2CN", 0x20014007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC1CN", 0x20014008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RE3CN", 0x20014009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140RE2CN", 0x20014010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140RE1CN", 0x20014011, NUMICRO_BANKS_NUC100(128*1024)}, - - {"NUC140RD3CN", 0x20014012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD2CN", 0x20014013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD1CN", 0x20014014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RC3CN", 0x20014015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC2CN", 0x20014016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC1CN", 0x20014017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VE3CN", 0x20014018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VE2CN", 0x20014019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VE1CN", 0x20014020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VD3CN", 0x20014021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VD2CN", 0x20014022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VD1CN", 0x20014023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VC3CN", 0x20014024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VC2CN", 0x20014025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VC1CN", 0x20014026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC100 Version A */ - {"NUC100LE3AN", 0x00010000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LE2AN", 0x00010001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LE1AN", 0x00010002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100LD3AN", 0x00010003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD2AN", 0x00010004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD1AN", 0x00010005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LC3AN", 0x00010006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC2AN", 0x00010007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LC1AN", 0x00010008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RE3AN", 0x00010009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RE2AN", 0x00010010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RE1AN", 0x00010011, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RD3AN", 0x00010012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD2AN", 0x00010013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD1AN", 0x00010014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RC3AN", 0x00010015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC2AN", 0x00010016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RC1AN", 0x00010017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VE3AN", 0x00010018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VE2AN", 0x00010019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VE1AN", 0x00010020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VD3AN", 0x00010021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VD2AN", 0x00010022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VD1AN", 0x00010023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VC3AN", 0x00010024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VC2AN", 0x00010025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100VC1AN", 0x00010026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC100 Version A */ - {"NUC101LE3AN", 0x00010100, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LE2AN", 0x00010101, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LE1AN", 0x00010102, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101LD3AN", 0x00010103, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD2AN", 0x00010104, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LD1AN", 0x00010105, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101LC3AN", 0x00010106, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC2AN", 0x00010107, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101LC1AN", 0x00010108, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RE3AN", 0x00010109, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101RE2AN", 0x00010110, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101RE1AN", 0x00010111, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101RD3AN", 0x00010112, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD2AN", 0x00010113, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RD1AN", 0x00010114, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101RC3AN", 0x00010115, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC2AN", 0x00010116, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101RC1AN", 0x00010117, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VE3AN", 0x00010118, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VE2AN", 0x00010119, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VE1AN", 0x00010120, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC101VD3AN", 0x00010121, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VD2AN", 0x00010122, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VD1AN", 0x00010123, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC101VC3AN", 0x00010124, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VC2AN", 0x00010125, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC101VC1AN", 0x00010126, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC120 Version A */ - {"NUC120LE3AN", 0x00012000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LE2AN", 0x00012001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LE1AN", 0x00012002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LD3AN", 0x00012003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD2AN", 0x00012004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD1AN", 0x00012005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LC3AN", 0x00012006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC2AN", 0x00012007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LC1AN", 0x00012008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RE3AN", 0x00012009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RE2AN", 0x00012010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RE1AN", 0x00012011, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RD3AN", 0x00012012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD2AN", 0x00012013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD1AN", 0x00012014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RC3AN", 0x00012015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC2AN", 0x00012016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RC1AN", 0x00012017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VE3AN", 0x00012018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VE2AN", 0x00012019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VE1AN", 0x00012020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VD3AN", 0x00012021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VD2AN", 0x00012022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VD1AN", 0x00012023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VC3AN", 0x00012024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VC2AN", 0x00012025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120VC1AN", 0x00012026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC120 Version A */ - {"NUC130LE3AN", 0x00013000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LE2AN", 0x00013001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LE1AN", 0x00013002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130LD3AN", 0x00013003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD2AN", 0x00013004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LD1AN", 0x00013005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130LC3AN", 0x00013006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC2AN", 0x00013007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130LC1AN", 0x00013008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RE3AN", 0x00013009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RE2AN", 0x00013010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RE1AN", 0x00013011, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RD3AN", 0x00013012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD2AN", 0x00013013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RD1AN", 0x00013014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130RC3AN", 0x00013015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC2AN", 0x00013016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130RC1AN", 0x00013017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VE3AN", 0x00013018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VE2AN", 0x00013019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VE1AN", 0x00013020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130VD3AN", 0x00013021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VD2AN", 0x00013022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VD1AN", 0x00013023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC130VC3AN", 0x00013024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VC2AN", 0x00013025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC130VC1AN", 0x00013026, NUMICRO_BANKS_NUC100(32*1024)}, - - /* NUC140 Version A */ - {"NUC140LE3AN", 0x00014000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LE2AN", 0x00014001, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LE1AN", 0x00014002, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140LD3AN", 0x00014003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD2AN", 0x00014004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LD1AN", 0x00014005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140LC3AN", 0x00014006, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC2AN", 0x00014007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140LC1AN", 0x00014008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RE3AN", 0x00014009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140RE2AN", 0x00014010, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140RE1AN", 0x00014011, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140RD3AN", 0x00014012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD2AN", 0x00014013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RD1AN", 0x00014014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140RC3AN", 0x00014015, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC2AN", 0x00014016, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140RC1AN", 0x00014017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VE3AN", 0x00014018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VE2AN", 0x00014019, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VE1AN", 0x00014020, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC140VD3AN", 0x00014021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VD2AN", 0x00014022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VD1AN", 0x00014023, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC140VC3AN", 0x00014024, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VC2AN", 0x00014025, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC140VC1AN", 0x00014026, NUMICRO_BANKS_NUC100(32*1024)}, - - - /* M052 */ - {"M052LAN" , 0x00005200, NUMICRO_BANKS_M051(8*1024)}, - {"M052PAN" , 0x00005201, NUMICRO_BANKS_M051(8*1024)}, - {"M052YAN" , 0x00005202, NUMICRO_BANKS_M051(8*1024)}, - {"M052ZAN" , 0x00005203, NUMICRO_BANKS_M051(8*1024)}, - - /* M054 */ - {"M054LAN" , 0x00005400, NUMICRO_BANKS_M051(16*1024)}, - {"M054PAN" , 0x00005401, NUMICRO_BANKS_M051(16*1024)}, - {"M054YAN" , 0x00005402, NUMICRO_BANKS_M051(16*1024)}, - {"M054ZAN" , 0x00005403, NUMICRO_BANKS_M051(16*1024)}, - - /* M058 */ - {"M058LAN" , 0x00005800, NUMICRO_BANKS_M051(32*1024)}, - {"M058PAN" , 0x00005801, NUMICRO_BANKS_M051(32*1024)}, - {"M058YAN" , 0x00005802, NUMICRO_BANKS_M051(32*1024)}, - {"M058ZAN" , 0x00005803, NUMICRO_BANKS_M051(32*1024)}, - - /* M0516 */ - {"M0516LAN" , 0x00005A00, NUMICRO_BANKS_M051(64*1024)}, - {"M0516PAN" , 0x00005A01, NUMICRO_BANKS_M051(64*1024)}, - {"M0516YAN" , 0x00005A02, NUMICRO_BANKS_M051(64*1024)}, - {"M0516ZAN" , 0x00005A03, NUMICRO_BANKS_M051(64*1024)}, - {"M051LBN" , 0x10005100, NUMICRO_BANKS_M051(4*1024)}, - {"M051PBN" , 0x10005101, NUMICRO_BANKS_M051(4*1024)}, - {"M051YBN" , 0x10005102, NUMICRO_BANKS_M051(4*1024)}, - {"M051ZBN" , 0x10005103, NUMICRO_BANKS_M051(4*1024)}, - {"M052LBN" , 0x10005200, NUMICRO_BANKS_M051(8*1024)}, - {"M052PBN" , 0x10005201, NUMICRO_BANKS_M051(8*1024)}, - {"M052YBN" , 0x10005202, NUMICRO_BANKS_M051(8*1024)}, - {"M052ZBN" , 0x10005203, NUMICRO_BANKS_M051(8*1024)}, - {"M054LBN" , 0x10005400, NUMICRO_BANKS_M051(16*1024)}, - {"M054PBN" , 0x10005401, NUMICRO_BANKS_M051(16*1024)}, - {"M054YBN" , 0x10005402, NUMICRO_BANKS_M051(16*1024)}, - {"M054ZBN" , 0x10005403, NUMICRO_BANKS_M051(16*1024)}, - {"M058LBN" , 0x10005800, NUMICRO_BANKS_M051(32*1024)}, - {"M058PBN" , 0x10005801, NUMICRO_BANKS_M051(32*1024)}, - {"M058YBN" , 0x10005802, NUMICRO_BANKS_M051(32*1024)}, - {"M058ZBN" , 0x10005803, NUMICRO_BANKS_M051(32*1024)}, - {"M0516LBN" , 0x10005A00, NUMICRO_BANKS_M051(64*1024)}, - {"M0516PBN" , 0x10005A01, NUMICRO_BANKS_M051(64*1024)}, - {"M0516YBN" , 0x10005A02, NUMICRO_BANKS_M051(64*1024)}, - {"M0516ZBN" , 0x10005A03, NUMICRO_BANKS_M051(64*1024)}, - {"M052LDN" , 0x20005200, NUMICRO_BANKS_M051(8*1024)}, - {"M054LDN" , 0x20005400, NUMICRO_BANKS_M051(16*1024)}, - {"M058LDN" , 0x20005800, NUMICRO_BANKS_M051(32*1024)}, - {"M0516LDN" , 0x20005A00, NUMICRO_BANKS_M051(64*1024)}, - {"M052ZDN" , 0x20005203, NUMICRO_BANKS_M051(8*1024)}, - {"M054ZDN" , 0x20005403, NUMICRO_BANKS_M051(16*1024)}, - {"M058ZDN" , 0x20005803, NUMICRO_BANKS_M051(32*1024)}, - {"M0516ZDN" , 0x20005A03, NUMICRO_BANKS_M051(64*1024)}, - {"M052TDN" , 0x20005204, NUMICRO_BANKS_M051(8*1024)}, - {"M054TDN" , 0x20005404, NUMICRO_BANKS_M051(16*1024)}, - {"M058TDN" , 0x20005804, NUMICRO_BANKS_M051(32*1024)}, - {"M0516TDN" , 0x20005A04, NUMICRO_BANKS_M051(64*1024)}, - {"M052XDN" , 0x20005205, NUMICRO_BANKS_M051(8*1024)}, - {"M054XDN" , 0x20005405, NUMICRO_BANKS_M051(16*1024)}, - {"M058XDN" , 0x20005805, NUMICRO_BANKS_M051(32*1024)}, - {"M0516XDN" , 0x20005A05, NUMICRO_BANKS_M051(64*1024)}, - {"M052LDE" , 0x30005200, NUMICRO_BANKS_M051(8*1024)}, - {"M054LDE" , 0x30005400, NUMICRO_BANKS_M051(16*1024)}, - {"M058LDE" , 0x30005800, NUMICRO_BANKS_M051(32*1024)}, - {"M0516LDE" , 0x30005A00, NUMICRO_BANKS_M051(64*1024)}, - {"M052ZDE" , 0x30005203, NUMICRO_BANKS_M051(8*1024)}, - {"M054ZDE" , 0x30005403, NUMICRO_BANKS_M051(16*1024)}, - {"M058ZDE" , 0x30005803, NUMICRO_BANKS_M051(32*1024)}, - {"M0516ZDE" , 0x30005A03, NUMICRO_BANKS_M051(64*1024)}, - {"M052TDE" , 0x30005204, NUMICRO_BANKS_M051(8*1024)}, - {"M054TDE" , 0x30005404, NUMICRO_BANKS_M051(16*1024)}, - {"M058TDE" , 0x30005804, NUMICRO_BANKS_M051(32*1024)}, - {"M0516TDE" , 0x30005A04, NUMICRO_BANKS_M051(64*1024)}, - {"M052XDE" , 0x30005205, NUMICRO_BANKS_M051(8*1024)}, - {"M054XDE" , 0x30005405, NUMICRO_BANKS_M051(16*1024)}, - {"M058XDE" , 0x30005805, NUMICRO_BANKS_M051(32*1024)}, - {"M0516XDE" , 0x30005A05, NUMICRO_BANKS_M051(64*1024)}, - - /* Mini51 */ - {"MINI51LAN", 0x00205100, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51QAN", 0x00205101, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51 ", 0x00205102, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51ZAN", 0x00205103, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51TAN", 0x00205104, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI52LAN", 0x00205200, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52QAN", 0x00205201, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52 ", 0x00205202, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52ZAN", 0x00205203, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52TAN", 0x00205204, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI54LAN", 0x00205400, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54QAN", 0x00205401, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54 ", 0x00205402, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54ZAN", 0x00205403, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54TAN", 0x00205404, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI51LBN", 0x10205100, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51QBN", 0x10205101, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51 ", 0x10205102, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51ZBN", 0x10205103, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51TBN", 0x10205104, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI52LBN", 0x10205200, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52QBN", 0x10205201, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52 ", 0x10205202, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52ZBN", 0x10205203, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52TBN", 0x10205204, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI54LBN", 0x10205400, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54QBN", 0x10205401, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54 ", 0x10205402, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54ZBN" , 0x10205403, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54TBN" , 0x10205404, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI51LDE" , 0x20205100, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51QDE" , 0x20205101, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51 " , 0x20205102, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51ZDE" , 0x20205103, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51TDE" , 0x20205104, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI51FDE" , 0x20205105, NUMICRO_BANKS_MINI51(4*1024)}, - {"MINI52LDE" , 0x20205200, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52QDE" , 0x20205201, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52 " , 0x20205202, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52ZDE" , 0x20205203, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52TDE" , 0x20205204, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI52FDE" , 0x20205205, NUMICRO_BANKS_MINI51(8*1024)}, - {"MINI54LDE" , 0x20205400, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54QDE" , 0x20205401, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54 " , 0x20205402, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54ZDE" , 0x20205403, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54TDE" , 0x20205404, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI54FDE" , 0x20205405, NUMICRO_BANKS_MINI51(16*1024)}, - {"MINI55LDE" , 0x20205500, NUMICRO_BANKS_MINI51(16*1024)}, - - /* NANO100 */ - {"NANO100VF3AN" , 0x00110000, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100VF2AN" , 0x00110001, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100RF3AN" , 0x00110002, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100RF2AN" , 0x00110003, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100LF3AN" , 0x00110004, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100LF2AN" , 0x00110005, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO100VE3AN" , 0x00110006, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100VE2AN" , 0x00110007, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100RE3AN" , 0x00110008, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100RE2AN" , 0x00110009, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100LE3AN" , 0x00110010, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100LE2AN" , 0x00110011, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100VD3AN" , 0x00110012, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100VD2AN" , 0x00110013, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100VD1AN" , 0x00110014, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100RD3AN" , 0x00110015, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100RD2AN" , 0x00110016, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100RD1AN" , 0x00110017, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100LD3AN" , 0x00110018, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100LD2AN" , 0x00110019, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100LD1AN" , 0x00110020, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100VC2AN" , 0x00110021, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100VC1AN" , 0x00110022, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100RC2AN" , 0x00110023, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100RC1AN" , 0x00110024, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100LC2AN" , 0x00110025, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100LC1AN" , 0x00110026, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100VB1AN" , 0x00110027, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO100VB0AN" , 0x00110028, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO100RB1AN" , 0x00110029, NUMICRO_BANKS_NANO(16*1024)}, - - {"NANO110VF3AN" , 0x00111000, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO110VF2AN" , 0x00111001, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO110RF3AN" , 0x00111002, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO110RF2AN" , 0x00111003, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO110VE3AN" , 0x00111006, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110VE2AN" , 0x00111007, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110RE3AN" , 0x00111008, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110RE2AN" , 0x00111009, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110VD3AN" , 0x00111012, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110VD2AN" , 0x00111013, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110VD1AN" , 0x00111014, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110RD3AN" , 0x00111015, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110RD2AN" , 0x00111016, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110RD1AN" , 0x00111017, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110VC2AN" , 0x00111021, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110VC1AN" , 0x00111022, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110SC2AN" , 0x00111023, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110SC1AN" , 0x00111024, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120VF3AN" , 0x00112000, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120VF2AN" , 0x00112001, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120RF3AN" , 0x00112002, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120RF2AN" , 0x00112003, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120LF3AN" , 0x00112004, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120LF2AN" , 0x00112005, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO120VE3AN" , 0x00112006, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120VE2AN" , 0x00112007, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120RE3AN" , 0x00112008, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120RE2AN" , 0x00112009, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120LE3AN" , 0x00112010, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120LE2AN" , 0x00112011, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120VD3AN" , 0x00112012, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120VD2AN" , 0x00112013, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120VD1AN" , 0x00112014, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120SD3AN" , 0x00112015, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120SD2AN" , 0x00112016, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120SD1AN" , 0x00112017, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120LD3AN" , 0x00112018, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120LD2AN" , 0x00112019, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120LD1AN" , 0x00112020, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120VC2AN" , 0x00112021, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120VC1AN" , 0x00112022, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120SC2AN" , 0x00112023, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120SC1AN" , 0x00112024, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120LC2AN" , 0x00112025, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120LC1AN" , 0x00112026, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130VF3AN" , 0x00113000, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO130VF2AN" , 0x00113001, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO130SF3AN" , 0x00113002, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO130SF2AN" , 0x00113003, NUMICRO_BANKS_NANO(256*1024)}, - {"NANO130VE3AN" , 0x00113006, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO130VE2AN" , 0x00113007, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO130SE3AN" , 0x00113008, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO130SE2AN" , 0x00113009, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO130VD3AN" , 0x00113012, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130VD2AN" , 0x00113013, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130VD1AN" , 0x00113014, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130SD3AN" , 0x00113015, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130SD2AN" , 0x00113016, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130SD1AN" , 0x00113017, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130VC2AN" , 0x00113021, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130VC1AN" , 0x00113022, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130SC2AN" , 0x00113023, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130SC1AN" , 0x00113024, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100KE3BN" , 0x00110030, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100KE2BN" , 0x00110031, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100VE3BN" , 0x00110032, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100VE2BN" , 0x00110033, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100SE3BN" , 0x00110034, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100SE2BN" , 0x00110035, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100LE3BN" , 0x00110036, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100LE2BN" , 0x00110037, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO100KD3BN" , 0x00110038, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100KD2BN" , 0x00110039, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100VD3BN" , 0x0011003A, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100VD2BN" , 0x0011003B, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100SD3BN" , 0x0011003C, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100SD2BN" , 0x0011003D, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100LD3BN" , 0x0011003E, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100LD2BN" , 0x0011003F, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO100KC2BN" , 0x00110040, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100VC2BN" , 0x00110041, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100SC2BN" , 0x00110042, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO100LC2BN" , 0x00110043, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110KE3BN" , 0x00111030, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110KE2BN" , 0x00111031, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110VE3BN" , 0x00111032, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110VE2BN" , 0x00111033, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110SE3BN" , 0x00111034, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110SE2BN" , 0x00111035, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110KD3BN" , 0x00111038, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110KD2BN" , 0x00111039, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110VD3BN" , 0x0011103A, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110VD2BN" , 0x0011103B, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110SD3BN" , 0x0011103C, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110SD2BN" , 0x0011103D, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO110KC2BN" , 0x00111040, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110VC2BN" , 0x00111041, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110SC2BN" , 0x00111042, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120KE3BN" , 0x00112030, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120KE2BN" , 0x00112031, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120VE3BN" , 0x00112032, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120VE2BN" , 0x00112033, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120SE3BN" , 0x00112034, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120SE2BN" , 0x00112035, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120LE3BN" , 0x00112036, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120LE2BN" , 0x00112037, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO120KD3BN" , 0x00112038, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120KD2BN" , 0x00112039, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120VD3BN" , 0x0011203A, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120VD2BN" , 0x0011203B, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120SD3BN" , 0x0011203C, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120SD2BN" , 0x0011203D, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120LD3BN" , 0x0011203E, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120LD2BN" , 0x0011203F, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO120KC2BN" , 0x00112040, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120VC2BN" , 0x00112041, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120SC2BN" , 0x00112042, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO120LC2BN" , 0x00112043, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130KE3BN" , 0x00113030, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130KE2BN" , 0x00113031, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130VE3BN" , 0x00113032, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130VE2BN" , 0x00113033, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130SE3BN" , 0x00113034, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130SE2BN" , 0x00113035, NUMICRO_BANKS_NANO(123*1024)}, - {"NANO130KD3BN" , 0x00113038, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130KD2BN" , 0x00113039, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130VD3BN" , 0x0011303A, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130VD2BN" , 0x0011303B, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130SD3BN" , 0x0011303C, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130SD2BN" , 0x0011303D, NUMICRO_BANKS_NANO(64*1024)}, - {"NANO130KC2BN" , 0x00113040, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130VC2BN" , 0x00113041, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO130SC2BN" , 0x00113042, NUMICRO_BANKS_NANO(32*1024)}, - {"N512DC4" , 0x00100000, NUMICRO_BANKS_NANO(64*1024)}, - {"N512LC4" , 0x00100001, NUMICRO_BANKS_NANO(64*1024)}, - {"N512MC4" , 0x00100003, NUMICRO_BANKS_NANO(64*1024)}, - - {"N512SC4" , 0x00100005, NUMICRO_BANKS_NANO(64*1024)}, - {"N512VD4" , 0x00100008, NUMICRO_BANKS_NANO(128*1024)}, - {"N512MD4" , 0x00100009, NUMICRO_BANKS_NANO(128*1024)}, - {"N512SD4" , 0x00100010, NUMICRO_BANKS_NANO(128*1024)}, - {"NANO110RC2BN" , 0x00111043, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO110RD3BN" , 0x00111045, NUMICRO_BANKS_NANO(64*1024)}, - {"TX110VE3BN" , 0x00111036, NUMICRO_BANKS_NANO(128*1024)}, - - /* NANO102/NANO112 */ - {"NANO112LB0AN" , 0x00111201, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112LB1AN" , 0x00111202, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112LC1AN" , 0x00111203, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112LC2AN" , 0x00111204, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112SB0AN" , 0x00111205, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112SB1AN" , 0x00111206, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112SC1AN" , 0x00111207, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112SC2AN" , 0x00111208, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112RB0AN" , 0x00111209, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112RB1AN" , 0x00111210, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112RC1AN" , 0x00111211, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112RC2AN" , 0x00111212, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112VB0AN" , 0x00111213, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112VB1AN" , 0x00111214, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO112VC1AN" , 0x00111215, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO112VC2AN" , 0x00111216, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102ZB0AN" , 0x00110201, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102ZB1AN" , 0x00110202, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102ZC1AN" , 0x00110203, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102ZC2AN" , 0x00110204, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102LB0AN" , 0x00110205, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102LB1AN" , 0x00110206, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102LC1AN" , 0x00110207, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102LC2AN" , 0x00110208, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102SB0AN" , 0x00110209, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102SB1AN" , 0x00110210, NUMICRO_BANKS_NANO(16*1024)}, - {"NANO102SC1AN" , 0x00110211, NUMICRO_BANKS_NANO(32*1024)}, - {"NANO102SC2AN" , 0x00110212, NUMICRO_BANKS_NANO(32*1024)}, - - /* NUC103/NUC105/NUC123 */ - {"NUC123SC2AN" , 0x00012305, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC123SD4AN" , 0x00012315, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC123LC2AN" , 0x00012325, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC103LC2AN" , 0x00010325, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC105LC2AN" , 0x00010525, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC123LD4AN" , 0x00012335, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC103LD4AN" , 0x00010335, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC105LD4AN" , 0x00010535, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC123ZC2AN" , 0x00012345, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC103ZC2AN" , 0x00010345, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC105ZC2AN" , 0x00010545, NUMICRO_BANKS_NUC100(36*1024)}, - {"NUC123ZD4AN" , 0x00012355, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC103ZD4AN" , 0x00010355, NUMICRO_BANKS_NUC100(68*1024)}, - {"NUC105ZD4AN" , 0x00010555, NUMICRO_BANKS_NUC100(68*1024)}, - - /* NUC200 */ - {"NUC200LC2AN" , 0x00020007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC200LD2AN" , 0x00020004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC200LE3AN" , 0x00020000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC200SC1AN" , 0x00020035, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC200SD2AN" , 0x00020031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC200SE3AN" , 0x00020027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC200VE3AN" , 0x00020018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC220LC2AN" , 0x00022007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC220LD2AN" , 0x00022004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC220LE3AN" , 0x00022000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC220SC1AN" , 0x00022035, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC220SD2AN" , 0x00022031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC220SE3AN" , 0x00022027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC220VE3AN" , 0x00022018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230LC2AN" , 0x00023007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC230LD2AN" , 0x00023004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC230LE3AN" , 0x00023000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230SC1AN" , 0x00023035, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC230SD2AN" , 0x00023031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC230SE3AN" , 0x00023027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230VE3AN" , 0x00023018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240LC2AN" , 0x00024007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC240LD2AN" , 0x00024004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC240LE3AN" , 0x00024000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240SC1AN" , 0x00024035, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC240SD2AN" , 0x00024031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC240SE3AN" , 0x00024027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240VE3AN" , 0x00024018, NUMICRO_BANKS_NUC100(128*1024)}, - - /* NUC200 NUC2XXAE */ - {"NUC230RC1AE" , 0x40013017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC200LC2AE" , 0x10020007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC200LD2AE" , 0x10020004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC200LE3AE" , 0x10020000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC200SC2AE" , 0x10020034, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC200SD2AE" , 0x10020031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC200SE3AE" , 0x10020027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC200VE3AE" , 0x10020018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230LC2AE" , 0x10023007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC230LD2AE" , 0x10023004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC230LE3AE" , 0x10023000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230SC2AE" , 0x10023034, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC230SD2AE" , 0x10023031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC230SE3AE" , 0x10023027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC230VE3AE" , 0x10023018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240LC2AE" , 0x10024007, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC240LD2AE" , 0x10024004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC240LE3AE" , 0x10024000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240SC2AE" , 0x10024034, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC240SD2AE" , 0x10024031, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC240SE3AE" , 0x10024027, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC240VE3AE" , 0x10024018, NUMICRO_BANKS_NUC100(128*1024)}, - - /* NUC100 Version D */ - {"NUC100LC1DN" , 0x30010008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100LD1DN" , 0x30010005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD2DN" , 0x30010004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RC1DN" , 0x30010017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC100RD1DN" , 0x30010014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RD2DN" , 0x30010013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LD3DN" , 0x30010003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100LE3DN" , 0x30010000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100RD3DN" , 0x30010012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100RE3DN" , 0x30010009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC100VD2DN" , 0x30010022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VD3DN" , 0x30010021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC100VE3DN" , 0x30010018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120LC1DN" , 0x30012008, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120LD1DN" , 0x30012005, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD2DN" , 0x30012004, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RC1DN" , 0x30012017, NUMICRO_BANKS_NUC100(32*1024)}, - {"NUC120RD1DN" , 0x30012014, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RD2DN" , 0x30012013, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LD3DN" , 0x30012003, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120LE3DN" , 0x30012000, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120RD3DN" , 0x30012012, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120RE3DN" , 0x30012009, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC120VD2DN" , 0x30012022, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VD3DN" , 0x30012021, NUMICRO_BANKS_NUC100(64*1024)}, - {"NUC120VE3DN" , 0x30012018, NUMICRO_BANKS_NUC100(128*1024)}, - {"NUC130RC1DN" , 0x30013017, NUMICRO_BANKS_NUC100(32*1024)}, - - {"UNKNOWN" , 0x00000000, NUMICRO_BANKS_NUC100(128*1024)}, + /* M051AN */ + {"M052LAN", 0x00005200, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054LAN", 0x00005400, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058LAN", 0x00005800, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516LAN", 0x00005A00, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052ZAN", 0x00005203, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054ZAN", 0x00005403, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058ZAN", 0x00005803, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516ZAN", 0x00005A03, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + + /* M051BN */ + {"M052LBN", 0x10005200, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054LBN", 0x10005400, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058LBN", 0x10005800, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516LBN", 0x10005A00, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052ZBN", 0x10005203, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054ZBN", 0x10005403, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058ZBN", 0x10005803, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516ZBN", 0x10005A03, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + + /* M051DN */ + {"M0516LDN", 0x20005A00, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516ZDN", 0x20005A03, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052LDN", 0x20005200, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052ZDN", 0x20005203, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054LDN", 0x20005400, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054ZDN", 0x20005403, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058LDN", 0x20005800, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058ZDN", 0x20005803, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + + /* M051DE */ + {"M0516LDE", 0x30005A00, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M0516ZDE", 0x30005A03, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052LDE", 0x30005200, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M052ZDE", 0x30005203, NUMICRO_BANKS_GENERAL(8 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054LDE", 0x30005400, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M054ZDE", 0x30005403, NUMICRO_BANKS_GENERAL(16 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058LDE", 0x30005800, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"M058ZDE", 0x30005803, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + + /* M0518 */ + {"M0518LC2AE", 0x10051803, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M0518LD2AE", 0x10051800, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M0518SC2AE", 0x10051813, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M0518SD2AE", 0x10051810, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* M0519 */ + {"M0519LD3AE", 0x00051902, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"M0519LE3AE", 0x00051900, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"M0519SD3AE", 0x00051922, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"M0519SE3AE", 0x00051920, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"M0519VE3AE", 0x00051930, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + + /* M058S */ + {"M058SFAN", 0x00005818, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M058SLAN", 0x00005810, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M058SSAN", 0x00005816, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"M058SZAN", 0x00005813, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* MINI51AN */ + {"MINI51LAN", 0x00205100, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI51TAN", 0x00205104, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI51ZAN", 0x00205103, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52LAN", 0x00205200, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52TAN", 0x00205204, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52ZAN", 0x00205203, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54LAN", 0x00205400, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54TAN", 0x00205404, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54ZAN", 0x00205403, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + + /* MINI51DE */ + {"MINI51FDE", 0x20205105, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI51LDE", 0x20205100, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI51TDE", 0x20205104, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI51ZDE", 0x20205103, NUMICRO_BANKS_GENERAL(4 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52FDE", 0x20205205, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52LDE", 0x20205200, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52TDE", 0x20205204, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI52ZDE", 0x20205203, NUMICRO_BANKS_GENERAL(8 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54FDE", 0x20205405, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54LDE", 0x20205400, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54TDE", 0x20205404, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + {"MINI54ZDE", 0x20205403, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + + /* MINI55 */ + {"MINI55LDE", 0x00505500, NUMICRO_BANKS_GENERAL(35 * 512, 0 * 1024, 2 * 1024, 8)}, + {"MINI55ZDE", 0x00505503, NUMICRO_BANKS_GENERAL(35 * 512, 0 * 1024, 2 * 1024, 8)}, + + /* MINI58 */ + {"MINI58FDE", 0x00A05805, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 5 * 512, 8)}, + {"MINI58LDE", 0x00A05800, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 5 * 512, 8)}, + {"MINI58TDE", 0x00A05804, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 5 * 512, 8)}, + {"MINI58ZDE", 0x00A05803, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 5 * 512, 8)}, + + /* NANO100AN */ + {"NANO100LC2AN", 0x00110025, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LD2AN", 0x00110019, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LD3AN", 0x00110018, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SC2AN", 0x00110023, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SD2AN", 0x00110016, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SD3AN", 0x00110015, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100VD2AN", 0x00110013, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100VD3AN", 0x00110012, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100ZC2AN", 0x00110029, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100ZD2AN", 0x00110028, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100ZD3AN", 0x00110027, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LC2AN", 0x00112025, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LD2AN", 0x00112019, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LD3AN", 0x00112018, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SC2AN", 0x00112023, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SD2AN", 0x00112016, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SD3AN", 0x00112015, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120VD2AN", 0x00112013, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120VD3AN", 0x00112012, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120ZC2AN", 0x00112029, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120ZD2AN", 0x00112028, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120ZD3AN", 0x00112027, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NANO100BN */ + {"NANO100KC2BN", 0x00110040, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100KD2BN", 0x00110039, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100KD3BN", 0x00110038, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100KE3BN", 0x00110030, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LC2BN", 0x00110043, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LD2BN", 0x0011003F, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LD3BN", 0x0011003E, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100LE3BN", 0x00110036, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100ND2BN", 0x00110046, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100ND3BN", 0x00110045, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100NE3BN", 0x00110044, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SC2BN", 0x00110042, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SD2BN", 0x0011003D, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SD3BN", 0x0011003C, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO100SE3BN", 0x00110034, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110KC2BN", 0x00111040, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110KD2BN", 0x00111039, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110KD3BN", 0x00111038, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110KE3BN", 0x00111030, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110RC2BN", 0x00111043, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110RD2BN", 0x00111044, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110RD3BN", 0x00111045, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110SC2BN", 0x00111042, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110SD2BN", 0x0011103D, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110SD3BN", 0x0011103C, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO110SE3BN", 0x00111034, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120KC2BN", 0x00112040, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120KD2BN", 0x00112039, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120KD3BN", 0x00112038, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120KE3BN", 0x00112030, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LC2BN", 0x00112043, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LD2BN", 0x0011203F, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LD3BN", 0x0011203E, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120LE3BN", 0x00112036, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SC2BN", 0x00112042, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SD2BN", 0x0011203D, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SD3BN", 0x0011203C, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO120SE3BN", 0x00112034, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130KC2BN", 0x00113040, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130KD2BN", 0x00113039, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130KD3BN", 0x00113038, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130KE3BN", 0x00113030, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130SC2BN", 0x00113042, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130SD2BN", 0x0011303D, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130SD3BN", 0x0011303C, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO130SE3BN", 0x00113034, NUMICRO_BANKS_GENERAL(123 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NANO103 */ + {"NANO103SD3AE", 0x00110301, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO103LD3AE", 0x00110304, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO103ZD3AE", 0x00110307, NUMICRO_BANKS_GENERAL(64 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NANO112AN */ + {"NANO102LB1AN", 0x00110206, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO102LC2AN", 0x00110208, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO102SC2AN", 0x00110212, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO102ZB1AN", 0x00110202, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO102ZC2AN", 0x00110204, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112LB1AN", 0x00111202, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112LC2AN", 0x00111204, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112RB1AN", 0x00111210, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112RC2AN", 0x00111212, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112SB1AN", 0x00111206, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112SC2AN", 0x00111208, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NANO112VC2AN", 0x00111216, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC029AN */ + {"NUC029LAN", 0x00295A00, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 4)}, + {"NUC029TAN", 0x00295804, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 4)}, + + /* NUC029AE */ + {"NUC029FAE", 0x00295415, NUMICRO_BANKS_GENERAL(16 * 1024, 0 * 1024, 2 * 1024, 8)}, + + /* NUC100AN */ + {"NUC100LD3AN", 0x00010003, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LE3AN", 0x00010000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC100RD3AN", 0x00010012, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RE3AN", 0x00010009, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC100VD2AN", 0x00010022, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100VD3AN", 0x00010021, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100VE3AN", 0x00100018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120LD3AN", 0x00012003, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LE3AN", 0x00120000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120RD3AN", 0x00012012, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RE3AN", 0x00012009, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120VD2AN", 0x00012022, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120VD3AN", 0x00012021, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120VE3AN", 0x00012018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC100BN */ + {"NUC100LC1BN", 0x10010008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LD1BN", 0x10010005, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LD2BN", 0x10010004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RC1BN", 0x10010017, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RD1BN", 0x10010014, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RD2BN", 0x10010013, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LC1BN", 0x10012008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LD1BN", 0x10012005, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LD2BN", 0x10012004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RC1BN", 0x10012017, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RD1BN", 0x10012014, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RD2BN", 0x10012013, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* NUC100CN */ + {"NUC130LC1CN", 0x20013008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC130LD2CN", 0x20013004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC130LE3CN", 0x20013000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC130RC1CN", 0x20013017, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC130RD2CN", 0x20013013, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC130RE3CN", 0x20013009, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC130VE3CN", 0x20013018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC140LC1CN", 0x20014008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC140LD2CN", 0x20014004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC140LE3CN", 0x20014000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC140RC1CN", 0x20014017, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC140RD2CN", 0x20014013, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC140RE3CN", 0x20014009, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC140VE3CN", 0x20014018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC100DN */ + {"NUC100LC1DN", 0x30010008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LD1DN", 0x30010005, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LD2DN", 0x30010004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LD3DN", 0x30010003, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100LE3DN", 0x30010000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC100RC1DN", 0x30010017, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RD1DN", 0x30010014, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RD2DN", 0x30010013, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RD3DN", 0x30010012, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100RE3DN", 0x30010009, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC100VD2DN", 0x30010022, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100VD3DN", 0x30010021, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC100VE3DN", 0x30010018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120LC1DN", 0x30012008, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LD1DN", 0x30012005, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LD2DN", 0x30012004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LD3DN", 0x30012003, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120LE3DN", 0x30012000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120RC1DN", 0x30012035, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RD1DN", 0x30012032, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RD2DN", 0x30012031, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RD3DN", 0x30012030, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120RE3DN", 0x30012027, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC120VD2DN", 0x30012022, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120VD3DN", 0x30012021, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC120VE3DN", 0x30012018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC121 */ + {"NUC121SC2AE", 0x00012105, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + {"NUC121LC2AE", 0x00012125, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + {"NUC121ZC2AE", 0x00012145, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + {"NUC125SC2AE", 0x00012505, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + {"NUC125LC2AE", 0x00012525, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + {"NUC125ZC2AE", 0x00012545, NUMICRO_BANKS_GENERAL(32 * 1024, 0 * 1024, 9 * 512, 8)}, + + /* NUC122 */ + {"NUC122LC1AN", 0x00012208, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC122LD2AN", 0x00012204, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC122SC1AN", 0x00012226, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC122SD2AN", 0x00012222, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC122ZC1AN", 0x00012235, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC122ZD2AN", 0x00012231, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* NUC123AN */ + {"NUC123LC2AN1", 0x00012325, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123LD4AN0", 0x00012335, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123SC2AN1", 0x00012305, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123SD4AN0", 0x00012315, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123ZC2AN1", 0x00012345, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123ZD4AN0", 0x00012355, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* NUC123AE */ + {"NUC123LC2AE1", 0x10012325, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123LD4AE0", 0x10012335, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123SC2AE1", 0x10012305, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123SD4AE0", 0x10012315, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123ZC2AE1", 0x10012345, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC123ZD4AE0", 0x10012355, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* NUC131AE */ + {"NUC131LC2AE", 0x10013103, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC131LD2AE", 0x10013100, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC131SC2AE", 0x10013113, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC131SD2AE", 0x10013110, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + + /* NUC200/220AN */ + {"NUC200LC2AN", 0x00020007, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC200LD2AN", 0x00020004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC200LE3AN", 0x00020000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC200SC2AN", 0x00020034, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC200SD2AN", 0x00020031, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC200SE3AN", 0x00020027, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC200VE3AN", 0x00020018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC220LC2AN", 0x00022007, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC220LD2AN", 0x00022004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC220LE3AN", 0x00022000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC220SC2AN", 0x00022034, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC220SD2AN", 0x00022031, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 4 * 1024, 8)}, + {"NUC220SE3AN", 0x00022027, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"NUC220VE3AN", 0x00022018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC230/240AE */ + {"NUC230LC2AE", 0x10023007, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC230LD2AE", 0x10023004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC230LE3AE", 0x10023000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"NUC230SC2AE", 0x10023034, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC230SD2AE", 0x10023031, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC230SE3AE", 0x10023027, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"NUC230VE3AE", 0x10023018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"NUC240LC2AE", 0x10024007, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC240LD2AE", 0x10024004, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC240LE3AE", 0x10024000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"NUC240SC2AE", 0x10024034, NUMICRO_BANKS_GENERAL(32 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC240SD2AE", 0x10024031, NUMICRO_BANKS_GENERAL(64 * 1024, 4 * 1024, 8 * 1024, 8)}, + {"NUC240SE3AE", 0x10024027, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + {"NUC240VE3AE", 0x10024018, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 8 * 1024, 8)}, + + /* M451 */ + {"M451LC3AE", 0x00945101, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451LD3AE", 0x00945100, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451LE6AE", 0x00845101, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451LG6AE", 0x00845100, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MLC3AE", 0x00945001, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MLD3AE", 0x00945000, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MLE6AE", 0x00845001, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MLG6AE", 0x00845000, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MSC3AE", 0x00945011, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451MSD3AE", 0x00945010, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451RC3AE", 0x00945121, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451RD3AE", 0x00945120, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451RE6AE", 0x00845121, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451RG6AE", 0x00845120, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451VE6AE", 0x00845131, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M451VG6AE", 0x00845130, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452LC3AE", 0x00945201, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452LD3AE", 0x00945200, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452LE6AE", 0x00845201, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452LG6AE", 0x00845200, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452RD3AE", 0x00945220, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452RE6AE", 0x00845221, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M452RG6AE", 0x00845220, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453LC3AE", 0x00945301, NUMICRO_BANKS_GENERAL(40 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453LD3AE", 0x00945300, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453LE6AE", 0x00845301, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453LG6AE", 0x00845300, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453RD3AE", 0x00945320, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453RE6AE", 0x00845321, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453RG6AE", 0x00845320, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453VD3AE", 0x00945330, NUMICRO_BANKS_GENERAL(72 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453VE6AE", 0x00845331, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M453VG6AE", 0x00845330, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKVG6AE", 0x00845430, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKVE6AE", 0x00845431, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKRG6AE", 0x00845420, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKRE6AE", 0x00845421, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKLG6AE", 0x00845400, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 4 * 1024, 8)}, + {"M4TKLE6AE", 0x00845401, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 4 * 1024, 8)}, + + /* NUC442_472 */ + {"NUC442JG8AE", 0x00044203, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442JI8AE", 0x00044201, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442KG8AE", 0x00044206, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442KI8AE", 0x00044204, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442RG8AE", 0x00044212, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442RI8AE", 0x00044210, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442VG8AE", 0x00044209, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC442VI8AE", 0x00044207, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472HG8AE", 0x00047203, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472HI8AE", 0x00047201, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472JG8AE", 0x00047206, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472JI8AE", 0x00047204, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472KG8AE", 0x00047209, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472KI8AE", 0x00047207, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472VG8AE", 0x00047212, NUMICRO_BANKS_GENERAL(256 * 1024, 0 * 1024, 16 * 1024, 16)}, + {"NUC472VI8AE", 0x00047210, NUMICRO_BANKS_GENERAL(512 * 1024, 0 * 1024, 16 * 1024, 16)}, + + {"UNKNOWN", 0x00000000, NUMICRO_BANKS_GENERAL(128 * 1024, 0 * 1024, 16 * 1024, 8)}, }; /* Private bank information for NuMicro. */ @@ -1125,32 +535,53 @@ struct numicro_flash_bank { const struct numicro_cpu_type *cpu; }; +/* Private variables */ +static uint32_t m_page_size = NUMICRO_PAGESIZE; +static uint32_t m_address_bias_offset; + /* Private methods */ +static int numicro_get_arm_arch(struct target *target) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + + if (armv7m->arm.arch != ARM_ARCH_V6M) { + LOG_DEBUG("NuMicro arm architecture: armv7m\n"); + m_page_size = NUMICRO_PAGESIZE * 4; + m_address_bias_offset = 0x10000000; + } else { + LOG_DEBUG("NuMicro arm architecture: armv6m\n"); + m_page_size = NUMICRO_PAGESIZE; + m_address_bias_offset = 0x0; + } + + return ERROR_OK; +} + static int numicro_reg_unlock(struct target *target) { uint32_t is_protected; int retval = ERROR_OK; /* Check to see if NUC is register unlocked or not */ - retval = target_read_u32(target, NUMICRO_SYS_WRPROT, &is_protected); + retval = target_read_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, &is_protected); if (retval != ERROR_OK) return retval; LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected); if (is_protected == 0) { /* means protected - so unlock it */ /* unlock flash registers */ - retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY1); + retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY1); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY2); + retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY2); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY3); + retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY3); if (retval != ERROR_OK) return retval; } /* Check that unlock worked */ - retval = target_read_u32(target, NUMICRO_SYS_WRPROT, &is_protected); + retval = target_read_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, &is_protected); if (retval != ERROR_OK) return retval; @@ -1178,27 +609,27 @@ static int numicro_init_isp(struct target *target) return retval; /* Enable ISP/SRAM/TICK Clock */ - retval = target_read_u32(target, NUMICRO_SYSCLK_AHBCLK, ®_stat); + retval = target_read_u32(target, NUMICRO_SYSCLK_AHBCLK - m_address_bias_offset, ®_stat); if (retval != ERROR_OK) return retval; reg_stat |= AHBCLK_ISP_EN | AHBCLK_SRAM_EN | AHBCLK_TICK_EN; - retval = target_write_u32(target, NUMICRO_SYSCLK_AHBCLK, reg_stat); + retval = target_write_u32(target, NUMICRO_SYSCLK_AHBCLK - m_address_bias_offset, reg_stat); if (retval != ERROR_OK) return retval; /* Enable ISP */ - retval = target_read_u32(target, NUMICRO_FLASH_ISPCON, ®_stat); + retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, ®_stat); if (retval != ERROR_OK) return retval; reg_stat |= ISPCON_ISPFF | ISPCON_LDUEN | ISPCON_APUEN | ISPCON_CFGUEN | ISPCON_ISPEN; - retval = target_write_u32(target, NUMICRO_FLASH_ISPCON, reg_stat); + retval = target_write_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, reg_stat); if (retval != ERROR_OK) return retval; /* Write one to undocumented flash control register */ - retval = target_write_u32(target, NUMICRO_FLASH_CHEAT, 1); + retval = target_write_u32(target, NUMICRO_FLASH_CHEAT - m_address_bias_offset, 1); if (retval != ERROR_OK) return retval; @@ -1210,29 +641,28 @@ static uint32_t numicro_fmc_cmd(struct target *target, uint32_t cmd, uint32_t ad uint32_t timeout, status; int retval = ERROR_OK; - retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD, cmd); + retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD - m_address_bias_offset, cmd); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPDAT, wdata); + retval = target_write_u32(target, NUMICRO_FLASH_ISPDAT - m_address_bias_offset, wdata); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, addr); + retval = target_write_u32(target, NUMICRO_FLASH_ISPADR - m_address_bias_offset, addr); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG, ISPTRG_ISPGO); + retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG - m_address_bias_offset, ISPTRG_ISPGO); if (retval != ERROR_OK) return retval; /* Wait for busy to clear - check the GO flag */ timeout = 100; for (;;) { - retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status); + retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG - m_address_bias_offset, &status); if (retval != ERROR_OK) return retval; - LOG_DEBUG("status: 0x%" PRIx32 "", status); if ((status & (ISPTRG_ISPGO)) == 0) break; if (timeout-- <= 0) { @@ -1242,79 +672,28 @@ static uint32_t numicro_fmc_cmd(struct target *target, uint32_t cmd, uint32_t ad busy_sleep(1); /* can use busy sleep for short times. */ } - retval = target_read_u32(target, NUMICRO_FLASH_ISPDAT, rdata); + retval = target_read_u32(target, NUMICRO_FLASH_ISPDAT - m_address_bias_offset, rdata); if (retval != ERROR_OK) return retval; return ERROR_OK; } - /* NuMicro Program-LongWord Microcodes */ static const uint8_t numicro_flash_write_code[] = { - /* Params: - * r0 - workarea buffer / result - * r1 - target address - * r2 - wordcount - * Clobbered: - * r4 - tmp - * r5 - tmp - * r6 - tmp - * r7 - tmp - */ - - /* .L1: */ - /* for(register uint32_t i=0;i<wcount;i++){ */ - 0x04, 0x1C, /* mov r4, r0 */ - 0x00, 0x23, /* mov r3, #0 */ - /* .L2: */ - 0x0D, 0x1A, /* sub r5, r1, r0 */ - 0x67, 0x19, /* add r7, r4, r7 */ - 0x93, 0x42, /* cmp r3, r2 */ - 0x0C, 0xD0, /* beq .L7 */ - /* .L4: */ - /* NUMICRO_FLASH_ISPADR = faddr; */ - 0x08, 0x4E, /* ldr r6, .L8 */ - 0x37, 0x60, /* str r7, [r6] */ - /* NUMICRO_FLASH_ISPDAT = *pLW; */ - 0x80, 0xCC, /* ldmia r4!, {r7} */ - 0x08, 0x4D, /* ldr r5, .L8+4 */ - 0x2F, 0x60, /* str r7, [r5] */ - /* faddr += 4; */ - /* pLW++; */ - /* Trigger write action */ - /* NUMICRO_FLASH_ISPTRG = ISPTRG_ISPGO; */ - 0x08, 0x4D, /* ldr r5, .L8+8 */ - 0x01, 0x26, /* mov r6, #1 */ - 0x2E, 0x60, /* str r6, [r5] */ - /* .L3: */ - /* while((NUMICRO_FLASH_ISPTRG & ISPTRG_ISPGO) == ISPTRG_ISPGO){}; */ - 0x2F, 0x68, /* ldr r7, [r5] */ - 0xFF, 0x07, /* lsl r7, r7, #31 */ - 0xFC, 0xD4, /* bmi .L3 */ - - 0x01, 0x33, /* add r3, r3, #1 */ - 0xEE, 0xE7, /* b .L2 */ - /* .L7: */ - /* return (NUMICRO_FLASH_ISPCON & ISPCON_ISPFF); */ - 0x05, 0x4B, /* ldr r3, .L8+12 */ - 0x18, 0x68, /* ldr r0, [r3] */ - 0x40, 0x21, /* mov r1, #64 */ - 0x08, 0x40, /* and r0, r1 */ - /* .L9: */ - 0x00, 0xBE, /* bkpt #0 */ - /* .L8: */ - 0x04, 0xC0, 0x00, 0x50,/* .word 1342226436 */ - 0x08, 0xC0, 0x00, 0x50,/* .word 1342226440 */ - 0x10, 0xC0, 0x00, 0x50,/* .word 1342226448 */ - 0x00, 0xC0, 0x00, 0x50 /* .word 1342226432 */ +#include "../../../contrib/loaders/flash/numicro/numicro_m0.inc" }; + +static const uint8_t numicro_m4_flash_write_code[] = { +#include "../../../contrib/loaders/flash/numicro/numicro_m4.inc" +}; + /* Program LongWord Block Write */ static int numicro_writeblock(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { struct target *target = bank->target; - uint32_t buffer_size = 1024; /* Default minimum value */ + uint32_t buffer_size = 1024; /* Default minimum value */ struct working_area *write_algorithm; struct working_area *source; uint32_t address = bank->base + offset; @@ -1342,18 +721,34 @@ static int numicro_writeblock(struct flash_bank *bank, const uint8_t *buffer, LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset); return ERROR_FLASH_DST_BREAKS_ALIGNMENT; } + /* Difference between M0 and M4 */ + if (m_page_size == NUMICRO_PAGESIZE) { + /* allocate working area with flash programming code */ + if (target_alloc_working_area(target, sizeof(numicro_flash_write_code), + &write_algorithm) != ERROR_OK) { + LOG_WARNING("no working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - /* allocate working area with flash programming code */ - if (target_alloc_working_area(target, sizeof(numicro_flash_write_code), + retval = target_write_buffer(target, write_algorithm->address, + sizeof(numicro_flash_write_code), numicro_flash_write_code); + if (retval != ERROR_OK) + return retval; + } else { /* for M4 */ + /* allocate working area with flash programming code */ + if (target_alloc_working_area(target, sizeof(numicro_m4_flash_write_code), &write_algorithm) != ERROR_OK) { - LOG_WARNING("no working area available, can't do block memory writes"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + LOG_WARNING("no working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - retval = target_write_buffer(target, write_algorithm->address, - sizeof(numicro_flash_write_code), numicro_flash_write_code); - if (retval != ERROR_OK) - return retval; + retval = target_write_buffer(target, write_algorithm->address, + sizeof(numicro_m4_flash_write_code), numicro_m4_flash_write_code); + if (retval != ERROR_OK) + return retval; + + buffer_size = m_page_size; + } /* memory buffer */ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) { @@ -1424,13 +819,14 @@ static int numicro_protect_check(struct flash_bank *bank) LOG_INFO("Nuvoton NuMicro: Flash Lock Check..."); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; /* Read CONFIG0,CONFIG1 */ - numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0, 0 , &config[0]); - numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1, 0 , &config[1]); + numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0 - m_address_bias_offset, 0, &config[0]); + numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1 - m_address_bias_offset, 0, &config[1]); LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]); @@ -1470,31 +866,34 @@ static int numicro_erase(struct flash_bank *bank, unsigned int first, LOG_INFO("Nuvoton NuMicro: Sector Erase ... (%u to %u)", first, last); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD, ISPCMD_ERASE); + retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD - m_address_bias_offset, ISPCMD_ERASE); if (retval != ERROR_OK) return retval; for (unsigned int i = first; i <= last; i++) { - LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, - bank->base + bank->sectors[i].offset); - retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + bank->sectors[i].offset); + LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, bank->base + bank->sectors[i].offset); + retval = target_write_u32(target, + NUMICRO_FLASH_ISPADR - m_address_bias_offset, + bank->base + bank->sectors[i].offset); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG, ISPTRG_ISPGO); /* This is the only bit available */ + retval = target_write_u32(target, + NUMICRO_FLASH_ISPTRG - m_address_bias_offset, + ISPTRG_ISPGO); /* This is the only bit available */ if (retval != ERROR_OK) return retval; /* wait for busy to clear - check the GO flag */ timeout = 100; for (;;) { - retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status); + retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG - m_address_bias_offset, &status); if (retval != ERROR_OK) return retval; - LOG_DEBUG("status: 0x%" PRIx32 "", status); if (status == 0) break; if (timeout-- <= 0) { @@ -1505,13 +904,13 @@ static int numicro_erase(struct flash_bank *bank, unsigned int first, } /* check for failure */ - retval = target_read_u32(target, NUMICRO_FLASH_ISPCON, &status); + retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, &status); if (retval != ERROR_OK) return retval; if ((status & ISPCON_ISPFF) != 0) { LOG_DEBUG("failure: 0x%" PRIx32 "", status); /* if bit is set, then must write to it to clear it. */ - retval = target_write_u32(target, NUMICRO_FLASH_ISPCON, (status | ISPCON_ISPFF)); + retval = target_write_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, (status | ISPCON_ISPFF)); if (retval != ERROR_OK) return retval; } @@ -1538,11 +937,12 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer, LOG_INFO("Nuvoton NuMicro: Flash Write ..."); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD, ISPCMD_WRITE); + retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD - m_address_bias_offset, ISPCMD_WRITE); if (retval != ERROR_OK) return retval; @@ -1562,26 +962,34 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer, /* program command */ for (uint32_t i = 0; i < count; i += 4) { + /* write 4 bytes each time with 0xff padding to avoid unaligned case */ + uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff}; + memcpy(padding, buffer + i, MIN(4, count - i)); - LOG_DEBUG("write longword @ %08" PRIX32, offset + i); - - retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + offset + i); + retval = target_write_u32(target, + NUMICRO_FLASH_ISPADR - m_address_bias_offset, + bank->base + offset + i); if (retval != ERROR_OK) return retval; - retval = target_write_memory(target, NUMICRO_FLASH_ISPDAT, 4, 1, buffer + i); + retval = target_write_memory(target, + NUMICRO_FLASH_ISPDAT - m_address_bias_offset, + 4, 1, padding); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG, ISPTRG_ISPGO); + retval = target_write_u32(target, + NUMICRO_FLASH_ISPTRG - m_address_bias_offset, + ISPTRG_ISPGO); if (retval != ERROR_OK) return retval; /* wait for busy to clear - check the GO flag */ timeout = 100; for (;;) { - retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status); + retval = target_read_u32(target, + NUMICRO_FLASH_ISPTRG - m_address_bias_offset, + &status); if (retval != ERROR_OK) return retval; - LOG_DEBUG("status: 0x%" PRIx32 "", status); if (status == 0) break; if (timeout-- <= 0) { @@ -1595,13 +1003,15 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer, } /* check for failure */ - retval = target_read_u32(target, NUMICRO_FLASH_ISPCON, &status); + retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, &status); if (retval != ERROR_OK) return retval; if ((status & ISPCON_ISPFF) != 0) { LOG_DEBUG("failure: 0x%" PRIx32 "", status); /* if bit is set, then must write to it to clear it. */ - retval = target_write_u32(target, NUMICRO_FLASH_ISPCON, (status | ISPCON_ISPFF)); + retval = target_write_u32(target, + NUMICRO_FLASH_ISPCON - m_address_bias_offset, + (status | ISPCON_ISPFF)); if (retval != ERROR_OK) return retval; } else { @@ -1619,8 +1029,9 @@ static int numicro_get_cpu_type(struct target *target, const struct numicro_cpu_ uint32_t part_id; int retval = ERROR_OK; + numicro_get_arm_arch(target); /* Read NuMicro PartID */ - retval = target_read_u32(target, NUMICRO_SYS_BASE, &part_id); + retval = target_read_u32(target, NUMICRO_SYS_BASE - m_address_bias_offset, &part_id); if (retval != ERROR_OK) { LOG_WARNING("NuMicro flash driver: Failed to Get PartID\n"); return ERROR_FLASH_OPERATION_FAILED; @@ -1672,7 +1083,7 @@ static int numicro_probe(struct flash_bank *bank) return ERROR_FLASH_OPERATION_FAILED; } - num_pages = flash_size / NUMICRO_PAGESIZE; + num_pages = flash_size / m_page_size; bank->num_sectors = num_pages; bank->sectors = malloc(sizeof(struct flash_sector) * num_pages); @@ -1680,10 +1091,10 @@ static int numicro_probe(struct flash_bank *bank) for (int i = 0; i < num_pages; i++) { bank->sectors[i].offset = offset; - bank->sectors[i].size = NUMICRO_PAGESIZE; + bank->sectors[i].size = m_page_size; bank->sectors[i].is_erased = -1; bank->sectors[i].is_protected = 0; - offset += NUMICRO_PAGESIZE; + offset += m_page_size; } struct numicro_flash_bank *numicro_info = bank->driver_priv; @@ -1722,7 +1133,6 @@ FLASH_BANK_COMMAND_HANDLER(numicro_flash_bank_command) bank->write_start_alignment = bank->write_end_alignment = 4; return ERROR_OK; - } COMMAND_HANDLER(numicro_handle_read_isp_command) @@ -1738,6 +1148,7 @@ COMMAND_HANDLER(numicro_handle_read_isp_command) struct target *target = get_current_target(CMD_CTX); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; @@ -1765,6 +1176,7 @@ COMMAND_HANDLER(numicro_handle_write_isp_command) struct target *target = get_current_target(CMD_CTX); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; @@ -1787,6 +1199,7 @@ COMMAND_HANDLER(numicro_handle_chip_erase_command) struct target *target = get_current_target(CMD_CTX); + numicro_get_arm_arch(target); retval = numicro_init_isp(target); if (retval != ERROR_OK) return retval; diff --git a/src/flash/nor/ocl.c b/src/flash/nor/ocl.c index 4c1de632f8..61af908f58 100644 --- a/src/flash/nor/ocl.c +++ b/src/flash/nor/ocl.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * @@ -160,7 +160,7 @@ static int ocl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of retval = embeddedice_send(ocl->jtag_info, dcc_buffer, dcc_bufptr-dcc_buffer); if (retval != ERROR_OK) { free(dcc_buffer); - return retval; + return retval; } /* wait for response, fixed timeout of 1 s */ diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c index 960fb8d253..982c9610a4 100644 --- a/src/flash/nor/pic32mx.c +++ b/src/flash/nor/pic32mx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -92,7 +92,7 @@ struct pic32mx_flash_bank { * DEVID values as per PIC32MX Flash Programming Specification Rev N */ -static const struct pic32mx_devs_s { +static const struct pic32mx_devs { uint32_t devid; const char *name; } pic32mx_devs[] = { @@ -759,7 +759,7 @@ static int pic32mx_probe(struct flash_bank *bank) } } - LOG_INFO("flash size = %" PRIu32 "kbytes", num_pages / 1024); + LOG_INFO("flash size = %" PRIu32 " KiB", num_pages / 1024); free(bank->sectors); @@ -866,10 +866,8 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command) struct mips_ejtag *ejtag_info; int timeout = 10; - if (CMD_ARGC < 1) { - command_print(CMD, "pic32mx unlock <bank>"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -932,7 +930,7 @@ static const struct command_registration pic32mx_exec_command_handlers[] = { .name = "unlock", .handler = pic32mx_handle_unlock_command, .mode = COMMAND_EXEC, - .usage = "[bank_id]", + .usage = "bank_id", .help = "Unlock/Erase entire device.", }, COMMAND_REGISTRATION_DONE diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c index 4b5aa55cf6..72cf0ee05b 100644 --- a/src/flash/nor/psoc4.c +++ b/src/flash/nor/psoc4.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -384,15 +384,15 @@ static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, u * bit 7..0 family ID (lowest 8 bits) */ if (silicon_id) - *silicon_id = ((part0 & 0x0000ffff) << 16) - | ((part0 & 0x00ff0000) >> 8) - | (part1 & 0x000000ff); + *silicon_id = ((part0 & 0x0000ffff) << 16) + | ((part0 & 0x00ff0000) >> 8) + | (part1 & 0x000000ff); if (family_id) - *family_id = part1 & 0x0fff; + *family_id = part1 & 0x0fff; if (protection) - *protection = (part1 >> 12) & 0x0f; + *protection = (part1 >> 12) & 0x0f; return ERROR_OK; } @@ -651,9 +651,6 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer, if (row_offset) memset(row_buffer, bank->default_padded_value, row_offset); - bool save_poll = jtag_poll_get_enabled(); - jtag_poll_set_enabled(false); - while (count) { uint32_t chunk_size = psoc4_info->row_size - row_offset; if (chunk_size > count) { @@ -693,8 +690,6 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer, } cleanup: - jtag_poll_set_enabled(save_poll); - free(sysrq_buffer); return retval; } @@ -774,7 +769,7 @@ static int psoc4_probe(struct flash_bank *bank) num_macros++; } - LOG_DEBUG("SPCIF geometry: %" PRIu32 " kb flash, row %" PRIu32 " bytes.", + LOG_DEBUG("SPCIF geometry: %" PRIu32 " KiB flash, row %" PRIu32 " bytes.", flash_size_in_kb, row_size); /* if the user sets the size manually then ignore the probed value @@ -784,11 +779,11 @@ static int psoc4_probe(struct flash_bank *bank) flash_size_in_kb = psoc4_info->user_bank_size / 1024; } - char macros_txt[20] = ""; + char macros_txt[22] = ""; if (num_macros > 1) snprintf(macros_txt, sizeof(macros_txt), " in %" PRIu32 " macros", num_macros); - LOG_INFO("flash size = %" PRIu32 " kbytes%s", flash_size_in_kb, macros_txt); + LOG_INFO("flash size = %" PRIu32 " KiB%s", flash_size_in_kb, macros_txt); /* calculate number of pages */ uint32_t num_rows = flash_size_in_kb * 1024 / row_size; diff --git a/src/flash/nor/psoc5lp.c b/src/flash/nor/psoc5lp.c index a8265bc239..e8c9019505 100644 --- a/src/flash/nor/psoc5lp.c +++ b/src/flash/nor/psoc5lp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * PSoC 5LP flash driver @@ -102,10 +102,10 @@ struct psoc5lp_device { uint32_t id; - unsigned fam; - unsigned speed_mhz; - unsigned flash_kb; - unsigned eeprom_kb; + unsigned int fam; + unsigned int speed_mhz; + unsigned int flash_kb; + unsigned int eeprom_kb; }; /* @@ -245,7 +245,7 @@ static int psoc5lp_find_device(struct target *target, const struct psoc5lp_device **device) { uint32_t device_id; - unsigned i; + unsigned int i; int retval; *device = NULL; @@ -381,9 +381,9 @@ static int psoc5lp_spc_load_byte(struct target *target, } static int psoc5lp_spc_load_row(struct target *target, - uint8_t array_id, const uint8_t *data, unsigned row_size) + uint8_t array_id, const uint8_t *data, unsigned int row_size) { - unsigned i; + unsigned int i; int retval; retval = psoc5lp_spc_write_opcode(target, SPC_LOAD_ROW); @@ -811,24 +811,8 @@ FLASH_BANK_COMMAND_HANDLER(psoc5lp_nvl_flash_bank_command) return ERROR_OK; } -static const struct command_registration psoc5lp_nvl_exec_command_handlers[] = { - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration psoc5lp_nvl_command_handlers[] = { - { - .name = "psoc5lp_nvl", - .mode = COMMAND_ANY, - .help = "PSoC 5LP NV Latch command group", - .usage = "", - .chain = psoc5lp_nvl_exec_command_handlers, - }, - COMMAND_REGISTRATION_DONE -}; - const struct flash_driver psoc5lp_nvl_flash = { .name = "psoc5lp_nvl", - .commands = psoc5lp_nvl_command_handlers, .flash_bank_command = psoc5lp_nvl_flash_bank_command, .info = psoc5lp_nvl_get_info_command, .probe = psoc5lp_nvl_probe, @@ -869,7 +853,7 @@ static int psoc5lp_eeprom_write(struct flash_bank *bank, { struct target *target = bank->target; uint8_t temp[2]; - unsigned row; + unsigned int row; int retval; if (offset % EEPROM_ROW_SIZE != 0) { @@ -1010,24 +994,8 @@ FLASH_BANK_COMMAND_HANDLER(psoc5lp_eeprom_flash_bank_command) return ERROR_OK; } -static const struct command_registration psoc5lp_eeprom_exec_command_handlers[] = { - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration psoc5lp_eeprom_command_handlers[] = { - { - .name = "psoc5lp_eeprom", - .mode = COMMAND_ANY, - .help = "PSoC 5LP EEPROM command group", - .usage = "", - .chain = psoc5lp_eeprom_exec_command_handlers, - }, - COMMAND_REGISTRATION_DONE -}; - const struct flash_driver psoc5lp_eeprom_flash = { .name = "psoc5lp_eeprom", - .commands = psoc5lp_eeprom_command_handlers, .flash_bank_command = psoc5lp_eeprom_flash_bank_command, .info = psoc5lp_eeprom_get_info_command, .probe = psoc5lp_eeprom_probe, @@ -1156,7 +1124,7 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer, struct working_area *code_area, *even_row_area, *odd_row_area; uint32_t row_size; uint8_t temp[2], buf[12], ecc_bytes[ROW_ECC_SIZE]; - unsigned array_id, row; + unsigned int array_id, row; int i, retval; if (offset + byte_count > bank->size) { @@ -1215,7 +1183,7 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer, row < ROWS_PER_BLOCK && byte_count > 0; row++) { bool even_row = (row % 2 == 0); struct working_area *data_area = even_row ? even_row_area : odd_row_area; - unsigned len = MIN(ROW_SIZE, byte_count); + unsigned int len = MIN(ROW_SIZE, byte_count); LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT, array_id, row, data_area->address); @@ -1339,8 +1307,8 @@ static int psoc5lp_protect_check(struct flash_bank *bank) { struct psoc5lp_flash_bank *psoc_bank = bank->driver_priv; uint8_t row_data[ROW_SIZE]; - const unsigned protection_bytes_per_sector = ROWS_PER_SECTOR * 2 / 8; - unsigned i, k, num_sectors; + const unsigned int protection_bytes_per_sector = ROWS_PER_SECTOR * 2 / 8; + unsigned int i, k, num_sectors; int retval; if (bank->target->state != TARGET_HALTED) { diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c index ce615fc2a0..662910aa04 100644 --- a/src/flash/nor/psoc6.c +++ b/src/flash/nor/psoc6.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * * @@ -18,7 +18,6 @@ #include "target/target.h" #include "target/cortex_m.h" #include "target/breakpoints.h" -#include "target/target_type.h" #include "target/algorithm.h" /************************************************************************************************** @@ -224,6 +223,8 @@ static int ipc_poll_lock_stat(struct target *target, uint32_t ipc_id, bool lock_ { int hr; uint32_t reg_val; + struct armv7m_common *armv7m = target_to_armv7m(target); + bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M); struct timeout to; timeout_init(&to, IPC_TIMEOUT_MS); @@ -245,7 +246,7 @@ static int ipc_poll_lock_stat(struct target *target, uint32_t ipc_id, bool lock_ return ERROR_OK; } - if (target->coreid) { + if (!is_cm0) { LOG_WARNING("SROM API calls via CM4 target are supported on single-core PSoC6 devices only. " "Please perform all Flash-related operations via CM0+ target on dual-core devices."); } @@ -486,7 +487,7 @@ static int psoc6_get_info(struct flash_bank *bank, struct command_invocation *cm { struct psoc6_target_info *psoc6_info = bank->driver_priv; - if (psoc6_info->is_probed == false) + if (!psoc6_info->is_probed) return ERROR_FAIL; int hr = get_silicon_id(bank->target, &psoc6_info->silicon_id, &psoc6_info->protection); @@ -591,8 +592,7 @@ static int psoc6_probe(struct flash_bank *bank) unsigned int num_sectors = bank_size / row_sz; bank->size = bank_size; - bank->chip_width = 4; - bank->bus_width = 4; + bank->erased_value = 0; bank->default_padded_value = 0; @@ -888,7 +888,8 @@ static int handle_reset_halt(struct target *target) { int hr; uint32_t reset_addr; - bool is_cm0 = (target->coreid == 0); + struct armv7m_common *armv7m = target_to_armv7m(target); + bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M); /* Halt target device */ if (target->state != TARGET_HALTED) { diff --git a/src/flash/nor/qn908x.c b/src/flash/nor/qn908x.c new file mode 100644 index 0000000000..8cd7a2f04a --- /dev/null +++ b/src/flash/nor/qn908x.c @@ -0,0 +1,1197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*************************************************************************** + * Copyright (C) 2020 iosabi * + * iosabi <iosabi@protonmail.com> * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "imp.h" + +#include <helper/binarybuffer.h> +#include <helper/bits.h> +#include <helper/crc32.h> +#include <helper/time_support.h> +#include <helper/types.h> + +/* The QN908x has two flash regions, one is the main flash region holding the + * user code and the second one is a small (0x800 bytes) "Flash information + * page" that can't be written to by the user. This page contains information + * programmed at the factory. + * + * The main flash region is normally 512 KiB, there's a field in the "Flash + * information page" that allows to specify for 256 KiB size chips. However, at + * the time of writing, none of the variants in the market have 256 KiB. + * + * The flash is divided into blocks of 256 KiB each, therefore containing two + * blocks. A block is subdivided into pages, of 2048 bytes. A page is the + * smallest region that can be erased or protected independently, although it + * is also possible to erase a whole block or both blocks. A page is subdivided + * into 8 rows of 64 words (32-bit words). The word subdivision is only + * relevant because DMA can write multiple words in the same row in the same + * flash program operation. + * + * For the Flash information page we are only interested in the last + * 0x100 bytes which contain a CRC-32 checksum of that 0x100 bytes long region + * and a field stating the size of the flash. This is also a good check that + * we are dealing with the right chip/flash configuration and is used in the + * probe() function. + */ +#define QN908X_FLASH_BASE 0x01000000 + +#define QN908X_FLASH_PAGE_SIZE 2048 +#define QN908X_FLASH_PAGES_PER_BLOCK 128 +#define QN908X_FLASH_MAX_BLOCKS 2 +#define QN908X_FLASH_BLOCK_SIZE \ + (QN908X_FLASH_PAGES_PER_BLOCK * QN908X_FLASH_PAGE_SIZE) +#define QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS 0x1c +#define QN908X_FLASH_IRQ_VECTOR_CHECKSUM_SIZE 4 +#define QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END \ + (QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_SIZE) + + +/* Flash information page memory fields. */ +#define QN908X_INFO_PAGE_BASE 0x210b0000u +#define QN908X_INFO_PAGE_CRC32 (QN908X_INFO_PAGE_BASE + 0x700) +#define QN908X_INFO_PAGE_CRC_START (QN908X_INFO_PAGE_BASE + 0x704) +#define QN908X_INFO_PAGE_BOOTLOADER_VER (QN908X_INFO_PAGE_BASE + 0x704) +#define QN908X_INFO_PAGE_FLASH_SIZE (QN908X_INFO_PAGE_BASE + 0x708) +#define QN908X_INFO_PAGE_BLUETOOTH_ADDR (QN908X_INFO_PAGE_BASE + 0x7fa) +#define QN908X_INFO_PAGE_CRC_END (QN908X_INFO_PAGE_BASE + 0x800) + + +/* Possible values of the QN908X_INFO_PAGE_FLASH_SIZE field. */ +enum qn908x_info_page_flash_size { + QN908X_FLASH_SIZE_512K = 0xfffff0ff, + QN908X_FLASH_SIZE_256K = 0xffffe0ff, +}; + +/* QN908x "Flash memory controller", described in section 28 of the user + * manual. In the NXP SDK this peripheral is called "FLASH", however we use the + * name "FMC" (Flash Memory Controller) here when referring to the controller + * to avoid confusion with other "flash" terms in OpenOCD. */ +#define QN908X_FMC_BASE 0x40081000u +#define QN908X_FMC_INI_RD_EN (QN908X_FMC_BASE + 0x00) +#define QN908X_FMC_ERASE_CTRL (QN908X_FMC_BASE + 0x04) +#define QN908X_FMC_ERASE_TIME (QN908X_FMC_BASE + 0x08) +#define QN908X_FMC_TIME_CTRL (QN908X_FMC_BASE + 0x0c) +#define QN908X_FMC_SMART_CTRL (QN908X_FMC_BASE + 0x10) +#define QN908X_FMC_INT_STAT (QN908X_FMC_BASE + 0x18) +#define QN908X_FMC_LOCK_STAT_0 (QN908X_FMC_BASE + 0x20) +#define QN908X_FMC_LOCK_STAT_1 (QN908X_FMC_BASE + 0x24) +#define QN908X_FMC_LOCK_STAT_2 (QN908X_FMC_BASE + 0x28) +#define QN908X_FMC_LOCK_STAT_3 (QN908X_FMC_BASE + 0x2c) +#define QN908X_FMC_LOCK_STAT_4 (QN908X_FMC_BASE + 0x30) +#define QN908X_FMC_LOCK_STAT_5 (QN908X_FMC_BASE + 0x34) +#define QN908X_FMC_LOCK_STAT_6 (QN908X_FMC_BASE + 0x38) +#define QN908X_FMC_LOCK_STAT_7 (QN908X_FMC_BASE + 0x3c) +#define QN908X_FMC_LOCK_STAT_8 (QN908X_FMC_BASE + 0x40) +#define QN908X_FMC_STATUS1 (QN908X_FMC_BASE + 0x48) +#define QN908X_FMC_DEBUG_PASSWORD (QN908X_FMC_BASE + 0xa8) +#define QN908X_FMC_ERASE_PASSWORD (QN908X_FMC_BASE + 0xac) + +#define QN908X_FMC_INI_RD_EN_INI_RD_EN_MASK BIT(0) + +#define QN908X_FMC_STATUS1_FSH_ERA_BUSY_L_MASK BIT(9) +#define QN908X_FMC_STATUS1_FSH_WR_BUSY_L_MASK BIT(10) +#define QN908X_FMC_STATUS1_FSH_ERA_BUSY_H_MASK BIT(12) +#define QN908X_FMC_STATUS1_FSH_WR_BUSY_H_MASK BIT(13) +#define QN908X_FMC_STATUS1_INI_RD_DONE_MASK BIT(15) +#define QN908X_FMC_STATUS1_FSH_STA_MASK BIT(26) + +#define QN908X_FMC_ERASE_CTRL_PAGE_IDXL_SHIFT 0 +#define QN908X_FMC_ERASE_CTRL_PAGE_IDXH_SHIFT 8 +#define QN908X_FMC_ERASE_CTRL_HALF_ERASEL_EN_SHIFT 28 +#define QN908X_FMC_ERASE_CTRL_HALF_ERASEH_EN_SHIFT 29 +#define QN908X_FMC_ERASE_CTRL_PAGE_ERASEL_EN_SHIFT 30 +#define QN908X_FMC_ERASE_CTRL_PAGE_ERASEH_EN_SHIFT 31 + +#define QN908X_FMC_INT_STAT_AHBL_INT_MASK BIT(0) +#define QN908X_FMC_INT_STAT_LOCKL_INT_MASK BIT(1) +#define QN908X_FMC_INT_STAT_ERASEL_INT_MASK BIT(2) +#define QN908X_FMC_INT_STAT_WRITEL_INT_MASK BIT(3) +#define QN908X_FMC_INT_STAT_WR_BUFL_INT_MASK BIT(4) +#define QN908X_FMC_INT_STAT_WRITE_FAIL_L_INT_MASK BIT(5) +#define QN908X_FMC_INT_STAT_ERASE_FAIL_L_INT_MASK BIT(6) +#define QN908X_FMC_INT_STAT_AHBH_INT_MASK BIT(8) +#define QN908X_FMC_INT_STAT_LOCKH_INT_MASK BIT(9) +#define QN908X_FMC_INT_STAT_ERASEH_INT_MASK BIT(10) +#define QN908X_FMC_INT_STAT_WRITEH_INT_MASK BIT(11) +#define QN908X_FMC_INT_STAT_WR_BUFH_INT_MASK BIT(12) +#define QN908X_FMC_INT_STAT_WRITE_FAIL_H_INT_MASK BIT(13) +#define QN908X_FMC_INT_STAT_ERASE_FAIL_H_INT_MASK BIT(14) + +#define QN908X_FMC_SMART_CTRL_PRGML_EN_MASK BIT(0) +#define QN908X_FMC_SMART_CTRL_PRGMH_EN_MASK BIT(1) +#define QN908X_FMC_SMART_CTRL_SMART_WRITEL_EN_MASK BIT(2) +#define QN908X_FMC_SMART_CTRL_SMART_WRITEH_EN_MASK BIT(3) +#define QN908X_FMC_SMART_CTRL_SMART_ERASEL_EN_MASK BIT(4) +#define QN908X_FMC_SMART_CTRL_SMART_ERASEH_EN_MASK BIT(5) +#define QN908X_FMC_SMART_CTRL_MAX_WRITE_MASK 0xf00u +#define QN908X_FMC_SMART_CTRL_MAX_WRITE_SHIFT 8u +#define QN908X_FMC_SMART_CTRL_MAX_WRITE(x) \ + (((uint32_t)(((uint32_t)(x)) << QN908X_FMC_SMART_CTRL_MAX_WRITE_SHIFT)) \ + & QN908X_FMC_SMART_CTRL_MAX_WRITE_MASK) +#define QN908X_FMC_SMART_CTRL_MAX_ERASE_MASK 0x3f000u +#define QN908X_FMC_SMART_CTRL_MAX_ERASE_SHIFT 12u +#define QN908X_FMC_SMART_CTRL_MAX_ERASE(x) \ + (((uint32_t)(((uint32_t)(x)) << QN908X_FMC_SMART_CTRL_MAX_ERASE_SHIFT)) \ + & QN908X_FMC_SMART_CTRL_MAX_ERASE_MASK) + +#define QN908X_FMC_SMART_CTRL_MAX_ERASE_RETRIES 9 +#define QN908X_FMC_SMART_CTRL_MAX_WRITE_RETRIES 9 + +#define QN908X_FMC_TIME_CTRL_PRGM_CYCLE_MASK 0xfffu +#define QN908X_FMC_TIME_CTRL_PRGM_CYCLE_SHIFT 0u +#define QN908X_FMC_TIME_CTRL_PRGM_CYCLE(x) \ + (((uint32_t)(((uint32_t)(x)) << QN908X_FMC_TIME_CTRL_PRGM_CYCLE_SHIFT)) \ + & QN908X_FMC_TIME_CTRL_PRGM_CYCLE_MASK) +#define QN908X_FMC_TIME_CTRL_TIME_BASE_MASK 0xff000u +#define QN908X_FMC_TIME_CTRL_TIME_BASE_SHIFT 12u +#define QN908X_FMC_TIME_CTRL_TIME_BASE(x) \ + (((uint32_t)(((uint32_t)(x)) << QN908X_FMC_TIME_CTRL_TIME_BASE_SHIFT)) \ + & QN908X_FMC_TIME_CTRL_TIME_BASE_MASK) + +#define QN908X_FMC_LOCK_STAT_8_MASS_ERASE_LOCK_EN BIT(0) +#define QN908X_FMC_LOCK_STAT_8_FSH_PROTECT_EN BIT(1) +#define QN908X_FMC_LOCK_STAT_8_MEM_PROTECT_EN BIT(2) +#define QN908X_FMC_LOCK_STAT_8_PROTECT_ANY (BIT(1) | BIT(2)) + +/* See Table 418 "Flash lock and protect description" in the user manual */ +#define QN908X_FLASH_LOCK_ADDR (QN908X_FLASH_BASE + 0x7f820) +/* Allow mass erase */ +#define QN908X_FLASH_LOCK_ENABLE_MASS_ERASE BIT(0) +/* disallow flash access from SWD */ +#define QN908X_FLASH_LOCK_ENABLE_FLASH_PROTECTION BIT(1) +/* disallow SRAM access from SWD */ +#define QN908X_FLASH_LOCK_ENABLE_MEMORY_PROTECTION BIT(2) + +/* Page lock information located at the beginning of the last page. */ +struct qn908x_flash_page_lock { + uint8_t bits[QN908X_FLASH_MAX_BLOCKS * QN908X_FLASH_PAGES_PER_BLOCK / 8]; + uint8_t protection; + uint8_t _reserved[3]; + /* nvds_size is unused here, but we need to preserve it across erases + * when locking and unlocking pages. */ + uint8_t nvds_size[4]; +} __attribute__ ((packed)); + +/* Clock configuration is stored in the SYSCON. */ +#define QN908X_SYSCON_BASE 0x40000000u +#define QN908X_SYSCON_CLK_EN (QN908X_SYSCON_BASE + 0x00cu) +#define QN908X_SYSCON_CLK_CTRL (QN908X_SYSCON_BASE + 0x010u) +#define QN908X_SYSCON_CHIP_ID (QN908X_SYSCON_BASE + 0x108u) +#define QN908X_SYSCON_XTAL_CTRL (QN908X_SYSCON_BASE + 0x180u) + +/* Internal 16MHz / 8MHz clock used by the erase operation. */ +#define QN908X_SYSCON_CLK_EN_CLK_DP_EN_MASK BIT(21) + +#define SYSCON_XTAL_CTRL_XTAL_DIV_MASK BIT(31) + +#define SYSCON_CLK_CTRL_AHB_DIV_MASK 0x1FFF0u +#define SYSCON_CLK_CTRL_AHB_DIV_SHIFT 4u +#define SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK BIT(19) +#define SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK BIT(20) +#define SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK 0xC0000000u +#define SYSCON_CLK_CTRL_SYS_CLK_SEL_SHIFT 30u + +#define CLOCK_16MHZ 16000000u +#define CLOCK_32MHZ 32000000u +#define CLOCK_32KHZ 32000u + +/* Watchdog block registers */ +#define QN908X_WDT_BASE 0x40001000u +#define QN908X_WDT_CTRL (QN908X_WDT_BASE + 0x08u) +#define QN908X_WDT_LOCK (QN908X_WDT_BASE + 0x20u) + +struct qn908x_flash_bank { + /* The number of flash blocks. Initially set to zero until the flash + * is probed. This determines the size of the flash. */ + unsigned int num_blocks; + + unsigned int user_bank_size; + bool calc_checksum; + + /* Whether we allow to flash an image that disables SWD access, potentially + * bricking the device since the image can't be reflashed from SWD. */ + bool allow_swd_disabled; + + bool page_lock_loaded; + struct qn908x_flash_page_lock page_lock; +}; + +/* 500 ms timeout. */ +#define QN908X_DEFAULT_TIMEOUT_MS 500 + +/* Forward declaration of commands. */ +static int qn908x_probe(struct flash_bank *bank); +static int qn908x_write(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count); + +/* Update the value of a register with a mask. This helper allows to read a + * register, modify a subset of the bits and write back the value, which is a + * common operation when modifying only a bit filed in a register. */ +static int qn908x_update_reg(struct target *target, target_addr_t reg, + uint32_t mask, uint32_t value) +{ + uint32_t orig_value = 0; + uint32_t new_value; + int retval; + if (mask != 0xffffffff) { + /* No need to read the old value if we request a mask of 32 bits. */ + retval = target_read_u32(target, reg, &orig_value); + if (retval != ERROR_OK) { + LOG_DEBUG("Error reading reg at " TARGET_ADDR_FMT + ": %d", reg, retval); + return retval; + } + } + new_value = (orig_value & ~mask) | (value & mask); + retval = target_write_u32(target, reg, new_value); + if (retval != ERROR_OK) { + LOG_DEBUG("Error writing reg at " TARGET_ADDR_FMT " with 0x%08" + PRIx32 ": %d", reg, new_value, retval); + return retval; + } + if (mask == 0xffffffff) { + LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08" + PRIx32 "", reg, new_value); + } else { + LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32 + " -> 0x%.08" PRIx32, reg, orig_value, new_value); + } + return ERROR_OK; +} + +/* Load lock bit and protection bit and load redundancy page info. + * This populates the LOCK_STAT_n registers with the values from the lock page, + * making protection bit changes to the last page effective. */ +static int qn908x_load_lock_stat(struct target *target) +{ + int retval = target_write_u32(target, QN908X_FMC_INI_RD_EN, + QN908X_FMC_INI_RD_EN_INI_RD_EN_MASK); + if (retval != ERROR_OK) + return retval; + + uint32_t status1; + const uint32_t status_mask = QN908X_FMC_STATUS1_FSH_STA_MASK + | QN908X_FMC_STATUS1_INI_RD_DONE_MASK; + do { + retval = target_read_u32(target, QN908X_FMC_STATUS1, &status1); + if (retval != ERROR_OK) + return retval; + } while ((status1 & status_mask) != QN908X_FMC_STATUS1_INI_RD_DONE_MASK); + + for (int i = 0; i <= 8; i++) { + uint32_t addr = QN908X_FMC_LOCK_STAT_0 + i * 4; + uint32_t lock_stat; + if (target_read_u32(target, addr, &lock_stat) == ERROR_OK) + LOG_DEBUG("LOCK_STAT_%d = 0x%08" PRIx32, i, lock_stat); + } + return ERROR_OK; +} + +/* Initializes the FMC controller registers for allowing writing. */ +static int qn908x_init_flash(struct target *target) +{ + /* Determine the current clock configuration. */ + uint32_t clk_ctrl; + int retval = target_read_u32(target, QN908X_SYSCON_CLK_CTRL, &clk_ctrl); + if (retval != ERROR_OK) + return retval; + + uint32_t clk_sel = (clk_ctrl & SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK) + >> SYSCON_CLK_CTRL_SYS_CLK_SEL_SHIFT; + LOG_DEBUG("Clock clk_sel=0x%08" PRIu32, clk_sel); + + /* Core clock frequency. */ + uint32_t core_freq = 0; + switch (clk_sel) { + case 0: /* RCO 32 MHz */ + core_freq = (clk_ctrl & SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK) ? + CLOCK_16MHZ : CLOCK_32MHZ; + break; + case 1: /* Xin frequency */ + { + uint32_t clk_xtal; + retval = target_read_u32(target, QN908X_SYSCON_XTAL_CTRL, &clk_xtal); + if (retval != ERROR_OK) + return retval; + core_freq = (clk_ctrl & SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK) + && (clk_xtal & SYSCON_XTAL_CTRL_XTAL_DIV_MASK) + ? CLOCK_32MHZ : CLOCK_16MHZ; + } + break; + case 2: /* 32 Kz */ + core_freq = CLOCK_32KHZ; + break; + default: + return ERROR_FAIL; + } + + uint32_t ahb_div = (clk_ctrl & SYSCON_CLK_CTRL_AHB_DIV_MASK) + >> SYSCON_CLK_CTRL_AHB_DIV_SHIFT; + uint32_t ahb_freq = core_freq / (ahb_div + 1); + + LOG_DEBUG("Core freq: %" PRIu32 " Hz | AHB freq: %" PRIu32 " Hz", + core_freq, ahb_freq); + + /* TIME_BASE is 2uS at the current AHB clock speed. */ + retval = target_write_u32(target, QN908X_FMC_TIME_CTRL, + QN908X_FMC_TIME_CTRL_TIME_BASE(2 * ahb_freq / 1000000) | + QN908X_FMC_TIME_CTRL_PRGM_CYCLE(30)); + if (retval != ERROR_OK) + return retval; + + return qn908x_load_lock_stat(target); +} + +/* flash bank qn908x <base> <size> 0 0 <target#> [calc_checksum] */ +FLASH_BANK_COMMAND_HANDLER(qn908x_flash_bank_command) +{ + struct qn908x_flash_bank *qn908x_info; + + if (CMD_ARGC < 6 || CMD_ARGC > 7) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (bank->base != QN908X_FLASH_BASE) { + LOG_ERROR("Address " TARGET_ADDR_FMT + " is an invalid bank address (try 0x%08" PRIx32 ")", + bank->base, QN908X_FLASH_BASE); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + qn908x_info = malloc(sizeof(struct qn908x_flash_bank)); + + if (!qn908x_info) + return ERROR_FAIL; + + bank->driver_priv = qn908x_info; + qn908x_info->num_blocks = 0; + qn908x_info->user_bank_size = bank->size; + qn908x_info->page_lock_loaded = false; + qn908x_info->allow_swd_disabled = false; + + qn908x_info->calc_checksum = false; + if (CMD_ARGC == 7) { + if (strcmp(CMD_ARGV[6], "calc_checksum")) { + free(qn908x_info); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + qn908x_info->calc_checksum = true; + } + + return ERROR_OK; +} + +static int qn908x_read_page_lock(struct flash_bank *bank) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* The last page of the flash contains the "Flash lock and protect" + * information. It is not clear where this is located on chips with only + * one block. */ + uint32_t prot_offset = qn908x_info->num_blocks * QN908X_FLASH_BLOCK_SIZE + - QN908X_FLASH_PAGE_SIZE; + + int retval = target_read_memory(bank->target, bank->base + prot_offset, 4, + sizeof(qn908x_info->page_lock) / 4, + (void *)(&qn908x_info->page_lock)); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("Flash protection = 0x%02" PRIx8, + qn908x_info->page_lock.protection); + + qn908x_info->page_lock_loaded = true; + return ERROR_OK; +} + +static int qn908x_busy_check(struct target *target) +{ + uint32_t status1; + int retval = target_read_u32(target, QN908X_FMC_STATUS1, &status1); + if (retval != ERROR_OK) + return retval; + + if ((status1 & (QN908X_FMC_STATUS1_FSH_ERA_BUSY_L_MASK + | QN908X_FMC_STATUS1_FSH_WR_BUSY_L_MASK + | QN908X_FMC_STATUS1_FSH_ERA_BUSY_H_MASK + | QN908X_FMC_STATUS1_FSH_WR_BUSY_H_MASK))) + return ERROR_FLASH_BUSY; + return ERROR_OK; +} + +static int qn908x_status_check(struct target *target) +{ + uint32_t int_stat; + int retval = target_read_u32(target, QN908X_FMC_INT_STAT, &int_stat); + if (retval != ERROR_OK) + return retval; + + /* The error bits for block 0 and block 1 have the exact same layout, only + * that block 1 error bits are shifted by 8 bits. We use this fact to + * loop over the blocks */ + for (unsigned int block = 0; block <= 1; block++) { + unsigned int shift = (block) ? 8 : 0; + if (int_stat & (QN908X_FMC_INT_STAT_AHBL_INT_MASK << shift)) { + LOG_ERROR("AHB error on block %u", block); + return ERROR_FAIL; + } + + if (int_stat & (QN908X_FMC_INT_STAT_LOCKL_INT_MASK << shift)) { + LOG_ERROR("Locked page being accessed error on block %u", block); + return ERROR_FAIL; + } + + if (int_stat & (QN908X_FMC_INT_STAT_WRITE_FAIL_L_INT_MASK << shift)) { + LOG_ERROR("Smart write on block %u failed", block); + return ERROR_FAIL; + } + + if ((int_stat & (QN908X_FMC_INT_STAT_ERASE_FAIL_L_INT_MASK << shift)) + || (int_stat & (QN908X_FMC_INT_STAT_ERASE_FAIL_H_INT_MASK << shift))) { + LOG_ERROR("Smart erase on block %u failed", block); + return ERROR_FAIL; + } + } + + return ERROR_OK; +} + +static int qn908x_wait_for_idle(struct target *target, int64_t timeout_ms) +{ + int64_t ms_start = timeval_ms(); + + int busy = ERROR_FLASH_BUSY; + while (busy != ERROR_OK) { + busy = qn908x_busy_check(target); + if (busy != ERROR_OK && busy != ERROR_FLASH_BUSY) + return busy; + if (timeval_ms() - ms_start > timeout_ms) { + LOG_ERROR("Timeout waiting to be idle."); + return ERROR_TIMEOUT_REACHED; + } + } + return ERROR_OK; +} + +/* Set up the chip to perform an erase (page or block) operation. */ +static int qn908x_setup_erase(struct target *target) +{ + int retval; + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* Enable 8MHz clock. */ + retval = qn908x_update_reg(target, QN908X_SYSCON_CLK_EN, + QN908X_SYSCON_CLK_EN_CLK_DP_EN_MASK, + QN908X_SYSCON_CLK_EN_CLK_DP_EN_MASK); + if (retval != ERROR_OK) + return retval; + + /* Set ERASE_TIME to 2ms for smart erase. */ + retval = qn908x_update_reg(target, QN908X_FMC_ERASE_TIME, + (1u << 20) - 1, + 2000 * 8); /* 2000 uS * 8 MHz = x cycles */ + if (retval != ERROR_OK) + return retval; + + /* Set up smart erase. SWD can only perform smart erase. */ + uint32_t ctrl_val = QN908X_FMC_SMART_CTRL_SMART_ERASEH_EN_MASK + | QN908X_FMC_SMART_CTRL_SMART_ERASEL_EN_MASK + | QN908X_FMC_SMART_CTRL_MAX_ERASE(QN908X_FMC_SMART_CTRL_MAX_ERASE_RETRIES) + | QN908X_FMC_SMART_CTRL_MAX_WRITE(QN908X_FMC_SMART_CTRL_MAX_WRITE_RETRIES); + retval = target_write_u32(target, QN908X_FMC_SMART_CTRL, ctrl_val); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_wait_for_idle(target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; +} + +static int qn908x_erase(struct flash_bank *bank, unsigned int first, + unsigned int last) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + int retval = ERROR_OK; + + if (!qn908x_info->num_blocks) { + if (qn908x_probe(bank) != ERROR_OK) + return ERROR_FLASH_BANK_NOT_PROBED; + } + + retval = qn908x_setup_erase(bank->target); + if (retval != ERROR_OK) + return retval; + + for (unsigned int i = first; i <= last; i++) { + if (i >= bank->num_sectors) + return ERROR_FLASH_SECTOR_INVALID; + uint32_t block_idx = i / QN908X_FLASH_PAGES_PER_BLOCK; + uint32_t page_idx = i % QN908X_FLASH_PAGES_PER_BLOCK; + if (block_idx >= qn908x_info->num_blocks) + return ERROR_FLASH_SECTOR_INVALID; + + LOG_DEBUG("Erasing page %" PRIu32 " of block %" PRIu32, + page_idx, block_idx); + + /* Depending on the block the page we are erasing is located we + * need to use a different set of bits in the registers. */ + uint32_t ctrl_page_idx_shift = block_idx ? + QN908X_FMC_ERASE_CTRL_PAGE_IDXH_SHIFT : + QN908X_FMC_ERASE_CTRL_PAGE_IDXL_SHIFT; + uint32_t ctrl_erase_en_shift = block_idx ? + QN908X_FMC_ERASE_CTRL_PAGE_ERASEH_EN_SHIFT : + QN908X_FMC_ERASE_CTRL_PAGE_ERASEL_EN_SHIFT; + + retval = target_write_u32(bank->target, QN908X_FMC_ERASE_CTRL, + BIT(ctrl_erase_en_shift) | (page_idx << ctrl_page_idx_shift)); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_status_check(bank->target); + if (retval != ERROR_OK) + return retval; + } + + return retval; +} + +static int qn908x_protect(struct flash_bank *bank, int set, unsigned int first, + unsigned int last) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (!qn908x_info->page_lock_loaded) { + int retval = qn908x_read_page_lock(bank); + if (retval != ERROR_OK) + return retval; + } + + /* Use [first, last) interval open on the right side from now on. */ + last++; + /* We use sectors as prot_blocks. */ + bool needs_update = false; + for (unsigned int i = first; i < last; i++) { + if (set != (((qn908x_info->page_lock.bits[i / 8] >> (i % 8)) & 1) ^ 1)) + needs_update = true; + } + + /* Check that flash protection still allows SWD access to flash and RAM, + * otherwise we won't be able to re-flash this chip from SWD unless we do a + * mass erase. */ + if (qn908x_info->page_lock.protection & QN908X_FMC_LOCK_STAT_8_PROTECT_ANY) { + LOG_WARNING("SWD flash/RAM access disabled in the Flash lock and " + "protect descriptor. You might need to issue a mass_erase to " + "regain SWD access to this chip after reboot."); + } + + if (!needs_update) + return ERROR_OK; + + int last_page = qn908x_info->num_blocks * QN908X_FLASH_PAGES_PER_BLOCK - 1; + int retval; + + if (qn908x_info->page_lock.bits[sizeof(qn908x_info->page_lock.bits) - 1] & 0x80) { + /* A bit 1 in the MSB in the page_lock.bits array means that the last + * page is unlocked, so we can just erase it. */ + retval = qn908x_erase(bank, last_page, last_page); + if (retval != ERROR_OK) + return retval; + } else { + /* TODO: The last page is locked and we can't erase unless we use the + * ERASE_PASSWORD from code running on the device. For this we need to + * copy a little program to RAM and execute the erase command from + * there since there's no way to override the page protection from + * SWD. */ + LOG_ERROR("Unprotecting the last page is not supported. Issue a " + "\"qn908x mass_erase\" command to erase the whole flash, " + "including the last page and its protection."); + return ERROR_FAIL; + } + + for (unsigned int i = first / 8; i < (last + 7) / 8; i++) { + /* first_mask contains a bit set if the bit corresponds to a block id + * that is larger or equal than first. This is basically 0xff in all + * cases except potentially the first iteration. */ + uint8_t first_mask = (first <= i * 8) + ? 0xff : 0xff ^ ((1u << (first - i * 8)) - 1); + /* Similar to first_mask, this contains a bit set if the corresponding + * is smaller than last. */ + uint8_t last_mask = (i * 8 + 8 <= last) + ? 0xff : ((1u << (last - i * 8)) - 1); + + uint8_t mask = first_mask & last_mask; + LOG_DEBUG("protect set=%d bits[%d] with mask=0x%02x", set, i, mask); + /* To "set" the protection bit means to clear the bit in the page_lock + * bit array. */ + if (set) + qn908x_info->page_lock.bits[i] &= ~mask; + else + qn908x_info->page_lock.bits[i] |= mask; + } + + retval = qn908x_write(bank, (void *)(&qn908x_info->page_lock), + last_page * QN908X_FLASH_PAGE_SIZE, sizeof(qn908x_info->page_lock)); + if (retval != ERROR_OK) + return retval; + + /* Reload the lock_stat to make the changes effective. */ + retval = qn908x_load_lock_stat(bank->target); + if (retval != ERROR_OK) + return retval; + + for (unsigned int i = first; i < last; i++) + bank->sectors[i].is_protected = set; + + return ERROR_OK; +} + +static int qn908x_write(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + int retval = ERROR_OK; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* The flash infrastructure was requested to align writes to 32 bit */ + assert(((offset % 4) == 0) && ((count % 4) == 0)); + + /* Compute the calc_checksum even if it wasn't requested. */ + uint32_t checksum = 0; + if (offset == 0 && count >= 0x20) { + for (int i = 0; i < 7; i++) + checksum += buf_get_u32(buffer + (i * 4), 0, 32); + checksum = 0 - checksum; + LOG_DEBUG("computed image checksum: 0x%8.8" PRIx32, checksum); + uint32_t stored_checksum = buf_get_u32(buffer + 7 * 4, 0, 32); + if (checksum != stored_checksum) { + LOG_WARNING("Image vector table checksum mismatch: expected 0x%08" + PRIx32 " but found 0x%08" PRIx32, + checksum, stored_checksum); + if (!qn908x_info->calc_checksum) + LOG_WARNING("This device will not boot, use calc_checksum in " + "the flash bank."); + else + LOG_WARNING("Updating checksum, verification will fail."); + } + } + + /* Check the Code Read Protection (CRP) word for invalid values or not + * allowed ones. */ + if (offset <= 0x20 && offset + count >= 0x24) { + uint32_t crp = buf_get_u32(buffer + 0x20 - offset, 0, 32); + /* 2-bit fields at bits 10, 12, 14, 16 and 18 must not be 00 or 11. */ + for (int i = 10; i <= 18; i += 2) { + uint32_t field = (crp >> i) & 3; + if (field == 0 || field == 3) { + LOG_DEBUG("Code Read Protection = 0x%08" PRIx32, crp); + LOG_ERROR("The Code Read Protection (CRP) field at bit %d is " + "invalid (%" PRIu32 "). An invalid value could make " + "the flash inaccessible.", i, field); + return ERROR_FAIL; + } + } + + uint32_t swd_allowed = (crp >> 18) & 3; + if (swd_allowed != 2) { + LOG_WARNING("The Code Read Protection (CRP) in this image " + "(0x%08" PRIx32 ") is disabling the SWD access, which is " + "currently used by OpenOCD to flash this device. After " + "reboot, this device will not be accessible to OpenOCD " + "anymore.", crp); + if (!qn908x_info->allow_swd_disabled) { + LOG_ERROR("Disabling SWD is not allowed, run " + "\"qn908x allow_brick\" before if you really want to " + "disable SWD. You won't be able to access this chip " + "anymore from OpenOCD."); + return ERROR_FAIL; + } + } + } + + retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + uint32_t smart_ctrl = QN908X_FMC_SMART_CTRL_SMART_WRITEL_EN_MASK + | QN908X_FMC_SMART_CTRL_PRGML_EN_MASK + | QN908X_FMC_SMART_CTRL_MAX_WRITE(QN908X_FMC_SMART_CTRL_MAX_WRITE_RETRIES); + if (qn908x_info->num_blocks > 1) { + smart_ctrl |= QN908X_FMC_SMART_CTRL_SMART_WRITEH_EN_MASK + | QN908X_FMC_SMART_CTRL_PRGMH_EN_MASK; + } + retval = target_write_u32(bank->target, QN908X_FMC_SMART_CTRL, smart_ctrl); + if (retval != ERROR_OK) + return retval; + + /* Write data page-wise, as suggested in the examples in section + * 28.5.2 "Flash write" of user manual UM11023 in revision 1.1 + * (February 2018). */ + while (count > 0) { + uint32_t next_offset = (offset & ~(QN908X_FLASH_PAGE_SIZE - 1)) + QN908X_FLASH_PAGE_SIZE; + uint32_t chunk_len = next_offset - offset; + if (chunk_len > count) + chunk_len = count; + + if (offset == 0 + && chunk_len >= QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END + && qn908x_info->calc_checksum) { + /* write data prior to checksum */ + retval = target_write_buffer(bank->target, bank->base, + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS, buffer); + if (retval != ERROR_OK) + return retval; + + /* write computed crc checksum instead of provided data */ + retval = target_write_u32(bank->target, bank->base + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS, checksum); + if (retval != ERROR_OK) + return retval; + + retval = target_write_buffer(bank->target, + bank->base + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END, + chunk_len - QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END, + buffer + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END); + } else { + retval = target_write_buffer(bank->target, bank->base + offset, + chunk_len, buffer); + } + + if (retval != ERROR_OK) + return retval; + + keep_alive(); + buffer += chunk_len; + count -= chunk_len; + offset = next_offset; + + /* Wait for FMC to complete write */ + retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + /* Check if FMC reported any errors */ + retval = qn908x_status_check(bank->target); + if (retval != ERROR_OK) + return retval; + } + + return retval; +} + +static int is_flash_protected(struct flash_bank *bank, bool *is_protected) +{ + int retval; + uint32_t lock_stat; + retval = target_read_u32(bank->target, QN908X_FMC_LOCK_STAT_8, &lock_stat); + if (retval) + return retval; + + *is_protected = false; + if (lock_stat & QN908X_FMC_LOCK_STAT_8_PROTECT_ANY) + *is_protected = true; + + return ERROR_OK; +} + +static int qn908x_probe(struct flash_bank *bank) +{ + int retval; + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + uint8_t info_page[QN908X_INFO_PAGE_CRC_END - QN908X_INFO_PAGE_CRC_START]; + qn908x_info->num_blocks = 0; + + /* When the SWD access to the RAM is locked by the LOCK_STAT_8 register we + * can't access the info page to verify the chip/bank version and it will + * read all zeros. This situation prevents the bank from being initialized + * at all so no other operation can be performed. The only option to + * re-flash the chip is to perform a mass_erase from SWD, which can be + * performed even if the mass_erase operation is locked as well. + * We attempt to read the info page and redirect the user to perform a + * mass_erase if we detect this situation. */ + retval = target_read_memory(bank->target, QN908X_INFO_PAGE_CRC_START, + sizeof(uint32_t), sizeof(info_page) / sizeof(uint32_t), + info_page); + if (retval != ERROR_OK) + return retval; + + const uint32_t crc_seed = 0xffffffff; + /* The QN908x uses the standard little endian CRC32 polynomial and all ones + * as seed. The CRC32 is however finalized by one last xor operation that + * is not part of the common CRC32 implementation, so we do that by hand */ + uint32_t computed_crc = crc32_le(CRC32_POLY_LE, crc_seed, + info_page, sizeof(info_page)); + computed_crc ^= crc_seed; + uint32_t read_crc; + retval = target_read_u32(bank->target, QN908X_INFO_PAGE_CRC32, &read_crc); + if (retval != ERROR_OK) + return retval; + + if (computed_crc != read_crc) { + uint32_t info_page_or = 0; + for (unsigned int i = 0; i < sizeof(info_page); i++) + info_page_or |= info_page[i]; + bool is_protected; + retval = is_flash_protected(bank, &is_protected); + if (retval != ERROR_OK) + return retval; + + if (info_page_or == 0 && is_protected) { + LOG_ERROR("The flash or memory in this chip is protected and " + "cannot be accessed from the SWD interface. However, a " + "\"qn908x mass_erase\" can erase the device and lift this " + "protection."); + return ERROR_FAIL; + } + + LOG_ERROR("Flash information page CRC32 mismatch, found 0x%08" + PRIx32 " but computed 0x%08" PRIx32 ". Flash size unknown", + read_crc, computed_crc); + return ERROR_FAIL; + } + + uint32_t flash_size_fld = target_buffer_get_u32(bank->target, + info_page + (QN908X_INFO_PAGE_FLASH_SIZE - QN908X_INFO_PAGE_CRC_START)); + + switch (flash_size_fld) { + case QN908X_FLASH_SIZE_512K: + qn908x_info->num_blocks = 2; + break; + case QN908X_FLASH_SIZE_256K: + qn908x_info->num_blocks = 1; + break; + default: + LOG_ERROR("Unknown Flash size field: 0x%08" PRIx32, + flash_size_fld); + return ERROR_FAIL; + } + + bank->size = qn908x_info->num_blocks * QN908X_FLASH_BLOCK_SIZE; + bank->write_start_alignment = 4; + bank->write_end_alignment = 4; + + /* The flash supports erasing and protecting individual pages. */ + bank->num_sectors = qn908x_info->num_blocks * + QN908X_FLASH_PAGES_PER_BLOCK; + bank->sectors = alloc_block_array(0, QN908X_FLASH_PAGE_SIZE, + bank->num_sectors); + if (!bank->sectors) + return ERROR_FAIL; + + retval = qn908x_init_flash(bank->target); + if (retval != ERROR_OK) + return retval; + + LOG_INFO("Detected flash size: %d KiB", bank->size / 1024); + + return ERROR_OK; +} + +static int qn908x_auto_probe(struct flash_bank *bank) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + if (qn908x_info->num_blocks != 0) + return ERROR_OK; + LOG_DEBUG("auto_probe"); + return qn908x_probe(bank); +} + +static int qn908x_protect_check(struct flash_bank *bank) +{ + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + + int retval = qn908x_read_page_lock(bank); + if (retval != ERROR_OK) + return retval; + + for (uint32_t i = 0; + i < qn908x_info->num_blocks * QN908X_FLASH_PAGES_PER_BLOCK; + i++) { + /* A bit 0 in page_lock means page is locked. */ + bank->sectors[i].is_protected = + ((qn908x_info->page_lock.bits[i / 8] >> (i % 8)) & 1) ^ 1; + } + return ERROR_OK; +} + +static int qn908x_get_info(struct flash_bank *bank, + struct command_invocation *cmd) +{ + uint32_t bootloader_version; + uint32_t chip_id; + uint8_t bluetooth[6]; + int retval; + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + + retval = target_read_u32(bank->target, QN908X_SYSCON_CHIP_ID, &chip_id); + if (retval != ERROR_OK) { + command_print_sameline(cmd, "Cannot read QN908x chip ID."); + return retval; + } + retval = target_read_u32(bank->target, QN908X_INFO_PAGE_BOOTLOADER_VER, + &bootloader_version); + if (retval != ERROR_OK) { + command_print_sameline(cmd, "Cannot read from QN908x info page."); + return retval; + } + + retval = target_read_memory(bank->target, QN908X_INFO_PAGE_BLUETOOTH_ADDR, + 1, sizeof(bluetooth), bluetooth); + if (retval != ERROR_OK) { + command_print_sameline(cmd, "Cannot read QN908x bluetooth L2 address."); + return retval; + } + + command_print_sameline(cmd, "qn908x: chip id: 0x%" PRIx32, chip_id); + + command_print_sameline(cmd, " bdaddr: " + "%02" PRIx8 ":%02" PRIx8 ":%02" PRIx8 + ":%02" PRIx8 ":%02" PRIx8 ":%02" PRIx8, + bluetooth[0], bluetooth[1], bluetooth[2], + bluetooth[3], bluetooth[4], bluetooth[5]); + + command_print_sameline(cmd, " bootloader: %08" PRIx32, bootloader_version); + + command_print_sameline(cmd, " blocks: %" PRIu32, qn908x_info->num_blocks); + + return ERROR_OK; +} + +COMMAND_HANDLER(qn908x_handle_allow_brick_command) +{ + int retval; + + struct target *target = get_current_target(CMD_CTX); + struct flash_bank *bank = NULL; + + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + retval = get_flash_bank_by_addr(target, QN908X_FLASH_BASE, true, &bank); + if (retval != ERROR_OK) + return retval; + + /* If get_flash_bank_by_addr() did not find the flash bank, it should have + * returned and error code instead of ERROR_OK */ + assert(bank); + struct qn908x_flash_bank *qn908x_info = bank->driver_priv; + + LOG_WARNING("Flashing images that disable SWD in qn908x is now allowed."); + qn908x_info->allow_swd_disabled = true; + + return ERROR_OK; +} + +COMMAND_HANDLER(qn908x_handle_disable_wdog_command) +{ + int retval; + struct target *target = get_current_target(CMD_CTX); + + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (target->state != TARGET_HALTED) { + command_print(CMD, "Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* To change any value in the watchdog block (WDT) we need to first write + * 0x1ACCE551 to the LOCK register, and we can then set it back to any other + * value to prevent accidental changes to the watchdog. */ + retval = target_write_u32(target, QN908X_WDT_LOCK, 0x1ACCE551); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(target, QN908X_WDT_CTRL, 0); + if (retval != ERROR_OK) + return retval; + + return target_write_u32(target, QN908X_WDT_LOCK, 0); +} + +COMMAND_HANDLER(qn908x_handle_mass_erase_command) +{ + int retval; + bool keep_lock = false; + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + if (CMD_ARGC == 1) { + if (strcmp("keep_lock", CMD_ARGV[0])) + return ERROR_COMMAND_ARGUMENT_INVALID; + keep_lock = true; + } + + /* This operation can be performed without probing the bank since it is the + * only way to unlock a chip when the flash and ram have been locked. */ + struct target *target = get_current_target(CMD_CTX); + + retval = qn908x_setup_erase(target); + if (retval != ERROR_OK) + return retval; + + /* Check the mass-erase locking status for information purposes only. This + * lock applies to both the SWD and the code running in the core but can be + * bypassed in either case. */ + uint32_t lock_stat_8; + retval = target_read_u32(target, QN908X_FMC_LOCK_STAT_8, &lock_stat_8); + LOG_DEBUG("LOCK_STAT_8 before erasing: 0x%" PRIx32, lock_stat_8); + if (retval != ERROR_OK) + return retval; + if ((lock_stat_8 & QN908X_FMC_LOCK_STAT_8_MASS_ERASE_LOCK_EN) == 0) { + LOG_INFO("mass_erase disabled by Flash lock and protection, forcing " + "mass_erase."); + } + /* Set the DEBUG_PASSWORD so we can force the mass erase from the SWD. We do + * this regardless of the lock status. */ + retval = target_write_u32(target, QN908X_FMC_DEBUG_PASSWORD, 0xCA1E093F); + if (retval != ERROR_OK) + return retval; + + /* Erase both halves of the flash at the same time. These are actually done + * sequentially but we need to send the command to erase both blocks since + * doing so in a locked flash will change the LOCK_STAT_8 register to 0x01, + * allowing us to access the (now erase) flash an memory. Erasing only one + * block at a time does not reset the LOCK_STAT_8 register and therefore + * will not grant access to program the chip. */ + uint32_t erase_cmd = (1u << QN908X_FMC_ERASE_CTRL_HALF_ERASEH_EN_SHIFT) | + (1u << QN908X_FMC_ERASE_CTRL_HALF_ERASEL_EN_SHIFT); + LOG_DEBUG("Erasing both blocks with command 0x%" PRIx32, erase_cmd); + + retval = target_write_u32(target, QN908X_FMC_ERASE_CTRL, erase_cmd); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_wait_for_idle(target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_status_check(target); + if (retval != ERROR_OK) + return retval; + + /* Set the debug password back to 0 to avoid accidental mass_erase. */ + retval = target_write_u32(target, QN908X_FMC_DEBUG_PASSWORD, 0); + if (retval != ERROR_OK) + return retval; + + /* At this point the flash is erased and we are able to write to the flash + * since the LOCK_STAT_8 gets updated to 0x01 after the mass_erase. However, + * after a hard reboot this value will be realoaded from flash which after + * an erase is 0xff. This means that after flashing an image that doesn't + * set the protection bits we end up with a chip that we can't debug. We + * update this value to 0x01 unless "keep_lock" is passed to allow the SWD + * interface to debug the flash and RAM after a hard reset. */ + if (keep_lock) + return retval; + + retval = qn908x_init_flash(target); + if (retval != ERROR_OK) + return retval; + + /* Unlock access to RAM and FLASH in the last page of the flash and + * reloading */ + retval = qn908x_wait_for_idle(target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + uint32_t smart_ctrl = QN908X_FMC_SMART_CTRL_SMART_WRITEH_EN_MASK | + QN908X_FMC_SMART_CTRL_PRGMH_EN_MASK; + retval = target_write_u32(target, QN908X_FMC_SMART_CTRL, smart_ctrl); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(target, QN908X_FLASH_LOCK_ADDR, + QN908X_FLASH_LOCK_ENABLE_MASS_ERASE); + if (retval != ERROR_OK) + return retval; + + retval = qn908x_wait_for_idle(target, QN908X_DEFAULT_TIMEOUT_MS); + if (retval != ERROR_OK) + return retval; + + /* Force a page_lock reload after the mass_erase . */ + retval = qn908x_load_lock_stat(target); + if (retval != ERROR_OK) + return retval; + + return retval; +} + +static const struct command_registration qn908x_exec_command_handlers[] = { + { + .name = "allow_brick", + .handler = qn908x_handle_allow_brick_command, + .mode = COMMAND_EXEC, + .help = "Allow writing images that disable SWD access in their " + "Code Read Protection (CRP) word. Warning: This can make your " + "chip inaccessible from OpenOCD or any other SWD debugger.", + .usage = "", + }, + { + .name = "disable_wdog", + .handler = qn908x_handle_disable_wdog_command, + .mode = COMMAND_EXEC, + .help = "Disabled the watchdog (WDT).", + .usage = "", + }, + { + .name = "mass_erase", + .handler = qn908x_handle_mass_erase_command, + .mode = COMMAND_EXEC, + .help = "Erase the whole flash chip.", + .usage = "[keep_lock]", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration qn908x_command_handlers[] = { + { + .name = "qn908x", + .mode = COMMAND_ANY, + .help = "qn908x flash controller commands", + .usage = "", + .chain = qn908x_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +const struct flash_driver qn908x_flash = { + .name = "qn908x", + .commands = qn908x_command_handlers, + .flash_bank_command = qn908x_flash_bank_command, + .info = qn908x_get_info, + .erase = qn908x_erase, + .protect = qn908x_protect, + .write = qn908x_write, + .read = default_flash_read, + .probe = qn908x_probe, + .auto_probe = qn908x_auto_probe, + .erase_check = default_flash_blank_check, + .protect_check = qn908x_protect_check, + .free_driver_priv = default_flash_free_driver_priv, +}; diff --git a/src/flash/nor/renesas_rpchf.c b/src/flash/nor/renesas_rpchf.c index 145642fbed..6c51b8f670 100644 --- a/src/flash/nor/renesas_rpchf.c +++ b/src/flash/nor/renesas_rpchf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Renesas RCar Gen3 RPC Hyperflash driver diff --git a/src/flash/nor/rp2040.c b/src/flash/nor/rp2040.c deleted file mode 100644 index fb34172d20..0000000000 --- a/src/flash/nor/rp2040.c +++ /dev/null @@ -1,452 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "imp.h" -#include <helper/binarybuffer.h> -#include <target/algorithm.h> -#include <target/armv7m.h> -#include "spi.h" - -/* NOTE THAT THIS CODE REQUIRES FLASH ROUTINES in BOOTROM WITH FUNCTION TABLE PTR AT 0x00000010 - Your gdbinit should load the bootrom.elf if appropriate */ - -/* this is 'M' 'u', 1 (version) */ -#define BOOTROM_MAGIC 0x01754d -#define BOOTROM_MAGIC_ADDR 0x00000010 - -/* Call a ROM function via the debug trampoline - Up to four arguments passed in r0...r3 as per ABI - Function address is passed in r7 - the trampoline is needed because OpenOCD "algorithm" code insists on sw breakpoints. */ - -#define MAKE_TAG(a, b) (((b)<<8) | a) -#define FUNC_DEBUG_TRAMPOLINE MAKE_TAG('D', 'T') -#define FUNC_DEBUG_TRAMPOLINE_END MAKE_TAG('D', 'E') -#define FUNC_FLASH_EXIT_XIP MAKE_TAG('E', 'X') -#define FUNC_CONNECT_INTERNAL_FLASH MAKE_TAG('I', 'F') -#define FUNC_FLASH_RANGE_ERASE MAKE_TAG('R', 'E') -#define FUNC_FLASH_RANGE_PROGRAM MAKE_TAG('R', 'P') -#define FUNC_FLASH_FLUSH_CACHE MAKE_TAG('F', 'C') -#define FUNC_FLASH_ENTER_CMD_XIP MAKE_TAG('C', 'X') - -struct rp2040_flash_bank { - /* flag indicating successful flash probe */ - bool probed; - /* stack used by Boot ROM calls */ - struct working_area *stack; - /* function jump table populated by rp2040_flash_probe() */ - uint16_t jump_debug_trampoline; - uint16_t jump_debug_trampoline_end; - uint16_t jump_flash_exit_xip; - uint16_t jump_connect_internal_flash; - uint16_t jump_flash_range_erase; - uint16_t jump_flash_range_program; - uint16_t jump_flush_cache; - uint16_t jump_enter_cmd_xip; - /* detected model of SPI flash */ - const struct flash_device *dev; -}; - -static uint32_t rp2040_lookup_symbol(struct target *target, uint32_t tag, uint16_t *symbol) -{ - uint32_t magic; - int err = target_read_u32(target, BOOTROM_MAGIC_ADDR, &magic); - if (err != ERROR_OK) - return err; - - magic &= 0xffffff; /* ignore bootrom version */ - if (magic != BOOTROM_MAGIC) { - if (!((magic ^ BOOTROM_MAGIC)&0xffff)) - LOG_ERROR("Incorrect RP2040 BOOT ROM version"); - else - LOG_ERROR("RP2040 BOOT ROM not found"); - return ERROR_FAIL; - } - - /* dereference the table pointer */ - uint16_t table_entry; - err = target_read_u16(target, BOOTROM_MAGIC_ADDR + 4, &table_entry); - if (err != ERROR_OK) - return err; - - uint16_t entry_tag; - do { - err = target_read_u16(target, table_entry, &entry_tag); - if (err != ERROR_OK) - return err; - if (entry_tag == tag) { - /* 16 bit symbol is next */ - return target_read_u16(target, table_entry + 2, symbol); - } - table_entry += 4; - } while (entry_tag); - return ERROR_FAIL; -} - -static int rp2040_call_rom_func(struct target *target, struct rp2040_flash_bank *priv, - uint16_t func_offset, uint32_t argdata[], unsigned int n_args) -{ - char *regnames[4] = { "r0", "r1", "r2", "r3" }; - - assert(n_args <= ARRAY_SIZE(regnames)); /* only allow register arguments */ - - if (!priv->stack) { - LOG_ERROR("no stack for flash programming code"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - target_addr_t stacktop = priv->stack->address + priv->stack->size; - - LOG_DEBUG("Calling ROM func @0x%" PRIx16 " with %d arguments", func_offset, n_args); - LOG_DEBUG("Calling on core \"%s\"", target->cmd_name); - - struct reg_param args[ARRAY_SIZE(regnames) + 2]; - struct armv7m_algorithm alg_info; - - for (unsigned int i = 0; i < n_args; ++i) { - init_reg_param(&args[i], regnames[i], 32, PARAM_OUT); - buf_set_u32(args[i].value, 0, 32, argdata[i]); - } - /* Pass function pointer in r7 */ - init_reg_param(&args[n_args], "r7", 32, PARAM_OUT); - buf_set_u32(args[n_args].value, 0, 32, func_offset); - init_reg_param(&args[n_args + 1], "sp", 32, PARAM_OUT); - buf_set_u32(args[n_args + 1].value, 0, 32, stacktop); - - - for (unsigned int i = 0; i < n_args + 2; ++i) - LOG_DEBUG("Set %s = 0x%" PRIx32, args[i].reg_name, buf_get_u32(args[i].value, 0, 32)); - - /* Actually call the function */ - alg_info.common_magic = ARMV7M_COMMON_MAGIC; - alg_info.core_mode = ARM_MODE_THREAD; - int err = target_run_algorithm( - target, - 0, NULL, /* No memory arguments */ - n_args + 1, args, /* User arguments + r7 */ - priv->jump_debug_trampoline, priv->jump_debug_trampoline_end, - 3000, /* 3s timeout */ - &alg_info - ); - for (unsigned int i = 0; i < n_args + 2; ++i) - destroy_reg_param(&args[i]); - if (err != ERROR_OK) - LOG_ERROR("Failed to invoke ROM function @0x%" PRIx16 "\n", func_offset); - return err; - -} - -static int stack_grab_and_prep(struct flash_bank *bank) -{ - struct rp2040_flash_bank *priv = bank->driver_priv; - - /* target_alloc_working_area always allocates multiples of 4 bytes, so no worry about alignment */ - const int STACK_SIZE = 256; - int err = target_alloc_working_area(bank->target, STACK_SIZE, &priv->stack); - if (err != ERROR_OK) { - LOG_ERROR("Could not allocate stack for flash programming code"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - LOG_DEBUG("Connecting internal flash"); - err = rp2040_call_rom_func(bank->target, priv, priv->jump_connect_internal_flash, NULL, 0); - if (err != ERROR_OK) { - LOG_ERROR("RP2040 erase: failed to connect internal flash"); - return err; - } - - LOG_DEBUG("Kicking flash out of XIP mode"); - err = rp2040_call_rom_func(bank->target, priv, priv->jump_flash_exit_xip, NULL, 0); - if (err != ERROR_OK) { - LOG_ERROR("RP2040 erase: failed to exit flash XIP mode"); - return err; - } - - return ERROR_OK; -} - -static int rp2040_flash_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) -{ - LOG_DEBUG("Writing %d bytes starting at 0x%" PRIx32, count, offset); - - struct rp2040_flash_bank *priv = bank->driver_priv; - struct target *target = bank->target; - struct working_area *bounce; - - int err = stack_grab_and_prep(bank); - if (err != ERROR_OK) - return err; - - const unsigned int chunk_size = target_get_working_area_avail(target); - if (target_alloc_working_area(target, chunk_size, &bounce) != ERROR_OK) { - LOG_ERROR("Could not allocate bounce buffer for flash programming. Can't continue"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address); - - while (count > 0) { - uint32_t write_size = count > chunk_size ? chunk_size : count; - LOG_DEBUG("Writing %d bytes to offset 0x%" PRIx32, write_size, offset); - err = target_write_buffer(target, bounce->address, write_size, buffer); - if (err != ERROR_OK) { - LOG_ERROR("Could not load data into target bounce buffer"); - break; - } - uint32_t args[3] = { - offset, /* addr */ - bounce->address, /* data */ - write_size /* count */ - }; - err = rp2040_call_rom_func(target, priv, priv->jump_flash_range_program, args, ARRAY_SIZE(args)); - if (err != ERROR_OK) { - LOG_ERROR("Failed to invoke flash programming code on target"); - break; - } - - buffer += write_size; - offset += write_size; - count -= write_size; - } - target_free_working_area(target, bounce); - - if (err != ERROR_OK) - return err; - - /* Flash is successfully programmed. We can now do a bit of poking to make the flash - contents visible to us via memory-mapped (XIP) interface in the 0x1... memory region */ - LOG_DEBUG("Flushing flash cache after write behind"); - err = rp2040_call_rom_func(bank->target, priv, priv->jump_flush_cache, NULL, 0); - if (err != ERROR_OK) { - LOG_ERROR("RP2040 write: failed to flush flash cache"); - return err; - } - LOG_DEBUG("Configuring SSI for execute-in-place"); - err = rp2040_call_rom_func(bank->target, priv, priv->jump_enter_cmd_xip, NULL, 0); - if (err != ERROR_OK) - LOG_ERROR("RP2040 write: failed to flush flash cache"); - return err; -} - -static int rp2040_flash_erase(struct flash_bank *bank, unsigned int first, unsigned int last) -{ - struct rp2040_flash_bank *priv = bank->driver_priv; - uint32_t start_addr = bank->sectors[first].offset; - uint32_t length = bank->sectors[last].offset + bank->sectors[last].size - start_addr; - LOG_DEBUG("RP2040 erase %d bytes starting at 0x%" PRIx32, length, start_addr); - - int err = stack_grab_and_prep(bank); - if (err != ERROR_OK) - return err; - - LOG_DEBUG("Remote call flash_range_erase"); - - uint32_t args[4] = { - bank->sectors[first].offset, /* addr */ - bank->sectors[last].offset + bank->sectors[last].size - bank->sectors[first].offset, /* count */ - priv->dev->sectorsize, /* block_size */ - priv->dev->erase_cmd /* block_cmd */ - }; - - /* - The RP2040 Boot ROM provides a _flash_range_erase() API call documented in Section 2.8.3.1.3: - https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf - and the particular source code for said Boot ROM function can be found here: - https://github.com/raspberrypi/pico-bootrom/blob/master/bootrom/program_flash_generic.c - - In theory, the function algorithm provides for erasing both a smaller "sector" (4096 bytes) and - an optional larger "block" (size and command provided in args). OpenOCD's spi.c only uses "block" sizes. - */ - - err = rp2040_call_rom_func(bank->target, priv, priv->jump_flash_range_erase, args, ARRAY_SIZE(args)); - - return err; -} - -/* ----------------------------------------------------------------------------- - Driver probing etc */ - -static int rp2040_ssel_active(struct target *target, bool active) -{ - const target_addr_t qspi_ctrl_addr = 0x4001800c; - const uint32_t qspi_ctrl_outover_low = 2UL << 8; - const uint32_t qspi_ctrl_outover_high = 3UL << 8; - uint32_t state = (active) ? qspi_ctrl_outover_low : qspi_ctrl_outover_high; - uint32_t val; - - int err = target_read_u32(target, qspi_ctrl_addr, &val); - if (err != ERROR_OK) - return err; - - val = (val & ~qspi_ctrl_outover_high) | state; - - err = target_write_u32(target, qspi_ctrl_addr, val); - if (err != ERROR_OK) - return err; - - return ERROR_OK; -} - -static int rp2040_flash_probe(struct flash_bank *bank) -{ - struct rp2040_flash_bank *priv = bank->driver_priv; - struct target *target = bank->target; - - int err = rp2040_lookup_symbol(target, FUNC_DEBUG_TRAMPOLINE, &priv->jump_debug_trampoline); - if (err != ERROR_OK) { - LOG_ERROR("Debug trampoline not found in RP2040 ROM."); - return err; - } - priv->jump_debug_trampoline &= ~1u; /* mask off thumb bit */ - - err = rp2040_lookup_symbol(target, FUNC_DEBUG_TRAMPOLINE_END, &priv->jump_debug_trampoline_end); - if (err != ERROR_OK) { - LOG_ERROR("Debug trampoline end not found in RP2040 ROM."); - return err; - } - priv->jump_debug_trampoline_end &= ~1u; /* mask off thumb bit */ - - err = rp2040_lookup_symbol(target, FUNC_FLASH_EXIT_XIP, &priv->jump_flash_exit_xip); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_FLASH_EXIT_XIP not found in RP2040 ROM."); - return err; - } - - err = rp2040_lookup_symbol(target, FUNC_CONNECT_INTERNAL_FLASH, &priv->jump_connect_internal_flash); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_CONNECT_INTERNAL_FLASH not found in RP2040 ROM."); - return err; - } - - err = rp2040_lookup_symbol(target, FUNC_FLASH_RANGE_ERASE, &priv->jump_flash_range_erase); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_FLASH_RANGE_ERASE not found in RP2040 ROM."); - return err; - } - - err = rp2040_lookup_symbol(target, FUNC_FLASH_RANGE_PROGRAM, &priv->jump_flash_range_program); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_FLASH_RANGE_PROGRAM not found in RP2040 ROM."); - return err; - } - - err = rp2040_lookup_symbol(target, FUNC_FLASH_FLUSH_CACHE, &priv->jump_flush_cache); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_FLASH_FLUSH_CACHE not found in RP2040 ROM."); - return err; - } - - err = rp2040_lookup_symbol(target, FUNC_FLASH_ENTER_CMD_XIP, &priv->jump_enter_cmd_xip); - if (err != ERROR_OK) { - LOG_ERROR("Function FUNC_FLASH_ENTER_CMD_XIP not found in RP2040 ROM."); - return err; - } - - err = stack_grab_and_prep(bank); - if (err != ERROR_OK) - return err; - - uint32_t device_id = 0; - const target_addr_t ssi_dr0 = 0x18000060; - - err = rp2040_ssel_active(target, true); - - /* write RDID request into SPI peripheral's FIFO */ - for (int count = 0; (count < 4) && (err == ERROR_OK); count++) - err = target_write_u32(target, ssi_dr0, SPIFLASH_READ_ID); - - /* by this time, there is a receive FIFO entry for every write */ - for (int count = 0; (count < 4) && (err == ERROR_OK); count++) { - uint32_t status; - err = target_read_u32(target, ssi_dr0, &status); - - device_id >>= 8; - device_id |= (status & 0xFF) << 24; - } - device_id >>= 8; - - err = rp2040_ssel_active(target, false); - if (err != ERROR_OK) { - LOG_ERROR("SSEL inactive failed"); - return err; - } - - /* search for a SPI flash Device ID match */ - priv->dev = NULL; - for (const struct flash_device *p = flash_devices; p->name ; p++) - if (p->device_id == device_id) { - priv->dev = p; - break; - } - - if (!priv->dev) { - LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", device_id); - return ERROR_FAIL; - } - - LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")", - priv->dev->name, priv->dev->device_id); - - /* the Boot ROM flash_range_program() routine requires page alignment */ - bank->write_start_alignment = priv->dev->pagesize; - bank->write_end_alignment = priv->dev->pagesize; - - bank->size = priv->dev->size_in_bytes; - - bank->num_sectors = bank->size / priv->dev->sectorsize; - LOG_INFO("RP2040 B0 Flash Probe: %d bytes @" TARGET_ADDR_FMT ", in %d sectors\n", - bank->size, bank->base, bank->num_sectors); - bank->sectors = alloc_block_array(0, priv->dev->sectorsize, bank->num_sectors); - if (!bank->sectors) - return ERROR_FAIL; - - if (err == ERROR_OK) - priv->probed = true; - - return err; -} - -static int rp2040_flash_auto_probe(struct flash_bank *bank) -{ - struct rp2040_flash_bank *priv = bank->driver_priv; - - if (priv->probed) - return ERROR_OK; - - return rp2040_flash_probe(bank); -} - -static void rp2040_flash_free_driver_priv(struct flash_bank *bank) -{ - free(bank->driver_priv); - bank->driver_priv = NULL; -} - -/* ----------------------------------------------------------------------------- - Driver boilerplate */ - -FLASH_BANK_COMMAND_HANDLER(rp2040_flash_bank_command) -{ - struct rp2040_flash_bank *priv; - priv = malloc(sizeof(struct rp2040_flash_bank)); - priv->probed = false; - - /* Set up driver_priv */ - bank->driver_priv = priv; - - return ERROR_OK; -} - -struct flash_driver rp2040_flash = { - .name = "rp2040_flash", - .flash_bank_command = rp2040_flash_bank_command, - .erase = rp2040_flash_erase, - .write = rp2040_flash_write, - .read = default_flash_read, - .probe = rp2040_flash_probe, - .auto_probe = rp2040_flash_auto_probe, - .erase_check = default_flash_blank_check, - .free_driver_priv = rp2040_flash_free_driver_priv -}; diff --git a/src/flash/nor/rp2xxx.c b/src/flash/nor/rp2xxx.c new file mode 100644 index 0000000000..30c6e99141 --- /dev/null +++ b/src/flash/nor/rp2xxx.c @@ -0,0 +1,1486 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "imp.h" +#include <helper/binarybuffer.h> +#include <target/algorithm.h> +#include <target/armv7m.h> +#include "spi.h" +#include "sfdp.h" +#include <target/cortex_m.h> + +/* this is 'M' 'u', 1 (version) */ +#define BOOTROM_RP2040_MAGIC 0x01754d +/* this is 'M' 'u', 2 (version) */ +#define BOOTROM_RP2350_MAGIC 0x02754d +#define BOOTROM_MAGIC_MASK 0xffffff +#define BOOTROM_MAGIC_ADDR 0x00000010 + +#define MAKE_TAG(a, b) (((b)<<8) | a) +#define FUNC_FLASH_EXIT_XIP MAKE_TAG('E', 'X') +#define FUNC_CONNECT_INTERNAL_FLASH MAKE_TAG('I', 'F') +#define FUNC_FLASH_RANGE_ERASE MAKE_TAG('R', 'E') +#define FUNC_FLASH_RANGE_PROGRAM MAKE_TAG('R', 'P') +#define FUNC_FLASH_FLUSH_CACHE MAKE_TAG('F', 'C') +#define FUNC_FLASH_ENTER_CMD_XIP MAKE_TAG('C', 'X') +#define FUNC_BOOTROM_STATE_RESET MAKE_TAG('S', 'R') +#define FUNC_BOOTROM_SET_STACK MAKE_TAG('S', 'S') +#define FUNC_FLASH_RESET_ADDRESS_TRANS MAKE_TAG('R', 'A') + +/* ROM table flags for RP2350 A1 ROM onwards */ +#define RT_FLAG_FUNC_RISCV 0x01 +#define RT_FLAG_FUNC_ARM_SEC 0x04 +#define RT_FLAG_FUNC_ARM_NONSEC 0x10 +#define RT_FLAG_DATA 0x40 + +// these form a bit set +#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01 +#define BOOTROM_STATE_RESET_OTHER_CORE 0x02 +#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 + +#define ACCESSCTRL_LOCK_OFFSET 0x40060000u +#define ACCESSCTRL_CFGRESET_OFFSET 0x40060008u +#define ACCESSCTRL_GPIO_NSMASK0_OFFSET 0x4006000cu +#define ACCESSCTRL_GPIO_ROM_OFFSET 0x40060014u +#define ACCESSCTRL_GPIO_XIP_AUX_OFFSET 0x400600e8u + +#define ACCESSCTRL_SAVE_BASE ACCESSCTRL_GPIO_NSMASK0_OFFSET +#define ACCESSCTRL_SAVE_SIZE \ + (ACCESSCTRL_GPIO_XIP_AUX_OFFSET + 4 - ACCESSCTRL_SAVE_BASE) + +#define ACCESSCTRL_LOCK_DEBUG_BITS 0x00000008u +#define ACCESSCTRL_WRITE_PASSWORD 0xacce0000u + +#define RP2040_SSI_DR0 0x18000060 +#define RP2040_QSPI_CTRL 0x4001800c + +#define RP2040_QSPI_CTRL_OUTOVER_MASK (3ul << 8) +#define RP2040_QSPI_CTRL_OUTOVER_LOW (2ul << 8) +#define RP2040_QSPI_CTRL_OUTOVER_HIGH (3ul << 8) + +#define RP2350_QMI_DIRECT_CSR 0x400d0000 +#define RP2350_QMI_DIRECT_TX 0x400d0004 +#define RP2350_QMI_DIRECT_RX 0x400d0008 + +#define RP2350_QMI_DIRECT_CSR_EN BIT(0) +#define RP2350_QMI_DIRECT_CSR_ASSERT_CS0N BIT(2) +#define RP2350_QMI_DIRECT_TX_NOPUSH BIT(20) +#define RP2350_QMI_DIRECT_TX_OE BIT(19) + +#define RP2XXX_SYSINFO_CHIP_ID 0x40000000 +#define RP2XXX_CHIP_ID_PART_MANUFACTURER(id) ((id) & 0x0fffffff) +#define RP2XXX_CHIP_ID_MANUFACTURER 0x493 +#define RP2XXX_MK_PART(part) (((part) << 12) | (RP2XXX_CHIP_ID_MANUFACTURER << 1) | 1) +#define RP2040_CHIP_ID_PART 0x0002 +#define IS_RP2040(id) (RP2XXX_CHIP_ID_PART_MANUFACTURER(id) == RP2XXX_MK_PART(RP2040_CHIP_ID_PART)) +#define RP2350_CHIP_ID_PART 0x0004 +#define IS_RP2350(id) (RP2XXX_CHIP_ID_PART_MANUFACTURER(id) == RP2XXX_MK_PART(RP2350_CHIP_ID_PART)) +#define RP2XXX_CHIP_ID_REVISION(id) ((id) >> 28) + +#define RP2XXX_MAX_ALGO_STACK_USAGE 1024 +#define RP2XXX_MAX_RAM_ALGO_SIZE 1024 + +#define RP2XXX_ROM_API_FIXED_FLASH_PAGE 256 +#define RP2XXX_ROM_API_FIXED_FLASH_SECTOR 4096 + +// Calling bootrom functions on Arm RP2350 requires the redundancy +// coprocessor (RCP) to be initialised. Usually this is done first thing by +// the bootrom, but the debugger may skip this, e.g. by resetting the cores +// and then running a NO_FLASH binary, or by reset-halting the cores before +// flash programming. +// +// The first case can be handled by a stub in the binary itself to initialise +// the RCP with dummy values if the bootrom has not already initialised it. +// (Note this case is only reachable via the debugger.) The second case +// requires the debugger itself to initialise the RCP, using this stub code: + +static const int rcp_init_code_bkpt_offset = 24; +static const uint8_t rcp_init_code[] = { + // Just enable the RCP which is fine if it already was (we assume no other + // co-processors are enabled at this point to save space) + 0x06, 0x48, // ldr r0, = PPB_BASE + M33_CPACR_OFFSET + 0x5f, 0xf4, 0x40, 0x41, // movs r1, #M33_CPACR_CP7_BITS + 0x01, 0x60, // str r1, [r0] + // Only initialize canary seeds if they haven't been (as to do so twice is a fault) + 0x30, 0xee, 0x10, 0xf7, // mrc p7, #1, r15, c0, c0, #0 + 0x04, 0xd4, // bmi 1f + // Todo should we use something random here and pass it into the algorithm? + 0x40, 0xec, 0x80, 0x07, // mcrr p7, #8, r0, r0, c0 + 0x40, 0xec, 0x81, 0x07, // mcrr p7, #8, r0, r0, c1 + // Let other core know + 0x40, 0xbf, // sev + // 1: + 0x00, 0xbe, // bkpt (end of algorithm) + 0x00, 0x00, // pad + 0x88, 0xed, 0x00, 0xe0 // PPB_BASE + M33_CPACR_OFFSET +}; + +// An algorithm stub that can be concatenated with a null-terminated list of +// (PC, SP, r0-r3) records to perform a batch of ROM calls under a single +// OpenOCD algorithm call, to save on algorithm overhead: +#define ROM_CALL_BATCH_ALGO_SIZE_BYTES 32 +static const int rp2xxx_rom_call_batch_algo_bkpt_offset = ROM_CALL_BATCH_ALGO_SIZE_BYTES - 2; +static const uint8_t rp2xxx_rom_call_batch_algo_armv6m[ROM_CALL_BATCH_ALGO_SIZE_BYTES] = { +// <_start>: + 0x07, 0xa7, // add r7, pc, #28 ; (adr r7, 20 <_args>) +// <_do_next>: + 0x10, 0xcf, // ldmia r7!, {r4} + 0x00, 0x2c, // cmp r4, #0 + 0x0a, 0xd0, // beq.n 1e <_done> + 0x20, 0xcf, // ldmia r7!, {r5} + 0xad, 0x46, // mov sp, r5 + 0x0f, 0xcf, // ldmia r7!, {r0, r1, r2, r3} + 0xa0, 0x47, // blx r4 + 0xf7, 0xe7, // b.n 2 <_do_next> + 0xc0, 0x46, // nop + 0xc0, 0x46, // nop + 0xc0, 0x46, // nop + 0xc0, 0x46, // nop + 0xc0, 0x46, // nop + 0xc0, 0x46, // nop +// <_done>: + 0x00, 0xbe, // bkpt 0x0000 +// <_args>: +}; + +// The same as rom_call_batch_algo_armv6m, but clearing stack limits before setting stack: +static const uint8_t rp2xxx_rom_call_batch_algo_armv8m[ROM_CALL_BATCH_ALGO_SIZE_BYTES] = { +// <_start>: + 0x07, 0xa7, // add r7, pc, #28 ; (adr r7, 20 <_args>) + 0x00, 0x20, // movs r0, #0 + 0x80, 0xf3, 0x0a, 0x88, // msr MSPLIM, r0 + 0x80, 0xf3, 0x0b, 0x88, // msr PSPLIM, r0 +// <_do_next>: + 0x10, 0xcf, // ldmia r7!, {r4} + 0x00, 0x2c, // cmp r4, #0 + 0x05, 0xd0, // beq.n 1e <_done> + 0x20, 0xcf, // ldmia r7!, {r5} + 0xad, 0x46, // mov sp, r5 + 0x0f, 0xcf, // ldmia r7!, {r0, r1, r2, r3} + 0xa0, 0x47, // blx r4 + 0xf7, 0xe7, // b.n c <_do_next> + 0xc0, 0x46, // nop +// <_done>: + 0x00, 0xbe, // bkpt 0x0000 +// <_args>: +}; + +// The same as rom_call_batch_algo_armv6m, but placing arguments in a0-a3 on RISC-V: +static const uint8_t rp2xxx_rom_call_batch_algo_riscv[ROM_CALL_BATCH_ALGO_SIZE_BYTES] = { +// <_start>: + 0x97, 0x04, 0x00, 0x00, // auipc s1,0 + 0x93, 0x84, 0x04, 0x02, // add s1,s1,32 # 20 <_args> +// <_do_next>: + 0x98, 0x40, // lw a4,0(s1) + 0x11, 0xcb, // beqz a4,1e <_done> + 0x03, 0xa1, 0x44, 0x00, // lw sp,4(s1) + 0x88, 0x44, // lw a0,8(s1) + 0xcc, 0x44, // lw a1,12(s1) + 0x90, 0x48, // lw a2,16(s1) + 0xd4, 0x48, // lw a3,20(s1) + 0xe1, 0x04, // add s1,s1,24 + 0x02, 0x97, // jalr a4 + 0xf5, 0xb7, // j 8 <_do_next> +// <_done>: + 0x02, 0x90, // ebreak +// <_args>: +}; + +struct rp2xxx_rom_call_batch_record { + uint32_t pc; + uint32_t sp; + uint32_t args[4]; +}; + +struct rp2xxx_flash_bank { + bool probed; /* flag indicating successful flash probe */ + uint32_t id; /* cached SYSINFO CHIP_ID */ + struct working_area *stack; /* stack used by Boot ROM calls */ + /* static code scratchpad used for RAM algorithms -- allocated in advance + so that higher-level calls can just grab all remaining workarea: */ + struct working_area *ram_algo_space; + /* function jump table populated by rp2xxx_flash_probe() */ + uint16_t jump_flash_exit_xip; + uint16_t jump_connect_internal_flash; + uint16_t jump_flash_range_erase; + uint16_t jump_flash_range_program; + uint16_t jump_flush_cache; + uint16_t jump_flash_reset_address_trans; + uint16_t jump_enter_cmd_xip; + uint16_t jump_bootrom_reset_state; + uint16_t jump_bootrom_set_varm_stack; + + char dev_name[20]; + bool size_override; + struct flash_device spi_dev; /* detected model of SPI flash */ + unsigned int sfdp_dummy, sfdp_dummy_detect; + + struct cortex_m_saved_security saved_security; + bool accessctrl_dirty; + uint8_t saved_accessctrl[ACCESSCTRL_SAVE_SIZE]; /* in target byte order */ +}; + +#ifndef LOG_ROM_SYMBOL_DEBUG +#define LOG_ROM_SYMBOL_DEBUG LOG_DEBUG +#endif + +static int rp2040_lookup_rom_symbol(struct target *target, uint16_t tag, uint16_t flags, uint16_t *symbol_out) +{ + LOG_ROM_SYMBOL_DEBUG("Looking up ROM symbol '%c%c' in RP2040 table", tag & 0xff, (tag >> 8) & 0xff); + if (flags != RT_FLAG_FUNC_ARM_SEC && flags != RT_FLAG_DATA) { + /* Note RT flags do not exist on RP2040, so just sanity check that we + are asked for a type of thing that actually exists in the ROM table */ + LOG_ERROR("Only data and Secure Arm functions can be looked up in RP2040 ROM table"); + return ERROR_FAIL; + } + + uint16_t ptr_to_entry; + unsigned int offset_magic_to_table_ptr = flags == RT_FLAG_DATA ? 6 : 4; + int err = target_read_u16(target, BOOTROM_MAGIC_ADDR + offset_magic_to_table_ptr, &ptr_to_entry); + if (err != ERROR_OK) + return err; + + uint16_t entry_tag; + do { + err = target_read_u16(target, ptr_to_entry, &entry_tag); + if (err != ERROR_OK) + return err; + + if (entry_tag == tag) { + /* 16 bit symbol is next */ + err = target_read_u16(target, ptr_to_entry + 2, symbol_out); + if (err != ERROR_OK) + return err; + + LOG_ROM_SYMBOL_DEBUG(" -> found: 0x%04" PRIx16, *symbol_out); + return ERROR_OK; + } + ptr_to_entry += 4; + } while (entry_tag); + *symbol_out = 0; + return ERROR_FAIL; +} + +static int rp2350_a0_lookup_symbol(struct target *target, uint16_t tag, uint16_t flags, uint16_t *symbol_out) +{ + LOG_ROM_SYMBOL_DEBUG("Looking up ROM symbol '%c%c' in RP2350 A0 table", tag & 0xff, (tag >> 8) & 0xff); + + /* RP2350 A0 table format is the same as RP2040 except with 16 bits of + flags after each 16-bit pointer. We ignore the flags, as each symbol + only has one datum associated with it. */ + + uint32_t magic_ptr = BOOTROM_MAGIC_ADDR; + if (flags == RT_FLAG_FUNC_RISCV) { + /* RP2350 A0 used split function tables for Arm/RISC-V -- not used on + any other device or any other version of this device. There is a + well-known RISC-V table at the top of ROM, matching the well-known + Arm table at the bottom of ROM. */ + magic_ptr = 0x7decu; + } else if (flags != RT_FLAG_FUNC_ARM_SEC) { + LOG_WARNING("Ignoring non-default flags for RP2350 A0 lookup, hope you like Secure Arm functions"); + } + + uint16_t ptr_to_entry; + const unsigned int offset_magic_to_table_ptr = 4; + int err = target_read_u16(target, magic_ptr + offset_magic_to_table_ptr, &ptr_to_entry); + if (err != ERROR_OK) + return err; + + uint16_t entry_tag; + do { + err = target_read_u16(target, ptr_to_entry, &entry_tag); + if (err != ERROR_OK) + return err; + + if (entry_tag == tag) { + err = target_read_u16(target, ptr_to_entry + 2, symbol_out); + if (err != ERROR_OK) + return err; + + LOG_ROM_SYMBOL_DEBUG(" -> found: 0x%04" PRIx16, *symbol_out); + return ERROR_OK; + } + ptr_to_entry += 6; + } while (entry_tag); + *symbol_out = 0; + return ERROR_FAIL; +} + +static int rp2350_lookup_rom_symbol(struct target *target, uint32_t ptr_to_entry, + uint16_t tag, uint16_t flags, uint16_t *symbol_out) +{ + LOG_ROM_SYMBOL_DEBUG("Looking up ROM symbol '%c%c' in RP2350 A1 table", tag & 0xff, (tag >> 8) & 0xff); + + /* On RP2350 A1, Each entry has a flag bitmap identifying the type of its + contents. The entry contains one halfword of data for each set flag + bit. There may be both Arm and RISC-V entries under the same tag, or + separate Arm Secure/NonSecure entries (or all three, why not). */ + + while (true) { + uint16_t entry_tag, entry_flags; + + int err = target_read_u16(target, ptr_to_entry, &entry_tag); + if (err != ERROR_OK) + return err; + + if (entry_tag == 0) { + *symbol_out = 0; + return ERROR_FAIL; + } + ptr_to_entry += 2; + + err = target_read_u16(target, ptr_to_entry, &entry_flags); + if (err != ERROR_OK) + return err; + + ptr_to_entry += 2; + + uint16_t matching_flags = flags & entry_flags; + + if (tag == entry_tag && matching_flags != 0) { + /* This is our entry, seek to the correct data item and return it. */ + bool is_riscv_func = matching_flags & RT_FLAG_FUNC_RISCV; + while (!(matching_flags & 1)) { + if (entry_flags & 1) + ptr_to_entry += 2; + + matching_flags >>= 1; + entry_flags >>= 1; + } + if (is_riscv_func) { + /* For RISC-V, the table entry itself is the entry point -- trick + to make shared function implementations smaller */ + *symbol_out = ptr_to_entry; + return ERROR_OK; + } + err = target_read_u16(target, ptr_to_entry, symbol_out); + if (err != ERROR_OK) + return err; + + LOG_ROM_SYMBOL_DEBUG(" -> found: 0x%04" PRIx16, *symbol_out); + return ERROR_OK; + } + /* Skip past this entry */ + while (entry_flags) { + if (entry_flags & 1) + ptr_to_entry += 2; + + entry_flags >>= 1; + } + } +} + +static int rp2xxx_lookup_rom_symbol(struct target *target, uint16_t tag, uint16_t flags, uint16_t *symbol_out) +{ + uint32_t magic; + int err = target_read_u32(target, BOOTROM_MAGIC_ADDR, &magic); + if (err != ERROR_OK) + return err; + + /* Ignore version */ + magic &= BOOTROM_MAGIC_MASK; + + if (magic == BOOTROM_RP2350_MAGIC) { + /* Distinguish old-style RP2350 ROM table (A0, and earlier A1 builds) + based on position of table -- a high address means it is shared with + RISC-V, i.e. new-style. */ + uint16_t table_ptr; + err = target_read_u16(target, BOOTROM_MAGIC_ADDR + 4, &table_ptr); + if (err != ERROR_OK) + return err; + if (table_ptr < 0x7c00) + return rp2350_a0_lookup_symbol(target, tag, flags, symbol_out); + else + return rp2350_lookup_rom_symbol(target, table_ptr, tag, flags, symbol_out); + + } else if (magic == BOOTROM_RP2040_MAGIC) { + return rp2040_lookup_rom_symbol(target, tag, flags, symbol_out); + } + LOG_ERROR("RP2040/RP2350 BOOT ROM not found"); + return ERROR_FAIL; +} + +static int rp2xxx_populate_rom_pointer_cache(struct target *target, struct rp2xxx_flash_bank *priv) +{ + uint16_t symtype_func = is_arm(target_to_arm(target)) + ? RT_FLAG_FUNC_ARM_SEC : RT_FLAG_FUNC_RISCV; + int err; + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_EXIT_XIP, + symtype_func, &priv->jump_flash_exit_xip); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_FLASH_EXIT_XIP not found in RP2xxx ROM"); + return err; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_CONNECT_INTERNAL_FLASH, + symtype_func, &priv->jump_connect_internal_flash); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_CONNECT_INTERNAL_FLASH not found in RP2xxx ROM"); + return err; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_RANGE_ERASE, symtype_func, &priv->jump_flash_range_erase); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_FLASH_RANGE_ERASE not found in RP2xxx ROM"); + return err; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_RANGE_PROGRAM, symtype_func, &priv->jump_flash_range_program); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_FLASH_RANGE_PROGRAM not found in RP2xxx ROM"); + return err; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_FLUSH_CACHE, symtype_func, &priv->jump_flush_cache); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_FLASH_FLUSH_CACHE not found in RP2xxx ROM"); + return err; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_ENTER_CMD_XIP, symtype_func, &priv->jump_enter_cmd_xip); + if (err != ERROR_OK) { + LOG_ERROR("Function FUNC_FLASH_ENTER_CMD_XIP not found in RP2xxx ROM"); + return err; + } + + // From this point are optional functions which do not exist on e.g. RP2040 + // or pre-production RP2350 ROM versions: + if (IS_RP2040(priv->id)) { + priv->jump_bootrom_reset_state = 0; + priv->jump_flash_reset_address_trans = 0; + return ERROR_OK; + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_BOOTROM_STATE_RESET, symtype_func, &priv->jump_bootrom_reset_state); + if (err != ERROR_OK) { + priv->jump_bootrom_reset_state = 0; + LOG_WARNING("Function FUNC_BOOTROM_STATE_RESET not found in RP2xxx ROM. (probably an RP2350 A0)"); + } + + if (!is_arm(target_to_arm(target))) { + err = rp2xxx_lookup_rom_symbol(target, FUNC_BOOTROM_SET_STACK, symtype_func, + &priv->jump_bootrom_set_varm_stack); + if (err != ERROR_OK) { + priv->jump_bootrom_set_varm_stack = 0; + LOG_WARNING("Function FUNC_BOOTROM_SET_STACK not found in RP2xxx ROM. (probably an RP2350 A0)"); + } + } + + err = rp2xxx_lookup_rom_symbol(target, FUNC_FLASH_RESET_ADDRESS_TRANS, + symtype_func, &priv->jump_flash_reset_address_trans); + if (err != ERROR_OK) { + priv->jump_flash_reset_address_trans = 0; + LOG_WARNING("Function FUNC_FLASH_RESET_ADDRESS_TRANS not found in RP2xxx ROM. (probably an RP2350 A0)"); + } + return ERROR_OK; +} + +// Call a list of PC + SP + r0-r3 function call tuples with a single OpenOCD +// algorithm invocation, to amortise the algorithm overhead over multiple calls: +static int rp2xxx_call_rom_func_batch(struct target *target, struct rp2xxx_flash_bank *priv, + struct rp2xxx_rom_call_batch_record *calls, unsigned int n_calls) +{ + // Note + sizeof(uint32_t) is for the null terminator + unsigned int batch_size = ROM_CALL_BATCH_ALGO_SIZE_BYTES + + n_calls * sizeof(struct rp2xxx_rom_call_batch_record) + + sizeof(uint32_t); + + if (!priv->ram_algo_space) { + LOG_ERROR("No RAM code space allocated for ROM call"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + if (priv->ram_algo_space->size < batch_size) { + LOG_ERROR("RAM code space too small for call batch size of %u", n_calls); + return ERROR_BUF_TOO_SMALL; + } + + LOG_TARGET_DEBUG(target, "Calling batch of %u ROM functions:", n_calls); + for (unsigned int i = 0; i < n_calls; ++i) { + LOG_DEBUG(" func @ %" PRIx32, calls[i].pc); + LOG_DEBUG(" sp = %" PRIx32, calls[i].sp); + for (unsigned int j = 0; j < 4; ++j) + LOG_DEBUG(" a%u = %" PRIx32, j, calls[i].args[j]); + } + + if (n_calls <= 0) { + LOG_DEBUG("Returning early from call of 0 ROM functions"); + return ERROR_OK; + } + + const uint8_t *algo_code; + if (is_arm(target_to_arm(target))) { + if (target_to_arm(target)->arch == ARM_ARCH_V8M) { + LOG_DEBUG("Using algo: rp2xxx_rom_call_batch_algo_armv8m"); + algo_code = rp2xxx_rom_call_batch_algo_armv8m; + } else { + LOG_DEBUG("Using algo: rp2xxx_rom_call_batch_algo_armv6m"); + algo_code = rp2xxx_rom_call_batch_algo_armv6m; + } + } else { + LOG_DEBUG("Using algo: rp2xxx_rom_call_batch_algo_riscv"); + algo_code = rp2xxx_rom_call_batch_algo_riscv; + } + + uint8_t *batch_bf = malloc(batch_size); + if (!batch_bf) { + LOG_ERROR("No memory for batch buffer"); + return ERROR_FAIL; + } + memcpy(batch_bf, algo_code, ROM_CALL_BATCH_ALGO_SIZE_BYTES); + unsigned int words = n_calls * sizeof(struct rp2xxx_rom_call_batch_record) + / sizeof(uint32_t); + target_buffer_set_u32_array(target, + &batch_bf[ROM_CALL_BATCH_ALGO_SIZE_BYTES], words, + (const uint32_t *)calls); + /* Null terminator */ + target_buffer_set_u32(target, &batch_bf[batch_size - sizeof(uint32_t)], 0); + + int err = target_write_buffer(target, + priv->ram_algo_space->address, + batch_size, + batch_bf + ); + free(batch_bf); + + if (err != ERROR_OK) { + LOG_ERROR("Failed to write ROM batch algorithm to RAM code space"); + return err; + } + + // Call into the ROM batch algorithm -- this will in turn call each ROM + // call specified by the batch records. + target_addr_t algo_start_addr = priv->ram_algo_space->address; + target_addr_t algo_end_addr = priv->ram_algo_space->address + rp2xxx_rom_call_batch_algo_bkpt_offset; + unsigned int algo_timeout_ms = 3000; + if (is_arm(target_to_arm(target))) { + struct armv7m_algorithm alg_info; + alg_info.common_magic = ARMV7M_COMMON_MAGIC; + alg_info.core_mode = ARM_MODE_THREAD; + err = target_run_algorithm(target, + 0, NULL, /* No memory arguments */ + 0, NULL, /* No register arguments */ + algo_start_addr, algo_end_addr, + algo_timeout_ms, + &alg_info + ); + } else { + // Presumed RISC-V -- there is no RISCV_COMMON_MAGIC on older OpenOCD + err = target_run_algorithm(target, + 0, NULL, /* No memory arguments */ + 0, NULL, /* No register arguments */ + algo_start_addr, algo_end_addr, + algo_timeout_ms, + NULL /* Currently no RISC-V-specific algorithm info */ + ); + } + if (err != ERROR_OK) { + LOG_ERROR("Failed to call ROM function batch"); + /* This case is hit when loading new ROM images on FPGA, but can also be hit on real + hardware if you swap two devices with different ROM versions without restarting OpenOCD: */ + LOG_ROM_SYMBOL_DEBUG("Repopulating ROM address cache after failed ROM call"); + /* We ignore the error on this next call because we have already failed, this is just + recovery for the next attempt. */ + (void)rp2xxx_populate_rom_pointer_cache(target, priv); + return err; + } + return ERROR_OK; +} + +// Call a single ROM function, using the default algorithm stack. +static int rp2xxx_call_rom_func(struct target *target, struct rp2xxx_flash_bank *priv, + uint16_t func_offset, uint32_t argdata[], unsigned int n_args) +{ + assert(n_args <= 4); /* only allow register arguments -- capped at just 4 on Arm */ + + if (!priv->stack) { + LOG_ERROR("no stack for flash programming code"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + target_addr_t stacktop = priv->stack->address + priv->stack->size; + + struct rp2xxx_rom_call_batch_record call = { + .pc = func_offset, + .sp = stacktop + }; + for (unsigned int i = 0; i < n_args; ++i) + call.args[i] = argdata[i]; + + return rp2xxx_call_rom_func_batch(target, priv, &call, 1); +} + +static int rp2350_save_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv) +{ + return target_read_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4, + priv->saved_accessctrl); +} + +static int rp2350_restore_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv) +{ + // Add write passwords to all ACCESSCTRL regs from ACCESSCTRL_GPIO_ROM to the end + // (exclude not keyed ACCESSCTRL_GPIO_NSMASK0 and ACCESSCTRL_GPIO_NSMASK1 + for (unsigned int i = ACCESSCTRL_GPIO_ROM_OFFSET - ACCESSCTRL_SAVE_BASE; + i < ACCESSCTRL_SAVE_SIZE; i += 4) + target_buffer_set_u32(target, priv->saved_accessctrl + i, + target_buffer_get_u32(target, priv->saved_accessctrl + i) | ACCESSCTRL_WRITE_PASSWORD); + + return target_write_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4, + priv->saved_accessctrl); +} + +static int rp2350_init_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv) +{ + priv->accessctrl_dirty = false; + // Attempt to reset ACCESSCTRL, in case Secure access to SRAM has been + // blocked, which will stop us from loading/running algorithms such as RCP + // init. (Also ROM, QMI regs are needed later) + uint32_t accessctrl_lock_reg; + if (target_read_u32(target, ACCESSCTRL_LOCK_OFFSET, &accessctrl_lock_reg) != ERROR_OK) { + LOG_ERROR("Failed to read ACCESSCTRL lock register"); + // Failed to read an APB register which should always be readable from + // any security/privilege level. Something fundamental is wrong. E.g.: + // + // - The debugger is attempting to perform Secure bus accesses on a + // system where Secure debug has been disabled + // - clk_sys or busfabric clock are stopped (try doing a rescue reset) + return ERROR_FAIL; + } + if (accessctrl_lock_reg & ACCESSCTRL_LOCK_DEBUG_BITS) { + LOG_ERROR("ACCESSCTRL is locked, so can't reset permissions. Following steps might fail"); + } else { + int retval = rp2350_save_accessctrl(target, priv); + if (retval == ERROR_OK) + priv->accessctrl_dirty = true; + // If the ACCESSCTRL backup copy is valid, mark it dirty + // as we immediately proceed to ACCESSCTRL config reset. + // Don't fail on save ACCESSCTRL error, not vital for ROM API call + + LOG_DEBUG("Reset ACCESSCTRL permissions via CFGRESET"); + return target_write_u32(target, ACCESSCTRL_CFGRESET_OFFSET, ACCESSCTRL_WRITE_PASSWORD | 1u); + } + return ERROR_OK; +} + +static int rp2350_init_arm_core0(struct target *target, struct rp2xxx_flash_bank *priv) +{ + // Flash algorithms (and the RCP init stub called by this function) must + // run in the Secure state, so flip the state now before attempting to + // execute any code on the core. + int retval; + retval = cortex_m_set_secure(target, &priv->saved_security); + if (retval != ERROR_OK) { + LOG_ERROR("RP2350 init ARM core: set secure mode failed"); + return retval; + } + + if (!priv->stack) { + LOG_ERROR("No stack for flash programming code"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (!priv->ram_algo_space || priv->ram_algo_space->size < sizeof(rcp_init_code)) { + LOG_ERROR("No algorithm space for rcp_init code"); + return ERROR_BUF_TOO_SMALL; + } + + int err = target_write_memory(target, + priv->ram_algo_space->address, + 1, + sizeof(rcp_init_code), + rcp_init_code + ); + if (err != ERROR_OK) { + LOG_ERROR("Failed to load rcp_init algorithm into RAM"); + return ERROR_FAIL; + } + + LOG_TARGET_DEBUG(target, "Calling rcp_init, code at " TARGET_ADDR_FMT, + priv->ram_algo_space->address); + + /* Actually call the function */ + struct armv7m_algorithm alg_info; + alg_info.common_magic = ARMV7M_COMMON_MAGIC; + alg_info.core_mode = ARM_MODE_THREAD; + err = target_run_algorithm(target, + 0, NULL, /* No memory arguments */ + 0, NULL, /* No register arguments */ + priv->ram_algo_space->address, + priv->ram_algo_space->address + rcp_init_code_bkpt_offset, + 1000, /* 1s timeout */ + &alg_info + ); + if (err != ERROR_OK) { + LOG_ERROR("Failed to invoke rcp_init"); + return err; + } + + return err; +} + +static int setup_for_raw_flash_cmd(struct target *target, struct rp2xxx_flash_bank *priv) +{ + int err = ERROR_OK; + + if (!priv->stack) { + /* target_alloc_working_area always allocates multiples of 4 bytes, so no worry about alignment */ + err = target_alloc_working_area(target, RP2XXX_MAX_ALGO_STACK_USAGE, &priv->stack); + if (err != ERROR_OK) { + LOG_ERROR("Could not allocate stack for flash programming code -- insufficient space"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + } + + if (!priv->ram_algo_space) { + err = target_alloc_working_area(target, RP2XXX_MAX_RAM_ALGO_SIZE, &priv->ram_algo_space); + if (err != ERROR_OK) { + LOG_ERROR("Could not allocate RAM code space for ROM calls -- insufficient space"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + } + + if (IS_RP2350(priv->id)) { + err = rp2350_init_accessctrl(target, priv); + if (err != ERROR_OK) { + LOG_ERROR("Failed to init ACCESSCTRL before ROM call"); + return err; + } + if (is_arm(target_to_arm(target))) { + err = rp2350_init_arm_core0(target, priv); + if (err != ERROR_OK) { + LOG_ERROR("Failed to init Arm core 0 before ROM call"); + return err; + } + } + uint32_t reset_args[1] = { + BOOTROM_STATE_RESET_CURRENT_CORE + }; + if (!priv->jump_bootrom_reset_state) { + LOG_WARNING("RP2350 flash: no bootrom_reset_method"); + } else { + /* This is mainly required to clear varmulet_enclosing_cpu pointers on RISC-V, in case + an Arm -> RISC-V call has been interrupted (these pointers are used to handle + reentrant calls to the ROM emulator) */ + LOG_DEBUG("Clearing core 0 ROM state"); + err = rp2xxx_call_rom_func(target, priv, priv->jump_bootrom_reset_state, + reset_args, ARRAY_SIZE(reset_args)); + if (err != ERROR_OK) { + LOG_ERROR("RP2350 flash: failed to call reset core state"); + return err; + } + } + if (!is_arm(target_to_arm(target)) && priv->jump_bootrom_set_varm_stack) { + /* Pass {0, 0} to set_varmulet_user_stack() to enable automatic emulation of Arm APIs + using the ROM's default stacks. Usually the bootrom does this before exiting to user + code, but it needs to be done manually when the USB bootloader has been interrupted. */ + LOG_DEBUG("Enabling default Arm emulator stacks for RISC-V ROM calls"); + struct working_area *set_stack_mem_args; + err = target_alloc_working_area(target, 2 * sizeof(uint32_t), &set_stack_mem_args); + if (err != ERROR_OK) { + LOG_ERROR("Failed to allocate memory for arguments to set_varmulet_user_stack()"); + return err; + } + + err = target_write_u32(target, set_stack_mem_args->address, 0); + if (err == ERROR_OK) + err = target_write_u32(target, set_stack_mem_args->address + 4, 0); + + if (err != ERROR_OK) { + LOG_ERROR("Failed to initialise memory arguments for set_varmulet_user_stack()"); + target_free_working_area(target, set_stack_mem_args); + return err; + } + + uint32_t set_stack_register_args[1] = { + set_stack_mem_args->address + }; + err = rp2xxx_call_rom_func(target, priv, priv->jump_bootrom_set_varm_stack, + set_stack_register_args, ARRAY_SIZE(set_stack_register_args)); + target_free_working_area(target, set_stack_mem_args); + if (err != ERROR_OK) { + LOG_ERROR("Failed to initialise Arm emulation stacks for RISC-V"); + return err; + } + } + } + + LOG_DEBUG("Connecting flash IOs and issuing XIP exit sequence to flash"); + struct rp2xxx_rom_call_batch_record calls[2] = { + { + .pc = priv->jump_connect_internal_flash, + .sp = priv->stack->address + priv->stack->size + }, + { + .pc = priv->jump_flash_exit_xip, + .sp = priv->stack->address + priv->stack->size + } + }; + err = rp2xxx_call_rom_func_batch(target, priv, calls, 2); + if (err != ERROR_OK) { + LOG_ERROR("RP2xxx flash: failed to exit flash XIP mode"); + return err; + } + + return ERROR_OK; +} + +static int rp2xxx_invalidate_cache_restore_xip(struct target *target, struct rp2xxx_flash_bank *priv) +{ + // Flash content has changed. We can now do a bit of poking to make + // the new flash contents visible to us via memory-mapped (XIP) interface + // in the 0x1... memory region. + + LOG_DEBUG("Flushing flash cache after write behind"); + + struct rp2xxx_rom_call_batch_record finishing_calls[2] = { + { + .pc = priv->jump_flush_cache, + .sp = priv->stack->address + priv->stack->size + }, + { + .sp = priv->stack->address + priv->stack->size + }, + }; + + int num_finishing_calls = 1; + // Note on RP2350 it's not *required* to call flash_enter_cmd_xip, since + // the ROM leaves flash XIPable by default in between direct-mode + // accesses + if (IS_RP2040(priv->id)) { + finishing_calls[num_finishing_calls++].pc = priv->jump_enter_cmd_xip; + } else if (priv->jump_flash_reset_address_trans) { + // Note flash_reset_address_trans function does not exist on older devices + finishing_calls[num_finishing_calls++].pc = priv->jump_flash_reset_address_trans; + } + + int retval = rp2xxx_call_rom_func_batch(target, priv, finishing_calls, num_finishing_calls); + if (retval != ERROR_OK) + LOG_ERROR("RP2xxx: failed to flush flash cache/restore XIP"); + + return retval; +} + +static void cleanup_after_raw_flash_cmd(struct target *target, struct rp2xxx_flash_bank *priv) +{ + /* OpenOCD is prone to trashing work-area allocations on target state + transitions, which leaves us with stale work area pointers in our + driver state. Best to clean up our allocations manually after + completing each flash call, so we know to make fresh ones next time. */ + LOG_DEBUG("Cleaning up after flash operations"); + + if (IS_RP2350(priv->id)) { + int retval1 = ERROR_OK; + if (priv->accessctrl_dirty) { + retval1 = rp2350_restore_accessctrl(target, priv); + priv->accessctrl_dirty = false; + } + + int retval2 = ERROR_OK; + if (is_arm(target_to_arm(target))) + retval2 = cortex_m_security_restore(target, &priv->saved_security); + + if (retval1 != ERROR_OK || retval2 != ERROR_OK) + LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead"); + /* Don't fail on security restore error, not vital for flash operation */ + } + if (priv->stack) { + target_free_working_area(target, priv->stack); + priv->stack = 0; + } + if (priv->ram_algo_space) { + target_free_working_area(target, priv->ram_algo_space); + priv->ram_algo_space = 0; + } +} + +static int rp2xxx_flash_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) +{ + LOG_DEBUG("Writing %" PRIu32 " bytes starting at 0x%" PRIx32, count, offset); + + struct rp2xxx_flash_bank *priv = bank->driver_priv; + struct target *target = bank->target; + + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + struct working_area *bounce = NULL; + + int err = setup_for_raw_flash_cmd(target, priv); + if (err != ERROR_OK) + goto cleanup_and_return; + + unsigned int avail_pages = target_get_working_area_avail(target) / RP2XXX_ROM_API_FIXED_FLASH_PAGE; + /* We try to allocate working area rounded down to device page size, + * al least 1 page, at most the write data size */ + unsigned int chunk_size = MIN(MAX(avail_pages, 1) * RP2XXX_ROM_API_FIXED_FLASH_PAGE, count); + err = target_alloc_working_area(target, chunk_size, &bounce); + if (err != ERROR_OK) { + LOG_ERROR("Could not allocate bounce buffer for flash programming. Can't continue"); + goto cleanup_and_return; + } + + LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address); + + while (count > 0) { + uint32_t write_size = count > chunk_size ? chunk_size : count; + LOG_DEBUG("Writing %" PRIu32 " bytes to offset 0x%" PRIx32, + write_size, offset); + err = target_write_buffer(target, bounce->address, write_size, buffer); + if (err != ERROR_OK) { + LOG_ERROR("Could not load data into target bounce buffer"); + break; + } + uint32_t args[3] = { + offset, /* addr */ + bounce->address, /* data */ + write_size /* count */ + }; + err = rp2xxx_call_rom_func(target, priv, priv->jump_flash_range_program, + args, ARRAY_SIZE(args)); + keep_alive(); + if (err != ERROR_OK) { + LOG_ERROR("Failed to invoke flash programming code on target"); + break; + } + + buffer += write_size; + offset += write_size; + count -= write_size; + } + +cleanup_and_return: + target_free_working_area(target, bounce); + + /* Don't propagate error or user gets fooled the flash write failed */ + (void)rp2xxx_invalidate_cache_restore_xip(target, priv); + + cleanup_after_raw_flash_cmd(target, priv); + return err; +} + +static int rp2xxx_flash_erase(struct flash_bank *bank, unsigned int first, unsigned int last) +{ + struct rp2xxx_flash_bank *priv = bank->driver_priv; + struct target *target = bank->target; + + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + uint32_t offset_start = bank->sectors[first].offset; + uint32_t offset_last = bank->sectors[last].offset + bank->sectors[last].size; + uint32_t length = offset_last - offset_start; + LOG_DEBUG("erase %" PRIu32 " bytes starting at 0x%" PRIx32, + length, offset_start); + + int err = setup_for_raw_flash_cmd(target, priv); + if (err != ERROR_OK) + goto cleanup_and_return; + + uint32_t offset_next = offset_start; + + /* Break erase into multiple calls to avoid timeout on large erase. Choose 128k chunk which has + fairly low ROM call overhead and empirically seems to avoid the default keep_alive() limit + as well as our ROM call timeout. */ + const uint32_t erase_chunk_size = 128 * 1024; + + /* Promote log level for long erases to provide feedback */ + bool requires_loud_prints = offset_last - offset_next >= 2 * erase_chunk_size; + enum log_levels chunk_log_level = requires_loud_prints ? LOG_LVL_INFO : LOG_LVL_DEBUG; + + while (offset_next < offset_last) { + uint32_t remaining = offset_last - offset_next; + uint32_t call_size = remaining < erase_chunk_size ? remaining : erase_chunk_size; + /* Shorten the first call of a large erase if necessary to align subsequent calls */ + if (offset_next % erase_chunk_size != 0 && call_size == erase_chunk_size) + call_size = erase_chunk_size - offset_next % erase_chunk_size; + + LOG_CUSTOM_LEVEL(chunk_log_level, + " Erase chunk: 0x%08" PRIx32 " -> 0x%08" PRIx32, + offset_next, + offset_next + call_size - 1 + ); + + /* This ROM function uses the optimal mixture of 4k 20h and 64k D8h erases, without + over-erase. This is why we force the flash_bank sector size attribute to 4k even if + OpenOCD prefers to give the block size instead. */ + uint32_t args[4] = { + offset_next, + call_size, + 65536, /* block_size */ + 0xd8 /* block_cmd */ + }; + + err = rp2xxx_call_rom_func(target, priv, priv->jump_flash_range_erase, args, ARRAY_SIZE(args)); + keep_alive(); + + if (err != ERROR_OK) + break; + + offset_next += call_size; + } + + +cleanup_and_return: + /* Don't propagate error or user gets fooled the flash erase failed */ + (void)rp2xxx_invalidate_cache_restore_xip(target, priv); + + cleanup_after_raw_flash_cmd(target, priv); + return err; +} + +/* ----------------------------------------------------------------------------- + Driver probing etc */ + + +static int rp2040_ssel_active(struct target *target, bool active) +{ + uint32_t state = active ? RP2040_QSPI_CTRL_OUTOVER_LOW : RP2040_QSPI_CTRL_OUTOVER_HIGH; + uint32_t val; + + int err = target_read_u32(target, RP2040_QSPI_CTRL, &val); + if (err != ERROR_OK) + return err; + + val = (val & ~RP2040_QSPI_CTRL_OUTOVER_MASK) | state; + + err = target_write_u32(target, RP2040_QSPI_CTRL, val); + if (err != ERROR_OK) + return err; + + return ERROR_OK; +} + +static int rp2040_spi_tx_rx(struct target *target, + const uint8_t *tx, unsigned int tx_len, + unsigned int dummy_len, + uint8_t *rx, unsigned int rx_len) +{ + int retval, retval2; + + retval = rp2040_ssel_active(target, true); + if (retval != ERROR_OK) { + LOG_ERROR("QSPI select failed"); + goto deselect; + } + + unsigned int tx_cnt = 0; + unsigned int rx_cnt = 0; + unsigned int xfer_len = tx_len + dummy_len + rx_len; + while (rx_cnt < xfer_len) { + int in_flight = tx_cnt - rx_cnt; + if (tx_cnt < xfer_len && in_flight < 14) { + uint32_t dr = tx_cnt < tx_len ? tx[tx_cnt] : 0; + retval = target_write_u32(target, RP2040_SSI_DR0, dr); + if (retval != ERROR_OK) + break; + + tx_cnt++; + continue; + } + uint32_t dr; + retval = target_read_u32(target, RP2040_SSI_DR0, &dr); + if (retval != ERROR_OK) + break; + + if (rx_cnt >= tx_len + dummy_len) + rx[rx_cnt - tx_len - dummy_len] = (uint8_t)dr; + + rx_cnt++; + } + +deselect: + retval2 = rp2040_ssel_active(target, false); + + if (retval != ERROR_OK) { + LOG_ERROR("QSPI Tx/Rx failed"); + return retval; + } + if (retval2 != ERROR_OK) + LOG_ERROR("QSPI deselect failed"); + + return retval2; +} + +static int rp2350_spi_tx_rx(struct target *target, + const uint8_t *tx, unsigned int tx_len, + unsigned int dummy_len, + uint8_t *rx, unsigned int rx_len) +{ + uint32_t direct_csr; + int retval = target_read_u32(target, RP2350_QMI_DIRECT_CSR, &direct_csr); + if (retval != ERROR_OK) { + LOG_ERROR("QMI DIRECT_CSR read failed"); + return retval; + } + direct_csr |= RP2350_QMI_DIRECT_CSR_EN | RP2350_QMI_DIRECT_CSR_ASSERT_CS0N; + retval = target_write_u32(target, RP2350_QMI_DIRECT_CSR, direct_csr); + if (retval != ERROR_OK) { + LOG_ERROR("QMI DIRECT mode enable failed"); + goto deselect; + } + + unsigned int tx_cnt = 0; + unsigned int rx_cnt = 0; + unsigned int xfer_len = tx_len + dummy_len + rx_len; + while (tx_cnt < xfer_len || rx_cnt < rx_len) { + int in_flight = tx_cnt - tx_len - dummy_len - rx_cnt; + if (tx_cnt < xfer_len && in_flight < 4) { + uint32_t tx_cmd; + if (tx_cnt < tx_len) + tx_cmd = tx[tx_cnt] | RP2350_QMI_DIRECT_TX_NOPUSH | RP2350_QMI_DIRECT_TX_OE; + else if (tx_cnt < tx_len + dummy_len) + tx_cmd = RP2350_QMI_DIRECT_TX_NOPUSH; + else + tx_cmd = 0; + + retval = target_write_u32(target, RP2350_QMI_DIRECT_TX, tx_cmd); + if (retval != ERROR_OK) + break; + + tx_cnt++; + continue; + } + if (rx_cnt < rx_len) { + uint32_t dr; + retval = target_read_u32(target, RP2350_QMI_DIRECT_RX, &dr); + if (retval != ERROR_OK) + break; + + rx[rx_cnt] = (uint8_t)dr; + rx_cnt++; + } + } + +deselect: + direct_csr &= ~(RP2350_QMI_DIRECT_CSR_EN | RP2350_QMI_DIRECT_CSR_ASSERT_CS0N); + int retval2 = target_write_u32(target, RP2350_QMI_DIRECT_CSR, direct_csr); + + if (retval != ERROR_OK) { + LOG_ERROR("QSPI Tx/Rx failed"); + return retval; + } + if (retval2 != ERROR_OK) + LOG_ERROR("QMI DIRECT mode disable failed"); + + return retval2; +} + +static int rp2xxx_spi_tx_rx(struct flash_bank *bank, + const uint8_t *tx, unsigned int tx_len, + unsigned int dummy_len, + uint8_t *rx, unsigned int rx_len) +{ + struct rp2xxx_flash_bank *priv = bank->driver_priv; + struct target *target = bank->target; + + if (IS_RP2040(priv->id)) + return rp2040_spi_tx_rx(target, tx, tx_len, dummy_len, rx, rx_len); + else if (IS_RP2350(priv->id)) + return rp2350_spi_tx_rx(target, tx, tx_len, dummy_len, rx, rx_len); + else + return ERROR_FAIL; +} + +static int rp2xxx_read_sfdp_block(struct flash_bank *bank, uint32_t addr, + unsigned int words, uint32_t *buffer) +{ + struct rp2xxx_flash_bank *priv = bank->driver_priv; + + uint8_t cmd[4] = { SPIFLASH_READ_SFDP }; + uint8_t data[4 * words + priv->sfdp_dummy_detect]; + + h_u24_to_be(&cmd[1], addr); + + int retval = rp2xxx_spi_tx_rx(bank, cmd, sizeof(cmd), priv->sfdp_dummy, + data, 4 * words + priv->sfdp_dummy_detect); + if (retval != ERROR_OK) + return retval; + + if (priv->sfdp_dummy_detect) { + for (unsigned int i = 0; i < priv->sfdp_dummy_detect; i++) + if (le_to_h_u32(&data[i]) == SFDP_MAGIC) { + priv->sfdp_dummy_detect = 0; + priv->sfdp_dummy = i; + break; + } + for (unsigned int i = 0; i < words; i++) + buffer[i] = le_to_h_u32(&data[4 * i + priv->sfdp_dummy]); + } else { + for (unsigned int i = 0; i < words; i++) + buffer[i] = le_to_h_u32(&data[4 * i]); + } + return retval; +} + +static int rp2xxx_flash_probe(struct flash_bank *bank) +{ + struct rp2xxx_flash_bank *priv = bank->driver_priv; + struct target *target = bank->target; + + int retval = target_read_u32(target, RP2XXX_SYSINFO_CHIP_ID, &priv->id); + if (retval != ERROR_OK) { + LOG_ERROR("SYSINFO CHIP_ID read failed"); + return retval; + } + if (!IS_RP2040(priv->id) && !IS_RP2350(priv->id)) { + LOG_ERROR("Unknown SYSINFO CHIP_ID 0x%08" PRIx32, priv->id); + return ERROR_FLASH_BANK_INVALID; + } + + retval = rp2xxx_populate_rom_pointer_cache(target, priv); + if (retval != ERROR_OK) + return retval; + + /* the Boot ROM flash_range_program() routine requires page alignment */ + bank->write_start_alignment = RP2XXX_ROM_API_FIXED_FLASH_PAGE; + bank->write_end_alignment = RP2XXX_ROM_API_FIXED_FLASH_PAGE; + + uint32_t flash_id = 0; + if (priv->size_override) { + priv->spi_dev.name = "size override"; + LOG_DEBUG("SPI flash autodetection disabled, using configured size"); + } else { + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + bank->size = 0; + + (void)setup_for_raw_flash_cmd(target, priv); + /* ignore error, flash size detection could work anyway */ + + const uint8_t cmd[] = { SPIFLASH_READ_ID }; + uint8_t data[3]; + retval = rp2xxx_spi_tx_rx(bank, cmd, sizeof(cmd), 0, data, sizeof(data)); + if (retval == ERROR_OK) { + flash_id = le_to_h_u24(data); + + /* search for a SPI flash Device ID match */ + for (const struct flash_device *p = flash_devices; p->name ; p++) { + if (p->device_id == flash_id) { + priv->spi_dev = *p; + bank->size = p->size_in_bytes; + break; + } + } + } + + if (bank->size == 0) { + priv->sfdp_dummy_detect = 8; + priv->sfdp_dummy = 0; + retval = spi_sfdp(bank, &priv->spi_dev, &rp2xxx_read_sfdp_block); + if (retval == ERROR_OK) + bank->size = priv->spi_dev.size_in_bytes; + } + + cleanup_after_raw_flash_cmd(target, priv); + } + + snprintf(priv->dev_name, sizeof(priv->dev_name), "%s rev %u", + IS_RP2350(priv->id) ? "RP2350" : "RP2040", + RP2XXX_CHIP_ID_REVISION(priv->id)); + + if (bank->size == 0) { + LOG_ERROR("%s, QSPI Flash id = 0x%06" PRIx32 " not recognised", + priv->dev_name, flash_id); + return ERROR_FLASH_BANK_INVALID; + } + + bank->num_sectors = bank->size / RP2XXX_ROM_API_FIXED_FLASH_SECTOR; + + if (priv->size_override) { + LOG_INFO("%s, QSPI Flash size override = %u KiB in %u sectors", + priv->dev_name, bank->size / 1024, bank->num_sectors); + } else { + LOG_INFO("%s, QSPI Flash %s id = 0x%06" PRIx32 " size = %u KiB in %u sectors", + priv->dev_name, priv->spi_dev.name, flash_id, + bank->size / 1024, bank->num_sectors); + } + + free(bank->sectors); + bank->sectors = alloc_block_array(0, RP2XXX_ROM_API_FIXED_FLASH_SECTOR, bank->num_sectors); + if (!bank->sectors) + return ERROR_FAIL; + + priv->probed = true; + + return ERROR_OK; +} + +static int rp2xxx_flash_auto_probe(struct flash_bank *bank) +{ + struct rp2xxx_flash_bank *priv = bank->driver_priv; + + if (priv->probed) + return ERROR_OK; + + return rp2xxx_flash_probe(bank); +} + +/* ----------------------------------------------------------------------------- + Driver boilerplate */ + +FLASH_BANK_COMMAND_HANDLER(rp2xxx_flash_bank_command) +{ + struct rp2xxx_flash_bank *priv; + priv = calloc(1, sizeof(struct rp2xxx_flash_bank)); + priv->size_override = bank->size != 0; + + /* Set up driver_priv */ + bank->driver_priv = priv; + + return ERROR_OK; +} + + +COMMAND_HANDLER(rp2xxx_rom_api_call_handler) +{ + if (CMD_ARGC < 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD->ctx); + + struct flash_bank *bank; + for (bank = flash_bank_list(); bank; bank = bank->next) { + if (bank->driver != &rp2xxx_flash) + continue; + + if (bank->target == target) + break; + } + + if (!bank) { + command_print(CMD, "[%s] No associated RP2xxx flash bank found", + target_name(target)); + return ERROR_FAIL; + } + + int retval = rp2xxx_flash_auto_probe(bank); + if (retval != ERROR_OK) { + command_print(CMD, "auto_probe failed"); + return retval; + } + + uint16_t tag = MAKE_TAG(CMD_ARGV[0][0], CMD_ARGV[0][1]); + + uint32_t args[4] = { 0 }; + for (unsigned int i = 0; i + 1 < CMD_ARGC && i < ARRAY_SIZE(args); i++) + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[i + 1], args[i]); + + if (target->state != TARGET_HALTED) { + command_print(CMD, "Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + struct rp2xxx_flash_bank *priv = bank->driver_priv; + retval = setup_for_raw_flash_cmd(target, priv); + if (retval != ERROR_OK) + goto cleanup_and_return; + + uint16_t symtype_func = is_arm(target_to_arm(target)) + ? RT_FLAG_FUNC_ARM_SEC : RT_FLAG_FUNC_RISCV; + + uint16_t fc; + retval = rp2xxx_lookup_rom_symbol(target, tag, symtype_func, &fc); + if (retval != ERROR_OK) { + command_print(CMD, "Function %.2s not found in RP2xxx ROM", + CMD_ARGV[0]); + goto cleanup_and_return; + } + + /* command_print() output gets lost if the command is called + * in an event handler, use LOG_INFO instead */ + LOG_INFO("RP2xxx ROM API function %.2s @ %04" PRIx16, CMD_ARGV[0], fc); + + retval = rp2xxx_call_rom_func(target, priv, fc, args, ARRAY_SIZE(args)); + if (retval != ERROR_OK) + command_print(CMD, "RP2xxx ROM API call failed"); + +cleanup_and_return: + cleanup_after_raw_flash_cmd(target, priv); + return retval; +} + +COMMAND_HANDLER(rp2xxx_switch_target_handler) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *old_target = get_target(CMD_ARGV[0]); + if (!old_target) { + command_print(CMD, "Unrecognised old target %s", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + struct target *new_target = get_target(CMD_ARGV[1]); + if (!new_target) { + command_print(CMD, "Unrecognised new target %s", CMD_ARGV[1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + struct flash_bank *bank; + for (bank = flash_bank_list(); bank; bank = bank->next) { + if (bank->driver == &rp2xxx_flash) { + if (bank->target == old_target) { + bank->target = new_target; + struct rp2xxx_flash_bank *priv = bank->driver_priv; + priv->probed = false; + return ERROR_OK; + } else if (bank->target == new_target) { + return ERROR_OK; + } + } + } + + command_print(CMD, "Neither old nor new target %s found in flash bank list", + CMD_ARGV[0]); + return ERROR_FAIL; +} + +static const struct command_registration rp2xxx_exec_command_handlers[] = { + { + .name = "rom_api_call", + .mode = COMMAND_EXEC, + .help = "arbitrary ROM API call", + .usage = "fc [p0 [p1 [p2 [p3]]]]", + .handler = rp2xxx_rom_api_call_handler, + }, + { + .name = "_switch_target", + .mode = COMMAND_EXEC, + .help = "internal use", + .usage = "old_target new_target", + .handler = rp2xxx_switch_target_handler, + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration rp2xxx_command_handler[] = { + { + .name = "rp2xxx", + .mode = COMMAND_ANY, + .help = "rp2xxx flash controller commands", + .usage = "", + .chain = rp2xxx_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +const struct flash_driver rp2xxx_flash = { + .name = "rp2xxx", + .commands = rp2xxx_command_handler, + .flash_bank_command = rp2xxx_flash_bank_command, + .erase = rp2xxx_flash_erase, + .write = rp2xxx_flash_write, + .read = default_flash_read, + .probe = rp2xxx_flash_probe, + .auto_probe = rp2xxx_flash_auto_probe, + .erase_check = default_flash_blank_check, + .free_driver_priv = default_flash_free_driver_priv +}; diff --git a/src/flash/nor/rsl10.c b/src/flash/nor/rsl10.c new file mode 100644 index 0000000000..c33099787a --- /dev/null +++ b/src/flash/nor/rsl10.c @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Toms StÅ«rmanis * + * toms.sturmanis@gmail.com * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stdint.h> + +#include <helper/binarybuffer.h> +#include <helper/bits.h> + +#include <target/algorithm.h> +#include <target/arm_adi_v5.h> +#include <target/armv7m.h> +#include <target/cortex_m.h> + +#include "imp.h" + +#define RSL10_FLASH_ADDRESS_MAIN 0x00100000 +#define RSL10_FLASH_ADDRESS_NVR1 0x00080000 +#define RSL10_FLASH_ADDRESS_NVR2 0x00080800 +#define RSL10_FLASH_ADDRESS_NVR3 0x00081000 +#define RSL10_FLASH_ADDRESS_NVR4 0x00081800 +#define RSL10_FLASH_ADDRESS_LOCK_INFO_SETTING 0x00081040 + +#define RSL10_REG_ID 0x1FFFFFFC + +#define RSL10_FLASH_REG_MAIN_WRITE_UNLOCK 0x40000504 +#define RSL10_FLASH_REG_MAIN_CTRL 0x40000508 +#define RSL10_FLASH_REG_IF_STATUS 0x40000538 +#define RSL10_FLASH_REG_NVR_WRITE_UNLOCK 0x40000548 +#define RSL10_FLASH_REG_NVR_CTRL 0x4000054C + +#define RSL10_FLASH_REG_DEBUG_UNLOCK_KEY1 0x400000F0 +#define RSL10_FLASH_REG_DEBUG_UNLOCK_KEY2 0x400000F4 +#define RSL10_FLASH_REG_DEBUG_UNLOCK_KEY3 0x400000F8 +#define RSL10_FLASH_REG_DEBUG_UNLOCK_KEY4 0x400000FC + +#define RSL10_NVR3_USER_KEY_OFFSET 0x40 + +#define RSL10_ID 0x09010106 +#define RSL10_FLASH_KEY_MAIN 0xDBC8264E +#define RSL10_FLASH_KEY_NVR 0x71B371F5 +#define RSL10_KEY_DEBUG_LOCK 0x4C6F634B + +#define RSL10_FLASH_REG_MAIN_CTRL_LOW_W_ENABLE BIT(0) +#define RSL10_FLASH_REG_MAIN_CTRL_MIDDLE_W_ENABLE BIT(1) +#define RSL10_FLASH_REG_MAIN_CTRL_HIGH_W_ENABLE BIT(2) + +#define RSL10_FLASH_REG_NVR_CTRL_NVR1_W_ENABLE BIT(1) +#define RSL10_FLASH_REG_NVR_CTRL_NVR2_W_ENABLE BIT(2) +#define RSL10_FLASH_REG_NVR_CTRL_NVR3_W_ENABLE BIT(3) + +#define RSL10_FLASH_REG_STATUS_LOW_W_UNLOCKED BIT(0) +#define RSL10_FLASH_REG_STATUS_MIDDLE_W_UNLOCKED BIT(1) +#define RSL10_FLASH_REG_STATUS_HIGH_W_UNLOCKED BIT(2) +#define RSL10_FLASH_REG_STATUS_NVR1_W_UNLOCKED BIT(4) +#define RSL10_FLASH_REG_STATUS_NVR2_W_UNLOCKED BIT(5) +#define RSL10_FLASH_REG_STATUS_NVR3_W_UNLOCKED BIT(6) + +#define RSL10_ROM_CMD_WRITE_WORD_PAIR 0x3C +#define RSL10_ROM_CMD_WRITE_BUFFER 0x40 +#define RSL10_ROM_CMD_ERASE_SECTOR 0x44 +#define RSL10_ROM_CMD_ERASE_ALL 0x48 + +#define FLASH_SECTOR_SIZE 0x2000 + +#define RSL10_ROM_CMD_WRITE_BUFFER_MAX_SIZE FLASH_SECTOR_SIZE + +#define ALGO_STACK_POINTER_ADDR 0x20002000 + +/* Used to launch flash related functions from ROM + * Params : + * r0-r2 = arguments + * r3 = target address in rom + */ +static const uint8_t rsl10_rom_launcher_code[] = { +#include "../../../contrib/loaders/flash/rsl10/rom_launcher.inc" +}; + +enum rsl10_flash_status { + RSL10_FLASH_ERR_NONE = 0x0, + RSL10_FLASH_ERR_GENERAL_FAILURE = 0x1, + RSL10_FLASH_ERR_WRITE_NOT_ENABLED = 0x2, + RSL10_FLASH_ERR_BAD_ADDRESS = 0x3, + RSL10_FLASH_ERR_ERASE_FAILED = 0x4, + RSL10_FLASH_ERR_BAD_LENGTH = 0x5, + RSL10_FLASH_ERR_INACCESSIBLE = 0x6, + RSL10_FLASH_ERR_COPIER_BUSY = 0x7, + RSL10_FLASH_ERR_PROG_FAILED = 0x8, + RSL10_FLASH_MAX_ERR_CODES /* must be the last one */ +}; + +static const char *const rsl10_error_list[] = { + [RSL10_FLASH_ERR_GENERAL_FAILURE] = "general failure", + [RSL10_FLASH_ERR_WRITE_NOT_ENABLED] = "write not enabled, protected", + [RSL10_FLASH_ERR_BAD_ADDRESS] = "bad address", + [RSL10_FLASH_ERR_ERASE_FAILED] = "erase failed", + [RSL10_FLASH_ERR_BAD_LENGTH] = "bad length", + [RSL10_FLASH_ERR_INACCESSIBLE] = "inaccessible: not powered up, or isolated", + [RSL10_FLASH_ERR_COPIER_BUSY] = "copier busy", + [RSL10_FLASH_ERR_PROG_FAILED] = "prog failed", +}; + +static const char *rsl10_error(enum rsl10_flash_status x) +{ + if (x >= RSL10_FLASH_MAX_ERR_CODES || !rsl10_error_list[x]) + return "unknown"; + return rsl10_error_list[x]; +} + +const struct flash_driver rsl10_flash; + +struct rsl10_info { + unsigned int refcount; + + struct rsl10_bank { + struct rsl10_info *chip; + bool probed; + } bank[5]; + struct target *target; + + unsigned int flash_size_kb; +}; + +static bool rsl10_bank_is_probed(const struct flash_bank *bank) +{ + struct rsl10_bank *nbank = bank->driver_priv; + assert(nbank); + return nbank->probed; +} + +static int rsl10_probe(struct flash_bank *bank); + +static int rsl10_get_probed_chip_if_halted(struct flash_bank *bank, struct rsl10_info **chip) +{ + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + struct rsl10_bank *nbank = bank->driver_priv; + *chip = nbank->chip; + + if (rsl10_bank_is_probed(bank)) + return ERROR_OK; + + return rsl10_probe(bank); +} + +static int rsl10_protect_check(struct flash_bank *bank) +{ + uint32_t status; + + int retval = target_read_u32(bank->target, RSL10_FLASH_REG_IF_STATUS, &status); + if (retval != ERROR_OK) + return retval; + + if (bank->base == RSL10_FLASH_ADDRESS_MAIN) { + for (unsigned int i = 0; i < bank->num_prot_blocks; i++) + bank->prot_blocks[i].is_protected = (status & (1 << i)) ? 0 : 1; + + } else { + uint32_t test_bit = 0; + switch (bank->base) { + case RSL10_FLASH_ADDRESS_NVR1: + test_bit = RSL10_FLASH_REG_STATUS_NVR1_W_UNLOCKED; + break; + case RSL10_FLASH_ADDRESS_NVR2: + test_bit = RSL10_FLASH_REG_STATUS_NVR2_W_UNLOCKED; + break; + case RSL10_FLASH_ADDRESS_NVR3: + test_bit = RSL10_FLASH_REG_STATUS_NVR3_W_UNLOCKED; + break; + default: + break; + } + + bank->sectors[0].is_protected = (status & test_bit) ? 0 : 1; + } + return ERROR_OK; +} + +static int rsl10_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last) +{ + + struct rsl10_info *chip; + int retval = rsl10_get_probed_chip_if_halted(bank, &chip); + if (retval != ERROR_OK) + return retval; + + if (bank->base == RSL10_FLASH_ADDRESS_MAIN) { + uint32_t status; + retval = target_read_u32(bank->target, RSL10_FLASH_REG_MAIN_CTRL, &status); + if (retval != ERROR_OK) + return retval; + + for (unsigned int i = first; i <= last; i++) { + if (set) + status &= ~(1 << i); + else + status |= (1 << i); + } + + retval = target_write_u32(bank->target, RSL10_FLASH_REG_MAIN_CTRL, status); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(bank->target, RSL10_FLASH_REG_MAIN_WRITE_UNLOCK, RSL10_FLASH_KEY_MAIN); + if (retval != ERROR_OK) + return retval; + } else { + uint32_t bit = 0; + switch (bank->base) { + case RSL10_FLASH_ADDRESS_NVR1: + bit = RSL10_FLASH_REG_NVR_CTRL_NVR1_W_ENABLE; + break; + case RSL10_FLASH_ADDRESS_NVR2: + bit = RSL10_FLASH_REG_NVR_CTRL_NVR2_W_ENABLE; + break; + case RSL10_FLASH_ADDRESS_NVR3: + bit = RSL10_FLASH_REG_NVR_CTRL_NVR3_W_ENABLE; + break; + default: + break; + } + + uint32_t status; + retval = target_read_u32(bank->target, RSL10_FLASH_REG_NVR_CTRL, &status); + if (retval != ERROR_OK) + return retval; + + if (set) + status &= ~bit; + else + status |= bit; + + retval = target_write_u32(bank->target, RSL10_FLASH_REG_NVR_CTRL, status); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(bank->target, RSL10_FLASH_REG_NVR_WRITE_UNLOCK, RSL10_FLASH_KEY_NVR); + if (retval != ERROR_OK) + return retval; + } + + return ERROR_OK; +} + +static int rsl10_check_device(struct flash_bank *bank) +{ + uint32_t configid; + int retval = target_read_u32(bank->target, RSL10_REG_ID, &configid); + if (retval != ERROR_OK) + return retval; + + if (configid != RSL10_ID) { + LOG_ERROR("This is not supported (RSL10) device, use other flash driver!!!"); + return ERROR_TARGET_INVALID; + } + return ERROR_OK; +} + +static int rsl10_probe(struct flash_bank *bank) +{ + struct rsl10_bank *nbank = bank->driver_priv; + struct rsl10_info *chip = nbank->chip; + + int retval = rsl10_check_device(bank); + if (retval != ERROR_OK) + return retval; + + unsigned int bank_id; + unsigned int num_prot_blocks = 0; + switch (bank->base) { + case RSL10_FLASH_ADDRESS_MAIN: + bank_id = 0; + num_prot_blocks = 3; + break; + case RSL10_FLASH_ADDRESS_NVR1: + bank_id = 1; + break; + case RSL10_FLASH_ADDRESS_NVR2: + bank_id = 2; + break; + case RSL10_FLASH_ADDRESS_NVR3: + bank_id = 3; + break; + default: + return ERROR_FAIL; + } + + uint32_t flash_page_size = 2048; + + bank->write_start_alignment = 8; + bank->write_end_alignment = 8; + + bank->num_sectors = bank->size / flash_page_size; + chip->flash_size_kb = bank->size / 1024; + + free(bank->sectors); + bank->sectors = NULL; + + bank->sectors = alloc_block_array(0, flash_page_size, bank->num_sectors); + if (!bank->sectors) + return ERROR_FAIL; + + free(bank->prot_blocks); + bank->prot_blocks = NULL; + + if (num_prot_blocks > 0) { + bank->num_prot_blocks = num_prot_blocks; + bank->prot_blocks = alloc_block_array(0, bank->num_sectors / 3 * flash_page_size, bank->num_prot_blocks); + if (!bank->prot_blocks) + return ERROR_FAIL; + } + + chip->bank[bank_id].probed = true; + return ERROR_OK; +} + +static int rsl10_auto_probe(struct flash_bank *bank) +{ + if (rsl10_bank_is_probed(bank)) + return ERROR_OK; + + return rsl10_probe(bank); +} + +static int rsl10_ll_flash_erase(struct rsl10_info *chip, uint32_t address) +{ + struct target *target = chip->target; + struct working_area *write_algorithm; + + LOG_DEBUG("erasing buffer flash address=0x%" PRIx32, address); + + int retval = target_alloc_working_area(target, sizeof(rsl10_rom_launcher_code), &write_algorithm); + if (retval != ERROR_OK) { + LOG_ERROR("Current working area 0x%x is too small! Increase working area size!", target->working_area_size); + return ERROR_FAIL; + } + + retval = + target_write_buffer(target, write_algorithm->address, sizeof(rsl10_rom_launcher_code), rsl10_rom_launcher_code); + if (retval != ERROR_OK) + goto free_algorithm; + + struct reg_param reg_params[3]; + struct armv7m_algorithm armv7m_info; + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* address */ + init_reg_param(®_params[1], "r3", 32, PARAM_OUT); /* cmd */ + init_reg_param(®_params[2], "sp", 32, PARAM_OUT); /* stack pointer */ + + buf_set_u32(reg_params[0].value, 0, 32, address); + uint32_t cmd; + retval = target_read_u32(target, RSL10_ROM_CMD_ERASE_SECTOR, &cmd); + if (retval != ERROR_OK) + goto free_reg_params; + buf_set_u32(reg_params[1].value, 0, 32, cmd); + buf_set_u32(reg_params[2].value, 0, 32, ALGO_STACK_POINTER_ADDR); + + retval = target_run_algorithm( + target, 0, NULL, ARRAY_SIZE(reg_params), reg_params, write_algorithm->address, + write_algorithm->address + sizeof(rsl10_rom_launcher_code) - 2, 1000, &armv7m_info + ); + if (retval != ERROR_OK) + goto free_reg_params; + + int algo_ret = buf_get_u32(reg_params[0].value, 0, 32); + if (algo_ret != RSL10_FLASH_ERR_NONE) { + LOG_ERROR("RSL10 ERASE ERROR: '%s' (%d)", rsl10_error(algo_ret), algo_ret); + retval = ERROR_FLASH_SECTOR_NOT_ERASED; + } + +free_reg_params: + for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++) + destroy_reg_param(®_params[i]); + +free_algorithm: + target_free_working_area(target, write_algorithm); + return retval; +} + +static int rsl10_ll_flash_write(struct rsl10_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes) +{ + struct target *target = chip->target; + struct working_area *write_algorithm; + + if (bytes == 8) { + uint32_t data; + data = buf_get_u32(buffer, 0, 32); + LOG_DEBUG("Writing 0x%" PRIx32 " to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, data, address, bytes); + } else + LOG_DEBUG("Writing buffer to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, address, bytes); + + /* allocate working area with flash programming code */ + int retval = target_alloc_working_area(target, sizeof(rsl10_rom_launcher_code), &write_algorithm); + if (retval != ERROR_OK) { + LOG_ERROR("Current working area 0x%x is too small! Increase working area size!", target->working_area_size); + return ERROR_FAIL; + } + + retval = + target_write_buffer(target, write_algorithm->address, sizeof(rsl10_rom_launcher_code), rsl10_rom_launcher_code); + if (retval != ERROR_OK) + goto free_algorithm; + + /* memory buffer, rounded down, to be multiple of 8 */ + uint32_t buffer_avail = target_get_working_area_avail(target) & ~7; + uint32_t buffer_size = MIN(RSL10_ROM_CMD_WRITE_BUFFER_MAX_SIZE, buffer_avail); + struct working_area *source; + retval = target_alloc_working_area(target, buffer_size, &source); + if (retval != ERROR_OK) { + LOG_ERROR("Current working area 0x%x is too small! Increase working area size!", target->working_area_size); + goto free_algorithm; + } + + struct reg_param reg_params[5]; + struct armv7m_algorithm armv7m_info; + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* start addr, return value */ + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* length */ + init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* data */ + init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* cmd */ + init_reg_param(®_params[4], "sp", 32, PARAM_OUT); /* stack pointer */ + buf_set_u32(reg_params[4].value, 0, 32, ALGO_STACK_POINTER_ADDR); + + uint32_t cmd = 0; + uint32_t sent_bytes = 0; + uint32_t write_address = 0; + uint32_t bytes_to_send = 0; + uint32_t remaining_bytes = 0; + + retval = target_read_u32(target, RSL10_ROM_CMD_WRITE_BUFFER, &cmd); + if (retval != ERROR_OK) + goto free_everything; + + while (sent_bytes < bytes) { + remaining_bytes = bytes - sent_bytes; + bytes_to_send = remaining_bytes >= buffer_size ? buffer_size : remaining_bytes; + + retval = target_write_buffer(target, source->address, bytes_to_send, buffer + sent_bytes); + if (retval != ERROR_OK) + goto free_everything; + + write_address = address + sent_bytes; + + LOG_DEBUG( + "write_address: 0x%" PRIx32 ", words: 0x%" PRIx32 ", source: 0x%" PRIx64 ", cmd: 0x%" PRIx32, write_address, + bytes_to_send / 4, source->address, cmd + ); + buf_set_u32(reg_params[0].value, 0, 32, write_address); + buf_set_u32(reg_params[1].value, 0, 32, bytes_to_send / 4); + buf_set_u32(reg_params[2].value, 0, 32, source->address); + buf_set_u32(reg_params[3].value, 0, 32, cmd); + + retval = target_run_algorithm( + target, 0, NULL, ARRAY_SIZE(reg_params), reg_params, write_algorithm->address, + write_algorithm->address + sizeof(rsl10_rom_launcher_code) - 2, 1000, &armv7m_info + ); + if (retval != ERROR_OK) + goto free_everything; + + int algo_ret = buf_get_u32(reg_params[0].value, 0, 32); + if (algo_ret != RSL10_FLASH_ERR_NONE) { + LOG_ERROR("RSL10 WRITE ERROR: '%s' (%d)", rsl10_error(algo_ret), algo_ret); + retval = ERROR_FLASH_OPERATION_FAILED; + goto free_everything; + } + + sent_bytes += bytes_to_send; + } + +free_everything: + target_free_working_area(target, source); + + for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++) + destroy_reg_param(®_params[i]); + +free_algorithm: + target_free_working_area(target, write_algorithm); + + return retval; +} + +static int rsl10_mass_erase(struct target *target) +{ + struct working_area *write_algorithm; + + int retval = target_alloc_working_area(target, sizeof(rsl10_rom_launcher_code), &write_algorithm); + if (retval != ERROR_OK) { + LOG_ERROR("Current working area 0x%x is too small! Increase working area size!", target->working_area_size); + return ERROR_FAIL; + } + + retval = + target_write_buffer(target, write_algorithm->address, sizeof(rsl10_rom_launcher_code), rsl10_rom_launcher_code); + if (retval != ERROR_OK) + goto free_algorithm; + + struct reg_param reg_params[3]; + struct armv7m_algorithm armv7m_info; + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* return value */ + init_reg_param(®_params[1], "r3", 32, PARAM_OUT); /* cmd */ + init_reg_param(®_params[2], "sp", 32, PARAM_OUT); /* stack pointer */ + + uint32_t cmd; + retval = target_read_u32(target, RSL10_ROM_CMD_ERASE_ALL, &cmd); + if (retval != ERROR_OK) + goto free_reg_params; + buf_set_u32(reg_params[1].value, 0, 32, cmd); + buf_set_u32(reg_params[2].value, 0, 32, ALGO_STACK_POINTER_ADDR); + + retval = target_run_algorithm( + target, 0, NULL, ARRAY_SIZE(reg_params), reg_params, write_algorithm->address, + write_algorithm->address + sizeof(rsl10_rom_launcher_code) - 2, 1000, &armv7m_info + ); + if (retval != ERROR_OK) + goto free_reg_params; + + int algo_ret = buf_get_u32(reg_params[0].value, 0, 32); + if (algo_ret != RSL10_FLASH_ERR_NONE) { + LOG_ERROR("RSL10 MASS ERASE ERROR: '%s' (%d)", rsl10_error(algo_ret), algo_ret); + retval = ERROR_FLASH_OPERATION_FAILED; + } + +free_reg_params: + for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++) + destroy_reg_param(®_params[i]); + +free_algorithm: + target_free_working_area(target, write_algorithm); + return retval; +} + +static int rsl10_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) +{ + struct rsl10_info *chip; + + int retval = rsl10_get_probed_chip_if_halted(bank, &chip); + if (retval != ERROR_OK) + return retval; + + return rsl10_ll_flash_write(chip, bank->base + offset, buffer, count); +} + +static int rsl10_erase(struct flash_bank *bank, unsigned int first, unsigned int last) +{ + LOG_INFO("erase bank: %x, %x", first, last); + int retval; + struct rsl10_info *chip; + + retval = rsl10_get_probed_chip_if_halted(bank, &chip); + if (retval != ERROR_OK) + return retval; + + for (unsigned int i = first; i <= last; i++) { + retval = rsl10_ll_flash_erase(chip, bank->base + i * 0x800); + if (retval != ERROR_OK) + return retval; + } + + return ERROR_OK; +} + +static void rsl10_free_driver_priv(struct flash_bank *bank) +{ + struct rsl10_bank *nbank = bank->driver_priv; + struct rsl10_info *chip = nbank->chip; + if (!chip) + return; + + chip->refcount--; + if (chip->refcount == 0) { + free(chip); + bank->driver_priv = NULL; + } +} + +static struct rsl10_info *rsl10_get_chip(struct target *target) +{ + struct flash_bank *bank_iter; + + /* iterate over rsl10 banks of same target */ + for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) { + if (bank_iter->driver != &rsl10_flash) + continue; + + if (bank_iter->target != target) + continue; + + struct rsl10_bank *nbank = bank_iter->driver_priv; + if (!nbank) + continue; + + if (nbank->chip) + return nbank->chip; + } + return NULL; +} + +FLASH_BANK_COMMAND_HANDLER(rsl10_flash_bank_command) +{ + struct rsl10_info *chip = NULL; + struct rsl10_bank *nbank = NULL; + LOG_INFO("Creating flash @ " TARGET_ADDR_FMT, bank->base); + + switch (bank->base) { + case RSL10_FLASH_ADDRESS_MAIN: + case RSL10_FLASH_ADDRESS_NVR1: + case RSL10_FLASH_ADDRESS_NVR2: + case RSL10_FLASH_ADDRESS_NVR3: + case RSL10_FLASH_ADDRESS_NVR4: + break; + default: + LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base); + return ERROR_FAIL; + } + + chip = rsl10_get_chip(bank->target); + if (!chip) { + chip = calloc(1, sizeof(*chip)); + if (!chip) + return ERROR_FAIL; + + chip->target = bank->target; + } + + switch (bank->base) { + case RSL10_FLASH_ADDRESS_MAIN: + nbank = &chip->bank[0]; + break; + case RSL10_FLASH_ADDRESS_NVR1: + nbank = &chip->bank[1]; + break; + case RSL10_FLASH_ADDRESS_NVR2: + nbank = &chip->bank[2]; + break; + case RSL10_FLASH_ADDRESS_NVR3: + nbank = &chip->bank[3]; + break; + case RSL10_FLASH_ADDRESS_NVR4: + nbank = &chip->bank[4]; + break; + } + assert(nbank); + + chip->refcount++; + nbank->chip = chip; + nbank->probed = false; + bank->driver_priv = nbank; + + return ERROR_OK; +} + +COMMAND_HANDLER(rsl10_lock_command) +{ + struct target *target = get_current_target(CMD_CTX); + + if (CMD_ARGC != 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct flash_bank *bank; + int retval = get_flash_bank_by_addr(target, RSL10_FLASH_ADDRESS_NVR3, true, &bank); + if (retval != ERROR_OK) + return retval; + + LOG_INFO("Keys used: %s %s %s %s", CMD_ARGV[0], CMD_ARGV[1], CMD_ARGV[2], CMD_ARGV[3]); + + uint32_t user_key[4]; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], user_key[0]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], user_key[1]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], user_key[2]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], user_key[3]); + + uint8_t write_buffer[6 * 4]; + target_buffer_set_u32(target, write_buffer, RSL10_KEY_DEBUG_LOCK); + target_buffer_set_u32_array(target, &write_buffer[4], 4, user_key); + /* pad the end to 64-bit word boundary */ + memset(&write_buffer[5 * 4], bank->default_padded_value, 4); + + retval = rsl10_erase(bank, 0, 0); + if (retval != ERROR_OK) + return retval; + + retval = rsl10_write(bank, write_buffer, RSL10_NVR3_USER_KEY_OFFSET, sizeof(write_buffer)); + if (retval != ERROR_OK) { + /* erase sector, if write fails, otherwise it can lock debug with wrong keys */ + return rsl10_erase(bank, 0, 0); + } + + command_print( + CMD, "****** WARNING ******\n" + "rsl10 device has been successfully prepared to lock.\n" + "Debug port is locked after restart.\n" + "Unlock with 'rsl10_unlock key0 key1 key2 key3'\n" + "****** ....... ******\n" + ); + + return rsl10_protect(bank, true, 0, 0); +} + +COMMAND_HANDLER(rsl10_unlock_command) +{ + if (CMD_ARGC != 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + struct cortex_m_common *cortex_m = target_to_cm(target); + + struct adiv5_dap *dap = cortex_m->armv7m.arm.dap; + struct adiv5_ap *ap = dap_get_ap(dap, 0); + + uint32_t user_key[4]; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], user_key[0]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], user_key[1]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], user_key[2]); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], user_key[3]); + + uint8_t write_buffer1[4 * 4]; + target_buffer_set_u32_array(target, write_buffer1, 4, user_key); + int retval = mem_ap_write_buf(ap, write_buffer1, 4, 4, RSL10_FLASH_REG_DEBUG_UNLOCK_KEY1); + if (retval != ERROR_OK) { + dap_put_ap(ap); + return retval; + } + + dap_put_ap(ap); + + uint32_t key; + retval = mem_ap_read_atomic_u32(ap, RSL10_FLASH_ADDRESS_LOCK_INFO_SETTING, &key); + if (retval != ERROR_OK) + return retval; + LOG_INFO("mem read: 0x%08" PRIx32, key); + + if (key == RSL10_KEY_DEBUG_LOCK) { + retval = command_run_line(CMD_CTX, "reset init"); + if (retval != ERROR_OK) + return retval; + + struct flash_bank *bank; + retval = get_flash_bank_by_addr(target, RSL10_FLASH_ADDRESS_NVR3, true, &bank); + if (retval != ERROR_OK) + return retval; + + retval = rsl10_protect(bank, false, 0, 0); + if (retval != ERROR_OK) + return retval; + + uint8_t write_buffer2[4 * 2]; + target_buffer_set_u32(target, write_buffer2, 0x1); + /* pad the end to 64-bit word boundary */ + memset(&write_buffer2[4], bank->default_padded_value, 4); + + /* let it fail, because sector is not erased, maybe just erase all? */ + (void)rsl10_write(bank, write_buffer2, RSL10_NVR3_USER_KEY_OFFSET, sizeof(write_buffer2)); + command_print(CMD, "Debug port is unlocked!"); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(rsl10_mass_erase_command) +{ + if (CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + int retval = rsl10_mass_erase(target); + if (retval != ERROR_OK) + return retval; + + command_print(CMD, "Mass erase was succesfull!"); + return ERROR_OK; +} + +static const struct command_registration rsl10_exec_command_handlers[] = { + { + .name = "lock", + .handler = rsl10_lock_command, + .mode = COMMAND_EXEC, + .help = "Lock rsl10 debug, with passed keys", + .usage = "key1 key2 key3 key4", + }, + { + .name = "unlock", + .handler = rsl10_unlock_command, + .mode = COMMAND_EXEC, + .help = "Unlock rsl10 debug, with passed keys", + .usage = "key1 key2 key3 key4", + }, + { + .name = "mass_erase", + .handler = rsl10_mass_erase_command, + .mode = COMMAND_EXEC, + .help = "Mass erase all unprotected flash areas", + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration rsl10_command_handlers[] = { + { + .name = "rsl10", + .mode = COMMAND_ANY, + .help = "rsl10 flash command group", + .usage = "", + .chain = rsl10_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +const struct flash_driver rsl10_flash = { + .name = "rsl10", + .commands = rsl10_command_handlers, + .flash_bank_command = rsl10_flash_bank_command, + .erase = rsl10_erase, + .protect = rsl10_protect, + .write = rsl10_write, + .read = default_flash_read, + .probe = rsl10_probe, + .auto_probe = rsl10_auto_probe, + .erase_check = default_flash_blank_check, + .protect_check = rsl10_protect_check, + .free_driver_priv = rsl10_free_driver_priv, +}; diff --git a/src/flash/nor/sfdp.c b/src/flash/nor/sfdp.c index e177a19453..8e25ba680b 100644 --- a/src/flash/nor/sfdp.c +++ b/src/flash/nor/sfdp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2019 by Andreas Bolsch <andreas.bolsch@mni.thm.de * @@ -12,7 +12,6 @@ #include "spi.h" #include "sfdp.h" -#define SFDP_MAGIC 0x50444653 #define SFDP_ACCESS_PROT 0xFF #define SFDP_BASIC_FLASH 0xFF00 #define SFDP_4BYTE_ADDR 0xFF84 @@ -100,11 +99,11 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev, goto err; for (k = 0; k < nph; k++) { - uint8_t words = (pheaders[k].revision >> 24) & 0xFF; + unsigned int words = (pheaders[k].revision >> 24) & 0xFF; uint16_t id = (((pheaders[k].ptr) >> 16) & 0xFF00) | (pheaders[k].revision & 0xFF); uint32_t ptr = pheaders[k].ptr & 0xFFFFFF; - LOG_DEBUG("pheader %d len=0x%02" PRIx8 " id=0x%04" PRIx16 + LOG_DEBUG("pheader %d len=0x%02x id=0x%04" PRIx16 " ptr=0x%06" PRIx32, k, words, id, ptr); /* retrieve parameter table */ diff --git a/src/flash/nor/sfdp.h b/src/flash/nor/sfdp.h index 1c9af326b3..0d43519f65 100644 --- a/src/flash/nor/sfdp.h +++ b/src/flash/nor/sfdp.h @@ -7,6 +7,8 @@ #ifndef OPENOCD_FLASH_NOR_SFDP_H #define OPENOCD_FLASH_NOR_SFDP_H +#define SFDP_MAGIC 0x50444653 + /* per JESD216D 'addr' is *byte* based but must be word aligned, * 'buffer' is word based, word aligned and always little-endian encoded, * in the flash, 'addr_len' is 3 or 4, 'dummy' ***usually*** 8 @@ -16,7 +18,7 @@ * * buffer contents is supposed to be returned in ***host*** endianness */ typedef int (*read_sfdp_block_t)(struct flash_bank *bank, uint32_t addr, - uint32_t words, uint32_t *buffer); + unsigned int words, uint32_t *buffer); extern int spi_sfdp(struct flash_bank *bank, struct flash_device *dev, read_sfdp_block_t read_sfdp_block); diff --git a/src/flash/nor/sh_qspi.c b/src/flash/nor/sh_qspi.c index 691c137dcb..e8ca626df0 100644 --- a/src/flash/nor/sh_qspi.c +++ b/src/flash/nor/sh_qspi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-License-Identifier: GPL-2.0-only /* * SH QSPI (Quad SPI) driver diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c index eede4825f8..58d7913c26 100644 --- a/src/flash/nor/sim3x.c +++ b/src/flash/nor/sim3x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2014 by Ladislav Bábel * @@ -859,7 +859,7 @@ static int sim3x_flash_info(struct flash_bank *bank, struct command_invocation * * reg 3:2 - register * reg 1:0 - no effect */ -static int ap_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value) +static int ap_write_register(struct adiv5_dap *dap, unsigned int reg, uint32_t value) { LOG_DEBUG("DAP_REG[0x%02x] <- %08" PRIX32, reg, value); @@ -886,7 +886,7 @@ static int ap_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value return ERROR_OK; } -static int ap_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result) +static int ap_read_register(struct adiv5_dap *dap, unsigned int reg, uint32_t *result) { struct adiv5_ap *ap = dap_get_ap(dap, SIM3X_AP); if (!ap) { @@ -912,7 +912,7 @@ static int ap_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *resul return ERROR_OK; } -static int ap_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value, int timeout) +static int ap_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value, int timeout) { uint32_t val; int retval; diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c index 8f35d8f168..7f03f1fead 100644 --- a/src/flash/nor/spi.c +++ b/src/flash/nor/spi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Andreas Bolsch * @@ -22,8 +22,27 @@ /* Shared table of known SPI flash devices for SPI-based flash drivers. Taken * from device datasheets and Linux SPI flash drivers. */ const struct flash_device flash_devices[] = { - /* name, read_cmd, qread_cmd, pprog_cmd, erase_cmd, chip_erase_cmd, device_id, - * pagesize, sectorsize, size_in_bytes */ + /* Note: device_id is usually 3 bytes long, however the unused highest byte counts + * continuation codes for manufacturer id as per JEP106xx. + * + * All sizes (page, sector/block and flash) are in bytes. + * + * Guide to select a proper erase command (if both sector and block erase cmds are available): + * Use 4kbit sector erase cmd and set erase size to the size of sector for small devices + * (4Mbit and less, size <= 0x80000) to prevent too raw erase granularity. + * Use 64kbit block erase cmd and set erase size to the size of block for bigger devices + * (8Mbit and more, size >= 0x100000) to keep erase speed reasonable. + * If the device implements also 32kbit block erase, use it for 8Mbit, size == 0x100000. + */ + /* name read qread page erase chip device_id page erase flash + * _cmd _cmd _prog _cmd* _erase size size* size + * _cmd _cmd + */ + FLASH_ID("st m25pe10", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00118020, 0x100, 0x10000, 0x20000), + FLASH_ID("st m25pe20", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00128020, 0x100, 0x10000, 0x40000), + FLASH_ID("st m25pe40", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00138020, 0x100, 0x10000, 0x80000), + FLASH_ID("st m25pe80", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00148020, 0x100, 0x10000, 0x100000), + FLASH_ID("st m25pe16", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00158020, 0x100, 0x10000, 0x200000), FLASH_ID("st m25p05", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00102020, 0x80, 0x8000, 0x10000), FLASH_ID("st m25p10", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00112020, 0x80, 0x8000, 0x20000), FLASH_ID("st m25p20", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00122020, 0x100, 0x10000, 0x40000), @@ -51,12 +70,28 @@ const struct flash_device flash_devices[] = { FLASH_ID("cyp s25fl064l", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00176001, 0x100, 0x10000, 0x800000), FLASH_ID("cyp s25fl128l", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00186001, 0x100, 0x10000, 0x1000000), FLASH_ID("cyp s25fl256l", 0x13, 0x00, 0x12, 0xdc, 0xc7, 0x00196001, 0x100, 0x10000, 0x2000000), + FLASH_ID("cyp s28hl256t", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x00195a34, 0x100, 0x40000, 0x2000000), /* page! */ + FLASH_ID("cyp s28hs256t", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x00195b34, 0x100, 0x40000, 0x2000000), /* page! */ + FLASH_ID("cyp s28hl512t", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001a5a34, 0x100, 0x40000, 0x4000000), /* page! */ + FLASH_ID("cyp s28hs512t", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001a5b34, 0x100, 0x40000, 0x4000000), /* page! */ + FLASH_ID("cyp s28hl01gt", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001b5a34, 0x100, 0x40000, 0x8000000), /* page! */ + FLASH_ID("cyp s28hs01gt", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001b5b34, 0x100, 0x40000, 0x8000000), /* page! */ FLASH_ID("atmel 25f512", 0x03, 0x00, 0x02, 0x52, 0xc7, 0x0065001f, 0x80, 0x8000, 0x10000), FLASH_ID("atmel 25f1024", 0x03, 0x00, 0x02, 0x52, 0x62, 0x0060001f, 0x100, 0x8000, 0x20000), FLASH_ID("atmel 25f2048", 0x03, 0x00, 0x02, 0x52, 0x62, 0x0063001f, 0x100, 0x10000, 0x40000), FLASH_ID("atmel 25f4096", 0x03, 0x00, 0x02, 0x52, 0x62, 0x0064001f, 0x100, 0x10000, 0x80000), FLASH_ID("atmel 25fs040", 0x03, 0x00, 0x02, 0xd7, 0xc7, 0x0004661f, 0x100, 0x10000, 0x80000), + FLASH_ID("adesto 25sf041b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001841f, 0x100, 0x10000, 0x80000), FLASH_ID("adesto 25df081a", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001451f, 0x100, 0x10000, 0x100000), + FLASH_ID("adesto 25sf081b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001851f, 0x100, 0x10000, 0x100000), + FLASH_ID("adesto 25sf161b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001861f, 0x100, 0x10000, 0x200000), + FLASH_ID("adesto 25df321b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001471f, 0x100, 0x10000, 0x400000), + FLASH_ID("adesto 25sf321b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001871f, 0x100, 0x10000, 0x400000), + FLASH_ID("adesto 25xf641b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001881f, 0x100, 0x10000, 0x800000), /* sf/qf */ + FLASH_ID("adesto 25xf128a", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0001891f, 0x100, 0x10000, 0x1000000), /* sf/qf */ + FLASH_ID("adesto xp032", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0700a743, 0x100, 0x10000, 0x400000), /* 4-byte */ + FLASH_ID("adesto xp064b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0001a81f, 0x100, 0x10000, 0x800000), /* 4-byte */ + FLASH_ID("adesto xp128", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0000a91f, 0x100, 0x10000, 0x1000000), /* 4-byte */ FLASH_ID("mac 25l512", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001020c2, 0x010, 0x10000, 0x10000), FLASH_ID("mac 25l1005", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001120c2, 0x010, 0x10000, 0x20000), FLASH_ID("mac 25l2005", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001220c2, 0x010, 0x10000, 0x40000), @@ -78,6 +113,9 @@ const struct flash_device flash_devices[] = { FLASH_ID("mac 25r3235f", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001628c2, 0x100, 0x10000, 0x400000), FLASH_ID("mac 25r6435f", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001728c2, 0x100, 0x10000, 0x800000), FLASH_ID("mac 25u1635e", 0x03, 0xeb, 0x02, 0x20, 0xc7, 0x003525c2, 0x100, 0x1000, 0x100000), + FLASH_ID("mac 66l1g45g", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001b20c2, 0x100, 0x10000, 0x8000000), + FLASH_ID("mac 66um1g45g", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x003b80c2, 0x100, 0x10000, 0x8000000), + FLASH_ID("mac 66lm1g45g", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x003b85c2, 0x100, 0x10000, 0x8000000), FLASH_ID("micron n25q032", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0016ba20, 0x100, 0x10000, 0x400000), FLASH_ID("micron n25q064", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0017ba20, 0x100, 0x10000, 0x800000), FLASH_ID("micron n25q128", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0018ba20, 0x100, 0x10000, 0x1000000), @@ -102,6 +140,10 @@ const struct flash_device flash_devices[] = { FLASH_ID("win w25q256fv/jv", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x001940ef, 0x100, 0x10000, 0x2000000), FLASH_ID("win w25q256fv", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x001960ef, 0x100, 0x10000, 0x2000000), /* QPI mode */ FLASH_ID("win w25q256jv", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001970ef, 0x100, 0x10000, 0x2000000), + FLASH_ID("win w25q512jv", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x002040ef, 0x100, 0x10000, 0x4000000), + FLASH_ID("win w25q01jv", 0x13, 0x00, 0x12, 0xdc, 0xc7, 0x002140ef, 0x100, 0x10000, 0x8000000), + FLASH_ID("win w25q01jv-dtr", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x002170ef, 0x100, 0x10000, 0x8000000), + FLASH_ID("win w25q02jv-dtr", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x002270ef, 0x100, 0x10000, 0x10000000), FLASH_ID("gd gd25q512", 0x03, 0x00, 0x02, 0x20, 0xc7, 0x001040c8, 0x100, 0x1000, 0x10000), FLASH_ID("gd gd25q10", 0x03, 0x00, 0x02, 0x20, 0xc7, 0x001140c8, 0x100, 0x1000, 0x20000), FLASH_ID("gd gd25q20", 0x03, 0x00, 0x02, 0x20, 0xc7, 0x001240c8, 0x100, 0x1000, 0x40000), @@ -109,9 +151,18 @@ const struct flash_device flash_devices[] = { FLASH_ID("gd gd25q16c", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001540c8, 0x100, 0x10000, 0x200000), FLASH_ID("gd gd25q32c", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001640c8, 0x100, 0x10000, 0x400000), FLASH_ID("gd gd25q64c", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001740c8, 0x100, 0x10000, 0x800000), - FLASH_ID("gd gd25q128c", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x001840c8, 0x100, 0x10000, 0x1000000), + FLASH_ID("gd gd25q128c", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x001840c8, 0x100, 0x10000, 0x1000000), FLASH_ID("gd gd25q256c", 0x13, 0x00, 0x12, 0xdc, 0xc7, 0x001940c8, 0x100, 0x10000, 0x2000000), FLASH_ID("gd gd25q512mc", 0x13, 0x00, 0x12, 0xdc, 0xc7, 0x002040c8, 0x100, 0x10000, 0x4000000), + FLASH_ID("gd gd25lx256e", 0x13, 0x0c, 0x12, 0xdc, 0xc7, 0x001968c8, 0x100, 0x10000, 0x2000000), + FLASH_ID("zbit zb25vq16", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0015605e, 0x100, 0x10000, 0x200000), + FLASH_ID("zbit zb25vq32", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0016405e, 0x100, 0x10000, 0x400000), + FLASH_ID("zbit zb25vq32", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0016605e, 0x100, 0x10000, 0x400000), /* QPI mode */ + FLASH_ID("zbit zb25vq64", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0017405e, 0x100, 0x10000, 0x800000), + FLASH_ID("zbit zb25vq64", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0017605e, 0x100, 0x10000, 0x800000), /* QPI mode */ + FLASH_ID("zbit zb25vq128", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0018405e, 0x100, 0x10000, 0x1000000), + FLASH_ID("zbit zb25vq128", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0018605e, 0x100, 0x10000, 0x1000000), /* QPI mode */ + FLASH_ID("issi is25lq040b", 0x03, 0xeb, 0x02, 0x20, 0xc7, 0x0013409d, 0x100, 0x1000, 0x80000), FLASH_ID("issi is25lp032", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0016609d, 0x100, 0x10000, 0x400000), FLASH_ID("issi is25lp064", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0017609d, 0x100, 0x10000, 0x800000), FLASH_ID("issi is25lp128d", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0018609d, 0x100, 0x10000, 0x1000000), @@ -120,8 +171,36 @@ const struct flash_device flash_devices[] = { FLASH_ID("issi is25wp256d", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x0019709d, 0x100, 0x10000, 0x2000000), FLASH_ID("issi is25lp512m", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001a609d, 0x100, 0x10000, 0x4000000), FLASH_ID("issi is25wp512m", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x001a709d, 0x100, 0x10000, 0x4000000), + FLASH_ID("xtx xt25f02e", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0012400b, 0x100, 0x10000, 0x40000), + FLASH_ID("xtx xt25f04d", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0013400b, 0x100, 0x10000, 0x80000), + FLASH_ID("xtx xt25f08b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0014400b, 0x100, 0x10000, 0x100000), + FLASH_ID("xtx xt25f16b", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0015400b, 0x100, 0x10000, 0x200000), + FLASH_ID("xtx xt25f32b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0016400b, 0x100, 0x10000, 0x200000), + FLASH_ID("xtx xt25f64b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0017400b, 0x100, 0x10000, 0x400000), + FLASH_ID("xtx xt25f128b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0018400b, 0x100, 0x10000, 0x800000), + FLASH_ID("xtx xt25q08d", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0014600b, 0x100, 0x10000, 0x100000), + FLASH_ID("xtx xt25q16b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0015600b, 0x100, 0x10000, 0x200000), + FLASH_ID("xtx xt25q32b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0016600b, 0x100, 0x10000, 0x400000), /* exists ? */ + FLASH_ID("xtx xt25q64b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0017600b, 0x100, 0x10000, 0x800000), + FLASH_ID("xtx xt25q128b", 0x03, 0x0b, 0x02, 0xd8, 0xc7, 0x0018600b, 0x100, 0x10000, 0x1000000), + FLASH_ID("zetta zd25q16", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001560ba, 0x100, 0x10000, 0x200000), + FLASH_ID("puya p25q05", 0x03, 0x6b, 0x02, 0x20, 0xc7, 0x00106085, 0x100, 0x1000, 0x10000), + FLASH_ID("puya p25q10", 0x03, 0x6b, 0x02, 0x20, 0xc7, 0x00116085, 0x100, 0x1000, 0x20000), + FLASH_ID("puya p25q20", 0x03, 0x6b, 0x02, 0x20, 0xc7, 0x00126085, 0x100, 0x1000, 0x40000), + FLASH_ID("puya p25q40", 0x03, 0x6b, 0x02, 0x20, 0xc7, 0x00136085, 0x100, 0x1000, 0x80000), + FLASH_ID("puya p25q80", 0x03, 0x6b, 0x02, 0x52, 0xc7, 0x00146085, 0x100, 0x8000, 0x100000), + FLASH_ID("puya p25q16", 0x03, 0x6b, 0x02, 0xd8, 0xc7, 0x00156085, 0x100, 0x10000, 0x200000), + FLASH_ID("puya p25q32", 0x03, 0x6b, 0x02, 0xd8, 0xc7, 0x00166085, 0x100, 0x10000, 0x400000), + FLASH_ID("puya p25q64", 0x03, 0x6b, 0x02, 0xd8, 0xc7, 0x00176085, 0x100, 0x10000, 0x800000), + FLASH_ID("puya p25q128", 0x03, 0x6b, 0x02, 0xd8, 0xc7, 0x00186085, 0x100, 0x10000, 0x1000000), + /* FRAM, no erase commands, no write page or sectors */ + + /* name read qread page device_id total + * _cmd _cmd _prog size + * _cmd + */ FRAM_ID("fu mb85rs16n", 0x03, 0, 0x02, 0x00010104, 0x800), FRAM_ID("fu mb85rs32v", 0x03, 0, 0x02, 0x00010204, 0x1000), /* exists ? */ FRAM_ID("fu mb85rs64v", 0x03, 0, 0x02, 0x00020304, 0x2000), @@ -130,13 +209,30 @@ const struct flash_device flash_devices[] = { FRAM_ID("fu mb85rs512t", 0x03, 0, 0x02, 0x00032604, 0x10000), FRAM_ID("fu mb85rs1mt", 0x03, 0, 0x02, 0x00032704, 0x20000), FRAM_ID("fu mb85rs2mta", 0x03, 0, 0x02, 0x00034804, 0x40000), - FRAM_ID("cyp fm25v01a", 0x03, 0, 0x02, 0x000821c2, 0x4000), - FRAM_ID("cyp fm25v02", 0x03, 0, 0x02, 0x000022c2, 0x8000), - FRAM_ID("cyp fm25v02a", 0x03, 0, 0x02, 0x000822c2, 0x8000), - FRAM_ID("cyp fm25v05", 0x03, 0, 0x02, 0x000023c2, 0x10000), - FRAM_ID("cyp fm25v10", 0x03, 0, 0x02, 0x000024c2, 0x20000), - FRAM_ID("cyp fm25v20a", 0x03, 0, 0x02, 0x000825c2, 0x40000), - FRAM_ID("cyp fm25v40", 0x03, 0, 0x02, 0x004026c2, 0x80000), + FRAM_ID("cyp fm25v01a", 0x03, 0, 0x02, 0x060821c2, 0x4000), + FRAM_ID("cyp fm25v02", 0x03, 0, 0x02, 0x060022c2, 0x8000), + FRAM_ID("cyp fm25v02a", 0x03, 0, 0x02, 0x060822c2, 0x8000), + FRAM_ID("cyp fm25v05", 0x03, 0, 0x02, 0x060023c2, 0x10000), + FRAM_ID("cyp fm25v10", 0x03, 0, 0x02, 0x060024c2, 0x20000), + FRAM_ID("cyp fm25v20a", 0x03, 0, 0x02, 0x060825c2, 0x40000), + FRAM_ID("cyp fm25v40", 0x03, 0, 0x02, 0x064026c2, 0x80000), + FRAM_ID("cyp cy15b102qn", 0x03, 0, 0x02, 0x06002ac2, 0x40000), + FRAM_ID("cyp cy15v102qn", 0x03, 0, 0x02, 0x06042ac2, 0x40000), + FRAM_ID("cyp cy15b104qi", 0x03, 0, 0x02, 0x06012dc2, 0x80000), + FRAM_ID("cyp cy15b104qi", 0x03, 0, 0x02, 0x06a12dc2, 0x80000), + FRAM_ID("cyp cy15v104qi", 0x03, 0, 0x02, 0x06052dc2, 0x80000), + FRAM_ID("cyp cy15v104qi", 0x03, 0, 0x02, 0x06a52dc2, 0x80000), + FRAM_ID("cyp cy15b104qn", 0x03, 0, 0x02, 0x06402cc2, 0x80000), + FRAM_ID("cyp cy15b108qi", 0x03, 0, 0x02, 0x06012fc2, 0x100000), + FRAM_ID("cyp cy15b108qi", 0x03, 0, 0x02, 0x06a12fc2, 0x100000), + FRAM_ID("cyp cy15v108qi", 0x03, 0, 0x02, 0x06052fc2, 0x100000), + FRAM_ID("cyp cy15v108qi", 0x03, 0, 0x02, 0x06a52fc2, 0x100000), + FRAM_ID("cyp cy15b108qn", 0x03, 0, 0x02, 0x06012ec2, 0x100000), + FRAM_ID("cyp cy15b108qn", 0x03, 0, 0x02, 0x06032ec2, 0x100000), + FRAM_ID("cyp cy15b108qn", 0x03, 0, 0x02, 0x06a12ec2, 0x100000), + FRAM_ID("cyp cy15v108qn", 0x03, 0, 0x02, 0x06052ec2, 0x100000), + FRAM_ID("cyp cy15v108qn", 0x03, 0, 0x02, 0x06072ec2, 0x100000), + FRAM_ID("cyp cy15v108qn", 0x03, 0, 0x02, 0x06a52ec2, 0x100000), FLASH_ID(NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0) }; diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index aa323d6368..f7dcc6f0e3 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin * @@ -453,7 +453,7 @@ FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command) if (CMD_ARGC < 6) return ERROR_COMMAND_SYNTAX_ERROR; - stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1); + stellaris_info = calloc(1, sizeof(struct stellaris_flash_bank)); bank->base = 0x0; bank->driver_priv = stellaris_info; @@ -530,7 +530,7 @@ static void stellaris_set_flash_timing(struct flash_bank *bank) target_write_u32(target, SCB_BASE | USECRL, usecrl); } -static const unsigned rcc_xtal[32] = { +static const unsigned int rcc_xtal[32] = { [0x00] = 1000000, /* no pll */ [0x01] = 1843200, /* no pll */ [0x02] = 2000000, /* no pll */ @@ -569,7 +569,7 @@ static void stellaris_read_clock_info(struct flash_bank *bank) struct stellaris_flash_bank *stellaris_info = bank->driver_priv; struct target *target = bank->target; uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc; - unsigned xtal; + unsigned int xtal; unsigned long mainfreq; target_read_u32(target, SCB_BASE | RCC, &rcc); @@ -1029,7 +1029,7 @@ static int stellaris_write_block(struct flash_bank *bank, int retval = ERROR_OK; /* power of two, and multiple of word size */ - static const unsigned buf_min = 128; + static const unsigned int buf_min = 128; /* for small buffers it's faster not to download an algorithm */ if (wcount * 4 < buf_min) @@ -1056,8 +1056,8 @@ static int stellaris_write_block(struct flash_bank *bank, target_free_working_area(target, write_algorithm); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)", - target_name(target), (unsigned) buffer_size); + LOG_DEBUG("retry target_alloc_working_area(%s, size=%" PRIu32 ")", + target_name(target), buffer_size); } target_write_buffer(target, write_algorithm->address, @@ -1342,7 +1342,7 @@ COMMAND_HANDLER(stellaris_handle_recover_command) * cycle to recover. */ - Jim_Eval_Named(CMD_CTX->interp, "catch { hla_command \"debug unlock\" }", 0, 0); + Jim_Eval_Named(CMD_CTX->interp, "catch { hla command \"debug unlock\" }", NULL, 0); if (!strcmp(Jim_GetString(Jim_GetResult(CMD_CTX->interp), NULL), "0")) { retval = ERROR_OK; goto user_action; diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index 455a06a9b8..5a3c2da663 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -473,7 +473,7 @@ static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buff /* memory buffer */ buffer_size = target_get_working_area_avail(target); - buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256)); + buffer_size = MIN(hwords_count * 2 + 8, MAX(buffer_size, 256)); /* Normally we allocate all available working area. * MIN shrinks buffer_size if the size of the written block is smaller. * MAX prevents using async algo if the available working area is smaller @@ -743,8 +743,9 @@ static int stm32x_get_property_addr(struct target *target, struct stm32x_propert return ERROR_TARGET_NOT_EXAMINED; } - switch (cortex_m_get_partno_safe(target)) { + switch (cortex_m_get_impl_part(target)) { case CORTEX_M0_PARTNO: /* STM32F0x devices */ + case CORTEX_M0P_PARTNO: /* APM32F0x devices */ addr->device_id = 0x40015800; addr->flash_size = 0x1FFFF7CC; return ERROR_OK; @@ -1006,7 +1007,7 @@ static int stm32x_probe(struct flash_bank *bank) flash_size_in_kb = stm32x_info->user_bank_size / 1024; } - LOG_INFO("flash size = %dkbytes", flash_size_in_kb); + LOG_INFO("flash size = %d KiB", flash_size_in_kb); /* did we assign flash size? */ assert(flash_size_in_kb != 0xffff); diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c index 5e95b9b6b5..3bafde56f8 100644 --- a/src/flash/nor/stm32f2x.c +++ b/src/flash/nor/stm32f2x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -230,11 +230,11 @@ static int stm32x_otp_enable(struct flash_bank *bank) struct stm32x_flash_bank *stm32x_info = bank->driver_priv; if (!stm32x_info->otp_unlocked) { - LOG_INFO("OTP memory bank #%u is is enabled for write commands.", + LOG_INFO("OTP memory bank #%u is enabled for write commands.", bank->bank_number); stm32x_info->otp_unlocked = true; } else { - LOG_WARNING("OTP memory bank #%u is is already enabled for write commands.", + LOG_WARNING("OTP memory bank #%u is already enabled for write commands.", bank->bank_number); } return ERROR_OK; @@ -659,8 +659,10 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first, } if (stm32x_is_otp(bank)) { - if (!set) + if (!set) { + LOG_ERROR("OTP protection can only be enabled"); return ERROR_COMMAND_ARGUMENT_INVALID; + } return stm32x_otp_protect(bank, first, last); } @@ -959,7 +961,7 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) return retval; if ((*device_id & 0xfff) == 0x411 - && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) { + && cortex_m_get_impl_part(target) == CORTEX_M4_PARTNO) { *device_id &= ~((0xFFFF << 16) | 0xfff); *device_id |= (0x1000 << 16) | 0x413; LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE"); @@ -1018,7 +1020,7 @@ static int stm32x_probe(struct flash_bank *bank) assert(num_sectors > 0); bank->num_sectors = num_sectors; - bank->sectors = calloc(sizeof(struct flash_sector), num_sectors); + bank->sectors = calloc(num_sectors, sizeof(struct flash_sector)); if (stm32x_otp_is_f7(bank)) bank->size = STM32F7_OTP_SIZE; @@ -1125,7 +1127,7 @@ static int stm32x_probe(struct flash_bank *bank) flash_size_in_kb = stm32x_info->user_bank_size / 1024; } - LOG_INFO("flash size = %" PRIu16 " kbytes", flash_size_in_kb); + LOG_INFO("flash size = %" PRIu16 " KiB", flash_size_in_kb); /* did we assign flash size? */ assert(flash_size_in_kb != 0xffff); @@ -1538,10 +1540,8 @@ static int stm32x_mass_erase(struct flash_bank *bank) COMMAND_HANDLER(stm32x_handle_mass_erase_command) { - if (CMD_ARGC < 1) { - command_print(CMD, "stm32x mass_erase <bank>"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -1564,10 +1564,8 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command) struct flash_bank *bank; struct stm32x_flash_bank *stm32x_info = NULL; - if (CMD_ARGC != 1) { - command_print(CMD, "stm32f2x options_read <bank>"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); if (retval != ERROR_OK) @@ -1610,10 +1608,8 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) struct stm32x_flash_bank *stm32x_info = NULL; uint16_t user_options, boot_addr0, boot_addr1, options_mask; - if (CMD_ARGC < 1) { - command_print(CMD, "stm32f2x options_write <bank> ..."); + if (CMD_ARGC < 1) return ERROR_COMMAND_SYNTAX_ERROR; - } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); if (retval != ERROR_OK) @@ -1625,19 +1621,14 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) stm32x_info = bank->driver_priv; if (stm32x_info->has_boot_addr) { - if (CMD_ARGC != 4) { - command_print(CMD, "stm32f2x options_write <bank> <user_options>" - " <boot_addr0> <boot_addr1>"); + if (CMD_ARGC != 4) return ERROR_COMMAND_SYNTAX_ERROR; - } + COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0); COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1); stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16); - } else { - if (CMD_ARGC != 2) { - command_print(CMD, "stm32f2x options_write <bank> <user_options>"); - return ERROR_COMMAND_SYNTAX_ERROR; - } + } else if (CMD_ARGC != 2) { + return ERROR_COMMAND_SYNTAX_ERROR; } COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options); @@ -1672,10 +1663,8 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command) struct stm32x_flash_bank *stm32x_info = NULL; uint32_t optcr2_pcrop; - if (CMD_ARGC != 2) { - command_print(CMD, "stm32f2x optcr2_write <bank> <optcr2_value>"); + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; - } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); if (retval != ERROR_OK) @@ -1709,10 +1698,8 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command) COMMAND_HANDLER(stm32x_handle_otp_command) { - if (CMD_ARGC < 2) { - command_print(CMD, "stm32x otp <bank> (enable|disable|show)"); + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -1785,7 +1772,7 @@ static const struct command_registration stm32f2x_exec_command_handlers[] = { .name = "otp", .handler = stm32x_handle_otp_command, .mode = COMMAND_EXEC, - .usage = "bank_id", + .usage = "bank_id (enable|disable|show)", .help = "OTP (One Time Programmable) memory write enable/disable.", }, COMMAND_REGISTRATION_DONE diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c index 126caa9cd5..c02fae992c 100644 --- a/src/flash/nor/stm32h7x.c +++ b/src/flash/nor/stm32h7x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by STMicroelectronics * @@ -795,7 +795,7 @@ static int stm32x_probe(struct flash_bank *bank) /* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */ retval = ERROR_FAIL; if (device_id == DEVID_STM32H74_H75XX - && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) + && cortex_m_get_impl_part(target) == CORTEX_M4_PARTNO) LOG_WARNING("%s cannot read the flash size register", target_name(target)); else retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb); @@ -1080,10 +1080,8 @@ static int stm32x_mass_erase(struct flash_bank *bank) COMMAND_HANDLER(stm32x_handle_mass_erase_command) { - if (CMD_ARGC < 1) { - command_print(CMD, "stm32h7x mass_erase <bank>"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -1101,10 +1099,8 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) COMMAND_HANDLER(stm32x_handle_option_read_command) { - if (CMD_ARGC < 2) { - command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>"); + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -1126,10 +1122,8 @@ COMMAND_HANDLER(stm32x_handle_option_read_command) COMMAND_HANDLER(stm32x_handle_option_write_command) { - if (CMD_ARGC < 3) { - command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]"); + if (CMD_ARGC != 3 && CMD_ARGC != 4) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index 2b428f032a..f16333201b 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Uwe Bonnes * @@ -57,6 +57,9 @@ */ /* STM32WBxxx series for reference. + * + * RM0493 (STM32WBA52x) + * http://www.st.com/resource/en/reference_manual/dm00821869.pdf * * RM0434 (STM32WB55/WB35x) * http://www.st.com/resource/en/reference_manual/dm00318631.pdf @@ -80,6 +83,12 @@ * http://www.st.com/resource/en/reference_manual/dm00451556.pdf */ +/* STM32C0xxx series for reference. + * + * RM0490 (STM32C0x1) + * http://www.st.com/resource/en/reference_manual/dm00781702.pdf + */ + /* STM32G0xxx series for reference. * * RM0444 (STM32G0x1) @@ -111,6 +120,18 @@ * http://www.st.com/resource/en/reference_manual/dm00346336.pdf */ +/* STM32U0xxx series for reference. + * + * RM0503 (STM32U0xx) + * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + */ + +/* STM32U5xxx series for reference. + * + * RM0456 (STM32U5xx) + * http://www.st.com/resource/en/reference_manual/dm00477635.pdf + */ + /* Erase time can be as high as 25ms, 10x this and assume it's toast... */ #define FLASH_ERASE_TIMEOUT 250 @@ -263,7 +284,7 @@ struct stm32l4_wrp { }; /* human readable list of families this drivers supports (sorted alphabetically) */ -static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL"; +static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL"; static const struct stm32l4_rev stm32l47_l48xx_revs[] = { { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" } @@ -273,6 +294,27 @@ static const struct stm32l4_rev stm32l43_l44xx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" }, }; + +static const struct stm32l4_rev stm32c01xx_revs[] = { + { 0x1000, "A" }, { 0x1001, "Z" }, +}; + +static const struct stm32l4_rev stm32c03xx_revs[] = { + { 0x1000, "A" }, { 0x1001, "Z" }, +}; + +static const struct stm32l4_rev stm32c05xx_revs[] = { + { 0x1000, "A" }, +}; + +static const struct stm32l4_rev stm32c071xx_revs[] = { + { 0x1001, "Z" }, +}; + +static const struct stm32l4_rev stm32c09xx_revs[] = { + { 0x1000, "A" }, +}; + static const struct stm32l4_rev stm32g05_g06xx_revs[] = { { 0x1000, "A" }, }; @@ -289,7 +331,7 @@ static const struct stm32l4_rev stm32l45_l46xx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" }, }; -static const struct stm32l4_rev stm32l41_L42xx_revs[] = { +static const struct stm32l4_rev stm32l41_l42xx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" }, }; @@ -301,6 +343,10 @@ static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = { { 0x1000, "A" }, }; +static const struct stm32l4_rev stm32u0xx_revs[] = { + { 0x1000, "A" }, +}; + static const struct stm32l4_rev stm32g43_g44xx_revs[] = { { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" }, }; @@ -311,6 +357,7 @@ static const struct stm32l4_rev stm32g47_g48xx_revs[] = { static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" }, + { 0x101F, "V" }, }; static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = { @@ -318,15 +365,32 @@ static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = { }; static const struct stm32l4_rev stm32l55_l56xx_revs[] = { - { 0x1000, "A" }, { 0x2000, "B" }, + { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" }, }; static const struct stm32l4_rev stm32g49_g4axx_revs[] = { { 0x1000, "A" }, }; +static const struct stm32l4_rev stm32u53_u54xx_revs[] = { + { 0x1000, "A" }, { 0x1001, "Z" }, +}; + static const struct stm32l4_rev stm32u57_u58xx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" }, + { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" }, { 0x3007, "U" }, +}; + +static const struct stm32l4_rev stm32u59_u5axx_revs[] = { + { 0x3001, "X" }, { 0x3002, "W" }, +}; + +static const struct stm32l4_rev stm32u5f_u5gxx_revs[] = { + { 0x1000, "A" }, { 0x1001, "Z" }, +}; + +static const struct stm32l4_rev stm32wba5x_revs[] = { + { 0x1000, "A" }, }; static const struct stm32l4_rev stm32wb1xx_revs[] = { @@ -370,6 +434,78 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_base = 0x1FFF7000, .otp_size = 1024, }, + { + .id = DEVID_STM32C01XX, + .revs = stm32c01xx_revs, + .num_revs = ARRAY_SIZE(stm32c01xx_revs), + .device_str = "STM32C01xx", + .max_flash_size_kb = 32, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, + { + .id = DEVID_STM32C03XX, + .revs = stm32c03xx_revs, + .num_revs = ARRAY_SIZE(stm32c03xx_revs), + .device_str = "STM32C03xx", + .max_flash_size_kb = 32, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, + { + .id = DEVID_STM32C05XX, + .revs = stm32c05xx_revs, + .num_revs = ARRAY_SIZE(stm32c05xx_revs), + .device_str = "STM32C05xx", + .max_flash_size_kb = 64, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, + { + .id = DEVID_STM32C071XX, + .revs = stm32c071xx_revs, + .num_revs = ARRAY_SIZE(stm32c071xx_revs), + .device_str = "STM32C071xx", + .max_flash_size_kb = 128, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, + { + .id = DEVID_STM32C09XX, + .revs = stm32c09xx_revs, + .num_revs = ARRAY_SIZE(stm32c09xx_revs), + .device_str = "STM32C09xx", + .max_flash_size_kb = 256, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, + { + .id = DEVID_STM32U53_U54XX, + .revs = stm32u53_u54xx_revs, + .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs), + .device_str = "STM32U535/U545", + .max_flash_size_kb = 512, + .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x0BFA07A0, + .otp_base = 0x0BFA0000, + .otp_size = 512, + }, { .id = DEVID_STM32G05_G06XX, .revs = stm32g05_g06xx_revs, @@ -420,8 +556,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = { }, { .id = DEVID_STM32L41_L42XX, - .revs = stm32l41_L42xx_revs, - .num_revs = ARRAY_SIZE(stm32l41_L42xx_revs), + .revs = stm32l41_l42xx_revs, + .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs), .device_str = "STM32L41/L42xx", .max_flash_size_kb = 128, .flags = F_NONE, @@ -526,6 +662,42 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_base = 0x1FFF7000, .otp_size = 1024, }, + { + .id = DEVID_STM32U031XX, + .revs = stm32u0xx_revs, + .num_revs = ARRAY_SIZE(stm32u0xx_revs), + .device_str = "STM32U031xx", + .max_flash_size_kb = 64, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF3EA0, + .otp_base = 0x1FFF6800, + .otp_size = 1024, + }, + { + .id = DEVID_STM32U073_U083XX, + .revs = stm32u0xx_revs, + .num_revs = ARRAY_SIZE(stm32u0xx_revs), + .device_str = "STM32U073/U083xx", + .max_flash_size_kb = 256, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF6EA0, + .otp_base = 0x1FFF6800, + .otp_size = 1024, + }, + { + .id = DEVID_STM32U59_U5AXX, + .revs = stm32u59_u5axx_revs, + .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs), + .device_str = "STM32U59/U5Axx", + .max_flash_size_kb = 4096, + .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x0BFA07A0, + .otp_base = 0x0BFA0000, + .otp_size = 512, + }, { .id = DEVID_STM32U57_U58XX, .revs = stm32u57_u58xx_revs, @@ -538,6 +710,30 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_base = 0x0BFA0000, .otp_size = 512, }, + { + .id = DEVID_STM32U5F_U5GXX, + .revs = stm32u5f_u5gxx_revs, + .num_revs = ARRAY_SIZE(stm32u5f_u5gxx_revs), + .device_str = "STM32U5F/U5Gxx", + .max_flash_size_kb = 4096, + .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x0BFA07A0, + .otp_base = 0x0BFA0000, + .otp_size = 512, + }, + { + .id = DEVID_STM32WBA5X, + .revs = stm32wba5x_revs, + .num_revs = ARRAY_SIZE(stm32wba5x_revs), + .device_str = "STM32WBA5x", + .max_flash_size_kb = 1024, + .flags = F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x0FF907A0, + .otp_base = 0x0FF90000, + .otp_size = 512, + }, { .id = DEVID_STM32WB1XX, .revs = stm32wb1xx_revs, @@ -619,7 +815,8 @@ struct range { }; static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, - struct range *ranges, unsigned int *ranges_count) { + struct range *ranges, unsigned int *ranges_count) +{ *ranges_count = 0; bool last_bit = 0, cur_bit; for (unsigned int i = 0; i < nbits; i++) { @@ -1641,7 +1838,7 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id) /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1. * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */ - if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO && + if (cortex_m_get_impl_part(target) == CORTEX_M0P_PARTNO && armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) { uint32_t uid64_ids; @@ -1740,7 +1937,8 @@ static int stm32l4_probe(struct flash_bank *bank) /* Set flash write alignment boundaries. * Ask the flash infrastructure to ensure required alignment */ - bank->write_start_alignment = bank->write_end_alignment = stm32l4_info->data_width; + bank->write_start_alignment = stm32l4_info->data_width; + bank->write_end_alignment = stm32l4_info->data_width; /* Initialize the flash registers layout */ if (part_info->flags & F_HAS_L5_FLASH_REGS) @@ -1816,7 +2014,7 @@ static int stm32l4_probe(struct flash_bank *bank) flash_size_kb = stm32l4_info->user_bank_size / 1024; } - LOG_INFO("flash size = %dkbytes", flash_size_kb); + LOG_INFO("flash size = %d KiB", flash_size_kb); /* did we assign a flash size? */ assert((flash_size_kb != 0xffff) && flash_size_kb); @@ -1853,8 +2051,15 @@ static int stm32l4_probe(struct flash_bank *bank) } break; case DEVID_STM32L43_L44XX: + case DEVID_STM32C01XX: + case DEVID_STM32C03XX: + case DEVID_STM32C05XX: + case DEVID_STM32C071XX: + case DEVID_STM32C09XX: case DEVID_STM32G05_G06XX: case DEVID_STM32G07_G08XX: + case DEVID_STM32U031XX: + case DEVID_STM32U073_U083XX: case DEVID_STM32L45_L46XX: case DEVID_STM32L41_L42XX: case DEVID_STM32G03_G04XX: @@ -1937,10 +2142,23 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; + case DEVID_STM32U53_U54XX: case DEVID_STM32U57_U58XX: - /* if flash size is max (2M) the device is always dual bank - * otherwise check DUALBANK + case DEVID_STM32U59_U5AXX: + case DEVID_STM32U5F_U5GXX: + /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13 + * U53x/U54x have 512K max flash size: + * 512K variants are always in DUAL BANK mode + * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set + * U57x/U58x have 2M max flash size: + * 2M variants are always in DUAL BANK mode + * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set + * U59x/U5Ax/U5Fx/U5Gx have 4M max flash size: + * 4M variants are always in DUAL BANK mode + * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set + * Note: flash banks are always contiguous */ + page_size_kb = 8; num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; @@ -1949,6 +2167,12 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; + case DEVID_STM32WBA5X: + /* single bank flash */ + page_size_kb = 8; + num_pages = flash_size_kb / page_size_kb; + stm32l4_info->bank1_sectors = num_pages; + break; case DEVID_STM32WB5XX: case DEVID_STM32WB3XX: /* single bank flash */ @@ -2149,10 +2373,8 @@ static int stm32l4_mass_erase(struct flash_bank *bank) COMMAND_HANDLER(stm32l4_handle_mass_erase_command) { - if (CMD_ARGC < 1) { - command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -2170,10 +2392,8 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command) COMMAND_HANDLER(stm32l4_handle_option_read_command) { - if (CMD_ARGC < 2) { - command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>"); + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -2197,10 +2417,8 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command) COMMAND_HANDLER(stm32l4_handle_option_write_command) { - if (CMD_ARGC < 3) { - command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]"); + if (CMD_ARGC != 3 && CMD_ARGC != 4) return ERROR_COMMAND_SYNTAX_ERROR; - } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -2312,7 +2530,7 @@ COMMAND_HANDLER(stm32l4_handle_lock_command) { struct target *target = NULL; - if (CMD_ARGC < 1) + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; struct flash_bank *bank; @@ -2347,7 +2565,7 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) { struct target *target = NULL; - if (CMD_ARGC < 1) + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; struct flash_bank *bank; @@ -2451,7 +2669,7 @@ COMMAND_HANDLER(stm32l4_handle_wrp_info_command) COMMAND_HANDLER(stm32l4_handle_otp_command) { - if (CMD_ARGC < 2) + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; struct flash_bank *bank; @@ -2509,7 +2727,7 @@ static const struct command_registration stm32l4_exec_command_handlers[] = { .name = "option_write", .handler = stm32l4_handle_option_write_command, .mode = COMMAND_EXEC, - .usage = "bank_id reg_offset value mask", + .usage = "bank_id reg_offset value [mask]", .help = "Write device option bit fields with provided value.", }, { diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h index 06cc66d4d8..07b3615a24 100644 --- a/src/flash/nor/stm32l4x.h +++ b/src/flash/nor/stm32l4x.h @@ -87,7 +87,13 @@ /* Supported device IDs */ #define DEVID_STM32L47_L48XX 0x415 #define DEVID_STM32L43_L44XX 0x435 +#define DEVID_STM32C01XX 0x443 +#define DEVID_STM32C05XX 0x44C +#define DEVID_STM32C09XX 0x44D +#define DEVID_STM32C03XX 0x453 +#define DEVID_STM32U53_U54XX 0x455 #define DEVID_STM32G05_G06XX 0x456 +#define DEVID_STM32U031XX 0x459 #define DEVID_STM32G07_G08XX 0x460 #define DEVID_STM32L49_L4AXX 0x461 #define DEVID_STM32L45_L46XX 0x462 @@ -99,8 +105,13 @@ #define DEVID_STM32L4R_L4SXX 0x470 #define DEVID_STM32L4P_L4QXX 0x471 #define DEVID_STM32L55_L56XX 0x472 +#define DEVID_STM32U5F_U5GXX 0x476 #define DEVID_STM32G49_G4AXX 0x479 +#define DEVID_STM32U59_U5AXX 0x481 #define DEVID_STM32U57_U58XX 0x482 +#define DEVID_STM32U073_U083XX 0x489 +#define DEVID_STM32WBA5X 0x492 +#define DEVID_STM32C071XX 0x493 #define DEVID_STM32WB1XX 0x494 #define DEVID_STM32WB5XX 0x495 #define DEVID_STM32WB3XX 0x496 diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c index d7a83efa6c..1459e942d1 100644 --- a/src/flash/nor/stm32lx.c +++ b/src/flash/nor/stm32lx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -132,7 +132,7 @@ static const struct stm32lx_rev stm32_417_revs[] = { { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" } }; static const struct stm32lx_rev stm32_425_revs[] = { - { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" }, + { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" }, { 0x2018, "1, X" }, }; static const struct stm32lx_rev stm32_427_revs[] = { { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" }, @@ -141,7 +141,7 @@ static const struct stm32lx_rev stm32_429_revs[] = { { 0x1000, "A" }, { 0x1018, "Z" }, }; static const struct stm32lx_rev stm32_436_revs[] = { - { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, + { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }, }; static const struct stm32lx_rev stm32_437_revs[] = { { 0x1000, "A" }, diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c index a5332482f8..df58f6c55d 100644 --- a/src/flash/nor/stmqspi.c +++ b/src/flash/nor/stmqspi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 - 2019 by Andreas Bolsch * @@ -616,8 +616,6 @@ COMMAND_HANDLER(stmqspi_handle_set) LOG_DEBUG("%s", __func__); - dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0; - /* chip_erase_cmd, sectorsize and erase_cmd are optional */ if ((CMD_ARGC < 7) || (CMD_ARGC > 10)) return ERROR_COMMAND_SYNTAX_ERROR; @@ -628,8 +626,9 @@ COMMAND_HANDLER(stmqspi_handle_set) target = bank->target; stmqspi_info = bank->driver_priv; + dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0; - /* invalidate all old info */ + /* invalidate all flash device info */ if (stmqspi_info->probed) free(bank->sectors); bank->size = 0; @@ -647,21 +646,21 @@ COMMAND_HANDLER(stmqspi_handle_set) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.size_in_bytes); if (log2u(stmqspi_info->dev.size_in_bytes) < 8) { command_print(CMD, "stmqspi: device size must be 2^n with n >= 8"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.pagesize); if (stmqspi_info->dev.pagesize > stmqspi_info->dev.size_in_bytes || (log2u(stmqspi_info->dev.pagesize) < 0)) { command_print(CMD, "stmqspi: page size must be 2^n and <= device size"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.read_cmd); if ((stmqspi_info->dev.read_cmd != 0x03) && (stmqspi_info->dev.read_cmd != 0x13)) { command_print(CMD, "stmqspi: only 0x03/0x13 READ cmd allowed"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.qread_cmd); @@ -679,7 +678,7 @@ COMMAND_HANDLER(stmqspi_handle_set) (stmqspi_info->dev.qread_cmd != 0xEE)) { command_print(CMD, "stmqspi: only 0x0B/0x0C/0x3B/0x3C/" "0x6B/0x6C/0xBB/0xBC/0xEB/0xEC/0xEE QREAD allowed"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.pprog_cmd); @@ -687,7 +686,7 @@ COMMAND_HANDLER(stmqspi_handle_set) (stmqspi_info->dev.pprog_cmd != 0x12) && (stmqspi_info->dev.pprog_cmd != 0x32)) { command_print(CMD, "stmqspi: only 0x02/0x12/0x32 PPRG cmd allowed"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } if (index < CMD_ARGC) @@ -701,7 +700,7 @@ COMMAND_HANDLER(stmqspi_handle_set) (stmqspi_info->dev.sectorsize < stmqspi_info->dev.pagesize) || (log2u(stmqspi_info->dev.sectorsize) < 0)) { command_print(CMD, "stmqspi: sector size must be 2^n and <= device size"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } if (index < CMD_ARGC) @@ -721,10 +720,8 @@ COMMAND_HANDLER(stmqspi_handle_set) uint32_t dcr; retval = target_read_u32(target, io_base + SPI_DCR, &dcr); - if (retval != ERROR_OK) return retval; - fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1); LOG_DEBUG("FSIZE = 0x%04x", fsize); @@ -754,13 +751,13 @@ COMMAND_HANDLER(stmqspi_handle_set) bank->sectors = sectors; stmqspi_info->dev.name = stmqspi_info->devname; if (stmqspi_info->dev.size_in_bytes / 4096) - LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "kbytes," - " bank size = %" PRIu32 "kbytes", stmqspi_info->dev.name, + LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " KiB," + " bank size = %" PRIu32 " KiB", stmqspi_info->dev.name, stmqspi_info->dev.size_in_bytes / 1024, (stmqspi_info->dev.size_in_bytes / 1024) << dual); else - LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "bytes," - " bank size = %" PRIu32 "bytes", stmqspi_info->dev.name, + LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " B," + " bank size = %" PRIu32 " B", stmqspi_info->dev.name, stmqspi_info->dev.size_in_bytes, stmqspi_info->dev.size_in_bytes << dual); @@ -789,7 +786,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd) num_write = CMD_ARGC - 2; if (num_write > max) { LOG_ERROR("at most %d bytes may be sent", max); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); @@ -814,7 +811,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd) if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) { if ((num_write & 1) == 0) { LOG_ERROR("number of data bytes to write must be even in dual mode"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } } } else { @@ -822,12 +819,12 @@ COMMAND_HANDLER(stmqspi_handle_cmd) if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) { if ((num_read & 1) != 0) { LOG_ERROR("number of bytes to read must be even in dual mode"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } } if ((num_write < 1) || (num_write > 5)) { LOG_ERROR("one cmd and up to four addr bytes must be send when reading"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } } @@ -1799,7 +1796,6 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len) } } - retval = ERROR_FAIL; LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count); err: @@ -1811,7 +1807,7 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len) /* Read SFDP parameter block */ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr, - uint32_t words, uint32_t *buffer) + unsigned int words, uint32_t *buffer) { struct target *target = bank->target; struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv; @@ -1852,7 +1848,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr, } } - LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08" PRIx32 " dummy=%u", + LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08x dummy=%u", __func__, addr, words, *dummy); /* Abort any previous operation */ @@ -2081,16 +2077,17 @@ static int stmqspi_probe(struct flash_bank *bank) bool octal_dtr; int retval; - if (stmqspi_info->probed) { - bank->size = 0; - bank->num_sectors = 0; + /* invalidate all flash device info */ + if (stmqspi_info->probed) free(bank->sectors); - bank->sectors = NULL; - memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev)); - stmqspi_info->sfdp_dummy1 = 0; - stmqspi_info->sfdp_dummy2 = 0; - stmqspi_info->probed = false; - } + bank->size = 0; + bank->num_sectors = 0; + bank->sectors = NULL; + stmqspi_info->sfdp_dummy1 = 0; + stmqspi_info->sfdp_dummy2 = 0; + stmqspi_info->probed = false; + memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev)); + stmqspi_info->dev.name = "unknown"; /* Abort any previous operation */ retval = stmqspi_abort(bank); @@ -2105,8 +2102,8 @@ static int stmqspi_probe(struct flash_bank *bank) /* check whether QSPI_ABR is writeable and readback returns the value written */ retval = target_write_u32(target, io_base + QSPI_ABR, magic); if (retval == ERROR_OK) { - retval = target_read_u32(target, io_base + QSPI_ABR, &data); - retval = target_write_u32(target, io_base + QSPI_ABR, 0); + (void)target_read_u32(target, io_base + QSPI_ABR, &data); + (void)target_write_u32(target, io_base + QSPI_ABR, 0); } if (data == magic) { @@ -2206,10 +2203,10 @@ static int stmqspi_probe(struct flash_bank *bank) memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev)); if (p->size_in_bytes / 4096) LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "kbytes", p->name, id1, p->size_in_bytes / 1024); + " KiB", p->name, id1, p->size_in_bytes / 1024); else LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "bytes", p->name, id1, p->size_in_bytes); + " B", p->name, id1, p->size_in_bytes); break; } } @@ -2228,7 +2225,7 @@ static int stmqspi_probe(struct flash_bank *bank) if (retval == ERROR_OK) { LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "kbytes", temp.name, id1, temp.size_in_bytes / 1024); + " KiB", temp.name, id1, temp.size_in_bytes / 1024); /* save info and retrieved *good* id as spi_sfdp clears all info */ memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev)); stmqspi_info->dev.device_id = id1; @@ -2246,10 +2243,10 @@ static int stmqspi_probe(struct flash_bank *bank) if (p->device_id == id2) { if (p->size_in_bytes / 4096) LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "kbytes", p->name, id2, p->size_in_bytes / 1024); + " KiB", p->name, id2, p->size_in_bytes / 1024); else LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "bytes", p->name, id2, p->size_in_bytes); + " B", p->name, id2, p->size_in_bytes); if (!id1) memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev)); @@ -2286,7 +2283,7 @@ static int stmqspi_probe(struct flash_bank *bank) if (retval == ERROR_OK) LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32 - "kbytes", temp.name, id2, temp.size_in_bytes / 1024); + " KiB", temp.name, id2, temp.size_in_bytes / 1024); else { /* even not identified by SFDP, then give up */ LOG_WARNING("Unknown flash2 device id = 0x%06" PRIx32 @@ -2392,22 +2389,22 @@ static int get_stmqspi_info(struct flash_bank *bank, struct command_invocation * } command_print_sameline(cmd, "flash%s%s \'%s\', device id = 0x%06" PRIx32 - ", flash size = %" PRIu32 "%sbytes\n(page size = %" PRIu32 + ", flash size = %" PRIu32 "%s B\n(page size = %" PRIu32 ", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8 ", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8 - ", sector size = %" PRIu32 "%sbytes, sector_erase = 0x%02" PRIx8 ")", + ", sector size = %" PRIu32 " %sB, sector_erase = 0x%02" PRIx8 ")", ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "", ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "", stmqspi_info->dev.name, stmqspi_info->dev.device_id, bank->size / 4096 ? bank->size / 1024 : bank->size, - bank->size / 4096 ? "k" : "", stmqspi_info->dev.pagesize, + bank->size / 4096 ? "Ki" : "", stmqspi_info->dev.pagesize, stmqspi_info->dev.read_cmd, stmqspi_info->dev.qread_cmd, stmqspi_info->dev.pprog_cmd, stmqspi_info->dev.chip_erase_cmd, stmqspi_info->dev.sectorsize / 4096 ? stmqspi_info->dev.sectorsize / 1024 : stmqspi_info->dev.sectorsize, - stmqspi_info->dev.sectorsize / 4096 ? "k" : "", + stmqspi_info->dev.sectorsize / 4096 ? "Ki" : "", stmqspi_info->dev.erase_cmd); return ERROR_OK; @@ -2450,7 +2447,7 @@ static const struct command_registration stmqspi_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct flash_driver stmqspi_flash = { +const struct flash_driver stmqspi_flash = { .name = "stmqspi", .commands = stmqspi_command_handlers, .flash_bank_command = stmqspi_flash_bank_command, diff --git a/src/flash/nor/stmsmi.c b/src/flash/nor/stmsmi.c index a4339def5b..1aa244728f 100644 --- a/src/flash/nor/stmsmi.c +++ b/src/flash/nor/stmsmi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> * diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c index 98e0bbde05..b91e22e044 100644 --- a/src/flash/nor/str7x.c +++ b/src/flash/nor/str7x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c index 86ec455a12..1a26b839e9 100644 --- a/src/flash/nor/str9x.c +++ b/src/flash/nor/str9x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c index 28cfe5d4f9..eff7df5a11 100644 --- a/src/flash/nor/str9xpec.c +++ b/src/flash/nor/str9xpec.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -68,7 +68,7 @@ static int str9xpec_erase_area(struct flash_bank *bank, unsigned int first, static int str9xpec_set_address(struct flash_bank *bank, uint8_t sector); static int str9xpec_write_options(struct flash_bank *bank); -static int str9xpec_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state) +static int str9xpec_set_instr(struct jtag_tap *tap, uint32_t new_instr, enum tap_state end_state) { if (!tap) return ERROR_TARGET_INVALID; diff --git a/src/flash/nor/swm050.c b/src/flash/nor/swm050.c index d0cb986a01..dcf59d380e 100644 --- a/src/flash/nor/swm050.c +++ b/src/flash/nor/swm050.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> * @@ -183,7 +183,7 @@ static const struct command_registration swm050_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct flash_driver swm050_flash = { +const struct flash_driver swm050_flash = { .name = "swm050", .commands = swm050_command_handlers, .flash_bank_command = swm050_flash_bank_command, diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index c184513643..0d41e49c8e 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath <Dominic.Rath@gmx.de> * @@ -19,7 +19,7 @@ * Implements Tcl commands used to access NOR flash facilities. */ -static COMMAND_HELPER(flash_command_get_bank_maybe_probe, unsigned name_index, +COMMAND_HELPER(flash_command_get_bank_probe_optional, unsigned int name_index, struct flash_bank **bank, bool do_probe) { const char *name = CMD_ARGV[name_index]; @@ -36,7 +36,7 @@ static COMMAND_HELPER(flash_command_get_bank_maybe_probe, unsigned name_index, if (*bank) return ERROR_OK; - unsigned bank_num; + unsigned int bank_num; COMMAND_PARSE_NUMBER(uint, name, bank_num); if (do_probe) { @@ -48,10 +48,10 @@ static COMMAND_HELPER(flash_command_get_bank_maybe_probe, unsigned name_index, } } -COMMAND_HELPER(flash_command_get_bank, unsigned name_index, +COMMAND_HELPER(flash_command_get_bank, unsigned int name_index, struct flash_bank **bank) { - return CALL_COMMAND_HANDLER(flash_command_get_bank_maybe_probe, + return CALL_COMMAND_HANDLER(flash_command_get_bank_probe_optional, name_index, bank, true); } @@ -157,7 +157,7 @@ COMMAND_HANDLER(handle_flash_probe_command) if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - retval = CALL_COMMAND_HANDLER(flash_command_get_bank_maybe_probe, 0, &p, false); + retval = CALL_COMMAND_HANDLER(flash_command_get_bank_probe_optional, 0, &p, false); if (retval != ERROR_OK) return retval; @@ -518,7 +518,7 @@ COMMAND_HANDLER(handle_flash_fill_command) uint64_t pattern; uint32_t count; struct target *target = get_current_target(CMD_CTX); - unsigned i; + unsigned int i; uint32_t wordsize; int retval; @@ -727,6 +727,124 @@ COMMAND_HANDLER(handle_flash_md_command) return retval; } +COMMAND_HANDLER(handle_flash_read_memory_command) +{ + /* + * CMD_ARGV[0] = memory address + * CMD_ARGV[1] = desired element width in bits + * CMD_ARGV[2] = number of elements to read + */ + + if (CMD_ARGC != 3) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* Arg 1: Memory address. */ + target_addr_t addr; + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], addr); + + /* Arg 2: Bit width of one element. */ + unsigned int width_bits; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], width_bits); + + /* Arg 3: Number of elements to read. */ + unsigned int count; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], count); + + switch (width_bits) { + case 8: + case 16: + case 32: + case 64: + break; + default: + command_print(CMD, "invalid width, must be 8, 16, 32 or 64"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + if (count > 65536) { + command_print(CMD, "too large read request, exceeds 64K elements"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + const unsigned int width = width_bits / 8; + /* -1 is needed to handle cases when (addr + count * width) results in zero + * due to overflow. + */ + if ((addr + count * width - 1) < addr) { + command_print(CMD, "memory region wraps over address zero"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + struct target *target = get_current_target(CMD_CTX); + struct flash_bank *bank; + int retval = get_flash_bank_by_addr(target, addr, true, &bank); + if (retval != ERROR_OK) + return retval; + + uint32_t offset = addr - bank->base; + uint32_t sizebytes = count * width_bits; + if (offset + sizebytes > bank->size) { + command_print(CMD, "cannot cross flash bank borders"); + return ERROR_FAIL; + } + + const size_t buffer_size = 4096; + uint8_t *buffer = malloc(buffer_size); + + if (!buffer) { + command_print(CMD, "failed to allocate memory"); + return ERROR_FAIL; + } + + char *separator = ""; + while (count > 0) { + const unsigned int max_chunk_len = buffer_size / width; + const size_t chunk_len = MIN(count, max_chunk_len); + + retval = flash_driver_read(bank, buffer, offset, chunk_len * width); + + if (retval != ERROR_OK) { + LOG_DEBUG("read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed", + addr, width_bits, chunk_len); + /* + * FIXME: we append the errmsg to the list of value already read. + * Add a way to flush and replace old output, but LOG_DEBUG() it + */ + command_print(CMD, "failed to read memory"); + free(buffer); + return retval; + } + + for (size_t i = 0; i < chunk_len ; i++) { + uint64_t v = 0; + + switch (width) { + case 8: + v = target_buffer_get_u64(target, &buffer[i * width]); + break; + case 4: + v = target_buffer_get_u32(target, &buffer[i * width]); + break; + case 2: + v = target_buffer_get_u16(target, &buffer[i * width]); + break; + case 1: + v = buffer[i]; + break; + } + + command_print_sameline(CMD, "%s0x%" PRIx64, separator, v); + separator = " "; + } + + count -= chunk_len; + offset += chunk_len * width; + } + + free(buffer); + + return ERROR_OK; +} COMMAND_HANDLER(handle_flash_write_bank_command) { @@ -814,6 +932,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command) if (buf_cnt != length) { LOG_ERROR("Short read"); free(buffer); + fileio_close(fileio); return ERROR_FAIL; } @@ -1169,6 +1288,13 @@ static const struct command_registration flash_exec_command_handlers[] = { .usage = "address [count]", .help = "Display words from flash.", }, + { + .name = "read_memory", + .mode = COMMAND_EXEC, + .handler = handle_flash_read_memory_command, + .help = "Read Tcl list of 8/16/32/64 bit numbers from flash memory", + .usage = "address width count", + }, { .name = "write_bank", .handler = handle_flash_write_bank_command, @@ -1297,6 +1423,7 @@ COMMAND_HANDLER(handle_flash_bank_command) if (retval != ERROR_OK) { LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT "; usage: %s", driver_name, c->base, driver->usage); + free(c->name); free(c); return retval; } @@ -1314,7 +1441,7 @@ COMMAND_HANDLER(handle_flash_banks_command) if (CMD_ARGC != 0) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned n = 0; + unsigned int n = 0; for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) { command_print(CMD, "#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", " "buswidth %u, chipwidth %u", p->bank_number, @@ -1324,40 +1451,27 @@ COMMAND_HANDLER(handle_flash_banks_command) return ERROR_OK; } -static int jim_flash_list(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_flash_list) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, - "no arguments to 'flash list' command"); - return JIM_ERR; - } - - Jim_Obj *list = Jim_NewListObj(interp, NULL, 0); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; for (struct flash_bank *p = flash_bank_list(); p; p = p->next) { - Jim_Obj *elem = Jim_NewListObj(interp, NULL, 0); - - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "name", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, p->name, -1)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "driver", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, p->driver->name, -1)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "base", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->base)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "size", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->size)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "bus_width", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->bus_width)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "chip_width", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->chip_width)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "target", -1)); - Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, target_name(p->target), -1)); - - Jim_ListAppendElement(interp, list, elem); + command_print(CMD, + "{\n" + " name %s\n" + " driver %s\n" + " base " TARGET_ADDR_FMT "\n" + " size 0x%" PRIx32 "\n" + " bus_width %u\n" + " chip_width %u\n" + " target %s\n" + "}", + p->name, p->driver->name, p->base, p->size, p->bus_width, p->chip_width, + target_name(p->target)); } - Jim_SetResult(interp, list); - - return JIM_OK; + return ERROR_OK; } COMMAND_HANDLER(handle_flash_init_command) @@ -1404,8 +1518,9 @@ static const struct command_registration flash_config_command_handlers[] = { { .name = "list", .mode = COMMAND_ANY, - .jim_handler = jim_flash_list, + .handler = handle_flash_list, .help = "Returns a list of details about the flash banks.", + .usage = "", }, COMMAND_REGISTRATION_DONE }; diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c index 7b24fff1cd..00ee77bb80 100644 --- a/src/flash/nor/tms470.c +++ b/src/flash/nor/tms470.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007,2008 by Christopher Kilgour * @@ -16,7 +16,7 @@ * ---------------------------------------------------------------------- */ struct tms470_flash_bank { - unsigned ordinal; + unsigned int ordinal; /* device identification register */ uint32_t device_ident_reg; @@ -239,8 +239,8 @@ static int tms470_read_part_info(struct flash_bank *bank) break; default: - LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", - (unsigned)part_number); + LOG_WARNING("Could not identify part 0x%02" PRIx32 " as a member of the TMS470 family.", + part_number); return ERROR_FLASH_OPERATION_FAILED; } @@ -248,9 +248,6 @@ static int tms470_read_part_info(struct flash_bank *bank) target_write_u32(target, 0xFFFFFFE4, 0x00000000); target_write_u32(target, 0xFFFFFFE0, 0x00000000); - bank->chip_width = 32; - bank->bus_width = 32; - LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.", part_name, (int)(silicon_version), @@ -394,7 +391,7 @@ static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set) /* only perform the key match when 3VSTAT is clear */ target_read_u32(target, 0xFFE8BC0C, &fmmstat); if (!(fmmstat & 0x08)) { - unsigned i; + unsigned int i; uint32_t fmbptr, fmbac2, orig_fmregopt; target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07); @@ -458,7 +455,7 @@ static int tms470_unlock_flash(struct flash_bank *bank) { struct target *target = bank->target; const uint32_t *p_key_sets[5]; - unsigned i, key_set_count; + unsigned int i, key_set_count; if (keys_set) { key_set_count = 5; diff --git a/src/flash/nor/virtual.c b/src/flash/nor/virtual.c index 212d53a4c6..c5e33385e6 100644 --- a/src/flash/nor/virtual.c +++ b/src/flash/nor/virtual.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Spencer Oliver * diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c index 52105bd6d9..20968dcaaa 100644 --- a/src/flash/nor/w600.c +++ b/src/flash/nor/w600.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Simon Qian * @@ -312,7 +312,7 @@ static int w600_probe(struct flash_bank *bank) flash_size = 1 << flash_size; } - LOG_INFO("flash size = %" PRIu32 "kbytes", flash_size / 1024); + LOG_INFO("flash size = %" PRIu32 " KiB", flash_size / 1024); /* calculate numbers of pages */ size_t num_pages = flash_size / W600_FLASH_SECSIZE; diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c index eb1e842237..4011fa42be 100644 --- a/src/flash/nor/xcf.c +++ b/src/flash/nor/xcf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Uladzimir Pylinski aka barthess * @@ -130,8 +130,8 @@ static struct xcf_status read_status(struct flash_bank *bank) jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); jtag_execute_queue(); - ret.isc_error = ((irdata[0] >> 7) & 3) == 0b01; - ret.prog_error = ((irdata[0] >> 5) & 3) == 0b01; + ret.isc_error = ((irdata[0] >> 7) & 3) == 1; + ret.prog_error = ((irdata[0] >> 5) & 3) == 1; ret.prog_busy = ((irdata[0] >> 4) & 1) == 0; ret.isc_mode = ((irdata[0] >> 3) & 1) == 1; @@ -143,28 +143,27 @@ static int isc_enter(struct flash_bank *bank) struct xcf_status status = read_status(bank); - if (true == status.isc_mode) + if (status.isc_mode) return ERROR_OK; - else { - struct scan_field scan; - scan.check_mask = NULL; - scan.check_value = NULL; - scan.num_bits = 16; - scan.out_value = cmd_isc_enable; - scan.in_value = NULL; + struct scan_field scan; - jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); - jtag_execute_queue(); + scan.check_mask = NULL; + scan.check_value = NULL; + scan.num_bits = 16; + scan.out_value = cmd_isc_enable; + scan.in_value = NULL; - status = read_status(bank); - if (!status.isc_mode) { - LOG_ERROR("*** XCF: FAILED to enter ISC mode"); - return ERROR_FLASH_OPERATION_FAILED; - } + jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); + jtag_execute_queue(); - return ERROR_OK; + status = read_status(bank); + if (!status.isc_mode) { + LOG_ERROR("*** XCF: FAILED to enter ISC mode"); + return ERROR_FLASH_OPERATION_FAILED; } + + return ERROR_OK; } static int isc_leave(struct flash_bank *bank) @@ -174,27 +173,26 @@ static int isc_leave(struct flash_bank *bank) if (!status.isc_mode) return ERROR_OK; - else { - struct scan_field scan; - - scan.check_mask = NULL; - scan.check_value = NULL; - scan.num_bits = 16; - scan.out_value = cmd_isc_disable; - scan.in_value = NULL; - - jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); - jtag_execute_queue(); - alive_sleep(1); /* device needs 50 uS to leave ISC mode */ - - status = read_status(bank); - if (status.isc_mode) { - LOG_ERROR("*** XCF: FAILED to leave ISC mode"); - return ERROR_FLASH_OPERATION_FAILED; - } - return ERROR_OK; + struct scan_field scan; + + scan.check_mask = NULL; + scan.check_value = NULL; + scan.num_bits = 16; + scan.out_value = cmd_isc_disable; + scan.in_value = NULL; + + jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); + jtag_execute_queue(); + alive_sleep(1); /* device needs 50 uS to leave ISC mode */ + + status = read_status(bank); + if (status.isc_mode) { + LOG_ERROR("*** XCF: FAILED to leave ISC mode"); + return ERROR_FLASH_OPERATION_FAILED; } + + return ERROR_OK; } static int sector_state(uint8_t wrpt, int sector) @@ -528,7 +526,7 @@ static int isc_program_single_revision_btc(struct flash_bank *bank) { uint8_t buf[4]; uint32_t btc = 0xFFFFFFFF; - btc &= ~0b1111; + btc &= ~0xF; btc |= ((bank->num_sectors - 1) << 2); btc &= ~(1 << 4); h_u32_to_le(buf, btc); @@ -597,7 +595,7 @@ static int xcf_probe(struct flash_bank *bank) } /* check idcode and alloc memory for sector table */ - if (!bank->target->tap->hasidcode) + if (!bank->target->tap->has_idcode) return ERROR_FLASH_OPERATION_FAILED; /* guess number of blocks using chip ID */ diff --git a/src/flash/nor/xmc1xxx.c b/src/flash/nor/xmc1xxx.c index 70e07fcfaa..4aa97a912f 100644 --- a/src/flash/nor/xmc1xxx.c +++ b/src/flash/nor/xmc1xxx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * XMC1000 flash driver @@ -84,7 +84,7 @@ static int xmc1xxx_erase(struct flash_bank *bank, unsigned int first, struct working_area *workarea; struct reg_param reg_params[3]; struct armv7m_algorithm armv7m_algo; - unsigned i; + unsigned int i; int retval; const uint8_t erase_code[] = { #include "../../../contrib/loaders/flash/xmc1xxx/erase.inc" @@ -159,7 +159,7 @@ static int xmc1xxx_erase_check(struct flash_bank *bank) struct reg_param reg_params[3]; struct armv7m_algorithm armv7m_algo; uint16_t val; - unsigned i; + unsigned int i; int retval; const uint8_t erase_check_code[] = { #include "../../../contrib/loaders/flash/xmc1xxx/erase_check.inc" @@ -245,7 +245,7 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer, struct reg_param reg_params[4]; struct armv7m_algorithm armv7m_algo; uint32_t block_count = DIV_ROUND_UP(byte_count, NVM_BLOCK_SIZE); - unsigned i; + unsigned int i; int retval; const uint8_t write_code[] = { #include "../../../contrib/loaders/flash/xmc1xxx/write.inc" @@ -520,24 +520,8 @@ FLASH_BANK_COMMAND_HANDLER(xmc1xxx_flash_bank_command) return ERROR_OK; } -static const struct command_registration xmc1xxx_exec_command_handlers[] = { - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration xmc1xxx_command_handlers[] = { - { - .name = "xmc1xxx", - .mode = COMMAND_ANY, - .help = "xmc1xxx flash command group", - .usage = "", - .chain = xmc1xxx_exec_command_handlers, - }, - COMMAND_REGISTRATION_DONE -}; - const struct flash_driver xmc1xxx_flash = { .name = "xmc1xxx", - .commands = xmc1xxx_command_handlers, .flash_bank_command = xmc1xxx_flash_bank_command, .info = xmc1xxx_get_info_command, .probe = xmc1xxx_probe, diff --git a/src/flash/nor/xmc4xxx.c b/src/flash/nor/xmc4xxx.c index 50ec45f666..54fd5a5867 100644 --- a/src/flash/nor/xmc4xxx.c +++ b/src/flash/nor/xmc4xxx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /************************************************************************** * Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com> * diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl index 654f201a4e..0dd84efacc 100644 --- a/src/flash/startup.tcl +++ b/src/flash/startup.tcl @@ -5,7 +5,7 @@ # # program utility proc # usage: program filename -# optional args: verify, reset, exit and address +# optional args: preverify, verify, reset, exit and address # lappend _telnet_autocomplete_skip program_error @@ -101,8 +101,8 @@ proc program {filename args} { return } -add_help_text program "write an image to flash, address is only required for binary images. verify, reset, exit are optional" -add_usage_text program "<filename> \[address\] \[pre-verify\] \[verify\] \[reset\] \[exit\]" +add_help_text program "write an image to flash, address is only required for binary images. preverify, verify, reset, exit are optional" +add_usage_text program "<filename> \[address\] \[preverify\] \[verify\] \[reset\] \[exit\]" # stm32[f0x|f3x] uses the same flash driver as the stm32f1x proc stm32f0x args { eval stm32f1x $args } diff --git a/src/hello.c b/src/hello.c index db6774eaa3..4e27d4d68d 100644 --- a/src/hello.c +++ b/src/hello.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> * @@ -8,6 +8,7 @@ #include <config.h> #endif #include <helper/log.h> +#include "hello.h" COMMAND_HANDLER(handle_foo_command) { diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am index 7354f5422b..8072124784 100644 --- a/src/helper/Makefile.am +++ b/src/helper/Makefile.am @@ -3,20 +3,25 @@ noinst_LTLIBRARIES += %D%/libhelper.la %C%_libhelper_la_SOURCES = \ + %D%/base64.c \ %D%/binarybuffer.c \ %D%/options.c \ %D%/time_support_common.c \ %D%/configuration.c \ %D%/log.c \ %D%/command.c \ + %D%/crc32.c \ %D%/time_support.c \ %D%/replacements.c \ %D%/fileio.c \ %D%/util.c \ %D%/jep106.c \ %D%/jim-nvp.c \ + %D%/nvp.c \ %D%/align.h \ + %D%/base64.h \ %D%/binarybuffer.h \ + %D%/bitfield.h \ %D%/bits.h \ %D%/configuration.h \ %D%/list.h \ @@ -24,13 +29,16 @@ noinst_LTLIBRARIES += %D%/libhelper.la %D%/types.h \ %D%/log.h \ %D%/command.h \ + %D%/crc32.h \ %D%/time_support.h \ %D%/replacements.h \ %D%/fileio.h \ %D%/system.h \ %D%/jep106.h \ %D%/jep106.inc \ - %D%/jim-nvp.h + %D%/jim-nvp.h \ + %D%/nvp.h \ + %D%/compiler.h STARTUP_TCL_SRCS += %D%/startup.tcl EXTRA_DIST += \ diff --git a/src/helper/align.h b/src/helper/align.h index 935a6a3b26..d7170065ed 100644 --- a/src/helper/align.h +++ b/src/helper/align.h @@ -24,7 +24,7 @@ #define IS_PWR_OF_2(x) \ ({ \ typeof(x) _x = (x); \ - _x == 0 || (_x & (_x - 1)) == 0; \ + _x != 0 && (_x & (_x - 1)) == 0; \ }) #endif /* OPENOCD_HELPER_ALIGN_H */ diff --git a/src/helper/base64.c b/src/helper/base64.c new file mode 100644 index 0000000000..5e0ee0846e --- /dev/null +++ b/src/helper/base64.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Base64 encoding/decoding (RFC1341) + * Copyright (c) 2005-2011, Jouni Malinen <j@w1.fi> + * + * Original file from FreeBSD code + * https://cgit.freebsd.org/src/tree/contrib/wpa/src/utils/base64.c?id=f05cddf940db + */ + + +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + +#include "base64.h" + +static const unsigned char base64_table[65] = + "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + +/** + * base64_encode - Base64 encode + * @src: Data to be encoded + * @len: Length of the data to be encoded + * @out_len: Pointer to output length variable, or %NULL if not used + * Returns: Allocated buffer of out_len bytes of encoded data, + * or %NULL on failure + * + * Caller is responsible for freeing the returned buffer. Returned buffer is + * nul terminated to make it easier to use as a C string. The nul terminator is + * not included in out_len. + */ +unsigned char *base64_encode(const unsigned char *src, size_t len, + size_t *out_len) +{ + unsigned char *out, *pos; + const unsigned char *end, *in; + size_t olen; + int line_len; + + olen = len * 4 / 3 + 4; /* 3-byte blocks to 4-byte */ + olen += olen / 72; /* line feeds */ + olen++; /* nul termination */ + if (olen < len) + return NULL; /* integer overflow */ + out = malloc(olen); + if (!out) + return NULL; + + end = src + len; + in = src; + pos = out; + line_len = 0; + while (end - in >= 3) { + *pos++ = base64_table[in[0] >> 2]; + *pos++ = base64_table[((in[0] & 0x03) << 4) | (in[1] >> 4)]; + *pos++ = base64_table[((in[1] & 0x0f) << 2) | (in[2] >> 6)]; + *pos++ = base64_table[in[2] & 0x3f]; + in += 3; + line_len += 4; + if (line_len >= 72) { + *pos++ = '\n'; + line_len = 0; + } + } + + if (end - in) { + *pos++ = base64_table[in[0] >> 2]; + if (end - in == 1) { + *pos++ = base64_table[(in[0] & 0x03) << 4]; + *pos++ = '='; + } else { + *pos++ = base64_table[((in[0] & 0x03) << 4) | + (in[1] >> 4)]; + *pos++ = base64_table[(in[1] & 0x0f) << 2]; + } + *pos++ = '='; + line_len += 4; + } + + if (line_len) + *pos++ = '\n'; + + *pos = '\0'; + if (out_len) + *out_len = pos - out; + return out; +} + + +/** + * base64_decode - Base64 decode + * @src: Data to be decoded + * @len: Length of the data to be decoded + * @out_len: Pointer to output length variable + * Returns: Allocated buffer of out_len bytes of decoded data, + * or %NULL on failure + * + * Caller is responsible for freeing the returned buffer. + */ +unsigned char *base64_decode(const unsigned char *src, size_t len, + size_t *out_len) +{ + unsigned char dtable[256], *out, *pos, block[4], tmp; + size_t i, count, olen; + int pad = 0; + + memset(dtable, 0x80, 256); + for (i = 0; i < sizeof(base64_table) - 1; i++) + dtable[base64_table[i]] = (unsigned char)i; + dtable['='] = 0; + + count = 0; + for (i = 0; i < len; i++) { + if (dtable[src[i]] != 0x80) + count++; + } + + if (count == 0 || count % 4) + return NULL; + + olen = count / 4 * 3; + out = malloc(olen); + if (!out) + return NULL; + pos = out; + + count = 0; + for (i = 0; i < len; i++) { + tmp = dtable[src[i]]; + if (tmp == 0x80) + continue; + + if (src[i] == '=') + pad++; + block[count] = tmp; + count++; + if (count == 4) { + *pos++ = (block[0] << 2) | (block[1] >> 4); + *pos++ = (block[1] << 4) | (block[2] >> 2); + *pos++ = (block[2] << 6) | block[3]; + count = 0; + if (pad) { + if (pad == 1) { + pos--; + } else if (pad == 2) { + pos -= 2; + } else { + /* Invalid padding */ + free(out); + return NULL; + } + break; + } + } + } + + *out_len = pos - out; + return out; +} diff --git a/src/helper/base64.h b/src/helper/base64.h new file mode 100644 index 0000000000..d3e0462131 --- /dev/null +++ b/src/helper/base64.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* + * Base64 encoding/decoding (RFC1341) + * Copyright (c) 2005, Jouni Malinen <j@w1.fi> + * + * Original file from FreeBSD code + * https://cgit.freebsd.org/src/tree/contrib/wpa/src/utils/base64.h?id=f05cddf940db + */ + +#ifndef BASE64_H +#define BASE64_H + +unsigned char *base64_encode(const unsigned char *src, size_t len, + size_t *out_len); +unsigned char *base64_decode(const unsigned char *src, size_t len, + size_t *out_len); + +#endif /* BASE64_H */ diff --git a/src/helper/bin2char.sh b/src/helper/bin2char.sh index b89433d869..cf94bee29c 100755 --- a/src/helper/bin2char.sh +++ b/src/helper/bin2char.sh @@ -12,4 +12,4 @@ } echo "/* Autogenerated with $0 */" -od -v -A n -t x1 | sed 's/ *\(..\) */0x\1,/g' +od -v -A n -t x1 | sed 's/ *\(..\) */0x\1,/g;/^$/d' diff --git a/src/helper/binarybuffer.c b/src/helper/binarybuffer.c index 250ca43577..6fba86a660 100644 --- a/src/helper/binarybuffer.c +++ b/src/helper/binarybuffer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2004, 2005 by Dominic Rath * @@ -40,7 +40,7 @@ static const char hex_digits[] = { 'a', 'b', 'c', 'd', 'e', 'f' }; -void *buf_cpy(const void *from, void *_to, unsigned size) +void *buf_cpy(const void *from, void *_to, unsigned int size) { if (!from || !_to) return NULL; @@ -49,7 +49,7 @@ void *buf_cpy(const void *from, void *_to, unsigned size) memcpy(_to, from, DIV_ROUND_UP(size, 8)); /* mask out bits that don't belong to the buffer */ - unsigned trailing_bits = size % 8; + unsigned int trailing_bits = size % 8; if (trailing_bits) { uint8_t *to = _to; to[size / 8] &= (1 << trailing_bits) - 1; @@ -57,53 +57,52 @@ void *buf_cpy(const void *from, void *_to, unsigned size) return _to; } -static bool buf_cmp_masked(uint8_t a, uint8_t b, uint8_t m) +static bool buf_eq_masked(uint8_t a, uint8_t b, uint8_t m) { - return (a & m) != (b & m); + return (a & m) == (b & m); } -static bool buf_cmp_trailing(uint8_t a, uint8_t b, uint8_t m, unsigned trailing) +static bool buf_eq_trailing(uint8_t a, uint8_t b, uint8_t m, unsigned int trailing) { uint8_t mask = (1 << trailing) - 1; - return buf_cmp_masked(a, b, mask & m); + return buf_eq_masked(a, b, mask & m); } -bool buf_cmp(const void *_buf1, const void *_buf2, unsigned size) +bool buf_eq(const void *_buf1, const void *_buf2, unsigned int size) { if (!_buf1 || !_buf2) - return _buf1 != _buf2; + return _buf1 == _buf2; - unsigned last = size / 8; + unsigned int last = size / 8; if (memcmp(_buf1, _buf2, last) != 0) return false; - unsigned trailing = size % 8; + unsigned int trailing = size % 8; if (!trailing) - return false; + return true; const uint8_t *buf1 = _buf1, *buf2 = _buf2; - return buf_cmp_trailing(buf1[last], buf2[last], 0xff, trailing); + return buf_eq_trailing(buf1[last], buf2[last], 0xff, trailing); } -bool buf_cmp_mask(const void *_buf1, const void *_buf2, - const void *_mask, unsigned size) +bool buf_eq_mask(const void *_buf1, const void *_buf2, + const void *_mask, unsigned int size) { if (!_buf1 || !_buf2) - return _buf1 != _buf2 || _buf1 != _mask; + return _buf1 == _buf2 && _buf1 == _mask; const uint8_t *buf1 = _buf1, *buf2 = _buf2, *mask = _mask; - unsigned last = size / 8; - for (unsigned i = 0; i < last; i++) { - if (buf_cmp_masked(buf1[i], buf2[i], mask[i])) - return true; + unsigned int last = size / 8; + for (unsigned int i = 0; i < last; i++) { + if (!buf_eq_masked(buf1[i], buf2[i], mask[i])) + return false; } - unsigned trailing = size % 8; + unsigned int trailing = size % 8; if (!trailing) - return false; - return buf_cmp_trailing(buf1[last], buf2[last], mask[last], trailing); + return true; + return buf_eq_trailing(buf1[last], buf2[last], mask[last], trailing); } - -void *buf_set_ones(void *_buf, unsigned size) +void *buf_set_ones(void *_buf, unsigned int size) { uint8_t *buf = _buf; if (!buf) @@ -111,19 +110,19 @@ void *buf_set_ones(void *_buf, unsigned size) memset(buf, 0xff, size / 8); - unsigned trailing_bits = size % 8; + unsigned int trailing_bits = size % 8; if (trailing_bits) buf[size / 8] = (1 << trailing_bits) - 1; return buf; } -void *buf_set_buf(const void *_src, unsigned src_start, - void *_dst, unsigned dst_start, unsigned len) +void *buf_set_buf(const void *_src, unsigned int src_start, + void *_dst, unsigned int dst_start, unsigned int len) { const uint8_t *src = _src; uint8_t *dst = _dst; - unsigned i, sb, db, sq, dq, lb, lq; + unsigned int i, sb, db, sq, dq, lb, lq; sb = src_start / 8; db = dst_start / 8; @@ -176,26 +175,13 @@ uint32_t flip_u32(uint32_t value, unsigned int num) return c; } -static int ceil_f_to_u32(float x) +char *buf_to_hex_str(const void *_buf, unsigned int buf_len) { - if (x < 0) /* return zero for negative numbers */ - return 0; - - uint32_t y = x; /* cut off fraction */ - - if ((x - y) > 0.0) /* if there was a fractional part, increase by one */ - y++; - - return y; -} - -char *buf_to_hex_str(const void *_buf, unsigned buf_len) -{ - unsigned len_bytes = DIV_ROUND_UP(buf_len, 8); + unsigned int len_bytes = DIV_ROUND_UP(buf_len, 8); char *str = calloc(len_bytes * 2 + 1, 1); const uint8_t *buf = _buf; - for (unsigned i = 0; i < len_bytes; i++) { + for (unsigned int i = 0; i < len_bytes; i++) { uint8_t tmp = buf[len_bytes - i - 1]; if ((i == 0) && (buf_len % 8)) tmp &= (0xff >> (8 - (buf_len % 8))); @@ -206,94 +192,96 @@ char *buf_to_hex_str(const void *_buf, unsigned buf_len) return str; } -/** identify radix, and skip radix-prefix (0, 0x or 0X) */ -static void str_radix_guess(const char **_str, unsigned *_str_len, - unsigned *_radix) +/* + * TCL standard prefix is '0b', '0o', '0d' or '0x' respectively for binary, + * octal, decimal or hexadecimal. + * The prefix '0' is interpreted by TCL <= 8.6 as octal, but is ignored and + * interpreted as part of a decimal number by JimTCL and by TCL >= 9. + */ +int str_to_buf(const char *str, void *_buf, unsigned int buf_bitsize) { - unsigned radix = *_radix; - if (radix != 0) - return; - const char *str = *_str; - unsigned str_len = *_str_len; - if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) { - radix = 16; - str += 2; - str_len -= 2; - } else if ((str[0] == '0') && (str_len != 1)) { - radix = 8; - str += 1; - str_len -= 1; - } else - radix = 10; - *_str = str; - *_str_len = str_len; - *_radix = radix; -} + assert(str); + assert(_buf); + assert(buf_bitsize > 0); -int str_to_buf(const char *str, unsigned str_len, - void *_buf, unsigned buf_len, unsigned radix) -{ - str_radix_guess(&str, &str_len, &radix); - - float factor; - if (radix == 16) - factor = 0.5; /* log(16) / log(256) = 0.5 */ - else if (radix == 10) - factor = 0.41524; /* log(10) / log(256) = 0.41524 */ - else if (radix == 8) - factor = 0.375; /* log(8) / log(256) = 0.375 */ - else - return 0; + uint8_t *buf = _buf; + unsigned int radix = 10; /* default when no prefix */ + + if (str[0] == '0') { + switch (str[1]) { + case 'b': + case 'B': + radix = 2; + str += 2; + break; + case 'o': + case 'O': + radix = 8; + str += 2; + break; + case 'd': + case 'D': + radix = 10; + str += 2; + break; + case 'x': + case 'X': + radix = 16; + str += 2; + break; + default: + break; + } + } - /* copy to zero-terminated buffer */ - char *charbuf = strndup(str, str_len); - - /* number of digits in base-256 notation */ - unsigned b256_len = ceil_f_to_u32(str_len * factor); - uint8_t *b256_buf = calloc(b256_len, 1); - - /* go through zero terminated buffer - * input digits (ASCII) */ - unsigned i; - for (i = 0; charbuf[i]; i++) { - uint32_t tmp = charbuf[i]; - if ((tmp >= '0') && (tmp <= '9')) - tmp = (tmp - '0'); - else if ((tmp >= 'a') && (tmp <= 'f')) - tmp = (tmp - 'a' + 10); - else if ((tmp >= 'A') && (tmp <= 'F')) - tmp = (tmp - 'A' + 10); - else - continue; /* skip characters other than [0-9,a-f,A-F] */ + const size_t str_len = strlen(str); + if (str_len == 0) + return ERROR_INVALID_NUMBER; + + const size_t buf_len = DIV_ROUND_UP(buf_bitsize, 8); + memset(buf, 0, buf_len); + + /* Go through the zero-terminated buffer + * of input digits (ASCII) */ + for (; *str; str++) { + unsigned int tmp; + const char c = *str; + + if ((c >= '0') && (c <= '9')) { + tmp = c - '0'; + } else if ((c >= 'a') && (c <= 'f')) { + tmp = c - 'a' + 10; + } else if ((c >= 'A') && (c <= 'F')) { + tmp = c - 'A' + 10; + } else { + /* Characters other than [0-9,a-f,A-F] are invalid */ + return ERROR_INVALID_NUMBER; + } + /* Error on invalid digit for current radix */ if (tmp >= radix) - continue; /* skip digits invalid for the current radix */ + return ERROR_INVALID_NUMBER; - /* base-256 digits */ - for (unsigned j = 0; j < b256_len; j++) { - tmp += (uint32_t)b256_buf[j] * radix; - b256_buf[j] = (uint8_t)(tmp & 0xFF); + /* Add the current digit (tmp) to the intermediate result in buf */ + for (unsigned int j = 0; j < buf_len; j++) { + tmp += buf[j] * radix; + buf[j] = tmp & 0xFFu; tmp >>= 8; } + /* buf should be large enough to contain the whole result. */ + if (tmp != 0) + return ERROR_NUMBER_EXCEEDS_BUFFER; } - uint8_t *buf = _buf; - for (unsigned j = 0; j < DIV_ROUND_UP(buf_len, 8); j++) { - if (j < b256_len) - buf[j] = b256_buf[j]; - else - buf[j] = 0; + /* Check the partial most significant byte */ + if (buf_bitsize % 8) { + const uint8_t mask = 0xFFu << (buf_bitsize % 8); + if ((buf[buf_len - 1] & mask) != 0x0) + return ERROR_NUMBER_EXCEEDS_BUFFER; } - /* mask out bits that don't belong to the buffer */ - if (buf_len % 8) - buf[(buf_len / 8)] &= 0xff >> (8 - (buf_len % 8)); - - free(b256_buf); - free(charbuf); - - return i; + return ERROR_OK; } void bit_copy_queue_init(struct bit_copy_queue *q) @@ -301,8 +289,8 @@ void bit_copy_queue_init(struct bit_copy_queue *q) INIT_LIST_HEAD(&q->list); } -int bit_copy_queued(struct bit_copy_queue *q, uint8_t *dst, unsigned dst_offset, const uint8_t *src, - unsigned src_offset, unsigned bit_count) +int bit_copy_queued(struct bit_copy_queue *q, uint8_t *dst, unsigned int dst_offset, const uint8_t *src, + unsigned int src_offset, unsigned int bit_count) { struct bit_copy_queue_entry *qe = malloc(sizeof(*qe)); if (!qe) @@ -407,12 +395,12 @@ size_t hexify(char *hex, const uint8_t *bin, size_t count, size_t length) return i; } -void buffer_shr(void *_buf, unsigned buf_len, unsigned count) +void buffer_shr(void *_buf, unsigned int buf_len, unsigned int count) { - unsigned i; + unsigned int i; unsigned char *buf = _buf; - unsigned bytes_to_remove; - unsigned shift; + unsigned int bytes_to_remove; + unsigned int shift; bytes_to_remove = count / 8; shift = count - (bytes_to_remove * 8); diff --git a/src/helper/binarybuffer.h b/src/helper/binarybuffer.h index a8a5ef8f3f..99132798b6 100644 --- a/src/helper/binarybuffer.h +++ b/src/helper/binarybuffer.h @@ -11,7 +11,11 @@ #ifndef OPENOCD_HELPER_BINARYBUFFER_H #define OPENOCD_HELPER_BINARYBUFFER_H -#include "list.h" +#include <helper/list.h> +#include <helper/types.h> + +#define ERROR_INVALID_NUMBER (-1700) +#define ERROR_NUMBER_EXCEEDS_BUFFER (-1701) /** @file * Support functions to access arbitrary bits in a byte array @@ -28,8 +32,9 @@ * @param value Up to 32 bits that will be copied to _buffer. */ static inline void buf_set_u32(uint8_t *_buffer, - unsigned first, unsigned num, uint32_t value) + unsigned int first, unsigned int num, uint32_t value) { + assert(num >= 1 && num <= 32); uint8_t *buffer = _buffer; if ((num == 32) && (first == 0)) { @@ -38,7 +43,7 @@ static inline void buf_set_u32(uint8_t *_buffer, buffer[1] = (value >> 8) & 0xff; buffer[0] = (value >> 0) & 0xff; } else { - for (unsigned i = first; i < first + num; i++) { + for (unsigned int i = first; i < first + num; i++) { if (((value >> (i - first)) & 1) == 1) buffer[i / 8] |= 1 << (i % 8); else @@ -58,8 +63,9 @@ static inline void buf_set_u32(uint8_t *_buffer, * @param value Up to 64 bits that will be copied to _buffer. */ static inline void buf_set_u64(uint8_t *_buffer, - unsigned first, unsigned num, uint64_t value) + unsigned int first, unsigned int num, uint64_t value) { + assert(num >= 1 && num <= 64); uint8_t *buffer = _buffer; if ((num == 32) && (first == 0)) { @@ -77,7 +83,7 @@ static inline void buf_set_u64(uint8_t *_buffer, buffer[1] = (value >> 8) & 0xff; buffer[0] = (value >> 0) & 0xff; } else { - for (unsigned i = first; i < first + num; i++) { + for (unsigned int i = first; i < first + num; i++) { if (((value >> (i - first)) & 1) == 1) buffer[i / 8] |= 1 << (i % 8); else @@ -96,8 +102,9 @@ static inline void buf_set_u64(uint8_t *_buffer, * @returns Up to 32-bits that were read from @c _buffer. */ static inline uint32_t buf_get_u32(const uint8_t *_buffer, - unsigned first, unsigned num) + unsigned int first, unsigned int num) { + assert(num >= 1 && num <= 32); const uint8_t *buffer = _buffer; if ((num == 32) && (first == 0)) { @@ -107,7 +114,7 @@ static inline uint32_t buf_get_u32(const uint8_t *_buffer, (((uint32_t)buffer[0]) << 0); } else { uint32_t result = 0; - for (unsigned i = first; i < first + num; i++) { + for (unsigned int i = first; i < first + num; i++) { if (((buffer[i / 8] >> (i % 8)) & 1) == 1) result |= 1U << (i - first); } @@ -125,8 +132,9 @@ static inline uint32_t buf_get_u32(const uint8_t *_buffer, * @returns Up to 64-bits that were read from @c _buffer. */ static inline uint64_t buf_get_u64(const uint8_t *_buffer, - unsigned first, unsigned num) + unsigned int first, unsigned int num) { + assert(num >= 1 && num <= 64); const uint8_t *buffer = _buffer; if ((num == 32) && (first == 0)) { @@ -145,7 +153,7 @@ static inline uint64_t buf_get_u64(const uint8_t *_buffer, (((uint64_t)buffer[0]) << 0)); } else { uint64_t result = 0; - for (unsigned i = first; i < first + num; i++) { + for (unsigned int i = first; i < first + num; i++) { if (((buffer[i / 8] >> (i % 8)) & 1) == 1) result = result | ((uint64_t)1 << (uint64_t)(i - first)); } @@ -162,11 +170,11 @@ static inline uint64_t buf_get_u64(const uint8_t *_buffer, * @param width The number of bits in value (2-32). * @returns A 32-bit word with @c value in reversed bit-order. */ -uint32_t flip_u32(uint32_t value, unsigned width); +uint32_t flip_u32(uint32_t value, unsigned int width); -bool buf_cmp(const void *buf1, const void *buf2, unsigned size); -bool buf_cmp_mask(const void *buf1, const void *buf2, - const void *mask, unsigned size); +bool buf_eq(const void *buf1, const void *buf2, unsigned int size); +bool buf_eq_mask(const void *buf1, const void *buf2, + const void *mask, unsigned int size); /** * Copies @c size bits out of @c from and into @c to. Any extra @@ -175,7 +183,7 @@ bool buf_cmp_mask(const void *buf1, const void *buf2, * @param to The buffer that will receive the copy of @c from. * @param size The number of bits to copy. */ -void *buf_cpy(const void *from, void *to, unsigned size); +void *buf_cpy(const void *from, void *to, unsigned int size); /** * Set the contents of @c buf with @c count bits, all set to 1. @@ -183,14 +191,23 @@ void *buf_cpy(const void *from, void *to, unsigned size); * @param size The number of bits. * @returns The original buffer (@c buf). */ -void *buf_set_ones(void *buf, unsigned size); +void *buf_set_ones(void *buf, unsigned int size); + +void *buf_set_buf(const void *src, unsigned int src_start, + void *dst, unsigned int dst_start, unsigned int len); -void *buf_set_buf(const void *src, unsigned src_start, - void *dst, unsigned dst_start, unsigned len); +/** + * Parse an unsigned number (provided as a zero-terminated string) + * into a bit buffer whose size is buf_len bits. The base of the + * number is detected between decimal, hexadecimal and octal. + * @param str Input number, zero-terminated string + * @param _buf Output buffer, allocated by the caller + * @param buf_bitsize Output buffer size in bits + * @returns Error on invalid or overflowing number + */ +int str_to_buf(const char *str, void *_buf, unsigned int buf_bitsize); -int str_to_buf(const char *str, unsigned len, - void *bin_buf, unsigned buf_size, unsigned radix); -char *buf_to_hex_str(const void *buf, unsigned size); +char *buf_to_hex_str(const void *buf, unsigned int size); /* read a uint32_t from a buffer in target memory endianness */ static inline uint32_t fast_target_buffer_get_u32(const void *p, bool le) @@ -198,8 +215,8 @@ static inline uint32_t fast_target_buffer_get_u32(const void *p, bool le) return le ? le_to_h_u32(p) : be_to_h_u32(p); } -static inline void bit_copy(uint8_t *dst, unsigned dst_offset, const uint8_t *src, - unsigned src_offset, unsigned bit_count) +static inline void bit_copy(uint8_t *dst, unsigned int dst_offset, const uint8_t *src, + unsigned int src_offset, unsigned int bit_count) { buf_set_buf(src, src_offset, dst, dst_offset, bit_count); } @@ -210,16 +227,16 @@ struct bit_copy_queue { struct bit_copy_queue_entry { uint8_t *dst; - unsigned dst_offset; + unsigned int dst_offset; const uint8_t *src; - unsigned src_offset; - unsigned bit_count; + unsigned int src_offset; + unsigned int bit_count; struct list_head list; }; void bit_copy_queue_init(struct bit_copy_queue *q); -int bit_copy_queued(struct bit_copy_queue *q, uint8_t *dst, unsigned dst_offset, const uint8_t *src, - unsigned src_offset, unsigned bit_count); +int bit_copy_queued(struct bit_copy_queue *q, uint8_t *dst, unsigned int dst_offset, const uint8_t *src, + unsigned int src_offset, unsigned int bit_count); void bit_copy_execute(struct bit_copy_queue *q); void bit_copy_discard(struct bit_copy_queue *q); @@ -227,6 +244,6 @@ void bit_copy_discard(struct bit_copy_queue *q); * used in ti-icdi driver and gdb server */ size_t unhexify(uint8_t *bin, const char *hex, size_t count); size_t hexify(char *hex, const uint8_t *bin, size_t count, size_t out_maxlen); -void buffer_shr(void *_buf, unsigned buf_len, unsigned count); +void buffer_shr(void *_buf, unsigned int buf_len, unsigned int count); #endif /* OPENOCD_HELPER_BINARYBUFFER_H */ diff --git a/src/helper/bitfield.h b/src/helper/bitfield.h new file mode 100644 index 0000000000..9f397282cf --- /dev/null +++ b/src/helper/bitfield.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* +* Copyright (c) 2020-2024 The FreeBSD Foundation +* +* This software was developed by Björn Zeeb under sponsorship from +* the FreeBSD Foundation. +*/ + +#ifndef OPENOCD_HELPER_BITFIELD_H +#define OPENOCD_HELPER_BITFIELD_H + +/** + * These macros come from FreeBSD, check source on + * https://cgit.freebsd.org/src/tree/sys/compat/linuxkpi/common/include/linux/bitfield.h + * Which does not include example usages of them. + */ + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +/** + * FIELD_FIT(_mask, _value) - Check if a value fits in the specified bitfield mask + * @_mask: Bitfield mask + * @_value: Value to check + * + * This macro checks whether a given value fits within the range defined by the + * specified bitfield mask. It ensures that no bits outside the mask are set. + * + * Return: true if the value fits, false otherwise. + */ +#define FIELD_FIT(_mask, _value) \ + (!(((typeof(_mask))(_value) << __bf_shf(_mask)) & ~(_mask))) + +/** + * FIELD_PREP(_mask, _value) - Prepare a value for insertion into a bitfield + * @_mask: Bitfield mask + * @_value: Value to insert + * + * This macro prepares a value for insertion into a bitfield by shifting the + * value into the position defined by the mask and applying the mask. + * + * Return: The prepared bitfield value. + */ +#define FIELD_PREP(_mask, _value) \ + (((typeof(_mask))(_value) << __bf_shf(_mask)) & (_mask)) + +/** + * FIELD_GET(_mask, _value) - Extract a value from a bitfield + * @_mask: Bitfield mask + * @_value: Bitfield value to extract from + * + * This macro extracts a value from a bitfield by masking and shifting the + * relevant bits down to the least significant position. + * + * Return: The extracted value. + */ +#define FIELD_GET(_mask, _value) \ + ((typeof(_mask))(((_value) & (_mask)) >> __bf_shf(_mask))) + +#endif /* OPENOCD_HELPER_BITFIELD_H */ diff --git a/src/helper/command.c b/src/helper/command.c index 43fe033f71..b70081a4dd 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -18,9 +18,6 @@ #include "config.h" #endif -/* see Embedded-HOWTO.txt in Jim Tcl project hosted on BerliOS*/ -#define JIM_EMBEDDED - /* @todo the inclusion of target.h here is a layering violation */ #include <jtag/jtag.h> #include <target/target.h> @@ -34,8 +31,7 @@ #define __THIS__FILE__ "command.c" struct log_capture_state { - Jim_Interp *interp; - Jim_Obj *output; + char *output; }; static int unregister_command(struct command_context *context, @@ -44,6 +40,7 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a static int help_add_command(struct command_context *cmd_ctx, const char *cmd_name, const char *help_text, const char *usage_text); static int help_del_command(struct command_context *cmd_ctx, const char *cmd_name); +static enum command_mode get_command_mode(Jim_Interp *interp, const char *cmd_name); /* set of functions to wrap jimtcl internal data */ static inline bool jimcmd_is_proc(Jim_Cmd *cmd) @@ -61,71 +58,6 @@ void *jimcmd_privdata(Jim_Cmd *cmd) return cmd->isproc ? NULL : cmd->u.native.privData; } -static void tcl_output(void *privData, const char *file, unsigned line, - const char *function, const char *string) -{ - struct log_capture_state *state = privData; - Jim_AppendString(state->interp, state->output, string, strlen(string)); -} - -static struct log_capture_state *command_log_capture_start(Jim_Interp *interp) -{ - /* capture log output and return it. A garbage collect can - * happen, so we need a reference count to this object */ - Jim_Obj *jim_output = Jim_NewStringObj(interp, "", 0); - if (!jim_output) - return NULL; - - Jim_IncrRefCount(jim_output); - - struct log_capture_state *state = malloc(sizeof(*state)); - if (!state) { - LOG_ERROR("Out of memory"); - Jim_DecrRefCount(interp, jim_output); - return NULL; - } - - state->interp = interp; - state->output = jim_output; - - log_add_callback(tcl_output, state); - - return state; -} - -/* Classic openocd commands provide progress output which we - * will capture and return as a Tcl return value. - * - * However, if a non-openocd command has been invoked, then it - * makes sense to return the tcl return value from that command. - * - * The tcl return value is empty for openocd commands that provide - * progress output. - * - * Therefore we set the tcl return value only if we actually - * captured output. - */ -static void command_log_capture_finish(struct log_capture_state *state) -{ - if (!state) - return; - - log_remove_callback(tcl_output, state); - - int length; - Jim_GetString(state->output, &length); - - if (length > 0) - Jim_SetResult(state->interp, state->output); - else { - /* No output captured, use tcl return value (which could - * be empty too). */ - } - Jim_DecrRefCount(state->interp, state->output); - - free(state); -} - static int command_retval_set(Jim_Interp *interp, int retval) { int *return_retval = Jim_GetAssocData(interp, "retval"); @@ -145,9 +77,8 @@ static void script_debug(Jim_Interp *interp, unsigned int argc, Jim_Obj * const return; char *dbg = alloc_printf("command -"); - for (unsigned i = 0; i < argc; i++) { - int len; - const char *w = Jim_GetString(argv[i], &len); + for (unsigned int i = 0; i < argc; i++) { + const char *w = Jim_GetString(argv[i], NULL); char *t = alloc_printf("%s %s", dbg, w); free(dbg); dbg = t; @@ -156,34 +87,6 @@ static void script_debug(Jim_Interp *interp, unsigned int argc, Jim_Obj * const free(dbg); } -static void script_command_args_free(char **words, unsigned nwords) -{ - for (unsigned i = 0; i < nwords; i++) - free(words[i]); - free(words); -} - -static char **script_command_args_alloc( - unsigned argc, Jim_Obj * const *argv, unsigned *nwords) -{ - char **words = malloc(argc * sizeof(char *)); - if (!words) - return NULL; - - unsigned i; - for (i = 0; i < argc; i++) { - int len; - const char *w = Jim_GetString(argv[i], &len); - words[i] = strdup(w); - if (!words[i]) { - script_command_args_free(words, i); - return NULL; - } - } - *nwords = i; - return words; -} - struct command_context *current_command_context(Jim_Interp *interp) { /* grab the command context from the associated data */ @@ -227,13 +130,13 @@ static struct command *command_new(struct command_context *cmd_ctx, assert(cr->name); /* - * If it is a non-jim command with no .usage specified, + * If it is a command with no .usage specified, * log an error. * * strlen(.usage) == 0 means that the command takes no * arguments. */ - if (!cr->jim_handler && !cr->usage) + if (!cr->usage) LOG_ERROR("BUG: command '%s' does not have the " "'.usage' field filled out", full_name); @@ -249,7 +152,6 @@ static struct command *command_new(struct command_context *cmd_ctx, } c->handler = cr->handler; - c->jim_handler = cr->jim_handler; c->mode = cr->mode; if (cr->help || cr->usage) @@ -318,7 +220,7 @@ int __register_commands(struct command_context *cmd_ctx, const char *cmd_prefix, struct target *override_target) { int retval = ERROR_OK; - unsigned i; + unsigned int i; for (i = 0; cmds[i].name || cmds[i].chain; i++) { const struct command_registration *cr = cmds + i; @@ -353,7 +255,7 @@ int __register_commands(struct command_context *cmd_ctx, const char *cmd_prefix, } } if (retval != ERROR_OK) { - for (unsigned j = 0; j < i; j++) + for (unsigned int j = 0; j < i; j++) unregister_command(cmd_ctx, cmd_prefix, cmds[j].name); } return retval; @@ -519,15 +421,26 @@ static bool command_can_run(struct command_context *cmd_ctx, struct command *c, return false; } -static int run_command(struct command_context *context, - struct command *c, const char **words, unsigned num_words) +static int exec_command(Jim_Interp *interp, struct command_context *context, + struct command *c, int argc, Jim_Obj * const *argv) { + /* use c->handler */ + const char **words = malloc(argc * sizeof(char *)); + if (!words) { + LOG_ERROR("Out of memory"); + return JIM_ERR; + } + + for (int i = 0; i < argc; i++) + words[i] = Jim_GetString(argv[i], NULL); + struct command_invocation cmd = { .ctx = context, .current = c, .name = c->name, - .argc = num_words - 1, + .argc = argc - 1, .argv = words + 1, + .jimtcl_argv = argv + 1, }; cmd.output = Jim_NewEmptyStringObj(context->interp); @@ -543,12 +456,21 @@ static int run_command(struct command_context *context, if (retval != ERROR_OK) LOG_DEBUG("Command '%s' failed with error code %d", words[0], retval); - /* Use the command output as the Tcl result */ - Jim_SetResult(context->interp, cmd.output); + /* + * Use the command output as the Tcl result. + * Drop last '\n' to allow command output concatenation + * while keep using command_print() everywhere. + */ + const char *output_txt = Jim_String(cmd.output); + int len = strlen(output_txt); + if (len && output_txt[len - 1] == '\n') + --len; + Jim_SetResultString(context->interp, output_txt, len); } Jim_DecrRefCount(context->interp, cmd.output); - return retval; + free(words); + return command_retval_set(interp, retval); } int command_run_line(struct command_context *context, char *line) @@ -577,7 +499,7 @@ int command_run_line(struct command_context *context, char *line) Jim_DeleteAssocData(interp, "retval"); retcode = Jim_SetAssocData(interp, "retval", NULL, &retval); if (retcode == JIM_OK) { - retcode = Jim_Eval_Named(interp, line, 0, 0); + retcode = Jim_Eval_Named(interp, line, NULL, 0); Jim_DeleteAssocData(interp, "retval"); } @@ -657,19 +579,19 @@ void command_done(struct command_context *cmd_ctx) } /* find full path to file */ -static int jim_find(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_find) { - if (argc != 2) - return JIM_ERR; - const char *file = Jim_GetString(argv[1], NULL); - char *full_path = find_file(file); + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + char *full_path = find_file(CMD_ARGV[0]); if (!full_path) - return JIM_ERR; - Jim_Obj *result = Jim_NewStringObj(interp, full_path, strlen(full_path)); + return ERROR_COMMAND_ARGUMENT_INVALID; + + command_print(CMD, "%s", full_path); free(full_path); - Jim_SetResult(interp, result); - return JIM_OK; + return ERROR_OK; } COMMAND_HANDLER(handle_echo) @@ -680,21 +602,34 @@ COMMAND_HANDLER(handle_echo) } if (CMD_ARGC != 1) - return ERROR_FAIL; + return ERROR_COMMAND_SYNTAX_ERROR; LOG_USER("%s", CMD_ARGV[0]); return ERROR_OK; } -/* Capture progress output and return as tcl return value. If the - * progress output was empty, return tcl return value. +static void tcl_output(void *privData, const char *file, unsigned int line, + const char *function, const char *string) +{ + struct log_capture_state *state = privData; + char *old = state->output; + + state->output = alloc_printf("%s%s", old ? old : "", string); + free(old); + if (!state->output) + LOG_ERROR("Out of memory"); +} + +/* + * Return both the progress output (LOG_INFO and higher) + * and the tcl return value of a command. */ -static int jim_capture(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_command_capture) { - if (argc != 2) - return JIM_ERR; + struct log_capture_state state = {NULL}; - struct log_capture_state *state = command_log_capture_start(interp); + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; /* disable polling during capture. This avoids capturing output * from polling. @@ -702,18 +637,26 @@ static int jim_capture(Jim_Interp *interp, int argc, Jim_Obj *const *argv) * This is necessary in order to avoid accidentally getting a non-empty * string for tcl fn's. */ - bool save_poll = jtag_poll_get_enabled(); + bool save_poll_mask = jtag_poll_mask(); + + log_add_callback(tcl_output, &state); + + int jimretval = Jim_EvalObj(CMD_CTX->interp, CMD_JIMTCL_ARGV[0]); + const char *cmd_result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), NULL); + + log_remove_callback(tcl_output, &state); - jtag_poll_set_enabled(false); + jtag_poll_unmask(save_poll_mask); - const char *str = Jim_GetString(argv[1], NULL); - int retcode = Jim_Eval_Named(interp, str, __THIS__FILE__, __LINE__); + if (state.output && *state.output) + command_print(CMD, "%s", state.output); - jtag_poll_set_enabled(save_poll); + if (cmd_result && *cmd_result) + command_print(CMD, "%s", cmd_result); - command_log_capture_finish(state); + free(state.output); - return retcode; + return (jimretval == JIM_OK) ? ERROR_OK : ERROR_FAIL; } struct help_entry { @@ -737,12 +680,12 @@ static COMMAND_HELPER(command_help_show_list, bool show_help, const char *cmd_ma #define HELP_LINE_WIDTH(_n) (int)(76 - (2 * _n)) -static void command_help_show_indent(unsigned n) +static void command_help_show_indent(unsigned int n) { - for (unsigned i = 0; i < n; i++) + for (unsigned int i = 0; i < n; i++) LOG_USER_N(" "); } -static void command_help_show_wrap(const char *str, unsigned n, unsigned n2) +static void command_help_show_wrap(const char *str, unsigned int n, unsigned int n2) { const char *cp = str, *last = str; while (*cp) { @@ -788,24 +731,7 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c, if (is_match && show_help) { char *msg; - /* TODO: factorize jim_command_mode() to avoid running jim command here */ - char *request = alloc_printf("command mode %s", c->cmd_name); - if (!request) { - LOG_ERROR("Out of memory"); - return ERROR_FAIL; - } - int retval = Jim_Eval(CMD_CTX->interp, request); - free(request); - enum command_mode mode = COMMAND_UNKNOWN; - if (retval != JIM_ERR) { - const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), NULL); - if (!strcmp(result, "any")) - mode = COMMAND_ANY; - else if (!strcmp(result, "config")) - mode = COMMAND_CONFIG; - else if (!strcmp(result, "exec")) - mode = COMMAND_EXEC; - } + enum command_mode mode = get_command_mode(CMD_CTX->interp, c->cmd_name); /* Normal commands are runtime-only; highlight exceptions */ if (mode != COMMAND_EXEC) { @@ -818,6 +744,7 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c, case COMMAND_ANY: stage_msg = " (command valid any time)"; break; + case COMMAND_UNKNOWN: default: stage_msg = " (?mode error?)"; break; @@ -826,11 +753,13 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c, } else msg = alloc_printf("%s", c->help ? c->help : ""); - if (msg) { - command_help_show_wrap(msg, n + 3, n + 3); - free(msg); - } else - return -ENOMEM; + if (!msg) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + command_help_show_wrap(msg, n + 3, n + 3); + free(msg); } return ERROR_OK; @@ -865,22 +794,19 @@ COMMAND_HANDLER(handle_help_command) return retval; } -static char *alloc_concatenate_strings(int argc, Jim_Obj * const *argv) +static char *alloc_concatenate_strings(int argc, const char **argv) { - char *prev, *all; - int i; - assert(argc >= 1); - all = strdup(Jim_GetString(argv[0], NULL)); + char *all = strdup(argv[0]); if (!all) { LOG_ERROR("Out of memory"); return NULL; } - for (i = 1; i < argc; ++i) { - prev = all; - all = alloc_printf("%s %s", all, Jim_GetString(argv[i], NULL)); + for (int i = 1; i < argc; ++i) { + char *prev = all; + all = alloc_printf("%s %s", all, argv[i]); free(prev); if (!all) { LOG_ERROR("Out of memory"); @@ -891,23 +817,6 @@ static char *alloc_concatenate_strings(int argc, Jim_Obj * const *argv) return all; } -static int exec_command(Jim_Interp *interp, struct command_context *cmd_ctx, - struct command *c, int argc, Jim_Obj * const *argv) -{ - if (c->jim_handler) - return c->jim_handler(interp, argc, argv); - - /* use c->handler */ - unsigned int nwords; - char **words = script_command_args_alloc(argc, argv, &nwords); - if (!words) - return JIM_ERR; - - int retval = run_command(cmd_ctx, c, (const char **)words, nwords); - script_command_args_free(words, nwords); - return command_retval_set(interp, retval); -} - static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { /* check subcommands */ @@ -928,7 +837,7 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a script_debug(interp, argc, argv); struct command *c = jim_to_command(interp); - if (!c->jim_handler && !c->handler) { + if (!c->handler) { Jim_EvalObjPrefix(interp, Jim_NewStringObj(interp, "usage", -1), 1, argv); return JIM_ERR; } @@ -938,7 +847,7 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a if (!command_can_run(cmd_ctx, c, Jim_GetString(argv[0], NULL))) return JIM_ERR; - target_call_timer_callbacks_now(); + target_call_timer_callbacks(); /* * Black magic of overridden current target: @@ -962,35 +871,40 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a return retval; } -static int jim_command_mode(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +static enum command_mode get_command_mode(Jim_Interp *interp, const char *cmd_name) { - struct command_context *cmd_ctx = current_command_context(interp); - enum command_mode mode; + if (!cmd_name) + return COMMAND_UNKNOWN; - if (argc > 1) { - char *full_name = alloc_concatenate_strings(argc - 1, argv + 1); + Jim_Obj *s = Jim_NewStringObj(interp, cmd_name, -1); + Jim_IncrRefCount(s); + Jim_Cmd *cmd = Jim_GetCommand(interp, s, JIM_NONE); + Jim_DecrRefCount(interp, s); + + if (!cmd || !(jimcmd_is_proc(cmd) || jimcmd_is_oocd_command(cmd))) + return COMMAND_UNKNOWN; + + /* tcl proc */ + if (jimcmd_is_proc(cmd)) + return COMMAND_ANY; + + struct command *c = jimcmd_privdata(cmd); + return c->mode; +} + +COMMAND_HANDLER(handle_command_mode) +{ + enum command_mode mode = CMD_CTX->mode; + + if (CMD_ARGC) { + char *full_name = alloc_concatenate_strings(CMD_ARGC, CMD_ARGV); if (!full_name) - return JIM_ERR; - Jim_Obj *s = Jim_NewStringObj(interp, full_name, -1); - Jim_IncrRefCount(s); - Jim_Cmd *cmd = Jim_GetCommand(interp, s, JIM_NONE); - Jim_DecrRefCount(interp, s); - free(full_name); - if (!cmd || !(jimcmd_is_proc(cmd) || jimcmd_is_oocd_command(cmd))) { - Jim_SetResultString(interp, "unknown", -1); - return JIM_OK; - } + return ERROR_FAIL; - if (jimcmd_is_proc(cmd)) { - /* tcl proc */ - mode = COMMAND_ANY; - } else { - struct command *c = jimcmd_privdata(cmd); + mode = get_command_mode(CMD_CTX->interp, full_name); - mode = c->mode; - } - } else - mode = cmd_ctx->mode; + free(full_name); + } const char *mode_str; switch (mode) { @@ -1003,12 +917,13 @@ static int jim_command_mode(Jim_Interp *interp, int argc, Jim_Obj *const *argv) case COMMAND_EXEC: mode_str = "exec"; break; + case COMMAND_UNKNOWN: default: mode_str = "unknown"; break; } - Jim_SetResultString(interp, mode_str, -1); - return JIM_OK; + command_print(CMD, "%s", mode_str); + return ERROR_OK; } int help_del_all_commands(struct command_context *cmd_ctx) @@ -1147,7 +1062,7 @@ static const struct command_registration command_subcommand_handlers[] = { { .name = "mode", .mode = COMMAND_ANY, - .jim_handler = jim_command_mode, + .handler = handle_command_mode, .usage = "[command_name ...]", .help = "Returns the command modes allowed by a command: " "'any', 'config', or 'exec'. If no command is " @@ -1162,14 +1077,14 @@ static const struct command_registration command_builtin_handlers[] = { { .name = "ocd_find", .mode = COMMAND_ANY, - .jim_handler = jim_find, + .handler = handle_find, .help = "find full path to file", .usage = "file", }, { .name = "capture", .mode = COMMAND_ANY, - .jim_handler = jim_capture, + .handler = handle_command_capture, .help = "Capture progress output and return as tcl return value. If the " "progress output was empty, return tcl return value.", .usage = "command", @@ -1343,7 +1258,7 @@ DEFINE_PARSE_NUM_TYPE(_llong, long long, strtoll, LLONG_MIN, LLONG_MAX) #define DEFINE_PARSE_ULONGLONG(name, type, min, max) \ DEFINE_PARSE_WRAPPER(name, type, min, max, unsigned long long, _ullong) -DEFINE_PARSE_ULONGLONG(_uint, unsigned, 0, UINT_MAX) +DEFINE_PARSE_ULONGLONG(_uint, unsigned int, 0, UINT_MAX) DEFINE_PARSE_ULONGLONG(_u64, uint64_t, 0, UINT64_MAX) DEFINE_PARSE_ULONGLONG(_u32, uint32_t, 0, UINT32_MAX) DEFINE_PARSE_ULONGLONG(_u16, uint16_t, 0, UINT16_MAX) @@ -1386,6 +1301,27 @@ int command_parse_bool_arg(const char *in, bool *out) return ERROR_COMMAND_SYNTAX_ERROR; } +COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len) +{ + assert(str); + assert(buf); + + int ret = str_to_buf(str, buf, buf_len); + if (ret == ERROR_OK) + return ret; + + /* Provide a clear error message to the user */ + if (ret == ERROR_INVALID_NUMBER) { + command_print(CMD, "'%s' is not a valid number", str); + } else if (ret == ERROR_NUMBER_EXCEEDS_BUFFER) { + command_print(CMD, "Number %s exceeds %u bits", str, buf_len); + } else { + command_print(CMD, "Could not parse number '%s'", str); + } + + return ERROR_COMMAND_ARGUMENT_INVALID; +} + COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label) { switch (CMD_ARGC) { diff --git a/src/helper/command.h b/src/helper/command.h index 478e5c8ada..8bd2430e0b 100644 --- a/src/helper/command.h +++ b/src/helper/command.h @@ -21,7 +21,7 @@ /* To achieve C99 printf compatibility in MinGW, gnu_printf should be * used for __attribute__((format( ... ))), with GCC v4.4 or later */ -#if (defined(IS_MINGW) && (((__GNUC__ << 16) + __GNUC_MINOR__) >= 0x00040004)) +#if (defined(IS_MINGW) && (((__GNUC__ << 16) + __GNUC_MINOR__) >= 0x00040004)) && !defined(__clang__) #define PRINTF_ATTRIBUTE_FORMAT gnu_printf #else #define PRINTF_ATTRIBUTE_FORMAT printf @@ -77,8 +77,9 @@ struct command_invocation { struct command_context *ctx; struct command *current; const char *name; - unsigned argc; + unsigned int argc; const char **argv; + Jim_Obj * const *jimtcl_argv; Jim_Obj *output; }; @@ -153,6 +154,11 @@ void *jimcmd_privdata(Jim_Cmd *cmd); * rather than accessing the variable directly. It may be moved. */ #define CMD_ARGV (cmd->argv) +/** + * Use this macro to access the jimtcl arguments for the command being + * handled, rather than accessing the variable directly. It may be moved. + */ +#define CMD_JIMTCL_ARGV (cmd->jimtcl_argv) /** * Use this macro to access the name of the command being handled, * rather than accessing the variable directly. It may be moved. @@ -191,7 +197,6 @@ typedef __COMMAND_HANDLER((*command_handler_t)); struct command { char *name; command_handler_t handler; - Jim_CmdProc *jim_handler; void *jim_handler_data; /* Command handlers can use it for any handler specific data */ struct target *jim_override_target; @@ -228,7 +233,6 @@ static inline struct command *jim_to_command(Jim_Interp *interp) struct command_registration { const char *name; command_handler_t handler; - Jim_CmdProc *jim_handler; enum command_mode mode; const char *help; /** a string listing the options and arguments, required or optional */ @@ -370,10 +374,21 @@ struct command_context *copy_command_context(struct command_context *cmd_ctx); */ void command_done(struct command_context *context); +/* + * command_print() and command_print_sameline() are used to produce the TCL + * output of OpenOCD commands. command_print() automatically adds a '\n' at + * the end or the format string. Use command_print_sameline() to avoid the + * trailing '\n', e.g. to concatenate the command output in the same line. + * The very last '\n' of the command is stripped away (see run_command()). + * For commands that strictly require a '\n' as last output character, add + * it explicitly with either an empty command_print() or with a '\n' in the + * last command_print() and add a comment to document it. + */ void command_print(struct command_invocation *cmd, const char *format, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 2, 3))); void command_print_sameline(struct command_invocation *cmd, const char *format, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 2, 3))); + int command_run_line(struct command_context *context, char *line); int command_run_linef(struct command_context *context, const char *format, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 2, 3))); @@ -397,7 +412,7 @@ int parse_llong(const char *str, long long *ul); #define DECLARE_PARSE_WRAPPER(name, type) \ int parse ## name(const char *str, type * ul) -DECLARE_PARSE_WRAPPER(_uint, unsigned); +DECLARE_PARSE_WRAPPER(_uint, unsigned int); DECLARE_PARSE_WRAPPER(_u64, uint64_t); DECLARE_PARSE_WRAPPER(_u32, uint32_t); DECLARE_PARSE_WRAPPER(_u16, uint16_t); @@ -500,6 +515,15 @@ DECLARE_PARSE_WRAPPER(_target_addr, target_addr_t); int command_parse_bool_arg(const char *in, bool *out); COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label); +/** + * Parse a number (base 10, base 16 or base 8) and store the result + * into a bit buffer. Use the prefixes '0' and '0x' for base 8 and 16, + * otherwise defaults to base 10. + * + * In case of parsing error, a user-readable error message is produced. + */ +COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len); + /** parses an on/off command argument */ #define COMMAND_PARSE_ON_OFF(in, out) \ COMMAND_PARSE_BOOL(in, out, "on", "off") diff --git a/src/helper/compiler.h b/src/helper/compiler.h new file mode 100644 index 0000000000..312d261fc3 --- /dev/null +++ b/src/helper/compiler.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This file contains compiler specific workarounds to handle different + * compilers and different compiler versions. + * Inspired by Linux's include/linux/compiler_attributes.h + * and file sys/cdefs.h in libc and newlib. + */ + +#ifndef OPENOCD_HELPER_COMPILER_H +#define OPENOCD_HELPER_COMPILER_H + +/* + * __has_attribute is supported on gcc >= 5, clang >= 2.9 and icc >= 17. + */ +#ifndef __has_attribute +# define __has_attribute(x) 0 +#endif + +/* + * The __returns_nonnull function attribute marks the return type of the function + * as always being non-null. + */ +#ifndef __returns_nonnull +# if __has_attribute(__returns_nonnull__) +# define __returns_nonnull __attribute__((__returns_nonnull__)) +# else +# define __returns_nonnull +# endif +#endif + +/* + * The __nonnull function attribute marks pointer parameters that + * must not be NULL. + * + * clang for Apple defines + * #define __nonnull _Nonnull + * that is a per argument attribute, incompatible with the gcc per function attribute __nonnull__. + * gcc for Apple includes sys/cdefs.h from MacOSX.sdk that defines + * #define __nonnull + * In both cases, undefine __nonnull to keep compatibility among compilers and platforms. + */ +#if defined(__APPLE__) +# undef __nonnull +#endif +#ifndef __nonnull +# if __has_attribute(__nonnull__) +# define __nonnull(params) __attribute__ ((__nonnull__ params)) +# else +# define __nonnull(params) +# endif +#endif + +#endif /* OPENOCD_HELPER_COMPILER_H */ diff --git a/src/helper/configuration.c b/src/helper/configuration.c index b62279c28d..447b0dfefa 100644 --- a/src/helper/configuration.c +++ b/src/helper/configuration.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2004, 2005 by Dominic Rath * @@ -71,17 +71,18 @@ char *find_file(const char *file) full_path = alloc_printf("%s", file); fp = fopen(full_path, mode); - while (!fp) { - free(full_path); - full_path = NULL; - dir = *search_dirs++; + if (script_search_dirs) + while (!fp) { + free(full_path); + full_path = NULL; + dir = *search_dirs++; - if (!dir) - break; + if (!dir) + break; - full_path = alloc_printf("%s/%s", dir, file); - fp = fopen(full_path, mode); - } + full_path = alloc_printf("%s/%s", dir, file); + fp = fopen(full_path, mode); + } if (fp) { fclose(fp); diff --git a/src/helper/configuration.h b/src/helper/configuration.h index 295ea591d6..d646670eb3 100644 --- a/src/helper/configuration.h +++ b/src/helper/configuration.h @@ -11,6 +11,7 @@ #ifndef OPENOCD_HELPER_CONFIGURATION_H #define OPENOCD_HELPER_CONFIGURATION_H +#include <stdio.h> #include <helper/command.h> int parse_cmdline_args(struct command_context *cmd_ctx, diff --git a/src/helper/crc32.c b/src/helper/crc32.c new file mode 100644 index 0000000000..441a46c57f --- /dev/null +++ b/src/helper/crc32.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2013-2014 by Franck Jullien * + * elec4fun@gmail.com * + * * + * Copyright (C) 2022 Otto-von-Guericke-Universität Magdeburg * + * marian.buschsieweke@ovgu.de * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "crc32.h" +#include <stdint.h> +#include <stddef.h> + +static uint32_t crc_le_step(uint32_t poly, uint32_t crc, uint32_t data_in, + unsigned int data_bits) +{ + for (unsigned int i = 0; i < data_bits; i++) { + uint32_t d, c; + d = ((data_in >> i) & 0x1) ? 0xffffffff : 0; + c = (crc & 0x1) ? 0xffffffff : 0; + crc = crc >> 1; + crc = crc ^ ((d ^ c) & poly); + } + + return crc; +} + +uint32_t crc32_le(uint32_t poly, uint32_t seed, const void *_data, + size_t data_len) +{ + if (((uintptr_t)_data & 0x3) || (data_len & 0x3)) { + /* data is unaligned, processing data one byte at a time */ + const uint8_t *data = _data; + for (size_t i = 0; i < data_len; i++) + seed = crc_le_step(poly, seed, data[i], 8); + } else { + /* data is aligned, processing 32 bit at a time */ + data_len >>= 2; + const uint32_t *data = _data; + for (size_t i = 0; i < data_len; i++) + seed = crc_le_step(poly, seed, data[i], 32); + } + + return seed; +} diff --git a/src/helper/crc32.h b/src/helper/crc32.h new file mode 100644 index 0000000000..8f077863a3 --- /dev/null +++ b/src/helper/crc32.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 Otto-von-Guericke-Universität Magdeburg * + * marian.buschsieweke@ovgu.de * + ***************************************************************************/ + +#ifndef OPENOCD_HELPER_CRC32_H +#define OPENOCD_HELPER_CRC32_H + +#include <stdint.h> +#include <stddef.h> + +/** @file + * A generic CRC32 implementation + */ + +/** + * CRC32 polynomial commonly used for little endian CRC32 + */ +#define CRC32_POLY_LE 0xedb88320 + +/** + * Calculate the CRC32 value of the given data + * @param poly The polynomial of the CRC + * @param seed The seed to use (mostly either `0` or `0xffffffff`) + * @param data The data to calculate the CRC32 of + * @param data_len The length of the data in @p data in bytes + * @return The CRC value of the first @p data_len bytes at @p data + * @note This function can be used to incrementally compute the CRC one + * chunk of data at a time by using the CRC32 of the previous chunk + * as @p seed for the next chunk. + */ +uint32_t crc32_le(uint32_t poly, uint32_t seed, const void *data, + size_t data_len); + +#endif /* OPENOCD_HELPER_CRC32_H */ diff --git a/src/helper/fileio.c b/src/helper/fileio.c index a4130b79c0..a290a5d2ff 100644 --- a/src/helper/fileio.c +++ b/src/helper/fileio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * diff --git a/src/helper/jep106.c b/src/helper/jep106.c index 992452d270..62d24a9b23 100644 --- a/src/helper/jep106.c +++ b/src/helper/jep106.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 Andreas Fritiofson * @@ -26,7 +26,7 @@ const char *jep106_table_manufacturer(unsigned int bank, unsigned int id) /* index is zero based */ id--; - if (bank >= ARRAY_SIZE(jep106) || jep106[bank][id] == 0) + if (bank >= ARRAY_SIZE(jep106) || !jep106[bank][id]) return "<unknown>"; return jep106[bank][id]; diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc index 41afdb8456..5e50e19550 100644 --- a/src/helper/jep106.inc +++ b/src/helper/jep106.inc @@ -1,13 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* - * Should be autogenerated with update_jep106.pl but latest - * file from JEDEC is only available in PDF form. The PDF - * also breaks the pdftotext flow due to embedded watermarks. - * Created with a mix of scripts and manual editing. + * The manufacturer's standard identification code list appears in JEP106. + * Copyright (c) 2025 JEDEC. All rights reserved. + * + * JEP106 is regularly updated. For the current manufacturer's standard + * identification code list, please visit the JEDEC website at www.jedec.org . */ + +/* This file is aligned to revision JEP106BM June 2025. */ + [0][0x01 - 1] = "AMD", [0][0x02 - 1] = "AMI", [0][0x03 - 1] = "Fairchild", -[0][0x04 - 1] = "Fujitsu", +[0][0x04 - 1] = "RAMXEED Limited", [0][0x05 - 1] = "GTE", [0][0x06 - 1] = "Harris", [0][0x07 - 1] = "Hitachi", @@ -22,7 +28,7 @@ [0][0x10 - 1] = "NEC", [0][0x11 - 1] = "RCA", [0][0x12 - 1] = "Raytheon", -[0][0x13 - 1] = "Conexant (Rockwell)", +[0][0x13 - 1] = "Synaptics", [0][0x14 - 1] = "Seeq", [0][0x15 - 1] = "NXP (Philips)", [0][0x16 - 1] = "Synertek", @@ -72,7 +78,7 @@ [0][0x42 - 1] = "Macronix", [0][0x43 - 1] = "Xerox", [0][0x44 - 1] = "Plus Logic", -[0][0x45 - 1] = "Western Digital Technologies Inc", +[0][0x45 - 1] = "SanDisk Technologies Inc", [0][0x46 - 1] = "Elan Circuit Tech.", [0][0x47 - 1] = "European Silicon Str.", [0][0x48 - 1] = "Apple Computer", @@ -80,7 +86,7 @@ [0][0x4a - 1] = "Compaq", [0][0x4b - 1] = "Protocol Engines", [0][0x4c - 1] = "SCI", -[0][0x4d - 1] = "Seiko Instruments", +[0][0x4d - 1] = "ABLIC", [0][0x4e - 1] = "Samsung", [0][0x4f - 1] = "I3 Design System", [0][0x50 - 1] = "Klic", @@ -143,7 +149,7 @@ [1][0x0b - 1] = "Bestlink Systems", [1][0x0c - 1] = "Graychip", [1][0x0d - 1] = "GENNUM", -[1][0x0e - 1] = "VideoLogic", +[1][0x0e - 1] = "Imagination Technologies Limited", [1][0x0f - 1] = "Robert Bosch", [1][0x10 - 1] = "Chip Express", [1][0x11 - 1] = "DATARAM", @@ -171,7 +177,7 @@ [1][0x27 - 1] = "Cabletron", [1][0x28 - 1] = "STEC (Silicon Tech)", [1][0x29 - 1] = "Vanguard", -[1][0x2a - 1] = "Hagiwara Sys-Com", +[1][0x2a - 1] = "Hagiwara Solutions Co Ltd", [1][0x2b - 1] = "Vantis", [1][0x2c - 1] = "Celestica", [1][0x2d - 1] = "Century", @@ -966,7 +972,7 @@ [7][0x4e - 1] = "Mustang", [7][0x4f - 1] = "Orca Systems", [7][0x50 - 1] = "Passif Semiconductor", -[7][0x51 - 1] = "GigaDevice Semiconductor (Beijing) Inc", +[7][0x51 - 1] = "GigaDevice Semiconductor (Beijing)", [7][0x52 - 1] = "Memphis Electronic", [7][0x53 - 1] = "Beckhoff Automation GmbH", [7][0x54 - 1] = "Harmony Semiconductor Corp", @@ -1037,7 +1043,7 @@ [8][0x17 - 1] = "Axell Corporation", [8][0x18 - 1] = "Essencore Limited", [8][0x19 - 1] = "Phytium", -[8][0x1a - 1] = "Xi'an UniIC Semiconductors Co Ltd", +[8][0x1a - 1] = "UniIC Semiconductors Co Ltd", [8][0x1b - 1] = "Ambiq Micro", [8][0x1c - 1] = "eveRAM Technology Inc", [8][0x1d - 1] = "Infomax", @@ -1367,7 +1373,7 @@ [10][0x65 - 1] = "Esperanto Technologies", [10][0x66 - 1] = "JinSheng Electronic (Shenzhen) Co Ltd", [10][0x67 - 1] = "Shenzhen Shi Bolunshuai Technology", -[10][0x68 - 1] = "Shanghai Rei Zuan Information Tech", +[10][0x68 - 1] = "Shanghai Ruixuan Information Tech", [10][0x69 - 1] = "Fraunhofer IIS", [10][0x6a - 1] = "Kandou Bus SA", [10][0x6b - 1] = "Acer", @@ -1444,7 +1450,7 @@ [11][0x34 - 1] = "Acacia Communications", [11][0x35 - 1] = "Beijinjinshengyihe Technology Co Ltd", [11][0x36 - 1] = "Zyzyx", -[11][0x37 - 1] = "T-HEAD Semiconductor Co Ltd", +[11][0x37 - 1] = "C-SKY Microsystems Co Ltd", [11][0x38 - 1] = "Shenzhen Hystou Technology Co Ltd", [11][0x39 - 1] = "Syzexion", [11][0x3a - 1] = "Kembona", @@ -1495,7 +1501,7 @@ [11][0x67 - 1] = "Guangzhou Shuvrwine Technology Co", [11][0x68 - 1] = "Shenzhen Hangshun Chip Technology", [11][0x69 - 1] = "Chengboliwei Electronic Business", -[11][0x6a - 1] = "Kowin Memory Technology Co Ltd", +[11][0x6a - 1] = "Kowin Technology HK Limited", [11][0x6b - 1] = "Euronet Technology Inc", [11][0x6c - 1] = "SCY", [11][0x6d - 1] = "Shenzhen Xinhongyusheng Electrical", @@ -1553,7 +1559,7 @@ [12][0x23 - 1] = "Tangem AG", [12][0x24 - 1] = "FuturePath Technology (Shenzhen) Co", [12][0x25 - 1] = "RC Module", -[12][0x26 - 1] = "Team Research Inc", +[12][0x26 - 1] = "Timetec International Inc", [12][0x27 - 1] = "ICMAX Technologies Co Limited", [12][0x28 - 1] = "Lynxi Technologies Ltd Co", [12][0x29 - 1] = "Guangzhou Taisupanke Computer Equipment", @@ -1571,7 +1577,7 @@ [12][0x35 - 1] = "Shenzhen Xinxinshun Technology Co", [12][0x36 - 1] = "Galois Inc", [12][0x37 - 1] = "Ubilite Inc", -[12][0x38 - 1] = "Shenzhen Quanzing Technology Co Ltd", +[12][0x38 - 1] = "Shenzhen Quanxing Technology Co Ltd", [12][0x39 - 1] = "Group RZX Technology LTDA", [12][0x3a - 1] = "Yottac Technology (XI'AN) Cooperation", [12][0x3b - 1] = "Shenzhen RuiRen Technology Co Ltd", @@ -1611,4 +1617,471 @@ [12][0x5d - 1] = "OLOy Technology", [12][0x5e - 1] = "Wuhan P&S Semiconductor Co Ltd", [12][0x5f - 1] = "Sitrus Technology", +[12][0x60 - 1] = "AnHui Conner Storage Co Ltd", +[12][0x61 - 1] = "Rochester Electronics", +[12][0x62 - 1] = "Wuxi Smart Memories Technologies Co", +[12][0x63 - 1] = "Star Memory", +[12][0x64 - 1] = "Agile Memory Technology Co Ltd", +[12][0x65 - 1] = "MEJEC", +[12][0x66 - 1] = "Rockchip Electronics Co Ltd", +[12][0x67 - 1] = "Dongguan Guanma e-commerce Co Ltd", +[12][0x68 - 1] = "Rayson Hi-Tech (SZ) Limited", +[12][0x69 - 1] = "MINRES Technologies GmbH", +[12][0x6a - 1] = "Himax Technologies Inc", +[12][0x6b - 1] = "Shenzhen Cwinner Technology Co Ltd", +[12][0x6c - 1] = "Tecmiyo", +[12][0x6d - 1] = "Shenzhen Suhuicun Technology Co Ltd", +[12][0x6e - 1] = "Vickter Electronics Co. Ltd.", +[12][0x6f - 1] = "lowRISC", +[12][0x70 - 1] = "EXEGate FZE", +[12][0x71 - 1] = "Shenzhen 9 Chapter Technologies Co", +[12][0x72 - 1] = "Addlink", +[12][0x73 - 1] = "Starsway", +[12][0x74 - 1] = "Pensando Systems Inc.", +[12][0x75 - 1] = "AirDisk", +[12][0x76 - 1] = "Shenzhen Speedmobile Technology Co", +[12][0x77 - 1] = "PEZY Computing", +[12][0x78 - 1] = "Extreme Engineering Solutions Inc", +[12][0x79 - 1] = "Shangxin Technology Co Ltd", +[12][0x7a - 1] = "Shanghai Zhaoxin Semiconductor Co", +[12][0x7b - 1] = "Xsight Labs Ltd", +[12][0x7c - 1] = "Hangzhou Hikstorage Technology Co", +[12][0x7d - 1] = "Dell Technologies", +[12][0x7e - 1] = "Guangdong StarFive Technology Co", +[13][0x01 - 1] = "TECOTON", +[13][0x02 - 1] = "Abko Co Ltd", +[13][0x03 - 1] = "Shenzhen Feisrike Technology Co Ltd", +[13][0x04 - 1] = "Shenzhen Sunhome Electronics Co Ltd", +[13][0x05 - 1] = "Global Mixed-mode Technology Inc", +[13][0x06 - 1] = "Shenzhen Weien Electronics Co Ltd.", +[13][0x07 - 1] = "Shenzhen Cooyes Technology Co Ltd", +[13][0x08 - 1] = "ShenZhen ChaoYing ZhiNeng Technology", +[13][0x09 - 1] = "E-Rockic Technology Company Limited", +[13][0x0a - 1] = "Aerospace Science Memory Shenzhen", +[13][0x0b - 1] = "Shenzhen Quanji Technology Co Ltd", +[13][0x0c - 1] = "Dukosi", +[13][0x0d - 1] = "Maxell Corporation of America", +[13][0x0e - 1] = "Shenshen Xinxintao Electronics Co Ltd", +[13][0x0f - 1] = "Zhuhai Sanxia Semiconductor Co Ltd", +[13][0x10 - 1] = "Groq Inc", +[13][0x11 - 1] = "AstraTek", +[13][0x12 - 1] = "Shenzhen Xinyuze Technology Co Ltd", +[13][0x13 - 1] = "All Bit Semiconductor", +[13][0x14 - 1] = "ACFlow", +[13][0x15 - 1] = "Shenzhen Sipeed Technology Co Ltd", +[13][0x16 - 1] = "Linzhi Hong Kong Co Limited", +[13][0x17 - 1] = "Supreme Wise Limited", +[13][0x18 - 1] = "Blue Cheetah Analog Design Inc", +[13][0x19 - 1] = "Hefei Laiku Technology Co Ltd", +[13][0x1a - 1] = "Zord", +[13][0x1b - 1] = "SBO Hearing A/S", +[13][0x1c - 1] = "Regent Sharp International Limited", +[13][0x1d - 1] = "Permanent Potential Limited", +[13][0x1e - 1] = "Creative World International Limited", +[13][0x1f - 1] = "Base Creation International Limited", +[13][0x20 - 1] = "Shenzhen Zhixin Chuanglian Technology", +[13][0x21 - 1] = "Protected Logic Corporation", +[13][0x22 - 1] = "Sabrent", +[13][0x23 - 1] = "Union Memory", +[13][0x24 - 1] = "NEUCHIPS Corporation", +[13][0x25 - 1] = "Ingenic Semiconductor Co Ltd", +[13][0x26 - 1] = "SiPearl", +[13][0x27 - 1] = "Shenzhen Actseno Information Technology", +[13][0x28 - 1] = "RIVAI Technologies (Shenzhen) Co Ltd", +[13][0x29 - 1] = "Shenzhen Sunny Technology Co Ltd", +[13][0x2a - 1] = "Cott Electronics Ltd", +[13][0x2b - 1] = "Shanghai Synsense Technologies Co Ltd", +[13][0x2c - 1] = "Shenzhen Jintang Fuming Optoelectronics", +[13][0x2d - 1] = "CloudBEAR LLC", +[13][0x2e - 1] = "Emzior, LLC", +[13][0x2f - 1] = "Ehiway Microelectronic Science Tech Co", +[13][0x30 - 1] = "UNIM Innovation Technology (Wu XI)", +[13][0x31 - 1] = "GDRAMARS", +[13][0x32 - 1] = "Meminsights Technology", +[13][0x33 - 1] = "Zhuzhou Hongda Electronics Corp Ltd", +[13][0x34 - 1] = "Luminous Computing Inc", +[13][0x35 - 1] = "PROXMEM", +[13][0x36 - 1] = "Draper Labs", +[13][0x37 - 1] = "ORICO Technologies Co. Ltd.", +[13][0x38 - 1] = "Space Exploration Technologies Corp", +[13][0x39 - 1] = "AONDEVICES Inc", +[13][0x3a - 1] = "Shenzhen Netforward Micro Electronic", +[13][0x3b - 1] = "Syntacore Ltd", +[13][0x3c - 1] = "Shenzhen Secmem Microelectronics Co", +[13][0x3d - 1] = "ONiO As", +[13][0x3e - 1] = "Shenzhen Peladn Technology Co Ltd", +[13][0x3f - 1] = "O-Cubes Shanghai Microelectronics", +[13][0x40 - 1] = "ASTC", +[13][0x41 - 1] = "UMIS", +[13][0x42 - 1] = "Paradromics", +[13][0x43 - 1] = "Sinh Micro Co Ltd", +[13][0x44 - 1] = "Metorage Semiconductor Technology Co", +[13][0x45 - 1] = "Aeva Inc", +[13][0x46 - 1] = "HongKong Hyunion Electronics Co Ltd", +[13][0x47 - 1] = "China Flash Co Ltd", +[13][0x48 - 1] = "Sunplus Technology Co Ltd", +[13][0x49 - 1] = "Idaho Scientific", +[13][0x4a - 1] = "Suzhou SF Micro Electronics Co Ltd", +[13][0x4b - 1] = "IMEX Cap AG", +[13][0x4c - 1] = "Fitipower Integrated Technology Co Ltd", +[13][0x4d - 1] = "ShenzhenWooacme Technology Co Ltd", +[13][0x4e - 1] = "KeepData Original Chips", +[13][0x4f - 1] = "Rivos Inc", +[13][0x50 - 1] = "Big Innovation Company Limited", +[13][0x51 - 1] = "Wuhan YuXin Semiconductor Co Ltd", +[13][0x52 - 1] = "United Memory Technology (Jiangsu)", +[13][0x53 - 1] = "PQShield Ltd", +[13][0x54 - 1] = "ArchiTek Corporation", +[13][0x55 - 1] = "ShenZhen AZW Technology Co Ltd", +[13][0x56 - 1] = "Hengchi Zhixin (Dongguan) Technology", +[13][0x57 - 1] = "Eggtronic Engineering Spa", +[13][0x58 - 1] = "Fusontai Technology", +[13][0x59 - 1] = "PULP Platform", +[13][0x5a - 1] = "Koitek Electronic Technology (Shenzhen) Co", +[13][0x5b - 1] = "Shenzhen Jiteng Network Technology Co", +[13][0x5c - 1] = "Aviva Links Inc", +[13][0x5d - 1] = "Trilinear Technologies Inc", +[13][0x5e - 1] = "Shenzhen Developer Microelectronics Co", +[13][0x5f - 1] = "Guangdong OPPO Mobile Telecommunication", +[13][0x60 - 1] = "Akeana", +[13][0x61 - 1] = "Lyczar", +[13][0x62 - 1] = "QJTEK", +[13][0x63 - 1] = "Shenzhen Shangzhaoyuan Technology", +[13][0x64 - 1] = "Han Stor", +[13][0x65 - 1] = "China Micro Semicon Co., Ltd.", +[13][0x66 - 1] = "Shenzhen Zhuqin Technology Co Ltd", +[13][0x67 - 1] = "Shanghai Ningyuan Electronic Technology", +[13][0x68 - 1] = "Auradine", +[13][0x69 - 1] = "Suzhou Yishuo Electronics Co Ltd", +[13][0x6a - 1] = "Faurecia Clarion Electronics", +[13][0x6b - 1] = "SiMa Technologies", +[13][0x6c - 1] = "CFD Sales Inc", +[13][0x6d - 1] = "Suzhou Comay Information Co Ltd", +[13][0x6e - 1] = "Yentek", +[13][0x6f - 1] = "Qorvo Inc", +[13][0x70 - 1] = "Shenzhen Youzhi Computer Technology", +[13][0x71 - 1] = "Sychw Technology (Shenzhen) Co Ltd", +[13][0x72 - 1] = "MK Founder Technology Co Ltd", +[13][0x73 - 1] = "Siliconwaves Technologies Co Ltd", +[13][0x74 - 1] = "Hongkong Hyunion Electronics Co Ltd", +[13][0x75 - 1] = "Shenzhen Xinxinzhitao Electronics Business", +[13][0x76 - 1] = "Shenzhen HenQi Electronic Commerce Co", +[13][0x77 - 1] = "Shenzhen Jingyi Technology Co Ltd", +[13][0x78 - 1] = "Xiaohua Semiconductor Co. Ltd.", +[13][0x79 - 1] = "Shenzhen Dalu Semiconductor Technology", +[13][0x7a - 1] = "Shenzhen Ninespeed Electronics Co Ltd", +[13][0x7b - 1] = "ICYC Semiconductor Co Ltd", +[13][0x7c - 1] = "Shenzhen Jaguar Microsystems Co Ltd", +[13][0x7d - 1] = "Beijing EC-Founder Co Ltd", +[13][0x7e - 1] = "Shenzhen Taike Industrial Automation Co", +[14][0x01 - 1] = "Kalray SA", +[14][0x02 - 1] = "Shanghai Iluvatar CoreX Semiconductor Co", +[14][0x03 - 1] = "Fungible Inc", +[14][0x04 - 1] = "Song Industria E Comercio de Eletronicos", +[14][0x05 - 1] = "DreamBig Semiconductor Inc", +[14][0x06 - 1] = "ChampTek Electronics Corp", +[14][0x07 - 1] = "Fusontai Technology", +[14][0x08 - 1] = "Endress Hauser AG", +[14][0x09 - 1] = "altec ComputerSysteme GmbH", +[14][0x0a - 1] = "UltraRISC Technology (Shanghai) Co Ltd", +[14][0x0b - 1] = "Shenzhen Jing Da Kang Technology Co Ltd", +[14][0x0c - 1] = "Hangzhou Hongjun Microelectronics Co Ltd", +[14][0x0d - 1] = "Pliops Ltd", +[14][0x0e - 1] = "Cix Technology (Shanghai) Co Ltd", +[14][0x0f - 1] = "TeraDevices Inc", +[14][0x10 - 1] = "SpacemiT (Hangzhou)Technology Co Ltd", +[14][0x11 - 1] = "InnoPhase loT Inc", +[14][0x12 - 1] = "InnoPhase loT Inc", +[14][0x13 - 1] = "Yunhight Microelectronics", +[14][0x14 - 1] = "Samnix", +[14][0x15 - 1] = "HKC Storage Co Ltd", +[14][0x16 - 1] = "Chiplego Technology (Shanghai) Co Ltd", +[14][0x17 - 1] = "StoreSkill", +[14][0x18 - 1] = "Shenzhen Astou Technology Company", +[14][0x19 - 1] = "Guangdong LeapFive Technology Limited", +[14][0x1a - 1] = "Jin JuQuan", +[14][0x1b - 1] = "Huaxuan Technology (Shenzhen) Co Ltd", +[14][0x1c - 1] = "Gigastone Corporation", +[14][0x1d - 1] = "Kinsotin", +[14][0x1e - 1] = "PengYing", +[14][0x1f - 1] = "Shenzhen Xunhi Technology Co Ltd", +[14][0x20 - 1] = "FOXX Storage Inc", +[14][0x21 - 1] = "Shanghai Belling Corporation Ltd", +[14][0x22 - 1] = "Glenfy Tech Co Ltd", +[14][0x23 - 1] = "Sahasra Semiconductors Pvt Ltd", +[14][0x24 - 1] = "Chongqing SeekWave Technology Co Ltd", +[14][0x25 - 1] = "Shenzhen Zhixing Intelligent Manufacturing", +[14][0x26 - 1] = "Ethernovia", +[14][0x27 - 1] = "Shenzhen Xinrongda Technology Co Ltd", +[14][0x28 - 1] = "Hangzhou Clounix Technology Limited", +[14][0x29 - 1] = "JGINYUE", +[14][0x2a - 1] = "Shenzhen Xinwei Semiconductor Co Ltd", +[14][0x2b - 1] = "COLORFIRE Technology Co Ltd", +[14][0x2c - 1] = "B LKE", +[14][0x2d - 1] = "ZHUDIAN", +[14][0x2e - 1] = "REECHO", +[14][0x2f - 1] = "Enphase Energy Inc", +[14][0x30 - 1] = "Shenzhen Yingrui Storage Technology Co Ltd", +[14][0x31 - 1] = "Shenzhen Sinomos Semiconductor Technology", +[14][0x32 - 1] = "O2micro International Limited", +[14][0x33 - 1] = "Axelera AI BV", +[14][0x34 - 1] = "Silicon Legend Technology (Suzhou) Co Ltd", +[14][0x35 - 1] = "Suzhou Novosense Microelectronics Co Ltd", +[14][0x36 - 1] = "Pirateman", +[14][0x37 - 1] = "Yangtze MasonSemi", +[14][0x38 - 1] = "Shanghai Yunsilicon Technology Co Ltd", +[14][0x39 - 1] = "Rayson", +[14][0x3a - 1] = "Alphawave IP", +[14][0x3b - 1] = "Shenzhen Visions Chip Electronic Technology", +[14][0x3c - 1] = "KYO Group", +[14][0x3d - 1] = "Shenzhen Aboison Technology Co Ltd", +[14][0x3e - 1] = "Shenzhen JingSheng Semiconducto Co Ltd", +[14][0x3f - 1] = "Shenzhen Dingsheng Technology Co Ltd", +[14][0x40 - 1] = "EVAS Intelligence Co Ltd", +[14][0x41 - 1] = "Kaibright Electronic Technologies", +[14][0x42 - 1] = "Fraunhofer IMS", +[14][0x43 - 1] = "Shenzhen Xinrui Renhe Technology", +[14][0x44 - 1] = "Beijing Vcore Technology Co Ltd", +[14][0x45 - 1] = "Silicon Innovation Technologies Co Ltd", +[14][0x46 - 1] = "Shenzhen Zhengxinda Technology Co Ltd", +[14][0x47 - 1] = "Shenzhen Remai Electronics Co Lttd", +[14][0x48 - 1] = "Shenzhen Xinruiyan Electronics Co Ltd", +[14][0x49 - 1] = "CEC Huada Electronic Design Co Ltd", +[14][0x4a - 1] = "Westberry Technology Inc", +[14][0x4b - 1] = "Tongxin Microelectronics Co Ltd", +[14][0x4c - 1] = "UNIM Semiconductor (Shang Hai) Co Ltd", +[14][0x4d - 1] = "Shenzhen Qiaowenxingyu Industrial Co Ltd", +[14][0x4e - 1] = "ICC", +[14][0x4f - 1] = "Enfabrica Corporation", +[14][0x50 - 1] = "Niobium Microsystems Inc", +[14][0x51 - 1] = "Xiaoli AI Electronics (Shenzhen) Co Ltd", +[14][0x52 - 1] = "Silicon Mitus", +[14][0x53 - 1] = "Ajiatek Inc", +[14][0x54 - 1] = "HomeNet", +[14][0x55 - 1] = "Shenzhen Shubang Technology Co Ltd", +[14][0x56 - 1] = "Exacta Technologies Ltd", +[14][0x57 - 1] = "Synology", +[14][0x58 - 1] = "Trium Elektronik Bilgi Islem San Ve Dis", +[14][0x59 - 1] = "Wuxi HippStor Technology Co Ltd", +[14][0x5a - 1] = "SSCT", +[14][0x5b - 1] = "Sichuan Heentai Semiconductor Co Ltd", +[14][0x5c - 1] = "Zhejiang University", +[14][0x5d - 1] = "www.shingroup.cn", +[14][0x5e - 1] = "Suzhou Nano Mchip Technology Company", +[14][0x5f - 1] = "Feature Integration Technology Inc", +[14][0x60 - 1] = "d-Matrix", +[14][0x61 - 1] = "Golden Memory", +[14][0x62 - 1] = "Qingdao Thunderobot Technology Co Ltd", +[14][0x63 - 1] = "Shenzhen Tianxiang Chuangxin Technology", +[14][0x64 - 1] = "HYPHY USA", +[14][0x65 - 1] = "Valkyrie", +[14][0x66 - 1] = "Suzhou Hesetc Electronic Technology Co", +[14][0x67 - 1] = "Hainan Zhongyuncun Technology Co Ltd", +[14][0x68 - 1] = "Shenzhen Yousheng Bona Technology Co", +[14][0x69 - 1] = "Shenzhen Xinle Chuang Technology Co", +[14][0x6a - 1] = "DEEPX", +[14][0x6b - 1] = "iStarChip CA LLC", +[14][0x6c - 1] = "Shenzhen Vinreada Technology Co Ltd", +[14][0x6d - 1] = "Novatek Microelectronics Corp", +[14][0x6e - 1] = "Chemgdu EG Technology Co Ltd", +[14][0x6f - 1] = "AGI Technology", +[14][0x70 - 1] = "Syntiant", +[14][0x71 - 1] = "AOC", +[14][0x72 - 1] = "GamePP", +[14][0x73 - 1] = "Yibai Electronic Technologies", +[14][0x74 - 1] = "Hangzhou Rencheng Trading Co Ltd", +[14][0x75 - 1] = "HOGE Technology Co Ltd", +[14][0x76 - 1] = "United Micro Technology (Shenzhen) Co", +[14][0x77 - 1] = "Fabric of Truth Inc", +[14][0x78 - 1] = "Elpitech", +[14][0x79 - 1] = "Elitestek", +[14][0x7a - 1] = "Cornelis Networks Inc", +[14][0x7b - 1] = "WingSemi Technologies Co Ltd", +[14][0x7c - 1] = "ForwardEdge ASIC", +[14][0x7d - 1] = "Beijing Future Signet Technology Co Ltd", +[14][0x7e - 1] = "Fine Made Microelectronics Group Co Ltd", +[15][0x01 - 1] = "Changxin Memory Technology (Shanghai)", +[15][0x02 - 1] = "Synconv", +[15][0x03 - 1] = "MULTIUNIT", +[15][0x04 - 1] = "Zero ASIC Corporation", +[15][0x05 - 1] = "NTT Innovative Devices Corporation", +[15][0x06 - 1] = "Xbstor", +[15][0x07 - 1] = "Shenzhen South Electron Co Ltd", +[15][0x08 - 1] = "Iontra Inc", +[15][0x09 - 1] = "SIEFFI Inc", +[15][0x0a - 1] = "HK Winston Electronics Co Limited", +[15][0x0b - 1] = "Anhui SunChip Semiconductor Technology", +[15][0x0c - 1] = "HaiLa Technologies Inc", +[15][0x0d - 1] = "AUTOTALKS", +[15][0x0e - 1] = "Shenzhen Ranshuo Technology Co Limited", +[15][0x0f - 1] = "ScaleFlux", +[15][0x10 - 1] = "XC Memory", +[15][0x11 - 1] = "Guangzhou Beimu Technology Co Ltd", +[15][0x12 - 1] = "Rays Semiconductor Nanjing Co Ltd", +[15][0x13 - 1] = "Milli-Centi Intelligence Technology Jiangsu", +[15][0x14 - 1] = "Zilia Technologies", +[15][0x15 - 1] = "Incore Semiconductors", +[15][0x16 - 1] = "Kinetic Technologies", +[15][0x17 - 1] = "Nanjing Houmo Technology Co Ltd", +[15][0x18 - 1] = "Suzhou Yige Technology Co Ltd", +[15][0x19 - 1] = "Shenzhen Techwinsemi Technology Co Ltd", +[15][0x1a - 1] = "Pure Array Technology (Shanghai) Co Ltd", +[15][0x1b - 1] = "Shenzhen Techwinsemi Technology Udstore", +[15][0x1c - 1] = "RISE MODE", +[15][0x1d - 1] = "NEWREESTAR", +[15][0x1e - 1] = "Hangzhou Hualan Microeletronique Co Ltd", +[15][0x1f - 1] = "Senscomm Semiconductor Co Ltd", +[15][0x20 - 1] = "Holt Integrated Circuits", +[15][0x21 - 1] = "Tenstorrent Inc", +[15][0x22 - 1] = "SkyeChip", +[15][0x23 - 1] = "Guangzhou Kaishile Trading Co Ltd", +[15][0x24 - 1] = "Jing Pai Digital Technology (Shenzhen) Co", +[15][0x25 - 1] = "Memoritek", +[15][0x26 - 1] = "Zhejiang Hikstor Technology Co Ltd", +[15][0x27 - 1] = "Memoritek PTE Ltd", +[15][0x28 - 1] = "Longsailing Semiconductor Co Ltd", +[15][0x29 - 1] = "LX Semicon", +[15][0x2a - 1] = "Shenzhen Techwinsemi Technology Co Ltd", +[15][0x2b - 1] = "AOC", +[15][0x2c - 1] = "GOEPEL Electronic GmbH", +[15][0x2d - 1] = "Shenzhen G-Bong Technology Co Ltd", +[15][0x2e - 1] = "Openedges Technology Inc", +[15][0x2f - 1] = "EA Semi Shangahi Limited", +[15][0x30 - 1] = "EMBCORF", +[15][0x31 - 1] = "Shenzhen MicroBT Electronics Technology", +[15][0x32 - 1] = "Shanghai Simor Chip Semiconductor Co", +[15][0x33 - 1] = "Xllbyte", +[15][0x34 - 1] = "Guangzhou Maidite Electronics Co Ltd.", +[15][0x35 - 1] = "Zhejiang Changchun Technology Co Ltd", +[15][0x36 - 1] = "Beijing Cloud Security Technology Co Ltd", +[15][0x37 - 1] = "SSTC Technology and Distribution Inc", +[15][0x38 - 1] = "Shenzhen Panmin Technology Co Ltd", +[15][0x39 - 1] = "ITE Tech Inc", +[15][0x3a - 1] = "Beijing Zettastone Technology Co Ltd", +[15][0x3b - 1] = "Powerchip Micro Device", +[15][0x3c - 1] = "Shenzhen Ysemi Computing Co Ltd", +[15][0x3d - 1] = "Shenzhen Titan Micro Electronics Co Ltd", +[15][0x3e - 1] = "Shenzhen Macroflash Technology Co Ltd", +[15][0x3f - 1] = "Advantech Group", +[15][0x40 - 1] = "Shenzhen Xingjiachen Electronics Co Ltd", +[15][0x41 - 1] = "CHUQI", +[15][0x42 - 1] = "Dongguan Liesun Trading Co Ltd", +[15][0x43 - 1] = "Shenzhen Miuman Technology Co Ltd", +[15][0x44 - 1] = "Shenzhen Techwinsemi Technology Twsc", +[15][0x45 - 1] = "Encharge AI Inc", +[15][0x46 - 1] = "Shenzhen Zhenchuang Electronics Co Ltd", +[15][0x47 - 1] = "Giant Chip Co. Ltd", +[15][0x48 - 1] = "Shenzhen Runner Semiconductor Co Ltd", +[15][0x49 - 1] = "Scalinx", +[15][0x4a - 1] = "Shenzhen Lanqi Electronics Co Ltd", +[15][0x4b - 1] = "CoreComm Technology Co Ltd", +[15][0x4c - 1] = "DLI Memory", +[15][0x4d - 1] = "Shenzhen Fidat Technology Co Ltd", +[15][0x4e - 1] = "Hubei Yangtze Mason Semiconductor Tech", +[15][0x4f - 1] = "Flastor", +[15][0x50 - 1] = "PIRATEMAN", +[15][0x51 - 1] = "Barrie Technologies Co Ltd", +[15][0x52 - 1] = "Dynacard Co Ltd", +[15][0x53 - 1] = "Rivian Automotive", +[15][0x54 - 1] = "Shenzhen Fidat Technology Co Ltd", +[15][0x55 - 1] = "Zhejang Weiming Semiconductor Co Ltd", +[15][0x56 - 1] = "Shenzhen Xinhua Micro Technology Co Ltd", +[15][0x57 - 1] = "Duvonn Electronic Technology Co Ltd", +[15][0x58 - 1] = "Shenzhen Xinchang Technology Co Ltd", +[15][0x59 - 1] = "Leidos", +[15][0x5a - 1] = "Keepixo", +[15][0x5b - 1] = "Applied Brain Research Inc", +[15][0x5c - 1] = "Maxio Technology (Hangzhou) Co Ltd", +[15][0x5d - 1] = "HK DCHIP Technology Limited", +[15][0x5e - 1] = "Hitachi-LG Data Storage", +[15][0x5f - 1] = "Shenzhen Huadian Communication Co Ltd", +[15][0x60 - 1] = "Achieve Memory Technology (Suzhou) Co", +[15][0x61 - 1] = "Shenzhen Think Future Semiconductor Co", +[15][0x62 - 1] = "Innosilicon", +[15][0x63 - 1] = "Shenzhen Weilida Technology Co Ltd", +[15][0x64 - 1] = "Agrade Storage (Shenzhen) Co Ltd", +[15][0x65 - 1] = "Shenzhen Worldshine Data Technology Co", +[15][0x66 - 1] = "Mindgrove Technologies", +[15][0x67 - 1] = "BYD Semiconductor Co Ltd", +[15][0x68 - 1] = "Chipsine Semiconductor (Suzhou) Co Ltd", +[15][0x69 - 1] = "Shen Zhen Shi Xun He Shi Ji Dian Zi You", +[15][0x6a - 1] = "Shenzhen Jindacheng Computer Co Ltd", +[15][0x6b - 1] = "Shenzhen Baina Haichuan Technology Co", +[15][0x6c - 1] = "Shanghai Hengshi Electronic Technology", +[15][0x6d - 1] = "Beijing Boyu Tuxian Technology Co Ltd", +[15][0x6e - 1] = "China Chips Star Semiconductor Co Ltd", +[15][0x6f - 1] = "Shenzhen Shenghuacan Technology Co", +[15][0x70 - 1] = "Kinara Inc", +[15][0x71 - 1] = "TRASNA Semiconductor", +[15][0x72 - 1] = "KEYSOM", +[15][0x73 - 1] = "Shenzhen YYF Info Tech Co Ltd", +[15][0x74 - 1] = "Sharetronics Data Technology Co Ltd", +[15][0x75 - 1] = "AptCore Limited", +[15][0x76 - 1] = "Uchampion Semiconductor Co Ltd", +[15][0x77 - 1] = "YCT Semiconductor", +[15][0x78 - 1] = "FADU Inc", +[15][0x79 - 1] = "Hefei CLT Microelectronics Co LTD", +[15][0x7a - 1] = "Smart Technologies (BD) Ltd", +[15][0x7b - 1] = "Zhangdian District Qunyuan Computer Firm", +[15][0x7c - 1] = "Silicon Xpandas Electronics Co Ltd", +[15][0x7d - 1] = "PC Components Y Multimedia S", +[15][0x7e - 1] = "Shenzhen Tanlr Technology Group Co Ltd", +[16][0x01 - 1] = "Shenzhen JIEQING Technology Co Ltd", +[16][0x02 - 1] = "Orionix", +[16][0x03 - 1] = "JoulWatt Technology Co Ltd", +[16][0x04 - 1] = "Tenstorrent", +[16][0x05 - 1] = "Unis Flash Memory Technology (Chengdu)", +[16][0x06 - 1] = "Huatu Stars", +[16][0x07 - 1] = "Ardor Gaming", +[16][0x08 - 1] = "QuanZhou KunFang Semiconductor Co Ltd", +[16][0x09 - 1] = "EIAI PLANET", +[16][0x0a - 1] = "Ningbo Lingkai Semiconductor Technology Inc", +[16][0x0b - 1] = "Shenzhen Hancun Technology Co Ltd", +[16][0x0c - 1] = "Hongkong Manyi Technology Co Limited", +[16][0x0d - 1] = "Shenzhen Storgon Technology Co Ltd", +[16][0x0e - 1] = "YUNTU Microelectronics", +[16][0x0f - 1] = "Essencore", +[16][0x10 - 1] = "Shenzhen Xingyun Lianchuang Computer Tech", +[16][0x11 - 1] = "ShenZhen Aoscar Digital Tech Co Ltd", +[16][0x12 - 1] = "XOC Technologies Inc", +[16][0x13 - 1] = "BOS Semiconductors", +[16][0x14 - 1] = "Eliyan Corp", +[16][0x15 - 1] = "Hangzhou Lishu Technology Co Ltd", +[16][0x16 - 1] = "Tier IV Inc", +[16][0x17 - 1] = "Wuhan Xuanluzhe Network Technology Co", +[16][0x18 - 1] = "EA Semi (Shanghai) Limited", +[16][0x19 - 1] = "Tech Vision Information Technology Co", +[16][0x1a - 1] = "Zhihe Computing Technology", +[16][0x1b - 1] = "Beijing Apexichips Tech", +[16][0x1c - 1] = "Yemas Holdingsl Limited", +[16][0x1d - 1] = "Eluktronics", +[16][0x1e - 1] = "Walton Digi-Tech Industries Ltd", +[16][0x1f - 1] = "Beijing Qixin Gongli Technology Co Ltd", +[16][0x20 - 1] = "M.RED", +[16][0x21 - 1] = "Shenzhen Damay Semiconductor Co Ltd", +[16][0x22 - 1] = "Corelab Tech Singapore Holding PTE LTD", +[16][0x23 - 1] = "EmBestor Technology Inc", +[16][0x24 - 1] = "XConn Technologies", +[16][0x25 - 1] = "Flagchip", +[16][0x26 - 1] = "CUNNUC", +[16][0x27 - 1] = "SGMicro", +[16][0x28 - 1] = "Lanxin Computing (Shenzhen) Technology", +[16][0x29 - 1] = "FuturePlus Systems LLC", +[16][0x2a - 1] = "Shenzhen Jielong Storage Technology Co", +[16][0x2b - 1] = "Precision Planting LLC", +[16][0x2c - 1] = "Sichuan ZeroneStor Microelectronics Tech", +[16][0x2d - 1] = "The University of Tokyo", +[16][0x2e - 1] = "Aodu (Fujian) Information Technology Co", +[16][0x2f - 1] = "Bytera Memory Inc", +[16][0x30 - 1] = "XSemitron Technology Inc", +[16][0x31 - 1] = "Cloud Ridge Ltd", +[16][0x32 - 1] = "Shenzhen XinChiTai Technology Co Ltd", +[16][0x33 - 1] = "Shenzhen Xinxin Semiconductor Co Ltd", +[16][0x34 - 1] = "Shenzhen ShineKing Electronics Co Ltd.", +[16][0x35 - 1] = "Shenzhen Shande Semiconductor Co. Ltd.", +[16][0x36 - 1] = "AheadComputing", +[16][0x37 - 1] = "Beijing Ronghua Kangweiye Technology", +[16][0x38 - 1] = "Shanghai Yunsilicon Technology Co Ltd", +[16][0x39 - 1] = "Shenzhen Wolongtai Technology Co Ltd.", +[16][0x3a - 1] = "Vervesemi Microelectronics", /* EOF */ diff --git a/src/helper/jim-nvp.c b/src/helper/jim-nvp.c index 0e76f96deb..cdd4d34291 100644 --- a/src/helper/jim-nvp.c +++ b/src/helper/jim-nvp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: BSD-2-Clause-Views */ +// SPDX-License-Identifier: BSD-2-Clause-Views /* Jim - A small embeddable Tcl interpreter * @@ -21,6 +21,7 @@ #endif #include "jim-nvp.h" +#include <stdio.h> #include <string.h> int jim_get_nvp(Jim_Interp *interp, diff --git a/src/helper/jim-nvp.h b/src/helper/jim-nvp.h index 11824cabf4..45af6c867f 100644 --- a/src/helper/jim-nvp.h +++ b/src/helper/jim-nvp.h @@ -19,6 +19,7 @@ #ifndef OPENOCD_HELPER_JIM_NVP_H #define OPENOCD_HELPER_JIM_NVP_H +#include <stdbool.h> #include <jim.h> /** Name Value Pairs, aka: NVP @@ -136,7 +137,7 @@ struct jim_getopt_info { Jim_Interp *interp; int argc; Jim_Obj *const *argv; - int isconfigure; /* non-zero if configure */ + bool is_configure; }; /** GetOpt - how to. diff --git a/src/helper/list.h b/src/helper/list.h index 552a3202a5..89b8468ec4 100644 --- a/src/helper/list.h +++ b/src/helper/list.h @@ -1,15 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* - * The content of this file is mainly copied/inspired from Linux kernel - * code in include/linux/list.h, include/linux/types.h - * Last aligned with kernel v5.12: - * - skip the functions hlist_unhashed_lockless() and __list_del_clearprev() - * that are relevant only in kernel; - * - Remove non-standard GCC extension "omitted conditional operand" from - * list_prepare_entry; - * - expand READ_ONCE, WRITE_ONCE, smp_load_acquire, smp_store_release; - * - make comments compatible with doxygen. + * Copyright (c) 2010 Isilon Systems, Inc. + * Copyright (c) 2010 iX Systems, Inc. + * Copyright (c) 2010 Panasas, Inc. + * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. + * Copyright (c) 2021-2024 by Antonio Borneo <borneo.antonio@gmail.com> + * All rights reserved. + */ + +/* + * Circular doubly linked list implementation. + * + * The content of this file is mainly copied/inspired from FreeBSD code in: + * https://cgit.freebsd.org/src/tree/ + * files: + * sys/compat/linuxkpi/common/include/linux/list.h + * sys/compat/linuxkpi/common/include/linux/types.h + * + * Last aligned with release/13.3.0: + * + * - Skip 'hlist_*' double linked lists with a single pointer list head. + * - Expand WRITE_ONCE(). + * - Use TAB for indentation. + * - Put macro arguments within parenthesis. + * - Remove blank lines after an open brace '{'. + * - Remove multiple assignment. * * There is an example of using this file in contrib/list_example.c. */ @@ -17,162 +33,65 @@ #ifndef OPENOCD_HELPER_LIST_H #define OPENOCD_HELPER_LIST_H -/* begin local changes */ -#include <helper/types.h> +/* begin OpenOCD changes */ -#define LIST_POISON1 NULL -#define LIST_POISON2 NULL +#include <assert.h> +#include <stddef.h> struct list_head { - struct list_head *next, *prev; -}; - -struct hlist_head { - struct hlist_node *first; + struct list_head *next; + struct list_head *prev; }; -struct hlist_node { - struct hlist_node *next, **pprev; -}; -/* end local changes */ - -/* - * Circular doubly linked list implementation. - * - * Some of the internal functions ("__xxx") are useful when - * manipulating whole lists rather than single entries, as - * sometimes we already know the next/prev entries and we can - * generate better code by using them directly rather than - * using the generic single-entry routines. - */ +/* end OpenOCD changes */ #define LIST_HEAD_INIT(name) { &(name), &(name) } -#define LIST_HEAD(name) \ +#define OOCD_LIST_HEAD(name) \ struct list_head name = LIST_HEAD_INIT(name) -/** - * INIT_LIST_HEAD - Initialize a list_head structure - * @param list list_head structure to be initialized. - * - * Initializes the list_head to point to itself. If it is a list header, - * the result is an empty list. - */ -static inline void INIT_LIST_HEAD(struct list_head *list) +static inline void +INIT_LIST_HEAD(struct list_head *list) { list->next = list; list->prev = list; } -#ifdef CONFIG_DEBUG_LIST -extern bool __list_add_valid(struct list_head *new, - struct list_head *prev, - struct list_head *next); -extern bool __list_del_entry_valid(struct list_head *entry); -#else -static inline bool __list_add_valid(struct list_head *new, - struct list_head *prev, - struct list_head *next) +static inline int +list_empty(const struct list_head *head) { - return true; + return (head->next == head); } -static inline bool __list_del_entry_valid(struct list_head *entry) -{ - return true; -} -#endif -/* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next) +static inline int +list_empty_careful(const struct list_head *head) { - if (!__list_add_valid(new, prev, next)) - return; - - next->prev = new; - new->next = next; - new->prev = prev; - prev->next = new; -} - -/** - * list_add - add a new entry - * @param new new entry to be added - * @param head list head to add it after - * - * Insert a new entry after the specified head. - * This is good for implementing stacks. - */ -static inline void list_add(struct list_head *new, struct list_head *head) -{ - __list_add(new, head, head->next); -} - + struct list_head *next = head->next; -/** - * list_add_tail - add a new entry - * @param new new entry to be added - * @param head list head to add it before - * - * Insert a new entry before the specified head. - * This is useful for implementing queues. - */ -static inline void list_add_tail(struct list_head *new, struct list_head *head) -{ - __list_add(new, head->prev, head); + return ((next == head) && (next == head->prev)); } -/* - * Delete a list entry by making the prev/next entries - * point to each other. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_del(struct list_head *prev, struct list_head *next) +static inline void +__list_del(struct list_head *prev, struct list_head *next) { next->prev = prev; prev->next = next; } -/* Ignore kernel __list_del_clearprev() */ - -static inline void __list_del_entry(struct list_head *entry) +static inline void +__list_del_entry(struct list_head *entry) { - if (!__list_del_entry_valid(entry)) - return; - __list_del(entry->prev, entry->next); } -/** - * list_del - deletes entry from list. - * @param entry the element to delete from the list. - * Note: list_empty() on entry does not return true after this, the entry is - * in an undefined state. - */ -static inline void list_del(struct list_head *entry) +static inline void +list_del(struct list_head *entry) { - __list_del_entry(entry); - entry->next = LIST_POISON1; - entry->prev = LIST_POISON2; + __list_del(entry->prev, entry->next); } -/** - * list_replace - replace old entry by new one - * @param old the element to be replaced - * @param new the new element to insert - * - * If @a old was empty, it will be overwritten. - */ -static inline void list_replace(struct list_head *old, - struct list_head *new) +static inline void +list_replace(struct list_head *old, struct list_head *new) { new->next = old->next; new->next->prev = new; @@ -180,197 +99,192 @@ static inline void list_replace(struct list_head *old, new->prev->next = new; } -/** - * list_replace_init - replace old entry by new one and initialize the old one - * @param old the element to be replaced - * @param new the new element to insert - * - * If @a old was empty, it will be overwritten. - */ -static inline void list_replace_init(struct list_head *old, - struct list_head *new) +static inline void +list_replace_init(struct list_head *old, struct list_head *new) { list_replace(old, new); INIT_LIST_HEAD(old); } -/** - * list_swap - replace entry1 with entry2 and re-add entry1 at entry2's position - * @param entry1 the location to place entry2 - * @param entry2 the location to place entry1 - */ -static inline void list_swap(struct list_head *entry1, - struct list_head *entry2) +static inline void +linux_list_add(struct list_head *new, struct list_head *prev, + struct list_head *next) { - struct list_head *pos = entry2->prev; + assert(next); + assert(prev); - list_del(entry2); - list_replace(entry1, entry2); - if (pos == entry1) - pos = entry2; - list_add(entry1, pos); + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; } -/** - * list_del_init - deletes entry from list and reinitialize it. - * @param entry the element to delete from the list. - */ -static inline void list_del_init(struct list_head *entry) +static inline void +list_del_init(struct list_head *entry) { - __list_del_entry(entry); + list_del(entry); INIT_LIST_HEAD(entry); } -/** - * list_move - delete from one list and add as another's head - * @param list the entry to move - * @param head the head that will precede our entry - */ -static inline void list_move(struct list_head *list, struct list_head *head) +#define list_entry(ptr, type, field) container_of(ptr, type, field) + +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +#define list_last_entry(ptr, type, member) \ + list_entry((ptr)->prev, type, member) + +#define list_first_entry_or_null(ptr, type, member) \ + (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) + +#define list_next_entry(ptr, member) \ + list_entry(((ptr)->member.next), typeof(*(ptr)), member) + +#define list_safe_reset_next(ptr, n, member) \ + (n) = list_next_entry(ptr, member) + +#define list_prev_entry(ptr, member) \ + list_entry(((ptr)->member.prev), typeof(*(ptr)), member) + +#define list_for_each(p, head) \ + for (p = (head)->next; p != (head); p = (p)->next) + +#define list_for_each_safe(p, n, head) \ + for (p = (head)->next, n = (p)->next; p != (head); p = n, n = (p)->next) + +#define list_for_each_entry(p, h, field) \ + for (p = list_entry((h)->next, typeof(*p), field); &(p)->field != (h); \ + p = list_entry((p)->field.next, typeof(*p), field)) + +#define list_for_each_entry_safe(p, n, h, field) \ + for (p = list_entry((h)->next, typeof(*p), field), \ + n = list_entry((p)->field.next, typeof(*p), field); &(p)->field != (h);\ + p = n, n = list_entry(n->field.next, typeof(*n), field)) + +#define list_for_each_entry_from(p, h, field) \ + for ( ; &(p)->field != (h); \ + p = list_entry((p)->field.next, typeof(*p), field)) + +#define list_for_each_entry_continue(p, h, field) \ + for (p = list_next_entry((p), field); &(p)->field != (h); \ + p = list_next_entry((p), field)) + +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry((pos)->member.next, typeof(*pos), member); \ + &(pos)->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +#define list_for_each_entry_reverse(p, h, field) \ + for (p = list_entry((h)->prev, typeof(*p), field); &(p)->field != (h); \ + p = list_entry((p)->field.prev, typeof(*p), field)) + +#define list_for_each_entry_safe_reverse(p, n, h, field) \ + for (p = list_entry((h)->prev, typeof(*p), field), \ + n = list_entry((p)->field.prev, typeof(*p), field); &(p)->field != (h); \ + p = n, n = list_entry(n->field.prev, typeof(*n), field)) + +#define list_for_each_entry_continue_reverse(p, h, field) \ + for (p = list_entry((p)->field.prev, typeof(*p), field); &(p)->field != (h); \ + p = list_entry((p)->field.prev, typeof(*p), field)) + +#define list_for_each_prev(p, h) for (p = (h)->prev; p != (h); p = (p)->prev) + +#define list_for_each_entry_from_reverse(p, h, field) \ + for (; &p->field != (h); \ + p = list_prev_entry(p, field)) + +static inline void +list_add(struct list_head *new, struct list_head *head) { - __list_del_entry(list); + linux_list_add(new, head, head->next); +} + +static inline void +list_add_tail(struct list_head *new, struct list_head *head) +{ + linux_list_add(new, head->prev, head); +} + +static inline void +list_move(struct list_head *list, struct list_head *head) +{ + list_del(list); list_add(list, head); } -/** - * list_move_tail - delete from one list and add as another's tail - * @param list the entry to move - * @param head the head that will follow our entry - */ -static inline void list_move_tail(struct list_head *list, - struct list_head *head) +static inline void +list_move_tail(struct list_head *entry, struct list_head *head) { - __list_del_entry(list); - list_add_tail(list, head); + list_del(entry); + list_add_tail(entry, head); } -/** - * list_bulk_move_tail - move a subsection of a list to its tail - * @param head the head that will follow our entry - * @param first the first entry to move - * @param last the last entry to move, can be the same as first - * - * Move all entries between @a first and including @a last before @a head. - * All three entries must belong to the same linked list. - */ -static inline void list_bulk_move_tail(struct list_head *head, - struct list_head *first, - struct list_head *last) +static inline void +list_rotate_to_front(struct list_head *entry, struct list_head *head) +{ + list_move_tail(entry, head); +} + +static inline void +list_bulk_move_tail(struct list_head *head, struct list_head *first, + struct list_head *last) { first->prev->next = last->next; last->next->prev = first->prev; - head->prev->next = first; first->prev = head->prev; - last->next = head; head->prev = last; } -/** - * list_is_first -- tests whether @a list is the first entry in list @a head - * @param list the entry to test - * @param head the head of the list - */ -static inline int list_is_first(const struct list_head *list, - const struct list_head *head) +static inline void +linux_list_splice(const struct list_head *list, struct list_head *prev, + struct list_head *next) { - return list->prev == head; -} + struct list_head *first; + struct list_head *last; -/** - * list_is_last - tests whether @a list is the last entry in list @a head - * @param list the entry to test - * @param head the head of the list - */ -static inline int list_is_last(const struct list_head *list, - const struct list_head *head) -{ - return list->next == head; + if (list_empty(list)) + return; + first = list->next; + last = list->prev; + first->prev = prev; + prev->next = first; + last->next = next; + next->prev = last; } -/** - * list_empty - tests whether a list is empty - * @param head the list to test. - */ -static inline int list_empty(const struct list_head *head) +static inline void +list_splice(const struct list_head *list, struct list_head *head) { - return head->next == head; + linux_list_splice(list, head, head->next); } -/** - * list_del_init_careful - deletes entry from list and reinitialize it. - * @param entry the element to delete from the list. - * - * This is the same as list_del_init(), except designed to be used - * together with list_empty_careful() in a way to guarantee ordering - * of other memory operations. - * - * Any memory operations done before a list_del_init_careful() are - * guaranteed to be visible after a list_empty_careful() test. - */ -static inline void list_del_init_careful(struct list_head *entry) +static inline void +list_splice_tail(struct list_head *list, struct list_head *head) { - __list_del_entry(entry); - entry->prev = entry; - entry->next = entry; + linux_list_splice(list, head->prev, head); } -/** - * list_empty_careful - tests whether a list is empty and not being modified - * @param head the list to test - * - * Description: - * tests whether a list is empty _and_ checks that no other CPU might be - * in the process of modifying either member (next or prev) - * - * NOTE: using list_empty_careful() without synchronization - * can only be safe if the only activity that can happen - * to the list entry is list_del_init(). Eg. it cannot be used - * if another CPU could re-list_add() it. - */ -static inline int list_empty_careful(const struct list_head *head) +static inline void +list_splice_init(struct list_head *list, struct list_head *head) { - struct list_head *next = head->next; - return (next == head) && (next == head->prev); + linux_list_splice(list, head, head->next); + INIT_LIST_HEAD(list); } -/** - * list_rotate_left - rotate the list to the left - * @param head the head of the list - */ -static inline void list_rotate_left(struct list_head *head) +static inline void +list_splice_tail_init(struct list_head *list, struct list_head *head) { - struct list_head *first; - - if (!list_empty(head)) { - first = head->next; - list_move_tail(first, head); - } + linux_list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); } -/** - * list_rotate_to_front() - Rotate list to specific item. - * @param list The desired new front of the list. - * @param head The head of the list. - * - * Rotates list so that @a list becomes the new front of the list. +/* + * Double linked lists with a single pointer list head. + * IGNORED */ -static inline void list_rotate_to_front(struct list_head *list, - struct list_head *head) -{ - /* - * Deletes the list head from the list denoted by @a head and - * places it as the tail of @a list, this effectively rotates the - * list so that @a list is at the front. - */ - list_move_tail(head, list); -} -/** - * list_is_singular - tests whether a list has just one entry. - * @param head the list to test. - */ static inline int list_is_singular(const struct list_head *head) { return !list_empty(head) && (head->next == head->prev); @@ -388,20 +302,6 @@ static inline void __list_cut_position(struct list_head *list, new_first->prev = head; } -/** - * list_cut_position - cut a list into two - * @param list a new list to add all removed entries - * @param head a list with entries - * @param entry an entry within head, could be the head itself - * and if so we won't cut the list - * - * This helper moves the initial part of @a head, up to and - * including @a entry, from @a head to @a list. You should - * pass on @a entry an element you know is on @a head. @a list - * should be an empty list or a list you do not care about - * losing its data. - * - */ static inline void list_cut_position(struct list_head *list, struct list_head *head, struct list_head *entry) { @@ -416,632 +316,65 @@ static inline void list_cut_position(struct list_head *list, __list_cut_position(list, head, entry); } -/** - * list_cut_before - cut a list into two, before given entry - * @param list a new list to add all removed entries - * @param head a list with entries - * @param entry an entry within head, could be the head itself - * - * This helper moves the initial part of @a head, up to but - * excluding @a entry, from @a head to @a list. You should pass - * in @a entry an element you know is on @a head. @a list should - * be an empty list or a list you do not care about losing - * its data. - * If @a entry == @a head, all entries on @a head are moved to - * @a list. - */ -static inline void list_cut_before(struct list_head *list, - struct list_head *head, - struct list_head *entry) -{ - if (head->next == entry) { - INIT_LIST_HEAD(list); - return; - } - list->next = head->next; - list->next->prev = list; - list->prev = entry->prev; - list->prev->next = list; - head->next = entry; - entry->prev = head; -} - -static inline void __list_splice(const struct list_head *list, - struct list_head *prev, - struct list_head *next) +static inline int list_is_first(const struct list_head *list, + const struct list_head *head) { - struct list_head *first = list->next; - struct list_head *last = list->prev; - - first->prev = prev; - prev->next = first; - - last->next = next; - next->prev = last; + return (list->prev == head); } -/** - * list_splice - join two lists, this is designed for stacks - * @param list the new list to add. - * @param head the place to add it in the first list. - */ -static inline void list_splice(const struct list_head *list, - struct list_head *head) +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) { - if (!list_empty(list)) - __list_splice(list, head, head->next); + return list->next == head; } -/** - * list_splice_tail - join two lists, each list being a queue - * @param list the new list to add. - * @param head the place to add it in the first list. - */ -static inline void list_splice_tail(struct list_head *list, - struct list_head *head) +static inline size_t +list_count_nodes(const struct list_head *list) { - if (!list_empty(list)) - __list_splice(list, head->prev, head); -} + const struct list_head *lh; + size_t count; -/** - * list_splice_init - join two lists and reinitialise the emptied list. - * @param list the new list to add. - * @param head the place to add it in the first list. - * - * The list at @a list is reinitialised - */ -static inline void list_splice_init(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) { - __list_splice(list, head, head->next); - INIT_LIST_HEAD(list); + count = 0; + list_for_each(lh, list) { + count++; } -} -/** - * list_splice_tail_init - join two lists and reinitialise the emptied list - * @param list the new list to add. - * @param head the place to add it in the first list. - * - * Each of the lists is a queue. - * The list at @a list is reinitialised - */ -static inline void list_splice_tail_init(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) { - __list_splice(list, head->prev, head); - INIT_LIST_HEAD(list); - } + return (count); } -/** - * list_entry - get the struct for this entry - * @param ptr the &struct list_head pointer. - * @param type the type of the struct this is embedded in. - * @param member the name of the list_head within the struct. - */ -#define list_entry(ptr, type, member) \ - container_of(ptr, type, member) - -/** - * list_first_entry - get the first element from a list - * @param ptr the list head to take the element from. - * @param type the type of the struct this is embedded in. - * @param member the name of the list_head within the struct. - * - * Note, that list is expected to be not empty. - */ -#define list_first_entry(ptr, type, member) \ - list_entry((ptr)->next, type, member) - -/** - * list_last_entry - get the last element from a list - * @param ptr the list head to take the element from. - * @param type the type of the struct this is embedded in. - * @param member the name of the list_head within the struct. - * - * Note, that list is expected to be not empty. - */ -#define list_last_entry(ptr, type, member) \ - list_entry((ptr)->prev, type, member) - -/** - * list_first_entry_or_null - get the first element from a list - * @param ptr the list head to take the element from. - * @param type the type of the struct this is embedded in. - * @param member the name of the list_head within the struct. - * - * Note that if the list is empty, it returns NULL. - */ -#define list_first_entry_or_null(ptr, type, member) ({ \ - struct list_head *head__ = (ptr); \ - struct list_head *pos__ = head__->next; \ - pos__ != head__ ? list_entry(pos__, type, member) : NULL; \ -}) - -/** - * list_next_entry - get the next element in list - * @param pos the type * to cursor - * @param member the name of the list_head within the struct. - */ -#define list_next_entry(pos, member) \ - list_entry((pos)->member.next, typeof(*(pos)), member) - -/** - * list_prev_entry - get the prev element in list - * @param pos the type * to cursor - * @param member the name of the list_head within the struct. - */ -#define list_prev_entry(pos, member) \ - list_entry((pos)->member.prev, typeof(*(pos)), member) - -/** - * list_for_each - iterate over a list - * @param pos the &struct list_head to use as a loop cursor. - * @param head the head for your list. - */ -#define list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) - -/** - * list_for_each_continue - continue iteration over a list - * @param pos the &struct list_head to use as a loop cursor. - * @param head the head for your list. - * - * Continue to iterate over a list, continuing after the current position. - */ -#define list_for_each_continue(pos, head) \ - for (pos = pos->next; pos != (head); pos = pos->next) - -/** - * list_for_each_prev - iterate over a list backwards - * @param pos the &struct list_head to use as a loop cursor. - * @param head the head for your list. - */ -#define list_for_each_prev(pos, head) \ - for (pos = (head)->prev; pos != (head); pos = pos->prev) - -/** - * list_for_each_safe - iterate over a list safe against removal of list entry - * @param pos the &struct list_head to use as a loop cursor. - * @param n another &struct list_head to use as temporary storage - * @param head the head for your list. - */ -#define list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - -/** - * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry - * @param pos the &struct list_head to use as a loop cursor. - * @param n another &struct list_head to use as temporary storage - * @param head the head for your list. - */ -#define list_for_each_prev_safe(pos, n, head) \ - for (pos = (head)->prev, n = pos->prev; \ - pos != (head); \ - pos = n, n = pos->prev) - -/** - * list_entry_is_head - test if the entry points to the head of the list - * @param pos the type * to cursor - * @param head the head for your list. - * @param member the name of the list_head within the struct. - */ -#define list_entry_is_head(pos, head, member) \ - (&pos->member == (head)) - -/** - * list_for_each_entry - iterate over list of given type - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - */ -#define list_for_each_entry(pos, head, member) \ - for (pos = list_first_entry(head, typeof(*pos), member); \ - !list_entry_is_head(pos, head, member); \ - pos = list_next_entry(pos, member)) - -/** - * list_for_each_entry_reverse - iterate backwards over list of given type. - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - */ -#define list_for_each_entry_reverse(pos, head, member) \ - for (pos = list_last_entry(head, typeof(*pos), member); \ - !list_entry_is_head(pos, head, member); \ - pos = list_prev_entry(pos, member)) - -/** - * list_for_each_entry_direction - iterate forward/backward over list of given type - * @param forward the iterate direction, true for forward, false for backward. - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - */ -#define list_for_each_entry_direction(forward, pos, head, member) \ - for (pos = forward ? list_first_entry(head, typeof(*pos), member) \ - : list_last_entry(head, typeof(*pos), member); \ - !list_entry_is_head(pos, head, member); \ - pos = forward ? list_next_entry(pos, member) \ - : list_prev_entry(pos, member)) - -/** - * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() - * @param pos the type * to use as a start point - * @param head the head of the list - * @param member the name of the list_head within the struct. - * - * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). - */ -#define list_prepare_entry(pos, head, member) \ - ((pos) ? (pos) : list_entry(head, typeof(*pos), member)) - -/** - * list_for_each_entry_continue - continue iteration over list of given type - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Continue to iterate over list of given type, continuing after - * the current position. - */ -#define list_for_each_entry_continue(pos, head, member) \ - for (pos = list_next_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = list_next_entry(pos, member)) - -/** - * list_for_each_entry_continue_reverse - iterate backwards from the given point - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Start to iterate over list of given type backwards, continuing after - * the current position. - */ -#define list_for_each_entry_continue_reverse(pos, head, member) \ - for (pos = list_prev_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = list_prev_entry(pos, member)) - -/** - * list_for_each_entry_from - iterate over list of given type from the current point - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Iterate over list of given type, continuing from current position. - */ -#define list_for_each_entry_from(pos, head, member) \ - for (; !list_entry_is_head(pos, head, member); \ - pos = list_next_entry(pos, member)) - -/** - * list_for_each_entry_from_reverse - iterate backwards over list of given type - * from the current point - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Iterate backwards over list of given type, continuing from current position. - */ -#define list_for_each_entry_from_reverse(pos, head, member) \ - for (; !list_entry_is_head(pos, head, member); \ - pos = list_prev_entry(pos, member)) - -/** - * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @param pos the type * to use as a loop cursor. - * @param n another type * to use as temporary storage - * @param head the head for your list. - * @param member the name of the list_head within the struct. - */ -#define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = list_first_entry(head, typeof(*pos), member), \ - n = list_next_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = n, n = list_next_entry(n, member)) - -/** - * list_for_each_entry_safe_continue - continue list iteration safe against removal - * @param pos the type * to use as a loop cursor. - * @param n another type * to use as temporary storage - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Iterate over list of given type, continuing after current point, - * safe against removal of list entry. - */ -#define list_for_each_entry_safe_continue(pos, n, head, member) \ - for (pos = list_next_entry(pos, member), \ - n = list_next_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = n, n = list_next_entry(n, member)) - -/** - * list_for_each_entry_safe_from - iterate over list from current point safe against removal - * @param pos the type * to use as a loop cursor. - * @param n another type * to use as temporary storage - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Iterate over list of given type from current point, safe against - * removal of list entry. - */ -#define list_for_each_entry_safe_from(pos, n, head, member) \ - for (n = list_next_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = n, n = list_next_entry(n, member)) - -/** - * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal - * @param pos the type * to use as a loop cursor. - * @param n another type * to use as temporary storage - * @param head the head for your list. - * @param member the name of the list_head within the struct. - * - * Iterate backwards over list of given type, safe against removal - * of list entry. - */ -#define list_for_each_entry_safe_reverse(pos, n, head, member) \ - for (pos = list_last_entry(head, typeof(*pos), member), \ - n = list_prev_entry(pos, member); \ - !list_entry_is_head(pos, head, member); \ - pos = n, n = list_prev_entry(n, member)) - -/** - * list_safe_reset_next - reset a stale list_for_each_entry_safe loop - * @param pos the loop cursor used in the list_for_each_entry_safe loop - * @param n temporary storage used in list_for_each_entry_safe - * @param member the name of the list_head within the struct. - * - * list_safe_reset_next is not safe to use in general if the list may be - * modified concurrently (eg. the lock is dropped in the loop body). An - * exception to this is if the cursor element (pos) is pinned in the list, - * and list_safe_reset_next is called after re-taking the lock and before - * completing the current iteration of the loop body. - */ -#define list_safe_reset_next(pos, n, member) \ - n = list_next_entry(pos, member) - /* * Double linked lists with a single pointer list head. - * Mostly useful for hash tables where the two pointer list head is - * too wasteful. - * You lose the ability to access the tail in O(1). + * IGNORED */ -#define HLIST_HEAD_INIT { .first = NULL } -#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } -#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) -static inline void INIT_HLIST_NODE(struct hlist_node *h) -{ - h->next = NULL; - h->pprev = NULL; -} +/* begin OpenOCD extensions */ /** - * hlist_unhashed - Has node been removed from list and reinitialized? - * @param h Node to be checked - * - * Not that not all removal functions will leave a node in unhashed - * state. For example, hlist_nulls_del_init_rcu() does leave the - * node in unhashed state, but hlist_nulls_del() does not. + * list_for_each_entry_direction - iterate forward/backward over list of given type + * @param is_fwd the iterate direction, true for forward, false for backward. + * @param p the type * to use as a loop cursor. + * @param h the head of the list. + * @param field the name of the list_head within the struct. */ -static inline int hlist_unhashed(const struct hlist_node *h) -{ - return !h->pprev; -} - -/* Ignore kernel hlist_unhashed_lockless() */ +#define list_for_each_entry_direction(is_fwd, p, h, field) \ + for (p = list_entry(is_fwd ? (h)->next : (h)->prev, typeof(*p), field); \ + &(p)->field != (h); \ + p = list_entry(is_fwd ? (p)->field.next : (p)->field.prev, typeof(*p), field)) /** - * hlist_empty - Is the specified hlist_head structure an empty hlist? - * @param h Structure to check. - */ -static inline int hlist_empty(const struct hlist_head *h) -{ - return !h->first; -} - -static inline void __hlist_del(struct hlist_node *n) -{ - struct hlist_node *next = n->next; - struct hlist_node **pprev = n->pprev; - - *pprev = next; - if (next) - next->pprev = pprev; -} - -/** - * hlist_del - Delete the specified hlist_node from its list - * @param n Node to delete. - * - * Note that this function leaves the node in hashed state. Use - * hlist_del_init() or similar instead to unhash @a n. + * list_rotate_left - rotate the list to the left + * @param h the head of the list */ -static inline void hlist_del(struct hlist_node *n) +static inline void list_rotate_left(struct list_head *h) { - __hlist_del(n); - n->next = LIST_POISON1; - n->pprev = LIST_POISON2; -} + struct list_head *first; -/** - * hlist_del_init - Delete the specified hlist_node from its list and initialize - * @param n Node to delete. - * - * Note that this function leaves the node in unhashed state. - */ -static inline void hlist_del_init(struct hlist_node *n) -{ - if (!hlist_unhashed(n)) { - __hlist_del(n); - INIT_HLIST_NODE(n); + if (!list_empty(h)) { + first = h->next; + list_move_tail(first, h); } } -/** - * hlist_add_head - add a new entry at the beginning of the hlist - * @param n new entry to be added - * @param h hlist head to add it after - * - * Insert a new entry after the specified head. - * This is good for implementing stacks. - */ -static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) -{ - struct hlist_node *first = h->first; - n->next = first; - if (first) - first->pprev = &n->next; - h->first = n; - n->pprev = &h->first; -} - -/** - * hlist_add_before - add a new entry before the one specified - * @param n new entry to be added - * @param next hlist node to add it before, which must be non-NULL - */ -static inline void hlist_add_before(struct hlist_node *n, - struct hlist_node *next) -{ - n->pprev = next->pprev; - n->next = next; - next->pprev = &n->next; - *(n->pprev) = n; -} - -/** - * hlist_add_behind - add a new entry after the one specified - * @param n new entry to be added - * @param prev hlist node to add it after, which must be non-NULL - */ -static inline void hlist_add_behind(struct hlist_node *n, - struct hlist_node *prev) -{ - n->next = prev->next; - prev->next = n; - n->pprev = &prev->next; - - if (n->next) - n->next->pprev = &n->next; -} - -/** - * hlist_add_fake - create a fake hlist consisting of a single headless node - * @param n Node to make a fake list out of - * - * This makes @a n appear to be its own predecessor on a headless hlist. - * The point of this is to allow things like hlist_del() to work correctly - * in cases where there is no list. - */ -static inline void hlist_add_fake(struct hlist_node *n) -{ - n->pprev = &n->next; -} - -/** - * hlist_fake: Is this node a fake hlist? - * @param h Node to check for being a self-referential fake hlist. - */ -static inline bool hlist_fake(struct hlist_node *h) -{ - return h->pprev == &h->next; -} - -/** - * hlist_is_singular_node - is node the only element of the specified hlist? - * @param n Node to check for singularity. - * @param h Header for potentially singular list. - * - * Check whether the node is the only node of the head without - * accessing head, thus avoiding unnecessary cache misses. - */ -static inline bool -hlist_is_singular_node(struct hlist_node *n, struct hlist_head *h) -{ - return !n->next && n->pprev == &h->first; -} - -/** - * hlist_move_list - Move an hlist - * @param old hlist_head for old list. - * @param new hlist_head for new list. - * - * Move a list from one list head to another. Fixup the pprev - * reference of the first entry if it exists. - */ -static inline void hlist_move_list(struct hlist_head *old, - struct hlist_head *new) -{ - new->first = old->first; - if (new->first) - new->first->pprev = &new->first; - old->first = NULL; -} - -#define hlist_entry(ptr, type, member) container_of(ptr, type, member) - -#define hlist_for_each(pos, head) \ - for (pos = (head)->first; pos ; pos = pos->next) - -#define hlist_for_each_safe(pos, n, head) \ - for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ - pos = n) - -#define hlist_entry_safe(ptr, type, member) \ - ({ typeof(ptr) ____ptr = (ptr); \ - ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ - }) - -/** - * hlist_for_each_entry - iterate over list of given type - * @param pos the type * to use as a loop cursor. - * @param head the head for your list. - * @param member the name of the hlist_node within the struct. - */ -#define hlist_for_each_entry(pos, head, member) \ - for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member);\ - pos; \ - pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) - -/** - * hlist_for_each_entry_continue - iterate over a hlist continuing after current point - * @param pos the type * to use as a loop cursor. - * @param member the name of the hlist_node within the struct. - */ -#define hlist_for_each_entry_continue(pos, member) \ - for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\ - pos; \ - pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) - -/** - * hlist_for_each_entry_from - iterate over a hlist continuing from current point - * @param pos the type * to use as a loop cursor. - * @param member the name of the hlist_node within the struct. - */ -#define hlist_for_each_entry_from(pos, member) \ - for (; pos; \ - pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) - -/** - * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @param pos the type * to use as a loop cursor. - * @param n a &struct hlist_node to use as temporary storage - * @param head the head for your list. - * @param member the name of the hlist_node within the struct. - */ -#define hlist_for_each_entry_safe(pos, n, head, member) \ - for (pos = hlist_entry_safe((head)->first, typeof(*pos), member);\ - pos && ({ n = pos->member.next; 1; }); \ - pos = hlist_entry_safe(n, typeof(*pos), member)) +/* end OpenOCD extensions */ #endif /* OPENOCD_HELPER_LIST_H */ diff --git a/src/helper/log.c b/src/helper/log.c index f3872b5411..8f7ab00397 100644 --- a/src/helper/log.c +++ b/src/helper/log.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -19,6 +19,7 @@ #include "command.h" #include "replacements.h" #include "time_support.h" +#include <server/gdb_server.h> #include <server/server.h> #include <stdarg.h> @@ -29,6 +30,18 @@ #else #error "malloc.h is required to use --enable-malloc-logging" #endif + +#ifdef __GLIBC__ +#if __GLIBC_PREREQ(2, 33) +#define FORDBLKS_FORMAT " %zu" +#else +/* glibc older than 2.33 (2021-02-01) use mallinfo(). Overwrite it */ +#define mallinfo2 mallinfo +#define FORDBLKS_FORMAT " %d" +#endif +#else +#error "GNU glibc is required to use --enable-malloc-logging" +#endif #endif int debug_level = LOG_LVL_INFO; @@ -52,7 +65,7 @@ static const char * const log_strings[6] = { static int count; /* forward the log to the listeners */ -static void log_forward(const char *file, unsigned line, const char *function, const char *string) +static void log_forward(const char *file, unsigned int line, const char *function, const char *string) { struct log_callback *cb, *next; cb = log_callbacks; @@ -104,12 +117,11 @@ static void log_puts(enum log_levels level, /* print with count and time information */ int64_t t = timeval_ms() - start; #ifdef _DEBUG_FREE_SPACE_ - struct mallinfo info; - info = mallinfo(); + struct mallinfo2 info = mallinfo2(); #endif fprintf(log_output, "%s%d %" PRId64 " %s:%d %s()" #ifdef _DEBUG_FREE_SPACE_ - " %d" + FORDBLKS_FORMAT #endif ": %s", log_strings[level + 1], count, t, file, line, function, #ifdef _DEBUG_FREE_SPACE_ @@ -132,7 +144,7 @@ static void log_puts(enum log_levels level, void log_printf(enum log_levels level, const char *file, - unsigned line, + unsigned int line, const char *function, const char *format, ...) @@ -155,7 +167,7 @@ void log_printf(enum log_levels level, va_end(ap); } -void log_vprintf_lf(enum log_levels level, const char *file, unsigned line, +void log_vprintf_lf(enum log_levels level, const char *file, unsigned int line, const char *function, const char *format, va_list args) { char *tmp; @@ -181,7 +193,7 @@ void log_vprintf_lf(enum log_levels level, const char *file, unsigned line, void log_printf_lf(enum log_levels level, const char *file, - unsigned line, + unsigned int line, const char *function, const char *format, ...) @@ -213,31 +225,28 @@ COMMAND_HANDLER(handle_debug_level_command) COMMAND_HANDLER(handle_log_output_command) { - if (CMD_ARGC == 0 || (CMD_ARGC == 1 && strcmp(CMD_ARGV[0], "default") == 0)) { - if (log_output != stderr && log_output) { - /* Close previous log file, if it was open and wasn't stderr. */ - fclose(log_output); - } - log_output = stderr; - LOG_DEBUG("set log_output to default"); - return ERROR_OK; - } - if (CMD_ARGC == 1) { - FILE *file = fopen(CMD_ARGV[0], "w"); + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + FILE *file; + if (CMD_ARGC == 1 && strcmp(CMD_ARGV[0], "default") != 0) { + file = fopen(CMD_ARGV[0], "w"); if (!file) { - LOG_ERROR("failed to open output log '%s'", CMD_ARGV[0]); + command_print(CMD, "failed to open output log \"%s\"", CMD_ARGV[0]); return ERROR_FAIL; } - if (log_output != stderr && log_output) { - /* Close previous log file, if it was open and wasn't stderr. */ - fclose(log_output); - } - log_output = file; - LOG_DEBUG("set log_output to \"%s\"", CMD_ARGV[0]); - return ERROR_OK; + command_print(CMD, "set log_output to \"%s\"", CMD_ARGV[0]); + } else { + file = stderr; + command_print(CMD, "set log_output to default"); } - return ERROR_COMMAND_SYNTAX_ERROR; + if (log_output != stderr && log_output) { + /* Close previous log file, if it was open and wasn't stderr. */ + fclose(log_output); + } + log_output = file; + return ERROR_OK; } static const struct command_registration log_command_handlers[] = { @@ -246,7 +255,7 @@ static const struct command_registration log_command_handlers[] = { .handler = handle_log_output_command, .mode = COMMAND_ANY, .help = "redirect logging to a file (default: stderr)", - .usage = "[file_name | \"default\"]", + .usage = "[file_name | 'default']", }, { .name = "debug_level", @@ -274,10 +283,10 @@ void log_init(void) if (debug_env) { int value; int retval = parse_int(debug_env, &value); - if (retval == ERROR_OK && - debug_level >= LOG_LVL_SILENT && - debug_level <= LOG_LVL_DEBUG_IO) - debug_level = value; + if (retval == ERROR_OK + && debug_level >= LOG_LVL_SILENT + && debug_level <= LOG_LVL_DEBUG_IO) + debug_level = value; } if (!log_output) @@ -295,12 +304,6 @@ void log_exit(void) log_output = NULL; } -int set_log_output(struct command_context *cmd_ctx, FILE *output) -{ - log_output = output; - return ERROR_OK; -} - /* add/remove log callback handler */ int log_add_callback(log_callback_fn fn, void *priv) { @@ -405,9 +408,7 @@ char *alloc_printf(const char *format, ...) static void gdb_timeout_warning(int64_t delta_time) { - extern int gdb_actual_connections; - - if (gdb_actual_connections) + if (gdb_get_actual_connections()) LOG_WARNING("keep_alive() was not invoked in the " "%d ms timelimit. GDB alive packet not " "sent! (%" PRId64 " ms). Workaround: increase " @@ -515,7 +516,7 @@ void log_socket_error(const char *socket_desc) * Find the first non-printable character in the char buffer, return a pointer to it. * If no such character exists, return NULL. */ -char *find_nonprint_char(char *buf, unsigned buf_len) +const char *find_nonprint_char(const char *buf, unsigned int buf_len) { for (unsigned int i = 0; i < buf_len; i++) { if (!isprint(buf[i])) diff --git a/src/helper/log.h b/src/helper/log.h index da1e652df2..ac24f8e833 100644 --- a/src/helper/log.h +++ b/src/helper/log.h @@ -19,7 +19,7 @@ /* To achieve C99 printf compatibility in MinGW, gnu_printf should be * used for __attribute__((format( ... ))), with GCC v4.4 or later */ -#if (defined(IS_MINGW) && (((__GNUC__ << 16) + __GNUC_MINOR__) >= 0x00040004)) +#if (defined(IS_MINGW) && (((__GNUC__ << 16) + __GNUC_MINOR__) >= 0x00040004)) && !defined(__clang__) #define PRINTF_ATTRIBUTE_FORMAT gnu_printf #else #define PRINTF_ATTRIBUTE_FORMAT printf @@ -48,12 +48,12 @@ enum log_levels { LOG_LVL_DEBUG_IO = 4, }; -void log_printf(enum log_levels level, const char *file, unsigned line, +void log_printf(enum log_levels level, const char *file, unsigned int line, const char *function, const char *format, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 5, 6))); -void log_vprintf_lf(enum log_levels level, const char *file, unsigned line, +void log_vprintf_lf(enum log_levels level, const char *file, unsigned int line, const char *function, const char *format, va_list args); -void log_printf_lf(enum log_levels level, const char *file, unsigned line, +void log_printf_lf(enum log_levels level, const char *file, unsigned int line, const char *function, const char *format, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 5, 6))); @@ -62,7 +62,6 @@ __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 5, 6))); */ void log_init(void); void log_exit(void); -int set_log_output(struct command_context *cmd_ctx, FILE *output); int log_register_commands(struct command_context *cmd_ctx); @@ -74,7 +73,7 @@ void busy_sleep(uint64_t ms); void log_socket_error(const char *socket_desc); -typedef void (*log_callback_fn)(void *priv, const char *file, unsigned line, +typedef void (*log_callback_fn)(void *priv, const char *file, unsigned int line, const char *function, const char *string); struct log_callback { @@ -86,11 +85,12 @@ struct log_callback { int log_add_callback(log_callback_fn fn, void *priv); int log_remove_callback(log_callback_fn fn, void *priv); -char *alloc_vprintf(const char *fmt, va_list ap); +char *alloc_vprintf(const char *fmt, va_list ap) + __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 1, 0))); char *alloc_printf(const char *fmt, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 1, 2))); -char *find_nonprint_char(char *buf, unsigned buf_len); +const char *find_nonprint_char(const char *buf, unsigned int buf_len); extern int debug_level; @@ -115,6 +115,15 @@ extern int debug_level; expr); \ } while (0) +#define LOG_CUSTOM_LEVEL(level, expr ...) \ + do { \ + enum log_levels _level = level; \ + if (debug_level >= _level) \ + log_printf_lf(_level, \ + __FILE__, __LINE__, __func__, \ + expr); \ + } while (0) + #define LOG_INFO(expr ...) \ log_printf_lf(LOG_LVL_INFO, __FILE__, __LINE__, __func__, expr) @@ -144,6 +153,9 @@ extern int debug_level; #define LOG_TARGET_INFO(target, fmt_str, ...) \ LOG_INFO("[%s] " fmt_str, target_name(target), ##__VA_ARGS__) +#define LOG_TARGET_USER(target, fmt_str, ...) \ + LOG_USER("[%s] " fmt_str, target_name(target), ##__VA_ARGS__) + #define LOG_TARGET_WARNING(target, fmt_str, ...) \ LOG_WARNING("[%s] " fmt_str, target_name(target), ##__VA_ARGS__) diff --git a/src/helper/nvp.c b/src/helper/nvp.c new file mode 100644 index 0000000000..a938716ae9 --- /dev/null +++ b/src/helper/nvp.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views + +/* + * Copyright 2005 Salvatore Sanfilippo <antirez@invece.org> + * Copyright 2005 Clemens Hintze <c.hintze@gmx.net> + * Copyright 2005 patthoyts - Pat Thoyts <patthoyts@users.sf.net> + * Copyright 2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com + * Copyright 2008 Andrew Lunn <andrew@lunn.ch> + * Copyright 2008 Duane Ellis <openocd@duaneellis.com> + * Copyright 2008 Uwe Klein <uklein@klein-messgeraete.de> + * Copyright 2008 Steve Bennett <steveb@workware.net.au> + * Copyright 2009 Nico Coesel <ncoesel@dealogic.nl> + * Copyright 2009 Zachary T Welch zw@superlucidity.net + * Copyright 2009 David Brownell + * Copyright (c) 2005-2011 Jim Tcl Project. All rights reserved. + * + * This file is extracted from jim-nvp.c, originally part of jim TCL code. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <string.h> + +#include <helper/command.h> +#include <helper/nvp.h> + +const struct nvp *nvp_name2value(const struct nvp *p, const char *name) +{ + while (p->name) { + if (strcmp(name, p->name) == 0) + break; + p++; + } + return p; +} + +const struct nvp *nvp_value2name(const struct nvp *p, int value) +{ + while (p->name) { + if (value == p->value) + break; + p++; + } + return p; +} + +void nvp_unknown_command_print(struct command_invocation *cmd, const struct nvp *nvp, + const char *param_name, const char *param_value) +{ + if (param_name) + command_print_sameline(cmd, "%s: Unknown: %s, try one of: ", param_name, param_value); + else + command_print_sameline(cmd, "Unknown param: %s, try one of: ", param_value); + + while (nvp->name) { + if ((nvp + 1)->name) + command_print_sameline(cmd, "%s, ", nvp->name); + else + command_print(cmd, "or %s", nvp->name); + + nvp++; + } + + /* We assume nvp to be not empty and loop has been taken; no need to add a '\n' */ +} diff --git a/src/helper/nvp.h b/src/helper/nvp.h new file mode 100644 index 0000000000..1f4e3d1b43 --- /dev/null +++ b/src/helper/nvp.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Views */ + +/* + * Copyright 2005 Salvatore Sanfilippo <antirez@invece.org> + * Copyright 2005 Clemens Hintze <c.hintze@gmx.net> + * Copyright 2005 patthoyts - Pat Thoyts <patthoyts@users.sf.net> + * Copyright 2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com + * Copyright 2008 Andrew Lunn <andrew@lunn.ch> + * Copyright 2008 Duane Ellis <openocd@duaneellis.com> + * Copyright 2008 Uwe Klein <uklein@klein-messgeraete.de> + * Copyright 2008 Steve Bennett <steveb@workware.net.au> + * Copyright 2009 Nico Coesel <ncoesel@dealogic.nl> + * Copyright 2009 Zachary T Welch zw@superlucidity.net + * Copyright 2009 David Brownell + * Copyright (c) 2005-2011 Jim Tcl Project. All rights reserved. + * + * This file is extracted from jim-nvp.h, originally part of jim TCL code. + */ + +#ifndef OPENOCD_HELPER_NVP_H +#define OPENOCD_HELPER_NVP_H + +#include <helper/compiler.h> + +/** Name Value Pairs, aka: NVP + * - Given a string - return the associated int. + * - Given a number - return the associated string. + * . + * + * Very useful when the number is not a simple index into an array of + * known string, or there may be multiple strings (aliases) that mean then same + * thing. + * + * An NVP Table is terminated with ".name = NULL". + * + * During the 'name2value' operation, if no matching string is found + * the pointer to the terminal element (with p->name == NULL) is returned. + * + * Example: + * \code + * const struct nvp yn[] = { + * { "yes", 1 }, + * { "no" , 0 }, + * { "yep", 1 }, + * { "nope", 0 }, + * { NULL, -1 }, + * }; + * + * struct nvp *result; + * result = nvp_name2value(yn, "yes"); + * returns &yn[0]; + * result = nvp_name2value(yn, "no"); + * returns &yn[1]; + * result = nvp_name2value(yn, "Blah"); + * returns &yn[4]; + * \endcode + * + * During the number2name operation, the first matching value is returned. + */ + +struct nvp { + const char *name; + int value; +}; + +struct command_invocation; + +/* Name Value Pairs Operations */ +const struct nvp *nvp_name2value(const struct nvp *nvp_table, const char *name) + __returns_nonnull __nonnull((1)); +const struct nvp *nvp_value2name(const struct nvp *nvp_table, int v) + __returns_nonnull __nonnull((1)); + +void nvp_unknown_command_print(struct command_invocation *cmd, const struct nvp *nvp, + const char *param_name, const char *param_value); + +#endif /* OPENOCD_HELPER_NVP_H */ diff --git a/src/helper/options.c b/src/helper/options.c index 205d5e7939..735b8af5f6 100644 --- a/src/helper/options.c +++ b/src/helper/options.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2004, 2005 by Dominic Rath * @@ -39,12 +39,12 @@ static int help_flag, version_flag; static const struct option long_options[] = { {"help", no_argument, &help_flag, 1}, {"version", no_argument, &version_flag, 1}, - {"debug", optional_argument, 0, 'd'}, - {"file", required_argument, 0, 'f'}, - {"search", required_argument, 0, 's'}, - {"log_output", required_argument, 0, 'l'}, - {"command", required_argument, 0, 'c'}, - {0, 0, 0, 0} + {"debug", optional_argument, NULL, 'd'}, + {"file", required_argument, NULL, 'f'}, + {"search", required_argument, NULL, 's'}, + {"log_output", required_argument, NULL, 'l'}, + {"command", required_argument, NULL, 'c'}, + {NULL, 0, NULL, 0} }; int configuration_output_handler(struct command_context *context, const char *line) @@ -303,12 +303,14 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[]) break; } case 'l': /* --log_output | -l */ - if (optarg) - command_run_linef(cmd_ctx, "log_output %s", optarg); + { + int retval = command_run_linef(cmd_ctx, "log_output %s", optarg); + if (retval != ERROR_OK) + return retval; break; + } case 'c': /* --command | -c */ - if (optarg) - add_config_command(optarg); + add_config_command(optarg); break; default: /* '?' */ /* getopt will emit an error message, all we have to do is bail. */ @@ -332,7 +334,7 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[]) LOG_OUTPUT(" | -d<n>\tset debug level to <level>\n"); LOG_OUTPUT("--log_output | -l\tredirect log output to file <name>\n"); LOG_OUTPUT("--command | -c\trun <command>\n"); - exit(-1); + exit(0); } if (version_flag) { @@ -341,6 +343,10 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[]) exit(0); } + /* dump full command line */ + for (int i = 0; i < argc; i++) + LOG_DEBUG("ARGV[%d] = \"%s\"", i, argv[i]); + /* paths specified on the command line take precedence over these * built-in paths */ diff --git a/src/helper/replacements.c b/src/helper/replacements.c index 2cbce7f3bd..782d975184 100644 --- a/src/helper/replacements.c +++ b/src/helper/replacements.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -10,10 +10,18 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * ***************************************************************************/ -/* DANGER!!!! These must be defined *BEFORE* replacements.h and the malloc() macro!!!! */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +/* define IN_REPLACEMENTS_C before include replacements.h */ +#define IN_REPLACEMENTS_C +#include "replacements.h" #include <stdlib.h> #include <string.h> + /* * clear_malloc * @@ -41,10 +49,6 @@ void *fill_malloc(size_t size) return t; } -#define IN_REPLACEMENTS_C -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif #ifdef HAVE_STRINGS_H #include <strings.h> #endif diff --git a/src/helper/replacements.h b/src/helper/replacements.h index 9eac4d2458..ecc0e5e955 100644 --- a/src/helper/replacements.h +++ b/src/helper/replacements.h @@ -66,12 +66,10 @@ int gettimeofday(struct timeval *tv, struct timezone *tz); #endif -#ifndef IN_REPLACEMENTS_C -/**** clear_malloc & fill_malloc ****/ void *clear_malloc(size_t size); void *fill_malloc(size_t size); -#endif +#ifndef IN_REPLACEMENTS_C /* * Now you have 3 ways for the malloc function: * @@ -100,6 +98,7 @@ void *fill_malloc(size_t size); /* #define malloc(_a) clear_malloc(_a) * #define malloc(_a) fill_malloc(_a) */ +#endif /* IN_REPLACEMENTS_C */ /* GNU extensions to the C library that may be missing on some systems */ #ifndef HAVE_STRNDUP @@ -112,7 +111,7 @@ size_t strnlen(const char *s, size_t maxlen); #ifndef HAVE_USLEEP #ifdef _WIN32 -static inline unsigned usleep(unsigned int usecs) +static inline unsigned int usleep(unsigned int usecs) { Sleep((usecs/1000)); return 0; diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl index 5a0d479f5e..e328cbe07f 100644 --- a/src/helper/startup.tcl +++ b/src/helper/startup.tcl @@ -7,19 +7,63 @@ # Try flipping / and \ to find file if the filename does not # match the precise spelling -proc find {filename} { +# lappend _telnet_autocomplete_skip _find_internal +proc _find_internal {filename} { if {[catch {ocd_find $filename} t]==0} { return $t } - if {[catch {ocd_find [string map {\ /} $filename} t]==0} { + if {[catch {ocd_find [string map {\\ /} $filename]} t]==0} { return $t } - if {[catch {ocd_find [string map {/ \\} $filename} t]==0} { + if {[catch {ocd_find [string map {/ \\} $filename]} t]==0} { return $t } # make sure error message matches original input string return -code error "Can't find $filename" } + +proc find {filename} { + if {[catch {_find_internal $filename} t]==0} { + return $t + } + + # Check in vendor specific folder: + + # - path/to/a/certain/vendor_config_file + # - path/to/a/certain/vendor-config_file + # replaced with + # - path/to/a/certain/vendor/config_file + regsub {([/\\])([^/\\_-]*)[_-]([^/\\]*$)} $filename "\\1\\2\\1\\3" f + if {[catch {_find_internal $f} t]==0} { + echo "WARNING: '$filename' is deprecated, use '$f' instead" + return $t + } + + foreach vendor {nordic ti st} { + # - path/to/a/certain/config_file + # replaced with + # - path/to/a/certain/${vendor}/config_file + regsub {([/\\])([^/\\]*$)} $filename "\\1$vendor\\1\\2" f + if {[catch {_find_internal $f} t]==0} { + echo "WARNING: '$filename' is deprecated, use '$f' instead" + return $t + } + } + + # at last, check for explicit renaming + if {[catch { + source [_find_internal file_renaming.cfg] + set unixname [string map {\\ /} $filename] + regsub {^(.*/|)((board|chip|cpld|cpu|fpga|interface|target|test|tools)/.*.cfg$)} $unixname {{\1} {\2}} split + set newname [lindex $split 0][dict get $_file_renaming [lindex $split 1]] + _find_internal $newname + } t]==0} { + echo "WARNING: '$filename' is deprecated, use '$newname' instead" + return $t + } + + return -code error "Can't find $filename" +} add_usage_text find "<file>" add_help_text find "print full path to file according to OpenOCD search rules" diff --git a/src/helper/time_support.c b/src/helper/time_support.c index 548a716938..dda3cb3e4e 100644 --- a/src/helper/time_support.c +++ b/src/helper/time_support.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * diff --git a/src/helper/time_support_common.c b/src/helper/time_support_common.c index 8d11602f3e..9d17a315bf 100644 --- a/src/helper/time_support_common.c +++ b/src/helper/time_support_common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * diff --git a/src/helper/types.h b/src/helper/types.h index b99ece1098..b3edd21184 100644 --- a/src/helper/types.h +++ b/src/helper/types.h @@ -51,7 +51,7 @@ * Compute the number of elements of a variable length array. * <code> * const char *strs[] = { "a", "b", "c" }; - * unsigned num_strs = ARRAY_SIZE(strs); + * size_t num_strs = ARRAY_SIZE(strs); * </code> */ #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) @@ -151,7 +151,7 @@ static inline uint16_t be_to_h_u16(const uint8_t *buf) return (uint16_t)((uint16_t)buf[1] | (uint16_t)buf[0] << 8); } -static inline void h_u64_to_le(uint8_t *buf, int64_t val) +static inline void h_u64_to_le(uint8_t *buf, uint64_t val) { buf[7] = (uint8_t) (val >> 56); buf[6] = (uint8_t) (val >> 48); @@ -163,7 +163,7 @@ static inline void h_u64_to_le(uint8_t *buf, int64_t val) buf[0] = (uint8_t) (val >> 0); } -static inline void h_u64_to_be(uint8_t *buf, int64_t val) +static inline void h_u64_to_be(uint8_t *buf, uint64_t val) { buf[0] = (uint8_t) (val >> 56); buf[1] = (uint8_t) (val >> 48); @@ -175,46 +175,46 @@ static inline void h_u64_to_be(uint8_t *buf, int64_t val) buf[7] = (uint8_t) (val >> 0); } -static inline void h_u32_to_le(uint8_t *buf, int val) +static inline void h_u32_to_le(uint8_t *buf, uint32_t val) { - buf[3] = (uint8_t) (val >> 24); - buf[2] = (uint8_t) (val >> 16); - buf[1] = (uint8_t) (val >> 8); - buf[0] = (uint8_t) (val >> 0); + buf[3] = (val >> 24) & 0xff; + buf[2] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[0] = (val >> 0) & 0xff; } -static inline void h_u32_to_be(uint8_t *buf, int val) +static inline void h_u32_to_be(uint8_t *buf, uint32_t val) { - buf[0] = (uint8_t) (val >> 24); - buf[1] = (uint8_t) (val >> 16); - buf[2] = (uint8_t) (val >> 8); - buf[3] = (uint8_t) (val >> 0); + buf[0] = (val >> 24) & 0xff; + buf[1] = (val >> 16) & 0xff; + buf[2] = (val >> 8) & 0xff; + buf[3] = (val >> 0) & 0xff; } -static inline void h_u24_to_le(uint8_t *buf, int val) +static inline void h_u24_to_le(uint8_t *buf, unsigned int val) { - buf[2] = (uint8_t) (val >> 16); - buf[1] = (uint8_t) (val >> 8); - buf[0] = (uint8_t) (val >> 0); + buf[2] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[0] = (val >> 0) & 0xff; } -static inline void h_u24_to_be(uint8_t *buf, int val) +static inline void h_u24_to_be(uint8_t *buf, unsigned int val) { - buf[0] = (uint8_t) (val >> 16); - buf[1] = (uint8_t) (val >> 8); - buf[2] = (uint8_t) (val >> 0); + buf[0] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[2] = (val >> 0) & 0xff; } -static inline void h_u16_to_le(uint8_t *buf, int val) +static inline void h_u16_to_le(uint8_t *buf, uint16_t val) { - buf[1] = (uint8_t) (val >> 8); - buf[0] = (uint8_t) (val >> 0); + buf[1] = (val >> 8) & 0xff; + buf[0] = (val >> 0) & 0xff; } -static inline void h_u16_to_be(uint8_t *buf, int val) +static inline void h_u16_to_be(uint8_t *buf, uint16_t val) { - buf[0] = (uint8_t) (val >> 8); - buf[1] = (uint8_t) (val >> 0); + buf[0] = (val >> 8) & 0xff; + buf[1] = (val >> 0) & 0xff; } /** diff --git a/src/helper/util.c b/src/helper/util.c index 397b8a2115..2e9f6155ee 100644 --- a/src/helper/util.c +++ b/src/helper/util.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Øyvind Harboe * @@ -12,29 +12,23 @@ #include "log.h" #include "time_support.h" +#include "util.h" -static int jim_util_ms(Jim_Interp *interp, - int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handler_util_ms) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "ls ?dir?"); - return JIM_ERR; - } + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - /* Cast from 64 to 32 bit int works for 2's-compliment - * when calculating differences*/ - Jim_SetResult(interp, Jim_NewIntObj(interp, (int)timeval_ms())); + command_print(CMD, "%" PRId64, timeval_ms()); - return JIM_OK; + return ERROR_OK; } static const struct command_registration util_command_handlers[] = { - /* jim handlers */ { .name = "ms", .mode = COMMAND_ANY, - .jim_handler = jim_util_ms, + .handler = handler_util_ms, .help = "Returns ever increasing milliseconds. Used to calculate differences in time.", .usage = "", diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am index 43c6f8b27d..7ce4adc295 100644 --- a/src/jtag/Makefile.am +++ b/src/jtag/Makefile.am @@ -9,11 +9,6 @@ include %D%/hla/Makefile.am %C%_libjtag_la_LIBADD += $(top_builddir)/%D%/hla/libocdhla.la endif -if AICE -include %D%/aice/Makefile.am -%C%_libjtag_la_LIBADD += $(top_builddir)/%D%/aice/libocdaice.la -endif - include %D%/drivers/Makefile.am %C%_libjtag_la_LIBADD += $(top_builddir)/%D%/drivers/libocdjtagdrivers.la diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index 14452d42f2..6785a74ef1 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2005 by Dominic Rath <Dominic.Rath@gmx.de> * Copyright (C) 2007-2010 Øyvind Harboe <oyvind.harboe@zylin.com> @@ -16,19 +16,15 @@ #include "minidriver.h" #include "interface.h" #include "interfaces.h" +#include <helper/bits.h> #include <transport/transport.h> -#ifdef HAVE_STRINGS_H -#include <strings.h> -#endif - /** * @file * Holds support for configuring debug adapters from TCl scripts. */ struct adapter_driver *adapter_driver; -const char * const jtag_only[] = { "jtag", NULL }; enum adapter_clk_mode { CLOCK_MODE_UNSELECTED = 0, @@ -36,6 +32,8 @@ enum adapter_clk_mode { CLOCK_MODE_RCLK }; +#define DEFAULT_CLOCK_SPEED_KHZ 100U + /** * Adapter configuration */ @@ -46,13 +44,77 @@ static struct { enum adapter_clk_mode clock_mode; int speed_khz; int rclk_fallback_speed_khz; + struct adapter_gpio_config gpios[ADAPTER_GPIO_IDX_NUM]; + bool gpios_initialized; /* Initialization of GPIOs to their unset values performed at run time */ } adapter_config; +static const struct gpio_map { + const char *name; + enum adapter_gpio_direction direction; + bool permit_drive_option; + bool permit_init_state_option; +} gpio_map[ADAPTER_GPIO_IDX_NUM] = { + [ADAPTER_GPIO_IDX_TDO] = { "tdo", ADAPTER_GPIO_DIRECTION_INPUT, false, true, }, + [ADAPTER_GPIO_IDX_TDI] = { "tdi", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, }, + [ADAPTER_GPIO_IDX_TMS] = { "tms", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, }, + [ADAPTER_GPIO_IDX_TCK] = { "tck", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, }, + [ADAPTER_GPIO_IDX_SWDIO] = { "swdio", ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL, true, true, }, + [ADAPTER_GPIO_IDX_SWDIO_DIR] = { "swdio_dir", ADAPTER_GPIO_DIRECTION_OUTPUT, true, false, }, + [ADAPTER_GPIO_IDX_SWCLK] = { "swclk", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, }, + [ADAPTER_GPIO_IDX_TRST] = { "trst", ADAPTER_GPIO_DIRECTION_OUTPUT, false, true, }, + [ADAPTER_GPIO_IDX_SRST] = { "srst", ADAPTER_GPIO_DIRECTION_OUTPUT, false, true, }, + [ADAPTER_GPIO_IDX_LED] = { "led", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, }, +}; + +static int adapter_config_khz(unsigned int khz); + bool is_adapter_initialized(void) { return adapter_config.adapter_initialized; } +/* For convenience of the bit-banging drivers keep the gpio_config drive + * settings for srst and trst in sync with values set by the "adapter + * reset_config" command. + */ +static void sync_adapter_reset_with_gpios(void) +{ + enum reset_types cfg = jtag_get_reset_config(); + if (cfg & RESET_SRST_PUSH_PULL) + adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL; + else + adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN; + if (cfg & RESET_TRST_OPEN_DRAIN) + adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN; + else + adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL; +} + +static void adapter_driver_gpios_init(void) +{ + if (adapter_config.gpios_initialized) + return; + + for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) { + /* Use ADAPTER_GPIO_NOT_SET as the sentinel 'unset' value. */ + adapter_config.gpios[i].gpio_num = ADAPTER_GPIO_NOT_SET; + adapter_config.gpios[i].chip_num = ADAPTER_GPIO_NOT_SET; + if (gpio_map[i].direction == ADAPTER_GPIO_DIRECTION_INPUT) + adapter_config.gpios[i].init_state = ADAPTER_GPIO_INIT_STATE_INPUT; + } + + /* Drivers assume active low, and this is the normal behaviour for reset + * lines so should be the default. */ + adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].active_low = true; + adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].active_low = true; + sync_adapter_reset_with_gpios(); + + /* JTAG GPIOs should be inactive except for tms */ + adapter_config.gpios[ADAPTER_GPIO_IDX_TMS].init_state = ADAPTER_GPIO_INIT_STATE_ACTIVE; + + adapter_config.gpios_initialized = true; +} + /** * Do low-level setup like initializing registers, output signals, * and clocking. @@ -69,23 +131,33 @@ int adapter_init(struct command_context *cmd_ctx) return ERROR_JTAG_INVALID_INTERFACE; } + adapter_driver_gpios_init(); + int retval; + + /* If the adapter supports configurable speed but the speed is not configured, + * provide a hint to the user. */ + if (adapter_driver->speed && adapter_config.clock_mode == CLOCK_MODE_UNSELECTED) { + LOG_WARNING("An adapter speed is not selected in the init scripts." + " OpenOCD will try to run the adapter at very low speed (%d kHz).", + DEFAULT_CLOCK_SPEED_KHZ); + LOG_WARNING("To remove this warnings and achieve reasonable communication speed with the target," + " set \"adapter speed\" or \"jtag_rclk\" in the init scripts."); + retval = adapter_config_khz(DEFAULT_CLOCK_SPEED_KHZ); + if (retval != ERROR_OK) + return ERROR_JTAG_INIT_FAILED; + } + retval = adapter_driver->init(); if (retval != ERROR_OK) return retval; adapter_config.adapter_initialized = true; if (!adapter_driver->speed) { - LOG_INFO("This adapter doesn't support configurable speed"); + LOG_INFO("Note: The adapter \"%s\" doesn't support configurable speed", adapter_driver->name); return ERROR_OK; } - if (adapter_config.clock_mode == CLOCK_MODE_UNSELECTED) { - LOG_ERROR("An adapter speed is not selected in the init script." - " Insert a call to \"adapter speed\" or \"jtag_rclk\" to proceed."); - return ERROR_JTAG_INIT_FAILED; - } - int requested_khz = adapter_get_speed_khz(); int actual_khz = requested_khz; int speed_var = 0; @@ -115,7 +187,6 @@ int adapter_init(struct command_context *cmd_ctx) int adapter_quit(void) { if (is_adapter_initialized() && adapter_driver->quit) { - /* close the JTAG interface */ int result = adapter_driver->quit(); if (result != ERROR_OK) LOG_ERROR("failed: %d", result); @@ -175,7 +246,8 @@ static int adapter_set_speed(int speed) return is_adapter_initialized() ? adapter_driver->speed(speed) : ERROR_OK; } -int adapter_config_khz(unsigned int khz) +/** Attempt to configure the adapter for the specified kHz. */ +static int adapter_config_khz(unsigned int khz) { LOG_DEBUG("handle adapter khz"); adapter_config.clock_mode = CLOCK_MODE_KHZ; @@ -305,71 +377,66 @@ bool adapter_usb_location_equal(uint8_t dev_bus, uint8_t *port_path, size_t path return equal; } -static int jim_adapter_name(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_adapter_name) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - - /* return the name of the interface */ + /* return the name of the adapter driver */ /* TCL code might need to know the exact type... */ /* FUTURE: we allow this as a means to "set" the interface. */ - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)"); - return JIM_ERR; - } - const char *name = adapter_driver ? adapter_driver->name : NULL; - Jim_SetResultString(goi.interp, name ? name : "undefined", -1); - return JIM_OK; + + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + command_print(CMD, "%s", adapter_driver ? adapter_driver->name : "undefined"); + + return ERROR_OK; } -COMMAND_HANDLER(adapter_transports_command) +COMMAND_HANDLER(dump_adapter_driver_list) { - char **transports; - int retval; - - retval = CALL_COMMAND_HANDLER(transport_list_parse, &transports); - if (retval != ERROR_OK) - return retval; + int max_len = 0; + for (unsigned int i = 0; adapter_drivers[i]; i++) { + int len = strlen(adapter_drivers[i]->name); + if (max_len < len) + max_len = len; + } - retval = allow_transports(CMD_CTX, (const char **)transports); + for (unsigned int i = 0; adapter_drivers[i]; i++) { + const char *name = adapter_drivers[i]->name; + unsigned int transport_ids = adapter_drivers[i]->transport_ids; - if (retval != ERROR_OK) { - for (unsigned i = 0; transports[i]; i++) - free(transports[i]); - free(transports); + command_print_sameline(CMD, "%-*s {", max_len, name); + for (unsigned int j = BIT(0); j & TRANSPORT_VALID_MASK; j <<= 1) + if (j & transport_ids) + command_print_sameline(CMD, " %s", transport_name(j)); + command_print(CMD, " }"); } - return retval; + + return ERROR_OK; } COMMAND_HANDLER(handle_adapter_list_command) { - if (strcmp(CMD_NAME, "list") == 0 && CMD_ARGC > 0) + if (CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; - command_print(CMD, "The following debug adapters are available:"); - for (unsigned i = 0; adapter_drivers[i]; i++) { - const char *name = adapter_drivers[i]->name; - command_print(CMD, "%u: %s", i + 1, name); - } - - return ERROR_OK; + return CALL_COMMAND_HANDLER(dump_adapter_driver_list); } COMMAND_HANDLER(handle_adapter_driver_command) { int retval; - /* check whether the interface is already configured */ + /* check whether the adapter driver is already configured */ if (adapter_driver) { - LOG_WARNING("Interface already configured, ignoring"); + LOG_WARNING("Adapter driver already configured, ignoring"); return ERROR_OK; } - /* interface name is a mandatory argument */ - if (CMD_ARGC != 1 || CMD_ARGV[0][0] == '\0') + /* adapter driver name is a mandatory argument */ + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned i = 0; adapter_drivers[i]; i++) { + for (unsigned int i = 0; adapter_drivers[i]; i++) { if (strcmp(CMD_ARGV[0], adapter_drivers[i]->name) != 0) continue; @@ -381,15 +448,17 @@ COMMAND_HANDLER(handle_adapter_driver_command) adapter_driver = adapter_drivers[i]; - return allow_transports(CMD_CTX, adapter_driver->transports); + return allow_transports(CMD_CTX, adapter_driver->transport_ids, + adapter_driver->transport_preferred_id); } - /* no valid interface was found (i.e. the configuration option, - * didn't match one of the compiled-in interfaces + /* no valid adapter driver was found (i.e. the configuration option, + * didn't match one of the compiled-in drivers */ - LOG_ERROR("The specified debug interface was not found (%s)", + LOG_ERROR("The specified adapter driver was not found (%s)", CMD_ARGV[0]); - CALL_COMMAND_HANDLER(handle_adapter_list_command); + command_print(CMD, "The following adapter drivers are available:"); + CALL_COMMAND_HANDLER(dump_adapter_driver_list); return ERROR_JTAG_INVALID_INTERFACE; } @@ -532,6 +601,8 @@ COMMAND_HANDLER(handle_reset_config_command) old_cfg &= ~mask; new_cfg |= old_cfg; jtag_set_reset_config(new_cfg); + sync_adapter_reset_with_gpios(); + } else new_cfg = jtag_get_reset_config(); @@ -615,7 +686,7 @@ COMMAND_HANDLER(handle_adapter_srst_delay_command) if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; if (CMD_ARGC == 1) { - unsigned delay; + unsigned int delay; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], delay); jtag_set_nsrst_delay(delay); @@ -629,7 +700,7 @@ COMMAND_HANDLER(handle_adapter_srst_pulse_width_command) if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; if (CMD_ARGC == 1) { - unsigned width; + unsigned int width; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], width); jtag_set_nsrst_assert_width(width); @@ -645,7 +716,7 @@ COMMAND_HANDLER(handle_adapter_speed_command) int retval = ERROR_OK; if (CMD_ARGC == 1) { - unsigned khz = 0; + unsigned int khz = 0; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz); retval = adapter_config_khz(khz); @@ -762,6 +833,219 @@ COMMAND_HANDLER(handle_adapter_reset_de_assert) (srst == VALUE_DEASSERT) ? SRST_DEASSERT : SRST_ASSERT); } +static int get_gpio_index(const char *signal_name) +{ + for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) { + if (strcmp(gpio_map[i].name, signal_name) == 0) + return i; + } + return -1; +} + +static COMMAND_HELPER(helper_adapter_gpio_print_config, enum adapter_gpio_config_index gpio_idx) +{ + struct adapter_gpio_config *gpio_config = &adapter_config.gpios[gpio_idx]; + const char *active_state = gpio_config->active_low ? "low" : "high"; + const char *dir = ""; + const char *drive = ""; + const char *pull = ""; + const char *init_state = ""; + + if (gpio_config->gpio_num == ADAPTER_GPIO_NOT_SET) { + command_print(CMD, "adapter gpio %s: not configured", gpio_map[gpio_idx].name); + return ERROR_OK; + } + + switch (gpio_map[gpio_idx].direction) { + case ADAPTER_GPIO_DIRECTION_INPUT: + dir = "input"; + break; + case ADAPTER_GPIO_DIRECTION_OUTPUT: + dir = "output"; + break; + case ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL: + dir = "bidirectional"; + break; + } + + if (gpio_map[gpio_idx].permit_drive_option) { + switch (gpio_config->drive) { + case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL: + drive = ", push-pull"; + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN: + drive = ", open-drain"; + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE: + drive = ", open-source"; + break; + } + } + + switch (gpio_config->pull) { + case ADAPTER_GPIO_PULL_NONE: + pull = ", pull-none"; + break; + case ADAPTER_GPIO_PULL_UP: + pull = ", pull-up"; + break; + case ADAPTER_GPIO_PULL_DOWN: + pull = ", pull-down"; + break; + } + + if (gpio_map[gpio_idx].permit_init_state_option) { + switch (gpio_config->init_state) { + case ADAPTER_GPIO_INIT_STATE_INACTIVE: + init_state = ", init-state inactive"; + break; + case ADAPTER_GPIO_INIT_STATE_ACTIVE: + init_state = ", init-state active"; + break; + case ADAPTER_GPIO_INIT_STATE_INPUT: + init_state = ", init-state input"; + break; + } + } + + command_print(CMD, "adapter gpio %s (%s): num %u, chip %d, active-%s%s%s%s", + gpio_map[gpio_idx].name, dir, gpio_config->gpio_num, (int)gpio_config->chip_num, active_state, + drive, pull, init_state); + + return ERROR_OK; +} + +COMMAND_HANDLER(helper_adapter_gpio_print_all_configs) +{ + for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) + CALL_COMMAND_HANDLER(helper_adapter_gpio_print_config, i); + return ERROR_OK; +} + +COMMAND_HANDLER(adapter_gpio_config_handler) +{ + unsigned int i = 1; + struct adapter_gpio_config *gpio_config; + + adapter_driver_gpios_init(); + + if (CMD_ARGC == 0) { + CALL_COMMAND_HANDLER(helper_adapter_gpio_print_all_configs); + return ERROR_OK; + } + + int gpio_idx = get_gpio_index(CMD_ARGV[0]); + if (gpio_idx == -1) { + LOG_ERROR("adapter has no gpio named %s", CMD_ARGV[0]); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (CMD_ARGC == 1) { + CALL_COMMAND_HANDLER(helper_adapter_gpio_print_config, gpio_idx); + return ERROR_OK; + } + + gpio_config = &adapter_config.gpios[gpio_idx]; + while (i < CMD_ARGC) { + LOG_DEBUG("Processing %s", CMD_ARGV[i]); + + if (isdigit(*CMD_ARGV[i])) { + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[i], gpio_config->gpio_num); + ++i; + continue; + } + + if (strcmp(CMD_ARGV[i], "-chip") == 0) { + if (CMD_ARGC - i < 2) { + LOG_ERROR("-chip option requires a parameter"); + return ERROR_FAIL; + } + LOG_DEBUG("-chip arg is %s", CMD_ARGV[i + 1]); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[i + 1], gpio_config->chip_num); + i += 2; + continue; + } + + if (strcmp(CMD_ARGV[i], "-active-high") == 0) { + ++i; + gpio_config->active_low = false; + continue; + } + if (strcmp(CMD_ARGV[i], "-active-low") == 0) { + ++i; + gpio_config->active_low = true; + continue; + } + + if (gpio_map[gpio_idx].permit_drive_option) { + if (strcmp(CMD_ARGV[i], "-push-pull") == 0) { + ++i; + gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL; + continue; + } + if (strcmp(CMD_ARGV[i], "-open-drain") == 0) { + ++i; + gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN; + continue; + } + if (strcmp(CMD_ARGV[i], "-open-source") == 0) { + ++i; + gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE; + continue; + } + } + + if (strcmp(CMD_ARGV[i], "-pull-none") == 0) { + ++i; + gpio_config->pull = ADAPTER_GPIO_PULL_NONE; + continue; + } + if (strcmp(CMD_ARGV[i], "-pull-up") == 0) { + ++i; + gpio_config->pull = ADAPTER_GPIO_PULL_UP; + continue; + } + if (strcmp(CMD_ARGV[i], "-pull-down") == 0) { + ++i; + gpio_config->pull = ADAPTER_GPIO_PULL_DOWN; + continue; + } + + if (gpio_map[gpio_idx].permit_init_state_option) { + if (strcmp(CMD_ARGV[i], "-init-inactive") == 0) { + ++i; + gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_INACTIVE; + continue; + } + if (strcmp(CMD_ARGV[i], "-init-active") == 0) { + ++i; + gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_ACTIVE; + continue; + } + + if (gpio_map[gpio_idx].direction == ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL && + strcmp(CMD_ARGV[i], "-init-input") == 0) { + ++i; + gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_INPUT; + continue; + } + } + + LOG_ERROR("illegal option for adapter %s %s: %s", + CMD_NAME, gpio_map[gpio_idx].name, CMD_ARGV[i]); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + /* Force swdio_dir init state to be compatible with swdio init state */ + if (gpio_idx == ADAPTER_GPIO_IDX_SWDIO) + adapter_config.gpios[ADAPTER_GPIO_IDX_SWDIO_DIR].init_state = + (gpio_config->init_state == ADAPTER_GPIO_INIT_STATE_INPUT) ? + ADAPTER_GPIO_INIT_STATE_INACTIVE : + ADAPTER_GPIO_INIT_STATE_ACTIVE; + + return ERROR_OK; +} + #ifdef HAVE_LIBUSB_GET_PORT_NUMBERS COMMAND_HANDLER(handle_usb_location_command) { @@ -840,9 +1124,10 @@ static const struct command_registration adapter_command_handlers[] = { { .name = "name", .mode = COMMAND_ANY, - .jim_handler = jim_adapter_name, + .handler = handle_adapter_name, .help = "Returns the name of the currently " "selected adapter (driver)", + .usage = "", }, { .name = "srst", @@ -851,13 +1136,6 @@ static const struct command_registration adapter_command_handlers[] = { .usage = "", .chain = adapter_srst_command_handlers, }, - { - .name = "transports", - .handler = adapter_transports_command, - .mode = COMMAND_CONFIG, - .help = "Declare transports the adapter supports.", - .usage = "transport ...", - }, { .name = "usb", .mode = COMMAND_ANY, @@ -879,6 +1157,19 @@ static const struct command_registration adapter_command_handlers[] = { .help = "Controls SRST and TRST lines.", .usage = "|assert [srst|trst [deassert|assert srst|trst]]", }, + { + .name = "gpio", + .handler = adapter_gpio_config_handler, + .mode = COMMAND_CONFIG, + .help = "gpio adapter command group", + .usage = "[ tdo|tdi|tms|tck|trst|swdio|swdio_dir|swclk|srst|led" + "[gpio_number] " + "[-chip chip_number] " + "[-active-high|-active-low] " + "[-push-pull|-open-drain|-open-source] " + "[-pull-none|-pull-up|-pull-down]" + "[-init-inactive|-init-active|-init-input] ]", + }, COMMAND_REGISTRATION_DONE }; @@ -915,3 +1206,14 @@ int adapter_register_commands(struct command_context *ctx) { return register_commands(ctx, NULL, interface_command_handlers); } + +const char *adapter_gpio_get_name(enum adapter_gpio_config_index idx) +{ + return gpio_map[idx].name; +} + +/* Allow drivers access to the GPIO configuration */ +const struct adapter_gpio_config *adapter_gpio_get_config(void) +{ + return adapter_config.gpios; +} diff --git a/src/jtag/adapter.h b/src/jtag/adapter.h index 300769c229..556952f8d7 100644 --- a/src/jtag/adapter.h +++ b/src/jtag/adapter.h @@ -10,6 +10,60 @@ #include <stdbool.h> #include <stddef.h> #include <stdint.h> +#include <limits.h> + +/** Supported output drive modes for adaptor GPIO */ +enum adapter_gpio_drive_mode { + ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL, + ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN, + ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE, +}; + +/** Supported GPIO directions */ +enum adapter_gpio_direction { + ADAPTER_GPIO_DIRECTION_INPUT, + ADAPTER_GPIO_DIRECTION_OUTPUT, + ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL, +}; + +/** Supported initial states for GPIO */ +enum adapter_gpio_init_state { + ADAPTER_GPIO_INIT_STATE_INACTIVE, /* Should be zero so it is the default state */ + ADAPTER_GPIO_INIT_STATE_ACTIVE, + ADAPTER_GPIO_INIT_STATE_INPUT, +}; + +/** Supported pull directions for GPIO */ +enum adapter_gpio_pull { + ADAPTER_GPIO_PULL_NONE, + ADAPTER_GPIO_PULL_UP, + ADAPTER_GPIO_PULL_DOWN, +}; + +/** Adapter GPIO */ +enum adapter_gpio_config_index { + ADAPTER_GPIO_IDX_TDO, + ADAPTER_GPIO_IDX_TDI, + ADAPTER_GPIO_IDX_TMS, + ADAPTER_GPIO_IDX_TCK, + ADAPTER_GPIO_IDX_TRST, + ADAPTER_GPIO_IDX_SWDIO, + ADAPTER_GPIO_IDX_SWDIO_DIR, + ADAPTER_GPIO_IDX_SWCLK, + ADAPTER_GPIO_IDX_SRST, + ADAPTER_GPIO_IDX_LED, + ADAPTER_GPIO_IDX_NUM, /* must be the last item */ +}; + +/** Configuration options for a single GPIO */ +struct adapter_gpio_config { + unsigned int gpio_num; + unsigned int chip_num; + enum adapter_gpio_drive_mode drive; /* For outputs only */ + enum adapter_gpio_init_state init_state; + bool active_low; + enum adapter_gpio_pull pull; +}; struct command_context; @@ -43,9 +97,6 @@ int adapter_get_speed(int *speed); */ int adapter_get_speed_readable(int *speed); -/** Attempt to configure the adapter for the specified kHz. */ -int adapter_config_khz(unsigned int khz); - /** * Attempt to enable RTCK/RCLK. If that fails, fallback to the * specified frequency. @@ -58,4 +109,16 @@ unsigned int adapter_get_speed_khz(void); /** Retrieves the serial number set with command 'adapter serial' */ const char *adapter_get_required_serial(void); +/** + * Retrieves gpio name + */ +const char *adapter_gpio_get_name(enum adapter_gpio_config_index idx); + +/** + * Retrieves gpio configuration set with command "adapter gpio <signal_name>" + */ +const struct adapter_gpio_config *adapter_gpio_get_config(void); + +#define ADAPTER_GPIO_NOT_SET UINT_MAX + #endif /* OPENOCD_JTAG_ADAPTER_H */ diff --git a/src/jtag/aice/Makefile.am b/src/jtag/aice/Makefile.am deleted file mode 100644 index bc5dac1e24..0000000000 --- a/src/jtag/aice/Makefile.am +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -noinst_LTLIBRARIES += %D%/libocdaice.la - -%C%_libocdaice_la_CPPFLAGS = -I$(top_srcdir)/src/jtag/drivers $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS) -%C%_libocdaice_la_SOURCES = \ - %D%/aice_transport.c \ - %D%/aice_interface.c \ - %D%/aice_port.c \ - %D%/aice_usb.c \ - %D%/aice_pipe.c \ - %D%/aice_transport.h \ - %D%/aice_interface.h \ - %D%/aice_port.h \ - %D%/aice_usb.h \ - %D%/aice_pipe.h diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c deleted file mode 100644 index 7c57d444de..0000000000 --- a/src/jtag/aice/aice_interface.c +++ /dev/null @@ -1,507 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <jtag/adapter.h> -#include <jtag/interface.h> -#include <jtag/commands.h> -#include <transport/transport.h> -#include <target/target.h> -#include <jtag/aice/aice_transport.h> -#include "aice_usb.h" - -#define AICE_KHZ_TO_SPEED_MAP_SIZE 16 -static const int aice_khz_to_speed_map[AICE_KHZ_TO_SPEED_MAP_SIZE] = { - 30000, - 15000, - 7500, - 3750, - 1875, - 937, - 468, - 234, - 48000, - 24000, - 12000, - 6000, - 3000, - 1500, - 750, - 375, -}; - -static const struct aice_port *aice_port; -static struct aice_port_param_s param; -static uint32_t retry_times; -static uint32_t count_to_check_dbger; - -/***************************************************************************/ -/* External interface implementation */ -static uint32_t aice_target_id_codes[AICE_MAX_NUM_CORE]; -static uint8_t aice_num_of_target_id_codes; - -/***************************************************************************/ -/* AICE operations */ -int aice_init_targets(void) -{ - int res; - struct target *target; - struct aice_port_s *aice; - - LOG_DEBUG("aice_init_targets"); - - if (aice_num_of_target_id_codes == 0) { - res = aice_port->api->idcode(aice_target_id_codes, &aice_num_of_target_id_codes); - if (res != ERROR_OK) { - LOG_ERROR("<-- TARGET ERROR! Failed to identify AndesCore " - "JTAG Manufacture ID in the JTAG scan chain. " - "Failed to access EDM registers. -->"); - return res; - } - } - - for (target = all_targets; target; target = target->next) { - target->tap->idcode = aice_target_id_codes[target->tap->abs_chain_position]; - - unsigned ii, limit = target->tap->expected_ids_cnt; - int found = 0; - - for (ii = 0; ii < limit; ii++) { - uint32_t expected = target->tap->expected_ids[ii]; - - /* treat "-expected-id 0" as a "don't-warn" wildcard */ - if (!expected || (target->tap->idcode == expected)) { - found = 1; - break; - } - } - - if (found == 0) { - LOG_ERROR - ("aice_init_targets: target not found: idcode: %" PRIx32, - target->tap->idcode); - return ERROR_FAIL; - } - - aice = calloc(1, sizeof(struct aice_port_s)); - aice->port = aice_port; - aice->coreid = target->tap->abs_chain_position; - - target->tap->priv = aice; - target->tap->hasidcode = 1; - } - - return ERROR_OK; -} - -/***************************************************************************/ -/* End of External interface implementation */ - -/* initial aice - * 1. open usb - * 2. get/show version number - * 3. reset - */ -static int aice_init(void) -{ - if (aice_port->api->open(¶m) != ERROR_OK) { - LOG_ERROR("Cannot find AICE Interface! Please check " - "connection and permissions."); - return ERROR_JTAG_INIT_FAILED; - } - - aice_port->api->set_retry_times(retry_times); - aice_port->api->set_count_to_check_dbger(count_to_check_dbger); - - LOG_INFO("AICE JTAG Interface ready"); - - return ERROR_OK; -} - -/* cleanup aice resource - * close usb - */ -static int aice_quit(void) -{ - aice_port->api->close(); - return ERROR_OK; -} - -static int aice_execute_reset(struct jtag_command *cmd) -{ - static int last_trst; - int retval = ERROR_OK; - - LOG_DEBUG_IO("reset trst: %d", cmd->cmd.reset->trst); - - if (cmd->cmd.reset->trst != last_trst) { - if (cmd->cmd.reset->trst) - retval = aice_port->api->reset(); - - last_trst = cmd->cmd.reset->trst; - } - - return retval; -} - -static int aice_execute_command(struct jtag_command *cmd) -{ - int retval; - - switch (cmd->type) { - case JTAG_RESET: - retval = aice_execute_reset(cmd); - break; - default: - retval = ERROR_OK; - break; - } - return retval; -} - -/* aice has no need to implement jtag execution model -*/ -static int aice_execute_queue(void) -{ - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ - int retval; - - retval = ERROR_OK; - - while (cmd) { - if (aice_execute_command(cmd) != ERROR_OK) - retval = ERROR_JTAG_QUEUE_FAILED; - - cmd = cmd->next; - } - - return retval; -} - -/* set jtag frequency(base frequency/frequency divider) to your jtag adapter */ -static int aice_speed(int speed) -{ - return aice_port->api->set_jtag_clock(speed); -} - -/* convert jtag adapter frequency(base frequency/frequency divider) to - * human readable KHz value */ -static int aice_speed_div(int speed, int *khz) -{ - *khz = aice_khz_to_speed_map[speed]; - - return ERROR_OK; -} - -/* convert human readable KHz value to jtag adapter frequency - * (base frequency/frequency divider) */ -static int aice_khz(int khz, int *jtag_speed) -{ - int i; - for (i = 0 ; i < AICE_KHZ_TO_SPEED_MAP_SIZE ; i++) { - if (khz == aice_khz_to_speed_map[i]) { - if (i >= 8) - *jtag_speed = i | AICE_TCK_CONTROL_TCK3048; - else - *jtag_speed = i; - break; - } - } - - if (i == AICE_KHZ_TO_SPEED_MAP_SIZE) { - LOG_INFO("No support the jtag clock: %d", khz); - LOG_INFO("Supported jtag clocks are:"); - - for (i = 0 ; i < AICE_KHZ_TO_SPEED_MAP_SIZE ; i++) - LOG_INFO("* %d", aice_khz_to_speed_map[i]); - - return ERROR_FAIL; - } - - return ERROR_OK; -} - -int aice_scan_jtag_chain(void) -{ - LOG_DEBUG("=== %s ===", __func__); - uint8_t num_of_idcode = 0; - struct target *target; - - int res = aice_port->api->idcode(aice_target_id_codes, &num_of_idcode); - if (res != ERROR_OK) { - LOG_ERROR("<-- TARGET ERROR! Failed to identify AndesCore " - "JTAG Manufacture ID in the JTAG scan chain. " - "Failed to access EDM registers. -->"); - return res; - } - - for (unsigned int i = 0; i < num_of_idcode; i++) - LOG_DEBUG("id_codes[%u] = 0x%" PRIx32, i, aice_target_id_codes[i]); - - /* Update tap idcode */ - for (target = all_targets; target; target = target->next) - target->tap->idcode = aice_target_id_codes[target->tap->abs_chain_position]; - - return ERROR_OK; -} - -/***************************************************************************/ -/* Command handlers */ -COMMAND_HANDLER(aice_handle_aice_info_command) -{ - LOG_DEBUG("aice_handle_aice_info_command"); - - command_print(CMD, "Description: %s", param.device_desc); - command_print(CMD, "Serial number: %s", adapter_get_required_serial()); - if (strncmp(aice_port->name, "aice_pipe", 9) == 0) - command_print(CMD, "Adapter: %s", param.adapter_name); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_port_command) -{ - LOG_DEBUG("aice_handle_aice_port_command"); - - if (CMD_ARGC != 1) { - LOG_ERROR("Need exactly one argument to 'aice port'"); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - for (const struct aice_port *l = aice_port_get_list(); l->name; l++) { - if (strcmp(l->name, CMD_ARGV[0]) == 0) { - aice_port = l; - return ERROR_OK; - } - } - - LOG_ERROR("No AICE port '%s' found", CMD_ARGV[0]); - return ERROR_FAIL; -} - -COMMAND_HANDLER(aice_handle_aice_desc_command) -{ - LOG_DEBUG("aice_handle_aice_desc_command"); - - if (CMD_ARGC == 1) - param.device_desc = strdup(CMD_ARGV[0]); - else - LOG_ERROR("expected exactly one argument to aice desc <description>"); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_vid_pid_command) -{ - LOG_DEBUG("aice_handle_aice_vid_pid_command"); - - if (CMD_ARGC != 2) { - LOG_WARNING("ignoring extra IDs in aice vid_pid (maximum is 1 pair)"); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], param.vid); - COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], param.pid); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_adapter_command) -{ - LOG_DEBUG("aice_handle_aice_adapter_command"); - - if (CMD_ARGC == 1) - param.adapter_name = strdup(CMD_ARGV[0]); - else - LOG_ERROR("expected exactly one argument to aice adapter <adapter-name>"); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_retry_times_command) -{ - LOG_DEBUG("aice_handle_aice_retry_times_command"); - - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], retry_times); - else - LOG_ERROR("expected exactly one argument to aice retry_times <num_of_retry>"); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_count_to_check_dbger_command) -{ - LOG_DEBUG("aice_handle_aice_count_to_check_dbger_command"); - - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], count_to_check_dbger); - else - LOG_ERROR("expected exactly one argument to aice count_to_check_dbger " - "<count_of_checking>"); - - return ERROR_OK; -} - -COMMAND_HANDLER(aice_handle_aice_custom_srst_script_command) -{ - LOG_DEBUG("aice_handle_aice_custom_srst_script_command"); - - if (CMD_ARGC > 0) { - aice_port->api->set_custom_srst_script(CMD_ARGV[0]); - return ERROR_OK; - } - - return ERROR_FAIL; -} - -COMMAND_HANDLER(aice_handle_aice_custom_trst_script_command) -{ - LOG_DEBUG("aice_handle_aice_custom_trst_script_command"); - - if (CMD_ARGC > 0) { - aice_port->api->set_custom_trst_script(CMD_ARGV[0]); - return ERROR_OK; - } - - return ERROR_FAIL; -} - -COMMAND_HANDLER(aice_handle_aice_custom_restart_script_command) -{ - LOG_DEBUG("aice_handle_aice_custom_restart_script_command"); - - if (CMD_ARGC > 0) { - aice_port->api->set_custom_restart_script(CMD_ARGV[0]); - return ERROR_OK; - } - - return ERROR_FAIL; -} - -COMMAND_HANDLER(aice_handle_aice_reset_command) -{ - LOG_DEBUG("aice_handle_aice_reset_command"); - - return aice_port->api->reset(); -} - - -static const struct command_registration aice_subcommand_handlers[] = { - { - .name = "info", - .handler = &aice_handle_aice_info_command, - .mode = COMMAND_EXEC, - .help = "show aice info", - .usage = "", - }, - { - .name = "port", - .handler = &aice_handle_aice_port_command, - .mode = COMMAND_CONFIG, - .help = "set the port of the AICE", - .usage = "['aice_pipe'|'aice_usb']", - }, - { - .name = "desc", - .handler = &aice_handle_aice_desc_command, - .mode = COMMAND_CONFIG, - .help = "set the aice device description", - .usage = "[description string]", - }, - { - .name = "vid_pid", - .handler = &aice_handle_aice_vid_pid_command, - .mode = COMMAND_CONFIG, - .help = "the vendor and product ID of the AICE device", - .usage = "(vid pid)*", - }, - { - .name = "adapter", - .handler = &aice_handle_aice_adapter_command, - .mode = COMMAND_CONFIG, - .help = "set the file name of adapter", - .usage = "[adapter name]", - }, - { - .name = "retry_times", - .handler = &aice_handle_aice_retry_times_command, - .mode = COMMAND_CONFIG, - .help = "set retry times as AICE timeout", - .usage = "num_of_retry", - }, - { - .name = "count_to_check_dbger", - .handler = &aice_handle_aice_count_to_check_dbger_command, - .mode = COMMAND_CONFIG, - .help = "set retry times as checking $DBGER status", - .usage = "count_of_checking", - }, - { - .name = "custom_srst_script", - .handler = &aice_handle_aice_custom_srst_script_command, - .mode = COMMAND_CONFIG, - .usage = "script_file_name", - .help = "set custom srst script", - }, - { - .name = "custom_trst_script", - .handler = &aice_handle_aice_custom_trst_script_command, - .mode = COMMAND_CONFIG, - .usage = "script_file_name", - .help = "set custom trst script", - }, - { - .name = "custom_restart_script", - .handler = &aice_handle_aice_custom_restart_script_command, - .mode = COMMAND_CONFIG, - .usage = "script_file_name", - .help = "set custom restart script", - }, - { - .name = "reset", - .handler = &aice_handle_aice_reset_command, - .mode = COMMAND_EXEC, - .usage = "", - .help = "reset AICE", - }, - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration aice_command_handlers[] = { - { - .name = "aice", - .mode = COMMAND_ANY, - .help = "perform aice management", - .usage = "[subcommand]", - .chain = aice_subcommand_handlers, - }, - COMMAND_REGISTRATION_DONE -}; -/***************************************************************************/ -/* End of Command handlers */ - -static struct jtag_interface aice_interface = { - .execute_queue = aice_execute_queue, -}; - -struct adapter_driver aice_adapter_driver = { - .name = "aice", - .transports = aice_transports, - .commands = aice_command_handlers, - - .init = aice_init, - .quit = aice_quit, - .speed = aice_speed, /* set interface speed */ - .khz = aice_khz, /* convert khz to interface speed value */ - .speed_div = aice_speed_div, /* return readable value */ - - .jtag_ops = &aice_interface, -}; diff --git a/src/jtag/aice/aice_interface.h b/src/jtag/aice/aice_interface.h deleted file mode 100644 index 615e90f2e8..0000000000 --- a/src/jtag/aice/aice_interface.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_AICE_AICE_INTERFACE_H -#define OPENOCD_JTAG_AICE_AICE_INTERFACE_H - -int aice_init_targets(void); -int aice_scan_jtag_chain(void); - -#endif /* OPENOCD_JTAG_AICE_AICE_INTERFACE_H */ diff --git a/src/jtag/aice/aice_pipe.c b/src/jtag/aice/aice_pipe.c deleted file mode 100644 index 3651952381..0000000000 --- a/src/jtag/aice/aice_pipe.c +++ /dev/null @@ -1,884 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/system.h> - -#ifdef _WIN32 -#include <windows.h> -#else -#include <signal.h> -#endif - -#include <helper/log.h> -#include <helper/time_support.h> -#include "aice_port.h" -#include "aice_pipe.h" - -#define AICE_PIPE_MAXLINE 8192 - -#ifdef _WIN32 -PROCESS_INFORMATION proc_info; - -static HANDLE aice_pipe_output[2]; -static HANDLE aice_pipe_input[2]; - -static int aice_pipe_write(const void *buffer, int count) -{ - BOOL success; - DWORD written; - - success = WriteFile(aice_pipe_output[1], buffer, count, &written, NULL); - if (!success) { - LOG_ERROR("(WIN32) write to pipe failed, error code: 0x%08l" PRIx32, GetLastError()); - return -1; - } - - return written; -} - -static int aice_pipe_read(void *buffer, int count) -{ - BOOL success; - DWORD has_read; - - success = ReadFile(aice_pipe_input[0], buffer, count, &has_read, NULL); - if (!success || (has_read == 0)) { - LOG_ERROR("(WIN32) read from pipe failed, error code: 0x%08l" PRIx32, GetLastError()); - return -1; - } - - return has_read; -} - -static int aice_pipe_child_init(struct aice_port_param_s *param) -{ - STARTUPINFO start_info; - BOOL success; - - ZeroMemory(&proc_info, sizeof(PROCESS_INFORMATION)); - ZeroMemory(&start_info, sizeof(STARTUPINFO)); - start_info.cb = sizeof(STARTUPINFO); - start_info.hStdError = aice_pipe_input[1]; - start_info.hStdOutput = aice_pipe_input[1]; - start_info.hStdInput = aice_pipe_output[0]; - start_info.dwFlags |= STARTF_USESTDHANDLES; - - success = CreateProcess(NULL, - param->adapter_name, - NULL, - NULL, - TRUE, - 0, - NULL, - NULL, - &start_info, - &proc_info); - - if (!success) { - LOG_ERROR("Create new process failed"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_pipe_parent_init(struct aice_port_param_s *param) -{ - /* send open to adapter */ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_OPEN; - set_u16(command + 1, param->vid); - set_u16(command + 3, param->pid); - - if (aice_pipe_write(command, 5) != 5) { - LOG_ERROR("write failed\n"); - return ERROR_FAIL; - } - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) { - LOG_ERROR("read failed\n"); - return ERROR_FAIL; - } - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_open(struct aice_port_param_s *param) -{ - SECURITY_ATTRIBUTES attribute; - - attribute.nLength = sizeof(SECURITY_ATTRIBUTES); - attribute.bInheritHandle = TRUE; - attribute.lpSecurityDescriptor = NULL; - - if (!CreatePipe(&aice_pipe_output[0], &aice_pipe_output[1], - &attribute, AICE_PIPE_MAXLINE)) { - LOG_ERROR("Create pipes failed"); - return ERROR_FAIL; - } - if (!CreatePipe(&aice_pipe_input[0], &aice_pipe_input[1], - &attribute, AICE_PIPE_MAXLINE)) { - LOG_ERROR("Create pipes failed"); - return ERROR_FAIL; - } - - /* do not inherit aice_pipe_output[1] & aice_pipe_input[0] to child process */ - if (!SetHandleInformation(aice_pipe_output[1], HANDLE_FLAG_INHERIT, 0)) - return ERROR_FAIL; - if (!SetHandleInformation(aice_pipe_input[0], HANDLE_FLAG_INHERIT, 0)) - return ERROR_FAIL; - - aice_pipe_child_init(param); - - aice_pipe_parent_init(param); - - return ERROR_OK; -} - -#else - -static int aice_pipe_output[2]; -static int aice_pipe_input[2]; - -static int aice_pipe_write(const void *buffer, int count) -{ - if (write(aice_pipe_output[1], buffer, count) != count) { - LOG_ERROR("write to pipe failed"); - return -1; - } - - return count; -} - -static int aice_pipe_read(void *buffer, int count) -{ - int n; - int64_t then, cur; - - then = timeval_ms(); - - while (1) { - n = read(aice_pipe_input[0], buffer, count); - - if ((n == -1) && (errno == EAGAIN)) { - cur = timeval_ms(); - if (cur - then > 500) - keep_alive(); - continue; - } else if (n > 0) - break; - else { - LOG_ERROR("read from pipe failed"); - break; - } - } - - return n; -} - -static int aice_pipe_child_init(struct aice_port_param_s *param) -{ - close(aice_pipe_output[1]); - close(aice_pipe_input[0]); - - if (aice_pipe_output[0] != STDIN_FILENO) { - if (dup2(aice_pipe_output[0], STDIN_FILENO) != STDIN_FILENO) { - LOG_ERROR("Map aice_pipe to STDIN failed"); - return ERROR_FAIL; - } - close(aice_pipe_output[0]); - } - - if (aice_pipe_input[1] != STDOUT_FILENO) { - if (dup2(aice_pipe_input[1], STDOUT_FILENO) != STDOUT_FILENO) { - LOG_ERROR("Map aice_pipe to STDOUT failed"); - return ERROR_FAIL; - } - close(aice_pipe_input[1]); - } - - if (execl(param->adapter_name, param->adapter_name, (char *)0) < 0) { - LOG_ERROR("Execute aice_pipe failed"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_pipe_parent_init(struct aice_port_param_s *param) -{ - close(aice_pipe_output[0]); - close(aice_pipe_input[1]); - - /* set read end of pipe as non-blocking */ - if (fcntl(aice_pipe_input[0], F_SETFL, O_NONBLOCK)) - return ERROR_FAIL; - - /* send open to adapter */ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_OPEN; - set_u16(command + 1, param->vid); - set_u16(command + 3, param->pid); - - if (aice_pipe_write(command, 5) != 5) { - LOG_ERROR("write failed\n"); - return ERROR_FAIL; - } - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) { - LOG_ERROR("read failed\n"); - return ERROR_FAIL; - } - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static void sig_pipe(int signo) -{ - exit(1); -} - -static int aice_pipe_open(struct aice_port_param_s *param) -{ - pid_t pid; - - if (signal(SIGPIPE, sig_pipe) == SIG_ERR) { - LOG_ERROR("Register SIGPIPE handler failed"); - return ERROR_FAIL; - } - - if (pipe(aice_pipe_output) < 0 || pipe(aice_pipe_input) < 0) { - LOG_ERROR("Create pipes failed"); - return ERROR_FAIL; - } - - pid = fork(); - if (pid < 0) { - LOG_ERROR("Fork new process failed"); - return ERROR_FAIL; - } else if (pid == 0) { - if (aice_pipe_child_init(param) != ERROR_OK) { - LOG_ERROR("AICE_PIPE child process initial error"); - return ERROR_FAIL; - } else { - if (aice_pipe_parent_init(param) != ERROR_OK) { - LOG_ERROR("AICE_PIPE parent process initial error"); - return ERROR_FAIL; - } - } - } - - return ERROR_OK; -} -#endif - -static int aice_pipe_close(void) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_CLOSE; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) { -#ifdef _WIN32 - WaitForSingleObject(proc_info.hProcess, INFINITE); - CloseHandle(proc_info.hProcess); - CloseHandle(proc_info.hThread); -#endif - return ERROR_OK; - } else - return ERROR_FAIL; -} - -static int aice_pipe_idcode(uint32_t *idcode, uint8_t *num_of_idcode) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_IDCODE; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - *num_of_idcode = line[0]; - - if ((*num_of_idcode == 0) || (*num_of_idcode >= 16)) - return ERROR_FAIL; - - for (int i = 0 ; i < *num_of_idcode ; i++) - idcode[i] = get_u32(line + i * 4 + 1); - - return ERROR_OK; -} - -static int aice_pipe_state(uint32_t coreid, enum aice_target_state_s *state) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_STATE; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - *state = (enum aice_target_state_s)line[0]; - - return ERROR_OK; -} - -static int aice_pipe_reset(void) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_RESET; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_assert_srst(uint32_t coreid, enum aice_srst_type_s srst) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_ASSERT_SRST; - command[1] = srst; - - if (aice_pipe_write(command, 2) != 2) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_run(uint32_t coreid) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_RUN; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_halt(uint32_t coreid) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_HALT; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_READ_REG; - set_u32(command + 1, num); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - *val = get_u32(line); - - return ERROR_OK; -} - -static int aice_pipe_write_reg(uint32_t coreid, uint32_t num, uint32_t val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_WRITE_REG; - set_u32(command + 1, num); - set_u32(command + 5, val); - - if (aice_pipe_write(command, 9) != 9) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_READ_REG_64; - set_u32(command + 1, num); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - *val = (((uint64_t)get_u32(line + 4)) << 32) | get_u32(line); - - return ERROR_OK; -} - -static int aice_pipe_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_WRITE_REG_64; - set_u32(command + 1, num); - set_u32(command + 5, val & 0xFFFFFFFF); - set_u32(command + 9, (val >> 32) & 0xFFFFFFFF); - - if (aice_pipe_write(command, 13) != 9) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_step(uint32_t coreid) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_STEP; - - if (aice_pipe_write(command, 1) != 1) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_read_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, uint8_t *buffer) -{ - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_READ_MEM_UNIT; - set_u32(command + 1, addr); - set_u32(command + 5, size); - set_u32(command + 9, count); - - if (aice_pipe_write(command, 13) != 13) - return ERROR_FAIL; - - if (aice_pipe_read(buffer, size * count) < 0) - return ERROR_FAIL; - - return ERROR_OK; -} - -static int aice_pipe_write_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, const uint8_t *buffer) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_WRITE_MEM_UNIT; - set_u32(command + 1, addr); - set_u32(command + 5, size); - set_u32(command + 9, count); - - /* WRITE_MEM_UNIT|addr|size|count|data */ - memcpy(command + 13, buffer, size * count); - - if (aice_pipe_write(command, 13 + size * count) < 0) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; - - return ERROR_OK; -} - -static int aice_pipe_read_mem_bulk(uint32_t coreid, uint32_t addr, - uint32_t length, uint8_t *buffer) -{ - char line[AICE_PIPE_MAXLINE + 1]; - char command[AICE_PIPE_MAXLINE]; - uint32_t remain_len = length; - uint32_t prepare_len; - char *received_line; - uint32_t received_len; - int read_len; - - command[0] = AICE_READ_MEM_BULK; - set_u32(command + 1, addr); - set_u32(command + 5, length); - - if (aice_pipe_write(command, 9) < 0) - return ERROR_FAIL; - - while (remain_len > 0) { - if (remain_len > AICE_PIPE_MAXLINE) - prepare_len = AICE_PIPE_MAXLINE; - else - prepare_len = remain_len; - - prepare_len++; - received_len = 0; - received_line = line; - do { - read_len = aice_pipe_read(received_line, prepare_len - received_len); - if (read_len < 0) - return ERROR_FAIL; - received_line += read_len; - received_len += read_len; - } while (received_len < prepare_len); - - if (line[0] != AICE_OK) - return ERROR_FAIL; - - prepare_len--; - memcpy(buffer, line + 1, prepare_len); - remain_len -= prepare_len; - buffer += prepare_len; - } - - return ERROR_OK; -} - -static int aice_pipe_write_mem_bulk(uint32_t coreid, uint32_t addr, - uint32_t length, const uint8_t *buffer) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE + 4]; - uint32_t remain_len = length; - uint32_t written_len = 0; - uint32_t write_len; - - command[0] = AICE_WRITE_MEM_BULK; - set_u32(command + 1, addr); - set_u32(command + 5, length); - - /* Send command first */ - if (aice_pipe_write(command, 9) < 0) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_ERROR) - return ERROR_FAIL; - - while (remain_len > 0) { - if (remain_len > AICE_PIPE_MAXLINE) - write_len = AICE_PIPE_MAXLINE; - else - write_len = remain_len; - - set_u32(command, write_len); - memcpy(command + 4, buffer + written_len, write_len); /* data only */ - - if (aice_pipe_write(command, write_len + 4) < 0) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_ERROR) - return ERROR_FAIL; - - remain_len -= write_len; - written_len += write_len; - } - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_READ_DEBUG_REG; - set_u32(command + 1, addr); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - *val = get_u32(line); - - return ERROR_OK; -} - -static int aice_pipe_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_WRITE_DEBUG_REG; - set_u32(command + 1, addr); - set_u32(command + 5, val); - - if (aice_pipe_write(command, 9) != 9) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_set_jtag_clock(uint32_t a_clock) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_SET_JTAG_CLOCK; - set_u32(command + 1, a_clock); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_memory_access(uint32_t coreid, enum nds_memory_access access_channel) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_MEMORY_ACCESS; - set_u32(command + 1, access_channel); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_memory_mode(uint32_t coreid, enum nds_memory_select mem_select) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_MEMORY_MODE; - set_u32(command + 1, mem_select); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_read_tlb(uint32_t coreid, target_addr_t virtual_address, - target_addr_t *physical_address) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_READ_TLB; - set_u32(command + 1, virtual_address); - - if (aice_pipe_write(command, 5) != 5) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) { - *physical_address = get_u32(line + 1); - return ERROR_OK; - } else - return ERROR_FAIL; -} - -static int aice_pipe_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address) -{ - char line[AICE_PIPE_MAXLINE]; - char command[AICE_PIPE_MAXLINE]; - - command[0] = AICE_CACHE_CTL; - set_u32(command + 1, subtype); - set_u32(command + 5, address); - - if (aice_pipe_write(command, 9) != 9) - return ERROR_FAIL; - - if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) - return ERROR_FAIL; - - if (line[0] == AICE_OK) - return ERROR_OK; - else - return ERROR_FAIL; -} - -static int aice_pipe_set_retry_times(uint32_t a_retry_times) -{ - return ERROR_OK; -} - -/** */ -struct aice_port_api_s aice_pipe = { - /** */ - .open = aice_pipe_open, - /** */ - .close = aice_pipe_close, - /** */ - .idcode = aice_pipe_idcode, - /** */ - .set_jtag_clock = aice_pipe_set_jtag_clock, - /** */ - .state = aice_pipe_state, - /** */ - .reset = aice_pipe_reset, - /** */ - .assert_srst = aice_pipe_assert_srst, - /** */ - .run = aice_pipe_run, - /** */ - .halt = aice_pipe_halt, - /** */ - .step = aice_pipe_step, - /** */ - .read_reg = aice_pipe_read_reg, - /** */ - .write_reg = aice_pipe_write_reg, - /** */ - .read_reg_64 = aice_pipe_read_reg_64, - /** */ - .write_reg_64 = aice_pipe_write_reg_64, - /** */ - .read_mem_unit = aice_pipe_read_mem_unit, - /** */ - .write_mem_unit = aice_pipe_write_mem_unit, - /** */ - .read_mem_bulk = aice_pipe_read_mem_bulk, - /** */ - .write_mem_bulk = aice_pipe_write_mem_bulk, - /** */ - .read_debug_reg = aice_pipe_read_debug_reg, - /** */ - .write_debug_reg = aice_pipe_write_debug_reg, - - /** */ - .memory_access = aice_pipe_memory_access, - /** */ - .memory_mode = aice_pipe_memory_mode, - - /** */ - .read_tlb = aice_pipe_read_tlb, - - /** */ - .cache_ctl = aice_pipe_cache_ctl, - - /** */ - .set_retry_times = aice_pipe_set_retry_times, -}; diff --git a/src/jtag/aice/aice_pipe.h b/src/jtag/aice/aice_pipe.h deleted file mode 100644 index 5a1f4107f6..0000000000 --- a/src/jtag/aice/aice_pipe.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_AICE_AICE_PIPE_H -#define OPENOCD_JTAG_AICE_AICE_PIPE_H - -#include <helper/types.h> - -#define set_u32(buffer, value) h_u32_to_le((uint8_t *)buffer, value) -#define set_u16(buffer, value) h_u16_to_le((uint8_t *)buffer, value) -#define get_u32(buffer) le_to_h_u32((const uint8_t *)buffer) -#define get_u16(buffer) le_to_h_u16((const uint8_t *)buffer) - -extern struct aice_port_api_s aice_pipe; - -#endif /* OPENOCD_JTAG_AICE_AICE_PIPE_H */ diff --git a/src/jtag/aice/aice_port.c b/src/jtag/aice/aice_port.c deleted file mode 100644 index 29188d8439..0000000000 --- a/src/jtag/aice/aice_port.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/log.h> -#include "aice_usb.h" -#include "aice_pipe.h" -#include "aice_port.h" - -static const struct aice_port aice_ports[] = { - { - .name = "aice_usb", - .type = AICE_PORT_AICE_USB, - .api = &aice_usb_api, - }, - { - .name = "aice_pipe", - .type = AICE_PORT_AICE_PIPE, - .api = &aice_pipe, - }, - {.name = NULL, /* END OF TABLE */ }, -}; - -/** */ -const struct aice_port *aice_port_get_list(void) -{ - return aice_ports; -} diff --git a/src/jtag/aice/aice_port.h b/src/jtag/aice/aice_port.h deleted file mode 100644 index fb914d853b..0000000000 --- a/src/jtag/aice/aice_port.h +++ /dev/null @@ -1,224 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_AICE_AICE_PORT_H -#define OPENOCD_JTAG_AICE_AICE_PORT_H - -#include <target/nds32_edm.h> - -#define AICE_MAX_NUM_CORE (0x10) - -#define ERROR_AICE_DISCONNECT (-200) -#define ERROR_AICE_TIMEOUT (-201) - -enum aice_target_state_s { - AICE_DISCONNECT = 0, - AICE_TARGET_DETACH, - AICE_TARGET_UNKNOWN, - AICE_TARGET_RUNNING, - AICE_TARGET_HALTED, - AICE_TARGET_RESET, - AICE_TARGET_DEBUG_RUNNING, -}; - -enum aice_srst_type_s { - AICE_SRST = 0x1, - AICE_RESET_HOLD = 0x8, -}; - -enum aice_target_endian { - AICE_LITTLE_ENDIAN = 0, - AICE_BIG_ENDIAN, -}; - -enum aice_api_s { - AICE_OPEN = 0x0, - AICE_CLOSE, - AICE_RESET, - AICE_IDCODE, - AICE_SET_JTAG_CLOCK, - AICE_ASSERT_SRST, - AICE_RUN, - AICE_HALT, - AICE_STEP, - AICE_READ_REG, - AICE_WRITE_REG, - AICE_READ_REG_64, - AICE_WRITE_REG_64, - AICE_READ_MEM_UNIT, - AICE_WRITE_MEM_UNIT, - AICE_READ_MEM_BULK, - AICE_WRITE_MEM_BULK, - AICE_READ_DEBUG_REG, - AICE_WRITE_DEBUG_REG, - AICE_STATE, - AICE_MEMORY_ACCESS, - AICE_MEMORY_MODE, - AICE_READ_TLB, - AICE_CACHE_CTL, - AICE_SET_RETRY_TIMES, - AICE_PROGRAM_EDM, - AICE_SET_COMMAND_MODE, - AICE_EXECUTE, - AICE_SET_CUSTOM_SRST_SCRIPT, - AICE_SET_CUSTOM_TRST_SCRIPT, - AICE_SET_CUSTOM_RESTART_SCRIPT, - AICE_SET_COUNT_TO_CHECK_DBGER, - AICE_SET_DATA_ENDIAN, -}; - -enum aice_error_s { - AICE_OK, - AICE_ACK, - AICE_ERROR, -}; - -enum aice_cache_ctl_type { - AICE_CACHE_CTL_L1D_INVALALL = 0, - AICE_CACHE_CTL_L1D_VA_INVAL, - AICE_CACHE_CTL_L1D_WBALL, - AICE_CACHE_CTL_L1D_VA_WB, - AICE_CACHE_CTL_L1I_INVALALL, - AICE_CACHE_CTL_L1I_VA_INVAL, -}; - -enum aice_command_mode { - AICE_COMMAND_MODE_NORMAL, - AICE_COMMAND_MODE_PACK, - AICE_COMMAND_MODE_BATCH, -}; - -struct aice_port_param_s { - /** */ - const char *device_desc; - /** */ - uint16_t vid; - /** */ - uint16_t pid; - /** */ - char *adapter_name; -}; - -struct aice_port_s { - /** */ - uint32_t coreid; - /** */ - const struct aice_port *port; -}; - -/** */ -extern struct aice_port_api_s aice_usb_layout_api; - -/** */ -struct aice_port_api_s { - /** */ - int (*open)(struct aice_port_param_s *param); - /** */ - int (*close)(void); - /** */ - int (*reset)(void); - /** */ - int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode); - /** */ - int (*set_jtag_clock)(uint32_t a_clock); - /** */ - int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst); - /** */ - int (*run)(uint32_t coreid); - /** */ - int (*halt)(uint32_t coreid); - /** */ - int (*step)(uint32_t coreid); - /** */ - int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val); - /** */ - int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val); - /** */ - int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val); - /** */ - int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val); - /** */ - int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, uint8_t *buffer); - /** */ - int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, const uint8_t *buffer); - /** */ - int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length, - uint8_t *buffer); - /** */ - int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length, - const uint8_t *buffer); - /** */ - int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val); - /** */ - int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val); - - /** */ - int (*state)(uint32_t coreid, enum aice_target_state_s *state); - - /** */ - int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access); - /** */ - int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select); - - /** */ - int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address); - - /** */ - int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address); - - /** */ - int (*set_retry_times)(uint32_t a_retry_times); - - /** */ - int (*program_edm)(uint32_t coreid, char *command_sequence); - - /** */ - int (*set_command_mode)(enum aice_command_mode command_mode); - - /** */ - int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num); - - /** */ - int (*set_custom_srst_script)(const char *script); - - /** */ - int (*set_custom_trst_script)(const char *script); - - /** */ - int (*set_custom_restart_script)(const char *script); - - /** */ - int (*set_count_to_check_dbger)(uint32_t count_to_check); - - /** */ - int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian); - - /** */ - int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration, - uint32_t reg_no, uint32_t *samples, uint32_t *num_samples); -}; - -#define AICE_PORT_UNKNOWN 0 -#define AICE_PORT_AICE_USB 1 -#define AICE_PORT_AICE_PIPE 2 - -/** */ -struct aice_port { - /** */ - const char *name; - /** */ - int type; - /** */ - struct aice_port_api_s *const api; -}; - -/** */ -const struct aice_port *aice_port_get_list(void); - -#endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */ diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c deleted file mode 100644 index be853a8621..0000000000 --- a/src/jtag/aice/aice_transport.c +++ /dev/null @@ -1,432 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -/* project specific includes */ -#include <jtag/interface.h> -#include <jtag/tcl.h> -#include <transport/transport.h> -#include <target/target.h> -#include <jtag/aice/aice_interface.h> -#include <jtag/aice/aice_transport.h> -#include <string.h> - -/* */ -static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, - struct jtag_tap *tap) -{ - jim_wide w; - int e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", - n->name); - return e; - } - - unsigned expected_len = sizeof(uint32_t) * tap->expected_ids_cnt; - uint32_t *new_expected_ids = malloc(expected_len + sizeof(uint32_t)); - if (!new_expected_ids) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; - } - - assert(tap->expected_ids); - memcpy(new_expected_ids, tap->expected_ids, expected_len); - - new_expected_ids[tap->expected_ids_cnt] = w; - - free(tap->expected_ids); - tap->expected_ids = new_expected_ids; - tap->expected_ids_cnt++; - - return JIM_OK; -} - -#define NTAP_OPT_EXPECTED_ID 0 - -/* */ -static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) -{ - struct jtag_tap *tap; - int x; - int e; - struct jim_nvp *n; - char *cp; - const struct jim_nvp opts[] = { - {.name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID}, - {.name = NULL, .value = -1}, - }; - - tap = calloc(1, sizeof(struct jtag_tap)); - if (!tap) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; - } - - /* - * we expect CHIP + TAP + OPTIONS - * */ - if (goi->argc < 3) { - Jim_SetResultFormatted(goi->interp, - "Missing CHIP TAP OPTIONS ...."); - free(tap); - return JIM_ERR; - } - - const char *tmp; - jim_getopt_string(goi, &tmp, NULL); - tap->chip = strdup(tmp); - - jim_getopt_string(goi, &tmp, NULL); - tap->tapname = strdup(tmp); - - /* name + dot + name + null */ - x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1; - cp = malloc(x); - sprintf(cp, "%s.%s", tap->chip, tap->tapname); - tap->dotted_name = cp; - - LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params", - tap->chip, tap->tapname, tap->dotted_name, goi->argc); - - while (goi->argc) { - e = jim_getopt_nvp(goi, opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, opts, 0); - free(cp); - free(tap); - return e; - } - LOG_DEBUG("Processing option: %s", n->name); - switch (n->value) { - case NTAP_OPT_EXPECTED_ID: - e = jim_newtap_expected_id(n, goi, tap); - if (e != JIM_OK) { - free(cp); - free(tap); - return e; - } - break; - } /* switch (n->value) */ - } /* while (goi->argc) */ - - /* default is enabled-after-reset */ - tap->enabled = !tap->disabled_after_reset; - - jtag_tap_init(tap); - return JIM_OK; -} - -/* */ -static int jim_aice_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - return jim_aice_newtap_cmd(&goi); -} - -/* */ -COMMAND_HANDLER(handle_aice_init_command) -{ - if (CMD_ARGC != 0) - return ERROR_COMMAND_SYNTAX_ERROR; - - static bool jtag_initialized; - if (jtag_initialized) { - LOG_INFO("'jtag init' has already been called"); - return ERROR_OK; - } - jtag_initialized = true; - - LOG_DEBUG("Initializing jtag devices..."); - return jtag_init(CMD_CTX); -} - -COMMAND_HANDLER(handle_scan_chain_command) -{ - struct jtag_tap *tap; - char expected_id[12]; - - aice_scan_jtag_chain(); - tap = jtag_all_taps(); - command_print(CMD, - " TapName Enabled IdCode Expected IrLen IrCap IrMask"); - command_print(CMD, - "-- ------------------- -------- ---------- ---------- ----- ----- ------"); - - while (tap) { - uint32_t expected, expected_mask, ii; - - snprintf(expected_id, sizeof(expected_id), "0x%08x", - (unsigned)((tap->expected_ids_cnt > 0) - ? tap->expected_ids[0] - : 0)); - if (tap->ignore_version) - expected_id[2] = '*'; - - expected = buf_get_u32(tap->expected, 0, tap->ir_length); - expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length); - - command_print(CMD, - "%2d %-18s %c 0x%08x %s %5d 0x%02x 0x%02x", - tap->abs_chain_position, - tap->dotted_name, - tap->enabled ? 'Y' : 'n', - (unsigned int)(tap->idcode), - expected_id, - (unsigned int)(tap->ir_length), - (unsigned int)(expected), - (unsigned int)(expected_mask)); - - for (ii = 1; ii < tap->expected_ids_cnt; ii++) { - snprintf(expected_id, sizeof(expected_id), "0x%08x", - (unsigned) tap->expected_ids[ii]); - if (tap->ignore_version) - expected_id[2] = '*'; - - command_print(CMD, - " %s", - expected_id); - } - - tap = tap->next_tap; - } - - return ERROR_OK; -} - -static int jim_aice_arp_init(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - LOG_DEBUG("No implement: jim_aice_arp_init"); - - return JIM_OK; -} - -/* */ -static int aice_init_reset(struct command_context *cmd_ctx) -{ - LOG_DEBUG("Initializing with hard TRST+SRST reset"); - - int retval; - enum reset_types jtag_reset_config = jtag_get_reset_config(); - - jtag_add_reset(1, 0); /* TAP_RESET */ - if (jtag_reset_config & RESET_HAS_SRST) { - jtag_add_reset(1, 1); - if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) - jtag_add_reset(0, 1); - } - jtag_add_reset(0, 0); - retval = jtag_execute_queue(); - if (retval != ERROR_OK) - return retval; - - return ERROR_OK; -} - -/* */ -static int jim_aice_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - int e = ERROR_OK; - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv - 1, "(no params)"); - return JIM_ERR; - } - struct command_context *context = current_command_context(interp); - e = aice_init_reset(context); - - if (e != ERROR_OK) { - Jim_Obj *obj = Jim_NewIntObj(goi.interp, e); - Jim_SetResultFormatted(goi.interp, "error: %#s", obj); - return JIM_ERR; - } - return JIM_OK; -} - -static int jim_aice_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(goi.interp, Jim_NewListObj(goi.interp, NULL, 0)); - struct jtag_tap *tap; - - for (tap = jtag_all_taps(); tap; tap = tap->next_tap) - Jim_ListAppendElement(goi.interp, - Jim_GetResult(goi.interp), - Jim_NewStringObj(goi.interp, - tap->dotted_name, -1)); - - return JIM_OK; -} - -/* */ -static const struct command_registration aice_transport_jtag_subcommand_handlers[] = { - { - .name = "init", - .mode = COMMAND_ANY, - .handler = handle_aice_init_command, - .help = "initialize jtag scan chain", - .usage = "" - }, - { - .name = "arp_init", - .mode = COMMAND_ANY, - .jim_handler = jim_aice_arp_init, - .help = "Validates JTAG scan chain against the list of " - "declared TAPs.", - }, - { - .name = "arp_init-reset", - .mode = COMMAND_ANY, - .jim_handler = jim_aice_arp_init_reset, - .help = "Uses TRST and SRST to try resetting everything on " - "the JTAG scan chain, then performs 'jtag arp_init'." - }, - { - .name = "newtap", - .mode = COMMAND_CONFIG, - .jim_handler = jim_aice_newtap, - .help = "Create a new TAP instance named basename.tap_type, " - "and appends it to the scan chain.", - .usage = "basename tap_type ['-expected_id' number]" - }, - { - .name = "tapisenabled", - .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, - .help = "Returns a Tcl boolean (0/1) indicating whether " - "the TAP is enabled (1) or not (0).", - .usage = "tap_name", - }, - { - .name = "tapenable", - .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, - .help = "Try to enable the specified TAP using the " - "'tap-enable' TAP event.", - .usage = "tap_name", - }, - { - .name = "tapdisable", - .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, - .help = "Try to disable the specified TAP using the " - "'tap-disable' TAP event.", - .usage = "tap_name", - }, - { - .name = "configure", - .mode = COMMAND_ANY, - .jim_handler = jim_jtag_configure, - .help = "Provide a Tcl handler for the specified " - "TAP event.", - .usage = "tap_name '-event' event_name handler", - }, - { - .name = "cget", - .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_configure, - .help = "Return any Tcl handler for the specified " - "TAP event.", - .usage = "tap_name '-event' event_name", - }, - { - .name = "names", - .mode = COMMAND_ANY, - .jim_handler = jim_aice_names, - .help = "Returns list of all JTAG tap names.", - }, - { - .name = "scan_chain", - .handler = handle_scan_chain_command, - .mode = COMMAND_ANY, - .help = "print current scan chain configuration", - .usage = "" - }, - - COMMAND_REGISTRATION_DONE -}; - -/* */ -static const struct command_registration aice_transport_command_handlers[] = { - { - .name = "jtag", - .mode = COMMAND_ANY, - .usage = "", - .chain = aice_transport_jtag_subcommand_handlers, - }, - COMMAND_REGISTRATION_DONE - -}; - -/* */ -static int aice_transport_register_commands(struct command_context *cmd_ctx) -{ - return register_commands(cmd_ctx, NULL, aice_transport_command_handlers); -} - -/* */ -static int aice_transport_init(struct command_context *cmd_ctx) -{ - LOG_DEBUG("aice_transport_init"); - struct target *t = get_current_target(cmd_ctx); - struct transport *transport; - - if (!t) { - LOG_ERROR("no current target"); - return ERROR_FAIL; - } - - transport = get_current_transport(); - - if (!transport) { - LOG_ERROR("no transport selected"); - return ERROR_FAIL; - } - - LOG_DEBUG("current transport %s", transport->name); - - return aice_init_targets(); -} - -/* */ -static int aice_transport_select(struct command_context *ctx) -{ - LOG_DEBUG("aice_transport_select"); - - int retval; - - retval = aice_transport_register_commands(ctx); - - if (retval != ERROR_OK) - return retval; - - return ERROR_OK; -} - -static struct transport aice_jtag_transport = { - .name = "aice_jtag", - .select = aice_transport_select, - .init = aice_transport_init, -}; - -const char *aice_transports[] = { "aice_jtag", NULL }; - -static void aice_constructor(void) __attribute__((constructor)); -static void aice_constructor(void) -{ - transport_register(&aice_jtag_transport); -} diff --git a/src/jtag/aice/aice_transport.h b/src/jtag/aice/aice_transport.h deleted file mode 100644 index b000031982..0000000000 --- a/src/jtag/aice/aice_transport.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_AICE_AICE_TRANSPORT_H -#define OPENOCD_JTAG_AICE_AICE_TRANSPORT_H - -extern const char *aice_transports[]; - -#endif /* OPENOCD_JTAG_AICE_AICE_TRANSPORT_H */ diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c deleted file mode 100644 index 66cd07f630..0000000000 --- a/src/jtag/aice/aice_usb.c +++ /dev/null @@ -1,4099 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/system.h> -#include <jtag/drivers/libusb_helper.h> -#include <helper/log.h> -#include <helper/time_support.h> -#include <target/target.h> -#include <jtag/jtag.h> -#include <target/nds32_insn.h> -#include <target/nds32_reg.h> -#include "aice_usb.h" - - -/* Global USB buffers */ -static uint8_t usb_in_buffer[AICE_IN_BUFFER_SIZE]; -static uint8_t usb_out_buffer[AICE_OUT_BUFFER_SIZE]; -static uint32_t jtag_clock; -static struct aice_usb_handler_s aice_handler; -/* AICE max retry times. If AICE command timeout, retry it. */ -static int aice_max_retry_times = 50; -/* Default endian is little endian. */ -static enum aice_target_endian data_endian; - -/* Constants for AICE command format length */ -#define AICE_FORMAT_HTDA (3) -#define AICE_FORMAT_HTDC (7) -#define AICE_FORMAT_HTDMA (4) -#define AICE_FORMAT_HTDMB (8) -#define AICE_FORMAT_HTDMC (8) -#define AICE_FORMAT_HTDMD (12) -#define AICE_FORMAT_DTHA (6) -#define AICE_FORMAT_DTHB (2) -#define AICE_FORMAT_DTHMA (8) -#define AICE_FORMAT_DTHMB (4) - -/* Constants for AICE command */ -#define AICE_CMD_SCAN_CHAIN 0x00 -#define AICE_CMD_T_READ_MISC 0x20 -#define AICE_CMD_T_READ_EDMSR 0x21 -#define AICE_CMD_T_READ_DTR 0x22 -#define AICE_CMD_T_READ_MEM_B 0x24 -#define AICE_CMD_T_READ_MEM_H 0x25 -#define AICE_CMD_T_READ_MEM 0x26 -#define AICE_CMD_T_FASTREAD_MEM 0x27 -#define AICE_CMD_T_WRITE_MISC 0x28 -#define AICE_CMD_T_WRITE_EDMSR 0x29 -#define AICE_CMD_T_WRITE_DTR 0x2A -#define AICE_CMD_T_WRITE_DIM 0x2B -#define AICE_CMD_T_WRITE_MEM_B 0x2C -#define AICE_CMD_T_WRITE_MEM_H 0x2D -#define AICE_CMD_T_WRITE_MEM 0x2E -#define AICE_CMD_T_FASTWRITE_MEM 0x2F -#define AICE_CMD_T_EXECUTE 0x3E -#define AICE_CMD_READ_CTRL 0x50 -#define AICE_CMD_WRITE_CTRL 0x51 -#define AICE_CMD_BATCH_BUFFER_READ 0x60 -#define AICE_CMD_READ_DTR_TO_BUFFER 0x61 -#define AICE_CMD_BATCH_BUFFER_WRITE 0x68 -#define AICE_CMD_WRITE_DTR_FROM_BUFFER 0x69 - -/***************************************************************************/ -/* AICE commands' pack/unpack functions */ -static void aice_pack_htda(uint8_t cmd_code, uint8_t extra_word_length, - uint32_t address) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = extra_word_length; - usb_out_buffer[2] = (uint8_t)(address & 0xFF); -} - -static void aice_pack_htdc(uint8_t cmd_code, uint8_t extra_word_length, - uint32_t address, uint32_t word, enum aice_target_endian access_endian) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = extra_word_length; - usb_out_buffer[2] = (uint8_t)(address & 0xFF); - if (access_endian == AICE_BIG_ENDIAN) { - usb_out_buffer[6] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[4] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[3] = (uint8_t)(word & 0xFF); - } else { - usb_out_buffer[3] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[4] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[6] = (uint8_t)(word & 0xFF); - } -} - -static void aice_pack_htdma(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = (uint8_t)(address & 0xFF); -} - -static void aice_pack_htdmb(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = 0; - usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF); - usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF); - usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF); - usb_out_buffer[7] = (uint8_t)(address & 0xFF); -} - -static void aice_pack_htdmc(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address, uint32_t word, - enum aice_target_endian access_endian) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = (uint8_t)(address & 0xFF); - if (access_endian == AICE_BIG_ENDIAN) { - usb_out_buffer[7] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[6] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[4] = (uint8_t)(word & 0xFF); - } else { - usb_out_buffer[4] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[6] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[7] = (uint8_t)(word & 0xFF); - } -} - -static void aice_pack_htdmc_multiple_data(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address, uint32_t *word, - uint8_t num_of_words, enum aice_target_endian access_endian) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = (uint8_t)(address & 0xFF); - - uint8_t i; - for (i = 0 ; i < num_of_words ; i++, word++) { - if (access_endian == AICE_BIG_ENDIAN) { - usb_out_buffer[7 + i * 4] = (uint8_t)((*word >> 24) & 0xFF); - usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 16) & 0xFF); - usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 8) & 0xFF); - usb_out_buffer[4 + i * 4] = (uint8_t)(*word & 0xFF); - } else { - usb_out_buffer[4 + i * 4] = (uint8_t)((*word >> 24) & 0xFF); - usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 16) & 0xFF); - usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 8) & 0xFF); - usb_out_buffer[7 + i * 4] = (uint8_t)(*word & 0xFF); - } - } -} - -static void aice_pack_htdmd(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address, uint32_t word, - enum aice_target_endian access_endian) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = 0; - usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF); - usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF); - usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF); - usb_out_buffer[7] = (uint8_t)(address & 0xFF); - if (access_endian == AICE_BIG_ENDIAN) { - usb_out_buffer[11] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[10] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[9] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[8] = (uint8_t)(word & 0xFF); - } else { - usb_out_buffer[8] = (uint8_t)((word >> 24) & 0xFF); - usb_out_buffer[9] = (uint8_t)((word >> 16) & 0xFF); - usb_out_buffer[10] = (uint8_t)((word >> 8) & 0xFF); - usb_out_buffer[11] = (uint8_t)(word & 0xFF); - } -} - -static void aice_pack_htdmd_multiple_data(uint8_t cmd_code, uint8_t target_id, - uint8_t extra_word_length, uint32_t address, const uint8_t *word, - enum aice_target_endian access_endian) -{ - usb_out_buffer[0] = cmd_code; - usb_out_buffer[1] = target_id; - usb_out_buffer[2] = extra_word_length; - usb_out_buffer[3] = 0; - usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF); - usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF); - usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF); - usb_out_buffer[7] = (uint8_t)(address & 0xFF); - - uint32_t i; - /* num_of_words may be over 0xFF, so use uint32_t */ - uint32_t num_of_words = extra_word_length + 1; - - for (i = 0 ; i < num_of_words ; i++, word += 4) { - if (access_endian == AICE_BIG_ENDIAN) { - usb_out_buffer[11 + i * 4] = word[3]; - usb_out_buffer[10 + i * 4] = word[2]; - usb_out_buffer[9 + i * 4] = word[1]; - usb_out_buffer[8 + i * 4] = word[0]; - } else { - usb_out_buffer[8 + i * 4] = word[3]; - usb_out_buffer[9 + i * 4] = word[2]; - usb_out_buffer[10 + i * 4] = word[1]; - usb_out_buffer[11 + i * 4] = word[0]; - } - } -} - -static void aice_unpack_dtha(uint8_t *cmd_ack_code, uint8_t *extra_word_length, - uint32_t *word, enum aice_target_endian access_endian) -{ - *cmd_ack_code = usb_in_buffer[0]; - *extra_word_length = usb_in_buffer[1]; - - if (access_endian == AICE_BIG_ENDIAN) { - *word = (usb_in_buffer[5] << 24) | - (usb_in_buffer[4] << 16) | - (usb_in_buffer[3] << 8) | - (usb_in_buffer[2]); - } else { - *word = (usb_in_buffer[2] << 24) | - (usb_in_buffer[3] << 16) | - (usb_in_buffer[4] << 8) | - (usb_in_buffer[5]); - } -} - -static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code, - uint8_t *extra_word_length, uint32_t *word, uint8_t num_of_words, - enum aice_target_endian access_endian) -{ - *cmd_ack_code = usb_in_buffer[0]; - *extra_word_length = usb_in_buffer[1]; - - uint8_t i; - for (i = 0 ; i < num_of_words ; i++, word++) { - if (access_endian == AICE_BIG_ENDIAN) { - *word = (usb_in_buffer[5 + i * 4] << 24) | - (usb_in_buffer[4 + i * 4] << 16) | - (usb_in_buffer[3 + i * 4] << 8) | - (usb_in_buffer[2 + i * 4]); - } else { - *word = (usb_in_buffer[2 + i * 4] << 24) | - (usb_in_buffer[3 + i * 4] << 16) | - (usb_in_buffer[4 + i * 4] << 8) | - (usb_in_buffer[5 + i * 4]); - } - } -} - -static void aice_unpack_dthb(uint8_t *cmd_ack_code, uint8_t *extra_word_length) -{ - *cmd_ack_code = usb_in_buffer[0]; - *extra_word_length = usb_in_buffer[1]; -} - -static void aice_unpack_dthma(uint8_t *cmd_ack_code, uint8_t *target_id, - uint8_t *extra_word_length, uint32_t *word, - enum aice_target_endian access_endian) -{ - *cmd_ack_code = usb_in_buffer[0]; - *target_id = usb_in_buffer[1]; - *extra_word_length = usb_in_buffer[2]; - if (access_endian == AICE_BIG_ENDIAN) { - *word = (usb_in_buffer[7] << 24) | - (usb_in_buffer[6] << 16) | - (usb_in_buffer[5] << 8) | - (usb_in_buffer[4]); - } else { - *word = (usb_in_buffer[4] << 24) | - (usb_in_buffer[5] << 16) | - (usb_in_buffer[6] << 8) | - (usb_in_buffer[7]); - } -} - -static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code, - uint8_t *target_id, uint8_t *extra_word_length, uint8_t *word, - enum aice_target_endian access_endian) -{ - *cmd_ack_code = usb_in_buffer[0]; - *target_id = usb_in_buffer[1]; - *extra_word_length = usb_in_buffer[2]; - if (access_endian == AICE_BIG_ENDIAN) { - word[0] = usb_in_buffer[4]; - word[1] = usb_in_buffer[5]; - word[2] = usb_in_buffer[6]; - word[3] = usb_in_buffer[7]; - } else { - word[0] = usb_in_buffer[7]; - word[1] = usb_in_buffer[6]; - word[2] = usb_in_buffer[5]; - word[3] = usb_in_buffer[4]; - } - word += 4; - - uint8_t i; - for (i = 0; i < *extra_word_length; i++) { - if (access_endian == AICE_BIG_ENDIAN) { - word[0] = usb_in_buffer[8 + i * 4]; - word[1] = usb_in_buffer[9 + i * 4]; - word[2] = usb_in_buffer[10 + i * 4]; - word[3] = usb_in_buffer[11 + i * 4]; - } else { - word[0] = usb_in_buffer[11 + i * 4]; - word[1] = usb_in_buffer[10 + i * 4]; - word[2] = usb_in_buffer[9 + i * 4]; - word[3] = usb_in_buffer[8 + i * 4]; - } - word += 4; - } -} - -static void aice_unpack_dthmb(uint8_t *cmd_ack_code, uint8_t *target_id, - uint8_t *extra_word_length) -{ - *cmd_ack_code = usb_in_buffer[0]; - *target_id = usb_in_buffer[1]; - *extra_word_length = usb_in_buffer[2]; -} - -/***************************************************************************/ -/* End of AICE commands' pack/unpack functions */ - -/* calls the given usb_bulk_* function, allowing for the data to - * trickle in with some timeouts */ -static int usb_bulk_with_retries( - int (*f)(struct libusb_device_handle *, int, char *, int, int, int *), - struct libusb_device_handle *dev, int ep, - char *bytes, int size, int timeout, int *transferred) -{ - int tries = 3, count = 0; - - while (tries && (count < size)) { - int result, ret; - - ret = f(dev, ep, bytes + count, size - count, timeout, &result); - if (ret == ERROR_OK) - count += result; - else if ((ret != ERROR_TIMEOUT_REACHED) || !--tries) - return ret; - } - - *transferred = count; - return ERROR_OK; -} - -static int wrap_usb_bulk_write(struct libusb_device_handle *dev, int ep, - char *buff, int size, int timeout, int *transferred) -{ - - /* usb_bulk_write() takes const char *buff */ - jtag_libusb_bulk_write(dev, ep, buff, size, timeout, transferred); - - return 0; -} - -static inline int usb_bulk_write_ex(struct libusb_device_handle *dev, int ep, - char *bytes, int size, int timeout) -{ - int tr = 0; - - usb_bulk_with_retries(&wrap_usb_bulk_write, - dev, ep, bytes, size, timeout, &tr); - return tr; -} - -static inline int usb_bulk_read_ex(struct libusb_device_handle *dev, int ep, - char *bytes, int size, int timeout) -{ - int tr = 0; - usb_bulk_with_retries(&jtag_libusb_bulk_read, - dev, ep, bytes, size, timeout, &tr); - return tr; -} - -/* Write data from out_buffer to USB. */ -static int aice_usb_write(uint8_t *out_buffer, int out_length) -{ - int result; - - if (out_length > AICE_OUT_BUFFER_SIZE) { - LOG_ERROR("aice_write illegal out_length=%i (max=%i)", - out_length, AICE_OUT_BUFFER_SIZE); - return -1; - } - - result = usb_bulk_write_ex(aice_handler.usb_handle, aice_handler.usb_write_ep, - (char *)out_buffer, out_length, AICE_USB_TIMEOUT); - - LOG_DEBUG_IO("aice_usb_write, out_length = %i, result = %i", - out_length, result); - - return result; -} - -/* Read data from USB into in_buffer. */ -static int aice_usb_read(uint8_t *in_buffer, int expected_size) -{ - int result = usb_bulk_read_ex(aice_handler.usb_handle, aice_handler.usb_read_ep, - (char *)in_buffer, expected_size, AICE_USB_TIMEOUT); - - LOG_DEBUG_IO("aice_usb_read, result = %d", result); - - return result; -} - -static uint8_t usb_out_packets_buffer[AICE_OUT_PACKETS_BUFFER_SIZE]; -static uint8_t usb_in_packets_buffer[AICE_IN_PACKETS_BUFFER_SIZE]; -static uint32_t usb_out_packets_buffer_length; -static uint32_t usb_in_packets_buffer_length; -static enum aice_command_mode aice_command_mode; - -static int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, - uint32_t num_of_words); - -static int aice_usb_packet_flush(void) -{ - if (usb_out_packets_buffer_length == 0) - return 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)"); - - if (aice_usb_write(usb_out_packets_buffer, - usb_out_packets_buffer_length) < 0) - return ERROR_FAIL; - - if (aice_usb_read(usb_in_packets_buffer, - usb_in_packets_buffer_length) < 0) - return ERROR_FAIL; - - usb_out_packets_buffer_length = 0; - usb_in_packets_buffer_length = 0; - - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)"); - - /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */ - if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0, - usb_out_packets_buffer, - (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK) - return ERROR_FAIL; - - usb_out_packets_buffer_length = 0; - usb_in_packets_buffer_length = 0; - - /* enable BATCH command */ - aice_command_mode = AICE_COMMAND_MODE_NORMAL; - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL, 0x80000000) != ERROR_OK) - return ERROR_FAIL; - aice_command_mode = AICE_COMMAND_MODE_BATCH; - - /* wait 1 second (AICE bug, workaround) */ - alive_sleep(1000); - - /* check status */ - uint32_t i; - uint32_t batch_status; - - i = 0; - while (1) { - int retval = aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status); - if (retval != ERROR_OK) - return retval; - - if (batch_status & 0x1) - return ERROR_OK; - else if (batch_status & 0xE) - return ERROR_FAIL; - - if ((i % 30) == 0) - keep_alive(); - - i++; - } - } - - return ERROR_OK; -} - -static int aice_usb_packet_append(uint8_t *out_buffer, int out_length, int in_length) -{ - uint32_t max_packet_size = AICE_OUT_PACKETS_BUFFER_SIZE; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - max_packet_size = AICE_OUT_PACK_COMMAND_SIZE; - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - max_packet_size = AICE_OUT_BATCH_COMMAND_SIZE; - } else { - /* AICE_COMMAND_MODE_NORMAL */ - if (aice_usb_packet_flush() != ERROR_OK) - return ERROR_FAIL; - } - - if (usb_out_packets_buffer_length + out_length > max_packet_size) - if (aice_usb_packet_flush() != ERROR_OK) { - LOG_DEBUG("Flush usb packets failed"); - return ERROR_FAIL; - } - - LOG_DEBUG("Append usb packets 0x%02x", out_buffer[0]); - - memcpy(usb_out_packets_buffer + usb_out_packets_buffer_length, out_buffer, out_length); - usb_out_packets_buffer_length += out_length; - usb_in_packets_buffer_length += in_length; - - return ERROR_OK; -} - -/***************************************************************************/ -/* AICE commands */ -static int aice_reset_box(void) -{ - if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS, 0x1) != ERROR_OK) - return ERROR_FAIL; - - /* turn off FASTMODE */ - uint32_t pin_status; - if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status) - != ERROR_OK) - return ERROR_FAIL; - - if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x2)) - != ERROR_OK) - return ERROR_FAIL; - - return ERROR_OK; -} - -static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htda(AICE_CMD_SCAN_CHAIN, 0x0F, 0x0); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA); - - LOG_DEBUG("SCAN_CHAIN, length: 0x0F"); - - /** TODO: modify receive length */ - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA); - if (result != AICE_FORMAT_DTHA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - aice_unpack_dtha_multiple_data(&cmd_ack_code, num_of_ids, id_codes, - 0x10, AICE_LITTLE_ENDIAN); - - if (cmd_ack_code != AICE_CMD_SCAN_CHAIN) { - - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_SCAN_CHAIN, cmd_ack_code); - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - continue; - } - - LOG_DEBUG("SCAN_CHAIN response, # of IDs: %" PRIu8, *num_of_ids); - - if (*num_of_ids == 0xFF) { - LOG_ERROR("No target connected"); - return ERROR_FAIL; - } else if (*num_of_ids == AICE_MAX_NUM_CORE) { - LOG_INFO("The ice chain over 16 targets"); - } else { - (*num_of_ids)++; - } - break; - } while (1); - - return ERROR_OK; -} - -int aice_read_ctrl(uint32_t address, uint32_t *data) -{ - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - aice_pack_htda(AICE_CMD_READ_CTRL, 0, address); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA); - - LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32, address); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA); - if (result != AICE_FORMAT_DTHA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - aice_unpack_dtha(&cmd_ack_code, &extra_length, data, AICE_LITTLE_ENDIAN); - - LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32, *data); - - if (cmd_ack_code != AICE_CMD_READ_CTRL) { - LOG_ERROR("aice command error (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_READ_CTRL, cmd_ack_code); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -int aice_write_ctrl(uint32_t address, uint32_t data) -{ - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDC, - AICE_FORMAT_DTHB); - } - - aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDC); - - LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHB); - if (result != AICE_FORMAT_DTHB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - aice_unpack_dthb(&cmd_ack_code, &extra_length); - - LOG_DEBUG("WRITE_CTRL response"); - - if (cmd_ack_code != AICE_CMD_WRITE_CTRL) { - LOG_ERROR("aice command error (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_WRITE_CTRL, cmd_ack_code); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_read_dtr(uint8_t target_id, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdma(AICE_CMD_T_READ_DTR, target_id, 0, 0); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("READ_DTR, COREID: %" PRIu8, target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, AICE_LITTLE_ENDIAN); - - if (cmd_ack_code == AICE_CMD_T_READ_DTR) { - LOG_DEBUG("READ_DTR response, data: 0x%" PRIx32, *data); - break; - } else { - - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_DTR, cmd_ack_code); - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8, target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_READ_DTR_TO_BUFFER) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_write_dtr(uint8_t target_id, uint32_t data) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC); - - LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8 ", data: 0x%" PRIx32, target_id, data); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_DTR) { - LOG_DEBUG("WRITE_DTR response"); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_DTR, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8 "", target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_WRITE_DTR_FROM_BUFFER) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdma(AICE_CMD_T_READ_MISC, target_id, 0, address); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("READ_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_AICE_DISCONNECT; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, AICE_LITTLE_ENDIAN); - - if (cmd_ack_code == AICE_CMD_T_READ_MISC) { - LOG_DEBUG("READ_MISC response, data: 0x%" PRIx32, *data); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_MISC, cmd_ack_code); - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, data, - AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, - data, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC); - - LOG_DEBUG("WRITE_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32, - target_id, address, data); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_MISC) { - LOG_DEBUG("WRITE_MISC response"); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_MISC, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdma(AICE_CMD_T_READ_EDMSR, target_id, 0, address); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, AICE_LITTLE_ENDIAN); - - if (cmd_ack_code == AICE_CMD_T_READ_EDMSR) { - LOG_DEBUG("READ_EDMSR response, data: 0x%" PRIx32, *data); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_EDMSR, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, data, - AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, - data, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC); - - LOG_DEBUG("WRITE_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32, - target_id, address, data); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_EDMSR) { - LOG_DEBUG("WRITE_EDMSR response"); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_EDMSR, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_switch_to_big_endian(uint32_t *word, uint8_t num_of_words) -{ - uint32_t tmp; - - for (uint8_t i = 0 ; i < num_of_words ; i++) { - tmp = ((word[i] >> 24) & 0x000000FF) | - ((word[i] >> 8) & 0x0000FF00) | - ((word[i] << 8) & 0x00FF0000) | - ((word[i] << 24) & 0xFF000000); - word[i] = tmp; - } - - return ERROR_OK; -} - -static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_words) -{ - uint32_t big_endian_word[4]; - int retry_times = 0; - - /** instruction is big-endian */ - memcpy(big_endian_word, word, sizeof(big_endian_word)); - aice_switch_to_big_endian(big_endian_word, num_of_words); - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id, - num_of_words - 1, 0, big_endian_word, num_of_words, - AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, - AICE_FORMAT_HTDMC + (num_of_words - 1) * 4, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id, num_of_words - 1, 0, - big_endian_word, num_of_words, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4); - - LOG_DEBUG("WRITE_DIM, COREID: %" PRIu8 - ", data: 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32, - target_id, - big_endian_word[0], - big_endian_word[1], - big_endian_word[2], - big_endian_word[3]); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - - if (cmd_ack_code == AICE_CMD_T_WRITE_DIM) { - LOG_DEBUG("WRITE_DIM response"); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_DIM, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_do_execute(uint8_t target_id) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN); - return aice_usb_packet_append(usb_out_buffer, - AICE_FORMAT_HTDMC, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC); - - LOG_DEBUG("EXECUTE, COREID: %" PRIu8 "", target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_EXECUTE) { - LOG_DEBUG("EXECUTE response"); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_EXECUTE, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data) -{ - int retry_times = 0; - - LOG_DEBUG("WRITE_MEM_B, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32, - target_id, - address, - data); - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, address, - data & 0x000000FF, data_endian); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, - AICE_FORMAT_DTHMB); - } else { - do { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, - address, data & 0x000000FF, data_endian); - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_B) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_MEM_B, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - } - - return ERROR_OK; -} - -static int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data) -{ - int retry_times = 0; - - LOG_DEBUG("WRITE_MEM_H, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32, - target_id, - address, - data); - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0, - (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, - AICE_FORMAT_DTHMB); - } else { - do { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0, - (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian); - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_H) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_MEM_H, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - } - - return ERROR_OK; -} - -static int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data) -{ - int retry_times = 0; - - LOG_DEBUG("WRITE_MEM, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32, - target_id, - address, - data); - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0, - (address >> 2) & 0x3FFFFFFF, data, data_endian); - return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, - AICE_FORMAT_DTHMB); - } else { - do { - aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0, - (address >> 2) & 0x3FFFFFFF, data, data_endian); - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_WRITE_MEM) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_WRITE_MEM, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - } - - return ERROR_OK; -} - -static int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_words) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM, target_id, num_of_words - 1, 0); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB); - - LOG_DEBUG("FASTREAD_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32, - target_id, num_of_words); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4); - if (result < 0) { - LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%d)", - AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id, - &extra_length, word, data_endian); - - if (cmd_ack_code == AICE_CMD_T_FASTREAD_MEM) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_FASTREAD_MEM, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t num_of_words) -{ - int retry_times = 0; - - if (aice_command_mode == AICE_COMMAND_MODE_PACK) { - aice_usb_packet_flush(); - } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { - aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id, - num_of_words - 1, 0, word, data_endian); - return aice_usb_packet_append(usb_out_buffer, - AICE_FORMAT_HTDMD + (num_of_words - 1) * 4, - AICE_FORMAT_DTHMB); - } - - do { - aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id, - num_of_words - 1, 0, word, data_endian); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD + (num_of_words - 1) * 4); - - LOG_DEBUG("FASTWRITE_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32, - target_id, num_of_words); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_T_FASTWRITE_MEM) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdmb(AICE_CMD_T_READ_MEM_B, target_id, 0, address); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB); - - LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8 "", target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, data_endian); - - if (cmd_ack_code == AICE_CMD_T_READ_MEM_B) { - LOG_DEBUG("READ_MEM_B response, data: 0x%02" PRIx32, *data); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_MEM_B, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdmb(AICE_CMD_T_READ_MEM_H, target_id, 0, (address >> 1) & 0x7FFFFFFF); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB); - - LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8 "", target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, data_endian); - - if (cmd_ack_code == AICE_CMD_T_READ_MEM_H) { - LOG_DEBUG("READ_MEM_H response, data: 0x%" PRIx32, *data); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_MEM_H, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data) -{ - int retry_times = 0; - - if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || - (aice_command_mode == AICE_COMMAND_MODE_BATCH)) - aice_usb_packet_flush(); - - do { - aice_pack_htdmb(AICE_CMD_T_READ_MEM, target_id, 0, - (address >> 2) & 0x3FFFFFFF); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB); - - LOG_DEBUG("READ_MEM, COREID: %" PRIu8 "", target_id); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (result != AICE_FORMAT_DTHMA) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMA, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length, - data, data_endian); - - if (cmd_ack_code == AICE_CMD_T_READ_MEM) { - LOG_DEBUG("READ_MEM response, data: 0x%" PRIx32, *data); - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_T_READ_MEM, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -static int aice_batch_buffer_read(uint8_t buf_index, uint32_t *word, uint32_t num_of_words) -{ - int retry_times = 0; - - do { - aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ, 0, num_of_words - 1, buf_index); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA); - - LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32, num_of_words); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4); - if (result < 0) { - LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%d)", - AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id, - &extra_length, (uint8_t *)word, data_endian); - - if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_READ) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num_of_words) -{ - int retry_times = 0; - - if (num_of_words == 0) - return ERROR_OK; - - do { - /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */ - aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE, 0, num_of_words - 1, buf_index, - 0, data_endian); - - /* use append instead of pack */ - memcpy(usb_out_buffer + 4, word, num_of_words * 4); - - aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4); - - LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32, num_of_words); - - int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (result != AICE_FORMAT_DTHMB) { - LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", - AICE_FORMAT_DTHMB, result); - return ERROR_FAIL; - } - - uint8_t cmd_ack_code; - uint8_t extra_length; - uint8_t res_target_id; - aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length); - - if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_WRITE) { - break; - } else { - if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", - AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code); - - return ERROR_FAIL; - } - - /* clear timeout and retry */ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - retry_times++; - } - } while (1); - - return ERROR_OK; -} - -/***************************************************************************/ -/* End of AICE commands */ - -typedef int (*read_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t *data); -typedef int (*write_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t data); - -static struct aice_nds32_info core_info[AICE_MAX_NUM_CORE]; -static uint8_t total_num_of_core; - -static char *custom_srst_script; -static char *custom_trst_script; -static char *custom_restart_script; -static uint32_t aice_count_to_check_dbger = 30; - -static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val); -static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val); - -static int check_suppressed_exception(uint32_t coreid, uint32_t dbger_value) -{ - uint32_t ir4_value = 0; - uint32_t ir6_value = 0; - /* the default value of handling_suppressed_exception is false */ - static bool handling_suppressed_exception; - - if (handling_suppressed_exception) - return ERROR_OK; - - if ((dbger_value & NDS_DBGER_ALL_SUPRS_EX) == NDS_DBGER_ALL_SUPRS_EX) { - LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->"); - handling_suppressed_exception = true; - - aice_read_reg(coreid, IR4, &ir4_value); - /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */ - aice_read_reg(coreid, IR6, &ir6_value); - /* - * For MCU version(MSC_CFG.MCU == 1) like V3m - * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8] - * |VECTOR[7:5] | INST[4] | Exc Type[3:0] | - * - * For non-MCU version(MSC_CFG.MCU == 0) like V3 - * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12] - * | VECTOR[11:5] | INST[4] | Exc Type[3:0] | - */ - LOG_INFO("EVA: 0x%08" PRIx32, ir4_value); - LOG_INFO("ITYPE: 0x%08" PRIx32, ir6_value); - - ir6_value = ir6_value & (~0x300); /* for MCU */ - ir6_value = ir6_value & (~0x3000); /* for non-MCU */ - aice_write_reg(coreid, IR6, ir6_value); - - handling_suppressed_exception = false; - } - - return ERROR_OK; -} - -static int check_privilege(uint32_t coreid, uint32_t dbger_value) -{ - if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) { - LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege " - "to execute the debug operations. -->"); - - /* Clear DBGER.ILL_SEC_ACC */ - if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, - NDS_DBGER_ILL_SEC_ACC) != ERROR_OK) - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_check_dbger(uint32_t coreid, uint32_t expect_status) -{ - uint32_t i = 0; - uint32_t value_dbger = 0; - - while (1) { - aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger); - - if ((value_dbger & expect_status) == expect_status) { - if (check_suppressed_exception(coreid, value_dbger) != ERROR_OK) - return ERROR_FAIL; - if (check_privilege(coreid, value_dbger) != ERROR_OK) - return ERROR_FAIL; - return ERROR_OK; - } - - if ((i % 30) == 0) - keep_alive(); - - int64_t then = 0; - if (i == aice_count_to_check_dbger) - then = timeval_ms(); - if (i >= aice_count_to_check_dbger) { - if ((timeval_ms() - then) > 1000) { - LOG_ERROR("Timeout (1000ms) waiting for $DBGER status " - "being 0x%08" PRIx32, expect_status); - return ERROR_FAIL; - } - } - i++; - } - - return ERROR_FAIL; -} - -static int aice_execute_dim(uint32_t coreid, uint32_t *insts, uint8_t n_inst) -{ - /** fill DIM */ - if (aice_write_dim(coreid, insts, n_inst) != ERROR_OK) - return ERROR_FAIL; - - /** clear DBGER.DPED */ - if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK) - return ERROR_FAIL; - - /** execute DIM */ - if (aice_do_execute(coreid) != ERROR_OK) - return ERROR_FAIL; - - /** read DBGER.DPED */ - if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) { - LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: " - "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 ". -->", - insts[0], - insts[1], - insts[2], - insts[3]); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) -{ - LOG_DEBUG("aice_read_reg, reg_no: 0x%08" PRIx32, num); - - uint32_t instructions[4]; /** execute instructions in DIM */ - - if (nds32_reg_type(num) == NDS32_REG_TYPE_GPR) { /* general registers */ - instructions[0] = MTSR_DTR(num); - instructions[1] = DSB; - instructions[2] = NOP; - instructions[3] = BEQ_MINUS_12; - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_SPR) { /* user special registers */ - instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_AUMR) { /* audio registers */ - if ((num >= CB_CTL) && (num <= CBE3)) { - instructions[0] = AMFAR2(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else { - instructions[0] = AMFAR(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_FPU) { /* fpu registers */ - if (num == FPCSR) { - instructions[0] = FMFCSR; - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (num == FPCFG) { - instructions[0] = FMFCFG; - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else { - if (num >= FS0 && num <= FS31) { /* single precision */ - instructions[0] = FMFSR(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (num >= FD0 && num <= FD31) { /* double precision */ - instructions[0] = FMFDR(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - } - } else { /* system registers */ - instructions[0] = MFSR(0, nds32_reg_sr_index(num)); - instructions[1] = MTSR_DTR(0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - - aice_execute_dim(coreid, instructions, 4); - - uint32_t value_edmsw = 0; - aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw); - if (value_edmsw & NDS_EDMSW_WDV) - aice_read_dtr(coreid, val); - else { - LOG_ERROR("<-- TARGET ERROR! The debug target failed to update " - "the DTR register. -->"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_usb_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) -{ - LOG_DEBUG("aice_usb_read_reg"); - - if (num == R0) { - *val = core_info[coreid].r0_backup; - } else if (num == R1) { - *val = core_info[coreid].r1_backup; - } else if (num == DR41) { - /* As target is halted, OpenOCD will backup DR41/DR42/DR43. - * As user wants to read these registers, OpenOCD should return - * the backup values, instead of reading the real values. - * As user wants to write these registers, OpenOCD should write - * to the backup values, instead of writing to real registers. */ - *val = core_info[coreid].edmsw_backup; - } else if (num == DR42) { - *val = core_info[coreid].edm_ctl_backup; - } else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) { - *val = core_info[coreid].target_dtr_backup; - } else { - if (aice_read_reg(coreid, num, val) != ERROR_OK) - *val = 0xBBADBEEF; - } - - return ERROR_OK; -} - -static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val) -{ - LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32 ", value: 0x%08" PRIx32, num, val); - - uint32_t instructions[4]; /** execute instructions in DIM */ - uint32_t value_edmsw = 0; - - aice_write_dtr(coreid, val); - aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw); - if (0 == (value_edmsw & NDS_EDMSW_RDV)) { - LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->"); - return ERROR_FAIL; - } - - if (nds32_reg_type(num) == NDS32_REG_TYPE_GPR) { /* general registers */ - instructions[0] = MFSR_DTR(num); - instructions[1] = DSB; - instructions[2] = NOP; - instructions[3] = BEQ_MINUS_12; - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_SPR) { /* user special registers */ - instructions[0] = MFSR_DTR(0); - instructions[1] = MTUSR_G0(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_AUMR) { /* audio registers */ - if ((num >= CB_CTL) && (num <= CBE3)) { - instructions[0] = MFSR_DTR(0); - instructions[1] = AMTAR2(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else { - instructions[0] = MFSR_DTR(0); - instructions[1] = AMTAR(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - } else if (nds32_reg_type(num) == NDS32_REG_TYPE_FPU) { /* fpu registers */ - if (num == FPCSR) { - instructions[0] = MFSR_DTR(0); - instructions[1] = FMTCSR; - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (num == FPCFG) { - /* FPCFG is readonly */ - } else { - if (num >= FS0 && num <= FS31) { /* single precision */ - instructions[0] = MFSR_DTR(0); - instructions[1] = FMTSR(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } else if (num >= FD0 && num <= FD31) { /* double precision */ - instructions[0] = MFSR_DTR(0); - instructions[1] = FMTDR(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - } - } else { - instructions[0] = MFSR_DTR(0); - instructions[1] = MTSR(0, nds32_reg_sr_index(num)); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - } - - return aice_execute_dim(coreid, instructions, 4); -} - -static int aice_usb_write_reg(uint32_t coreid, uint32_t num, uint32_t val) -{ - LOG_DEBUG("aice_usb_write_reg"); - - if (num == R0) - core_info[coreid].r0_backup = val; - else if (num == R1) - core_info[coreid].r1_backup = val; - else if (num == DR42) - /* As target is halted, OpenOCD will backup DR41/DR42/DR43. - * As user wants to read these registers, OpenOCD should return - * the backup values, instead of reading the real values. - * As user wants to write these registers, OpenOCD should write - * to the backup values, instead of writing to real registers. */ - core_info[coreid].edm_ctl_backup = val; - else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) - core_info[coreid].target_dtr_backup = val; - else - return aice_write_reg(coreid, num, val); - - return ERROR_OK; -} - -static int aice_usb_open(struct aice_port_param_s *param) -{ - const uint16_t vids[] = { param->vid, 0 }; - const uint16_t pids[] = { param->pid, 0 }; - struct libusb_device_handle *devh; - - if (jtag_libusb_open(vids, pids, &devh, NULL) != ERROR_OK) - return ERROR_FAIL; - - /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS - * AREA!!!!!!!!!!! The behavior of libusb is not completely - * consistent across Windows, Linux, and Mac OS X platforms. - * The actions taken in the following compiler conditionals may - * not agree with published documentation for libusb, but were - * found to be necessary through trials and tribulations. Even - * little tweaks can break one or more platforms, so if you do - * make changes test them carefully on all platforms before - * committing them! - */ - -#if IS_WIN32 == 0 - - libusb_reset_device(devh); - -#if IS_DARWIN == 0 - - int timeout = 5; - /* reopen jlink after usb_reset - * on win32 this may take a second or two to re-enumerate */ - int retval; - while ((retval = jtag_libusb_open(vids, pids, &devh, NULL)) != ERROR_OK) { - usleep(1000); - timeout--; - if (!timeout) - break; - } - if (retval != ERROR_OK) - return ERROR_FAIL; -#endif - -#endif - - /* usb_set_configuration required under win32 */ - libusb_set_configuration(devh, 0); - libusb_claim_interface(devh, 0); - - unsigned int aice_read_ep; - unsigned int aice_write_ep; - - jtag_libusb_choose_interface(devh, &aice_read_ep, &aice_write_ep, -1, -1, -1, LIBUSB_TRANSFER_TYPE_BULK); - LOG_DEBUG("aice_read_ep=0x%x, aice_write_ep=0x%x", aice_read_ep, aice_write_ep); - - aice_handler.usb_read_ep = aice_read_ep; - aice_handler.usb_write_ep = aice_write_ep; - aice_handler.usb_handle = devh; - - return ERROR_OK; -} - -static int aice_usb_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val) -{ - LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num)); - - uint32_t value; - uint32_t high_value; - - if (aice_read_reg(coreid, num, &value) != ERROR_OK) - value = 0xBBADBEEF; - - aice_read_reg(coreid, R1, &high_value); - - LOG_DEBUG("low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n", value, high_value); - - if (data_endian == AICE_BIG_ENDIAN) - *val = (((uint64_t)high_value) << 32) | value; - else - *val = (((uint64_t)value) << 32) | high_value; - - return ERROR_OK; -} - -static int aice_usb_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val) -{ - uint32_t value; - uint32_t high_value; - - if (data_endian == AICE_BIG_ENDIAN) { - value = val & 0xFFFFFFFF; - high_value = (val >> 32) & 0xFFFFFFFF; - } else { - high_value = val & 0xFFFFFFFF; - value = (val >> 32) & 0xFFFFFFFF; - } - - LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n", - nds32_reg_simple_name(num), value, high_value); - - aice_write_reg(coreid, R1, high_value); - return aice_write_reg(coreid, num, value); -} - -static int aice_get_version_info(void) -{ - uint32_t hardware_version; - uint32_t firmware_version; - uint32_t fpga_version; - - if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION, &hardware_version) != ERROR_OK) - return ERROR_FAIL; - - if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION, &firmware_version) != ERROR_OK) - return ERROR_FAIL; - - if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION, &fpga_version) != ERROR_OK) - return ERROR_FAIL; - - LOG_INFO("AICE version: hw_ver = 0x%" PRIx32 ", fw_ver = 0x%" PRIx32 ", fpga_ver = 0x%" PRIx32, - hardware_version, firmware_version, fpga_version); - - return ERROR_OK; -} - -#define LINE_BUFFER_SIZE 1024 - -static int aice_execute_custom_script(const char *script) -{ - FILE *script_fd; - char line_buffer[LINE_BUFFER_SIZE]; - char *op_str; - char *reset_str; - uint32_t delay; - uint32_t write_ctrl_value; - bool set_op; - - script_fd = fopen(script, "r"); - if (!script_fd) { - return ERROR_FAIL; - } else { - while (fgets(line_buffer, LINE_BUFFER_SIZE, script_fd)) { - /* execute operations */ - set_op = false; - op_str = strstr(line_buffer, "set"); - if (op_str) { - set_op = true; - goto get_reset_type; - } - - op_str = strstr(line_buffer, "clear"); - if (!op_str) - continue; -get_reset_type: - reset_str = strstr(op_str, "srst"); - if (reset_str) { - if (set_op) - write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST; - else - write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST; - goto get_delay; - } - reset_str = strstr(op_str, "dbgi"); - if (reset_str) { - if (set_op) - write_ctrl_value = AICE_CUSTOM_DELAY_SET_DBGI; - else - write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_DBGI; - goto get_delay; - } - reset_str = strstr(op_str, "trst"); - if (reset_str) { - if (set_op) - write_ctrl_value = AICE_CUSTOM_DELAY_SET_TRST; - else - write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_TRST; - goto get_delay; - } - continue; -get_delay: - /* get delay */ - delay = strtoul(reset_str + 4, NULL, 0); - write_ctrl_value |= (delay << 16); - - if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY, - write_ctrl_value) != ERROR_OK) { - fclose(script_fd); - return ERROR_FAIL; - } - } - fclose(script_fd); - } - - return ERROR_OK; -} - -static int aice_usb_set_clock(int set_clock) -{ - if (set_clock & AICE_TCK_CONTROL_TCK_SCAN) { - if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL, - AICE_TCK_CONTROL_TCK_SCAN) != ERROR_OK) - return ERROR_FAIL; - - /* Read out TCK_SCAN clock value */ - uint32_t scan_clock; - if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &scan_clock) != ERROR_OK) - return ERROR_FAIL; - - scan_clock &= 0x0F; - - uint32_t scan_base_freq; - if (scan_clock & 0x8) - scan_base_freq = 48000; /* 48 MHz */ - else - scan_base_freq = 30000; /* 30 MHz */ - - uint32_t set_base_freq; - if (set_clock & 0x8) - set_base_freq = 48000; - else - set_base_freq = 30000; - - uint32_t set_freq; - uint32_t scan_freq; - set_freq = set_base_freq >> (set_clock & 0x7); - scan_freq = scan_base_freq >> (scan_clock & 0x7); - - if (scan_freq < set_freq) { - LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock"); - return ERROR_FAIL; - } - } - - if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL, set_clock) != ERROR_OK) - return ERROR_FAIL; - - uint32_t check_speed; - if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &check_speed) != ERROR_OK) - return ERROR_FAIL; - - if (((int)check_speed & 0x0F) != set_clock) { - LOG_ERROR("Set jtag clock failed"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_edm_init(uint32_t coreid) -{ - aice_write_edmsr(coreid, NDS_EDM_SR_DIMBR, 0xFFFF0000); - aice_write_misc(coreid, NDS_EDM_MISC_DIMIR, 0); - - /* unconditionally try to turn on V3_EDM_MODE */ - uint32_t edm_ctl_value; - aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value); - aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value | 0x00000040); - - /* clear DBGER */ - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, - NDS_DBGER_DPED | NDS_DBGER_CRST | NDS_DBGER_AT_MAX); - - /* get EDM version */ - uint32_t value_edmcfg; - aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CFG, &value_edmcfg); - core_info[coreid].edm_version = (value_edmcfg >> 16) & 0xFFFF; - - return ERROR_OK; -} - -static bool is_v2_edm(uint32_t coreid) -{ - if ((core_info[coreid].edm_version & 0x1000) == 0) - return true; - else - return false; -} - -static int aice_init_edm_registers(uint32_t coreid, bool clear_dex_use_psw) -{ - /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */ - uint32_t host_edm_ctl = core_info[coreid].edm_ctl_backup | 0xA000004F; - if (clear_dex_use_psw) - /* After entering debug mode, OpenOCD may set - * DEX_USE_PSW accidentally through backup value - * of target EDM_CTL. - * So, clear DEX_USE_PSW by force. */ - host_edm_ctl &= ~(0x40000000); - - LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08" PRIx32, host_edm_ctl); - - int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, host_edm_ctl); - - return result; -} - -/** - * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the - * responsibility to keep EDM_CTL untouched after debugging. - * - * There are two scenarios to consider: - * 1. single step/running as debugging (running under debug session) - * 2. detached from gdb (exit debug session) - * - * So, we need to bakcup EDM_CTL before halted and restore it after - * running. The difference of these two scenarios is EDM_CTL.DEH_SEL - * is on for scenario 1, and off for scenario 2. - */ -static int aice_backup_edm_registers(uint32_t coreid) -{ - int result = aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, - &core_info[coreid].edm_ctl_backup); - - /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW - * may be not correct. (For example, hit breakpoint, then backup - * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug - * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after - * DEX is on. It only backups correct value before OpenOCD issues DBGI. - * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */ - if (core_info[coreid].edm_ctl_backup & 0x40000000) - core_info[coreid].dex_use_psw_on = true; - else - core_info[coreid].dex_use_psw_on = false; - - LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08" PRIx32 ", DEX_USE_PSW: %s", - core_info[coreid].edm_ctl_backup, - core_info[coreid].dex_use_psw_on ? "on" : "off"); - - return result; -} - -static int aice_restore_edm_registers(uint32_t coreid) -{ - LOG_DEBUG("aice_restore_edm_registers -"); - - /* set DEH_SEL, because target still under EDM control */ - int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, - core_info[coreid].edm_ctl_backup | 0x80000000); - - return result; -} - -static int aice_backup_tmp_registers(uint32_t coreid) -{ - LOG_DEBUG("backup_tmp_registers -"); - - /* backup target DTR first(if the target DTR is valid) */ - uint32_t value_edmsw = 0; - aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw); - core_info[coreid].edmsw_backup = value_edmsw; - if (value_edmsw & 0x1) { /* EDMSW.WDV == 1 */ - aice_read_dtr(coreid, &core_info[coreid].target_dtr_backup); - core_info[coreid].target_dtr_valid = true; - - LOG_DEBUG("Backup target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup); - } else { - core_info[coreid].target_dtr_valid = false; - } - - /* Target DTR has been backup, then backup $R0 and $R1 */ - aice_read_reg(coreid, R0, &core_info[coreid].r0_backup); - aice_read_reg(coreid, R1, &core_info[coreid].r1_backup); - - /* backup host DTR(if the host DTR is valid) */ - if (value_edmsw & 0x2) { /* EDMSW.RDV == 1*/ - /* read out host DTR and write into target DTR, then use aice_read_edmsr to - * read out */ - uint32_t instructions[4] = { - MFSR_DTR(R0), /* R0 has already been backup */ - DSB, - MTSR_DTR(R0), - BEQ_MINUS_12 - }; - aice_execute_dim(coreid, instructions, 4); - - aice_read_dtr(coreid, &core_info[coreid].host_dtr_backup); - core_info[coreid].host_dtr_valid = true; - - LOG_DEBUG("Backup host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup); - } else { - core_info[coreid].host_dtr_valid = false; - } - - LOG_DEBUG("r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32, - core_info[coreid].r0_backup, core_info[coreid].r1_backup); - - return ERROR_OK; -} - -static int aice_restore_tmp_registers(uint32_t coreid) -{ - LOG_DEBUG("restore_tmp_registers - r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32, - core_info[coreid].r0_backup, core_info[coreid].r1_backup); - - if (core_info[coreid].target_dtr_valid) { - uint32_t instructions[4] = { - SETHI(R0, core_info[coreid].target_dtr_backup >> 12), - ORI(R0, R0, core_info[coreid].target_dtr_backup & 0x00000FFF), - NOP, - BEQ_MINUS_12 - }; - aice_execute_dim(coreid, instructions, 4); - - instructions[0] = MTSR_DTR(R0); - instructions[1] = DSB; - instructions[2] = NOP; - instructions[3] = BEQ_MINUS_12; - aice_execute_dim(coreid, instructions, 4); - - LOG_DEBUG("Restore target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup); - } - - aice_write_reg(coreid, R0, core_info[coreid].r0_backup); - aice_write_reg(coreid, R1, core_info[coreid].r1_backup); - - if (core_info[coreid].host_dtr_valid) { - aice_write_dtr(coreid, core_info[coreid].host_dtr_backup); - - LOG_DEBUG("Restore host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup); - } - - return ERROR_OK; -} - -static int aice_open_device(struct aice_port_param_s *param) -{ - if (aice_usb_open(param) != ERROR_OK) - return ERROR_FAIL; - - if (aice_get_version_info() == ERROR_FAIL) { - LOG_ERROR("Cannot get AICE version!"); - return ERROR_FAIL; - } - - LOG_INFO("AICE initialization started"); - - /* attempt to reset Andes EDM */ - if (aice_reset_box() == ERROR_FAIL) { - LOG_ERROR("Cannot initial AICE box!"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_usb_set_jtag_clock(uint32_t a_clock) -{ - jtag_clock = a_clock; - - if (aice_usb_set_clock(a_clock) != ERROR_OK) { - LOG_ERROR("Cannot set AICE JTAG clock!"); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int aice_usb_close(void) -{ - jtag_libusb_close(aice_handler.usb_handle); - - free(custom_srst_script); - free(custom_trst_script); - free(custom_restart_script); - return ERROR_OK; -} - -static int aice_core_init(uint32_t coreid) -{ - core_info[coreid].access_channel = NDS_MEMORY_ACC_CPU; - core_info[coreid].memory_select = NDS_MEMORY_SELECT_AUTO; - core_info[coreid].core_state = AICE_TARGET_UNKNOWN; - - return ERROR_OK; -} - -static int aice_usb_idcode(uint32_t *idcode, uint8_t *num_of_idcode) -{ - int retval; - - retval = aice_scan_chain(idcode, num_of_idcode); - if (retval == ERROR_OK) { - for (int i = 0; i < *num_of_idcode; i++) { - aice_core_init(i); - aice_edm_init(i); - } - total_num_of_core = *num_of_idcode; - } - - return retval; -} - -static int aice_usb_halt(uint32_t coreid) -{ - if (core_info[coreid].core_state == AICE_TARGET_HALTED) { - LOG_DEBUG("aice_usb_halt check halted"); - return ERROR_OK; - } - - LOG_DEBUG("aice_usb_halt"); - - /** backup EDM registers */ - aice_backup_edm_registers(coreid); - /** init EDM for host debugging */ - /** no need to clear dex_use_psw, because dbgi will clear it */ - aice_init_edm_registers(coreid, false); - - /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */ - uint32_t edm_ctl_value = 0; - aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value); - if (edm_ctl_value & 0x3) - aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3)); - - uint32_t dbger = 0; - uint32_t acc_ctl_value = 0; - - core_info[coreid].debug_under_dex_on = false; - aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger); - - if (dbger & NDS_DBGER_AT_MAX) - LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->"); - - if (dbger & NDS_DBGER_DEX) { - if (is_v2_edm(coreid) == false) { - /** debug 'debug mode'. use force_debug to issue dbgi */ - aice_read_misc(coreid, NDS_EDM_MISC_ACC_CTL, &acc_ctl_value); - acc_ctl_value |= 0x8; - aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, acc_ctl_value); - core_info[coreid].debug_under_dex_on = true; - - aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0); - /* If CPU stalled due to AT_MAX, clear AT_MAX status. */ - if (dbger & NDS_DBGER_AT_MAX) - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX); - } - } else { - /** Issue DBGI normally */ - aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0); - /* If CPU stalled due to AT_MAX, clear AT_MAX status. */ - if (dbger & NDS_DBGER_AT_MAX) - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX); - } - - if (aice_check_dbger(coreid, NDS_DBGER_DEX) != ERROR_OK) { - LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->"); - return ERROR_FAIL; - } - - if (core_info[coreid].debug_under_dex_on) { - if (core_info[coreid].dex_use_psw_on == false) { - /* under debug 'debug mode', force $psw to 'debug mode' behavior */ - /* !!!NOTICE!!! this is workaround for debug 'debug mode'. - * it is only for debugging 'debug exception handler' purpose. - * after openocd detaches from target, target behavior is - * undefined. */ - uint32_t ir0_value = 0; - uint32_t debug_mode_ir0_value; - aice_read_reg(coreid, IR0, &ir0_value); - debug_mode_ir0_value = ir0_value | 0x408; /* turn on DEX, set POM = 1 */ - debug_mode_ir0_value &= ~(0x000000C1); /* turn off DT/IT/GIE */ - aice_write_reg(coreid, IR0, debug_mode_ir0_value); - } - } - - /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */ - if (edm_ctl_value & 0x3) - aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value); - - /* backup r0 & r1 */ - aice_backup_tmp_registers(coreid); - core_info[coreid].core_state = AICE_TARGET_HALTED; - - return ERROR_OK; -} - -static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state) -{ - uint32_t dbger_value; - uint32_t ice_state; - - int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value); - - if (result == ERROR_AICE_TIMEOUT) { - if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) { - LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->"); - return ERROR_FAIL; - } - - if ((ice_state & 0x20) == 0) { - LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->"); - return ERROR_FAIL; - } else { - return ERROR_FAIL; - } - } else if (result == ERROR_AICE_DISCONNECT) { - LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->"); - return ERROR_FAIL; - } - - if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) { - LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->"); - - /* Clear ILL_SEC_ACC */ - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_ILL_SEC_ACC); - - *state = AICE_TARGET_RUNNING; - core_info[coreid].core_state = AICE_TARGET_RUNNING; - } else if ((dbger_value & NDS_DBGER_AT_MAX) == NDS_DBGER_AT_MAX) { - /* Issue DBGI to exit cpu stall */ - aice_usb_halt(coreid); - - /* Read OIPC to find out the trigger point */ - uint32_t ir11_value; - aice_read_reg(coreid, IR11, &ir11_value); - - LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; " - "CPU is stalled at 0x%08" PRIx32 " for debugging. -->", ir11_value); - - *state = AICE_TARGET_HALTED; - } else if ((dbger_value & NDS_DBGER_CRST) == NDS_DBGER_CRST) { - LOG_DEBUG("DBGER.CRST is on."); - - *state = AICE_TARGET_RESET; - core_info[coreid].core_state = AICE_TARGET_RUNNING; - - /* Clear CRST */ - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST); - } else if ((dbger_value & NDS_DBGER_DEX) == NDS_DBGER_DEX) { - if (core_info[coreid].core_state == AICE_TARGET_RUNNING) { - /* enter debug mode, init EDM registers */ - /* backup EDM registers */ - aice_backup_edm_registers(coreid); - /* init EDM for host debugging */ - aice_init_edm_registers(coreid, true); - aice_backup_tmp_registers(coreid); - core_info[coreid].core_state = AICE_TARGET_HALTED; - } else if (core_info[coreid].core_state == AICE_TARGET_UNKNOWN) { - /* debug 'debug mode', use force debug to halt core */ - aice_usb_halt(coreid); - } - *state = AICE_TARGET_HALTED; - } else { - *state = AICE_TARGET_RUNNING; - core_info[coreid].core_state = AICE_TARGET_RUNNING; - } - - return ERROR_OK; -} - -static int aice_usb_reset(void) -{ - if (aice_reset_box() != ERROR_OK) - return ERROR_FAIL; - - /* issue TRST */ - if (!custom_trst_script) { - if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL, - AICE_JTAG_PIN_CONTROL_TRST) != ERROR_OK) - return ERROR_FAIL; - } else { - /* custom trst operations */ - if (aice_execute_custom_script(custom_trst_script) != ERROR_OK) - return ERROR_FAIL; - } - - if (aice_usb_set_clock(jtag_clock) != ERROR_OK) - return ERROR_FAIL; - - return ERROR_OK; -} - -static int aice_issue_srst(uint32_t coreid) -{ - LOG_DEBUG("aice_issue_srst"); - - /* After issuing srst, target will be running. So we need to restore EDM_CTL. */ - aice_restore_edm_registers(coreid); - - if (!custom_srst_script) { - if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL, - AICE_JTAG_PIN_CONTROL_SRST) != ERROR_OK) - return ERROR_FAIL; - } else { - /* custom srst operations */ - if (aice_execute_custom_script(custom_srst_script) != ERROR_OK) - return ERROR_FAIL; - } - - /* wait CRST infinitely */ - uint32_t dbger_value; - int i = 0; - while (1) { - if (aice_read_misc(coreid, - NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK) - return ERROR_FAIL; - - if (dbger_value & NDS_DBGER_CRST) - break; - - if ((i % 30) == 0) - keep_alive(); - i++; - } - - core_info[coreid].host_dtr_valid = false; - core_info[coreid].target_dtr_valid = false; - - core_info[coreid].core_state = AICE_TARGET_RUNNING; - return ERROR_OK; -} - -static int aice_issue_reset_hold(uint32_t coreid) -{ - LOG_DEBUG("aice_issue_reset_hold"); - - /* set no_dbgi_pin to 0 */ - uint32_t pin_status; - aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status); - if (pin_status & 0x4) - aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x4)); - - /* issue restart */ - if (!custom_restart_script) { - if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL, - AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK) - return ERROR_FAIL; - } else { - /* custom restart operations */ - if (aice_execute_custom_script(custom_restart_script) != ERROR_OK) - return ERROR_FAIL; - } - - if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) { - aice_backup_tmp_registers(coreid); - core_info[coreid].core_state = AICE_TARGET_HALTED; - - return ERROR_OK; - } else { - /* set no_dbgi_pin to 1 */ - aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status | 0x4); - - /* issue restart again */ - if (!custom_restart_script) { - if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL, - AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK) - return ERROR_FAIL; - } else { - /* custom restart operations */ - if (aice_execute_custom_script(custom_restart_script) != ERROR_OK) - return ERROR_FAIL; - } - - if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) { - aice_backup_tmp_registers(coreid); - core_info[coreid].core_state = AICE_TARGET_HALTED; - - return ERROR_OK; - } - - /* do software reset-and-hold */ - aice_issue_srst(coreid); - aice_usb_halt(coreid); - - uint32_t value_ir3; - aice_read_reg(coreid, IR3, &value_ir3); - aice_write_reg(coreid, PC, value_ir3 & 0xFFFF0000); - } - - return ERROR_FAIL; -} - -static int aice_issue_reset_hold_multi(void) -{ - uint32_t write_ctrl_value = 0; - - /* set SRST */ - write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST; - write_ctrl_value |= (0x200 << 16); - if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY, - write_ctrl_value) != ERROR_OK) - return ERROR_FAIL; - - for (uint8_t i = 0 ; i < total_num_of_core ; i++) - aice_write_misc(i, NDS_EDM_MISC_EDM_CMDR, 0); - - /* clear SRST */ - write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST; - write_ctrl_value |= (0x200 << 16); - if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY, - write_ctrl_value) != ERROR_OK) - return ERROR_FAIL; - - for (uint8_t i = 0; i < total_num_of_core; i++) - aice_edm_init(i); - - return ERROR_FAIL; -} - -static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst) -{ - if ((srst != AICE_SRST) && (srst != AICE_RESET_HOLD)) - return ERROR_FAIL; - - /* clear DBGER */ - if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, - NDS_DBGER_CLEAR_ALL) != ERROR_OK) - return ERROR_FAIL; - - int result = ERROR_OK; - if (srst == AICE_SRST) - result = aice_issue_srst(coreid); - else { - if (total_num_of_core == 1) - result = aice_issue_reset_hold(coreid); - else - result = aice_issue_reset_hold_multi(); - } - - /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors. - * assert_srst is user-intentional reset behavior, so we could - * clear DBGER.CRST safely. - */ - if (aice_write_misc(coreid, - NDS_EDM_MISC_DBGER, NDS_DBGER_CRST) != ERROR_OK) - return ERROR_FAIL; - - return result; -} - -static int aice_usb_run(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_run"); - - uint32_t dbger_value; - if (aice_read_misc(coreid, - NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK) - return ERROR_FAIL; - - if ((dbger_value & NDS_DBGER_DEX) != NDS_DBGER_DEX) { - LOG_WARNING("<-- TARGET WARNING! The debug target exited " - "the debug mode unexpectedly. -->"); - return ERROR_FAIL; - } - - /* restore r0 & r1 before free run */ - aice_restore_tmp_registers(coreid); - core_info[coreid].core_state = AICE_TARGET_RUNNING; - - /* clear DBGER */ - aice_write_misc(coreid, NDS_EDM_MISC_DBGER, - NDS_DBGER_CLEAR_ALL); - - /** restore EDM registers */ - /** OpenOCD should restore EDM_CTL **before** to exit debug state. - * Otherwise, following instruction will read wrong EDM_CTL value. - * - * pc -> mfsr $p0, EDM_CTL (single step) - * slli $p0, $p0, 1 - * slri $p0, $p0, 31 - */ - aice_restore_edm_registers(coreid); - - /** execute instructions in DIM */ - uint32_t instructions[4] = { - NOP, - NOP, - NOP, - IRET - }; - int result = aice_execute_dim(coreid, instructions, 4); - - return result; -} - -static int aice_usb_step(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_step"); - - uint32_t ir0_value; - uint32_t ir0_reg_num; - - if (is_v2_edm(coreid) == true) - /* V2 EDM will push interrupt stack as debug exception */ - ir0_reg_num = IR1; - else - ir0_reg_num = IR0; - - /** enable HSS */ - aice_read_reg(coreid, ir0_reg_num, &ir0_value); - if ((ir0_value & 0x800) == 0) { - /** set PSW.HSS */ - ir0_value |= (0x01 << 11); - aice_write_reg(coreid, ir0_reg_num, ir0_value); - } - - if (aice_usb_run(coreid) == ERROR_FAIL) - return ERROR_FAIL; - - int i = 0; - enum aice_target_state_s state; - while (1) { - /* read DBGER */ - if (aice_usb_state(coreid, &state) != ERROR_OK) - return ERROR_FAIL; - - if (state == AICE_TARGET_HALTED) - break; - - int64_t then = 0; - if (i == 30) - then = timeval_ms(); - - if (i >= 30) { - if ((timeval_ms() - then) > 1000) - LOG_WARNING("Timeout (1000ms) waiting for halt to complete"); - - return ERROR_FAIL; - } - i++; - } - - /** disable HSS */ - aice_read_reg(coreid, ir0_reg_num, &ir0_value); - ir0_value &= ~(0x01 << 11); - aice_write_reg(coreid, ir0_reg_num, ir0_value); - - return ERROR_OK; -} - -static int aice_usb_read_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t *data) -{ - return aice_read_mem_b(coreid, address, data); -} - -static int aice_usb_read_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t *data) -{ - return aice_read_mem_h(coreid, address, data); -} - -static int aice_usb_read_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t *data) -{ - return aice_read_mem(coreid, address, data); -} - -static int aice_usb_read_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t *data) -{ - uint32_t value; - uint32_t instructions[4] = { - LBI_BI(R1, R0), - MTSR_DTR(R1), - DSB, - BEQ_MINUS_12 - }; - - aice_execute_dim(coreid, instructions, 4); - - aice_read_dtr(coreid, &value); - *data = value & 0xFF; - - return ERROR_OK; -} - -static int aice_usb_read_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t *data) -{ - uint32_t value; - uint32_t instructions[4] = { - LHI_BI(R1, R0), - MTSR_DTR(R1), - DSB, - BEQ_MINUS_12 - }; - - aice_execute_dim(coreid, instructions, 4); - - aice_read_dtr(coreid, &value); - *data = value & 0xFFFF; - - return ERROR_OK; -} - -static int aice_usb_read_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t *data) -{ - uint32_t instructions[4] = { - LWI_BI(R1, R0), - MTSR_DTR(R1), - DSB, - BEQ_MINUS_12 - }; - - aice_execute_dim(coreid, instructions, 4); - - aice_read_dtr(coreid, data); - - return ERROR_OK; -} - -static int aice_usb_set_address_dim(uint32_t coreid, uint32_t address) -{ - uint32_t instructions[4] = { - SETHI(R0, address >> 12), - ORI(R0, R0, address & 0x00000FFF), - NOP, - BEQ_MINUS_12 - }; - - return aice_execute_dim(coreid, instructions, 4); -} - -static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, uint8_t *buffer) -{ - LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08" PRIx32 - ", size: %" PRIu32 ", count: %" PRIu32 "", - addr, size, count); - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - aice_usb_set_address_dim(coreid, addr); - - uint32_t value; - size_t i; - read_mem_func_t read_mem_func; - - switch (size) { - case 1: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - read_mem_func = aice_usb_read_mem_b_bus; - else - read_mem_func = aice_usb_read_mem_b_dim; - - for (i = 0; i < count; i++) { - read_mem_func(coreid, addr, &value); - *buffer++ = (uint8_t)value; - addr++; - } - break; - case 2: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - read_mem_func = aice_usb_read_mem_h_bus; - else - read_mem_func = aice_usb_read_mem_h_dim; - - for (i = 0; i < count; i++) { - read_mem_func(coreid, addr, &value); - uint16_t svalue = value; - memcpy(buffer, &svalue, sizeof(uint16_t)); - buffer += 2; - addr += 2; - } - break; - case 4: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - read_mem_func = aice_usb_read_mem_w_bus; - else - read_mem_func = aice_usb_read_mem_w_dim; - - for (i = 0; i < count; i++) { - read_mem_func(coreid, addr, &value); - memcpy(buffer, &value, sizeof(uint32_t)); - buffer += 4; - addr += 4; - } - break; - } - - return ERROR_OK; -} - -static int aice_usb_write_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t data) -{ - return aice_write_mem_b(coreid, address, data); -} - -static int aice_usb_write_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t data) -{ - return aice_write_mem_h(coreid, address, data); -} - -static int aice_usb_write_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t data) -{ - return aice_write_mem(coreid, address, data); -} - -static int aice_usb_write_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t data) -{ - uint32_t instructions[4] = { - MFSR_DTR(R1), - SBI_BI(R1, R0), - DSB, - BEQ_MINUS_12 - }; - - aice_write_dtr(coreid, data & 0xFF); - aice_execute_dim(coreid, instructions, 4); - - return ERROR_OK; -} - -static int aice_usb_write_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t data) -{ - uint32_t instructions[4] = { - MFSR_DTR(R1), - SHI_BI(R1, R0), - DSB, - BEQ_MINUS_12 - }; - - aice_write_dtr(coreid, data & 0xFFFF); - aice_execute_dim(coreid, instructions, 4); - - return ERROR_OK; -} - -static int aice_usb_write_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t data) -{ - uint32_t instructions[4] = { - MFSR_DTR(R1), - SWI_BI(R1, R0), - DSB, - BEQ_MINUS_12 - }; - - aice_write_dtr(coreid, data); - aice_execute_dim(coreid, instructions, 4); - - return ERROR_OK; -} - -static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size, - uint32_t count, const uint8_t *buffer) -{ - LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08" PRIx32 - ", size: %" PRIu32 ", count: %" PRIu32 "", - addr, size, count); - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - aice_usb_set_address_dim(coreid, addr); - - size_t i; - write_mem_func_t write_mem_func; - - switch (size) { - case 1: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - write_mem_func = aice_usb_write_mem_b_bus; - else - write_mem_func = aice_usb_write_mem_b_dim; - - for (i = 0; i < count; i++) { - write_mem_func(coreid, addr, *buffer); - buffer++; - addr++; - } - break; - case 2: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - write_mem_func = aice_usb_write_mem_h_bus; - else - write_mem_func = aice_usb_write_mem_h_dim; - - for (i = 0; i < count; i++) { - uint16_t value; - memcpy(&value, buffer, sizeof(uint16_t)); - - write_mem_func(coreid, addr, value); - buffer += 2; - addr += 2; - } - break; - case 4: - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) - write_mem_func = aice_usb_write_mem_w_bus; - else - write_mem_func = aice_usb_write_mem_w_dim; - - for (i = 0; i < count; i++) { - uint32_t value; - memcpy(&value, buffer, sizeof(uint32_t)); - - write_mem_func(coreid, addr, value); - buffer += 4; - addr += 4; - } - break; - } - - return ERROR_OK; -} - -static int aice_bulk_read_mem(uint32_t coreid, uint32_t addr, uint32_t count, - uint8_t *buffer) -{ - uint32_t packet_size; - - while (count > 0) { - packet_size = (count >= 0x100) ? 0x100 : count; - - /** set address */ - addr &= 0xFFFFFFFC; - if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr) != ERROR_OK) - return ERROR_FAIL; - - if (aice_fastread_mem(coreid, buffer, - packet_size) != ERROR_OK) - return ERROR_FAIL; - - buffer += (packet_size * 4); - addr += (packet_size * 4); - count -= packet_size; - } - - return ERROR_OK; -} - -static int aice_bulk_write_mem(uint32_t coreid, uint32_t addr, uint32_t count, - const uint8_t *buffer) -{ - uint32_t packet_size; - - while (count > 0) { - packet_size = (count >= 0x100) ? 0x100 : count; - - /** set address */ - addr &= 0xFFFFFFFC; - if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr | 1) != ERROR_OK) - return ERROR_FAIL; - - if (aice_fastwrite_mem(coreid, buffer, - packet_size) != ERROR_OK) - return ERROR_FAIL; - - buffer += (packet_size * 4); - addr += (packet_size * 4); - count -= packet_size; - } - - return ERROR_OK; -} - -static int aice_usb_bulk_read_mem(uint32_t coreid, uint32_t addr, - uint32_t length, uint8_t *buffer) -{ - LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length); - - int retval; - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - aice_usb_set_address_dim(coreid, addr); - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - retval = aice_usb_read_memory_unit(coreid, addr, 4, length / 4, buffer); - else - retval = aice_bulk_read_mem(coreid, addr, length / 4, buffer); - - return retval; -} - -static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr, - uint32_t length, const uint8_t *buffer) -{ - LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length); - - int retval; - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - aice_usb_set_address_dim(coreid, addr); - - if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) - retval = aice_usb_write_memory_unit(coreid, addr, 4, length / 4, buffer); - else - retval = aice_bulk_write_mem(coreid, addr, length / 4, buffer); - - return retval; -} - -static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val) -{ - if (core_info[coreid].core_state == AICE_TARGET_HALTED) { - if (addr == NDS_EDM_SR_EDMSW) { - *val = core_info[coreid].edmsw_backup; - } else if (addr == NDS_EDM_SR_EDM_DTR) { - if (core_info[coreid].target_dtr_valid) { - /* if EDM_DTR has read out, clear it. */ - *val = core_info[coreid].target_dtr_backup; - core_info[coreid].edmsw_backup &= (~0x1); - core_info[coreid].target_dtr_valid = false; - } else { - *val = 0; - } - } - } - - return aice_read_edmsr(coreid, addr, val); -} - -static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val) -{ - if (core_info[coreid].core_state == AICE_TARGET_HALTED) { - if (addr == NDS_EDM_SR_EDM_DTR) { - core_info[coreid].host_dtr_backup = val; - core_info[coreid].edmsw_backup |= 0x2; - core_info[coreid].host_dtr_valid = true; - } - } - - return aice_write_edmsr(coreid, addr, val); -} - -static int aice_usb_memory_access(uint32_t coreid, enum nds_memory_access channel) -{ - LOG_DEBUG("aice_usb_memory_access, access channel: %u", channel); - - core_info[coreid].access_channel = channel; - - return ERROR_OK; -} - -static int aice_usb_memory_mode(uint32_t coreid, enum nds_memory_select mem_select) -{ - if (core_info[coreid].memory_select == mem_select) - return ERROR_OK; - - LOG_DEBUG("aice_usb_memory_mode, memory select: %u", mem_select); - - core_info[coreid].memory_select = mem_select; - - if (core_info[coreid].memory_select != NDS_MEMORY_SELECT_AUTO) - aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, - core_info[coreid].memory_select - 1); - else - aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, - NDS_MEMORY_SELECT_MEM - 1); - - return ERROR_OK; -} - -static int aice_usb_read_tlb(uint32_t coreid, target_addr_t virtual_address, - target_addr_t *physical_address) -{ - LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08" TARGET_PRIxADDR, virtual_address); - - uint32_t instructions[4]; - uint32_t probe_result; - uint32_t value_mr3; - uint32_t value_mr4; - uint32_t access_page_size; - uint32_t virtual_offset; - uint32_t physical_page_number; - - aice_write_dtr(coreid, virtual_address); - - /* probe TLB first */ - instructions[0] = MFSR_DTR(R0); - instructions[1] = TLBOP_TARGET_PROBE(R1, R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - aice_execute_dim(coreid, instructions, 4); - - aice_read_reg(coreid, R1, &probe_result); - - if (probe_result & 0x80000000) - return ERROR_FAIL; - - /* read TLB entry */ - aice_write_dtr(coreid, probe_result & 0x7FF); - - /* probe TLB first */ - instructions[0] = MFSR_DTR(R0); - instructions[1] = TLBOP_TARGET_READ(R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - aice_execute_dim(coreid, instructions, 4); - - /* TODO: it should backup mr3, mr4 */ - aice_read_reg(coreid, MR3, &value_mr3); - aice_read_reg(coreid, MR4, &value_mr4); - - access_page_size = value_mr4 & 0xF; - if (access_page_size == 0) { /* 4K page */ - virtual_offset = virtual_address & 0x00000FFF; - physical_page_number = value_mr3 & 0xFFFFF000; - } else if (access_page_size == 1) { /* 8K page */ - virtual_offset = virtual_address & 0x00001FFF; - physical_page_number = value_mr3 & 0xFFFFE000; - } else if (access_page_size == 5) { /* 1M page */ - virtual_offset = virtual_address & 0x000FFFFF; - physical_page_number = value_mr3 & 0xFFF00000; - } else { - return ERROR_FAIL; - } - - *physical_address = physical_page_number | virtual_offset; - - return ERROR_OK; -} - -static int aice_usb_init_cache(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_init_cache"); - - uint32_t value_cr1; - uint32_t value_cr2; - - aice_read_reg(coreid, CR1, &value_cr1); - aice_read_reg(coreid, CR2, &value_cr2); - - struct cache_info *icache = &core_info[coreid].icache; - - icache->set = value_cr1 & 0x7; - icache->log2_set = icache->set + 6; - icache->set = 64 << icache->set; - icache->way = ((value_cr1 >> 3) & 0x7) + 1; - icache->line_size = (value_cr1 >> 6) & 0x7; - if (icache->line_size != 0) { - icache->log2_line_size = icache->line_size + 2; - icache->line_size = 8 << (icache->line_size - 1); - } else { - icache->log2_line_size = 0; - } - - LOG_DEBUG("\ticache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", " - "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "", - icache->set, icache->way, icache->line_size, - icache->log2_set, icache->log2_line_size); - - struct cache_info *dcache = &core_info[coreid].dcache; - - dcache->set = value_cr2 & 0x7; - dcache->log2_set = dcache->set + 6; - dcache->set = 64 << dcache->set; - dcache->way = ((value_cr2 >> 3) & 0x7) + 1; - dcache->line_size = (value_cr2 >> 6) & 0x7; - if (dcache->line_size != 0) { - dcache->log2_line_size = dcache->line_size + 2; - dcache->line_size = 8 << (dcache->line_size - 1); - } else { - dcache->log2_line_size = 0; - } - - LOG_DEBUG("\tdcache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", " - "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "", - dcache->set, dcache->way, dcache->line_size, - dcache->log2_set, dcache->log2_line_size); - - core_info[coreid].cache_init = true; - - return ERROR_OK; -} - -static int aice_usb_dcache_inval_all(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_dcache_inval_all"); - - uint32_t set_index; - uint32_t way_index; - uint32_t cache_index; - uint32_t instructions[4]; - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1D_IX_INVAL(R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - - struct cache_info *dcache = &core_info[coreid].dcache; - - for (set_index = 0; set_index < dcache->set; set_index++) { - for (way_index = 0; way_index < dcache->way; way_index++) { - cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) | - (set_index << dcache->log2_line_size); - - if (aice_write_dtr(coreid, cache_index) != ERROR_OK) - return ERROR_FAIL; - - if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int aice_usb_dcache_va_inval(uint32_t coreid, uint32_t address) -{ - LOG_DEBUG("aice_usb_dcache_va_inval"); - - uint32_t instructions[4]; - - aice_write_dtr(coreid, address); - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1D_VA_INVAL(R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - - return aice_execute_dim(coreid, instructions, 4); -} - -static int aice_usb_dcache_wb_all(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_dcache_wb_all"); - - uint32_t set_index; - uint32_t way_index; - uint32_t cache_index; - uint32_t instructions[4]; - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1D_IX_WB(R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - - struct cache_info *dcache = &core_info[coreid].dcache; - - for (set_index = 0; set_index < dcache->set; set_index++) { - for (way_index = 0; way_index < dcache->way; way_index++) { - cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) | - (set_index << dcache->log2_line_size); - - if (aice_write_dtr(coreid, cache_index) != ERROR_OK) - return ERROR_FAIL; - - if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int aice_usb_dcache_va_wb(uint32_t coreid, uint32_t address) -{ - LOG_DEBUG("aice_usb_dcache_va_wb"); - - uint32_t instructions[4]; - - aice_write_dtr(coreid, address); - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1D_VA_WB(R0); - instructions[2] = DSB; - instructions[3] = BEQ_MINUS_12; - - return aice_execute_dim(coreid, instructions, 4); -} - -static int aice_usb_icache_inval_all(uint32_t coreid) -{ - LOG_DEBUG("aice_usb_icache_inval_all"); - - uint32_t set_index; - uint32_t way_index; - uint32_t cache_index; - uint32_t instructions[4]; - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1I_IX_INVAL(R0); - instructions[2] = ISB; - instructions[3] = BEQ_MINUS_12; - - struct cache_info *icache = &core_info[coreid].icache; - - for (set_index = 0; set_index < icache->set; set_index++) { - for (way_index = 0; way_index < icache->way; way_index++) { - cache_index = (way_index << (icache->log2_set + icache->log2_line_size)) | - (set_index << icache->log2_line_size); - - if (aice_write_dtr(coreid, cache_index) != ERROR_OK) - return ERROR_FAIL; - - if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int aice_usb_icache_va_inval(uint32_t coreid, uint32_t address) -{ - LOG_DEBUG("aice_usb_icache_va_inval"); - - uint32_t instructions[4]; - - aice_write_dtr(coreid, address); - - instructions[0] = MFSR_DTR(R0); - instructions[1] = L1I_VA_INVAL(R0); - instructions[2] = ISB; - instructions[3] = BEQ_MINUS_12; - - return aice_execute_dim(coreid, instructions, 4); -} - -static int aice_usb_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address) -{ - LOG_DEBUG("aice_usb_cache_ctl"); - - int result; - - if (core_info[coreid].cache_init == false) - aice_usb_init_cache(coreid); - - switch (subtype) { - case AICE_CACHE_CTL_L1D_INVALALL: - result = aice_usb_dcache_inval_all(coreid); - break; - case AICE_CACHE_CTL_L1D_VA_INVAL: - result = aice_usb_dcache_va_inval(coreid, address); - break; - case AICE_CACHE_CTL_L1D_WBALL: - result = aice_usb_dcache_wb_all(coreid); - break; - case AICE_CACHE_CTL_L1D_VA_WB: - result = aice_usb_dcache_va_wb(coreid, address); - break; - case AICE_CACHE_CTL_L1I_INVALALL: - result = aice_usb_icache_inval_all(coreid); - break; - case AICE_CACHE_CTL_L1I_VA_INVAL: - result = aice_usb_icache_va_inval(coreid, address); - break; - default: - result = ERROR_FAIL; - break; - } - - return result; -} - -static int aice_usb_set_retry_times(uint32_t a_retry_times) -{ - aice_max_retry_times = a_retry_times; - return ERROR_OK; -} - -static int aice_usb_program_edm(uint32_t coreid, char *command_sequence) -{ - char *command_str; - char *reg_name_0; - char *reg_name_1; - uint32_t data_value; - int i; - - /* init strtok() */ - command_str = strtok(command_sequence, ";"); - if (!command_str) - return ERROR_OK; - - do { - i = 0; - /* process one command */ - while (command_str[i] == ' ' || - command_str[i] == '\n' || - command_str[i] == '\r' || - command_str[i] == '\t') - i++; - - /* skip ' ', '\r', '\n', '\t' */ - command_str = command_str + i; - - if (strncmp(command_str, "write_misc", 10) == 0) { - reg_name_0 = strstr(command_str, "gen_port0"); - reg_name_1 = strstr(command_str, "gen_port1"); - - if (reg_name_0) { - data_value = strtoul(reg_name_0 + 9, NULL, 0); - - if (aice_write_misc(coreid, - NDS_EDM_MISC_GEN_PORT0, data_value) != ERROR_OK) - return ERROR_FAIL; - - } else if (reg_name_1) { - data_value = strtoul(reg_name_1 + 9, NULL, 0); - - if (aice_write_misc(coreid, - NDS_EDM_MISC_GEN_PORT1, data_value) != ERROR_OK) - return ERROR_FAIL; - } else { - LOG_ERROR("program EDM, unsupported misc register: %s", command_str); - } - } else { - LOG_ERROR("program EDM, unsupported command: %s", command_str); - } - - /* update command_str */ - command_str = strtok(NULL, ";"); - - } while (command_str); - - return ERROR_OK; -} - -static int aice_usb_set_command_mode(enum aice_command_mode command_mode) -{ - int retval = ERROR_OK; - - /* flush usb_packets_buffer as users change mode */ - retval = aice_usb_packet_flush(); - - if (command_mode == AICE_COMMAND_MODE_BATCH) { - /* reset batch buffer */ - aice_command_mode = AICE_COMMAND_MODE_NORMAL; - retval = aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL, 0x40000); - } - - aice_command_mode = command_mode; - - return retval; -} - -static int aice_usb_execute(uint32_t coreid, uint32_t *instructions, - uint32_t instruction_num) -{ - uint32_t i, j; - uint8_t current_instruction_num; - uint32_t dim_instructions[4] = {NOP, NOP, NOP, BEQ_MINUS_12}; - - /* To execute 4 instructions as a special case */ - if (instruction_num == 4) - return aice_execute_dim(coreid, instructions, 4); - - for (i = 0 ; i < instruction_num ; i += 3) { - if (instruction_num - i < 3) { - current_instruction_num = instruction_num - i; - for (j = current_instruction_num ; j < 3 ; j++) - dim_instructions[j] = NOP; - } else { - current_instruction_num = 3; - } - - memcpy(dim_instructions, instructions + i, - current_instruction_num * sizeof(uint32_t)); - - /** fill DIM */ - if (aice_write_dim(coreid, - dim_instructions, - 4) != ERROR_OK) - return ERROR_FAIL; - - /** clear DBGER.DPED */ - if (aice_write_misc(coreid, - NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK) - return ERROR_FAIL; - - /** execute DIM */ - if (aice_do_execute(coreid) != ERROR_OK) - return ERROR_FAIL; - - /** check DBGER.DPED */ - if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) { - - LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:" - "0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 ". -->", - dim_instructions[0], - dim_instructions[1], - dim_instructions[2], - dim_instructions[3]); - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int aice_usb_set_custom_srst_script(const char *script) -{ - custom_srst_script = strdup(script); - - return ERROR_OK; -} - -static int aice_usb_set_custom_trst_script(const char *script) -{ - custom_trst_script = strdup(script); - - return ERROR_OK; -} - -static int aice_usb_set_custom_restart_script(const char *script) -{ - custom_restart_script = strdup(script); - - return ERROR_OK; -} - -static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check) -{ - aice_count_to_check_dbger = count_to_check; - - return ERROR_OK; -} - -static int aice_usb_set_data_endian(uint32_t coreid, - enum aice_target_endian target_data_endian) -{ - data_endian = target_data_endian; - - return ERROR_OK; -} - -static int fill_profiling_batch_commands(uint32_t coreid, uint32_t reg_no) -{ - uint32_t dim_instructions[4]; - - aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH); - - /* halt */ - if (aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0) != ERROR_OK) - return ERROR_FAIL; - - /* backup $r0 */ - dim_instructions[0] = MTSR_DTR(0); - dim_instructions[1] = DSB; - dim_instructions[2] = NOP; - dim_instructions[3] = BEQ_MINUS_12; - if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK) - return ERROR_FAIL; - aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_0); - - /* get samples */ - if (nds32_reg_type(reg_no) == NDS32_REG_TYPE_GPR) { - /* general registers */ - dim_instructions[0] = MTSR_DTR(reg_no); - dim_instructions[1] = DSB; - dim_instructions[2] = NOP; - dim_instructions[3] = BEQ_MINUS_12; - } else if (nds32_reg_type(reg_no) == NDS32_REG_TYPE_SPR) { - /* user special registers */ - dim_instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no)); - dim_instructions[1] = MTSR_DTR(0); - dim_instructions[2] = DSB; - dim_instructions[3] = BEQ_MINUS_12; - } else { /* system registers */ - dim_instructions[0] = MFSR(0, nds32_reg_sr_index(reg_no)); - dim_instructions[1] = MTSR_DTR(0); - dim_instructions[2] = DSB; - dim_instructions[3] = BEQ_MINUS_12; - } - if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK) - return ERROR_FAIL; - aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_1); - - /* restore $r0 */ - aice_write_dtr_from_buffer(coreid, AICE_BATCH_DATA_BUFFER_0); - dim_instructions[0] = MFSR_DTR(0); - dim_instructions[1] = DSB; - dim_instructions[2] = NOP; - dim_instructions[3] = IRET; /* free run */ - if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK) - return ERROR_FAIL; - - aice_command_mode = AICE_COMMAND_MODE_NORMAL; - - /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */ - if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0, - usb_out_packets_buffer, - (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK) - return ERROR_FAIL; - - usb_out_packets_buffer_length = 0; - usb_in_packets_buffer_length = 0; - - return ERROR_OK; -} - -static int aice_usb_profiling(uint32_t coreid, uint32_t interval, uint32_t iteration, - uint32_t reg_no, uint32_t *samples, uint32_t *num_samples) -{ - uint32_t iteration_count; - uint32_t this_iteration; - int retval = ERROR_OK; - const uint32_t MAX_ITERATION = 250; - - *num_samples = 0; - - /* init DIM size */ - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE, 4) != ERROR_OK) - return ERROR_FAIL; - - /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR. - * Set it to circular buffer */ - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL, 0xC0000) != ERROR_OK) - return ERROR_FAIL; - - fill_profiling_batch_commands(coreid, reg_no); - - iteration_count = 0; - while (iteration_count < iteration) { - if (iteration - iteration_count < MAX_ITERATION) - this_iteration = iteration - iteration_count; - else - this_iteration = MAX_ITERATION; - - /* set number of iterations */ - uint32_t val_iteration; - val_iteration = interval << 16 | this_iteration; - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION, - val_iteration) != ERROR_OK) { - retval = ERROR_FAIL; - goto end_profiling; - } - - /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */ - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL, - 0x40000) != ERROR_OK) { - retval = ERROR_FAIL; - goto end_profiling; - } - - aice_usb_run(coreid); - - /* enable BATCH command */ - if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL, - 0x80000000) != ERROR_OK) { - aice_usb_halt(coreid); - retval = ERROR_FAIL; - goto end_profiling; - } - - /* wait a while (AICE bug, workaround) */ - alive_sleep(this_iteration); - - /* check status */ - uint32_t i; - uint32_t batch_status = 0; - - i = 0; - while (1) { - aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status); - - if (batch_status & 0x1) { - break; - } else if (batch_status & 0xE) { - aice_usb_halt(coreid); - retval = ERROR_FAIL; - goto end_profiling; - } - - if ((i % 30) == 0) - keep_alive(); - - i++; - } - - aice_usb_halt(coreid); - - /* get samples from batch data buffer */ - if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1, - samples + iteration_count, this_iteration) != ERROR_OK) { - retval = ERROR_FAIL; - goto end_profiling; - } - - iteration_count += this_iteration; - } - -end_profiling: - *num_samples = iteration_count; - - return retval; -} - -/** */ -struct aice_port_api_s aice_usb_api = { - /** */ - .open = aice_open_device, - /** */ - .close = aice_usb_close, - /** */ - .idcode = aice_usb_idcode, - /** */ - .state = aice_usb_state, - /** */ - .reset = aice_usb_reset, - /** */ - .assert_srst = aice_usb_assert_srst, - /** */ - .run = aice_usb_run, - /** */ - .halt = aice_usb_halt, - /** */ - .step = aice_usb_step, - /** */ - .read_reg = aice_usb_read_reg, - /** */ - .write_reg = aice_usb_write_reg, - /** */ - .read_reg_64 = aice_usb_read_reg_64, - /** */ - .write_reg_64 = aice_usb_write_reg_64, - /** */ - .read_mem_unit = aice_usb_read_memory_unit, - /** */ - .write_mem_unit = aice_usb_write_memory_unit, - /** */ - .read_mem_bulk = aice_usb_bulk_read_mem, - /** */ - .write_mem_bulk = aice_usb_bulk_write_mem, - /** */ - .read_debug_reg = aice_usb_read_debug_reg, - /** */ - .write_debug_reg = aice_usb_write_debug_reg, - /** */ - .set_jtag_clock = aice_usb_set_jtag_clock, - /** */ - .memory_access = aice_usb_memory_access, - /** */ - .memory_mode = aice_usb_memory_mode, - /** */ - .read_tlb = aice_usb_read_tlb, - /** */ - .cache_ctl = aice_usb_cache_ctl, - /** */ - .set_retry_times = aice_usb_set_retry_times, - /** */ - .program_edm = aice_usb_program_edm, - /** */ - .set_command_mode = aice_usb_set_command_mode, - /** */ - .execute = aice_usb_execute, - /** */ - .set_custom_srst_script = aice_usb_set_custom_srst_script, - /** */ - .set_custom_trst_script = aice_usb_set_custom_trst_script, - /** */ - .set_custom_restart_script = aice_usb_set_custom_restart_script, - /** */ - .set_count_to_check_dbger = aice_usb_set_count_to_check_dbger, - /** */ - .set_data_endian = aice_usb_set_data_endian, - /** */ - .profiling = aice_usb_profiling, -}; diff --git a/src/jtag/aice/aice_usb.h b/src/jtag/aice/aice_usb.h deleted file mode 100644 index d85d25f89d..0000000000 --- a/src/jtag/aice/aice_usb.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 by Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_AICE_AICE_USB_H -#define OPENOCD_JTAG_AICE_AICE_USB_H - -#include "aice_port.h" - -/* AICE USB timeout value */ -#define AICE_USB_TIMEOUT 5000 - -/* AICE USB buffer size */ -#define AICE_IN_BUFFER_SIZE 2048 -#define AICE_OUT_BUFFER_SIZE 2048 -#define AICE_IN_PACKETS_BUFFER_SIZE 2048 -#define AICE_OUT_PACKETS_BUFFER_SIZE 2048 -#define AICE_IN_BATCH_COMMAND_SIZE 512 -#define AICE_OUT_BATCH_COMMAND_SIZE 512 -#define AICE_IN_PACK_COMMAND_SIZE 2048 -#define AICE_OUT_PACK_COMMAND_SIZE 2048 - -/* Constants for AICE command READ_CTRL */ -#define AICE_READ_CTRL_GET_ICE_STATE 0x00 -#define AICE_READ_CTRL_GET_HARDWARE_VERSION 0x01 -#define AICE_READ_CTRL_GET_FPGA_VERSION 0x02 -#define AICE_READ_CTRL_GET_FIRMWARE_VERSION 0x03 -#define AICE_READ_CTRL_GET_JTAG_PIN_STATUS 0x04 -#define AICE_READ_CTRL_BATCH_BUF_INFO 0x22 -#define AICE_READ_CTRL_BATCH_STATUS 0x23 -#define AICE_READ_CTRL_BATCH_BUF0_STATE 0x31 -#define AICE_READ_CTRL_BATCH_BUF4_STATE 0x39 -#define AICE_READ_CTRL_BATCH_BUF5_STATE 0x3b - -/* Constants for AICE command WRITE_CTRL */ -#define AICE_WRITE_CTRL_TCK_CONTROL 0x00 -#define AICE_WRITE_CTRL_JTAG_PIN_CONTROL 0x01 -#define AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS 0x02 -#define AICE_WRITE_CTRL_RESERVED 0x03 -#define AICE_WRITE_CTRL_JTAG_PIN_STATUS 0x04 -#define AICE_WRITE_CTRL_CUSTOM_DELAY 0x0d -#define AICE_WRITE_CTRL_BATCH_CTRL 0x20 -#define AICE_WRITE_CTRL_BATCH_ITERATION 0x21 -#define AICE_WRITE_CTRL_BATCH_DIM_SIZE 0x22 -#define AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL 0x30 -#define AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL 0x38 -#define AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL 0x3a - -#define AICE_BATCH_COMMAND_BUFFER_0 0x0 -#define AICE_BATCH_COMMAND_BUFFER_1 0x1 -#define AICE_BATCH_COMMAND_BUFFER_2 0x2 -#define AICE_BATCH_COMMAND_BUFFER_3 0x3 -#define AICE_BATCH_DATA_BUFFER_0 0x4 -#define AICE_BATCH_DATA_BUFFER_1 0x5 -#define AICE_BATCH_DATA_BUFFER_2 0x6 -#define AICE_BATCH_DATA_BUFFER_3 0x7 - -/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */ -#define AICE_TCK_CONTROL_TCK3048 0x08 -#define AICE_TCK_CONTROL_TCK_SCAN 0x10 - -/* Constants for AICE command WRITE_CTRL:JTAG_PIN_CONTROL */ -#define AICE_JTAG_PIN_CONTROL_SRST 0x01 -#define AICE_JTAG_PIN_CONTROL_TRST 0x02 -#define AICE_JTAG_PIN_CONTROL_STOP 0x04 -#define AICE_JTAG_PIN_CONTROL_RESTART 0x08 - -/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */ -#define AICE_TCK_CONTROL_TCK_SCAN 0x10 - -/* Custom SRST/DBGI/TRST */ -#define AICE_CUSTOM_DELAY_SET_SRST 0x01 -#define AICE_CUSTOM_DELAY_CLEAN_SRST 0x02 -#define AICE_CUSTOM_DELAY_SET_DBGI 0x04 -#define AICE_CUSTOM_DELAY_CLEAN_DBGI 0x08 -#define AICE_CUSTOM_DELAY_SET_TRST 0x10 -#define AICE_CUSTOM_DELAY_CLEAN_TRST 0x20 - -struct aice_usb_handler_s { - unsigned int usb_read_ep; - unsigned int usb_write_ep; - struct libusb_device_handle *usb_handle; -}; - -struct cache_info { - uint32_t set; - uint32_t way; - uint32_t line_size; - - uint32_t log2_set; - uint32_t log2_line_size; -}; - -struct aice_nds32_info { - uint32_t edm_version; - uint32_t r0_backup; - uint32_t r1_backup; - uint32_t host_dtr_backup; - uint32_t target_dtr_backup; - uint32_t edmsw_backup; - uint32_t edm_ctl_backup; - bool debug_under_dex_on; - bool dex_use_psw_on; - bool host_dtr_valid; - bool target_dtr_valid; - enum nds_memory_access access_channel; - enum nds_memory_select memory_select; - enum aice_target_state_s core_state; - bool cache_init; - struct cache_info icache; - struct cache_info dcache; -}; - -extern struct aice_port_api_s aice_usb_api; - -int aice_read_ctrl(uint32_t address, uint32_t *data); -int aice_write_ctrl(uint32_t address, uint32_t data); - -#endif /* OPENOCD_JTAG_AICE_AICE_USB_H */ diff --git a/src/jtag/commands.c b/src/jtag/commands.c index 8d7875af28..1bca4e8df3 100644 --- a/src/jtag/commands.c +++ b/src/jtag/commands.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -33,7 +33,7 @@ struct cmd_queue_page { static struct cmd_queue_page *cmd_queue_pages; static struct cmd_queue_page *cmd_queue_pages_tail; -struct jtag_command *jtag_command_queue; +static struct jtag_command *jtag_command_queue; static struct jtag_command **next_command_pointer = &jtag_command_queue; void jtag_queue_command(struct jtag_command *cmd) @@ -103,7 +103,7 @@ void *cmd_queue_alloc(size_t size) if (*p_page) { p_page = &cmd_queue_pages_tail; - if (CMD_QUEUE_PAGE_SIZE - (*p_page)->used < size) + if (CMD_QUEUE_PAGE_SIZE < (*p_page)->used + size) p_page = &((*p_page)->next); } @@ -147,6 +147,11 @@ void jtag_command_queue_reset(void) next_command_pointer = &jtag_command_queue; } +struct jtag_command *jtag_command_queue_get(void) +{ + return jtag_command_queue; +} + /** * Copy a struct scan_field for insertion into the queue. * @@ -161,10 +166,9 @@ void jtag_scan_field_clone(struct scan_field *dst, const struct scan_field *src) enum scan_type jtag_scan_type(const struct scan_command *cmd) { - int i; int type = 0; - for (i = 0; i < cmd->num_fields; i++) { + for (unsigned int i = 0; i < cmd->num_fields; i++) { if (cmd->fields[i].in_value) type |= SCAN_IN; if (cmd->fields[i].out_value) @@ -174,13 +178,12 @@ enum scan_type jtag_scan_type(const struct scan_command *cmd) return type; } -int jtag_scan_size(const struct scan_command *cmd) +unsigned int jtag_scan_size(const struct scan_command *cmd) { - int bit_count = 0; - int i; + unsigned int bit_count = 0; /* count bits in scan command */ - for (i = 0; i < cmd->num_fields; i++) + for (unsigned int i = 0; i < cmd->num_fields; i++) bit_count += cmd->fields[i].num_bits; return bit_count; @@ -188,19 +191,16 @@ int jtag_scan_size(const struct scan_command *cmd) int jtag_build_buffer(const struct scan_command *cmd, uint8_t **buffer) { - int bit_count = 0; - int i; - - bit_count = jtag_scan_size(cmd); + unsigned int bit_count = jtag_scan_size(cmd); *buffer = calloc(1, DIV_ROUND_UP(bit_count, 8)); bit_count = 0; - LOG_DEBUG_IO("%s num_fields: %i", + LOG_DEBUG_IO("%s num_fields: %u", cmd->ir_scan ? "IRSCAN" : "DRSCAN", cmd->num_fields); - for (i = 0; i < cmd->num_fields; i++) { + for (unsigned int i = 0; i < cmd->num_fields; i++) { if (cmd->fields[i].out_value) { if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) { char *char_buf = buf_to_hex_str(cmd->fields[i].out_value, @@ -208,14 +208,14 @@ int jtag_build_buffer(const struct scan_command *cmd, uint8_t **buffer) ? DEBUG_JTAG_IOZ : cmd->fields[i].num_bits); - LOG_DEBUG("fields[%i].out_value[%i]: 0x%s", i, + LOG_DEBUG("fields[%u].out_value[%u]: 0x%s", i, cmd->fields[i].num_bits, char_buf); free(char_buf); } buf_set_buf(cmd->fields[i].out_value, 0, *buffer, bit_count, cmd->fields[i].num_bits); } else { - LOG_DEBUG_IO("fields[%i].out_value[%i]: NULL", + LOG_DEBUG_IO("fields[%u].out_value[%u]: NULL", i, cmd->fields[i].num_bits); } @@ -229,19 +229,18 @@ int jtag_build_buffer(const struct scan_command *cmd, uint8_t **buffer) int jtag_read_buffer(uint8_t *buffer, const struct scan_command *cmd) { - int i; int bit_count = 0; int retval; /* we return ERROR_OK, unless a check fails, or a handler reports a problem */ retval = ERROR_OK; - for (i = 0; i < cmd->num_fields; i++) { + for (unsigned int i = 0; i < cmd->num_fields; i++) { /* if neither in_value nor in_handler * are specified we don't have to examine this field */ if (cmd->fields[i].in_value) { - int num_bits = cmd->fields[i].num_bits; + const unsigned int num_bits = cmd->fields[i].num_bits; uint8_t *captured = buf_set_buf(buffer, bit_count, malloc(DIV_ROUND_UP(num_bits, 8)), 0, num_bits); @@ -251,7 +250,7 @@ int jtag_read_buffer(uint8_t *buffer, const struct scan_command *cmd) ? DEBUG_JTAG_IOZ : num_bits); - LOG_DEBUG("fields[%i].in_value[%i]: 0x%s", + LOG_DEBUG("fields[%u].in_value[%u]: 0x%s", i, num_bits, char_buf); free(char_buf); } diff --git a/src/jtag/commands.h b/src/jtag/commands.h index a8c7ffdc66..2923df1e6f 100644 --- a/src/jtag/commands.h +++ b/src/jtag/commands.h @@ -15,7 +15,7 @@ #define OPENOCD_JTAG_COMMANDS_H /** - * The inferred type of a scan_command_s structure, indicating whether + * The inferred type of a scan_command structure, indicating whether * the command has the host scan in from the device, the host scan out * to the device, or both. */ @@ -29,43 +29,43 @@ enum scan_type { }; /** - * The scan_command provide a means of encapsulating a set of scan_field_s + * The scan_command provide a means of encapsulating a set of scan_field * structures that should be scanned in/out to the device. */ struct scan_command { /** instruction/not data scan */ bool ir_scan; /** number of fields in *fields array */ - int num_fields; + unsigned int num_fields; /** pointer to an array of data scan fields */ struct scan_field *fields; /** state in which JTAG commands should finish */ - tap_state_t end_state; + enum tap_state end_state; }; struct statemove_command { /** state in which JTAG commands should finish */ - tap_state_t end_state; + enum tap_state end_state; }; struct pathmove_command { /** number of states in *path */ - int num_states; + unsigned int num_states; /** states that have to be passed */ - tap_state_t *path; + enum tap_state *path; }; struct runtest_command { /** number of cycles to spend in Run-Test/Idle state */ - int num_cycles; + unsigned int num_cycles; /** state in which JTAG commands should finish */ - tap_state_t end_state; + enum tap_state end_state; }; struct stableclocks_command { /** number of clock cycles that should be sent */ - int num_cycles; + unsigned int num_cycles; }; @@ -78,7 +78,7 @@ struct reset_command { struct end_state_command { /** state in which JTAG commands should finish */ - tap_state_t end_state; + enum tap_state end_state; }; struct sleep_command { @@ -100,7 +100,7 @@ struct sleep_command { */ struct tms_command { /** How many bits should be clocked out. */ - unsigned num_bits; + unsigned int num_bits; /** The bits to clock out; the LSB is bit 0 of bits[0]. */ const uint8_t *bits; }; @@ -123,7 +123,7 @@ union jtag_command_container { /** * The type of the @c jtag_command_container contained by a - * @c jtag_command_s structure. + * @c jtag_command structure. */ enum jtag_command_type { JTAG_SCAN = 1, @@ -149,17 +149,15 @@ struct jtag_command { struct jtag_command *next; }; -/** The current queue of jtag_command_s structures. */ -extern struct jtag_command *jtag_command_queue; - void *cmd_queue_alloc(size_t size); void jtag_queue_command(struct jtag_command *cmd); void jtag_command_queue_reset(void); +struct jtag_command *jtag_command_queue_get(void); void jtag_scan_field_clone(struct scan_field *dst, const struct scan_field *src); enum scan_type jtag_scan_type(const struct scan_command *cmd); -int jtag_scan_size(const struct scan_command *cmd); +unsigned int jtag_scan_size(const struct scan_command *cmd); int jtag_read_buffer(uint8_t *buffer, const struct scan_command *cmd); int jtag_build_buffer(const struct scan_command *cmd, uint8_t **buffer); diff --git a/src/jtag/core.c b/src/jtag/core.c index 27c7b3de49..6dd2144c63 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 Zachary T Welch * @@ -39,7 +39,7 @@ #include "server/ipdbg.h" /** The number of JTAG queue flushes (for profiling and debugging purposes). */ -static int jtag_flush_queue_count; +static unsigned int jtag_flush_queue_count; /* Sleep this # of ms after flushing the queue */ static int jtag_flush_queue_sleep; @@ -48,8 +48,10 @@ static void jtag_add_scan_check(struct jtag_tap *active, void (*jtag_add_scan)(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, - tap_state_t state), - int in_num_fields, struct scan_field *in_fields, tap_state_t state); + enum tap_state state), + int in_num_fields, struct scan_field *in_fields, enum tap_state state); + +static int jtag_error_clear(void); /** * The jtag_error variable is set when an error occurs while executing @@ -85,17 +87,17 @@ static int jtag_srst = -1; static struct jtag_tap *__jtag_all_taps; static enum reset_types jtag_reset_config = RESET_NONE; -tap_state_t cmd_queue_cur_state = TAP_RESET; +enum tap_state cmd_queue_cur_state = TAP_RESET; static bool jtag_verify_capture_ir = true; -static int jtag_verify = 1; +static bool jtag_verify = true; /* how long the OpenOCD should wait before attempting JTAG communication after reset lines *deasserted (in ms) */ -static int adapter_nsrst_delay; /* default to no nSRST delay */ -static int jtag_ntrst_delay;/* default to no nTRST delay */ -static int adapter_nsrst_assert_width; /* width of assertion */ -static int jtag_ntrst_assert_width; /* width of assertion */ +static unsigned int adapter_nsrst_delay; /* default to no nSRST delay */ +static unsigned int jtag_ntrst_delay;/* default to no nTRST delay */ +static unsigned int adapter_nsrst_assert_width; /* width of assertion */ +static unsigned int jtag_ntrst_assert_width; /* width of assertion */ /** * Contains a single callback along with a pointer that will be passed @@ -127,7 +129,11 @@ void jtag_set_error(int error) jtag_error = error; } -int jtag_error_clear(void) +/** + * Resets jtag_error to ERROR_OK, returning its previous value. + * @returns The previous value of @c jtag_error. + */ +static int jtag_error_clear(void) { int temp = jtag_error; jtag_error = ERROR_OK; @@ -136,14 +142,19 @@ int jtag_error_clear(void) /************/ -static bool jtag_poll = 1; +static bool jtag_poll = true; +static bool jtag_poll_en = true; bool is_jtag_poll_safe(void) { /* Polling can be disabled explicitly with set_enabled(false). + * It can also be masked with mask(). * It is also implicitly disabled while TRST is active and * while SRST is gating the JTAG clock. */ + if (!jtag_poll_en) + return false; + if (!transport_is_jtag()) return jtag_poll; @@ -162,6 +173,18 @@ void jtag_poll_set_enabled(bool value) jtag_poll = value; } +bool jtag_poll_mask(void) +{ + bool retval = jtag_poll_en; + jtag_poll_en = false; + return retval; +} + +void jtag_poll_unmask(bool saved) +{ + jtag_poll_en = saved; +} + /************/ struct jtag_tap *jtag_all_taps(void) @@ -169,10 +192,10 @@ struct jtag_tap *jtag_all_taps(void) return __jtag_all_taps; }; -unsigned jtag_tap_count(void) +static unsigned int jtag_tap_count(void) { struct jtag_tap *t = jtag_all_taps(); - unsigned n = 0; + unsigned int n = 0; while (t) { n++; t = t->next_tap; @@ -180,10 +203,10 @@ unsigned jtag_tap_count(void) return n; } -unsigned jtag_tap_count_enabled(void) +unsigned int jtag_tap_count_enabled(void) { struct jtag_tap *t = jtag_all_taps(); - unsigned n = 0; + unsigned int n = 0; while (t) { if (t->enabled) n++; @@ -195,7 +218,7 @@ unsigned jtag_tap_count_enabled(void) /** Append a new TAP to the chain of all taps. */ static void jtag_tap_add(struct jtag_tap *t) { - unsigned jtag_num_taps = 0; + unsigned int jtag_num_taps = 0; struct jtag_tap **tap = &__jtag_all_taps; while (*tap) { @@ -207,7 +230,7 @@ static void jtag_tap_add(struct jtag_tap *t) } /* returns a pointer to the n-th device in the scan chain */ -struct jtag_tap *jtag_tap_by_position(unsigned n) +struct jtag_tap *jtag_tap_by_position(unsigned int n) { struct jtag_tap *t = jtag_all_taps(); @@ -229,7 +252,7 @@ struct jtag_tap *jtag_tap_by_string(const char *s) } /* no tap found by name, so try to parse the name as a number */ - unsigned n; + unsigned int n; if (parse_uint(s, &n) != ERROR_OK) return NULL; @@ -327,7 +350,7 @@ static void jtag_checks(void) assert(jtag_trst == 0); } -static void jtag_prelude(tap_state_t state) +static void jtag_prelude(enum tap_state state) { jtag_checks(); @@ -337,7 +360,7 @@ static void jtag_prelude(tap_state_t state) } void jtag_add_ir_scan_noverify(struct jtag_tap *active, const struct scan_field *in_fields, - tap_state_t state) + enum tap_state state) { jtag_prelude(state); @@ -348,13 +371,13 @@ void jtag_add_ir_scan_noverify(struct jtag_tap *active, const struct scan_field static void jtag_add_ir_scan_noverify_callback(struct jtag_tap *active, int dummy, const struct scan_field *in_fields, - tap_state_t state) + enum tap_state state) { jtag_add_ir_scan_noverify(active, in_fields, state); } /* If fields->in_value is filled out, then the captured IR value will be checked */ -void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state) +void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, enum tap_state state) { assert(state != TAP_RESET); @@ -373,7 +396,7 @@ void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap } void jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, - tap_state_t state) + enum tap_state state) { assert(out_bits); assert(state != TAP_RESET); @@ -403,8 +426,8 @@ static void jtag_add_scan_check(struct jtag_tap *active, void (*jtag_add_scan)( struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, - tap_state_t state), - int in_num_fields, struct scan_field *in_fields, tap_state_t state) + enum tap_state state), + int in_num_fields, struct scan_field *in_fields, enum tap_state state) { jtag_add_scan(active, in_num_fields, in_fields, state); @@ -422,7 +445,7 @@ static void jtag_add_scan_check(struct jtag_tap *active, void (*jtag_add_scan)( void jtag_add_dr_scan_check(struct jtag_tap *active, int in_num_fields, struct scan_field *in_fields, - tap_state_t state) + enum tap_state state) { if (jtag_verify) jtag_add_scan_check(active, jtag_add_dr_scan, in_num_fields, in_fields, state); @@ -434,7 +457,7 @@ void jtag_add_dr_scan_check(struct jtag_tap *active, void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, - tap_state_t state) + enum tap_state state) { assert(state != TAP_RESET); @@ -446,7 +469,7 @@ void jtag_add_dr_scan(struct jtag_tap *active, } void jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, - tap_state_t state) + enum tap_state state) { assert(out_bits); assert(state != TAP_RESET); @@ -482,7 +505,7 @@ void jtag_add_tlr(void) * * @todo Update naming conventions to stop assuming everything is JTAG. */ -int jtag_add_tms_seq(unsigned nbits, const uint8_t *seq, enum tap_state state) +int jtag_add_tms_seq(unsigned int nbits, const uint8_t *seq, enum tap_state state) { int retval; @@ -497,9 +520,9 @@ int jtag_add_tms_seq(unsigned nbits, const uint8_t *seq, enum tap_state state) return retval; } -void jtag_add_pathmove(int num_states, const tap_state_t *path) +void jtag_add_pathmove(unsigned int num_states, const enum tap_state *path) { - tap_state_t cur_state = cmd_queue_cur_state; + enum tap_state cur_state = cmd_queue_cur_state; /* the last state has to be a stable state */ if (!tap_is_state_stable(path[num_states - 1])) { @@ -508,7 +531,7 @@ void jtag_add_pathmove(int num_states, const tap_state_t *path) return; } - for (int i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (path[i] == TAP_RESET) { LOG_ERROR("BUG: TAP_RESET is not a valid state for pathmove sequences"); jtag_set_error(ERROR_JTAG_STATE_INVALID); @@ -531,9 +554,9 @@ void jtag_add_pathmove(int num_states, const tap_state_t *path) cmd_queue_cur_state = path[num_states - 1]; } -int jtag_add_statemove(tap_state_t goal_state) +int jtag_add_statemove(enum tap_state goal_state) { - tap_state_t cur_state = cmd_queue_cur_state; + enum tap_state cur_state = cmd_queue_cur_state; if (goal_state != cur_state) { LOG_DEBUG("cur_state=%s goal_state=%s", @@ -550,12 +573,12 @@ int jtag_add_statemove(tap_state_t goal_state) /* nothing to do */; else if (tap_is_state_stable(cur_state) && tap_is_state_stable(goal_state)) { - unsigned tms_bits = tap_get_tms_path(cur_state, goal_state); - unsigned tms_count = tap_get_tms_path_len(cur_state, goal_state); - tap_state_t moves[8]; + unsigned int tms_bits = tap_get_tms_path(cur_state, goal_state); + unsigned int tms_count = tap_get_tms_path_len(cur_state, goal_state); + enum tap_state moves[8]; assert(tms_count < ARRAY_SIZE(moves)); - for (unsigned i = 0; i < tms_count; i++, tms_bits >>= 1) { + for (unsigned int i = 0; i < tms_count; i++, tms_bits >>= 1) { bool bit = tms_bits & 1; cur_state = tap_state_transition(cur_state, bit); @@ -572,14 +595,14 @@ int jtag_add_statemove(tap_state_t goal_state) return ERROR_OK; } -void jtag_add_runtest(int num_cycles, tap_state_t state) +void jtag_add_runtest(unsigned int num_cycles, enum tap_state state) { jtag_prelude(state); jtag_set_error(interface_jtag_add_runtest(num_cycles, state)); } -void jtag_add_clocks(int num_cycles) +void jtag_add_clocks(unsigned int num_cycles) { if (!tap_is_state_stable(cmd_queue_cur_state)) { LOG_ERROR("jtag_add_clocks() called with TAP in unstable state \"%s\"", @@ -608,6 +631,13 @@ static int adapter_system_reset(int req_srst) /* Maybe change SRST signal state */ if (jtag_srst != req_srst) { + if (!adapter_driver->reset) { + if (req_srst) + LOG_ERROR("Adapter driver does not implement SRST handling"); + + return ERROR_NOT_IMPLEMENTED; + } + retval = adapter_driver->reset(0, req_srst); if (retval != ERROR_OK) { LOG_ERROR("SRST error"); @@ -864,9 +894,9 @@ static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value, int compare_failed; if (in_check_mask) - compare_failed = buf_cmp_mask(captured, in_check_value, in_check_mask, num_bits); + compare_failed = !buf_eq_mask(captured, in_check_value, in_check_mask, num_bits); else - compare_failed = buf_cmp(captured, in_check_value, num_bits); + compare_failed = !buf_eq(captured, in_check_value, num_bits); if (compare_failed) { char *captured_str, *in_check_value_str; @@ -934,25 +964,25 @@ int default_interface_jtag_execute_queue(void) return ERROR_OK; } - int result = adapter_driver->jtag_ops->execute_queue(); + struct jtag_command *cmd = jtag_command_queue_get(); + int result = adapter_driver->jtag_ops->execute_queue(cmd); - struct jtag_command *cmd = jtag_command_queue; while (debug_level >= LOG_LVL_DEBUG_IO && cmd) { switch (cmd->type) { case JTAG_SCAN: LOG_DEBUG_IO("JTAG %s SCAN to %s", cmd->cmd.scan->ir_scan ? "IR" : "DR", tap_state_name(cmd->cmd.scan->end_state)); - for (int i = 0; i < cmd->cmd.scan->num_fields; i++) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++) { struct scan_field *field = cmd->cmd.scan->fields + i; if (field->out_value) { char *str = buf_to_hex_str(field->out_value, field->num_bits); - LOG_DEBUG_IO(" %db out: %s", field->num_bits, str); + LOG_DEBUG_IO(" %ub out: %s", field->num_bits, str); free(str); } if (field->in_value) { char *str = buf_to_hex_str(field->in_value, field->num_bits); - LOG_DEBUG_IO(" %db in: %s", field->num_bits, str); + LOG_DEBUG_IO(" %ub in: %s", field->num_bits, str); free(str); } } @@ -1012,7 +1042,7 @@ void jtag_execute_queue_noclear(void) } } -int jtag_get_flush_queue_count(void) +unsigned int jtag_get_flush_queue_count(void) { return jtag_flush_queue_count; } @@ -1032,7 +1062,7 @@ static int jtag_reset_callback(enum jtag_event event, void *priv) /* current instruction is either BYPASS or IDCODE */ buf_set_ones(tap->cur_instr, tap->ir_length); - tap->bypass = 1; + tap->bypass = true; } return ERROR_OK; @@ -1064,7 +1094,7 @@ void jtag_sleep(uint32_t us) /* a larger IR length than we ever expect to autoprobe */ #define JTAG_IRLEN_MAX 60 -static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcode) +static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned int num_idcode) { struct scan_field field = { .num_bits = num_idcode * 32, @@ -1073,7 +1103,7 @@ static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcod }; /* initialize to the end of chain ID value */ - for (unsigned i = 0; i < num_idcode; i++) + for (unsigned int i = 0; i < num_idcode; i++) buf_set_u32(idcode_buffer, i * 32, 32, END_OF_CHAIN_FLAG); jtag_add_plain_dr_scan(field.num_bits, field.out_value, field.in_value, TAP_DRPAUSE); @@ -1081,12 +1111,12 @@ static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcod return jtag_execute_queue(); } -static bool jtag_examine_chain_check(uint8_t *idcodes, unsigned count) +static bool jtag_examine_chain_check(uint8_t *idcodes, unsigned int count) { uint8_t zero_check = 0x0; uint8_t one_check = 0xff; - for (unsigned i = 0; i < count * 4; i++) { + for (unsigned int i = 0; i < count * 4; i++) { zero_check |= idcodes[i]; one_check &= idcodes[i]; } @@ -1141,7 +1171,8 @@ static bool jtag_idcode_is_final(uint32_t idcode) * with the JTAG chain earlier, gives more helpful/explicit error messages. * Returns TRUE iff garbage was found. */ -static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned max) +static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned int count, + unsigned int max) { bool triggered = false; for (; count < max - 31; count += 32) { @@ -1160,7 +1191,7 @@ static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned ma static bool jtag_examine_chain_match_tap(const struct jtag_tap *tap) { - if (tap->expected_ids_cnt == 0 || !tap->hasidcode) + if (tap->expected_ids_cnt == 0 || !tap->has_idcode) return true; /* optionally ignore the JTAG version field - bits 28-31 of IDCODE */ @@ -1168,26 +1199,26 @@ static bool jtag_examine_chain_match_tap(const struct jtag_tap *tap) uint32_t idcode = tap->idcode & mask; /* Loop over the expected identification codes and test for a match */ - for (unsigned ii = 0; ii < tap->expected_ids_cnt; ii++) { - uint32_t expected = tap->expected_ids[ii] & mask; + for (unsigned int i = 0; i < tap->expected_ids_cnt; i++) { + uint32_t expected = tap->expected_ids[i] & mask; if (idcode == expected) return true; /* treat "-expected-id 0" as a "don't-warn" wildcard */ - if (tap->expected_ids[ii] == 0) + if (tap->expected_ids[i] == 0) return true; } /* If none of the expected ids matched, warn */ jtag_examine_chain_display(LOG_LVL_WARNING, "UNEXPECTED", tap->dotted_name, tap->idcode); - for (unsigned ii = 0; ii < tap->expected_ids_cnt; ii++) { + for (unsigned int i = 0; i < tap->expected_ids_cnt; i++) { char msg[32]; - snprintf(msg, sizeof(msg), "expected %u of %u", ii + 1, tap->expected_ids_cnt); + snprintf(msg, sizeof(msg), "expected %u of %u", i + 1, tap->expected_ids_cnt); jtag_examine_chain_display(LOG_LVL_ERROR, msg, - tap->dotted_name, tap->expected_ids[ii]); + tap->dotted_name, tap->expected_ids[i]); } return false; } @@ -1198,7 +1229,7 @@ static bool jtag_examine_chain_match_tap(const struct jtag_tap *tap) static int jtag_examine_chain(void) { int retval; - unsigned max_taps = jtag_tap_count(); + unsigned int max_taps = jtag_tap_count(); /* Autoprobe up to this many. */ if (max_taps < JTAG_MAX_AUTO_TAPS) @@ -1226,9 +1257,9 @@ static int jtag_examine_chain(void) /* Point at the 1st predefined tap, if any */ struct jtag_tap *tap = jtag_tap_next_enabled(NULL); - unsigned bit_count = 0; - unsigned autocount = 0; - for (unsigned i = 0; i < max_taps; i++) { + unsigned int bit_count = 0; + unsigned int autocount = 0; + for (unsigned int i = 0; i < max_taps; i++) { assert(bit_count < max_taps * 32); uint32_t idcode = buf_get_u32(idcode_buffer, bit_count, 32); @@ -1266,13 +1297,13 @@ static int jtag_examine_chain(void) /* Zero for LSB indicates a device in bypass */ LOG_INFO("TAP %s does not have valid IDCODE (idcode=0x%" PRIx32 ")", tap->dotted_name, idcode); - tap->hasidcode = false; + tap->has_idcode = false; tap->idcode = 0; bit_count += 1; } else { /* Friendly devices support IDCODE */ - tap->hasidcode = true; + tap->has_idcode = true; tap->idcode = idcode; jtag_examine_chain_display(LOG_LVL_INFO, "tap/device found", tap->dotted_name, idcode); @@ -1320,7 +1351,7 @@ static int jtag_validate_ircapture(void) int retval; /* when autoprobing, accommodate huge IR lengths */ - int total_ir_length = 0; + unsigned int total_ir_length = 0; for (tap = jtag_tap_next_enabled(NULL); tap; tap = jtag_tap_next_enabled(tap)) { if (tap->ir_length == 0) total_ir_length += JTAG_IRLEN_MAX; @@ -1379,7 +1410,7 @@ static int jtag_validate_ircapture(void) && tap->ir_length < JTAG_IRLEN_MAX) { tap->ir_length++; } - LOG_WARNING("AUTO %s - use \"jtag newtap %s %s -irlen %d " + LOG_WARNING("AUTO %s - use \"jtag newtap %s %s -irlen %u " "-expected-id 0x%08" PRIx32 "\"", tap->dotted_name, tap->chip, tap->tapname, tap->ir_length, tap->idcode); } @@ -1428,8 +1459,8 @@ static int jtag_validate_ircapture(void) void jtag_tap_init(struct jtag_tap *tap) { - unsigned ir_len_bits; - unsigned ir_len_bytes; + unsigned int ir_len_bits; + unsigned int ir_len_bytes; /* if we're autoprobing, cope with potentially huge ir_length */ ir_len_bits = tap->ir_length ? tap->ir_length : JTAG_IRLEN_MAX; @@ -1447,18 +1478,17 @@ void jtag_tap_init(struct jtag_tap *tap) buf_set_u32(tap->expected_mask, 0, ir_len_bits, tap->ir_capture_mask); /* TAP will be in bypass mode after jtag_validate_ircapture() */ - tap->bypass = 1; + tap->bypass = true; buf_set_ones(tap->cur_instr, tap->ir_length); /* register the reset callback for the TAP */ jtag_register_event_callback(&jtag_reset_callback, tap); jtag_tap_add(tap); - LOG_DEBUG("Created Tap: %s @ abs position %d, " - "irlen %d, capture: 0x%x mask: 0x%x", tap->dotted_name, + LOG_DEBUG("Created Tap: %s @ abs position %u, " + "irlen %u, capture: 0x%" PRIx32 " mask: 0x%" PRIx32, tap->dotted_name, tap->abs_chain_position, tap->ir_length, - (unsigned) tap->ir_capture_value, - (unsigned) tap->ir_capture_mask); + tap->ir_capture_value, tap->ir_capture_mask); } void jtag_tap_free(struct jtag_tap *tap) @@ -1732,37 +1762,36 @@ int jtag_get_srst(void) return jtag_srst == 1; } -void jtag_set_nsrst_delay(unsigned delay) +void jtag_set_nsrst_delay(unsigned int delay) { adapter_nsrst_delay = delay; } -unsigned jtag_get_nsrst_delay(void) +unsigned int jtag_get_nsrst_delay(void) { return adapter_nsrst_delay; } -void jtag_set_ntrst_delay(unsigned delay) +void jtag_set_ntrst_delay(unsigned int delay) { jtag_ntrst_delay = delay; } -unsigned jtag_get_ntrst_delay(void) +unsigned int jtag_get_ntrst_delay(void) { return jtag_ntrst_delay; } - -void jtag_set_nsrst_assert_width(unsigned delay) +void jtag_set_nsrst_assert_width(unsigned int delay) { adapter_nsrst_assert_width = delay; } -unsigned jtag_get_nsrst_assert_width(void) +unsigned int jtag_get_nsrst_assert_width(void) { return adapter_nsrst_assert_width; } -void jtag_set_ntrst_assert_width(unsigned delay) +void jtag_set_ntrst_assert_width(unsigned int delay) { jtag_ntrst_assert_width = delay; } -unsigned jtag_get_ntrst_assert_width(void) +unsigned int jtag_get_ntrst_assert_width(void) { return jtag_ntrst_assert_width; } @@ -1794,7 +1823,7 @@ static int jtag_select(struct command_context *ctx) } static struct transport jtag_transport = { - .name = "jtag", + .id = TRANSPORT_JTAG, .select = jtag_select, .init = jtag_init, }; @@ -1839,7 +1868,7 @@ int adapter_resets(int trst, int srst) transport_is_swim()) { if (trst == TRST_ASSERT) { LOG_ERROR("transport %s has no trst signal", - get_current_transport()->name); + get_current_transport_name()); return ERROR_FAIL; } @@ -1855,7 +1884,7 @@ int adapter_resets(int trst, int srst) return ERROR_OK; LOG_ERROR("reset is not supported on transport %s", - get_current_transport()->name); + get_current_transport_name()); return ERROR_FAIL; } @@ -1874,7 +1903,7 @@ int adapter_assert_reset(void) return adapter_system_reset(1); else if (get_current_transport()) LOG_ERROR("reset is not supported on %s", - get_current_transport()->name); + get_current_transport_name()); else LOG_ERROR("transport is not selected"); return ERROR_FAIL; @@ -1891,7 +1920,7 @@ int adapter_deassert_reset(void) return adapter_system_reset(0); else if (get_current_transport()) LOG_ERROR("reset is not supported on %s", - get_current_transport()->name); + get_current_transport_name()); else LOG_ERROR("transport is not selected"); return ERROR_FAIL; diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am index 6410f37545..b0dd8e3ad1 100644 --- a/src/jtag/drivers/Makefile.am +++ b/src/jtag/drivers/Makefile.am @@ -123,6 +123,17 @@ ulinkdir = $(pkgdatadir)/OpenULINK dist_ulink_DATA = $(ULINK_FIRMWARE)/ulink_firmware.hex %C%_libocdjtagdrivers_la_LIBADD += -lm endif + +if ANGIE + angiedir = $(pkgdatadir)/angie + DRIVERFILES += %D%/angie.c + DRIVERFILES += %D%/angie/include/msgtypes.h + EXTRA_DIST += %D%/angie/README + dist_angie_DATA = %D%/angie/angie_firmware.bin + dist_angie_DATA += %D%/angie/angie_bitstream.bit + %C%_libocdjtagdrivers_la_LIBADD += -lm +endif + if VSLLINK DRIVERFILES += %D%/versaloon/usbtoxxx/usbtogpio.c DRIVERFILES += %D%/versaloon/usbtoxxx/usbtojtagraw.c @@ -135,7 +146,7 @@ endif if ARMJTAGEW DRIVERFILES += %D%/arm-jtag-ew.c endif -if BUSPIRATE +if BUS_PIRATE DRIVERFILES += %D%/buspirate.c endif if REMOTE_BITBANG @@ -153,6 +164,9 @@ endif if RSHIM DRIVERFILES += %D%/rshim.c endif +if DMEM +DRIVERFILES += %D%/dmem.c +endif if OSBDM DRIVERFILES += %D%/osbdm.c endif @@ -162,6 +176,9 @@ endif if SYSFSGPIO DRIVERFILES += %D%/sysfsgpio.c endif +if LINUXSPIDEV +DRIVERFILES += %D%/linuxspidev.c +endif if XLNX_PCIE_XVC DRIVERFILES += %D%/xlnx-pcie-xvc.c endif diff --git a/src/jtag/drivers/OpenULINK/src/delay.c b/src/jtag/drivers/OpenULINK/src/delay.c index d858a8ace1..b68e8148a8 100644 --- a/src/jtag/drivers/OpenULINK/src/delay.c +++ b/src/jtag/drivers/OpenULINK/src/delay.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Martin Schmoelzer * diff --git a/src/jtag/drivers/OpenULINK/src/jtag.c b/src/jtag/drivers/OpenULINK/src/jtag.c index e6b57eae9b..c9253a3414 100644 --- a/src/jtag/drivers/OpenULINK/src/jtag.c +++ b/src/jtag/drivers/OpenULINK/src/jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Martin Schmoelzer * diff --git a/src/jtag/drivers/OpenULINK/src/main.c b/src/jtag/drivers/OpenULINK/src/main.c index c8d4e18b09..51d3a3b947 100644 --- a/src/jtag/drivers/OpenULINK/src/main.c +++ b/src/jtag/drivers/OpenULINK/src/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Martin Schmoelzer * diff --git a/src/jtag/drivers/OpenULINK/src/protocol.c b/src/jtag/drivers/OpenULINK/src/protocol.c index 319785e66b..b3d562236d 100644 --- a/src/jtag/drivers/OpenULINK/src/protocol.c +++ b/src/jtag/drivers/OpenULINK/src/protocol.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Martin Schmoelzer * diff --git a/src/jtag/drivers/OpenULINK/src/usb.c b/src/jtag/drivers/OpenULINK/src/usb.c index fa0ff6c6d2..408e212178 100644 --- a/src/jtag/drivers/OpenULINK/src/usb.c +++ b/src/jtag/drivers/OpenULINK/src/usb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011-2013 by Martin Schmoelzer * diff --git a/src/jtag/drivers/am335xgpio.c b/src/jtag/drivers/am335xgpio.c index 62e276737d..a4727cc891 100644 --- a/src/jtag/drivers/am335xgpio.c +++ b/src/jtag/drivers/am335xgpio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2022 by Steve Marple, stevemarple@googlemail.com * @@ -10,23 +10,24 @@ #include "config.h" #endif +#include <jtag/adapter.h> #include <jtag/interface.h> #include <transport/transport.h> #include "bitbang.h" #include <sys/mman.h> -/* - * GPIO register base addresses. Values taken from "AM335x and AMIC110 Sitara +/* GPIO register base addresses. Values taken from "AM335x and AMIC110 Sitara * Processors Technical Reference Manual", Chapter 2 Memory Map. */ -#define AM335XGPIO_NUM_GPIO_PORTS 4 +#define AM335XGPIO_NUM_GPIO_PER_CHIP 32 +#define AM335XGPIO_NUM_GPIO_CHIPS 4 #define AM335XGPIO_GPIO0_HW_ADDR 0x44E07000 #define AM335XGPIO_GPIO1_HW_ADDR 0x4804C000 #define AM335XGPIO_GPIO2_HW_ADDR 0x481AC000 #define AM335XGPIO_GPIO3_HW_ADDR 0x481AE000 -/* 32-bit offsets from GPIO port base address. Values taken from "AM335x and +/* 32-bit offsets from GPIO chip base address. Values taken from "AM335x and * AMIC110 Sitara Processors Technical Reference Manual", Chapter 25 * General-Purpose Input/Output. */ @@ -36,34 +37,34 @@ #define AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET (0x190 / 4) #define AM335XGPIO_GPIO_SETDATAOUT_OFFSET (0x194 / 4) -/* GPIOs are integer values; need to map to a port module, and the pin within - * that module. GPIOs 0 to 31 map to GPIO0, 32 to 63 to GPIO1 etc. This scheme - * matches that used by Linux on the BeagleBone. - */ -#define AM335XGPIO_PORT_NUM(gpio_num) ((gpio_num) / 32) -#define AM335XGPIO_BIT_NUM(gpio_num) ((gpio_num) % 32) -#define AM335XGPIO_BIT_MASK(gpio_num) BIT(AM335XGPIO_BIT_NUM(gpio_num)) +#define AM335XGPIO_READ_REG(chip_num, offset) \ + (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset))) -#define AM335XGPIO_READ_REG(gpio_num, offset) \ - (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset))) +#define AM335XGPIO_WRITE_REG(chip_num, offset, value) \ + (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) = (value)) -#define AM335XGPIO_WRITE_REG(gpio_num, offset, value) \ - (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) = (value)) +#define AM335XGPIO_SET_REG_BITS(chip_num, offset, bit_mask) \ + (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) |= (bit_mask)) -#define AM335XGPIO_SET_REG_BITS(gpio_num, offset, bit_mask) \ - (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) |= (bit_mask)) +#define AM335XGPIO_CLEAR_REG_BITS(chip_num, offset, bit_mask) \ + (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) &= ~(bit_mask)) -#define AM335XGPIO_CLEAR_REG_BITS(gpio_num, offset, bit_mask) \ - (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) &= ~(bit_mask)) +#define AM335XGPIO_SET_INPUT(gpio_config) \ + AM335XGPIO_SET_REG_BITS((gpio_config)->chip_num, AM335XGPIO_GPIO_OE_OFFSET, BIT((gpio_config)->gpio_num)) +#define AM335XGPIO_SET_OUTPUT(gpio_config) \ + AM335XGPIO_CLEAR_REG_BITS((gpio_config)->chip_num, AM335XGPIO_GPIO_OE_OFFSET, BIT((gpio_config)->gpio_num)) +#define AM335XGPIO_SET_HIGH(gpio_config) \ + AM335XGPIO_WRITE_REG((gpio_config)->chip_num, AM335XGPIO_GPIO_SETDATAOUT_OFFSET, BIT((gpio_config)->gpio_num)) +#define AM335XGPIO_SET_LOW(gpio_config) \ + AM335XGPIO_WRITE_REG((gpio_config)->chip_num, AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET, BIT((gpio_config)->gpio_num)) -enum amx335gpio_gpio_mode { +enum amx335gpio_initial_gpio_mode { AM335XGPIO_GPIO_MODE_INPUT, - AM335XGPIO_GPIO_MODE_OUTPUT, /* To set output mode but not state */ AM335XGPIO_GPIO_MODE_OUTPUT_LOW, AM335XGPIO_GPIO_MODE_OUTPUT_HIGH, }; -static const uint32_t am335xgpio_gpio_port_hw_addr[AM335XGPIO_NUM_GPIO_PORTS] = { +static const uint32_t am335xgpio_gpio_chip_hw_addr[AM335XGPIO_NUM_GPIO_CHIPS] = { AM335XGPIO_GPIO0_HW_ADDR, AM335XGPIO_GPIO1_HW_ADDR, AM335XGPIO_GPIO2_HW_ADDR, @@ -71,117 +72,150 @@ static const uint32_t am335xgpio_gpio_port_hw_addr[AM335XGPIO_NUM_GPIO_PORTS] = }; /* Memory-mapped address pointers */ -static volatile uint32_t *am335xgpio_gpio_port_mmap_addr[AM335XGPIO_NUM_GPIO_PORTS]; +static volatile uint32_t *am335xgpio_gpio_chip_mmap_addr[AM335XGPIO_NUM_GPIO_CHIPS]; static int dev_mem_fd; - -/* GPIO numbers for each signal. Negative values are invalid */ -static int tck_gpio = -1; -static enum amx335gpio_gpio_mode tck_gpio_mode; -static int tms_gpio = -1; -static enum amx335gpio_gpio_mode tms_gpio_mode; -static int tdi_gpio = -1; -static enum amx335gpio_gpio_mode tdi_gpio_mode; -static int tdo_gpio = -1; -static enum amx335gpio_gpio_mode tdo_gpio_mode; -static int trst_gpio = -1; -static enum amx335gpio_gpio_mode trst_gpio_mode; -static int srst_gpio = -1; -static enum amx335gpio_gpio_mode srst_gpio_mode; -static int swclk_gpio = -1; -static enum amx335gpio_gpio_mode swclk_gpio_mode; -static int swdio_gpio = -1; -static enum amx335gpio_gpio_mode swdio_gpio_mode; -static int swdio_dir_gpio = -1; -static enum amx335gpio_gpio_mode swdio_dir_gpio_mode; -static int led_gpio = -1; -static enum amx335gpio_gpio_mode led_gpio_mode = -1; - -static bool swdio_dir_is_active_high = true; /* Active state means output */ -static bool led_is_active_high = true; +static enum amx335gpio_initial_gpio_mode initial_gpio_mode[ADAPTER_GPIO_IDX_NUM]; /* Transition delay coefficients */ static int speed_coeff = 600000; static int speed_offset = 575; static unsigned int jtag_delay; -static int is_gpio_valid(int gpio_num) -{ - return gpio_num >= 0 && gpio_num < (32 * AM335XGPIO_NUM_GPIO_PORTS); -} +static const struct adapter_gpio_config *adapter_gpio_config; -static int get_gpio_value(int gpio_num) +static bool is_gpio_config_valid(const struct adapter_gpio_config *gpio_config) { - unsigned int shift = AM335XGPIO_BIT_NUM(gpio_num); - return (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_DATAIN_OFFSET) >> shift) & 1; + return gpio_config->chip_num < AM335XGPIO_NUM_GPIO_CHIPS + && gpio_config->gpio_num < AM335XGPIO_NUM_GPIO_PER_CHIP; } -static void set_gpio_value(int gpio_num, int value) +static int get_gpio_value(const struct adapter_gpio_config *gpio_config) { - if (value) - AM335XGPIO_WRITE_REG(gpio_num, AM335XGPIO_GPIO_SETDATAOUT_OFFSET, AM335XGPIO_BIT_MASK(gpio_num)); - else - AM335XGPIO_WRITE_REG(gpio_num, AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET, AM335XGPIO_BIT_MASK(gpio_num)); + unsigned int shift = gpio_config->gpio_num; + uint32_t value = AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_DATAIN_OFFSET); + value = (value >> shift) & 1; + return value ^ (gpio_config->active_low ? 1 : 0); } -static enum amx335gpio_gpio_mode get_gpio_mode(int gpio_num) +static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int value) { - if (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_OE_OFFSET) & AM335XGPIO_BIT_MASK(gpio_num)) { - return AM335XGPIO_GPIO_MODE_INPUT; - } else { - /* Return output level too so that pin mode can be fully restored */ - if (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_DATAOUT_OFFSET) & AM335XGPIO_BIT_MASK(gpio_num)) - return AM335XGPIO_GPIO_MODE_OUTPUT_HIGH; + value = value ^ (gpio_config->active_low ? 1 : 0); + switch (gpio_config->drive) { + case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL: + if (value) + AM335XGPIO_SET_HIGH(gpio_config); else - return AM335XGPIO_GPIO_MODE_OUTPUT_LOW; + AM335XGPIO_SET_LOW(gpio_config); + /* For performance reasons assume the GPIO is already set as an output + * and therefore the call can be omitted here. + */ + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN: + if (value) { + AM335XGPIO_SET_INPUT(gpio_config); + } else { + AM335XGPIO_SET_LOW(gpio_config); + AM335XGPIO_SET_OUTPUT(gpio_config); + } + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE: + if (value) { + AM335XGPIO_SET_HIGH(gpio_config); + AM335XGPIO_SET_OUTPUT(gpio_config); + } else { + AM335XGPIO_SET_INPUT(gpio_config); + } + break; } } -static void set_gpio_mode(int gpio_num, enum amx335gpio_gpio_mode gpio_mode) +static enum amx335gpio_initial_gpio_mode get_gpio_mode(const struct adapter_gpio_config *gpio_config) { - if (gpio_mode == AM335XGPIO_GPIO_MODE_INPUT) { - AM335XGPIO_SET_REG_BITS(gpio_num, AM335XGPIO_GPIO_OE_OFFSET, AM335XGPIO_BIT_MASK(gpio_num)); - return; - } - - if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_LOW) - set_gpio_value(gpio_num, 0); - if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_HIGH) - set_gpio_value(gpio_num, 1); + if (AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_OE_OFFSET) & BIT(gpio_config->gpio_num)) + return AM335XGPIO_GPIO_MODE_INPUT; - if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT || - gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_LOW || - gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_HIGH) { - AM335XGPIO_CLEAR_REG_BITS(gpio_num, AM335XGPIO_GPIO_OE_OFFSET, AM335XGPIO_BIT_MASK(gpio_num)); - } + /* Return output level too so that pin mode can be fully restored */ + if (AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_DATAOUT_OFFSET) & BIT(gpio_config->gpio_num)) + return AM335XGPIO_GPIO_MODE_OUTPUT_HIGH; + return AM335XGPIO_GPIO_MODE_OUTPUT_LOW; } -static const char *get_gpio_mode_name(enum amx335gpio_gpio_mode gpio_mode) +static const char *get_gpio_mode_name(enum amx335gpio_initial_gpio_mode gpio_mode) { switch (gpio_mode) { case AM335XGPIO_GPIO_MODE_INPUT: return "input"; - case AM335XGPIO_GPIO_MODE_OUTPUT: - return "output"; case AM335XGPIO_GPIO_MODE_OUTPUT_LOW: return "output (low)"; case AM335XGPIO_GPIO_MODE_OUTPUT_HIGH: return "output (high)"; - default: - return "unknown"; + } + return "unknown"; +} + +static void initialize_gpio(enum adapter_gpio_config_index idx) +{ + if (!is_gpio_config_valid(&adapter_gpio_config[idx])) + return; + + initial_gpio_mode[idx] = get_gpio_mode(&adapter_gpio_config[idx]); + LOG_DEBUG("saved GPIO mode for %s (GPIO %d %d): %s", + adapter_gpio_get_name(idx), adapter_gpio_config[idx].chip_num, adapter_gpio_config[idx].gpio_num, + get_gpio_mode_name(initial_gpio_mode[idx])); + + if (adapter_gpio_config[idx].pull != ADAPTER_GPIO_PULL_NONE) { + LOG_WARNING("am335xgpio does not support pull-up or pull-down settings (signal %s)", + adapter_gpio_get_name(idx)); + } + + switch (adapter_gpio_config[idx].init_state) { + case ADAPTER_GPIO_INIT_STATE_INACTIVE: + set_gpio_value(&adapter_gpio_config[idx], 0); + break; + case ADAPTER_GPIO_INIT_STATE_ACTIVE: + set_gpio_value(&adapter_gpio_config[idx], 1); + break; + case ADAPTER_GPIO_INIT_STATE_INPUT: + AM335XGPIO_SET_INPUT(&adapter_gpio_config[idx]); + break; + } + + /* Direction for non push-pull is already set by set_gpio_value() */ + if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL + && adapter_gpio_config[idx].init_state != ADAPTER_GPIO_INIT_STATE_INPUT) + AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]); +} + +static void restore_gpio(enum adapter_gpio_config_index idx) +{ + if (is_gpio_config_valid(&adapter_gpio_config[idx])) { + switch (initial_gpio_mode[idx]) { + case AM335XGPIO_GPIO_MODE_INPUT: + AM335XGPIO_SET_INPUT(&adapter_gpio_config[idx]); + break; + case AM335XGPIO_GPIO_MODE_OUTPUT_LOW: + AM335XGPIO_SET_LOW(&adapter_gpio_config[idx]); + AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]); + break; + case AM335XGPIO_GPIO_MODE_OUTPUT_HIGH: + AM335XGPIO_SET_HIGH(&adapter_gpio_config[idx]); + AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]); + break; + } } } -static bb_value_t am335xgpio_read(void) +static enum bb_value am335xgpio_read(void) { - return get_gpio_value(tdo_gpio) ? BB_HIGH : BB_LOW; + return get_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDO]) ? BB_HIGH : BB_LOW; } static int am335xgpio_write(int tck, int tms, int tdi) { - set_gpio_value(tdi_gpio, tdi); - set_gpio_value(tms_gpio, tms); - set_gpio_value(tck_gpio, tck); /* Write clock last */ + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDI], tdi); + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TMS], tms); + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TCK], tck); /* Write clock last */ for (unsigned int i = 0; i < jtag_delay; ++i) asm volatile (""); @@ -191,8 +225,8 @@ static int am335xgpio_write(int tck, int tms, int tdi) static int am335xgpio_swd_write(int swclk, int swdio) { - set_gpio_value(swdio_gpio, swdio); - set_gpio_value(swclk_gpio, swclk); /* Write clock last */ + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO], swdio); + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK], swclk); /* Write clock last */ for (unsigned int i = 0; i < jtag_delay; ++i) asm volatile (""); @@ -203,54 +237,53 @@ static int am335xgpio_swd_write(int swclk, int swdio) /* (1) assert or (0) deassert reset lines */ static int am335xgpio_reset(int trst, int srst) { - /* assume active low */ - if (is_gpio_valid(srst_gpio)) { - if (jtag_get_reset_config() & RESET_SRST_PUSH_PULL) - set_gpio_mode(srst_gpio, srst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH); - else - set_gpio_mode(srst_gpio, srst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_INPUT); - } - - /* assume active low */ - if (is_gpio_valid(trst_gpio)) { - if (jtag_get_reset_config() & RESET_TRST_OPEN_DRAIN) - set_gpio_mode(trst_gpio, trst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_INPUT); - else - set_gpio_mode(trst_gpio, trst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH); - } - - LOG_DEBUG("am335xgpio_reset(%d, %d), trst_gpio: %d (%s), srst_gpio: %d (%s)", - trst, srst, - trst_gpio, get_gpio_mode_name(get_gpio_mode(trst_gpio)), - srst_gpio, get_gpio_mode_name(get_gpio_mode(srst_gpio))); + /* As the "adapter reset_config" command keeps the srst and trst gpio drive + * mode settings in sync we can use our standard set_gpio_value() function + * that honours drive mode and active low. + */ + if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST])) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST], srst); + + if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST])) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST], trst); + + LOG_DEBUG("trst %d gpio: %d %d, srst %d gpio: %d %d", + trst, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].chip_num, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].gpio_num, + srst, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].chip_num, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].gpio_num); return ERROR_OK; } static void am335xgpio_swdio_drive(bool is_output) { if (is_output) { - set_gpio_value(swdio_dir_gpio, swdio_dir_is_active_high ? 1 : 0); - set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_OUTPUT); + if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR])) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 1); + AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]); } else { - set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_INPUT); - set_gpio_value(swdio_dir_gpio, swdio_dir_is_active_high ? 0 : 1); + AM335XGPIO_SET_INPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]); + if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR])) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0); } } static int am335xgpio_swdio_read(void) { - return get_gpio_value(swdio_gpio); + return get_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]); } -static int am335xgpio_blink(int on) +static int am335xgpio_blink(bool on) { - if (is_gpio_valid(led_gpio)) - set_gpio_value(led_gpio, (!on ^ led_is_active_high) ? 1 : 0); + if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED])) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED], on ? 1 : 0); return ERROR_OK; } -static struct bitbang_interface am335xgpio_bitbang = { +static const struct bitbang_interface am335xgpio_bitbang = { .read = am335xgpio_read, .write = am335xgpio_write, .swdio_read = am335xgpio_swdio_read, @@ -283,144 +316,6 @@ static int am335xgpio_speed(int speed) return ERROR_OK; } -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionums) -{ - if (CMD_ARGC == 4) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(CMD, "AM335x GPIO config: tck = %d, tms = %d, tdi = %d, tdo = %d", - tck_gpio, tms_gpio, tdi_gpio, tdo_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tck) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio); - - command_print(CMD, "AM335x GPIO config: tck = %d", tck_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tms) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio); - - command_print(CMD, "AM335x GPIO config: tms = %d", tms_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdo) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio); - - command_print(CMD, "AM335x GPIO config: tdo = %d", tdo_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdi) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio); - - command_print(CMD, "AM335x GPIO config: tdi = %d", tdi_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_srst) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio); - - command_print(CMD, "AM335x GPIO config: srst = %d", srst_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_trst) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio); - - command_print(CMD, "AM335x GPIO config: trst = %d", trst_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_swd_gpionums) -{ - if (CMD_ARGC == 2) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(CMD, "AM335x GPIO config: swclk = %d, swdio = %d", swclk_gpio, swdio_gpio); - - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swclk) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio); - - command_print(CMD, "AM335x GPIO config: swclk = %d", swclk_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swdio) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio); - - command_print(CMD, "AM335x GPIO config: swdio = %d", swdio_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swdio_dir) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_dir_gpio); - - command_print(CMD, "AM335x GPIO config: swdio_dir = %d", swdio_dir_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_swd_dir_output_state) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_BOOL(CMD_ARGV[0], swdio_dir_is_active_high, "high", "low"); - - command_print(CMD, "AM335x GPIO config: swdio_dir_output_state = %s", swdio_dir_is_active_high ? "high" : "low"); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_gpionum_led) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], led_gpio); - - command_print(CMD, "AM335x GPIO config: led = %d", led_gpio); - return ERROR_OK; -} - -COMMAND_HANDLER(am335xgpio_handle_led_on_state) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_BOOL(CMD_ARGV[0], led_is_active_high, "high", "low"); - - command_print(CMD, "AM335x GPIO config: led_on_state = %s", led_is_active_high ? "high" : "low"); - return ERROR_OK; -} - COMMAND_HANDLER(am335xgpio_handle_speed_coeffs) { if (CMD_ARGC == 2) { @@ -434,104 +329,6 @@ COMMAND_HANDLER(am335xgpio_handle_speed_coeffs) } static const struct command_registration am335xgpio_subcommand_handlers[] = { - { - .name = "jtag_nums", - .handler = am335xgpio_handle_jtag_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for tck, tms, tdi, tdo (in that order).", - .usage = "[tck tms tdi tdo]", - }, - { - .name = "tck_num", - .handler = am335xgpio_handle_jtag_gpionum_tck, - .mode = COMMAND_CONFIG, - .help = "gpio number for tck.", - .usage = "[tck]", - }, - { - .name = "tms_num", - .handler = am335xgpio_handle_jtag_gpionum_tms, - .mode = COMMAND_CONFIG, - .help = "gpio number for tms.", - .usage = "[tms]", - }, - { - .name = "tdo_num", - .handler = am335xgpio_handle_jtag_gpionum_tdo, - .mode = COMMAND_CONFIG, - .help = "gpio number for tdo.", - .usage = "[tdo]", - }, - { - .name = "tdi_num", - .handler = am335xgpio_handle_jtag_gpionum_tdi, - .mode = COMMAND_CONFIG, - .help = "gpio number for tdi.", - .usage = "[tdi]", - }, - { - .name = "swd_nums", - .handler = am335xgpio_handle_swd_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for swclk, swdio (in that order).", - .usage = "[swclk swdio]", - }, - { - .name = "swclk_num", - .handler = am335xgpio_handle_swd_gpionum_swclk, - .mode = COMMAND_CONFIG, - .help = "gpio number for swclk.", - .usage = "[swclk]", - }, - { - .name = "swdio_num", - .handler = am335xgpio_handle_swd_gpionum_swdio, - .mode = COMMAND_CONFIG, - .help = "gpio number for swdio.", - .usage = "[swdio]", - }, - { - .name = "swdio_dir_num", - .handler = am335xgpio_handle_swd_gpionum_swdio_dir, - .mode = COMMAND_CONFIG, - .help = "gpio number for swdio direction control pin.", - .usage = "[swdio_dir]", - }, - { - .name = "swdio_dir_output_state", - .handler = am335xgpio_handle_swd_dir_output_state, - .mode = COMMAND_CONFIG, - .help = "required state for swdio_dir pin to select SWDIO buffer to be output.", - .usage = "['off'|'on']", - }, - { - .name = "srst_num", - .handler = am335xgpio_handle_jtag_gpionum_srst, - .mode = COMMAND_CONFIG, - .help = "gpio number for srst.", - .usage = "[srst]", - }, - { - .name = "trst_num", - .handler = am335xgpio_handle_jtag_gpionum_trst, - .mode = COMMAND_CONFIG, - .help = "gpio number for trst.", - .usage = "[trst]", - }, - { - .name = "led_num", - .handler = am335xgpio_handle_gpionum_led, - .mode = COMMAND_CONFIG, - .help = "gpio number for led.", - .usage = "[led]", - }, - { - .name = "led_on_state", - .handler = am335xgpio_handle_led_on_state, - .mode = COMMAND_CONFIG, - .help = "required state for led pin to turn on LED.", - .usage = "['off'|'on']", - }, { .name = "speed_coeffs", .handler = am335xgpio_handle_speed_coeffs, @@ -553,8 +350,6 @@ static const struct command_registration am335xgpio_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static const char * const am335xgpio_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface am335xgpio_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = bitbang_execute_queue, @@ -562,32 +357,40 @@ static struct jtag_interface am335xgpio_interface = { static bool am335xgpio_jtag_mode_possible(void) { - if (!is_gpio_valid(tck_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TCK])) return false; - if (!is_gpio_valid(tms_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TMS])) return false; - if (!is_gpio_valid(tdi_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDI])) return false; - if (!is_gpio_valid(tdo_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDO])) return false; return true; } static bool am335xgpio_swd_mode_possible(void) { - if (!is_gpio_valid(swclk_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK])) return false; - if (!is_gpio_valid(swdio_gpio)) + if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO])) return false; return true; } -static int am335xgpio_init(void) +static void am335xgpio_munmap(void) { - bitbang_interface = &am335xgpio_bitbang; + for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_CHIPS && am335xgpio_gpio_chip_mmap_addr[i] != MAP_FAILED; ++i) + if (munmap((void *)am335xgpio_gpio_chip_mmap_addr[i], sysconf(_SC_PAGE_SIZE)) < 0) + LOG_ERROR("Cannot unmap GPIO memory for chip %d: %s", i, strerror(errno)); +} +static int am335xgpio_init(void) +{ LOG_INFO("AM335x GPIO JTAG/SWD bitbang driver"); + bitbang_interface = &am335xgpio_bitbang; + adapter_gpio_config = adapter_gpio_get_config(); + if (transport_is_jtag() && !am335xgpio_jtag_mode_possible()) { LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode"); return ERROR_JTAG_INIT_FAILED; @@ -608,106 +411,89 @@ static int am335xgpio_init(void) return ERROR_JTAG_INIT_FAILED; } - for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_PORTS; ++i) { - am335xgpio_gpio_port_mmap_addr[i] = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE, - MAP_SHARED, dev_mem_fd, am335xgpio_gpio_port_hw_addr[i]); + for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_CHIPS; ++i) { + am335xgpio_gpio_chip_mmap_addr[i] = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE, + MAP_SHARED, dev_mem_fd, am335xgpio_gpio_chip_hw_addr[i]); - if (am335xgpio_gpio_port_mmap_addr[i] == MAP_FAILED) { + if (am335xgpio_gpio_chip_mmap_addr[i] == MAP_FAILED) { LOG_ERROR("mmap: %s", strerror(errno)); + am335xgpio_munmap(); close(dev_mem_fd); return ERROR_JTAG_INIT_FAILED; } } + close(dev_mem_fd); - /* - * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST as outputs. - * Drive TDI and TCK low, and TMS high. + /* Configure JTAG/SWD signals. Default directions and initial states are handled + * by adapter.c and "adapter gpio" command. */ if (transport_is_jtag()) { - tdo_gpio_mode = get_gpio_mode(tdo_gpio); - tdi_gpio_mode = get_gpio_mode(tdi_gpio); - tck_gpio_mode = get_gpio_mode(tck_gpio); - tms_gpio_mode = get_gpio_mode(tms_gpio); - LOG_DEBUG("saved GPIO mode for tdo (GPIO #%d): %s", tdo_gpio, get_gpio_mode_name(tdo_gpio_mode)); - LOG_DEBUG("saved GPIO mode for tdi (GPIO #%d): %s", tdi_gpio, get_gpio_mode_name(tdi_gpio_mode)); - LOG_DEBUG("saved GPIO mode for tck (GPIO #%d): %s", tck_gpio, get_gpio_mode_name(tck_gpio_mode)); - LOG_DEBUG("saved GPIO mode for tms (GPIO #%d): %s", tms_gpio, get_gpio_mode_name(tms_gpio_mode)); - - set_gpio_mode(tdo_gpio, AM335XGPIO_GPIO_MODE_INPUT); - set_gpio_mode(tdi_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW); - set_gpio_mode(tms_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_HIGH); - set_gpio_mode(tck_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW); - - if (is_gpio_valid(trst_gpio)) { - trst_gpio_mode = get_gpio_mode(trst_gpio); - LOG_DEBUG("saved GPIO mode for trst (GPIO #%d): %s", trst_gpio, get_gpio_mode_name(trst_gpio_mode)); - } + initialize_gpio(ADAPTER_GPIO_IDX_TDO); + initialize_gpio(ADAPTER_GPIO_IDX_TDI); + initialize_gpio(ADAPTER_GPIO_IDX_TMS); + initialize_gpio(ADAPTER_GPIO_IDX_TCK); + initialize_gpio(ADAPTER_GPIO_IDX_TRST); } if (transport_is_swd()) { - swclk_gpio_mode = get_gpio_mode(swclk_gpio); - swdio_gpio_mode = get_gpio_mode(swdio_gpio); - LOG_DEBUG("saved GPIO mode for swclk (GPIO #%d): %s", swclk_gpio, get_gpio_mode_name(swclk_gpio_mode)); - LOG_DEBUG("saved GPIO mode for swdio (GPIO #%d): %s", swdio_gpio, get_gpio_mode_name(swdio_gpio_mode)); - if (is_gpio_valid(swdio_dir_gpio)) { - swdio_dir_gpio_mode = get_gpio_mode(swdio_dir_gpio); - LOG_DEBUG("saved GPIO mode for swdio_dir (GPIO #%d): %s", - swdio_dir_gpio, get_gpio_mode_name(swdio_dir_gpio_mode)); - set_gpio_mode(swdio_dir_gpio, - swdio_dir_is_active_high ? AM335XGPIO_GPIO_MODE_OUTPUT_HIGH : AM335XGPIO_GPIO_MODE_OUTPUT_LOW); - + /* swdio and its buffer should be initialized in the order that prevents + * two outputs from being connected together. This will occur if the + * swdio GPIO of the AM335x is configured as an output while its + * external buffer is configured to send the swdio signal from the + * target to the AM335x. + */ + if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) { + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO); + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + } else { + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO); } - set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW); - set_gpio_mode(swclk_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW); - } - if (is_gpio_valid(srst_gpio)) { - srst_gpio_mode = get_gpio_mode(srst_gpio); - LOG_DEBUG("saved GPIO mode for srst (GPIO #%d): %s", srst_gpio, get_gpio_mode_name(srst_gpio_mode)); + initialize_gpio(ADAPTER_GPIO_IDX_SWCLK); } - if (is_gpio_valid(led_gpio)) { - led_gpio_mode = get_gpio_mode(led_gpio); - LOG_DEBUG("saved GPIO mode for led (GPIO #%d): %s", led_gpio, get_gpio_mode_name(led_gpio_mode)); - set_gpio_mode(led_gpio, - led_is_active_high ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH); - } + initialize_gpio(ADAPTER_GPIO_IDX_SRST); + initialize_gpio(ADAPTER_GPIO_IDX_LED); - /* Set GPIO modes for TRST and SRST and make both inactive */ - am335xgpio_reset(0, 0); return ERROR_OK; } static int am335xgpio_quit(void) { if (transport_is_jtag()) { - set_gpio_mode(tdo_gpio, tdo_gpio_mode); - set_gpio_mode(tdi_gpio, tdi_gpio_mode); - set_gpio_mode(tck_gpio, tck_gpio_mode); - set_gpio_mode(tms_gpio, tms_gpio_mode); - if (is_gpio_valid(trst_gpio)) - set_gpio_mode(trst_gpio, trst_gpio_mode); + restore_gpio(ADAPTER_GPIO_IDX_TDO); + restore_gpio(ADAPTER_GPIO_IDX_TDI); + restore_gpio(ADAPTER_GPIO_IDX_TMS); + restore_gpio(ADAPTER_GPIO_IDX_TCK); + restore_gpio(ADAPTER_GPIO_IDX_TRST); } if (transport_is_swd()) { - set_gpio_mode(swclk_gpio, swclk_gpio_mode); - set_gpio_mode(swdio_gpio, swdio_gpio_mode); - if (is_gpio_valid(swdio_dir_gpio)) - set_gpio_mode(swdio_dir_gpio, swdio_dir_gpio_mode); + /* Restore swdio/swdio_dir to their initial modes, even if that means + * connecting two outputs. Begin by making swdio an input so that the + * current and final states of swdio and swdio_dir do not have to be + * considered to calculate the safe restoration order. + */ + AM335XGPIO_SET_INPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]); + restore_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + restore_gpio(ADAPTER_GPIO_IDX_SWDIO); + + restore_gpio(ADAPTER_GPIO_IDX_SWCLK); } - if (is_gpio_valid(srst_gpio)) - set_gpio_mode(srst_gpio, srst_gpio_mode); + restore_gpio(ADAPTER_GPIO_IDX_SRST); + restore_gpio(ADAPTER_GPIO_IDX_LED); - if (is_gpio_valid(led_gpio)) - set_gpio_mode(led_gpio, led_gpio_mode); + am335xgpio_munmap(); return ERROR_OK; } struct adapter_driver am335xgpio_adapter_driver = { .name = "am335xgpio", - .transports = am335xgpio_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = am335xgpio_command_handlers, .init = am335xgpio_init, diff --git a/src/jtag/drivers/amt_jtagaccel.c b/src/jtag/drivers/amt_jtagaccel.c index 01db6e4ca2..d3f8bb61eb 100644 --- a/src/jtag/drivers/amt_jtagaccel.c +++ b/src/jtag/drivers/amt_jtagaccel.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -146,7 +146,7 @@ static int amt_jtagaccel_speed(int speed) return ERROR_OK; } -static void amt_jtagaccel_end_state(tap_state_t state) +static void amt_jtagaccel_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -179,8 +179,8 @@ static void amt_jtagaccel_state_move(void) uint8_t aw_scan_tms_5; uint8_t tms_scan[2]; - tap_state_t cur_state = tap_get_state(); - tap_state_t end_state = tap_get_end_state(); + enum tap_state cur_state = tap_get_state(); + enum tap_state end_state = tap_get_end_state(); tms_scan[0] = amt_jtagaccel_tap_move[tap_move_ndx(cur_state)][tap_move_ndx(end_state)][0]; tms_scan[1] = amt_jtagaccel_tap_move[tap_move_ndx(cur_state)][tap_move_ndx(end_state)][1]; @@ -203,13 +203,13 @@ static void amt_jtagaccel_state_move(void) tap_set_state(end_state); } -static void amt_jtagaccel_runtest(int num_cycles) +static void amt_jtagaccel_runtest(unsigned int num_cycles) { int i = 0; uint8_t aw_scan_tms_5; uint8_t aw_scan_tms_1to4; - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -237,7 +237,7 @@ static void amt_jtagaccel_scan(bool ir_scan, enum scan_type type, uint8_t *buffe { int bits_left = scan_size; int bit_count = 0; - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); uint8_t aw_tdi_option; uint8_t dw_tdi_scan; uint8_t dr_tdo; @@ -317,9 +317,9 @@ static void amt_jtagaccel_scan(bool ir_scan, enum scan_type type, uint8_t *buffe tap_set_state(tap_get_end_state()); } -static int amt_jtagaccel_execute_queue(void) +static int amt_jtagaccel_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -419,6 +419,8 @@ static int amt_jtagaccel_init(void) #endif uint8_t ar_status; + LOG_WARNING("This adapter is deprecated and support will be removed in the next release!"); + #if PARPORT_USE_PPDEV == 1 if (device_handle > 0) { LOG_ERROR("device is already opened"); @@ -579,7 +581,8 @@ static struct jtag_interface amt_jtagaccel_interface = { struct adapter_driver amt_jtagaccel_adapter_driver = { .name = "amt_jtagaccel", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = amtjtagaccel_command_handlers, .init = amt_jtagaccel_init, diff --git a/src/jtag/drivers/angie.c b/src/jtag/drivers/angie.c new file mode 100644 index 0000000000..56a118eaed --- /dev/null +++ b/src/jtag/drivers/angie.c @@ -0,0 +1,2402 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*************************************************************************** + File : angie.c * + Contents : OpenOCD driver code for NanoXplore USB-JTAG ANGIE * + adapter hardware. * + Based on openULINK driver code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + <aboudjelida@nanoxplore.com> * + <ahmederrachedbjld@gmail.com> * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stdio.h> +#include <stdlib.h> +#include <math.h> +#include "helper/system.h" +#include <helper/types.h> +#include <jtag/interface.h> +#include <jtag/commands.h> +#include <target/image.h> +#include <libusb.h> +#include "libusb_helper.h" +#include "angie/include/msgtypes.h" + +/** USB Vendor ID of ANGIE device in unconfigured state (no firmware loaded + * yet) or with its firmware. */ +#define ANGIE_VID 0x584e + +/** USB Product ID of ANGIE device in unconfigured state (no firmware loaded + * yet) or with its firmware. */ +#define ANGIE_PID 0x414F +#define ANGIE_PID_2 0x424e +#define ANGIE_PID_3 0x4255 +#define ANGIE_PID_4 0x4355 +#define ANGIE_PID_5 0x4a55 + +/** Address of EZ-USB ANGIE CPU Control & Status register. This register can be + * written by issuing a Control EP0 vendor request. */ +#define CPUCS_REG 0xE600 + +/** USB Control EP0 bRequest: "Firmware Load". */ +#define REQUEST_FIRMWARE_LOAD 0xA0 + +/** Value to write into CPUCS to put EZ-USB ANGIE into reset. */ +#define CPU_RESET 0x01 + +/** Value to write into CPUCS to put EZ-USB ANGIE out of reset. */ +#define CPU_START 0x00 + +/** Base address of firmware in EZ-USB ANGIE code space. */ +#define FIRMWARE_ADDR 0x0000 + +/** USB interface number */ +#define USB_INTERFACE 0 + +/** Delay (in microseconds) to wait while EZ-USB performs ReNumeration. */ +#define ANGIE_RENUMERATION_DELAY_US 1500000 + +/** Default location of ANGIE firmware image. */ +#define ANGIE_FIRMWARE_FILE PKGDATADIR "/angie/angie_firmware.bin" + +/** Default location of ANGIE firmware image. */ +#define ANGIE_BITSTREAM_FILE PKGDATADIR "/angie/angie_bitstream.bit" + +/** Maximum size of a single firmware section. Entire EZ-USB ANGIE code space = 16kB */ +#define SECTION_BUFFERSIZE 16384 + +/** Tuning of OpenOCD SCAN commands split into multiple ANGIE commands. */ +#define SPLIT_SCAN_THRESHOLD 10 + +/** ANGIE hardware type */ +enum angie_type { + ANGIE, +}; + +enum angie_payload_direction { + PAYLOAD_DIRECTION_OUT, + PAYLOAD_DIRECTION_IN +}; + +enum angie_delay_type { + DELAY_CLOCK_TCK, + DELAY_CLOCK_TMS, + DELAY_SCAN_IN, + DELAY_SCAN_OUT, + DELAY_SCAN_IO +}; + +/** + * ANGIE command (ANGIE command queue element). + * + * For the OUT direction payload, things are quite easy: Payload is stored + * in a rather small array (up to 63 bytes), the payload is always allocated + * by the function generating the command and freed by angie_clear_queue(). + * + * For the IN direction payload, things get a little bit more complicated: + * The maximum IN payload size for a single command is 64 bytes. Assume that + * a single OpenOCD command needs to scan 256 bytes. This results in the + * generation of four ANGIE commands. The function generating these + * commands shall allocate an uint8_t[256] array. Each command's #payload_in + * pointer shall point to the corresponding offset where IN data shall be + * placed, while #payload_in_start shall point to the first element of the 256 + * byte array. + * - first command: #payload_in_start + 0 + * - second command: #payload_in_start + 64 + * - third command: #payload_in_start + 128 + * - fourth command: #payload_in_start + 192 + * + * The last command sets #needs_postprocessing to true. + */ +struct angie_cmd { + uint8_t id; /**< ANGIE command ID */ + + uint8_t *payload_out; /**< Pointer where OUT payload shall be stored */ + uint8_t payload_out_size; /**< OUT direction payload size for this command */ + + uint8_t *payload_in_start; /**< Pointer to first element of IN payload array */ + uint8_t *payload_in; /**< Pointer where IN payload shall be stored */ + uint8_t payload_in_size; /**< IN direction payload size for this command */ + + /** Indicates if this command needs post-processing */ + bool needs_postprocessing; + + /** Indicates if angie_clear_queue() should free payload_in_start */ + bool free_payload_in_start; + + /** Pointer to corresponding OpenOCD command for post-processing */ + struct jtag_command *cmd_origin; + + struct angie_cmd *next; /**< Pointer to next command (linked list) */ +}; + +/** Describes one driver instance */ +struct angie { + struct libusb_context *libusb_ctx; + struct libusb_device_handle *usb_device_handle; + enum angie_type type; + + unsigned int ep_in; /**< IN endpoint number */ + unsigned int ep_out; /**< OUT endpoint number */ + + /* delay value for "SLOW_CLOCK commands" in [0:255] range in units of 4 us; + -1 means no need for delay */ + int delay_scan_in; /**< Delay value for SCAN_IN commands */ + int delay_scan_out; /**< Delay value for SCAN_OUT commands */ + int delay_scan_io; /**< Delay value for SCAN_IO commands */ + int delay_clock_tck; /**< Delay value for CLOCK_TMS commands */ + int delay_clock_tms; /**< Delay value for CLOCK_TCK commands */ + + int commands_in_queue; /**< Number of commands in queue */ + struct angie_cmd *queue_start; /**< Pointer to first command in queue */ + struct angie_cmd *queue_end; /**< Pointer to last command in queue */ +}; + +/**************************** Function Prototypes *****************************/ + +/* USB helper functions */ +static int angie_usb_open(struct angie *device); +static int angie_usb_close(struct angie *device); + +/* ANGIE MCU (Cypress EZ-USB) specific functions */ +static int angie_cpu_reset(struct angie *device, char reset_bit); +static int angie_load_firmware_and_renumerate(struct angie *device, const char *filename, + uint32_t delay_us); +static int angie_load_firmware(struct angie *device, const char *filename); +static int angie_load_bitstream(struct angie *device, const char *filename); +static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_data_size); +static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value); +static int angie_write_firmware_section(struct angie *device, + struct image *firmware_image, int section_index); + +/* Generic helper functions */ +static void angie_dump_signal_states(uint8_t input_signals, uint8_t output_signals); + +/* ANGIE command generation helper functions */ +static int angie_allocate_payload(struct angie_cmd *angie_cmd, int size, + enum angie_payload_direction direction); + +/* ANGIE command queue helper functions */ +static int angie_get_queue_size(struct angie *device, + enum angie_payload_direction direction); +static void angie_clear_queue(struct angie *device); +static int angie_append_queue(struct angie *device, struct angie_cmd *angie_cmd); +static int angie_execute_queued_commands(struct angie *device, int timeout_ms); + +static void angie_dump_queue(struct angie *device); + +static int angie_append_scan_cmd(struct angie *device, + enum scan_type scan_type, + int scan_size_bits, + uint8_t *tdi, + uint8_t *tdo_start, + uint8_t *tdo, + uint8_t tms_count_start, + uint8_t tms_sequence_start, + uint8_t tms_count_end, + uint8_t tms_sequence_end, + struct jtag_command *origin, + bool postprocess); +static int angie_append_clock_tms_cmd(struct angie *device, uint8_t count, + uint8_t sequence); +static int angie_append_clock_tck_cmd(struct angie *device, uint16_t count); +static int angie_append_get_signals_cmd(struct angie *device); +static int angie_append_set_signals_cmd(struct angie *device, uint8_t low, + uint8_t high); +static int angie_append_sleep_cmd(struct angie *device, uint32_t us); +static int angie_append_configure_tck_cmd(struct angie *device, + int delay_scan_in, + int delay_scan_out, + int delay_scan_io, + int delay_tck, + int delay_tms); +static int angie_append_test_cmd(struct angie *device); + +/* ANGIE TCK frequency helper functions */ +static int angie_calculate_delay(enum angie_delay_type type, long f, int *delay); + +/* Interface between ANGIE and OpenOCD */ +static void angie_set_end_state(enum tap_state endstate); +static int angie_queue_statemove(struct angie *device); + +static int angie_queue_scan(struct angie *device, struct jtag_command *cmd); +static int angie_queue_tlr_reset(struct angie *device, struct jtag_command *cmd); +static int angie_queue_runtest(struct angie *device, struct jtag_command *cmd); +static int angie_queue_pathmove(struct angie *device, struct jtag_command *cmd); +static int angie_queue_sleep(struct angie *device, struct jtag_command *cmd); +static int angie_queue_stableclocks(struct angie *device, struct jtag_command *cmd); + +static int angie_post_process_scan(struct angie_cmd *angie_cmd); +static int angie_post_process_queue(struct angie *device); + +/* adapter driver functions */ +static int angie_execute_queue(struct jtag_command *cmd_queue); +static int angie_khz(int khz, int *jtag_speed); +static int angie_speed(int speed); +static int angie_speed_div(int speed, int *khz); +static int angie_init(void); +static int angie_quit(void); +static int angie_reset(int trst, int srst); + +/****************************** Global Variables ******************************/ + +static struct angie *angie_handle; + +/**************************** USB helper functions ****************************/ + +/** + * Opens the ANGIE device + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_usb_open(struct angie *device) +{ + struct libusb_device_handle *usb_device_handle; + const uint16_t vids[] = {ANGIE_VID, ANGIE_VID, ANGIE_VID, ANGIE_VID, ANGIE_VID, 0}; + const uint16_t pids[] = {ANGIE_PID, ANGIE_PID_2, ANGIE_PID_3, ANGIE_PID_4, ANGIE_PID_5, 0}; + + int ret = jtag_libusb_open(vids, pids, NULL, &usb_device_handle, NULL); + + if (ret != ERROR_OK) { + LOG_ERROR("Could not find and open ANGIE"); + return ret; + } + + device->usb_device_handle = usb_device_handle; + device->type = ANGIE; + + return ERROR_OK; +} + +/** + * Releases the ANGIE interface and closes the USB device handle. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_usb_close(struct angie *device) +{ + if (device->usb_device_handle) { + if (libusb_release_interface(device->usb_device_handle, 0) != 0) { + LOG_ERROR("Could not release interface 0"); + return ERROR_FAIL; + } + + jtag_libusb_close(device->usb_device_handle); + device->usb_device_handle = NULL; + } + return ERROR_OK; +} + +/******************* ANGIE CPU (EZ-USB) specific functions ********************/ + +/** + * Writes '0' or '1' to the CPUCS register, putting the EZ-USB CPU into reset + * or out of reset. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param reset_bit 0 to put CPU into reset, 1 to put CPU out of reset. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_cpu_reset(struct angie *device, char reset_bit) +{ + return jtag_libusb_control_transfer(device->usb_device_handle, + (LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE), + REQUEST_FIRMWARE_LOAD, CPUCS_REG, 0, &reset_bit, 1, LIBUSB_TIMEOUT_MS, NULL); +} + +/** + * Puts the ANGIE's EZ-USB microcontroller into reset state, downloads + * the firmware image, resumes the microcontroller and re-enumerates + * USB devices. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * The usb_handle member will be modified during re-enumeration. + * @param filename path to the Intel HEX file containing the firmware image. + * @param delay_us the delay to wait for the device to re-enumerate. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_load_firmware_and_renumerate(struct angie *device, + const char *filename, uint32_t delay_us) +{ + int ret; + + /* Basic process: After downloading the firmware, the ANGIE will disconnect + * itself and re-connect after a short amount of time so we have to close + * the handle and re-enumerate USB devices */ + + ret = angie_load_firmware(device, filename); + if (ret != ERROR_OK) + return ret; + + ret = angie_usb_close(device); + if (ret != ERROR_OK) + return ret; + + usleep(delay_us); + + ret = angie_usb_open(device); + if (ret != ERROR_OK) + return ret; + + ret = libusb_claim_interface(angie_handle->usb_device_handle, 0); + if (ret != LIBUSB_SUCCESS) + return ERROR_FAIL; + + return ERROR_OK; +} + +/** + * Downloads a firmware image to the ANGIE's EZ-USB microcontroller + * over the USB bus. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param filename an absolute or relative path to the Intel HEX file + * containing the firmware image. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_load_firmware(struct angie *device, const char *filename) +{ + struct image angie_firmware_image; + int ret; + + ret = angie_cpu_reset(device, CPU_RESET); + if (ret != ERROR_OK) { + LOG_ERROR("Could not halt ANGIE CPU"); + return ret; + } + + angie_firmware_image.base_address = 0; + angie_firmware_image.base_address_set = false; + + ret = image_open(&angie_firmware_image, filename, "bin"); + if (ret != ERROR_OK) { + LOG_ERROR("Could not load firmware image"); + return ret; + } + + /* Download all sections in the image to ANGIE */ + for (unsigned int i = 0; i < angie_firmware_image.num_sections; i++) { + ret = angie_write_firmware_section(device, &angie_firmware_image, i); + if (ret != ERROR_OK) { + LOG_ERROR("Could not write firmware section"); + return ret; + } + } + + image_close(&angie_firmware_image); + + ret = angie_cpu_reset(device, CPU_START); + if (ret != ERROR_OK) { + LOG_ERROR("Could not restart ANGIE CPU"); + return ret; + } + + return ERROR_OK; +} + +/** + * Downloads a bitstream file to the ANGIE's FPGA through the EZ-USB microcontroller + * over the USB bus. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param filename an absolute or relative path to the Xilinx .bit file + * containing the bitstream data. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_load_bitstream(struct angie *device, const char *filename) +{ + int ret, transferred; + const char *bitstream_file_path = filename; + FILE *bitstream_file = NULL; + char *bitstream_data = NULL; + size_t bitstream_size = 0; + uint8_t gpifcnt[4]; + + /* Open the bitstream file */ + bitstream_file = fopen(bitstream_file_path, "rb"); + if (!bitstream_file) { + LOG_ERROR("Failed to open bitstream file: %s\n", bitstream_file_path); + return ERROR_FAIL; + } + + /* Get the size of the bitstream file */ + fseek(bitstream_file, 0, SEEK_END); + bitstream_size = ftell(bitstream_file); + fseek(bitstream_file, 0, SEEK_SET); + + /* Allocate memory for the bitstream data */ + bitstream_data = malloc(bitstream_size); + if (!bitstream_data) { + LOG_ERROR("Failed to allocate memory for bitstream data."); + fclose(bitstream_file); + return ERROR_FAIL; + } + + /* Read the bitstream data from the file */ + if (fread(bitstream_data, 1, bitstream_size, bitstream_file) != bitstream_size) { + LOG_ERROR("Failed to read bitstream data."); + free(bitstream_data); + fclose(bitstream_file); + return ERROR_FAIL; + } + + h_u32_to_be(gpifcnt, bitstream_size); + + /* CFGopen */ + ret = jtag_libusb_control_transfer(device->usb_device_handle, + 0x00, 0xB0, 0, 0, (char *)gpifcnt, 4, LIBUSB_TIMEOUT_MS, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Failed opencfg"); + /* Abort if libusb sent less data than requested */ + return ERROR_FAIL; + } + + /* Send the bitstream data to the microcontroller */ + int actual_length = 0; + ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x02, bitstream_data, bitstream_size, 1000, &actual_length); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to send bitstream data: %s", libusb_strerror(ret)); + free(bitstream_data); + fclose(bitstream_file); + return ERROR_FAIL; + } + + LOG_INFO("Bitstream sent successfully."); + + /* Clean up */ + free(bitstream_data); + fclose(bitstream_file); + + /* CFGclose */ + transferred = 0; + ret = jtag_libusb_control_transfer(device->usb_device_handle, + 0x00, 0xB1, 0, 0, NULL, 0, LIBUSB_TIMEOUT_MS, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Failed cfgclose"); + /* Abort if libusb sent less data than requested */ + return ERROR_FAIL; + } + return ERROR_OK; +} + +/** + * Send an i2c write operation to dev-board components. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param i2c_data table of i2c data that we want to write to slave device. + * @param i2c_data_size the size of i2c data table. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_data_size) +{ + char i2c_data_buffer[i2c_data_size + 2]; + char buffer_received[1]; + int ret, transferred; + i2c_data_buffer[0] = 0; // write = 0 + i2c_data_buffer[1] = i2c_data_size - 1; // i2c_data count (without address) + + for (uint8_t i = 0; i < i2c_data_size; i++) + i2c_data_buffer[i + 2] = i2c_data[i]; + + // Send i2c packet to Dev-board and configure its clock source / + ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x06, i2c_data_buffer, + i2c_data_size + 2, 1000, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Error in i2c clock gen configuration : ret ERROR"); + return ret; + } + if (transferred != i2c_data_size + 2) { + LOG_ERROR("Error in i2c clock gen configuration : bytes transferred"); + return ERROR_FAIL; + } + + usleep(500); + + // Receive packet from ANGIE / + ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x88, buffer_received, 1, 1000, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Error in i2c clock gen configuration : ret ERROR"); + return ret; + } + return ERROR_OK; +} + +/** + * Configure dev-board gpio extender modules by configuring their + * register 3 and register 1 responsible for IO directions and values. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param i2c_adr i2c address of the gpio extender. + * @param cfg_value IOs configuration to be written in register Number 3. + * @param value the IOs value to be written in register Number 1. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value) +{ + uint8_t ioconfig[3] = {i2c_adr, 3, cfg_value}; + int ret = angie_i2c_write(device, ioconfig, 3); + if (ret != ERROR_OK) + return ret; + + usleep(500); + return ret; +} + +/** + * Send one contiguous firmware section to the ANGIE's EZ-USB microcontroller + * over the USB bus. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param firmware_image pointer to the firmware image that contains the section + * which should be sent to the ANGIE's EZ-USB microcontroller. + * @param section_index index of the section within the firmware image. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_write_firmware_section(struct angie *device, + struct image *firmware_image, int section_index) +{ + int addr, bytes_remaining, chunk_size; + uint8_t data[SECTION_BUFFERSIZE]; + uint8_t *data_ptr = data; + uint16_t size; + size_t size_read; + int ret, transferred; + + size = (uint16_t)firmware_image->sections[section_index].size; + addr = (uint16_t)firmware_image->sections[section_index].base_address; + + LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04" PRIx16 ")", section_index, addr, + size); + + /* Copy section contents to local buffer */ + ret = image_read_section(firmware_image, section_index, 0, size, data, + &size_read); + + if (ret != ERROR_OK) + return ret; + if (size_read != size) + return ERROR_FAIL; + + bytes_remaining = size; + + /* Send section data in chunks of up to 64 bytes to ANGIE */ + while (bytes_remaining > 0) { + if (bytes_remaining > 64) + chunk_size = 64; + else + chunk_size = bytes_remaining; + + ret = jtag_libusb_control_transfer(device->usb_device_handle, + (LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE), + REQUEST_FIRMWARE_LOAD, addr, FIRMWARE_ADDR, (char *)data_ptr, + chunk_size, LIBUSB_TIMEOUT_MS, &transferred); + + if (ret != ERROR_OK) + return ret; + + if (transferred != chunk_size) { + /* Abort if libusb sent less data than requested */ + return ERROR_FAIL; + } + + bytes_remaining -= chunk_size; + addr += chunk_size; + data_ptr += chunk_size; + } + + return ERROR_OK; +} + +/************************** Generic helper functions **************************/ + +/** + * Print state of interesting signals via LOG_INFO(). + * + * @param input_signals input signal states as returned by CMD_GET_SIGNALS + * @param output_signals output signal states as returned by CMD_GET_SIGNALS + */ +static void angie_dump_signal_states(uint8_t input_signals, uint8_t output_signals) +{ + LOG_INFO("ANGIE signal states: TDI: %i, TDO: %i, TMS: %i, TCK: %i, TRST: %i " + "SRST: %i", + (output_signals & SIGNAL_TDI ? 1 : 0), + (input_signals & SIGNAL_TDO ? 1 : 0), + (output_signals & SIGNAL_TMS ? 1 : 0), + (output_signals & SIGNAL_TCK ? 1 : 0), + (output_signals & SIGNAL_TRST ? 1 : 0), + (output_signals & SIGNAL_SRST ? 1 : 0)); +} + +/**************** ANGIE command generation helper functions ***************/ + +/** + * Allocate and initialize space in memory for ANGIE command payload. + * + * @param angie_cmd pointer to command whose payload should be allocated. + * @param size the amount of memory to allocate (bytes). + * @param direction which payload to allocate. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_allocate_payload(struct angie_cmd *angie_cmd, int size, + enum angie_payload_direction direction) +{ + uint8_t *payload; + + payload = calloc(size, sizeof(uint8_t)); + + if (!payload) { + LOG_ERROR("Could not allocate ANGIE command payload: out of memory"); + return ERROR_FAIL; + } + + switch (direction) { + case PAYLOAD_DIRECTION_OUT: + if (angie_cmd->payload_out) { + LOG_ERROR("BUG: Duplicate payload allocation for ANGIE command"); + free(payload); + return ERROR_FAIL; + } + angie_cmd->payload_out = payload; + angie_cmd->payload_out_size = size; + break; + case PAYLOAD_DIRECTION_IN: + if (angie_cmd->payload_in_start) { + LOG_ERROR("BUG: Duplicate payload allocation for ANGIE command"); + free(payload); + return ERROR_FAIL; + } + + angie_cmd->payload_in_start = payload; + angie_cmd->payload_in = payload; + angie_cmd->payload_in_size = size; + + /* By default, free payload_in_start in angie_clear_queue(). Commands + * that do not want this behavior (e. g. split scans) must turn it off + * separately! */ + angie_cmd->free_payload_in_start = true; + + break; + } + + return ERROR_OK; +} + +/****************** ANGIE command queue helper functions ******************/ + +/** + * Get the current number of bytes in the queue, including command IDs. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param direction the transfer direction for which to get byte count. + * @return the number of bytes currently stored in the queue for the specified + * direction. + */ +static int angie_get_queue_size(struct angie *device, + enum angie_payload_direction direction) +{ + struct angie_cmd *current = device->queue_start; + int sum = 0; + + while (current) { + switch (direction) { + case PAYLOAD_DIRECTION_OUT: + sum += current->payload_out_size + 1; /* + 1 byte for Command ID */ + break; + case PAYLOAD_DIRECTION_IN: + sum += current->payload_in_size; + break; + } + + current = current->next; + } + + return sum; +} + +/** + * Clear the ANGIE command queue. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + */ +static void angie_clear_queue(struct angie *device) +{ + struct angie_cmd *current = device->queue_start; + struct angie_cmd *next = NULL; + + while (current) { + /* Save pointer to next element */ + next = current->next; + + /* Free payloads: OUT payload can be freed immediately */ + free(current->payload_out); + current->payload_out = NULL; + + /* IN payload MUST be freed ONLY if no other commands use the + * payload_in_start buffer */ + if (current->free_payload_in_start) { + free(current->payload_in_start); + current->payload_in_start = NULL; + current->payload_in = NULL; + } + + /* Free queue element */ + free(current); + + /* Proceed with next element */ + current = next; + } + + device->commands_in_queue = 0; + device->queue_start = NULL; + device->queue_end = NULL; +} + +/** + * Add a command to the ANGIE command queue. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param angie_cmd pointer to command that shall be appended to the ANGIE + * command queue. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_queue(struct angie *device, struct angie_cmd *angie_cmd) +{ + int newsize_out, newsize_in; + int ret = ERROR_OK; + + newsize_out = angie_get_queue_size(device, PAYLOAD_DIRECTION_OUT) + 1 + + angie_cmd->payload_out_size; + + newsize_in = angie_get_queue_size(device, PAYLOAD_DIRECTION_IN) + + angie_cmd->payload_in_size; + + /* Check if the current command can be appended to the queue */ + if (newsize_out > 64 || newsize_in > 64) { + /* New command does not fit. Execute all commands in queue before starting + * new queue with the current command as first entry. */ + ret = angie_execute_queued_commands(device, LIBUSB_TIMEOUT_MS); + + if (ret == ERROR_OK) + ret = angie_post_process_queue(device); + + if (ret == ERROR_OK) + angie_clear_queue(device); + } + + if (!device->queue_start) { + /* Queue was empty */ + device->commands_in_queue = 1; + + device->queue_start = angie_cmd; + device->queue_end = angie_cmd; + } else { + /* There are already commands in the queue */ + device->commands_in_queue++; + + device->queue_end->next = angie_cmd; + device->queue_end = angie_cmd; + } + + if (ret != ERROR_OK) + angie_clear_queue(device); + + return ret; +} + +/** + * Sends all queued ANGIE commands to the ANGIE for execution. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param timeout_ms + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_execute_queued_commands(struct angie *device, int timeout_ms) +{ + struct angie_cmd *current; + int ret, i, index_out, index_in, count_out, count_in, transferred; + uint8_t buffer[64]; + + if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) + angie_dump_queue(device); + + index_out = 0; + count_out = 0; + count_in = 0; + + for (current = device->queue_start; current; current = current->next) { + /* Add command to packet */ + buffer[index_out] = current->id; + index_out++; + count_out++; + + for (i = 0; i < current->payload_out_size; i++) + buffer[index_out + i] = current->payload_out[i]; + index_out += current->payload_out_size; + count_in += current->payload_in_size; + count_out += current->payload_out_size; + } + + /* Send packet to ANGIE */ + ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_out, + (char *)buffer, count_out, timeout_ms, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Libusb bulk write queued commands failed."); + return ret; + } + if (transferred != count_out) { + LOG_ERROR("Libusb bulk write queued commands failed: transferred byte count"); + return ERROR_FAIL; + } + + /* Wait for response if commands contain IN payload data */ + if (count_in > 0) { + ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_in, + (char *)buffer, count_in, timeout_ms, &transferred); + if (ret != ERROR_OK) { + LOG_ERROR("Libusb bulk write input payload data failed"); + return ret; + } + if (transferred != count_in) { + LOG_ERROR("Libusb bulk write input payload data failed: transferred byte count"); + return ERROR_FAIL; + } + + /* Write back IN payload data */ + index_in = 0; + for (current = device->queue_start; current; current = current->next) { + for (i = 0; i < current->payload_in_size; i++) { + current->payload_in[i] = buffer[index_in]; + index_in++; + } + } + } + return ERROR_OK; +} + +/** + * Convert an ANGIE command ID (\a id) to a human-readable string. + * + * @param id the ANGIE command ID. + * @return the corresponding human-readable string. + */ +static const char *angie_cmd_id_string(uint8_t id) +{ + switch (id) { + case CMD_SCAN_IN: + return "CMD_SCAN_IN"; + case CMD_SLOW_SCAN_IN: + return "CMD_SLOW_SCAN_IN"; + case CMD_SCAN_OUT: + return "CMD_SCAN_OUT"; + case CMD_SLOW_SCAN_OUT: + return "CMD_SLOW_SCAN_OUT"; + case CMD_SCAN_IO: + return "CMD_SCAN_IO"; + case CMD_SLOW_SCAN_IO: + return "CMD_SLOW_SCAN_IO"; + case CMD_CLOCK_TMS: + return "CMD_CLOCK_TMS"; + case CMD_SLOW_CLOCK_TMS: + return "CMD_SLOW_CLOCK_TMS"; + case CMD_CLOCK_TCK: + return "CMD_CLOCK_TCK"; + case CMD_SLOW_CLOCK_TCK: + return "CMD_SLOW_CLOCK_TCK"; + case CMD_SLEEP_US: + return "CMD_SLEEP_US"; + case CMD_SLEEP_MS: + return "CMD_SLEEP_MS"; + case CMD_GET_SIGNALS: + return "CMD_GET_SIGNALS"; + case CMD_SET_SIGNALS: + return "CMD_SET_SIGNALS"; + case CMD_CONFIGURE_TCK_FREQ: + return "CMD_CONFIGURE_TCK_FREQ"; + case CMD_SET_LEDS: + return "CMD_SET_LEDS"; + case CMD_TEST: + return "CMD_TEST"; + default: + return "CMD_UNKNOWN"; + } +} + +/** + * Print one ANGIE command to stdout. + * + * @param angie_cmd pointer to ANGIE command. + */ +static void angie_dump_command(struct angie_cmd *angie_cmd) +{ + char hex[64 * 3]; + for (int i = 0; i < angie_cmd->payload_out_size; i++) + sprintf(hex + 3 * i, "%02" PRIX8 " ", angie_cmd->payload_out[i]); + + hex[3 * angie_cmd->payload_out_size - 1] = 0; + LOG_DEBUG_IO(" %-22s | OUT size = %" PRIi8 ", bytes = %s", + angie_cmd_id_string(angie_cmd->id), angie_cmd->payload_out_size, hex); + + LOG_DEBUG_IO("\n | IN size = %" PRIi8 "\n", angie_cmd->payload_in_size); +} + +/** + * Print the ANGIE command queue to stdout. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + */ +static void angie_dump_queue(struct angie *device) +{ + struct angie_cmd *current; + + LOG_DEBUG_IO("ANGIE command queue:\n"); + + for (current = device->queue_start; current; current = current->next) + angie_dump_command(current); +} + +/** + * Perform JTAG scan + * + * Creates and appends a JTAG scan command to the ANGIE command queue. + * A JTAG scan consists of three steps: + * - Move to the desired SHIFT state, depending on scan type (IR/DR scan). + * - Shift TDI data into the JTAG chain, optionally reading the TDO pin. + * - Move to the desired end state. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param scan_type the type of the scan (IN, OUT, IO (bidirectional)). + * @param scan_size_bits number of bits to shift into the JTAG chain. + * @param tdi pointer to array containing TDI data. + * @param tdo_start pointer to first element of array where TDO data shall be + * stored. See #angie_cmd for details. + * @param tdo pointer to array where TDO data shall be stored + * @param tms_count_start number of TMS state transitions to perform BEFORE + * shifting data into the JTAG chain. + * @param tms_sequence_start sequence of TMS state transitions that will be + * performed BEFORE shifting data into the JTAG chain. + * @param tms_count_end number of TMS state transitions to perform AFTER + * shifting data into the JTAG chain. + * @param tms_sequence_end sequence of TMS state transitions that will be + * performed AFTER shifting data into the JTAG chain. + * @param origin pointer to OpenOCD command that generated this scan command. + * @param postprocess whether this command needs to be post-processed after + * execution. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_scan_cmd(struct angie *device, enum scan_type scan_type, + int scan_size_bits, uint8_t *tdi, uint8_t *tdo_start, uint8_t *tdo, + uint8_t tms_count_start, uint8_t tms_sequence_start, uint8_t tms_count_end, + uint8_t tms_sequence_end, struct jtag_command *origin, bool postprocess) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret, i, scan_size_bytes; + uint8_t bits_last_byte; + + if (!cmd) + return ERROR_FAIL; + + /* Check size of command. USB buffer can hold 64 bytes, 1 byte is command ID, + * 5 bytes are setup data -> 58 remaining payload bytes for TDI data */ + if (scan_size_bits > (58 * 8)) { + LOG_ERROR("BUG: Tried to create CMD_SCAN_IO ANGIE command with too" + " large payload"); + free(cmd); + return ERROR_FAIL; + } + + scan_size_bytes = DIV_ROUND_UP(scan_size_bits, 8); + + bits_last_byte = scan_size_bits % 8; + if (bits_last_byte == 0) + bits_last_byte = 8; + + /* Allocate out_payload depending on scan type */ + switch (scan_type) { + case SCAN_IN: + if (device->delay_scan_in < 0) + cmd->id = CMD_SCAN_IN; + else + cmd->id = CMD_SLOW_SCAN_IN; + ret = angie_allocate_payload(cmd, 5, PAYLOAD_DIRECTION_IN); + break; + case SCAN_OUT: + if (device->delay_scan_out < 0) + cmd->id = CMD_SCAN_OUT; + else + cmd->id = CMD_SLOW_SCAN_OUT; + ret = angie_allocate_payload(cmd, scan_size_bytes + 5, PAYLOAD_DIRECTION_OUT); + break; + case SCAN_IO: + if (device->delay_scan_io < 0) + cmd->id = CMD_SCAN_IO; + else + cmd->id = CMD_SLOW_SCAN_IO; + ret = angie_allocate_payload(cmd, scan_size_bytes + 5, PAYLOAD_DIRECTION_OUT); + break; + default: + LOG_ERROR("BUG: 'append scan cmd' encountered an unknown scan type"); + ret = ERROR_FAIL; + break; + } + + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + /* Build payload_out that is common to all scan types */ + cmd->payload_out[0] = scan_size_bytes & 0xFF; + cmd->payload_out[1] = bits_last_byte & 0xFF; + cmd->payload_out[2] = ((tms_count_start & 0x0F) << 4) | (tms_count_end & 0x0F); + cmd->payload_out[3] = tms_sequence_start; + cmd->payload_out[4] = tms_sequence_end; + + /* Setup payload_out for types with OUT transfer */ + if (scan_type == SCAN_OUT || scan_type == SCAN_IO) { + for (i = 0; i < scan_size_bytes; i++) + cmd->payload_out[i + 5] = tdi[i]; + } + + /* Setup payload_in pointers for types with IN transfer */ + if (scan_type == SCAN_IN || scan_type == SCAN_IO) { + cmd->payload_in_start = tdo_start; + cmd->payload_in = tdo; + cmd->payload_in_size = scan_size_bytes; + } + + cmd->needs_postprocessing = postprocess; + cmd->cmd_origin = origin; + + /* For scan commands, we free payload_in_start only when the command is + * the last in a series of split commands or a stand-alone command */ + cmd->free_payload_in_start = postprocess; + + return angie_append_queue(device, cmd); +} + +/** + * Perform TAP state transitions + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param count defines the number of TCK clock cycles generated (up to 8). + * @param sequence defines the TMS pin levels for each state transition. The + * Least-Significant Bit is read first. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_clock_tms_cmd(struct angie *device, uint8_t count, + uint8_t sequence) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + if (device->delay_clock_tms < 0) + cmd->id = CMD_CLOCK_TMS; + else + cmd->id = CMD_SLOW_CLOCK_TMS; + + /* CMD_CLOCK_TMS has two OUT payload bytes and zero IN payload bytes */ + ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT); + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + cmd->payload_out[0] = count; + cmd->payload_out[1] = sequence; + + return angie_append_queue(device, cmd); +} + +/** + * Generate a defined amount of TCK clock cycles + * + * All other JTAG signals are left unchanged. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param count the number of TCK clock cycles to generate. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_clock_tck_cmd(struct angie *device, uint16_t count) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + if (device->delay_clock_tck < 0) + cmd->id = CMD_CLOCK_TCK; + else + cmd->id = CMD_SLOW_CLOCK_TCK; + + /* CMD_CLOCK_TCK has two OUT payload bytes and zero IN payload bytes */ + ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT); + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + cmd->payload_out[0] = count & 0xff; + cmd->payload_out[1] = (count >> 8) & 0xff; + + return angie_append_queue(device, cmd); +} + +/** + * Read JTAG signals. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_get_signals_cmd(struct angie *device) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + cmd->id = CMD_GET_SIGNALS; + cmd->needs_postprocessing = true; + + /* CMD_GET_SIGNALS has two IN payload bytes */ + ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_IN); + + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + return angie_append_queue(device, cmd); +} + +/** + * Arbitrarily set JTAG output signals. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param low defines which signals will be de-asserted. Each bit corresponds + * to a JTAG signal: + * - SIGNAL_TDI + * - SIGNAL_TMS + * - SIGNAL_TCK + * - SIGNAL_TRST + * - SIGNAL_BRKIN + * - SIGNAL_RESET + * - SIGNAL_OCDSE + * @param high defines which signals will be asserted. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_set_signals_cmd(struct angie *device, uint8_t low, + uint8_t high) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + cmd->id = CMD_SET_SIGNALS; + + /* CMD_SET_SIGNALS has two OUT payload bytes and zero IN payload bytes */ + ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT); + + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + cmd->payload_out[0] = low; + cmd->payload_out[1] = high; + + return angie_append_queue(device, cmd); +} + +/** + * Sleep for a pre-defined number of microseconds + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param us the number microseconds to sleep. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_sleep_cmd(struct angie *device, uint32_t us) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + cmd->id = CMD_SLEEP_US; + + /* CMD_SLEEP_US has two OUT payload bytes and zero IN payload bytes */ + ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT); + + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + cmd->payload_out[0] = us & 0x00ff; + cmd->payload_out[1] = (us >> 8) & 0x00ff; + + return angie_append_queue(device, cmd); +} + +/** + * Set TCK delay counters + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param delay_scan_in delay count top value in jtag_slow_scan_in() function. + * @param delay_scan_out delay count top value in jtag_slow_scan_out() function. + * @param delay_scan_io delay count top value in jtag_slow_scan_io() function. + * @param delay_tck delay count top value in jtag_clock_tck() function. + * @param delay_tms delay count top value in jtag_slow_clock_tms() function. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_configure_tck_cmd(struct angie *device, int delay_scan_in, + int delay_scan_out, int delay_scan_io, int delay_tck, int delay_tms) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + cmd->id = CMD_CONFIGURE_TCK_FREQ; + + /* CMD_CONFIGURE_TCK_FREQ has five OUT payload bytes and zero + * IN payload bytes */ + ret = angie_allocate_payload(cmd, 5, PAYLOAD_DIRECTION_OUT); + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + if (delay_scan_in < 0) + cmd->payload_out[0] = 0; + else + cmd->payload_out[0] = (uint8_t)delay_scan_in; + + if (delay_scan_out < 0) + cmd->payload_out[1] = 0; + else + cmd->payload_out[1] = (uint8_t)delay_scan_out; + + if (delay_scan_io < 0) + cmd->payload_out[2] = 0; + else + cmd->payload_out[2] = (uint8_t)delay_scan_io; + + if (delay_tck < 0) + cmd->payload_out[3] = 0; + else + cmd->payload_out[3] = (uint8_t)delay_tck; + + if (delay_tms < 0) + cmd->payload_out[4] = 0; + else + cmd->payload_out[4] = (uint8_t)delay_tms; + + return angie_append_queue(device, cmd); +} + +/** + * Test command. Used to check if the ANGIE device is ready to accept new + * commands. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_append_test_cmd(struct angie *device) +{ + struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd)); + int ret; + + if (!cmd) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + cmd->id = CMD_TEST; + + /* CMD_TEST has one OUT payload byte and zero IN payload bytes */ + ret = angie_allocate_payload(cmd, 1, PAYLOAD_DIRECTION_OUT); + if (ret != ERROR_OK) { + free(cmd); + return ret; + } + + cmd->payload_out[0] = 0xAA; + + return angie_append_queue(device, cmd); +} + +/****************** ANGIE TCK frequency helper functions ******************/ + +/** + * Calculate delay values for a given TCK frequency. + * + * The ANGIE firmware uses five different speed values for different + * commands. These speed values are calculated in these functions. + * + * The five different commands which support variable TCK frequency are + * implemented twice in the firmware: + * 1. Maximum possible frequency without any artificial delay + * 2. Variable frequency with artificial linear delay loop + * + * To set the ANGIE to maximum frequency, it is only necessary to use the + * corresponding command IDs. To set the ANGIE to a lower frequency, the + * delay loop top values have to be calculated first. Then, a + * CMD_CONFIGURE_TCK_FREQ command needs to be sent to the ANGIE device. + * + * The delay values are described by linear equations: + * t = k * x + d + * (t = period, k = constant, x = delay value, d = constant) + * + * Thus, the delay can be calculated as in the following equation: + * x = (t - d) / k + * + * The constants in these equations have been determined and validated by + * measuring the frequency resulting from different delay values. + * + * @param type for which command to calculate the delay value. + * @param f TCK frequency for which to calculate the delay value in Hz. + * @param delay where to store resulting delay value. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_calculate_delay(enum angie_delay_type type, long f, int *delay) +{ + float t_us, x, x_ceil; + + /* Calculate period of requested TCK frequency */ + t_us = 1000000.0 / f; + + switch (type) { + case DELAY_CLOCK_TCK: + x = (t_us - 6.0) / 4; + break; + case DELAY_CLOCK_TMS: + x = (t_us - 8.5) / 4; + break; + case DELAY_SCAN_IN: + x = (t_us - 8.8308) / 4; + break; + case DELAY_SCAN_OUT: + x = (t_us - 10.527) / 4; + break; + case DELAY_SCAN_IO: + x = (t_us - 13.132) / 4; + break; + default: + return ERROR_FAIL; + break; + } + + /* Check if the delay value is negative. This happens when a frequency is + * requested that is too high for the delay loop implementation. In this + * case, set delay value to zero. */ + if (x < 0) + x = 0; + + /* We need to convert the exact delay value to an integer. Therefore, we + * round the exact value UP to ensure that the resulting frequency is NOT + * higher than the requested frequency. */ + x_ceil = ceilf(x); + + /* Check if the value is within limits */ + if (x_ceil > 255) + return ERROR_FAIL; + + *delay = (int)x_ceil; + + return ERROR_OK; +} + +/** + * Calculate frequency for a given delay value. + * + * Similar to the #angie_calculate_delay function, this function calculates the + * TCK frequency for a given delay value by using linear equations of the form: + * t = k * x + d + * (t = period, k = constant, x = delay value, d = constant) + * + * @param type for which command to calculate the delay value. + * @param delay value for which to calculate the resulting TCK frequency. + * @return the resulting TCK frequency + */ +static long angie_calculate_frequency(enum angie_delay_type type, int delay) +{ + float t_us, f_float; + + if (delay > 255) + return 0; + + switch (type) { + case DELAY_CLOCK_TCK: + if (delay < 0) + t_us = 2.666; + else + t_us = (4.0 * delay) + 6.0; + break; + case DELAY_CLOCK_TMS: + if (delay < 0) + t_us = 5.666; + else + t_us = (4.0 * delay) + 8.5; + break; + case DELAY_SCAN_IN: + if (delay < 0) + t_us = 5.5; + else + t_us = (4.0 * delay) + 8.8308; + break; + case DELAY_SCAN_OUT: + if (delay < 0) + t_us = 7.0; + else + t_us = (4.0 * delay) + 10.527; + break; + case DELAY_SCAN_IO: + if (delay < 0) + t_us = 9.926; + else + t_us = (4.0 * delay) + 13.132; + break; + default: + return 0; + } + + f_float = 1000000.0 / t_us; + return roundf(f_float); +} + +/******************* Interface between ANGIE and OpenOCD ******************/ + +/** + * Sets the end state follower (see interface.h) if \a endstate is a stable + * state. + * + * @param endstate the state the end state follower should be set to. + */ +static void angie_set_end_state(enum tap_state endstate) +{ + if (tap_is_state_stable(endstate)) + tap_set_end_state(endstate); + else + LOG_ERROR("BUG: %s is not a valid end state", tap_state_name(endstate)); +} + +/** + * Move from the current TAP state to the current TAP end state. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_statemove(struct angie *device) +{ + uint8_t tms_sequence, tms_count; + int ret; + + if (tap_get_state() == tap_get_end_state()) { + /* Do nothing if we are already there */ + return ERROR_OK; + } + + tms_sequence = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + + ret = angie_append_clock_tms_cmd(device, tms_count, tms_sequence); + + if (ret == ERROR_OK) + tap_set_state(tap_get_end_state()); + + return ret; +} + +/** + * Perform a scan operation on a JTAG register. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_scan(struct angie *device, struct jtag_command *cmd) +{ + uint32_t scan_size_bits, scan_size_bytes, bits_last_scan; + uint32_t scans_max_payload, bytecount; + uint8_t *tdi_buffer_start = NULL, *tdi_buffer = NULL; + uint8_t *tdo_buffer_start = NULL, *tdo_buffer = NULL; + + uint8_t first_tms_count, first_tms_sequence; + uint8_t last_tms_count, last_tms_sequence; + + uint8_t tms_count_pause, tms_sequence_pause; + uint8_t tms_count_resume, tms_sequence_resume; + + uint8_t tms_count_start, tms_sequence_start; + uint8_t tms_count_end, tms_sequence_end; + + enum scan_type type; + int ret; + + /* Determine scan size */ + scan_size_bits = jtag_scan_size(cmd->cmd.scan); + scan_size_bytes = DIV_ROUND_UP(scan_size_bits, 8); + + /* Determine scan type (IN/OUT/IO) */ + type = jtag_scan_type(cmd->cmd.scan); + + /* Determine number of scan commands with maximum payload */ + scans_max_payload = scan_size_bytes / 58; + + /* Determine size of last shift command */ + bits_last_scan = scan_size_bits - (scans_max_payload * 58 * 8); + + /* Allocate TDO buffer if required */ + if (type == SCAN_IN || type == SCAN_IO) { + tdo_buffer_start = calloc(scan_size_bytes, sizeof(uint8_t)); + + if (!tdo_buffer_start) + return ERROR_FAIL; + + tdo_buffer = tdo_buffer_start; + } + + /* Fill TDI buffer if required */ + if (type == SCAN_OUT || type == SCAN_IO) { + jtag_build_buffer(cmd->cmd.scan, &tdi_buffer_start); + tdi_buffer = tdi_buffer_start; + } + + /* Get TAP state transitions */ + if (cmd->cmd.scan->ir_scan) { + angie_set_end_state(TAP_IRSHIFT); + first_tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + first_tms_sequence = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + + tap_set_state(TAP_IRSHIFT); + tap_set_end_state(cmd->cmd.scan->end_state); + last_tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + last_tms_sequence = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + + /* TAP state transitions for split scans */ + tms_count_pause = tap_get_tms_path_len(TAP_IRSHIFT, TAP_IRPAUSE); + tms_sequence_pause = tap_get_tms_path(TAP_IRSHIFT, TAP_IRPAUSE); + tms_count_resume = tap_get_tms_path_len(TAP_IRPAUSE, TAP_IRSHIFT); + tms_sequence_resume = tap_get_tms_path(TAP_IRPAUSE, TAP_IRSHIFT); + } else { + angie_set_end_state(TAP_DRSHIFT); + first_tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + first_tms_sequence = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + + tap_set_state(TAP_DRSHIFT); + tap_set_end_state(cmd->cmd.scan->end_state); + last_tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + last_tms_sequence = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + + /* TAP state transitions for split scans */ + tms_count_pause = tap_get_tms_path_len(TAP_DRSHIFT, TAP_DRPAUSE); + tms_sequence_pause = tap_get_tms_path(TAP_DRSHIFT, TAP_DRPAUSE); + tms_count_resume = tap_get_tms_path_len(TAP_DRPAUSE, TAP_DRSHIFT); + tms_sequence_resume = tap_get_tms_path(TAP_DRPAUSE, TAP_DRSHIFT); + } + + /* Generate scan commands */ + bytecount = scan_size_bytes; + while (bytecount > 0) { + if (bytecount == scan_size_bytes) { + /* This is the first scan */ + tms_count_start = first_tms_count; + tms_sequence_start = first_tms_sequence; + } else { + /* Resume from previous scan */ + tms_count_start = tms_count_resume; + tms_sequence_start = tms_sequence_resume; + } + + if (bytecount > 58) { /* Full scan, at least one scan will follow */ + tms_count_end = tms_count_pause; + tms_sequence_end = tms_sequence_pause; + + ret = angie_append_scan_cmd(device, + type, + 58 * 8, + tdi_buffer, + tdo_buffer_start, + tdo_buffer, + tms_count_start, + tms_sequence_start, + tms_count_end, + tms_sequence_end, + cmd, + false); + + bytecount -= 58; + + /* Update TDI and TDO buffer pointers */ + if (tdi_buffer_start) + tdi_buffer += 58; + if (tdo_buffer_start) + tdo_buffer += 58; + } else if (bytecount == 58) { /* Full scan, no further scans */ + tms_count_end = last_tms_count; + tms_sequence_end = last_tms_sequence; + + ret = angie_append_scan_cmd(device, + type, + 58 * 8, + tdi_buffer, + tdo_buffer_start, + tdo_buffer, + tms_count_start, + tms_sequence_start, + tms_count_end, + tms_sequence_end, + cmd, + true); + + bytecount = 0; + } else {/* Scan with less than maximum payload, no further scans */ + tms_count_end = last_tms_count; + tms_sequence_end = last_tms_sequence; + + ret = angie_append_scan_cmd(device, + type, + bits_last_scan, + tdi_buffer, + tdo_buffer_start, + tdo_buffer, + tms_count_start, + tms_sequence_start, + tms_count_end, + tms_sequence_end, + cmd, + true); + + bytecount = 0; + } + + if (ret != ERROR_OK) { + free(tdi_buffer_start); + free(tdo_buffer_start); + return ret; + } + } + + free(tdi_buffer_start); + + /* Set current state to the end state requested by the command */ + tap_set_state(cmd->cmd.scan->end_state); + + return ERROR_OK; +} + +/** + * Move the TAP into the Test Logic Reset state. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_tlr_reset(struct angie *device, struct jtag_command *cmd) +{ + int ret = angie_append_clock_tms_cmd(device, 5, 0xff); + + if (ret == ERROR_OK) + tap_set_state(TAP_RESET); + + return ret; +} + +/** + * Run Test. + * + * Generate TCK clock cycles while remaining + * in the Run-Test/Idle state. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_runtest(struct angie *device, struct jtag_command *cmd) +{ + int ret; + + /* Only perform statemove if the TAP currently isn't in the TAP_IDLE state */ + if (tap_get_state() != TAP_IDLE) { + angie_set_end_state(TAP_IDLE); + angie_queue_statemove(device); + } + + /* Generate the clock cycles */ + ret = angie_append_clock_tck_cmd(device, cmd->cmd.runtest->num_cycles); + if (ret != ERROR_OK) + return ret; + + /* Move to end state specified in command */ + if (cmd->cmd.runtest->end_state != tap_get_state()) { + tap_set_end_state(cmd->cmd.runtest->end_state); + angie_queue_statemove(device); + } + + return ERROR_OK; +} + +/** + * Execute a JTAG_RESET command + * + * @param device + * @param trst indicate if trst signal is activated. + * @param srst indicate if srst signal is activated. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_reset(int trst, int srst) +{ + struct angie *device = angie_handle; + uint8_t low = 0, high = 0; + + if (trst) { + tap_set_state(TAP_RESET); + low |= SIGNAL_TRST; + } else { + high |= SIGNAL_TRST; + } + + if (srst) + low |= SIGNAL_SRST; + else + high |= SIGNAL_SRST; + + int ret = angie_append_set_signals_cmd(device, low, high); + if (ret != ERROR_OK) + return ret; + + ret = angie_execute_queued_commands(device, LIBUSB_TIMEOUT_MS); + if (ret != ERROR_OK) + return ret; + + angie_clear_queue(device); + + return ERROR_OK; +} + +/** + * Move to one TAP state or several states in succession. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_pathmove(struct angie *device, struct jtag_command *cmd) +{ + int ret, state_count; + enum tap_state *path; + uint8_t tms_sequence; + + unsigned int num_states = cmd->cmd.pathmove->num_states; + path = cmd->cmd.pathmove->path; + state_count = 0; + + while (num_states > 0) { + unsigned int batch_size; + + tms_sequence = 0; + + /* Determine batch size */ + if (num_states >= 8) + batch_size = 8; + else + batch_size = num_states; + + for (unsigned int i = 0; i < batch_size; i++) { + if (tap_state_transition(tap_get_state(), false) == path[state_count]) { + /* Append '0' transition: clear bit 'i' in tms_sequence */ + buf_set_u32(&tms_sequence, i, 1, 0x0); + } else if (tap_state_transition(tap_get_state(), true) + == path[state_count]) { + /* Append '1' transition: set bit 'i' in tms_sequence */ + buf_set_u32(&tms_sequence, i, 1, 0x1); + } else { + /* Invalid state transition */ + LOG_ERROR("BUG: %s -> %s isn't a valid TAP state transition", + tap_state_name(tap_get_state()), + tap_state_name(path[state_count])); + return ERROR_FAIL; + } + + tap_set_state(path[state_count]); + state_count++; + num_states--; + } + + /* Append CLOCK_TMS command to ANGIE command queue */ + LOG_INFO("pathmove batch: count = %i, sequence = 0x%" PRIx8 "", batch_size, tms_sequence); + ret = angie_append_clock_tms_cmd(angie_handle, batch_size, tms_sequence); + if (ret != ERROR_OK) + return ret; + } + + return ERROR_OK; +} + +/** + * Sleep for a specific amount of time. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_queue_sleep(struct angie *device, struct jtag_command *cmd) +{ + /* IMPORTANT! Due to the time offset in command execution introduced by + * command queueing, this needs to be implemented in the ANGIE device */ + return angie_append_sleep_cmd(device, cmd->cmd.sleep->us); +} + +/** + * Generate TCK cycles while remaining in a stable state. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @param cmd pointer to the command that shall be executed. + */ +static int angie_queue_stableclocks(struct angie *device, struct jtag_command *cmd) +{ + int ret; + + if (!tap_is_state_stable(tap_get_state())) { + LOG_ERROR("JTAG_STABLECLOCKS: state not stable"); + return ERROR_FAIL; + } + + unsigned int num_cycles = cmd->cmd.stableclocks->num_cycles; + + /* TMS stays either high (Test Logic Reset state) or low (all other states) */ + if (tap_get_state() == TAP_RESET) + ret = angie_append_set_signals_cmd(device, 0, SIGNAL_TMS); + else + ret = angie_append_set_signals_cmd(device, SIGNAL_TMS, 0); + + if (ret != ERROR_OK) + return ret; + + while (num_cycles > 0) { + if (num_cycles > 0xFFFF) { + /* ANGIE CMD_CLOCK_TCK can generate up to 0xFFFF (uint16_t) cycles */ + ret = angie_append_clock_tck_cmd(device, 0xFFFF); + num_cycles -= 0xFFFF; + } else { + ret = angie_append_clock_tck_cmd(device, num_cycles); + num_cycles = 0; + } + + if (ret != ERROR_OK) + return ret; + } + + return ERROR_OK; +} + +/** + * Post-process JTAG_SCAN command + * + * @param angie_cmd pointer to ANGIE command that shall be processed. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_post_process_scan(struct angie_cmd *angie_cmd) +{ + struct jtag_command *cmd = angie_cmd->cmd_origin; + int ret; + + switch (jtag_scan_type(cmd->cmd.scan)) { + case SCAN_IN: + case SCAN_IO: + ret = jtag_read_buffer(angie_cmd->payload_in_start, cmd->cmd.scan); + break; + case SCAN_OUT: + /* Nothing to do for OUT scans */ + ret = ERROR_OK; + break; + default: + LOG_ERROR("BUG: angie post process scan encountered an unknown JTAG scan type"); + ret = ERROR_FAIL; + break; + } + + return ret; +} + +/** + * Perform post-processing of commands after ANGIE queue has been executed. + * + * @param device pointer to struct angie identifying ANGIE driver instance. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_post_process_queue(struct angie *device) +{ + struct angie_cmd *current; + struct jtag_command *openocd_cmd; + int ret; + + current = device->queue_start; + + while (current) { + openocd_cmd = current->cmd_origin; + + /* Check if a corresponding OpenOCD command is stored for this + * ANGIE command */ + if (current->needs_postprocessing && openocd_cmd) { + switch (openocd_cmd->type) { + case JTAG_SCAN: + ret = angie_post_process_scan(current); + break; + case JTAG_TLR_RESET: + case JTAG_RUNTEST: + case JTAG_PATHMOVE: + case JTAG_SLEEP: + case JTAG_STABLECLOCKS: + /* Nothing to do for these commands */ + ret = ERROR_OK; + break; + default: + ret = ERROR_FAIL; + LOG_ERROR("BUG: angie post process queue encountered unknown JTAG " + "command type"); + break; + } + + if (ret != ERROR_OK) + return ret; + } + + current = current->next; + } + + return ERROR_OK; +} + +/**************************** JTAG driver functions ***************************/ + +/** + * Executes the JTAG Command Queue. + * + * This is done in three stages: First, all OpenOCD commands are processed into + * queued ANGIE commands. Next, the ANGIE command queue is sent to the + * ANGIE device and data received from the ANGIE device is cached. Finally, + * the post-processing function writes back data to the corresponding OpenOCD + * commands. + * + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_execute_queue(struct jtag_command *cmd_queue) +{ + struct jtag_command *cmd = cmd_queue; + int ret; + + while (cmd) { + switch (cmd->type) { + case JTAG_SCAN: + ret = angie_queue_scan(angie_handle, cmd); + break; + case JTAG_TLR_RESET: + ret = angie_queue_tlr_reset(angie_handle, cmd); + break; + case JTAG_RUNTEST: + ret = angie_queue_runtest(angie_handle, cmd); + break; + case JTAG_PATHMOVE: + ret = angie_queue_pathmove(angie_handle, cmd); + break; + case JTAG_SLEEP: + ret = angie_queue_sleep(angie_handle, cmd); + break; + case JTAG_STABLECLOCKS: + ret = angie_queue_stableclocks(angie_handle, cmd); + break; + default: + ret = ERROR_FAIL; + LOG_ERROR("BUG: encountered unknown JTAG command type"); + break; + } + + if (ret != ERROR_OK) + return ret; + + cmd = cmd->next; + } + + if (angie_handle->commands_in_queue > 0) { + ret = angie_execute_queued_commands(angie_handle, LIBUSB_TIMEOUT_MS); + if (ret != ERROR_OK) + return ret; + + ret = angie_post_process_queue(angie_handle); + if (ret != ERROR_OK) + return ret; + + angie_clear_queue(angie_handle); + } + + return ERROR_OK; +} + +/** + * Set the TCK frequency of the ANGIE adapter. + * + * @param khz desired JTAG TCK frequency. + * @param jtag_speed where to store corresponding adapter-specific speed value. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_khz(int khz, int *jtag_speed) +{ + int ret; + + if (khz == 0) { + LOG_ERROR("RCLK not supported"); + return ERROR_FAIL; + } + + /* CLOCK_TCK commands are decoupled from others. Therefore, the frequency + * setting can be done independently from all other commands. */ + if (khz >= 375) { + angie_handle->delay_clock_tck = -1; + } else { + ret = angie_calculate_delay(DELAY_CLOCK_TCK, khz * 1000, + &angie_handle->delay_clock_tck); + if (ret != ERROR_OK) + return ret; + } + + /* SCAN_{IN,OUT,IO} commands invoke CLOCK_TMS commands. Therefore, if the + * requested frequency goes below the maximum frequency for SLOW_CLOCK_TMS + * commands, all SCAN commands MUST also use the variable frequency + * implementation! */ + if (khz >= 176) { + angie_handle->delay_clock_tms = -1; + angie_handle->delay_scan_in = -1; + angie_handle->delay_scan_out = -1; + angie_handle->delay_scan_io = -1; + } else { + ret = angie_calculate_delay(DELAY_CLOCK_TMS, khz * 1000, + &angie_handle->delay_clock_tms); + if (ret != ERROR_OK) + return ret; + + ret = angie_calculate_delay(DELAY_SCAN_IN, khz * 1000, + &angie_handle->delay_scan_in); + if (ret != ERROR_OK) + return ret; + + ret = angie_calculate_delay(DELAY_SCAN_OUT, khz * 1000, + &angie_handle->delay_scan_out); + if (ret != ERROR_OK) + return ret; + + ret = angie_calculate_delay(DELAY_SCAN_IO, khz * 1000, + &angie_handle->delay_scan_io); + if (ret != ERROR_OK) + return ret; + } + + LOG_DEBUG_IO("ANGIE TCK setup: delay_tck = %i (%li Hz),", + angie_handle->delay_clock_tck, + angie_calculate_frequency(DELAY_CLOCK_TCK, angie_handle->delay_clock_tck)); + LOG_DEBUG_IO(" delay_tms = %i (%li Hz),", + angie_handle->delay_clock_tms, + angie_calculate_frequency(DELAY_CLOCK_TMS, angie_handle->delay_clock_tms)); + LOG_DEBUG_IO(" delay_scan_in = %i (%li Hz),", + angie_handle->delay_scan_in, + angie_calculate_frequency(DELAY_SCAN_IN, angie_handle->delay_scan_in)); + LOG_DEBUG_IO(" delay_scan_out = %i (%li Hz),", + angie_handle->delay_scan_out, + angie_calculate_frequency(DELAY_SCAN_OUT, angie_handle->delay_scan_out)); + LOG_DEBUG_IO(" delay_scan_io = %i (%li Hz),", + angie_handle->delay_scan_io, + angie_calculate_frequency(DELAY_SCAN_IO, angie_handle->delay_scan_io)); + + /* Configure the ANGIE device with the new delay values */ + ret = angie_append_configure_tck_cmd(angie_handle, + angie_handle->delay_scan_in, + angie_handle->delay_scan_out, + angie_handle->delay_scan_io, + angie_handle->delay_clock_tck, + angie_handle->delay_clock_tms); + + if (ret != ERROR_OK) + return ret; + + *jtag_speed = khz; + + return ERROR_OK; +} + +/** + * Set the TCK frequency of the ANGIE adapter. + * + * Because of the way the TCK frequency is set up in the ANGIE firmware, + * there are five different speed settings. To simplify things, the + * adapter-specific speed setting value is identical to the TCK frequency in + * khz. + * + * @param speed desired adapter-specific speed value. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_speed(int speed) +{ + int dummy; + + return angie_khz(speed, &dummy); +} + +/** + * Convert adapter-specific speed value to corresponding TCK frequency in kHz. + * + * Because of the way the TCK frequency is set up in the ANGIE firmware, + * there are five different speed settings. To simplify things, the + * adapter-specific speed setting value is identical to the TCK frequency in + * khz. + * + * @param speed adapter-specific speed value. + * @param khz where to store corresponding TCK frequency in kHz. + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_speed_div(int speed, int *khz) +{ + *khz = speed; + + return ERROR_OK; +} + +/** + * Initiates the firmware download to the ANGIE adapter and prepares + * the USB handle. + * + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_init(void) +{ + int ret, transferred; + char str_manufacturer[20]; + bool download_firmware = false; + char dummy[64]; + uint8_t input_signals, output_signals; + + angie_handle = calloc(1, sizeof(struct angie)); + + if (!angie_handle) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + ret = angie_usb_open(angie_handle); + if (ret != ERROR_OK) { + free(angie_handle); + angie_handle = NULL; + return ret; + } + + /* Get String Descriptor to determine if firmware needs to be loaded */ + ret = libusb_get_string_descriptor_ascii(angie_handle->usb_device_handle, 1, (unsigned char *)str_manufacturer, 20); + if (ret < 0) { + /* Could not get descriptor -> Unconfigured or original Keil firmware */ + download_firmware = true; + } else { + /* We got a String Descriptor, check if it is the correct one */ + if (strncmp(str_manufacturer, "NanoXplore, SAS.", 16) != 0) + download_firmware = true; + } + + if (download_firmware) { + LOG_INFO("Loading ANGIE firmware. This is reversible by power-cycling ANGIE device."); + if (libusb_claim_interface(angie_handle->usb_device_handle, 0) != LIBUSB_SUCCESS) { + LOG_ERROR("Could not claim interface 0"); + return ERROR_FAIL; + } + ret = angie_load_firmware_and_renumerate(angie_handle, + ANGIE_FIRMWARE_FILE, ANGIE_RENUMERATION_DELAY_US); + if (ret != ERROR_OK) { + LOG_ERROR("Could not download firmware and re-numerate ANGIE"); + angie_quit(); + return ret; + } + ret = angie_load_bitstream(angie_handle, ANGIE_BITSTREAM_FILE); + if (ret != ERROR_OK) { + LOG_ERROR("Could not download bitstream"); + angie_quit(); + return ret; + } + if (libusb_release_interface(angie_handle->usb_device_handle, 0) != LIBUSB_SUCCESS) { + LOG_ERROR("Fail release interface 0"); + return ERROR_FAIL; + } + if (libusb_claim_interface(angie_handle->usb_device_handle, 1) != LIBUSB_SUCCESS) { + LOG_ERROR("Could not claim interface 1"); + return ERROR_FAIL; + } + /* Configure io extender 23: all input */ + ret = angie_io_extender_config(angie_handle, 0x23, 0xFF); + if (ret != ERROR_OK) { + LOG_ERROR("Could not configure io extender 23"); + return ret; + } + if (libusb_release_interface(angie_handle->usb_device_handle, 1) != LIBUSB_SUCCESS) { + LOG_ERROR("Fail release interface 1"); + return ERROR_FAIL; + } + } else { + LOG_INFO("ANGIE device is already running ANGIE firmware"); + } + + /* Get ANGIE USB IN/OUT endpoints and claim the interface 0 */ + ret = jtag_libusb_choose_interface(angie_handle->usb_device_handle, + &angie_handle->ep_in, &angie_handle->ep_out, 0xFF, 0, 0, -1); + if (ret != ERROR_OK) { + LOG_ERROR("Choose and claim interface failed"); + angie_quit(); + return ret; + } + + /* Initialize ANGIE command queue */ + angie_clear_queue(angie_handle); + + /* Issue one test command with short timeout */ + ret = angie_append_test_cmd(angie_handle); + if (ret != ERROR_OK) { + LOG_ERROR("Append test command failed."); + angie_quit(); + return ret; + } + + ret = angie_execute_queued_commands(angie_handle, 200); + if (ret != ERROR_OK) { + /* Sending test command failed. The ANGIE device may be forever waiting for + * the host to fetch an USB Bulk IN packet (e. g. OpenOCD crashed or was + * shut down by the user via Ctrl-C. Try to retrieve this Bulk IN packet. */ + + ret = jtag_libusb_bulk_write(angie_handle->usb_device_handle, angie_handle->ep_in, + dummy, 64, 200, &transferred); + + if (ret != ERROR_OK || transferred == 0) { + /* Bulk IN transfer failed -> unrecoverable error condition */ + LOG_ERROR("Cannot communicate with ANGIE device. Disconnect ANGIE from " + "the USB port and re-connect, then re-run OpenOCD"); + angie_quit(); + return ERROR_FAIL; + } + /* Successfully received Bulk IN packet -> continue */ + LOG_INFO("Recovered from lost Bulk IN packet"); + } + + angie_clear_queue(angie_handle); + + /* Execute get signals command */ + ret = angie_append_get_signals_cmd(angie_handle); + if (ret != ERROR_OK) { + LOG_ERROR("Append get signals command failed"); + angie_quit(); + return ret; + } + ret = angie_execute_queued_commands(angie_handle, 200); + if (ret != ERROR_OK) { + LOG_ERROR("Execute get signals command failed"); + angie_quit(); + return ret; + } + + /* Post-process the single CMD_GET_SIGNALS command */ + input_signals = angie_handle->queue_start->payload_in[0]; + output_signals = angie_handle->queue_start->payload_in[1]; + angie_dump_signal_states(input_signals, output_signals); + + angie_clear_queue(angie_handle); + + return ERROR_OK; +} + +/** + * Closes the USB handle for the ANGIE device. + * + * @return on success: ERROR_OK + * @return on failure: ERROR_FAIL + */ +static int angie_quit(void) +{ + int ret = angie_usb_close(angie_handle); + free(angie_handle); + angie_handle = NULL; + + return ret; +} + +static struct jtag_interface angie_interface = { + .execute_queue = angie_execute_queue, +}; + +struct adapter_driver angie_adapter_driver = { + .name = "angie", + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, + + .init = angie_init, + .quit = angie_quit, + .reset = angie_reset, + .speed = angie_speed, + .khz = angie_khz, + .speed_div = angie_speed_div, + + .jtag_ops = &angie_interface, +}; diff --git a/src/jtag/drivers/angie/README b/src/jtag/drivers/angie/README new file mode 100644 index 0000000000..c727154c48 --- /dev/null +++ b/src/jtag/drivers/angie/README @@ -0,0 +1,3 @@ +This folder contain only the files needed by ANGIE's driver. +You will find the complete ANGIE's firmware and the bitstream's code source in +contrib/firmware. diff --git a/src/jtag/drivers/angie/angie_bitstream.bit b/src/jtag/drivers/angie/angie_bitstream.bit new file mode 100644 index 0000000000..7b3a88f7c8 Binary files /dev/null and b/src/jtag/drivers/angie/angie_bitstream.bit differ diff --git a/src/jtag/drivers/angie/angie_firmware.bin b/src/jtag/drivers/angie/angie_firmware.bin new file mode 100644 index 0000000000..68486ef8f0 Binary files /dev/null and b/src/jtag/drivers/angie/angie_firmware.bin differ diff --git a/src/jtag/drivers/angie/include/msgtypes.h b/src/jtag/drivers/angie/include/msgtypes.h new file mode 100644 index 0000000000..fb045e98c3 --- /dev/null +++ b/src/jtag/drivers/angie/include/msgtypes.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + +**************************************************************************** + File : msgtypes.h * + Contents : Definition of the commands supported by NanoXplore * + USB-JTAG ANGIE adapter hardware. * + Based on openULINK project code by: Martin Schmoelzer. * + Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. * + <aboudjelida@nanoxplore.com> * + <ahmederrachedbjld@gmail.com> * +*****************************************************************************/ + +/** + * @file + * Definition of the commands supported by the ANGIE firmware. + * + * Basically, two types of commands can be distinguished: + * - Commands with fixed payload size + * - Commands with variable payload size + * + * SCAN commands (in all variations) carry payloads of variable size, all + * other commands carry payloads of fixed size. + * + * In the case of SCAN commands, the payload size (n) is calculated by + * dividing the scan_size_bits variable by 8, rounding up the result. + * + * Offset zero always contains the command ID. + * + **************************************************************************** + * CMD_SCAN_IN, CMD_SLOW_SCAN_IN: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * * + * IN: * + * offset 0..n: TDO data * + **************************************************************************** + * CMD_SCAN_OUT, CMD_SLOW_SCAN_OUT: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * offset 6..x: TDI data * + **************************************************************************** + * CMD_SCAN_IO, CMD_SLOW_SCAN_IO: * + * * + * OUT: * + * offset 1: scan_size_bytes * + * offset 2: bits_last_byte * + * offset 3: tms_count_start + tms_count_end * + * offset 4: tms_sequence_start * + * offset 5: tms_sequence_end * + * offset 6..x: TDI data * + * * + * IN: * + * offset 0..n: TDO data * + **************************************************************************** + * CMD_CLOCK_TMS, CMD_SLOW_CLOCK_TMS: * + * * + * OUT: * + * offset 1: tms_count * + * offset 2: tms_sequence * + **************************************************************************** + * CMD_CLOCK_TCK, CMD_SLOW_CLOCK_TCK: * + * * + * OUT: * + * offset 1: low byte of tck_count * + * offset 2: high byte of tck_count * + **************************************************************************** + * CMD_CLOCK_SLEEP_US: * + * * + * OUT: * + * offset 1: low byte of sleep_us * + * offset 2: high byte of sleep_us * + **************************************************************************** + * CMD_CLOCK_SLEEP_MS: * + * * + * OUT: * + * offset 1: low byte of sleep_ms * + * offset 2: high byte of sleep_ms * + **************************************************************************** + * CMD_GET_SIGNALS: * + * * + * IN: * + * offset 0: current state of input signals * + * offset 1: current state of output signals * + **************************************************************************** + * CMD_SET_SIGNALS: * + * * + * OUT: * + * offset 1: signals that should be de-asserted * + * offset 2: signals that should be asserted * + **************************************************************************** + * CMD_CONFIGURE_TCK_FREQ: * + * * + * OUT: * + * offset 1: delay value for scan_in function * + * offset 2: delay value for scan_out function * + * offset 3: delay value for scan_io function * + * offset 4: delay value for clock_tck function * + * offset 5: delay value for clock_tms function * + **************************************************************************** + * CMD_SET_LEDS: * + * * + * OUT: * + * offset 1: LED states: * + * Bit 0: turn COM LED on * + * Bit 1: turn RUN LED on * + * Bit 2: turn COM LED off * + * Bit 3: turn RUN LED off * + * Bits 7..4: Reserved * + **************************************************************************** + * CMD_TEST: * + * * + * OUT: * + * offset 1: unused dummy value * + **************************************************************************** + */ + +#ifndef __MSGTYPES_H +#define __MSGTYPES_H + +/* + * Command IDs: + * + * Bits 7..6: Reserved, should always be zero + * Bits 5..0: Command ID. There are 62 usable IDs. Of this 63 available IDs, + * the IDs 0x00..0x1F are commands with variable payload size, + * the IDs 0x20..0x3F are commands with fixed payload size. + */ + +#define CMD_ID_MASK 0x3F + +/* Commands with variable payload size */ +#define CMD_SCAN_IN 0x00 +#define CMD_SLOW_SCAN_IN 0x01 +#define CMD_SCAN_OUT 0x02 +#define CMD_SLOW_SCAN_OUT 0x03 +#define CMD_SCAN_IO 0x04 +#define CMD_SLOW_SCAN_IO 0x05 + +/* Commands with fixed payload size */ +#define CMD_CLOCK_TMS 0x20 +#define CMD_SLOW_CLOCK_TMS 0x21 +#define CMD_CLOCK_TCK 0x22 +#define CMD_SLOW_CLOCK_TCK 0x23 +#define CMD_SLEEP_US 0x24 +#define CMD_SLEEP_MS 0x25 +#define CMD_GET_SIGNALS 0x26 +#define CMD_SET_SIGNALS 0x27 +#define CMD_CONFIGURE_TCK_FREQ 0x28 +#define CMD_SET_LEDS 0x29 +#define CMD_TEST 0x2A + +/* JTAG signal definition for jtag_get_signals() -- Input signals! */ +#define SIGNAL_TDO 1 + +/* JTAG signal definition for jtag_get_signals() -- Output signals! */ +#define SIGNAL_TDI 8 +#define SIGNAL_TMS 2 +#define SIGNAL_TCK 4 +#define SIGNAL_TRST 1 +#define SIGNAL_SRST 32 + +#endif diff --git a/src/jtag/drivers/arm-jtag-ew.c b/src/jtag/drivers/arm-jtag-ew.c index 02c51d41e1..9d8c592edb 100644 --- a/src/jtag/drivers/arm-jtag-ew.c +++ b/src/jtag/drivers/arm-jtag-ew.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Dimitar Dimitrov <dinuxbg@gmail.com> * @@ -42,10 +42,10 @@ static uint8_t usb_in_buffer[ARMJTAGEW_IN_BUFFER_SIZE]; static uint8_t usb_out_buffer[ARMJTAGEW_OUT_BUFFER_SIZE]; /* Queue command functions */ -static void armjtagew_end_state(tap_state_t state); +static void armjtagew_end_state(enum tap_state state); static void armjtagew_state_move(void); -static void armjtagew_path_move(int num_states, tap_state_t *path); -static void armjtagew_runtest(int num_cycles); +static void armjtagew_path_move(unsigned int num_states, enum tap_state *path); +static void armjtagew_runtest(unsigned int num_cycles); static void armjtagew_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, @@ -85,9 +85,9 @@ static struct armjtagew *armjtagew_handle; /************************************************************************** * External interface implementation */ -static int armjtagew_execute_queue(void) +static int armjtagew_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int scan_size; enum scan_type type; uint8_t *buffer; @@ -95,7 +95,7 @@ static int armjtagew_execute_queue(void) while (cmd) { switch (cmd->type) { case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %i", + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); @@ -111,7 +111,7 @@ static int armjtagew_execute_queue(void) break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %i", + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); @@ -213,7 +213,7 @@ static int armjtagew_init(void) armjtagew_handle = armjtagew_usb_open(); - if (armjtagew_handle == 0) { + if (!armjtagew_handle) { LOG_ERROR( "Cannot find ARM-JTAG-EW Interface! Please check connection and permissions."); return ERROR_JTAG_INIT_FAILED; @@ -253,7 +253,7 @@ static int armjtagew_quit(void) /************************************************************************** * Queue command implementations */ -static void armjtagew_end_state(tap_state_t state) +static void armjtagew_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -279,11 +279,9 @@ static void armjtagew_state_move(void) tap_set_state(tap_get_end_state()); } -static void armjtagew_path_move(int num_states, tap_state_t *path) +static void armjtagew_path_move(unsigned int num_states, enum tap_state *path) { - int i; - - for (i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { /* * TODO: The ARM-JTAG-EW hardware delays TDI with 3 TCK cycles when in RTCK mode. * Either handle that here, or update the documentation with examples @@ -305,11 +303,9 @@ static void armjtagew_path_move(int num_states, tap_state_t *path) tap_set_end_state(tap_get_state()); } -static void armjtagew_runtest(int num_cycles) +static void armjtagew_runtest(unsigned int num_cycles) { - int i; - - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -318,7 +314,7 @@ static void armjtagew_runtest(int num_cycles) } /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) armjtagew_tap_append_step(0, 0); /* finish in end_state */ @@ -333,7 +329,7 @@ static void armjtagew_scan(bool ir_scan, int scan_size, struct scan_command *command) { - tap_state_t saved_end_state; + enum tap_state saved_end_state; armjtagew_tap_ensure_space(1, scan_size + 8); @@ -490,7 +486,8 @@ static struct jtag_interface armjtagew_interface = { struct adapter_driver armjtagew_adapter_driver = { .name = "arm-jtag-ew", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = armjtagew_command_handlers, .init = armjtagew_init, @@ -677,7 +674,7 @@ static struct armjtagew *armjtagew_usb_open(void) const uint16_t pids[] = { USB_PID, 0 }; struct libusb_device_handle *dev; - if (jtag_libusb_open(vids, pids, &dev, NULL) != ERROR_OK) + if (jtag_libusb_open(vids, pids, NULL, &dev, NULL) != ERROR_OK) return NULL; struct armjtagew *result = malloc(sizeof(struct armjtagew)); @@ -776,17 +773,12 @@ static int armjtagew_usb_read(struct armjtagew *armjtagew, int exp_in_length) static void armjtagew_debug_buffer(uint8_t *buffer, int length) { - char line[81]; - char s[4]; - int i; - int j; + char line[8 + 3 * BYTES_PER_LINE + 1]; - for (i = 0; i < length; i += BYTES_PER_LINE) { - snprintf(line, 5, "%04x", i); - for (j = i; j < i + BYTES_PER_LINE && j < length; j++) { - snprintf(s, 4, " %02x", buffer[j]); - strcat(line, s); - } + for (int i = 0; i < length; i += BYTES_PER_LINE) { + int n = snprintf(line, 9, "%04x", i); + for (int j = i; j < i + BYTES_PER_LINE && j < length; j++) + n += snprintf(line + n, 4, " %02x", buffer[j]); LOG_DEBUG("%s", line); /* Prevent GDB timeout (writing to log might take some time) */ diff --git a/src/jtag/drivers/at91rm9200.c b/src/jtag/drivers/at91rm9200.c index cc61e9a223..ddcf857a6b 100644 --- a/src/jtag/drivers/at91rm9200.c +++ b/src/jtag/drivers/at91rm9200.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Anders Larsen * @@ -98,19 +98,19 @@ static uint32_t *pio_base; /* low level command set */ -static bb_value_t at91rm9200_read(void); +static enum bb_value at91rm9200_read(void); static int at91rm9200_write(int tck, int tms, int tdi); static int at91rm9200_init(void); static int at91rm9200_quit(void); -static struct bitbang_interface at91rm9200_bitbang = { +static const struct bitbang_interface at91rm9200_bitbang = { .read = at91rm9200_read, .write = at91rm9200_write, - .blink = 0 + .blink = NULL, }; -static bb_value_t at91rm9200_read(void) +static enum bb_value at91rm9200_read(void) { return (pio_base[device->TDO_PIO + PIO_PDSR] & device->TDO_MASK) ? BB_HIGH : BB_LOW; } @@ -157,8 +157,12 @@ COMMAND_HANDLER(at91rm9200_handle_device_command) return ERROR_COMMAND_SYNTAX_ERROR; /* only if the device name wasn't overwritten by cmdline */ - if (at91rm9200_device == 0) { + if (!at91rm9200_device) { at91rm9200_device = malloc(strlen(CMD_ARGV[0]) + sizeof(char)); + if (!at91rm9200_device) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } strcpy(at91rm9200_device, CMD_ARGV[0]); } @@ -182,7 +186,8 @@ static struct jtag_interface at91rm9200_interface = { struct adapter_driver at91rm9200_adapter_driver = { .name = "at91rm9200", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = at91rm9200_command_handlers, .init = at91rm9200_init, diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c index 11d9a8020c..1a105aac44 100644 --- a/src/jtag/drivers/bcm2835gpio.c +++ b/src/jtag/drivers/bcm2835gpio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Paul Fertser, fercerpav@gmail.com * @@ -12,296 +12,300 @@ #include "config.h" #endif +#include <jtag/adapter.h> #include <jtag/interface.h> #include <transport/transport.h> #include "bitbang.h" #include <sys/mman.h> -uint32_t bcm2835_peri_base = 0x20000000; +static char *bcm2835_peri_mem_dev; +static off_t bcm2835_peri_base = 0x20000000; #define BCM2835_GPIO_BASE (bcm2835_peri_base + 0x200000) /* GPIO controller */ #define BCM2835_PADS_GPIO_0_27 (bcm2835_peri_base + 0x100000) #define BCM2835_PADS_GPIO_0_27_OFFSET (0x2c / 4) -/* GPIO setup macros */ -#define MODE_GPIO(g) (*(pio_base+((g)/10))>>(((g)%10)*3) & 7) -#define INP_GPIO(g) do { *(pio_base+((g)/10)) &= ~(7<<(((g)%10)*3)); } while (0) -#define SET_MODE_GPIO(g, m) do { /* clear the mode bits first, then set as necessary */ \ - INP_GPIO(g); \ - *(pio_base+((g)/10)) |= ((m)<<(((g)%10)*3)); } while (0) -#define OUT_GPIO(g) SET_MODE_GPIO(g, 1) +/* See "GPIO Function Select Registers (GPFSELn)" in "Broadcom BCM2835 ARM Peripherals" datasheet. */ +#define BCM2835_GPIO_MODE_INPUT 0 +#define BCM2835_GPIO_MODE_OUTPUT 1 -#define GPIO_SET (*(pio_base+7)) /* sets bits which are 1, ignores bits which are 0 */ -#define GPIO_CLR (*(pio_base+10)) /* clears bits which are 1, ignores bits which are 0 */ -#define GPIO_LEV (*(pio_base+13)) /* current level of the pin */ +/* GPIO setup macros */ +#define MODE_GPIO(_g) ({ \ + typeof(_g) g = (_g); \ + *(pio_base + (g / 10)) >> ((g % 10) * 3) & 7; \ +}) -static int dev_mem_fd; -static volatile uint32_t *pio_base; +#define INP_GPIO(_g) do { \ + typeof(_g) g1 = (_g); \ + *(pio_base + (g1 / 10)) &= ~(7 << ((g1 % 10) * 3)); \ +} while (0) -static bb_value_t bcm2835gpio_read(void); -static int bcm2835gpio_write(int tck, int tms, int tdi); +#define SET_MODE_GPIO(_g, m) do { \ + typeof(_g) g = (_g); \ + /* clear the mode bits first, then set as necessary */ \ + INP_GPIO(g); \ + *(pio_base + (g / 10)) |= ((m) << ((g % 10) * 3)); \ +} while (0) -static int bcm2835_swdio_read(void); -static void bcm2835_swdio_drive(bool is_output); -static int bcm2835gpio_swd_write(int swclk, int swdio); +#define OUT_GPIO(g) SET_MODE_GPIO(g, BCM2835_GPIO_MODE_OUTPUT) -static int bcm2835gpio_init(void); -static int bcm2835gpio_quit(void); +#define GPIO_SET (*(pio_base + 7)) /* sets bits which are 1, ignores bits which are 0 */ +#define GPIO_CLR (*(pio_base + 10)) /* clears bits which are 1, ignores bits which are 0 */ +#define GPIO_LEV (*(pio_base + 13)) /* current level of the pin */ -static struct bitbang_interface bcm2835gpio_bitbang = { - .read = bcm2835gpio_read, - .write = bcm2835gpio_write, - .swdio_read = bcm2835_swdio_read, - .swdio_drive = bcm2835_swdio_drive, - .swd_write = bcm2835gpio_swd_write, - .blink = NULL -}; - -/* GPIO numbers for each signal. Negative values are invalid */ -static int tck_gpio = -1; -static int tck_gpio_mode; -static int tms_gpio = -1; -static int tms_gpio_mode; -static int tdi_gpio = -1; -static int tdi_gpio_mode; -static int tdo_gpio = -1; -static int tdo_gpio_mode; -static int trst_gpio = -1; -static int trst_gpio_mode; -static int srst_gpio = -1; -static int srst_gpio_mode; -static int swclk_gpio = -1; -static int swclk_gpio_mode; -static int swdio_gpio = -1; -static int swdio_gpio_mode; -static int swdio_dir_gpio = -1; -static int swdio_dir_gpio_mode; +static int dev_mem_fd; +static volatile uint32_t *pio_base = MAP_FAILED; +static volatile uint32_t *pads_base = MAP_FAILED; /* Transition delay coefficients */ static int speed_coeff = 113714; static int speed_offset = 28; static unsigned int jtag_delay; -static int is_gpio_valid(int gpio) -{ - return gpio >= 0 && gpio <= 31; -} +static const struct adapter_gpio_config *adapter_gpio_config; +static struct initial_gpio_state { + unsigned int mode; + unsigned int output_level; +} initial_gpio_state[ADAPTER_GPIO_IDX_NUM]; +static uint32_t initial_drive_strength_etc; -static bb_value_t bcm2835gpio_read(void) +static inline const char *bcm2835_get_mem_dev(void) { - return (GPIO_LEV & 1<<tdo_gpio) ? BB_HIGH : BB_LOW; + if (bcm2835_peri_mem_dev) + return bcm2835_peri_mem_dev; + + return "/dev/gpiomem"; } -static int bcm2835gpio_write(int tck, int tms, int tdi) +static inline void bcm2835_gpio_synchronize(void) { - uint32_t set = tck<<tck_gpio | tms<<tms_gpio | tdi<<tdi_gpio; - uint32_t clear = !tck<<tck_gpio | !tms<<tms_gpio | !tdi<<tdi_gpio; - - GPIO_SET = set; - GPIO_CLR = clear; - - for (unsigned int i = 0; i < jtag_delay; i++) - asm volatile (""); - - return ERROR_OK; + /* Ensure that previous writes to GPIO registers are flushed out of + * the inner shareable domain to prevent pipelined writes to the + * same address being merged. + */ + __sync_synchronize(); } -static int bcm2835gpio_swd_write(int swclk, int swdio) +static inline void bcm2835_delay(void) { - uint32_t set = swclk << swclk_gpio | swdio << swdio_gpio; - uint32_t clear = !swclk << swclk_gpio | !swdio << swdio_gpio; - - GPIO_SET = set; - GPIO_CLR = clear; - for (unsigned int i = 0; i < jtag_delay; i++) asm volatile (""); - - return ERROR_OK; } -/* (1) assert or (0) deassert reset lines */ -static int bcm2835gpio_reset(int trst, int srst) +static bool is_gpio_config_valid(enum adapter_gpio_config_index idx) { - uint32_t set = 0; - uint32_t clear = 0; - - if (is_gpio_valid(trst_gpio)) { - set |= !trst<<trst_gpio; - clear |= trst<<trst_gpio; - } - - if (is_gpio_valid(srst_gpio)) { - set |= !srst<<srst_gpio; - clear |= srst<<srst_gpio; - } - - GPIO_SET = set; - GPIO_CLR = clear; - - return ERROR_OK; + /* Only chip 0 is supported, accept unset value (-1) too */ + return adapter_gpio_config[idx].gpio_num <= 31; } -static void bcm2835_swdio_drive(bool is_output) +static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int value) { - if (is_gpio_valid(swdio_dir_gpio)) { - if (is_output) { - GPIO_SET = 1 << swdio_dir_gpio; - OUT_GPIO(swdio_gpio); + value = value ^ (gpio_config->active_low ? 1 : 0); + switch (gpio_config->drive) { + case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL: + if (value) + GPIO_SET = 1 << gpio_config->gpio_num; + else + GPIO_CLR = 1 << gpio_config->gpio_num; + /* For performance reasons assume the GPIO is already set as an output + * and therefore the call can be omitted here. + */ + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN: + if (value) { + INP_GPIO(gpio_config->gpio_num); } else { - INP_GPIO(swdio_gpio); - GPIO_CLR = 1 << swdio_dir_gpio; + GPIO_CLR = 1 << gpio_config->gpio_num; + OUT_GPIO(gpio_config->gpio_num); } - } else { - if (is_output) - OUT_GPIO(swdio_gpio); - else - INP_GPIO(swdio_gpio); + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE: + if (value) { + GPIO_SET = 1 << gpio_config->gpio_num; + OUT_GPIO(gpio_config->gpio_num); + } else { + INP_GPIO(gpio_config->gpio_num); + } + break; } + bcm2835_gpio_synchronize(); } -static int bcm2835_swdio_read(void) +static void restore_gpio(enum adapter_gpio_config_index idx) { - return !!(GPIO_LEV & 1 << swdio_gpio); + if (is_gpio_config_valid(idx)) { + SET_MODE_GPIO(adapter_gpio_config[idx].gpio_num, initial_gpio_state[idx].mode); + if (initial_gpio_state[idx].mode == BCM2835_GPIO_MODE_OUTPUT) { + if (initial_gpio_state[idx].output_level) + GPIO_SET = 1 << adapter_gpio_config[idx].gpio_num; + else + GPIO_CLR = 1 << adapter_gpio_config[idx].gpio_num; + } + } + bcm2835_gpio_synchronize(); } -static int bcm2835gpio_khz(int khz, int *jtag_speed) +static void initialize_gpio(enum adapter_gpio_config_index idx) { - if (!khz) { - LOG_DEBUG("RCLK not supported"); - return ERROR_FAIL; + if (!is_gpio_config_valid(idx)) + return; + + initial_gpio_state[idx].mode = MODE_GPIO(adapter_gpio_config[idx].gpio_num); + unsigned int shift = adapter_gpio_config[idx].gpio_num; + initial_gpio_state[idx].output_level = (GPIO_LEV >> shift) & 1; + LOG_DEBUG("saved GPIO mode for %s (GPIO %d %d): %d", + adapter_gpio_get_name(idx), adapter_gpio_config[idx].chip_num, adapter_gpio_config[idx].gpio_num, + initial_gpio_state[idx].mode); + + if (adapter_gpio_config[idx].pull != ADAPTER_GPIO_PULL_NONE) { + LOG_WARNING("BCM2835 GPIO does not support pull-up or pull-down settings (signal %s)", + adapter_gpio_get_name(idx)); } - *jtag_speed = speed_coeff/khz - speed_offset; - if (*jtag_speed < 0) - *jtag_speed = 0; - return ERROR_OK; -} -static int bcm2835gpio_speed_div(int speed, int *khz) -{ - *khz = speed_coeff/(speed + speed_offset); - return ERROR_OK; -} + switch (adapter_gpio_config[idx].init_state) { + case ADAPTER_GPIO_INIT_STATE_INACTIVE: + set_gpio_value(&adapter_gpio_config[idx], 0); + break; + case ADAPTER_GPIO_INIT_STATE_ACTIVE: + set_gpio_value(&adapter_gpio_config[idx], 1); + break; + case ADAPTER_GPIO_INIT_STATE_INPUT: + INP_GPIO(adapter_gpio_config[idx].gpio_num); + break; + } -static int bcm2835gpio_speed(int speed) -{ - jtag_delay = speed; - return ERROR_OK; + /* Direction for non push-pull is already set by set_gpio_value() */ + if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL + && adapter_gpio_config[idx].init_state != ADAPTER_GPIO_INIT_STATE_INPUT) + OUT_GPIO(adapter_gpio_config[idx].gpio_num); + bcm2835_gpio_synchronize(); } -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionums) +static enum bb_value bcm2835gpio_read(void) { - if (CMD_ARGC == 4) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(CMD, - "BCM2835 GPIO config: tck = %d, tms = %d, tdi = %d, tdo = %d", - tck_gpio, tms_gpio, tdi_gpio, tdo_gpio); - - return ERROR_OK; + unsigned int shift = adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].gpio_num; + uint32_t value = (GPIO_LEV >> shift) & 1; + return value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].active_low ? BB_HIGH : BB_LOW); } -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tck) +static int bcm2835gpio_write(int tck, int tms, int tdi) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio); + uint32_t set = tck << adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num | + tms << adapter_gpio_config[ADAPTER_GPIO_IDX_TMS].gpio_num | + tdi << adapter_gpio_config[ADAPTER_GPIO_IDX_TDI].gpio_num; + uint32_t clear = !tck << adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num | + !tms << adapter_gpio_config[ADAPTER_GPIO_IDX_TMS].gpio_num | + !tdi << adapter_gpio_config[ADAPTER_GPIO_IDX_TDI].gpio_num; - command_print(CMD, "BCM2835 GPIO config: tck = %d", tck_gpio); - return ERROR_OK; -} + GPIO_SET = set; + GPIO_CLR = clear; + bcm2835_gpio_synchronize(); -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tms) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio); + bcm2835_delay(); - command_print(CMD, "BCM2835 GPIO config: tms = %d", tms_gpio); return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdo) +/* Requires push-pull drive mode for swclk and swdio */ +static int bcm2835gpio_swd_write_fast(int swclk, int swdio) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio); + swclk = swclk ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].active_low ? 1 : 0); + swdio = swdio ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0); - command_print(CMD, "BCM2835 GPIO config: tdo = %d", tdo_gpio); - return ERROR_OK; -} + uint32_t set = swclk << adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num | + swdio << adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num; + uint32_t clear = !swclk << adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num | + !swdio << adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num; -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdi) -{ - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio); + GPIO_SET = set; + GPIO_CLR = clear; + bcm2835_gpio_synchronize(); + + bcm2835_delay(); - command_print(CMD, "BCM2835 GPIO config: tdi = %d", tdi_gpio); return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_srst) +/* Generic mode that works for open-drain/open-source drive modes, but slower */ +static int bcm2835gpio_swd_write_generic(int swclk, int swdio) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio); + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO], swdio); + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK], swclk); /* Write clock last */ + + bcm2835_delay(); - command_print(CMD, "BCM2835 GPIO config: srst = %d", srst_gpio); return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_trst) +/* (1) assert or (0) deassert reset lines */ +static int bcm2835gpio_reset(int trst, int srst) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio); - - command_print(CMD, "BCM2835 GPIO config: trst = %d", trst_gpio); + /* As the "adapter reset_config" command keeps the srst and trst gpio drive + * mode settings in sync we can use our standard set_gpio_value() function + * that honours drive mode and active low. + */ + if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SRST)) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST], srst); + + if (is_gpio_config_valid(ADAPTER_GPIO_IDX_TRST)) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST], trst); + + LOG_DEBUG("trst %d gpio: %d %d, srst %d gpio: %d %d", + trst, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].chip_num, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].gpio_num, + srst, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].chip_num, + (int)adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].gpio_num); return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionums) +static void bcm2835_swdio_drive(bool is_output) { - if (CMD_ARGC == 2) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; + if (is_output) { + if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR)) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 1); + OUT_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num); + } else { + INP_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num); + if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR)) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0); } - - command_print(CMD, - "BCM2835 GPIO nums: swclk = %d, swdio = %d", - swclk_gpio, swdio_gpio); - - return ERROR_OK; + bcm2835_gpio_synchronize(); } -COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionum_swclk) +static int bcm2835_swdio_read(void) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio); + unsigned int shift = adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num; + uint32_t value = (GPIO_LEV >> shift) & 1; + return value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0); +} - command_print(CMD, "BCM2835 num: swclk = %d", swclk_gpio); +static int bcm2835gpio_khz(int khz, int *jtag_speed) +{ + if (!khz) { + LOG_DEBUG("BCM2835 GPIO: RCLK not supported"); + return ERROR_FAIL; + } + *jtag_speed = DIV_ROUND_UP(speed_coeff, khz) - speed_offset; + LOG_DEBUG("jtag_delay %d", *jtag_speed); + if (*jtag_speed < 0) + *jtag_speed = 0; return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionum_swdio) +static int bcm2835gpio_speed_div(int speed, int *khz) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio); - - command_print(CMD, "BCM2835 num: swdio = %d", swdio_gpio); + int divisor = speed + speed_offset; + /* divide with roundig to the closest */ + *khz = (speed_coeff + divisor / 2) / divisor; return ERROR_OK; } -COMMAND_HANDLER(bcm2835gpio_handle_swd_dir_gpionum_swdio) +static int bcm2835gpio_speed(int speed) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_dir_gpio); - - command_print(CMD, "BCM2835 num: swdio_dir = %d", swdio_dir_gpio); + jtag_delay = speed; return ERROR_OK; } @@ -317,94 +321,33 @@ COMMAND_HANDLER(bcm2835gpio_handle_speed_coeffs) return ERROR_OK; } +COMMAND_HANDLER(bcm2835gpio_handle_peripheral_mem_dev) +{ + if (CMD_ARGC == 1) { + free(bcm2835_peri_mem_dev); + bcm2835_peri_mem_dev = strdup(CMD_ARGV[0]); + } + + command_print(CMD, "BCM2835 GPIO: peripheral_mem_dev = %s", + bcm2835_get_mem_dev()); + return ERROR_OK; +} + COMMAND_HANDLER(bcm2835gpio_handle_peripheral_base) { - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bcm2835_peri_base); + uint64_t tmp_base; + if (CMD_ARGC == 1) { + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], tmp_base); + bcm2835_peri_base = (off_t)tmp_base; + } - command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08x", - bcm2835_peri_base); + tmp_base = bcm2835_peri_base; + command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08" PRIx64, + tmp_base); return ERROR_OK; } static const struct command_registration bcm2835gpio_subcommand_handlers[] = { - { - .name = "jtag_nums", - .handler = &bcm2835gpio_handle_jtag_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for tck, tms, tdi, tdo. (in that order)", - .usage = "[tck tms tdi tdo]", - }, - { - .name = "tck_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_tck, - .mode = COMMAND_CONFIG, - .help = "gpio number for tck.", - .usage = "[tck]", - }, - { - .name = "tms_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_tms, - .mode = COMMAND_CONFIG, - .help = "gpio number for tms.", - .usage = "[tms]", - }, - { - .name = "tdo_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_tdo, - .mode = COMMAND_CONFIG, - .help = "gpio number for tdo.", - .usage = "[tdo]", - }, - { - .name = "tdi_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_tdi, - .mode = COMMAND_CONFIG, - .help = "gpio number for tdi.", - .usage = "[tdi]", - }, - { - .name = "swd_nums", - .handler = &bcm2835gpio_handle_swd_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for swclk, swdio. (in that order)", - .usage = "[swclk swdio]", - }, - { - .name = "swclk_num", - .handler = &bcm2835gpio_handle_swd_gpionum_swclk, - .mode = COMMAND_CONFIG, - .help = "gpio number for swclk.", - .usage = "[swclk]", - }, - { - .name = "swdio_num", - .handler = &bcm2835gpio_handle_swd_gpionum_swdio, - .mode = COMMAND_CONFIG, - .help = "gpio number for swdio.", - .usage = "[swdio]", - }, - { - .name = "swdio_dir_num", - .handler = &bcm2835gpio_handle_swd_dir_gpionum_swdio, - .mode = COMMAND_CONFIG, - .help = "gpio number for swdio direction control pin (set=output mode, clear=input mode)", - .usage = "[swdio_dir]", - }, - { - .name = "srst_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_srst, - .mode = COMMAND_CONFIG, - .help = "gpio number for srst.", - .usage = "[srst]", - }, - { - .name = "trst_num", - .handler = &bcm2835gpio_handle_jtag_gpionum_trst, - .mode = COMMAND_CONFIG, - .help = "gpio number for trst.", - .usage = "[trst]", - }, { .name = "speed_coeffs", .handler = &bcm2835gpio_handle_speed_coeffs, @@ -412,11 +355,18 @@ static const struct command_registration bcm2835gpio_subcommand_handlers[] = { .help = "SPEED_COEFF and SPEED_OFFSET for delay calculations.", .usage = "[SPEED_COEFF SPEED_OFFSET]", }, + { + .name = "peripheral_mem_dev", + .handler = &bcm2835gpio_handle_peripheral_mem_dev, + .mode = COMMAND_CONFIG, + .help = "device to map memory mapped GPIOs from.", + .usage = "[device]", + }, { .name = "peripheral_base", .handler = &bcm2835gpio_handle_peripheral_base, .mode = COMMAND_CONFIG, - .help = "peripheral base to access GPIOs (RPi1 0x20000000, RPi2 0x3F000000).", + .help = "peripheral base to access GPIOs, not needed with /dev/gpiomem.", .usage = "[base]", }, @@ -434,57 +384,73 @@ static const struct command_registration bcm2835gpio_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static const char * const bcm2835_transports[] = { "jtag", "swd", NULL }; - -static struct jtag_interface bcm2835gpio_interface = { - .supported = DEBUG_CAP_TMS_SEQ, - .execute_queue = bitbang_execute_queue, -}; - -struct adapter_driver bcm2835gpio_adapter_driver = { - .name = "bcm2835gpio", - .transports = bcm2835_transports, - .commands = bcm2835gpio_command_handlers, - - .init = bcm2835gpio_init, - .quit = bcm2835gpio_quit, - .reset = bcm2835gpio_reset, - .speed = bcm2835gpio_speed, - .khz = bcm2835gpio_khz, - .speed_div = bcm2835gpio_speed_div, - - .jtag_ops = &bcm2835gpio_interface, - .swd_ops = &bitbang_swd, -}; - static bool bcm2835gpio_jtag_mode_possible(void) { - if (!is_gpio_valid(tck_gpio)) - return 0; - if (!is_gpio_valid(tms_gpio)) - return 0; - if (!is_gpio_valid(tdi_gpio)) - return 0; - if (!is_gpio_valid(tdo_gpio)) - return 0; - return 1; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TCK)) + return false; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TMS)) + return false; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDI)) + return false; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDO)) + return false; + return true; } static bool bcm2835gpio_swd_mode_possible(void) { - if (!is_gpio_valid(swclk_gpio)) - return 0; - if (!is_gpio_valid(swdio_gpio)) - return 0; - return 1; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWCLK)) + return false; + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO)) + return false; + return true; } -static int bcm2835gpio_init(void) +static void bcm2835gpio_munmap(void) { - bitbang_interface = &bcm2835gpio_bitbang; + if (pio_base != MAP_FAILED) { + munmap((void *)pio_base, sysconf(_SC_PAGE_SIZE)); + pio_base = MAP_FAILED; + } + + if (pads_base != MAP_FAILED) { + munmap((void *)pads_base, sysconf(_SC_PAGE_SIZE)); + pads_base = MAP_FAILED; + } +} + +static int bcm2835gpio_blink(bool on) +{ + if (is_gpio_config_valid(ADAPTER_GPIO_IDX_LED)) + set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED], on ? 1 : 0); + + return ERROR_OK; +} + +static const struct bitbang_interface bcm2835gpio_bitbang_swd_write_generic = { + .read = bcm2835gpio_read, + .write = bcm2835gpio_write, + .swdio_read = bcm2835_swdio_read, + .swdio_drive = bcm2835_swdio_drive, + .swd_write = bcm2835gpio_swd_write_generic, + .blink = bcm2835gpio_blink, +}; +static const struct bitbang_interface bcm2835gpio_bitbang_swd_write_fast = { + .read = bcm2835gpio_read, + .write = bcm2835gpio_write, + .swdio_read = bcm2835_swdio_read, + .swdio_drive = bcm2835_swdio_drive, + .swd_write = bcm2835gpio_swd_write_fast, + .blink = bcm2835gpio_blink, +}; + +static int bcm2835gpio_init(void) +{ LOG_INFO("BCM2835 GPIO JTAG/SWD bitbang driver"); + adapter_gpio_config = adapter_gpio_get_config(); + if (transport_is_jtag() && !bcm2835gpio_jtag_mode_possible()) { LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode"); return ERROR_JTAG_INIT_FAILED; @@ -495,13 +461,16 @@ static int bcm2835gpio_init(void) return ERROR_JTAG_INIT_FAILED; } - dev_mem_fd = open("/dev/gpiomem", O_RDWR | O_SYNC); - if (dev_mem_fd < 0) { - LOG_DEBUG("Cannot open /dev/gpiomem, fallback to /dev/mem"); - dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC); - } + bool is_gpiomem = strcmp(bcm2835_get_mem_dev(), "/dev/gpiomem") == 0; + bool pad_mapping_possible = !is_gpiomem; + + dev_mem_fd = open(bcm2835_get_mem_dev(), O_RDWR | O_SYNC); if (dev_mem_fd < 0) { - LOG_ERROR("open: %s", strerror(errno)); + LOG_ERROR("open %s: %s", bcm2835_get_mem_dev(), strerror(errno)); + /* TODO: add /dev/mem specific doc and refer to it + * if (!is_gpiomem && (errno == EACCES || errno == EPERM)) + * LOG_INFO("Consult the user's guide chapter 4.? how to set permissions and capabilities"); + */ return ERROR_JTAG_INIT_FAILED; } @@ -514,71 +483,73 @@ static int bcm2835gpio_init(void) return ERROR_JTAG_INIT_FAILED; } - static volatile uint32_t *pads_base; - pads_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE, + /* TODO: move pads config to a separate utility */ + if (pad_mapping_possible) { + pads_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE, MAP_SHARED, dev_mem_fd, BCM2835_PADS_GPIO_0_27); - if (pads_base == MAP_FAILED) { - LOG_ERROR("mmap: %s", strerror(errno)); - close(dev_mem_fd); - return ERROR_JTAG_INIT_FAILED; + if (pads_base == MAP_FAILED) { + LOG_ERROR("mmap pads: %s", strerror(errno)); + LOG_WARNING("Continuing with unchanged GPIO pad settings (drive strength and slew rate)"); + } + } else { + pads_base = MAP_FAILED; } - /* set 4mA drive strength, slew rate limited, hysteresis on */ - pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5a000008 + 1; + close(dev_mem_fd); + + if (pads_base != MAP_FAILED) { + /* set 4mA drive strength, slew rate limited, hysteresis on */ + initial_drive_strength_etc = pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] & 0x1f; +LOG_INFO("initial pads conf %08x", pads_base[BCM2835_PADS_GPIO_0_27_OFFSET]); + pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5a000008 + 1; +LOG_INFO("pads conf set to %08x", pads_base[BCM2835_PADS_GPIO_0_27_OFFSET]); + } - /* - * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST - * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high. + /* Configure JTAG/SWD signals. Default directions and initial states are handled + * by adapter.c and "adapter gpio" command. */ if (transport_is_jtag()) { - tdo_gpio_mode = MODE_GPIO(tdo_gpio); - tdi_gpio_mode = MODE_GPIO(tdi_gpio); - tck_gpio_mode = MODE_GPIO(tck_gpio); - tms_gpio_mode = MODE_GPIO(tms_gpio); - - INP_GPIO(tdo_gpio); - - GPIO_CLR = 1<<tdi_gpio | 1<<tck_gpio; - GPIO_SET = 1<<tms_gpio; - - OUT_GPIO(tdi_gpio); - OUT_GPIO(tck_gpio); - OUT_GPIO(tms_gpio); - - if (is_gpio_valid(trst_gpio)) { - trst_gpio_mode = MODE_GPIO(trst_gpio); - GPIO_SET = 1 << trst_gpio; - OUT_GPIO(trst_gpio); - } + initialize_gpio(ADAPTER_GPIO_IDX_TDO); + initialize_gpio(ADAPTER_GPIO_IDX_TDI); + initialize_gpio(ADAPTER_GPIO_IDX_TMS); + initialize_gpio(ADAPTER_GPIO_IDX_TCK); + initialize_gpio(ADAPTER_GPIO_IDX_TRST); } + const struct bitbang_interface *bcm2835gpio_bitbang = &bcm2835gpio_bitbang_swd_write_generic; + if (transport_is_swd()) { - /* Make buffer an output before the GPIO connected to it */ - if (is_gpio_valid(swdio_dir_gpio)) { - swdio_dir_gpio_mode = MODE_GPIO(swdio_dir_gpio); - GPIO_SET = 1 << swdio_dir_gpio; - OUT_GPIO(swdio_dir_gpio); + /* swdio and its buffer should be initialized in the order that prevents + * two outputs from being connected together. This will occur if the + * swdio GPIO of the AM335x is configured as an output while its + * external buffer is configured to send the swdio signal from the + * target to the AM335x. + */ + if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) { + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO); + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + } else { + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + initialize_gpio(ADAPTER_GPIO_IDX_SWDIO); } - swclk_gpio_mode = MODE_GPIO(swclk_gpio); - swdio_gpio_mode = MODE_GPIO(swdio_gpio); + initialize_gpio(ADAPTER_GPIO_IDX_SWCLK); - GPIO_CLR = 1<<swdio_gpio | 1<<swclk_gpio; - - OUT_GPIO(swclk_gpio); - OUT_GPIO(swdio_gpio); + if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL && + adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL) { + LOG_DEBUG("BCM2835 GPIO using fast mode for SWD write"); + bcm2835gpio_bitbang = &bcm2835gpio_bitbang_swd_write_fast; + } else { + LOG_DEBUG("BCM2835 GPIO using generic mode for SWD write"); + assert(bcm2835gpio_bitbang == &bcm2835gpio_bitbang_swd_write_generic); + } } - if (is_gpio_valid(srst_gpio)) { - srst_gpio_mode = MODE_GPIO(srst_gpio); - GPIO_SET = 1 << srst_gpio; - OUT_GPIO(srst_gpio); - } + initialize_gpio(ADAPTER_GPIO_IDX_SRST); + initialize_gpio(ADAPTER_GPIO_IDX_LED); - LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d " - "tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode, - tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode); + bitbang_interface = bcm2835gpio_bitbang; return ERROR_OK; } @@ -586,24 +557,56 @@ static int bcm2835gpio_init(void) static int bcm2835gpio_quit(void) { if (transport_is_jtag()) { - SET_MODE_GPIO(tdo_gpio, tdo_gpio_mode); - SET_MODE_GPIO(tdi_gpio, tdi_gpio_mode); - SET_MODE_GPIO(tck_gpio, tck_gpio_mode); - SET_MODE_GPIO(tms_gpio, tms_gpio_mode); - if (is_gpio_valid(trst_gpio)) - SET_MODE_GPIO(trst_gpio, trst_gpio_mode); + restore_gpio(ADAPTER_GPIO_IDX_TDO); + restore_gpio(ADAPTER_GPIO_IDX_TDI); + restore_gpio(ADAPTER_GPIO_IDX_TCK); + restore_gpio(ADAPTER_GPIO_IDX_TMS); + restore_gpio(ADAPTER_GPIO_IDX_TRST); } if (transport_is_swd()) { - SET_MODE_GPIO(swclk_gpio, swclk_gpio_mode); - SET_MODE_GPIO(swdio_gpio, swdio_gpio_mode); + /* Restore swdio/swdio_dir to their initial modes, even if that means + * connecting two outputs. Begin by making swdio an input so that the + * current and final states of swdio and swdio_dir do not have to be + * considered to calculate the safe restoration order. + */ + INP_GPIO(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num); + restore_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR); + restore_gpio(ADAPTER_GPIO_IDX_SWDIO); + restore_gpio(ADAPTER_GPIO_IDX_SWCLK); } - if (is_gpio_valid(srst_gpio)) - SET_MODE_GPIO(srst_gpio, srst_gpio_mode); + restore_gpio(ADAPTER_GPIO_IDX_SRST); + restore_gpio(ADAPTER_GPIO_IDX_LED); - if (is_gpio_valid(swdio_dir_gpio)) - SET_MODE_GPIO(swdio_dir_gpio, swdio_dir_gpio_mode); + if (pads_base != MAP_FAILED) { + /* Restore drive strength. MSB is password ("5A") */ + pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5A000000 | initial_drive_strength_etc; + } + bcm2835gpio_munmap(); + free(bcm2835_peri_mem_dev); return ERROR_OK; } + + +static struct jtag_interface bcm2835gpio_interface = { + .supported = DEBUG_CAP_TMS_SEQ, + .execute_queue = bitbang_execute_queue, +}; +struct adapter_driver bcm2835gpio_adapter_driver = { + .name = "bcm2835gpio", + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, + .commands = bcm2835gpio_command_handlers, + + .init = bcm2835gpio_init, + .quit = bcm2835gpio_quit, + .reset = bcm2835gpio_reset, + .speed = bcm2835gpio_speed, + .khz = bcm2835gpio_khz, + .speed_div = bcm2835gpio_speed_div, + + .jtag_ops = &bcm2835gpio_interface, + .swd_ops = &bitbang_swd, +}; diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c index 0b2783acac..c2e763ddb3 100644 --- a/src/jtag/drivers/bitbang.c +++ b/src/jtag/drivers/bitbang.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -15,10 +15,16 @@ #include "config.h" #endif +#include <jtag/jtag.h> /* Added to avoid include loop in commands.h */ #include "bitbang.h" #include <jtag/interface.h> #include <jtag/commands.h> +#include <helper/time_support.h> + +/* Timeout for retrying on SWD WAIT in msec */ +#define SWD_WAIT_TIMEOUT 500 + /** * Function bitbang_stableclocks * issues a number of clock cycles while staying in a stable state. @@ -27,11 +33,11 @@ * this function checks the current stable state to decide on the value of TMS * to use. */ -static int bitbang_stableclocks(int num_cycles); +static int bitbang_stableclocks(unsigned int num_cycles); static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk); -struct bitbang_interface *bitbang_interface; +const struct bitbang_interface *bitbang_interface; /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work! * @@ -54,7 +60,7 @@ struct bitbang_interface *bitbang_interface; #define CLOCK_IDLE() 0 /* The bitbang driver leaves the TCK 0 when in idle */ -static void bitbang_end_state(tap_state_t state) +static void bitbang_end_state(enum tap_state state) { assert(tap_is_state_stable(state)); tap_set_end_state(state); @@ -86,13 +92,13 @@ static int bitbang_state_move(int skip) */ static int bitbang_execute_tms(struct jtag_command *cmd) { - unsigned num_bits = cmd->cmd.tms->num_bits; + unsigned int num_bits = cmd->cmd.tms->num_bits; const uint8_t *bits = cmd->cmd.tms->bits; - LOG_DEBUG_IO("TMS: %d bits", num_bits); + LOG_DEBUG_IO("TMS: %u bits", num_bits); int tms = 0; - for (unsigned i = 0; i < num_bits; i++) { + for (unsigned int i = 0; i < num_bits; i++) { tms = ((bits[i/8] >> (i % 8)) & 1); if (bitbang_interface->write(0, tms, 0) != ERROR_OK) return ERROR_FAIL; @@ -107,7 +113,7 @@ static int bitbang_execute_tms(struct jtag_command *cmd) static int bitbang_path_move(struct pathmove_command *cmd) { - int num_states = cmd->num_states; + unsigned int num_states = cmd->num_states; int state_count; int tms = 0; @@ -141,11 +147,9 @@ static int bitbang_path_move(struct pathmove_command *cmd) return ERROR_OK; } -static int bitbang_runtest(int num_cycles) +static int bitbang_runtest(unsigned int num_cycles) { - int i; - - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -155,7 +159,7 @@ static int bitbang_runtest(int num_cycles) } /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { if (bitbang_interface->write(0, 0, 0) != ERROR_OK) return ERROR_FAIL; if (bitbang_interface->write(1, 0, 0) != ERROR_OK) @@ -173,13 +177,12 @@ static int bitbang_runtest(int num_cycles) return ERROR_OK; } -static int bitbang_stableclocks(int num_cycles) +static int bitbang_stableclocks(unsigned int num_cycles) { int tms = (tap_get_state() == TAP_RESET ? 1 : 0); - int i; /* send num_cycles clocks onto the cable */ - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { if (bitbang_interface->write(1, tms, 0) != ERROR_OK) return ERROR_FAIL; if (bitbang_interface->write(0, tms, 0) != ERROR_OK) @@ -190,10 +193,10 @@ static int bitbang_stableclocks(int num_cycles) } static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, - unsigned scan_size) + unsigned int scan_size) { - tap_state_t saved_end_state = tap_get_end_state(); - unsigned bit_cnt; + enum tap_state saved_end_state = tap_get_end_state(); + unsigned int bit_cnt; if (!((!ir_scan && (tap_get_state() == TAP_DRSHIFT)) || @@ -251,7 +254,7 @@ static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, if (type != SCAN_OUT && bitbang_interface->buf_size && (buffered == bitbang_interface->buf_size || bit_cnt == scan_size - 1)) { - for (unsigned i = bit_cnt + 1 - buffered; i <= bit_cnt; i++) { + for (unsigned int i = bit_cnt + 1 - buffered; i <= bit_cnt; i++) { switch (bitbang_interface->read_sample()) { case BB_LOW: buffer[i/8] &= ~(1 << (i % 8)); @@ -278,9 +281,18 @@ static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, return ERROR_OK; } -int bitbang_execute_queue(void) +static void bitbang_sleep(unsigned int microseconds) +{ + if (bitbang_interface->sleep) { + bitbang_interface->sleep(microseconds); + } else { + jtag_sleep(microseconds); + } +} + +int bitbang_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -297,14 +309,14 @@ int bitbang_execute_queue(void) retval = ERROR_OK; if (bitbang_interface->blink) { - if (bitbang_interface->blink(1) != ERROR_OK) + if (bitbang_interface->blink(true) != ERROR_OK) return ERROR_FAIL; } while (cmd) { switch (cmd->type) { case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %s", + LOG_DEBUG_IO("runtest %u cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state)); bitbang_end_state(cmd->cmd.runtest->end_state); @@ -328,7 +340,7 @@ int bitbang_execute_queue(void) return ERROR_FAIL; break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %s", + LOG_DEBUG_IO("pathmove: %u states, end in %s", cmd->cmd.pathmove->num_states, tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1])); if (bitbang_path_move(cmd->cmd.pathmove) != ERROR_OK) @@ -351,7 +363,9 @@ int bitbang_execute_queue(void) break; case JTAG_SLEEP: LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us); - jtag_sleep(cmd->cmd.sleep->us); + if (bitbang_interface->flush && (bitbang_interface->flush() != ERROR_OK)) + return ERROR_FAIL; + bitbang_sleep(cmd->cmd.sleep->us); break; case JTAG_TMS: retval = bitbang_execute_tms(cmd); @@ -363,7 +377,7 @@ int bitbang_execute_queue(void) cmd = cmd->next; } if (bitbang_interface->blink) { - if (bitbang_interface->blink(0) != ERROR_OK) + if (bitbang_interface->blink(false) != ERROR_OK) return ERROR_FAIL; } @@ -380,11 +394,9 @@ static int bitbang_swd_init(void) static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt) { - LOG_DEBUG("bitbang_swd_exchange"); - if (bitbang_interface->blink) { /* FIXME: we should manage errors */ - bitbang_interface->blink(1); + bitbang_interface->blink(true); } for (unsigned int i = offset; i < bit_cnt + offset; i++) { @@ -406,17 +418,15 @@ static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, u if (bitbang_interface->blink) { /* FIXME: we should manage errors */ - bitbang_interface->blink(0); + bitbang_interface->blink(false); } } static int bitbang_swd_switch_seq(enum swd_special_seq seq) { - LOG_DEBUG("bitbang_swd_switch_seq"); - switch (seq) { case LINE_RESET: - LOG_DEBUG("SWD line reset"); + LOG_DEBUG_IO("SWD line reset"); bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len); break; case JTAG_TO_SWD: @@ -459,7 +469,6 @@ static void swd_clear_sticky_errors(void) static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { - LOG_DEBUG("bitbang_swd_read_reg"); assert(cmd & SWD_CMD_RNW); if (queued_retval != ERROR_OK) { @@ -467,7 +476,8 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay return; } - for (;;) { + int64_t timeout = timeval_ms() + SWD_WAIT_TIMEOUT; + for (unsigned int retry = 0;; retry++) { uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)]; cmd |= SWD_CMD_START | SWD_CMD_PARK; @@ -481,16 +491,25 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32); int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1); - LOG_DEBUG("%s %s read reg %X = %08"PRIx32, - ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APNDP ? "AP" : "DP", - (cmd & SWD_CMD_A32) >> 1, - data); + LOG_CUSTOM_LEVEL((ack != SWD_ACK_OK && (retry == 0 || ack != SWD_ACK_WAIT)) + ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO, + "%s %s read reg %X = %08" PRIx32, + ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + (cmd & SWD_CMD_A32) >> 1, + data); - if (ack == SWD_ACK_WAIT) { + if (ack == SWD_ACK_WAIT && timeval_ms() <= timeout) { swd_clear_sticky_errors(); + if (retry > 20) + alive_sleep(1); + continue; - } else if (ack != SWD_ACK_OK) { + } + if (retry > 1) + LOG_DEBUG("SWD WAIT: retried %u times", retry); + + if (ack != SWD_ACK_OK) { queued_retval = swd_ack_to_error_code(ack); return; } @@ -510,7 +529,6 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { - LOG_DEBUG("bitbang_swd_write_reg"); assert(!(cmd & SWD_CMD_RNW)); if (queued_retval != ERROR_OK) { @@ -518,12 +536,14 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay return; } + int64_t timeout = timeval_ms() + SWD_WAIT_TIMEOUT; + /* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */ bool check_ack = swd_cmd_returns_ack(cmd); /* init the array to silence scan-build */ uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)] = {0}; - for (;;) { + for (unsigned int retry = 0;; retry++) { buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value); buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value)); @@ -531,27 +551,46 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay bitbang_swd_exchange(false, &cmd, 0, 8); bitbang_interface->swdio_drive(false); - bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1); + bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3); + + /* Avoid a glitch on SWDIO when changing the direction to output. + * To keep performance penalty minimal, pre-write the first data + * bit to SWDIO GPIO output buffer while clocking the turnaround bit. + * Following swdio_drive(true) outputs the pre-written value + * and the same value is rewritten by the next swd_write() + * instead of glitching SWDIO + * HiZ/pull-up --------------> 0 -------------> 1 + * swdio_drive(true) swd_write(0,1) + * in case of data bit 0 = 1 + */ + bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 1); bitbang_interface->swdio_drive(true); bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1); int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3); + LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK && (retry == 0 || ack != SWD_ACK_WAIT)) + ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO, + "%s%s %s write reg %X = %08" PRIx32, + check_ack ? "" : "ack ignored ", + ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + (cmd & SWD_CMD_A32) >> 1, + buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32)); + + if (check_ack && ack == SWD_ACK_WAIT && timeval_ms() <= timeout) { + swd_clear_sticky_errors(); + if (retry > 20) + alive_sleep(1); - LOG_DEBUG("%s%s %s write reg %X = %08"PRIx32, - check_ack ? "" : "ack ignored ", - ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APNDP ? "AP" : "DP", - (cmd & SWD_CMD_A32) >> 1, - buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32)); - - if (check_ack) { - if (ack == SWD_ACK_WAIT) { - swd_clear_sticky_errors(); - continue; - } else if (ack != SWD_ACK_OK) { - queued_retval = swd_ack_to_error_code(ack); - return; - } + continue; + } + + if (retry > 1) + LOG_DEBUG("SWD WAIT: retried %u times", retry); + + if (check_ack && ack != SWD_ACK_OK) { + queued_retval = swd_ack_to_error_code(ack); + return; } if (cmd & SWD_CMD_APNDP) @@ -562,14 +601,13 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay static int bitbang_swd_run_queue(void) { - LOG_DEBUG("bitbang_swd_run_queue"); /* A transaction must be followed by another transaction or at least 8 idle cycles to * ensure that data is clocked through the AP. */ bitbang_swd_exchange(true, NULL, 0, 8); int retval = queued_retval; queued_retval = ERROR_OK; - LOG_DEBUG("SWD queue return value: %02x", retval); + LOG_DEBUG_IO("SWD queue return value: %02x", retval); return retval; } diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h index 4ea1cc0454..6afa409e98 100644 --- a/src/jtag/drivers/bitbang.h +++ b/src/jtag/drivers/bitbang.h @@ -12,12 +12,13 @@ #define OPENOCD_JTAG_DRIVERS_BITBANG_H #include <jtag/swd.h> +#include <jtag/commands.h> -typedef enum { +enum bb_value { BB_LOW, BB_HIGH, BB_ERROR -} bb_value_t; +}; /** Low level callbacks (for bitbang). * @@ -28,7 +29,7 @@ typedef enum { * increase throughput. */ struct bitbang_interface { /** Sample TDO and return the value. */ - bb_value_t (*read)(void); + enum bb_value (*read)(void); /** The number of TDO samples that can be buffered up before the caller has * to call read_sample. */ @@ -38,13 +39,13 @@ struct bitbang_interface { int (*sample)(void); /** Return the next unread value from the buffer. */ - bb_value_t (*read_sample)(void); + enum bb_value (*read_sample)(void); /** Set TCK, TMS, and TDI to the given values. */ int (*write)(int tck, int tms, int tdi); /** Blink led (optional). */ - int (*blink)(int on); + int (*blink)(bool on); /** Sample SWDIO and return the value. */ int (*swdio_read)(void); @@ -54,12 +55,18 @@ struct bitbang_interface { /** Set SWCLK and SWDIO to the given value. */ int (*swd_write)(int swclk, int swdio); + + /** Sleep for some number of microseconds. **/ + int (*sleep)(unsigned int microseconds); + + /** Force a flush. */ + int (*flush)(void); }; extern const struct swd_driver bitbang_swd; -int bitbang_execute_queue(void); +int bitbang_execute_queue(struct jtag_command *cmd_queue); -extern struct bitbang_interface *bitbang_interface; +extern const struct bitbang_interface *bitbang_interface; #endif /* OPENOCD_JTAG_DRIVERS_BITBANG_H */ diff --git a/src/jtag/drivers/bitq.c b/src/jtag/drivers/bitq.c index 03ad7af87e..84acff8357 100644 --- a/src/jtag/drivers/bitq.c +++ b/src/jtag/drivers/bitq.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * @@ -18,8 +18,8 @@ struct bitq_interface *bitq_interface; /* low level bit queue interface */ /* state of input queue */ struct bitq_state { struct jtag_command *cmd; /* command currently processed */ - int field_idx; /* index of field currently being processed */ - int bit_pos; /* position of bit currently being processed */ + unsigned int field_idx; /* index of field currently being processed */ + unsigned int bit_pos; /* position of bit currently being processed */ int status; /* processing status */ }; static struct bitq_state bitq_in_state; @@ -76,7 +76,7 @@ static void bitq_io(int tms, int tdi, int tdo_req) bitq_in_proc(); } -static void bitq_end_state(tap_state_t state) +static void bitq_end_state(enum tap_state state) { if (!tap_is_state_stable(state)) { LOG_ERROR("BUG: %i is not a valid end state", state); @@ -85,7 +85,7 @@ static void bitq_end_state(tap_state_t state) tap_set_end_state(state); } -static void bitq_state_move(tap_state_t new_state) +static void bitq_state_move(enum tap_state new_state) { int i = 0; uint8_t tms_scan; @@ -108,9 +108,7 @@ static void bitq_state_move(tap_state_t new_state) static void bitq_path_move(struct pathmove_command *cmd) { - int i; - - for (i = 0; i < cmd->num_states; i++) { + for (unsigned int i = 0; i < cmd->num_states; i++) { if (tap_state_transition(tap_get_state(), false) == cmd->path[i]) bitq_io(0, 0, 0); else if (tap_state_transition(tap_get_state(), true) == cmd->path[i]) @@ -127,16 +125,14 @@ static void bitq_path_move(struct pathmove_command *cmd) tap_set_end_state(tap_get_state()); } -static void bitq_runtest(int num_cycles) +static void bitq_runtest(unsigned int num_cycles) { - int i; - /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) bitq_state_move(TAP_IDLE); /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) bitq_io(0, 0, 0); /* finish in end_state */ @@ -146,11 +142,10 @@ static void bitq_runtest(int num_cycles) static void bitq_scan_field(struct scan_field *field, int do_pause) { - int bit_cnt; int tdo_req; const uint8_t *out_ptr; - uint8_t out_mask; + uint8_t out_mask; if (field->in_value) tdo_req = 1; @@ -159,7 +154,7 @@ static void bitq_scan_field(struct scan_field *field, int do_pause) if (!field->out_value) { /* just send zeros and request data from TDO */ - for (bit_cnt = field->num_bits; bit_cnt > 1; bit_cnt--) + for (unsigned int i = 0; i < (field->num_bits - 1); i++) bitq_io(0, 0, tdo_req); bitq_io(do_pause, 0, tdo_req); @@ -167,7 +162,7 @@ static void bitq_scan_field(struct scan_field *field, int do_pause) /* send data, and optionally request TDO */ out_mask = 0x01; out_ptr = field->out_value; - for (bit_cnt = field->num_bits; bit_cnt > 1; bit_cnt--) { + for (unsigned int i = 0; i < (field->num_bits - 1); i++) { bitq_io(0, ((*out_ptr) & out_mask) != 0, tdo_req); if (out_mask == 0x80) { out_mask = 0x01; @@ -190,24 +185,23 @@ static void bitq_scan_field(struct scan_field *field, int do_pause) static void bitq_scan(struct scan_command *cmd) { - int i; - if (cmd->ir_scan) bitq_state_move(TAP_IRSHIFT); else bitq_state_move(TAP_DRSHIFT); + unsigned int i; for (i = 0; i < cmd->num_fields - 1; i++) bitq_scan_field(&cmd->fields[i], 0); bitq_scan_field(&cmd->fields[i], 1); } -int bitq_execute_queue(void) +int bitq_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ - bitq_in_state.cmd = jtag_command_queue; + bitq_in_state.cmd = cmd_queue; bitq_in_state.field_idx = 0; bitq_in_state.bit_pos = 0; bitq_in_state.status = ERROR_OK; @@ -226,7 +220,7 @@ int bitq_execute_queue(void) break; case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); bitq_end_state(cmd->cmd.runtest->end_state); bitq_runtest(cmd->cmd.runtest->num_cycles); break; @@ -238,7 +232,7 @@ int bitq_execute_queue(void) break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %i", cmd->cmd.pathmove->num_states, + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); bitq_path_move(cmd->cmd.pathmove); break; diff --git a/src/jtag/drivers/bitq.h b/src/jtag/drivers/bitq.h index 8e06fcf737..3ed182da4c 100644 --- a/src/jtag/drivers/bitq.h +++ b/src/jtag/drivers/bitq.h @@ -27,7 +27,7 @@ struct bitq_interface { extern struct bitq_interface *bitq_interface; -int bitq_execute_queue(void); +int bitq_execute_queue(struct jtag_command *cmd_queue); void bitq_cleanup(void); diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c index 1de8e2343f..4283616adc 100644 --- a/src/jtag/drivers/buspirate.c +++ b/src/jtag/drivers/buspirate.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Michal Demin * @@ -20,18 +20,18 @@ #undef DEBUG_SERIAL /*#define DEBUG_SERIAL */ -static int buspirate_execute_queue(void); +static int buspirate_execute_queue(struct jtag_command *cmd_queue); static int buspirate_init(void); static int buspirate_quit(void); static int buspirate_reset(int trst, int srst); -static void buspirate_end_state(tap_state_t state); +static void buspirate_end_state(enum tap_state state); static void buspirate_state_move(void); -static void buspirate_path_move(int num_states, tap_state_t *path); -static void buspirate_runtest(int num_cycles); +static void buspirate_path_move(unsigned int num_states, enum tap_state *path); +static void buspirate_runtest(unsigned int num_cycles); static void buspirate_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command); -static void buspirate_stableclocks(int num_cycles); +static void buspirate_stableclocks(unsigned int num_cycles); #define CMD_UNKNOWN 0x00 #define CMD_PORT_MODE 0x01 @@ -151,10 +151,10 @@ static int buspirate_serial_read(int fd, uint8_t *buf, int size); static void buspirate_serial_close(int fd); static void buspirate_print_buffer(uint8_t *buf, int size); -static int buspirate_execute_queue(void) +static int buspirate_execute_queue(struct jtag_command *cmd_queue) { /* currently processed command */ - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int scan_size; enum scan_type type; uint8_t *buffer; @@ -162,7 +162,7 @@ static int buspirate_execute_queue(void) while (cmd) { switch (cmd->type) { case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %s", + LOG_DEBUG_IO("runtest %u cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest ->end_state)); @@ -180,7 +180,7 @@ static int buspirate_execute_queue(void) buspirate_state_move(); break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %s", + LOG_DEBUG_IO("pathmove: %u states, end in %s", cmd->cmd.pathmove->num_states, tap_state_name(cmd->cmd.pathmove ->path[cmd->cmd.pathmove @@ -210,7 +210,7 @@ static int buspirate_execute_queue(void) jtag_sleep(cmd->cmd.sleep->us); break; case JTAG_STABLECLOCKS: - LOG_DEBUG_IO("stable clock %i cycles", cmd->cmd.stableclocks->num_cycles); + LOG_DEBUG_IO("stable clock %u cycles", cmd->cmd.stableclocks->num_cycles); buspirate_stableclocks(cmd->cmd.stableclocks->num_cycles); break; default: @@ -534,15 +534,14 @@ static const struct swd_driver buspirate_swd = { .run = buspirate_swd_run_queue, }; -static const char * const buspirate_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface buspirate_interface = { .execute_queue = buspirate_execute_queue, }; struct adapter_driver buspirate_adapter_driver = { .name = "buspirate", - .transports = buspirate_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = buspirate_command_handlers, .init = buspirate_init, @@ -554,7 +553,7 @@ struct adapter_driver buspirate_adapter_driver = { }; /*************** jtag execute commands **********************/ -static void buspirate_end_state(tap_state_t state) +static void buspirate_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -580,11 +579,9 @@ static void buspirate_state_move(void) tap_set_state(tap_get_end_state()); } -static void buspirate_path_move(int num_states, tap_state_t *path) +static void buspirate_path_move(unsigned int num_states, enum tap_state *path) { - int i; - - for (i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (tap_state_transition(tap_get_state(), false) == path[i]) { buspirate_tap_append(0, 0); } else if (tap_state_transition(tap_get_state(), true) @@ -604,11 +601,9 @@ static void buspirate_path_move(int num_states, tap_state_t *path) tap_set_end_state(tap_get_state()); } -static void buspirate_runtest(int num_cycles) +static void buspirate_runtest(unsigned int num_cycles) { - int i; - - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -616,7 +611,7 @@ static void buspirate_runtest(int num_cycles) buspirate_state_move(); } - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) buspirate_tap_append(0, 0); LOG_DEBUG_IO("runtest: cur_state %s end_state %s", @@ -632,7 +627,7 @@ static void buspirate_runtest(int num_cycles) static void buspirate_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command) { - tap_state_t saved_end_state; + enum tap_state saved_end_state; buspirate_tap_make_space(1, scan_size+8); /* is 8 correct ? (2 moves = 16) */ @@ -658,14 +653,13 @@ static void buspirate_scan(bool ir_scan, enum scan_type type, buspirate_state_move(); } -static void buspirate_stableclocks(int num_cycles) +static void buspirate_stableclocks(unsigned int num_cycles) { - int i; int tms = (tap_get_state() == TAP_RESET ? 1 : 0); buspirate_tap_make_space(0, num_cycles); - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) buspirate_tap_append(tms, 0); } @@ -1447,7 +1441,7 @@ static void buspirate_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_del data); switch (ack) { - case SWD_ACK_OK: + case SWD_ACK_OK: if (parity != parity_u32(data)) { LOG_DEBUG("Read data parity mismatch %x %x", parity, parity_u32(data)); queued_retval = ERROR_FAIL; @@ -1458,15 +1452,15 @@ static void buspirate_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_del if (cmd & SWD_CMD_APNDP) buspirate_swd_idle_clocks(ap_delay_clk); return; - case SWD_ACK_WAIT: + case SWD_ACK_WAIT: LOG_DEBUG("SWD_ACK_WAIT"); buspirate_swd_clear_sticky_errors(); return; - case SWD_ACK_FAULT: + case SWD_ACK_FAULT: LOG_DEBUG("SWD_ACK_FAULT"); queued_retval = ack; return; - default: + default: LOG_DEBUG("No valid acknowledge: ack=%d", ack); queued_retval = ack; return; @@ -1505,19 +1499,19 @@ static void buspirate_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_del value); switch (ack) { - case SWD_ACK_OK: + case SWD_ACK_OK: if (cmd & SWD_CMD_APNDP) buspirate_swd_idle_clocks(ap_delay_clk); return; - case SWD_ACK_WAIT: + case SWD_ACK_WAIT: LOG_DEBUG("SWD_ACK_WAIT"); buspirate_swd_clear_sticky_errors(); return; - case SWD_ACK_FAULT: + case SWD_ACK_FAULT: LOG_DEBUG("SWD_ACK_FAULT"); queued_retval = ack; return; - default: + default: LOG_DEBUG("No valid acknowledge: ack=%d", ack); queued_retval = ack; return; diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index 6a9c9df5e1..2bfcfcc2b0 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2021 by Adrian Negreanu * @@ -39,14 +39,22 @@ #include "cmsis_dap.h" #include "libusb_helper.h" -static const struct cmsis_dap_backend *const cmsis_dap_backends[] = { -#if BUILD_CMSIS_DAP_USB == 1 - &cmsis_dap_usb_backend, +/* Create a dummy backend for 'backend' command if real one does not build */ +#if BUILD_CMSIS_DAP_USB == 0 +const struct cmsis_dap_backend cmsis_dap_usb_backend = { + .name = "usb_bulk", +}; #endif -#if BUILD_CMSIS_DAP_HID == 1 - &cmsis_dap_hid_backend, +#if BUILD_CMSIS_DAP_HID == 0 +const struct cmsis_dap_backend cmsis_dap_hid_backend = { + .name = "hid" +}; #endif + +static const struct cmsis_dap_backend *const cmsis_dap_backends[] = { + &cmsis_dap_usb_backend, + &cmsis_dap_hid_backend, }; /* USB Config */ @@ -160,6 +168,11 @@ static bool swd_mode; #define CMD_DAP_TFER_BLOCK 0x06 #define CMD_DAP_TFER_ABORT 0x07 +/* DAP_TransferBlock increases the sum of command/response sizes + * (due to 16-bit Transfer Count) if used in a small packet. + * Prevent using it until we have at least r/w operations. */ +#define CMD_DAP_TFER_BLOCK_MIN_OPS 4 + /* DAP Status Code */ #define DAP_OK 0 #define DAP_ERROR 0xFF @@ -209,38 +222,21 @@ static const char * const info_caps_str[INFO_CAPS__NUM_CAPS] = { "UART via USB COM port supported", }; -struct pending_transfer_result { - uint8_t cmd; - uint32_t data; - void *buffer; -}; - -struct pending_request_block { - struct pending_transfer_result *transfers; - int transfer_count; -}; - struct pending_scan_result { /** Offset in bytes in the CMD_DAP_JTAG_SEQ response buffer. */ - unsigned first; + unsigned int first; /** Number of bits to read. */ - unsigned length; + unsigned int length; /** Location to store the result */ uint8_t *buffer; /** Offset in the destination buffer */ - unsigned buffer_offset; + unsigned int buffer_offset; }; -/* Up to MIN(packet_count, MAX_PENDING_REQUESTS) requests may be issued - * until the first response arrives */ -#define MAX_PENDING_REQUESTS 3 - -/* Pending requests are organized as a FIFO - circular buffer */ /* Each block in FIFO can contain up to pending_queue_len transfers */ -static int pending_queue_len; -static struct pending_request_block pending_fifo[MAX_PENDING_REQUESTS]; -static int pending_fifo_put_idx, pending_fifo_get_idx; -static int pending_fifo_block_count; +static unsigned int pending_queue_len; +static unsigned int tfer_max_command_size; +static unsigned int tfer_max_response_size; /* pointers to buffers that will receive jtag scan results on the next flush */ #define MAX_PENDING_SCAN_RESULTS 256 @@ -248,7 +244,7 @@ static int pending_scan_result_count; static struct pending_scan_result pending_scan_results[MAX_PENDING_SCAN_RESULTS]; /* queued JTAG sequences that will be executed on the next flush */ -#define QUEUED_SEQ_BUF_LEN (cmsis_dap_handle->packet_size - 3) +#define QUEUED_SEQ_BUF_LEN (cmsis_dap_handle->packet_usable_size - 3) static int queued_seq_count; static int queued_seq_buf_end; static int queued_seq_tdo_ptr; @@ -273,26 +269,32 @@ static int cmsis_dap_open(void) return ERROR_FAIL; } + int retval = ERROR_FAIL; if (cmsis_dap_backend >= 0) { /* Use forced backend */ backend = cmsis_dap_backends[cmsis_dap_backend]; - if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) != ERROR_OK) - backend = NULL; + if (backend->open) + retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()); + else + LOG_ERROR("Requested CMSIS-DAP backend is disabled by configure"); + } else { /* Try all backends */ for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) { backend = cmsis_dap_backends[i]; - if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) == ERROR_OK) + if (!backend->open) + continue; + + retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()); + if (retval == ERROR_OK) break; - else - backend = NULL; } } - if (!backend) { + if (retval != ERROR_OK) { LOG_ERROR("unable to find a matching CMSIS-DAP device"); free(dap); - return ERROR_FAIL; + return retval; } dap->backend = backend; @@ -305,18 +307,20 @@ static int cmsis_dap_open(void) static void cmsis_dap_close(struct cmsis_dap *dap) { if (dap->backend) { - dap->backend->close(dap); + if (dap->backend->close) + dap->backend->close(dap); dap->backend = NULL; } - free(cmsis_dap_handle->packet_buffer); - free(cmsis_dap_handle); - cmsis_dap_handle = NULL; + free(dap->packet_buffer); - for (int i = 0; i < MAX_PENDING_REQUESTS; i++) { - free(pending_fifo[i].transfers); - pending_fifo[i].transfers = NULL; + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) { + free(dap->pending_fifo[i].transfers); + dap->pending_fifo[i].transfers = NULL; } + + free(cmsis_dap_handle); + cmsis_dap_handle = NULL; } static void cmsis_dap_flush_read(struct cmsis_dap *dap) @@ -326,7 +330,7 @@ static void cmsis_dap_flush_read(struct cmsis_dap *dap) * USB close/open so we need to flush up to 64 old packets * to be sure all buffers are empty */ for (i = 0; i < 64; i++) { - int retval = dap->backend->read(dap, 10); + int retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING); if (retval == ERROR_TIMEOUT_REACHED) break; } @@ -337,27 +341,30 @@ static void cmsis_dap_flush_read(struct cmsis_dap *dap) /* Send a message and receive the reply */ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen) { - if (pending_fifo_block_count) { - LOG_ERROR("pending %d blocks, flushing", pending_fifo_block_count); - while (pending_fifo_block_count) { - dap->backend->read(dap, 10); - pending_fifo_block_count--; + if (dap->write_count + dap->read_count) { + LOG_ERROR("internal: queue not empty before xfer"); + } + if (dap->pending_fifo_block_count) { + LOG_ERROR("pending %u blocks, flushing", dap->pending_fifo_block_count); + while (dap->pending_fifo_block_count) { + dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING); + dap->pending_fifo_block_count--; } - pending_fifo_put_idx = 0; - pending_fifo_get_idx = 0; + dap->pending_fifo_put_idx = 0; + dap->pending_fifo_get_idx = 0; } - uint8_t current_cmd = cmsis_dap_handle->command[0]; + uint8_t current_cmd = dap->command[0]; int retval = dap->backend->write(dap, txlen, LIBUSB_TIMEOUT_MS); if (retval < 0) return retval; /* get reply */ - retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS); + retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, CMSIS_DAP_BLOCKING); if (retval < 0) return retval; - uint8_t *resp = cmsis_dap_handle->response; + uint8_t *resp = dap->response; if (resp[0] == DAP_ERROR) { LOG_ERROR("CMSIS-DAP command 0x%" PRIx8 " not implemented", current_cmd); return ERROR_NOT_IMPLEMENTED; @@ -367,6 +374,7 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen) LOG_ERROR("CMSIS-DAP command mismatch. Sent 0x%" PRIx8 " received 0x%" PRIx8, current_cmd, resp[0]); + dap->backend->cancel_all(dap); cmsis_dap_flush_read(dap); return ERROR_FAIL; } @@ -421,7 +429,7 @@ static int cmsis_dap_cmd_dap_swj_sequence(uint8_t s_len, const uint8_t *sequence #ifdef CMSIS_DAP_JTAG_DEBUG LOG_DEBUG("cmsis-dap TMS sequence: len=%d", s_len); - for (int i = 0; i < DIV_ROUND_UP(s_len, 8); ++i) + for (unsigned int i = 0; i < DIV_ROUND_UP(s_len, 8); ++i) printf("%02X ", sequence[i]); printf("\n"); @@ -564,7 +572,7 @@ static int cmsis_dap_cmd_dap_delay(uint16_t delay_us) static int cmsis_dap_metacmd_targetsel(uint32_t instance_id) { uint8_t *command = cmsis_dap_handle->command; - const uint32_t SEQ_RD = 0x80, SEQ_WR = 0x00; + const uint32_t seq_rd = 0x80, seq_wr = 0x00; /* SWD multi-drop requires a transfer ala CMD_DAP_TFER, but with no expectation of an SWD ACK response. In @@ -573,19 +581,21 @@ static int cmsis_dap_metacmd_targetsel(uint32_t instance_id) The purpose of this operation is to select the target corresponding to the instance_id that is written */ + LOG_DEBUG_IO("DP write reg TARGETSEL %" PRIx32, instance_id); + size_t idx = 0; command[idx++] = CMD_DAP_SWD_SEQUENCE; command[idx++] = 3; /* sequence count */ /* sequence 0: packet request for TARGETSEL */ - command[idx++] = SEQ_WR | 8; + command[idx++] = seq_wr | 8; command[idx++] = SWD_CMD_START | swd_cmd(false, false, DP_TARGETSEL) | SWD_CMD_STOP | SWD_CMD_PARK; /* sequence 1: read Trn ACK Trn, no expectation for target to ACK */ - command[idx++] = SEQ_RD | 5; + command[idx++] = seq_rd | 5; /* sequence 2: WDATA plus parity */ - command[idx++] = SEQ_WR | (32 + 1); + command[idx++] = seq_wr | (32 + 1); h_u32_to_le(command + idx, instance_id); idx += 4; command[idx++] = parity_u32(instance_id); @@ -658,7 +668,7 @@ static int cmsis_dap_cmd_dap_swo_baudrate( command[0] = CMD_DAP_SWO_BAUDRATE; h_u32_to_le(&command[1], in_baudrate); - int retval = cmsis_dap_xfer(cmsis_dap_handle, 4); + int retval = cmsis_dap_xfer(cmsis_dap_handle, 5); uint32_t rvbr = le_to_h_u32(&cmsis_dap_handle->response[1]); if (retval != ERROR_OK || rvbr == 0) { LOG_ERROR("CMSIS-DAP: command CMD_SWO_Baudrate(%u) -> %u failed.", in_baudrate, rvbr); @@ -758,32 +768,70 @@ static int cmsis_dap_cmd_dap_swo_data( return ERROR_OK; } +static void cmsis_dap_swd_discard_all_pending(struct cmsis_dap *dap) +{ + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) + dap->pending_fifo[i].transfer_count = 0; + + dap->pending_fifo_put_idx = 0; + dap->pending_fifo_get_idx = 0; + dap->pending_fifo_block_count = 0; +} + +static void cmsis_dap_swd_cancel_transfers(struct cmsis_dap *dap) +{ + dap->backend->cancel_all(dap); + cmsis_dap_flush_read(dap); + cmsis_dap_swd_discard_all_pending(dap); +} + static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) { - uint8_t *command = cmsis_dap_handle->command; - struct pending_request_block *block = &pending_fifo[pending_fifo_put_idx]; + uint8_t *command = dap->command; + struct pending_request_block *block = &dap->pending_fifo[dap->pending_fifo_put_idx]; + + assert(dap->write_count + dap->read_count == block->transfer_count); + + /* Reset packet size check counters for the next packet */ + dap->write_count = 0; + dap->read_count = 0; - LOG_DEBUG_IO("Executing %d queued transactions from FIFO index %d", block->transfer_count, pending_fifo_put_idx); + LOG_DEBUG_IO("Executing %d queued transactions from FIFO index %u%s", + block->transfer_count, dap->pending_fifo_put_idx, + cmsis_dap_handle->swd_cmds_differ ? "" : ", same swd ops"); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skipping due to previous errors: %d", queued_retval); goto skip; } - if (block->transfer_count == 0) + if (block->transfer_count == 0) { + LOG_ERROR("internal: write an empty queue?!"); goto skip; + } + + bool block_cmd = !cmsis_dap_handle->swd_cmds_differ + && block->transfer_count >= CMD_DAP_TFER_BLOCK_MIN_OPS; + block->command = block_cmd ? CMD_DAP_TFER_BLOCK : CMD_DAP_TFER; - command[0] = CMD_DAP_TFER; + command[0] = block->command; command[1] = 0x00; /* DAP Index */ - command[2] = block->transfer_count; - size_t idx = 3; - for (int i = 0; i < block->transfer_count; i++) { + unsigned int idx; + if (block_cmd) { + h_u16_to_le(&command[2], block->transfer_count); + idx = 4; /* The first transfer will store the common DAP register */ + } else { + command[2] = block->transfer_count; + idx = 3; + } + + for (unsigned int i = 0; i < block->transfer_count; i++) { struct pending_transfer_result *transfer = &(block->transfers[i]); uint8_t cmd = transfer->cmd; uint32_t data = transfer->data; - LOG_DEBUG_IO("%s %s reg %x %"PRIx32, + LOG_DEBUG_IO("%s %s reg %x %" PRIx32, cmd & SWD_CMD_APNDP ? "AP" : "DP", cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, data); @@ -807,7 +855,9 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) data &= ~CORUNDETECT; } - command[idx++] = (cmd >> 1) & 0x0f; + if (!block_cmd || i == 0) + command[idx++] = (cmd >> 1) & 0x0f; + if (!(cmd & SWD_CMD_RNW)) { h_u32_to_le(&command[idx], data); idx += 4; @@ -818,14 +868,13 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) if (retval < 0) { queued_retval = retval; goto skip; - } else { - queued_retval = ERROR_OK; } - pending_fifo_put_idx = (pending_fifo_put_idx + 1) % dap->packet_count; - pending_fifo_block_count++; - if (pending_fifo_block_count > dap->packet_count) - LOG_ERROR("too much pending writes %d", pending_fifo_block_count); + unsigned int packet_count = dap->quirk_mode ? 1 : dap->packet_count; + dap->pending_fifo_put_idx = (dap->pending_fifo_put_idx + 1) % packet_count; + dap->pending_fifo_block_count++; + if (dap->pending_fifo_block_count > packet_count) + LOG_ERROR("internal: too much pending writes %u", dap->pending_fifo_block_count); return; @@ -833,55 +882,91 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) block->transfer_count = 0; } -static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) +static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blocking blocking) { - struct pending_request_block *block = &pending_fifo[pending_fifo_get_idx]; + int retval; + struct pending_request_block *block = &dap->pending_fifo[dap->pending_fifo_get_idx]; - if (pending_fifo_block_count == 0) - LOG_ERROR("no pending write"); + if (dap->pending_fifo_block_count == 0) { + LOG_ERROR("internal: no pending write when reading?!"); + return; + } + + if (queued_retval != ERROR_OK) { + /* keep reading blocks until the pipeline is empty */ + retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING); + if (retval == ERROR_TIMEOUT_REACHED || retval == 0) { + /* timeout means that we flushed the pipeline, + * we can safely discard remaining pending requests */ + cmsis_dap_swd_discard_all_pending(dap); + return; + } + goto skip; + } /* get reply */ - int retval = dap->backend->read(dap, timeout_ms); - if (retval == ERROR_TIMEOUT_REACHED && timeout_ms < LIBUSB_TIMEOUT_MS) + retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, blocking); + bool timeout = (retval == ERROR_TIMEOUT_REACHED || retval == 0); + if (timeout && blocking == CMSIS_DAP_NON_BLOCKING) return; if (retval <= 0) { - LOG_DEBUG("error reading data"); + LOG_DEBUG("error reading adapter response"); queued_retval = ERROR_FAIL; + if (timeout) { + /* timeout means that we flushed the pipeline, + * we can safely discard remaining pending requests */ + cmsis_dap_swd_discard_all_pending(dap); + return; + } goto skip; } uint8_t *resp = dap->response; - if (resp[0] != CMD_DAP_TFER) { + if (resp[0] != block->command) { LOG_ERROR("CMSIS-DAP command mismatch. Expected 0x%x received 0x%" PRIx8, - CMD_DAP_TFER, resp[0]); + block->command, resp[0]); + cmsis_dap_swd_cancel_transfers(dap); queued_retval = ERROR_FAIL; - goto skip; + return; } - uint8_t transfer_count = resp[1]; - uint8_t ack = resp[2] & 0x07; - if (resp[2] & 0x08) { + unsigned int transfer_count; + unsigned int idx; + if (block->command == CMD_DAP_TFER_BLOCK) { + transfer_count = le_to_h_u16(&resp[1]); + idx = 3; + } else { + transfer_count = resp[1]; + idx = 2; + } + if (resp[idx] & 0x08) { LOG_DEBUG("CMSIS-DAP Protocol Error @ %d (wrong parity)", transfer_count); queued_retval = ERROR_FAIL; goto skip; } + uint8_t ack = resp[idx++] & 0x07; if (ack != SWD_ACK_OK) { LOG_DEBUG("SWD ack not OK @ %d %s", transfer_count, ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK"); - queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL; + queued_retval = swd_ack_to_error_code(ack); /* TODO: use results of transfers completed before the error occurred? */ goto skip; } - if (block->transfer_count != transfer_count) + if (block->transfer_count != transfer_count) { LOG_ERROR("CMSIS-DAP transfer count mismatch: expected %d, got %d", block->transfer_count, transfer_count); + cmsis_dap_swd_cancel_transfers(dap); + queued_retval = ERROR_FAIL; + return; + } + + LOG_DEBUG_IO("Received results of %d queued transactions FIFO index %u, %s mode", + transfer_count, dap->pending_fifo_get_idx, + blocking ? "blocking" : "nonblocking"); - LOG_DEBUG_IO("Received results of %d queued transactions FIFO index %d", - transfer_count, pending_fifo_get_idx); - size_t idx = 3; - for (int i = 0; i < transfer_count; i++) { + for (unsigned int i = 0; i < transfer_count; i++) { struct pending_transfer_result *transfer = &(block->transfers[i]); if (transfer->cmd & SWD_CMD_RNW) { static uint32_t last_read; @@ -889,7 +974,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) uint32_t tmp = data; idx += 4; - LOG_DEBUG_IO("Read result: %"PRIx32, data); + LOG_DEBUG_IO("Read result: %" PRIx32, data); /* Imitate posted AP reads */ if ((transfer->cmd & SWD_CMD_APNDP) || @@ -905,22 +990,25 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) skip: block->transfer_count = 0; - pending_fifo_get_idx = (pending_fifo_get_idx + 1) % dap->packet_count; - pending_fifo_block_count--; + if (!dap->quirk_mode && dap->packet_count > 1) + dap->pending_fifo_get_idx = (dap->pending_fifo_get_idx + 1) % dap->packet_count; + dap->pending_fifo_block_count--; } static int cmsis_dap_swd_run_queue(void) { - if (pending_fifo_block_count) - cmsis_dap_swd_read_process(cmsis_dap_handle, 0); + if (cmsis_dap_handle->write_count + cmsis_dap_handle->read_count) { + if (cmsis_dap_handle->pending_fifo_block_count) + cmsis_dap_swd_read_process(cmsis_dap_handle, CMSIS_DAP_NON_BLOCKING); - cmsis_dap_swd_write_from_queue(cmsis_dap_handle); + cmsis_dap_swd_write_from_queue(cmsis_dap_handle); + } - while (pending_fifo_block_count) - cmsis_dap_swd_read_process(cmsis_dap_handle, LIBUSB_TIMEOUT_MS); + while (cmsis_dap_handle->pending_fifo_block_count) + cmsis_dap_swd_read_process(cmsis_dap_handle, CMSIS_DAP_BLOCKING); - pending_fifo_put_idx = 0; - pending_fifo_get_idx = 0; + cmsis_dap_handle->pending_fifo_put_idx = 0; + cmsis_dap_handle->pending_fifo_get_idx = 0; int retval = queued_retval; queued_retval = ERROR_OK; @@ -928,37 +1016,103 @@ static int cmsis_dap_swd_run_queue(void) return retval; } +static unsigned int cmsis_dap_tfer_cmd_size(unsigned int write_count, + unsigned int read_count, bool block_tfer) +{ + unsigned int size; + if (block_tfer) { + size = 5; /* DAP_TransferBlock header */ + size += write_count * 4; /* data */ + } else { + size = 3; /* DAP_Transfer header */ + size += write_count * (1 + 4); /* DAP register + data */ + size += read_count; /* DAP register */ + } + return size; +} + +static unsigned int cmsis_dap_tfer_resp_size(unsigned int write_count, + unsigned int read_count, bool block_tfer) +{ + unsigned int size; + if (block_tfer) + size = 4; /* DAP_TransferBlock response header */ + else + size = 3; /* DAP_Transfer response header */ + + size += read_count * 4; /* data */ + return size; +} + static void cmsis_dap_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data) { - bool targetsel_cmd = swd_cmd(false, false, DP_TARGETSEL) == cmd; + /* TARGETSEL register write cannot be queued */ + if (swd_cmd(false, false, DP_TARGETSEL) == cmd) { + queued_retval = cmsis_dap_swd_run_queue(); + + cmsis_dap_metacmd_targetsel(data); + return; + } + + /* Compute sizes of the DAP Transfer command and the expected response + * for all queued and this operation */ + unsigned int write_count = cmsis_dap_handle->write_count; + unsigned int read_count = cmsis_dap_handle->read_count; + bool block_cmd; + if (write_count + read_count < CMD_DAP_TFER_BLOCK_MIN_OPS) + block_cmd = false; + else + block_cmd = !cmsis_dap_handle->swd_cmds_differ + && cmd == cmsis_dap_handle->common_swd_cmd; + + if (cmd & SWD_CMD_RNW) + read_count++; + else + write_count++; - if (pending_fifo[pending_fifo_put_idx].transfer_count == pending_queue_len - || targetsel_cmd) { - if (pending_fifo_block_count) - cmsis_dap_swd_read_process(cmsis_dap_handle, 0); + unsigned int cmd_size = cmsis_dap_tfer_cmd_size(write_count, read_count, + block_cmd); + unsigned int resp_size = cmsis_dap_tfer_resp_size(write_count, read_count, + block_cmd); + unsigned int max_transfer_count = block_cmd ? 65535 : 255; + + /* Does the DAP Transfer command and also its expected response fit into one packet? */ + if (cmd_size > tfer_max_command_size + || resp_size > tfer_max_response_size + || write_count + read_count > max_transfer_count) { + if (cmsis_dap_handle->pending_fifo_block_count) + cmsis_dap_swd_read_process(cmsis_dap_handle, CMSIS_DAP_NON_BLOCKING); /* Not enough room in the queue. Run the queue. */ cmsis_dap_swd_write_from_queue(cmsis_dap_handle); - if (pending_fifo_block_count >= cmsis_dap_handle->packet_count) - cmsis_dap_swd_read_process(cmsis_dap_handle, LIBUSB_TIMEOUT_MS); + unsigned int packet_count = cmsis_dap_handle->quirk_mode ? 1 : cmsis_dap_handle->packet_count; + if (cmsis_dap_handle->pending_fifo_block_count >= packet_count) + cmsis_dap_swd_read_process(cmsis_dap_handle, CMSIS_DAP_BLOCKING); } - if (queued_retval != ERROR_OK) - return; + assert(cmsis_dap_handle->pending_fifo[cmsis_dap_handle->pending_fifo_put_idx].transfer_count < pending_queue_len); - if (targetsel_cmd) { - cmsis_dap_metacmd_targetsel(data); + if (queued_retval != ERROR_OK) return; - } - struct pending_request_block *block = &pending_fifo[pending_fifo_put_idx]; + struct pending_request_block *block = &cmsis_dap_handle->pending_fifo[cmsis_dap_handle->pending_fifo_put_idx]; struct pending_transfer_result *transfer = &(block->transfers[block->transfer_count]); transfer->data = data; transfer->cmd = cmd; + if (block->transfer_count == 0) { + cmsis_dap_handle->swd_cmds_differ = false; + cmsis_dap_handle->common_swd_cmd = cmd; + } else if (cmd != cmsis_dap_handle->common_swd_cmd) { + cmsis_dap_handle->swd_cmds_differ = true; + } + if (cmd & SWD_CMD_RNW) { /* Queue a read transaction */ transfer->buffer = dst; + cmsis_dap_handle->read_count++; + } else { + cmsis_dap_handle->write_count++; } block->transfer_count++; } @@ -1020,7 +1174,7 @@ static int cmsis_dap_get_caps_info(void) cmsis_dap_handle->caps = caps; - for (int i = 0; i < INFO_CAPS__NUM_CAPS; ++i) { + for (unsigned int i = 0; i < INFO_CAPS__NUM_CAPS; ++i) { if (caps & BIT(i)) LOG_INFO("CMSIS-DAP: %s", info_caps_str[i]); } @@ -1073,7 +1227,12 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq) unsigned int s_len; int retval; - if ((output_pins & (SWJ_PIN_SRST | SWJ_PIN_TRST)) == (SWJ_PIN_SRST | SWJ_PIN_TRST)) { + if (swd_mode) + queued_retval = cmsis_dap_swd_run_queue(); + + if (cmsis_dap_handle->quirk_mode && seq != LINE_RESET && + (output_pins & (SWJ_PIN_SRST | SWJ_PIN_TRST)) + == (SWJ_PIN_SRST | SWJ_PIN_TRST)) { /* Following workaround deasserts reset on most adapters. * Do not reconnect if a reset line is active! * Reconnecting would break connecting under reset. */ @@ -1198,7 +1357,6 @@ static int cmsis_dap_init(void) /* Be conservative and suppress submitting multiple HID requests * until we get packet count info from the adaptor */ cmsis_dap_handle->packet_count = 1; - pending_queue_len = 12; /* INFO_ID_PKT_SZ - short */ retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_SZ, &data); @@ -1208,13 +1366,7 @@ static int cmsis_dap_init(void) if (data[0] == 2) { /* short */ uint16_t pkt_sz = data[1] + (data[2] << 8); if (pkt_sz != cmsis_dap_handle->packet_size) { - - /* 4 bytes of command header + 5 bytes per register - * write. For bulk read sequences just 4 bytes are - * needed per transfer, so this is suboptimal. */ - pending_queue_len = (pkt_sz - 4) / 5; - - free(cmsis_dap_handle->packet_buffer); + cmsis_dap_handle->backend->packet_buffer_free(cmsis_dap_handle); retval = cmsis_dap_handle->backend->packet_buffer_alloc(cmsis_dap_handle, pkt_sz); if (retval != ERROR_OK) goto init_err; @@ -1223,23 +1375,34 @@ static int cmsis_dap_init(void) } } + /* Maximal number of transfers which fit to one packet: + * Limited by response size: 3 bytes of response header + 4 per read + * Plus writes to full command size: 3 bytes cmd header + 1 per read + 5 per write */ + tfer_max_command_size = cmsis_dap_handle->packet_usable_size; + tfer_max_response_size = cmsis_dap_handle->packet_usable_size; + unsigned int max_reads = tfer_max_response_size / 4; + pending_queue_len = max_reads + (tfer_max_command_size - max_reads) / 5; + cmsis_dap_handle->write_count = 0; + cmsis_dap_handle->read_count = 0; + /* INFO_ID_PKT_CNT - byte */ retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_CNT, &data); if (retval != ERROR_OK) goto init_err; if (data[0] == 1) { /* byte */ - int pkt_cnt = data[1]; + unsigned int pkt_cnt = data[1]; if (pkt_cnt > 1) cmsis_dap_handle->packet_count = MIN(MAX_PENDING_REQUESTS, pkt_cnt); - LOG_DEBUG("CMSIS-DAP: Packet Count = %d", pkt_cnt); + LOG_DEBUG("CMSIS-DAP: Packet Count = %u", pkt_cnt); } - LOG_DEBUG("Allocating FIFO for %d pending packets", cmsis_dap_handle->packet_count); - for (int i = 0; i < cmsis_dap_handle->packet_count; i++) { - pending_fifo[i].transfers = malloc(pending_queue_len * sizeof(struct pending_transfer_result)); - if (!pending_fifo[i].transfers) { + LOG_DEBUG("Allocating FIFO for %u pending packets", cmsis_dap_handle->packet_count); + for (unsigned int i = 0; i < cmsis_dap_handle->packet_count; i++) { + cmsis_dap_handle->pending_fifo[i].transfers = malloc(pending_queue_len + * sizeof(struct pending_transfer_result)); + if (!cmsis_dap_handle->pending_fifo[i].transfers) { LOG_ERROR("Unable to allocate memory for CMSIS-DAP queue"); retval = ERROR_FAIL; goto init_err; @@ -1354,7 +1517,7 @@ static int cmsis_dap_execute_tlr_reset(struct jtag_command *cmd) } /* Set new end state */ -static void cmsis_dap_end_state(tap_state_t state) +static void cmsis_dap_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -1365,7 +1528,7 @@ static void cmsis_dap_end_state(tap_state_t state) } #ifdef SPRINT_BINARY -static void sprint_binary(char *s, const uint8_t *buf, int offset, int len) +static void sprint_binary(char *s, const uint8_t *buf, unsigned int offset, unsigned int len) { if (!len) return; @@ -1376,7 +1539,7 @@ static void sprint_binary(char *s, const uint8_t *buf, int offset, int len) buf = { 0xc0 0x18 } offset=3 len=10 should result in: 11000 11000 i=3 there means i/8 = 0 so c = 0xFF, and */ - for (int i = offset; i < offset + len; ++i) { + for (unsigned int i = offset; i < offset + len; ++i) { uint8_t c = buf[i / 8], mask = 1 << (i % 8); if ((i != offset) && !(i % 8)) putchar(' '); @@ -1490,10 +1653,11 @@ static void cmsis_dap_flush(void) * sequence=NULL means clock out zeros on TDI * tdo_buffer=NULL means don't capture TDO */ -static void cmsis_dap_add_jtag_sequence(int s_len, const uint8_t *sequence, int s_offset, - bool tms, uint8_t *tdo_buffer, int tdo_buffer_offset) +static void cmsis_dap_add_jtag_sequence(unsigned int s_len, const uint8_t *sequence, + unsigned int s_offset, bool tms, + uint8_t *tdo_buffer, unsigned int tdo_buffer_offset) { - LOG_DEBUG_IO("[at %d] %d bits, tms %s, seq offset %d, tdo buf %p, tdo offset %d", + LOG_DEBUG_IO("[at %d] %u bits, tms %s, seq offset %u, tdo buf %p, tdo offset %u", queued_seq_buf_end, s_len, tms ? "HIGH" : "LOW", s_offset, tdo_buffer, tdo_buffer_offset); @@ -1502,11 +1666,11 @@ static void cmsis_dap_add_jtag_sequence(int s_len, const uint8_t *sequence, int if (s_len > 64) { LOG_DEBUG_IO("START JTAG SEQ SPLIT"); - for (int offset = 0; offset < s_len; offset += 64) { - int len = s_len - offset; + for (unsigned int offset = 0; offset < s_len; offset += 64) { + unsigned int len = s_len - offset; if (len > 64) len = 64; - LOG_DEBUG_IO("Splitting long jtag sequence: %d-bit chunk starting at offset %d", len, offset); + LOG_DEBUG_IO("Splitting long jtag sequence: %u-bit chunk starting at offset %u", len, offset); cmsis_dap_add_jtag_sequence( len, sequence, @@ -1520,7 +1684,7 @@ static void cmsis_dap_add_jtag_sequence(int s_len, const uint8_t *sequence, int return; } - int cmd_len = 1 + DIV_ROUND_UP(s_len, 8); + unsigned int cmd_len = 1 + DIV_ROUND_UP(s_len, 8); if (queued_seq_count >= 255 || queued_seq_buf_end + cmd_len > QUEUED_SEQ_BUF_LEN) /* empty out the buffer */ cmsis_dap_flush(); @@ -1593,7 +1757,7 @@ static void cmsis_dap_execute_scan(struct jtag_command *cmd) LOG_DEBUG("discarding trailing empty field"); } - if (cmd->cmd.scan->num_fields == 0) { + if (!cmd->cmd.scan->num_fields) { LOG_DEBUG("empty scan, doing nothing"); return; } @@ -1613,11 +1777,11 @@ static void cmsis_dap_execute_scan(struct jtag_command *cmd) cmsis_dap_end_state(cmd->cmd.scan->end_state); struct scan_field *field = cmd->cmd.scan->fields; - unsigned scan_size = 0; + unsigned int scan_size = 0; - for (int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { scan_size += field->num_bits; - LOG_DEBUG_IO("%s%s field %d/%d %d bits", + LOG_DEBUG_IO("%s%s field %u/%u %u bits", field->in_value ? "in" : "", field->out_value ? "out" : "", i, @@ -1682,7 +1846,7 @@ static void cmsis_dap_execute_scan(struct jtag_command *cmd) tap_state_name(tap_get_end_state())); } -static void cmsis_dap_pathmove(int num_states, tap_state_t *path) +static void cmsis_dap_pathmove(int num_states, enum tap_state *path) { uint8_t tms0 = 0x00; uint8_t tms1 = 0xff; @@ -1713,18 +1877,18 @@ static void cmsis_dap_execute_pathmove(struct jtag_command *cmd) cmsis_dap_pathmove(cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path); } -static void cmsis_dap_stableclocks(int num_cycles) +static void cmsis_dap_stableclocks(unsigned int num_cycles) { uint8_t tms = tap_get_state() == TAP_RESET; /* TODO: Perform optimizations? */ /* Execute num_cycles. */ - for (int i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) cmsis_dap_add_tms_sequence(&tms, 1); } -static void cmsis_dap_runtest(int num_cycles) +static void cmsis_dap_runtest(unsigned int num_cycles) { - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* Only do a state_move when we're not already in IDLE. */ if (tap_get_state() != TAP_IDLE) { @@ -1742,7 +1906,7 @@ static void cmsis_dap_runtest(int num_cycles) static void cmsis_dap_execute_runtest(struct jtag_command *cmd) { - LOG_DEBUG_IO("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); cmsis_dap_end_state(cmd->cmd.runtest->end_state); @@ -1751,13 +1915,13 @@ static void cmsis_dap_execute_runtest(struct jtag_command *cmd) static void cmsis_dap_execute_stableclocks(struct jtag_command *cmd) { - LOG_DEBUG_IO("stableclocks %i cycles", cmd->cmd.runtest->num_cycles); + LOG_DEBUG_IO("stableclocks %u cycles", cmd->cmd.runtest->num_cycles); cmsis_dap_stableclocks(cmd->cmd.runtest->num_cycles); } static void cmsis_dap_execute_tms(struct jtag_command *cmd) { - LOG_DEBUG_IO("TMS: %d bits", cmd->cmd.tms->num_bits); + LOG_DEBUG_IO("TMS: %u bits", cmd->cmd.tms->num_bits); cmsis_dap_cmd_dap_swj_sequence(cmd->cmd.tms->num_bits, cmd->cmd.tms->bits); } @@ -1795,9 +1959,9 @@ static void cmsis_dap_execute_command(struct jtag_command *cmd) } } -static int cmsis_dap_execute_queue(void) +static int cmsis_dap_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; while (cmd) { cmsis_dap_execute_command(cmd); @@ -1994,7 +2158,7 @@ COMMAND_HANDLER(cmsis_dap_handle_cmd_command) { uint8_t *command = cmsis_dap_handle->command; - for (unsigned i = 0; i < CMD_ARGC; i++) + for (unsigned int i = 0; i < CMD_ARGC; i++) COMMAND_PARSE_NUMBER(u8, CMD_ARGV[i], command[i]); int retval = cmsis_dap_xfer(cmsis_dap_handle, CMD_ARGC); @@ -2014,19 +2178,19 @@ COMMAND_HANDLER(cmsis_dap_handle_cmd_command) COMMAND_HANDLER(cmsis_dap_handle_vid_pid_command) { if (CMD_ARGC > MAX_USB_IDS * 2) { - LOG_WARNING("ignoring extra IDs in cmsis_dap_vid_pid " + LOG_WARNING("ignoring extra IDs in cmsis-dap vid_pid " "(maximum is %d pairs)", MAX_USB_IDS); CMD_ARGC = MAX_USB_IDS * 2; } if (CMD_ARGC < 2 || (CMD_ARGC & 1)) { - LOG_WARNING("incomplete cmsis_dap_vid_pid configuration directive"); + LOG_WARNING("incomplete cmsis-dap vid_pid configuration directive"); if (CMD_ARGC < 2) return ERROR_COMMAND_SYNTAX_ERROR; /* remove the incomplete trailing id */ CMD_ARGC -= 1; } - unsigned i; + unsigned int i; for (i = 0; i < CMD_ARGC; i += 2) { COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i], cmsis_dap_vid[i >> 1]); COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i + 1], cmsis_dap_pid[i >> 1]); @@ -2043,26 +2207,45 @@ COMMAND_HANDLER(cmsis_dap_handle_vid_pid_command) COMMAND_HANDLER(cmsis_dap_handle_backend_command) { - if (CMD_ARGC == 1) { - if (strcmp(CMD_ARGV[0], "auto") == 0) { - cmsis_dap_backend = -1; /* autoselect */ - } else { - for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) { - if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) { + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[0], "auto") == 0) { + cmsis_dap_backend = -1; /* autoselect */ + } else { + for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) { + if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) { + if (cmsis_dap_backends[i]->open) { cmsis_dap_backend = i; return ERROR_OK; } - } - LOG_ERROR("invalid backend argument to cmsis_dap_backend <backend>"); + command_print(CMD, "Requested cmsis-dap backend %s is disabled by configure", + cmsis_dap_backends[i]->name); + return ERROR_NOT_IMPLEMENTED; + } } - } else { - LOG_ERROR("expected exactly one argument to cmsis_dap_backend <backend>"); + + command_print(CMD, "invalid argument %s to cmsis-dap backend", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } return ERROR_OK; } +COMMAND_HANDLER(cmsis_dap_handle_quirk_command) +{ + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 1) + COMMAND_PARSE_ENABLE(CMD_ARGV[0], cmsis_dap_handle->quirk_mode); + + command_print(CMD, "CMSIS-DAP quirk workarounds %s", + cmsis_dap_handle->quirk_mode ? "enabled" : "disabled"); + return ERROR_OK; +} + static const struct command_registration cmsis_dap_subcommand_handlers[] = { { .name = "info", @@ -2078,35 +2261,30 @@ static const struct command_registration cmsis_dap_subcommand_handlers[] = { .usage = "", .help = "issue cmsis-dap command", }, - COMMAND_REGISTRATION_DONE -}; - - -static const struct command_registration cmsis_dap_command_handlers[] = { { - .name = "cmsis-dap", - .mode = COMMAND_ANY, - .help = "perform CMSIS-DAP management", - .usage = "<cmd>", - .chain = cmsis_dap_subcommand_handlers, - }, - { - .name = "cmsis_dap_vid_pid", + .name = "vid_pid", .handler = &cmsis_dap_handle_vid_pid_command, .mode = COMMAND_CONFIG, .help = "the vendor ID and product ID of the CMSIS-DAP device", .usage = "(vid pid)*", }, { - .name = "cmsis_dap_backend", + .name = "backend", .handler = &cmsis_dap_handle_backend_command, .mode = COMMAND_CONFIG, .help = "set the communication backend to use (USB bulk or HID).", .usage = "(auto | usb_bulk | hid)", }, + { + .name = "quirk", + .handler = &cmsis_dap_handle_quirk_command, + .mode = COMMAND_ANY, + .help = "allow expensive workarounds of known adapter quirks.", + .usage = "[enable | disable]", + }, #if BUILD_CMSIS_DAP_USB { - .name = "cmsis_dap_usb", + .name = "usb", .chain = cmsis_dap_usb_subcommand_handlers, .mode = COMMAND_ANY, .help = "USB bulk backend-specific commands", @@ -2116,6 +2294,18 @@ static const struct command_registration cmsis_dap_command_handlers[] = { COMMAND_REGISTRATION_DONE }; + +static const struct command_registration cmsis_dap_command_handlers[] = { + { + .name = "cmsis-dap", + .mode = COMMAND_ANY, + .help = "perform CMSIS-DAP management", + .usage = "<cmd>", + .chain = cmsis_dap_subcommand_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + static const struct swd_driver cmsis_dap_swd_driver = { .init = cmsis_dap_swd_init, .switch_seq = cmsis_dap_swd_switch_seq, @@ -2124,8 +2314,6 @@ static const struct swd_driver cmsis_dap_swd_driver = { .run = cmsis_dap_swd_run_queue, }; -static const char * const cmsis_dap_transport[] = { "swd", "jtag", NULL }; - static struct jtag_interface cmsis_dap_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = cmsis_dap_execute_queue, @@ -2133,7 +2321,8 @@ static struct jtag_interface cmsis_dap_interface = { struct adapter_driver cmsis_dap_adapter_driver = { .name = "cmsis-dap", - .transports = cmsis_dap_transport, + .transport_ids = TRANSPORT_SWD | TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_SWD, .commands = cmsis_dap_command_handlers, .init = cmsis_dap_init, diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h index cf929b0693..aded0e54a3 100644 --- a/src/jtag/drivers/cmsis_dap.h +++ b/src/jtag/drivers/cmsis_dap.h @@ -7,30 +7,73 @@ struct cmsis_dap_backend; struct cmsis_dap_backend_data; -struct command_registration; + +struct pending_transfer_result { + uint8_t cmd; + uint32_t data; + void *buffer; +}; + +/* Up to MIN(packet_count, MAX_PENDING_REQUESTS) requests may be issued + * until the first response arrives */ +#define MAX_PENDING_REQUESTS 4 + +struct pending_request_block { + struct pending_transfer_result *transfers; + unsigned int transfer_count; + uint8_t command; +}; struct cmsis_dap { struct cmsis_dap_backend_data *bdata; const struct cmsis_dap_backend *backend; - uint16_t packet_size; - int packet_count; + unsigned int packet_size; + unsigned int packet_usable_size; + unsigned int packet_buffer_size; uint8_t *packet_buffer; - uint16_t packet_buffer_size; uint8_t *command; uint8_t *response; + + /* DP/AP register r/w operation counters used for checking the packet size + * that would result from the queue run */ + unsigned int write_count; + unsigned int read_count; + + /* We can use DAP_TransferBlock only if all SWD operations in the packet + * are either all writes or all reads and use the same DP/AP register. + * The following variables keep track of it */ + uint8_t common_swd_cmd; + bool swd_cmds_differ; + + /* Pending requests are organized as a FIFO - circular buffer */ + struct pending_request_block pending_fifo[MAX_PENDING_REQUESTS]; + unsigned int packet_count; + unsigned int pending_fifo_put_idx, pending_fifo_get_idx; + unsigned int pending_fifo_block_count; + uint16_t caps; - uint8_t mode; + bool quirk_mode; /* enable expensive workarounds */ + uint32_t swo_buf_sz; bool trace_enabled; }; +/* Read mode */ +enum cmsis_dap_blocking { + CMSIS_DAP_NON_BLOCKING, + CMSIS_DAP_BLOCKING +}; + struct cmsis_dap_backend { const char *name; int (*open)(struct cmsis_dap *dap, uint16_t vids[], uint16_t pids[], const char *serial); void (*close)(struct cmsis_dap *dap); - int (*read)(struct cmsis_dap *dap, int timeout_ms); + int (*read)(struct cmsis_dap *dap, int transfer_timeout_ms, + enum cmsis_dap_blocking blocking); int (*write)(struct cmsis_dap *dap, int len, int timeout_ms); int (*packet_buffer_alloc)(struct cmsis_dap *dap, unsigned int pkt_sz); + void (*packet_buffer_free)(struct cmsis_dap *dap); + void (*cancel_all)(struct cmsis_dap *dap); }; extern const struct cmsis_dap_backend cmsis_dap_hid_backend; diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c index 034527015b..0dd6b2bbce 100644 --- a/src/jtag/drivers/cmsis_dap_usb_bulk.c +++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Mickaël Thomas * @@ -28,8 +28,23 @@ #include <libusb.h> #include <helper/log.h> #include <helper/replacements.h> +#include <jtag/jtag.h> /* ERROR_JTAG_DEVICE_ERROR only */ #include "cmsis_dap.h" +#include "libusb_helper.h" + +enum { + CMSIS_DAP_TRANSFER_PENDING = 0, /* must be 0, used in libusb_handle_events_completed */ + CMSIS_DAP_TRANSFER_IDLE, + CMSIS_DAP_TRANSFER_COMPLETED +}; + +struct cmsis_dap_bulk_transfer { + struct libusb_transfer *transfer; + uint8_t *buffer; + int status; /* either CMSIS_DAP_TRANSFER_ enum or error code */ + int transferred; +}; struct cmsis_dap_backend_data { struct libusb_context *usb_ctx; @@ -37,12 +52,16 @@ struct cmsis_dap_backend_data { unsigned int ep_out; unsigned int ep_in; int interface; + + struct cmsis_dap_bulk_transfer command_transfers[MAX_PENDING_REQUESTS]; + struct cmsis_dap_bulk_transfer response_transfers[MAX_PENDING_REQUESTS]; }; static int cmsis_dap_usb_interface = -1; static void cmsis_dap_usb_close(struct cmsis_dap *dap); static int cmsis_dap_usb_alloc(struct cmsis_dap *dap, unsigned int pkt_sz); +static void cmsis_dap_usb_free(struct cmsis_dap *dap); static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t pids[], const char *serial) { @@ -262,8 +281,10 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p /* If the interface is reliably identified * then we need not insist on setting USB class, subclass and protocol * exactly as the specification requires. + * Just filter out the well known classes, mainly CDC and MSC. * At least KitProg3 uses class 0 contrary to the specification */ - if (intf_identified_reliably) { + if (intf_identified_reliably && + (intf_desc->bInterfaceClass == 0 || intf_desc->bInterfaceClass > 0x12)) { LOG_WARNING("Using CMSIS-DAPv2 interface %d with wrong class %" PRId8 " subclass %" PRId8 " or protocol %" PRId8, interface_num, @@ -341,7 +362,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p if (err) LOG_WARNING("could not claim interface: %s", libusb_strerror(err)); - dap->bdata = malloc(sizeof(struct cmsis_dap_backend_data)); + dap->bdata = calloc(1, sizeof(struct cmsis_dap_backend_data)); if (!dap->bdata) { LOG_ERROR("unable to allocate memory"); libusb_release_interface(dev_handle, interface_num); @@ -350,25 +371,35 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p return ERROR_FAIL; } - dap->packet_size = packet_size; - dap->packet_buffer_size = packet_size; dap->bdata->usb_ctx = ctx; dap->bdata->dev_handle = dev_handle; dap->bdata->ep_out = ep_out; dap->bdata->ep_in = ep_in; dap->bdata->interface = interface_num; - dap->packet_buffer = malloc(dap->packet_buffer_size); - if (!dap->packet_buffer) { - LOG_ERROR("unable to allocate memory"); - cmsis_dap_usb_close(dap); - return ERROR_FAIL; + for (unsigned int idx = 0; idx < MAX_PENDING_REQUESTS; idx++) { + dap->bdata->command_transfers[idx].status = CMSIS_DAP_TRANSFER_IDLE; + dap->bdata->command_transfers[idx].transfer = libusb_alloc_transfer(0); + if (!dap->bdata->command_transfers[idx].transfer) { + LOG_ERROR("unable to allocate USB transfer"); + cmsis_dap_usb_close(dap); + return ERROR_FAIL; + } + + dap->bdata->response_transfers[idx].status = CMSIS_DAP_TRANSFER_IDLE; + dap->bdata->response_transfers[idx].transfer = libusb_alloc_transfer(0); + if (!dap->bdata->response_transfers[idx].transfer) { + LOG_ERROR("unable to allocate USB transfer"); + cmsis_dap_usb_close(dap); + return ERROR_FAIL; + } } - dap->command = dap->packet_buffer; - dap->response = dap->packet_buffer; + err = cmsis_dap_usb_alloc(dap, packet_size); + if (err != ERROR_OK) + cmsis_dap_usb_close(dap); - return ERROR_OK; + return err; } libusb_close(dev_handle); @@ -382,74 +413,250 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p static void cmsis_dap_usb_close(struct cmsis_dap *dap) { + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) { + if (dap->bdata->command_transfers[i].status == CMSIS_DAP_TRANSFER_PENDING) { + LOG_DEBUG("busy command USB transfer at %u", dap->pending_fifo_put_idx); + struct timeval tv = { + .tv_sec = 1, + .tv_usec = 1000 + }; + /* Complete pending commands */ + int res = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx, &tv, NULL); + if (res == 0) + libusb_free_transfer(dap->bdata->command_transfers[i].transfer); + } else { + libusb_free_transfer(dap->bdata->command_transfers[i].transfer); + } + libusb_free_transfer(dap->bdata->response_transfers[i].transfer); + } + cmsis_dap_usb_free(dap); libusb_release_interface(dap->bdata->dev_handle, dap->bdata->interface); libusb_close(dap->bdata->dev_handle); libusb_exit(dap->bdata->usb_ctx); free(dap->bdata); dap->bdata = NULL; - free(dap->packet_buffer); - dap->packet_buffer = NULL; } -static int cmsis_dap_usb_read(struct cmsis_dap *dap, int timeout_ms) +static void LIBUSB_CALL cmsis_dap_usb_callback(struct libusb_transfer *transfer) +{ + struct cmsis_dap_bulk_transfer *tr; + + tr = (struct cmsis_dap_bulk_transfer *)transfer->user_data; + if (transfer->status == LIBUSB_TRANSFER_COMPLETED) { + tr->status = CMSIS_DAP_TRANSFER_COMPLETED; + tr->transferred = transfer->actual_length; + } else if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { + tr->status = ERROR_TIMEOUT_REACHED; + } else { + tr->status = ERROR_JTAG_DEVICE_ERROR; + } +} + +static int cmsis_dap_usb_read(struct cmsis_dap *dap, int transfer_timeout_ms, + enum cmsis_dap_blocking blocking) { int transferred = 0; int err; + struct cmsis_dap_bulk_transfer *tr; + tr = &dap->bdata->response_transfers[dap->pending_fifo_get_idx]; + + if (tr->status == CMSIS_DAP_TRANSFER_IDLE) { + libusb_fill_bulk_transfer(tr->transfer, + dap->bdata->dev_handle, dap->bdata->ep_in, + tr->buffer, dap->packet_size, + &cmsis_dap_usb_callback, tr, + transfer_timeout_ms); + LOG_DEBUG_IO("submit read @ %u", dap->pending_fifo_get_idx); + tr->status = CMSIS_DAP_TRANSFER_PENDING; + err = libusb_submit_transfer(tr->transfer); + if (err) { + tr->status = CMSIS_DAP_TRANSFER_IDLE; + LOG_ERROR("error submitting USB read: %s", libusb_strerror(err)); + return ERROR_FAIL; + } + } - err = libusb_bulk_transfer(dap->bdata->dev_handle, dap->bdata->ep_in, - dap->packet_buffer, dap->packet_size, &transferred, timeout_ms); - if (err) { - if (err == LIBUSB_ERROR_TIMEOUT) { - return ERROR_TIMEOUT_REACHED; - } else { - LOG_ERROR("error reading data: %s", libusb_strerror(err)); + struct timeval tv; + if (blocking == CMSIS_DAP_NON_BLOCKING) { + tv.tv_sec = 0; + tv.tv_usec = 0; + } else { + tv.tv_sec = transfer_timeout_ms / 1000; + tv.tv_usec = transfer_timeout_ms % 1000 * 1000; + } + + while (tr->status == CMSIS_DAP_TRANSFER_PENDING) { + err = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx, &tv, + &tr->status); + if (err) { + LOG_ERROR("error handling USB events: %s", libusb_strerror(err)); return ERROR_FAIL; } + if (tv.tv_sec == 0 && tv.tv_usec == 0) + break; + } + + if (tr->status < 0 || tr->status == CMSIS_DAP_TRANSFER_COMPLETED) { + /* Check related command request for an error */ + struct cmsis_dap_bulk_transfer *tr_cmd; + tr_cmd = &dap->bdata->command_transfers[dap->pending_fifo_get_idx]; + if (tr_cmd->status < 0) { + err = tr_cmd->status; + tr_cmd->status = CMSIS_DAP_TRANSFER_IDLE; + if (err != ERROR_TIMEOUT_REACHED) + LOG_ERROR("error writing USB data"); + else + LOG_DEBUG("command write USB timeout @ %u", dap->pending_fifo_get_idx); + + return err; + } + if (tr_cmd->status == CMSIS_DAP_TRANSFER_COMPLETED) + tr_cmd->status = CMSIS_DAP_TRANSFER_IDLE; } - memset(&dap->packet_buffer[transferred], 0, dap->packet_buffer_size - transferred); + if (tr->status < 0) { + err = tr->status; + tr->status = CMSIS_DAP_TRANSFER_IDLE; + if (err != ERROR_TIMEOUT_REACHED) + LOG_ERROR("error reading USB data"); + else + LOG_DEBUG("USB timeout @ %u", dap->pending_fifo_get_idx); + + return err; + } + + if (tr->status == CMSIS_DAP_TRANSFER_COMPLETED) { + transferred = tr->transferred; + LOG_DEBUG_IO("completed read @ %u, transferred %i", + dap->pending_fifo_get_idx, transferred); + memcpy(dap->packet_buffer, tr->buffer, transferred); + memset(&dap->packet_buffer[transferred], 0, dap->packet_buffer_size - transferred); + tr->status = CMSIS_DAP_TRANSFER_IDLE; + } return transferred; } static int cmsis_dap_usb_write(struct cmsis_dap *dap, int txlen, int timeout_ms) { - int transferred = 0; int err; + struct cmsis_dap_bulk_transfer *tr; + tr = &dap->bdata->command_transfers[dap->pending_fifo_put_idx]; + + if (tr->status == CMSIS_DAP_TRANSFER_PENDING) { + LOG_DEBUG_IO("busy command USB transfer at %u", dap->pending_fifo_put_idx); + struct timeval tv = { + .tv_sec = timeout_ms / 1000, + .tv_usec = timeout_ms % 1000 * 1000 + }; + libusb_handle_events_timeout_completed(dap->bdata->usb_ctx, &tv, &tr->status); + } + if (tr->status < 0) { + if (tr->status != ERROR_TIMEOUT_REACHED) + LOG_ERROR("error writing USB data, late detect"); + else + LOG_DEBUG("USB write timeout @ %u, late detect", dap->pending_fifo_get_idx); + tr->status = CMSIS_DAP_TRANSFER_IDLE; + } + if (tr->status == CMSIS_DAP_TRANSFER_COMPLETED) { + LOG_DEBUG_IO("USB write: late transfer competed"); + tr->status = CMSIS_DAP_TRANSFER_IDLE; + } + if (tr->status != CMSIS_DAP_TRANSFER_IDLE) { + libusb_cancel_transfer(tr->transfer); + /* TODO: switch to less verbose errors and wait for USB working again */ + return ERROR_JTAG_DEVICE_ERROR; + } - /* skip the first byte that is only used by the HID backend */ - err = libusb_bulk_transfer(dap->bdata->dev_handle, dap->bdata->ep_out, - dap->packet_buffer, txlen, &transferred, timeout_ms); + memcpy(tr->buffer, dap->packet_buffer, txlen); + + libusb_fill_bulk_transfer(tr->transfer, + dap->bdata->dev_handle, dap->bdata->ep_out, + tr->buffer, txlen, + &cmsis_dap_usb_callback, tr, + timeout_ms); + + LOG_DEBUG_IO("submit write @ %u", dap->pending_fifo_put_idx); + tr->status = CMSIS_DAP_TRANSFER_PENDING; + err = libusb_submit_transfer(tr->transfer); if (err) { - if (err == LIBUSB_ERROR_TIMEOUT) { - return ERROR_TIMEOUT_REACHED; - } else { - LOG_ERROR("error writing data: %s", libusb_strerror(err)); - return ERROR_FAIL; - } + if (err == LIBUSB_ERROR_BUSY) + libusb_cancel_transfer(tr->transfer); + else + tr->status = CMSIS_DAP_TRANSFER_IDLE; + + LOG_ERROR("error submitting USB write: %s", libusb_strerror(err)); + return ERROR_FAIL; } - return transferred; + return ERROR_OK; } static int cmsis_dap_usb_alloc(struct cmsis_dap *dap, unsigned int pkt_sz) { - uint8_t *buf = malloc(pkt_sz); - if (!buf) { + dap->packet_buffer = malloc(pkt_sz); + if (!dap->packet_buffer) { LOG_ERROR("unable to allocate CMSIS-DAP packet buffer"); return ERROR_FAIL; } - dap->packet_buffer = buf; dap->packet_size = pkt_sz; dap->packet_buffer_size = pkt_sz; + /* Prevent sending zero size USB packets */ + dap->packet_usable_size = pkt_sz - 1; dap->command = dap->packet_buffer; dap->response = dap->packet_buffer; + struct cmsis_dap_backend_data *bdata = dap->bdata; + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) { + bdata->command_transfers[i].buffer = + oocd_libusb_dev_mem_alloc(bdata->dev_handle, pkt_sz); + + bdata->response_transfers[i].buffer = + oocd_libusb_dev_mem_alloc(bdata->dev_handle, pkt_sz); + + if (!bdata->command_transfers[i].buffer + || !bdata->response_transfers[i].buffer) { + LOG_ERROR("unable to allocate CMSIS-DAP pending packet buffer"); + return ERROR_FAIL; + } + } return ERROR_OK; } +static void cmsis_dap_usb_free(struct cmsis_dap *dap) +{ + struct cmsis_dap_backend_data *bdata = dap->bdata; + + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) { + oocd_libusb_dev_mem_free(bdata->dev_handle, + bdata->command_transfers[i].buffer, dap->packet_size); + oocd_libusb_dev_mem_free(bdata->dev_handle, + bdata->response_transfers[i].buffer, dap->packet_size); + bdata->command_transfers[i].buffer = NULL; + bdata->response_transfers[i].buffer = NULL; + } + + free(dap->packet_buffer); + dap->packet_buffer = NULL; + dap->command = NULL; + dap->response = NULL; +} + +static void cmsis_dap_usb_cancel_all(struct cmsis_dap *dap) +{ + for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) { + if (dap->bdata->command_transfers[i].status == CMSIS_DAP_TRANSFER_PENDING) + libusb_cancel_transfer(dap->bdata->command_transfers[i].transfer); + if (dap->bdata->response_transfers[i].status == CMSIS_DAP_TRANSFER_PENDING) + libusb_cancel_transfer(dap->bdata->response_transfers[i].transfer); + + dap->bdata->command_transfers[i].status = CMSIS_DAP_TRANSFER_IDLE; + dap->bdata->response_transfers[i].status = CMSIS_DAP_TRANSFER_IDLE; + } +} + COMMAND_HANDLER(cmsis_dap_handle_usb_interface_command) { if (CMD_ARGC == 1) @@ -478,4 +685,6 @@ const struct cmsis_dap_backend cmsis_dap_usb_backend = { .read = cmsis_dap_usb_read, .write = cmsis_dap_usb_write, .packet_buffer_alloc = cmsis_dap_usb_alloc, + .packet_buffer_free = cmsis_dap_usb_free, + .cancel_all = cmsis_dap_usb_cancel_all, }; diff --git a/src/jtag/drivers/cmsis_dap_usb_hid.c b/src/jtag/drivers/cmsis_dap_usb_hid.c index 605811d952..a4058ec803 100644 --- a/src/jtag/drivers/cmsis_dap_usb_hid.c +++ b/src/jtag/drivers/cmsis_dap_usb_hid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Mickaël Thomas * @@ -34,8 +34,39 @@ struct cmsis_dap_backend_data { hid_device *dev_handle; }; +struct cmsis_dap_report_size { + unsigned short vid; + unsigned short pid; + unsigned int report_size; +}; + +static const struct cmsis_dap_report_size report_size_quirks[] = { + /* Third gen Atmel tools use a report size of 512 */ + /* This list of PIDs comes from toolinfo.py in Microchip's pyedbglib. */ + // Atmel JTAG-ICE 3 + { .vid = 0x03eb, .pid = 0x2140, .report_size = 512 }, + // Atmel-ICE + { .vid = 0x03eb, .pid = 0x2141, .report_size = 512 }, + // Atmel Power Debugger + { .vid = 0x03eb, .pid = 0x2144, .report_size = 512 }, + // EDBG (found on Xplained Pro boards) + { .vid = 0x03eb, .pid = 0x2111, .report_size = 512 }, + // Zero (???) + { .vid = 0x03eb, .pid = 0x2157, .report_size = 512 }, + // EDBG with Mass Storage (found on Xplained Pro boards) + { .vid = 0x03eb, .pid = 0x2169, .report_size = 512 }, + // Commercially available EDBG (for third-party use) + { .vid = 0x03eb, .pid = 0x216a, .report_size = 512 }, + // Kraken (???) + { .vid = 0x03eb, .pid = 0x2170, .report_size = 512 }, + + { .vid = 0, .pid = 0, .report_size = 0 } +}; + + static void cmsis_dap_hid_close(struct cmsis_dap *dap); static int cmsis_dap_hid_alloc(struct cmsis_dap *dap, unsigned int pkt_sz); +static void cmsis_dap_hid_free(struct cmsis_dap *dap); static int cmsis_dap_hid_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t pids[], const char *serial) { @@ -90,8 +121,12 @@ static int cmsis_dap_hid_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p break; if (cur_dev->serial_number) { - size_t len = (strlen(serial) + 1) * sizeof(wchar_t); - wchar_t *wserial = malloc(len); + size_t len = mbstowcs(NULL, serial, 0) + 1; + wchar_t *wserial = malloc(len * sizeof(wchar_t)); + if (!wserial) { + LOG_ERROR("unable to allocate serial number buffer"); + return ERROR_FAIL; + } mbstowcs(wserial, serial, len); if (wcscmp(wserial, cur_dev->serial_number) == 0) { @@ -138,13 +173,15 @@ static int cmsis_dap_hid_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p unsigned int packet_size = 64; - /* atmel cmsis-dap uses 512 byte reports */ - /* except when it doesn't e.g. with mEDBG on SAMD10 Xplained - * board */ + /* Check for adapters that are known to have unusual report lengths. */ + for (i = 0; report_size_quirks[i].vid != 0; i++) { + if (report_size_quirks[i].vid == target_vid && + report_size_quirks[i].pid == target_pid) { + packet_size = report_size_quirks[i].report_size; + } + } /* TODO: HID report descriptor should be parsed instead of - * hardcoding a match by VID */ - if (target_vid == 0x03eb && target_pid != 0x2145 && target_pid != 0x2175) - packet_size = 512; + * hardcoding a match by VID/PID */ dap->bdata->dev_handle = dev; @@ -165,14 +202,17 @@ static void cmsis_dap_hid_close(struct cmsis_dap *dap) hid_exit(); free(dap->bdata); dap->bdata = NULL; - free(dap->packet_buffer); - dap->packet_buffer = NULL; + cmsis_dap_hid_free(dap); } -static int cmsis_dap_hid_read(struct cmsis_dap *dap, int timeout_ms) +static int cmsis_dap_hid_read(struct cmsis_dap *dap, int transfer_timeout_ms, + enum cmsis_dap_blocking blocking) { - int retval = hid_read_timeout(dap->bdata->dev_handle, dap->packet_buffer, dap->packet_buffer_size, timeout_ms); + int wait_ms = (blocking == CMSIS_DAP_NON_BLOCKING) ? 0 : transfer_timeout_ms; + int retval = hid_read_timeout(dap->bdata->dev_handle, + dap->packet_buffer, dap->packet_buffer_size, + wait_ms); if (retval == 0) { return ERROR_TIMEOUT_REACHED; } else if (retval == -1) { @@ -213,6 +253,7 @@ static int cmsis_dap_hid_alloc(struct cmsis_dap *dap, unsigned int pkt_sz) dap->packet_buffer = buf; dap->packet_size = pkt_sz; + dap->packet_usable_size = pkt_sz; dap->packet_buffer_size = packet_buffer_size; dap->command = dap->packet_buffer + REPORT_ID_SIZE; @@ -221,6 +262,16 @@ static int cmsis_dap_hid_alloc(struct cmsis_dap *dap, unsigned int pkt_sz) return ERROR_OK; } +static void cmsis_dap_hid_free(struct cmsis_dap *dap) +{ + free(dap->packet_buffer); + dap->packet_buffer = NULL; +} + +static void cmsis_dap_hid_cancel_all(struct cmsis_dap *dap) +{ +} + const struct cmsis_dap_backend cmsis_dap_hid_backend = { .name = "hid", .open = cmsis_dap_hid_open, @@ -228,4 +279,6 @@ const struct cmsis_dap_backend cmsis_dap_hid_backend = { .read = cmsis_dap_hid_read, .write = cmsis_dap_hid_write, .packet_buffer_alloc = cmsis_dap_hid_alloc, + .packet_buffer_free = cmsis_dap_hid_free, + .cancel_all = cmsis_dap_hid_cancel_all, }; diff --git a/src/jtag/drivers/dmem.c b/src/jtag/drivers/dmem.c new file mode 100644 index 0000000000..c1eb5b80dd --- /dev/null +++ b/src/jtag/drivers/dmem.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ + +/** + * @file + * This file implements support for the Direct memory access to CoreSight + * Access Ports (APs) or emulate the same to access CoreSight debug registers + * directly. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <sys/mman.h> + +#include <helper/align.h> +#include <helper/types.h> +#include <helper/system.h> +#include <helper/time_support.h> +#include <helper/list.h> +#include <jtag/interface.h> + +#include <target/arm_adi_v5.h> +#include <transport/transport.h> + +struct dmem_emu_ap_info { + uint64_t ap_num; + /* Emulation mode AP state variables */ + uint32_t apbap_tar; + uint32_t apbap_csw; +}; + +/* + * This bit tells if the transaction is coming in from jtag or not + * we just mask this out to emulate direct address access + */ +#define ARM_APB_PADDR31 BIT(31) + +static void *dmem_map_base, *dmem_virt_base_addr; +static size_t dmem_mapped_size; + +/* Default dmem device. */ +#define DMEM_DEV_PATH_DEFAULT "/dev/mem" +static char *dmem_dev_path; +static uint64_t dmem_dap_base_address; +static unsigned int dmem_dap_max_aps = 1; +static uint32_t dmem_dap_ap_offset = 0x100; + +/* DAP error code. */ +static int dmem_dap_retval = ERROR_OK; + +/* AP Emulation Mode */ +static uint64_t dmem_emu_base_address; +static uint64_t dmem_emu_size; +static void *dmem_emu_map_base, *dmem_emu_virt_base_addr; +static size_t dmem_emu_mapped_size; +#define DMEM_MAX_EMULATE_APS 5 +static unsigned int dmem_emu_ap_count; +static struct dmem_emu_ap_info dmem_emu_ap_list[DMEM_MAX_EMULATE_APS]; + +/* + * This helper is used to determine the TAR increment size in bytes. The AP's + * CSW encoding for SIZE supports byte count decode using "1 << SIZE". + */ +static uint32_t dmem_memap_tar_inc(uint32_t csw) +{ + if ((csw & CSW_ADDRINC_MASK) != 0) + return 1 << (csw & CSW_SIZE_MASK); + return 0; +} + +/* + * EMULATION MODE: In Emulation MODE, we assume the following: + * TCL still describes as system is operational from the view of AP (ex. jtag) + * However, the hardware doesn't permit direct memory access to these APs + * (only permitted via JTAG). + * + * So, the access to these APs have to be decoded to a memory map + * access which we can directly access. + * + * A few TI processors have this issue. + */ +static bool dmem_is_emulated_ap(struct adiv5_ap *ap, unsigned int *idx) +{ + for (unsigned int i = 0; i < dmem_emu_ap_count; i++) { + if (ap->ap_num == dmem_emu_ap_list[i].ap_num) { + *idx = i; + return true; + } + } + return false; +} + +static void dmem_emu_set_ap_reg(uint32_t addr, uint32_t val) +{ + addr &= ~ARM_APB_PADDR31; + + *(volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr) = val; +} + +static uint32_t dmem_emu_get_ap_reg(uint32_t addr) +{ + uint32_t val; + + addr &= ~ARM_APB_PADDR31; + + val = *(volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr); + + return val; +} + +static int dmem_emu_ap_q_read(unsigned int ap_idx, unsigned int reg, uint32_t *data) +{ + uint32_t addr; + int ret = ERROR_OK; + struct dmem_emu_ap_info *ap_info = &dmem_emu_ap_list[ap_idx]; + + switch (reg) { + case ADIV5_MEM_AP_REG_CSW: + *data = ap_info->apbap_csw; + break; + case ADIV5_MEM_AP_REG_TAR: + *data = ap_info->apbap_tar; + break; + case ADIV5_MEM_AP_REG_CFG: + *data = 0; + break; + case ADIV5_MEM_AP_REG_BASE: + *data = 0; + break; + case ADIV5_AP_REG_IDR: + *data = 0; + break; + case ADIV5_MEM_AP_REG_BD0: + case ADIV5_MEM_AP_REG_BD1: + case ADIV5_MEM_AP_REG_BD2: + case ADIV5_MEM_AP_REG_BD3: + addr = (ap_info->apbap_tar & ~0xf) + (reg & 0x0C); + + *data = dmem_emu_get_ap_reg(addr); + + break; + case ADIV5_MEM_AP_REG_DRW: + addr = ap_info->apbap_tar; + + *data = dmem_emu_get_ap_reg(addr); + + ap_info->apbap_tar += dmem_memap_tar_inc(ap_info->apbap_csw); + break; + default: + LOG_INFO("%s: Unknown reg: 0x%02x", __func__, reg); + ret = ERROR_FAIL; + break; + } + + /* Track the last error code. */ + if (ret != ERROR_OK) + dmem_dap_retval = ret; + + return ret; +} + +static int dmem_emu_ap_q_write(unsigned int ap_idx, unsigned int reg, uint32_t data) +{ + uint32_t addr; + int ret = ERROR_OK; + struct dmem_emu_ap_info *ap_info = &dmem_emu_ap_list[ap_idx]; + + switch (reg) { + case ADIV5_MEM_AP_REG_CSW: + /* + * This implementation only supports 32-bit accesses. + * Force this by ensuring CSW_SIZE field indicates 32-BIT. + */ + ap_info->apbap_csw = ((data & ~CSW_SIZE_MASK) | CSW_32BIT); + break; + case ADIV5_MEM_AP_REG_TAR: + /* + * This implementation only supports 32-bit accesses. + * Force LS 2-bits of TAR to 00b + */ + ap_info->apbap_tar = (data & ~0x3); + break; + + case ADIV5_MEM_AP_REG_CFG: + case ADIV5_MEM_AP_REG_BASE: + case ADIV5_AP_REG_IDR: + /* We don't use this, so we don't need to store */ + break; + + case ADIV5_MEM_AP_REG_BD0: + case ADIV5_MEM_AP_REG_BD1: + case ADIV5_MEM_AP_REG_BD2: + case ADIV5_MEM_AP_REG_BD3: + addr = (ap_info->apbap_tar & ~0xf) + (reg & 0x0C); + + dmem_emu_set_ap_reg(addr, data); + + break; + case ADIV5_MEM_AP_REG_DRW: + addr = ap_info->apbap_tar; + dmem_emu_set_ap_reg(addr, data); + + ap_info->apbap_tar += dmem_memap_tar_inc(ap_info->apbap_csw); + break; + default: + LOG_INFO("%s: Unknown reg: 0x%02x", __func__, reg); + ret = EINVAL; + break; + } + + /* Track the last error code. */ + if (ret != ERROR_OK) + dmem_dap_retval = ret; + + return ret; +} + +/* AP MODE */ +static uint32_t dmem_get_ap_reg_offset(struct adiv5_ap *ap, unsigned int reg) +{ + return (dmem_dap_ap_offset * ap->ap_num) + reg; +} + +static void dmem_set_ap_reg(struct adiv5_ap *ap, unsigned int reg, uint32_t val) +{ + *(volatile uint32_t *)((uintptr_t)dmem_virt_base_addr + + dmem_get_ap_reg_offset(ap, reg)) = val; +} + +static uint32_t dmem_get_ap_reg(struct adiv5_ap *ap, unsigned int reg) +{ + return *(volatile uint32_t *)((uintptr_t)dmem_virt_base_addr + + dmem_get_ap_reg_offset(ap, reg)); +} + +static int dmem_dp_q_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data) +{ + if (!data) + return ERROR_OK; + + switch (reg) { + case DP_CTRL_STAT: + *data = CDBGPWRUPACK | CSYSPWRUPACK; + break; + + default: + *data = 0; + break; + } + + return ERROR_OK; +} + +static int dmem_dp_q_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data) +{ + return ERROR_OK; +} + +static int dmem_ap_q_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data) +{ + unsigned int idx; + + if (is_adiv6(ap->dap)) { + static bool error_flagged; + + if (!error_flagged) + LOG_ERROR("ADIv6 dap not supported by dmem dap-direct mode"); + + error_flagged = true; + + return ERROR_FAIL; + } + + if (dmem_is_emulated_ap(ap, &idx)) + return dmem_emu_ap_q_read(idx, reg, data); + + *data = dmem_get_ap_reg(ap, reg); + + return ERROR_OK; +} + +static int dmem_ap_q_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data) +{ + unsigned int idx; + + if (is_adiv6(ap->dap)) { + static bool error_flagged; + + if (!error_flagged) + LOG_ERROR("ADIv6 dap not supported by dmem dap-direct mode"); + + error_flagged = true; + + return ERROR_FAIL; + } + + if (dmem_is_emulated_ap(ap, &idx)) + return dmem_emu_ap_q_write(idx, reg, data); + + dmem_set_ap_reg(ap, reg, data); + + return ERROR_OK; +} + +static int dmem_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack) +{ + return ERROR_OK; +} + +static int dmem_dp_run(struct adiv5_dap *dap) +{ + int retval = dmem_dap_retval; + + /* Clear the error code. */ + dmem_dap_retval = ERROR_OK; + + return retval; +} + +static int dmem_connect(struct adiv5_dap *dap) +{ + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_dap_device_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + free(dmem_dev_path); + dmem_dev_path = strdup(CMD_ARGV[0]); + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_dap_base_address_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], dmem_dap_base_address); + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_dap_max_aps_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], dmem_dap_max_aps); + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_dap_ap_offset_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], dmem_dap_ap_offset); + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_emu_base_address_command) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], dmem_emu_base_address); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], dmem_emu_size); + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_emu_ap_list_command) +{ + uint64_t em_ap; + + if (CMD_ARGC < 1 || CMD_ARGC > DMEM_MAX_EMULATE_APS) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int i = 0; i < CMD_ARGC; i++) { + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[i], em_ap); + dmem_emu_ap_list[i].ap_num = em_ap; + } + + dmem_emu_ap_count = CMD_ARGC; + + return ERROR_OK; +} + +COMMAND_HANDLER(dmem_dap_config_info_command) +{ + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + command_print(CMD, "dmem (Direct Memory) AP Adapter Configuration:"); + command_print(CMD, " Device : %s", + dmem_dev_path ? dmem_dev_path : DMEM_DEV_PATH_DEFAULT); + command_print(CMD, " Base Address : 0x%" PRIx64, dmem_dap_base_address); + command_print(CMD, " Max APs : %u", dmem_dap_max_aps); + command_print(CMD, " AP offset : 0x%08" PRIx32, dmem_dap_ap_offset); + command_print(CMD, " Emulated AP Count : %u", dmem_emu_ap_count); + + if (dmem_emu_ap_count) { + command_print(CMD, " Emulated AP details:"); + command_print(CMD, " Emulated address : 0x%" PRIx64, dmem_emu_base_address); + command_print(CMD, " Emulated size : 0x%" PRIx64, dmem_emu_size); + for (unsigned int i = 0; i < dmem_emu_ap_count; i++) + command_print(CMD, " Emulated AP [%u] : %" PRIx64, i, + dmem_emu_ap_list[i].ap_num); + } + return ERROR_OK; +} + +static const struct command_registration dmem_dap_subcommand_handlers[] = { + { + .name = "info", + .handler = dmem_dap_config_info_command, + .mode = COMMAND_ANY, + .help = "print the config info", + .usage = "", + }, + { + .name = "device", + .handler = dmem_dap_device_command, + .mode = COMMAND_CONFIG, + .help = "set the dmem memory access device (default: /dev/mem)", + .usage = "device_path", + }, + { + .name = "base_address", + .handler = dmem_dap_base_address_command, + .mode = COMMAND_CONFIG, + .help = "set the dmem dap AP memory map base address", + .usage = "base_address", + }, + { + .name = "ap_address_offset", + .handler = dmem_dap_ap_offset_command, + .mode = COMMAND_CONFIG, + .help = "set the offsets of each ap index", + .usage = "offset_address", + }, + { + .name = "max_aps", + .handler = dmem_dap_max_aps_command, + .mode = COMMAND_CONFIG, + .help = "set the maximum number of APs this will support", + .usage = "n", + }, + { + .name = "emu_ap_list", + .handler = dmem_emu_ap_list_command, + .mode = COMMAND_CONFIG, + .help = "set the list of AP indices to be emulated (upto max)", + .usage = "n", + }, + { + .name = "emu_base_address_range", + .handler = dmem_emu_base_address_command, + .mode = COMMAND_CONFIG, + .help = "set the base address and size of emulated AP range (all emulated APs access this range)", + .usage = "base_address address_window_size", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration dmem_dap_command_handlers[] = { + { + .name = "dmem", + .mode = COMMAND_ANY, + .help = "Perform dmem (Direct Memory) DAP management and configuration", + .chain = dmem_dap_subcommand_handlers, + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; + +static int dmem_dap_init(void) +{ + char *path = dmem_dev_path ? dmem_dev_path : DMEM_DEV_PATH_DEFAULT; + uint32_t dmem_total_memory_window_size; + long page_size = sysconf(_SC_PAGESIZE); + size_t dmem_mapped_start, dmem_mapped_end; + long start_delta; + int dmem_fd; + + if (!dmem_dap_base_address) { + LOG_ERROR("dmem DAP Base address NOT set? value is 0"); + return ERROR_FAIL; + } + + dmem_fd = open(path, O_RDWR | O_SYNC); + if (dmem_fd == -1) { + LOG_ERROR("Unable to open %s", path); + return ERROR_FAIL; + } + + dmem_total_memory_window_size = (dmem_dap_max_aps + 1) * dmem_dap_ap_offset; + + dmem_mapped_start = dmem_dap_base_address; + dmem_mapped_end = dmem_dap_base_address + dmem_total_memory_window_size; + /* mmap() requires page aligned offsets */ + dmem_mapped_start = ALIGN_DOWN(dmem_mapped_start, page_size); + dmem_mapped_end = ALIGN_UP(dmem_mapped_end, page_size); + + dmem_mapped_size = dmem_mapped_end - dmem_mapped_start; + start_delta = dmem_mapped_start - dmem_dap_base_address; + + dmem_map_base = mmap(NULL, + dmem_mapped_size, + (PROT_READ | PROT_WRITE), + MAP_SHARED, dmem_fd, + dmem_mapped_start); + if (dmem_map_base == MAP_FAILED) { + LOG_ERROR("Mapping address 0x%zx for 0x%zx bytes failed!", + dmem_mapped_start, dmem_mapped_size); + goto error_fail; + } + + dmem_virt_base_addr = (void *)((uintptr_t)dmem_map_base + start_delta); + + /* Lets Map the emulated address if necessary */ + if (dmem_emu_ap_count) { + dmem_mapped_start = dmem_emu_base_address; + dmem_mapped_end = dmem_emu_base_address + dmem_emu_size; + /* mmap() requires page aligned offsets */ + dmem_mapped_start = ALIGN_DOWN(dmem_mapped_start, page_size); + dmem_mapped_end = ALIGN_UP(dmem_mapped_end, page_size); + + dmem_emu_mapped_size = dmem_mapped_end - dmem_mapped_start; + start_delta = dmem_mapped_start - dmem_emu_base_address; + + dmem_emu_map_base = mmap(NULL, + dmem_emu_mapped_size, + (PROT_READ | PROT_WRITE), + MAP_SHARED, dmem_fd, + dmem_mapped_start); + if (dmem_emu_map_base == MAP_FAILED) { + LOG_ERROR("Mapping EMU address 0x%" PRIx64 " for 0x%" PRIx64 " bytes failed!", + dmem_emu_base_address, dmem_emu_size); + goto error_fail; + } + dmem_emu_virt_base_addr = (void *)((uintptr_t)dmem_emu_map_base + + start_delta); + } + + close(dmem_fd); + return ERROR_OK; + +error_fail: + close(dmem_fd); + return ERROR_FAIL; +} + +static int dmem_dap_quit(void) +{ + if (munmap(dmem_map_base, dmem_mapped_size) == -1) + LOG_ERROR("%s: Failed to unmap mapped memory!", __func__); + + if (dmem_emu_ap_count + && munmap(dmem_emu_map_base, dmem_emu_mapped_size) == -1) + LOG_ERROR("%s: Failed to unmap emu mapped memory!", __func__); + + return ERROR_OK; +} + +static int dmem_dap_reset(int req_trst, int req_srst) +{ + return ERROR_OK; +} + +static int dmem_dap_speed(int speed) +{ + return ERROR_OK; +} + +static int dmem_dap_khz(int khz, int *jtag_speed) +{ + *jtag_speed = khz; + return ERROR_OK; +} + +static int dmem_dap_speed_div(int speed, int *khz) +{ + *khz = speed; + return ERROR_OK; +} + +/* DAP operations. */ +static const struct dap_ops dmem_dap_ops = { + .connect = dmem_connect, + .queue_dp_read = dmem_dp_q_read, + .queue_dp_write = dmem_dp_q_write, + .queue_ap_read = dmem_ap_q_read, + .queue_ap_write = dmem_ap_q_write, + .queue_ap_abort = dmem_ap_q_abort, + .run = dmem_dp_run, +}; + +struct adapter_driver dmem_dap_adapter_driver = { + .name = "dmem", + .transport_ids = TRANSPORT_DAPDIRECT_SWD, + .transport_preferred_id = TRANSPORT_DAPDIRECT_SWD, + .commands = dmem_dap_command_handlers, + + .init = dmem_dap_init, + .quit = dmem_dap_quit, + .reset = dmem_dap_reset, + .speed = dmem_dap_speed, + .khz = dmem_dap_khz, + .speed_div = dmem_dap_speed_div, + + .dap_swd_ops = &dmem_dap_ops, +}; diff --git a/src/jtag/drivers/driver.c b/src/jtag/drivers/driver.c index 1ce18707dd..43101b8659 100644 --- a/src/jtag/drivers/driver.c +++ b/src/jtag/drivers/driver.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -49,7 +49,7 @@ static void jtag_callback_queue_reset(void) * */ int interface_jtag_add_ir_scan(struct jtag_tap *active, - const struct scan_field *in_fields, tap_state_t state) + const struct scan_field *in_fields, enum tap_state state) { size_t num_taps = jtag_tap_count_enabled(); @@ -76,16 +76,22 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active, if (tap == active) { /* if TAP is listed in input fields, copy the value */ - tap->bypass = 0; + tap->bypass = false; jtag_scan_field_clone(field, in_fields); } else { /* if a TAP isn't listed in input fields, set it to BYPASS */ - tap->bypass = 1; + tap->bypass = true; field->num_bits = tap->ir_length; - field->out_value = buf_set_ones(cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8)), tap->ir_length); + if (tap->ir_bypass_value) { + uint8_t *v = cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8)); + buf_set_u64(v, 0, tap->ir_length, tap->ir_bypass_value); + field->out_value = v; + } else { + field->out_value = buf_set_ones(cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8)), tap->ir_length); + } field->in_value = NULL; /* do not collect input for tap's in bypass */ } @@ -105,17 +111,26 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active, * */ int interface_jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, - const struct scan_field *in_fields, tap_state_t state) + const struct scan_field *in_fields, enum tap_state state) { /* count devices in bypass */ size_t bypass_devices = 0; + size_t all_devices = 0; for (struct jtag_tap *tap = jtag_tap_next_enabled(NULL); tap; tap = jtag_tap_next_enabled(tap)) { + all_devices++; + if (tap->bypass) bypass_devices++; } + if (all_devices == bypass_devices) { + LOG_ERROR("At least one TAP shouldn't be in BYPASS mode"); + + return ERROR_FAIL; + } + struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); struct scan_command *scan = cmd_queue_alloc(sizeof(struct scan_command)); struct scan_field *out_fields = cmd_queue_alloc((in_num_fields + bypass_devices) * sizeof(struct scan_field)); @@ -169,7 +184,7 @@ int interface_jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, } static int jtag_add_plain_scan(int num_bits, const uint8_t *out_bits, - uint8_t *in_bits, tap_state_t state, bool ir_scan) + uint8_t *in_bits, enum tap_state state, bool ir_scan) { struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); struct scan_command *scan = cmd_queue_alloc(sizeof(struct scan_command)); @@ -192,19 +207,19 @@ static int jtag_add_plain_scan(int num_bits, const uint8_t *out_bits, return ERROR_OK; } -int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state) +int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, enum tap_state state) { return jtag_add_plain_scan(num_bits, out_bits, in_bits, state, false); } -int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state) +int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, enum tap_state state) { return jtag_add_plain_scan(num_bits, out_bits, in_bits, state, true); } int interface_jtag_add_tlr(void) { - tap_state_t state = TAP_RESET; + enum tap_state state = TAP_RESET; /* allocate memory for a new list member */ struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); @@ -219,7 +234,7 @@ int interface_jtag_add_tlr(void) return ERROR_OK; } -int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state state) +int interface_add_tms_seq(unsigned int num_bits, const uint8_t *seq, enum tap_state state) { struct jtag_command *cmd; @@ -244,7 +259,7 @@ int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state return ERROR_OK; } -int interface_jtag_add_pathmove(int num_states, const tap_state_t *path) +int interface_jtag_add_pathmove(unsigned int num_states, const enum tap_state *path) { /* allocate memory for a new list member */ struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); @@ -255,15 +270,15 @@ int interface_jtag_add_pathmove(int num_states, const tap_state_t *path) cmd->cmd.pathmove = cmd_queue_alloc(sizeof(struct pathmove_command)); cmd->cmd.pathmove->num_states = num_states; - cmd->cmd.pathmove->path = cmd_queue_alloc(sizeof(tap_state_t) * num_states); + cmd->cmd.pathmove->path = cmd_queue_alloc(sizeof(enum tap_state) * num_states); - for (int i = 0; i < num_states; i++) + for (unsigned int i = 0; i < num_states; i++) cmd->cmd.pathmove->path[i] = path[i]; return ERROR_OK; } -int interface_jtag_add_runtest(int num_cycles, tap_state_t state) +int interface_jtag_add_runtest(unsigned int num_cycles, enum tap_state state) { /* allocate memory for a new list member */ struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); @@ -279,7 +294,7 @@ int interface_jtag_add_runtest(int num_cycles, tap_state_t state) return ERROR_OK; } -int interface_jtag_add_clocks(int num_cycles) +int interface_jtag_add_clocks(unsigned int num_cycles) { /* allocate memory for a new list member */ struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command)); @@ -326,7 +341,7 @@ int interface_jtag_add_sleep(uint32_t us) } /* add callback to end of queue */ -void interface_jtag_add_callback4(jtag_callback_t callback, +static void interface_jtag_add_callback4(jtag_callback_t callback, jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3) { @@ -380,7 +395,7 @@ static int jtag_convert_to_callback4(jtag_callback_data_t data0, return ERROR_OK; } -void interface_jtag_add_callback(jtag_callback1_t callback, jtag_callback_data_t data0) +static void interface_jtag_add_callback(jtag_callback1_t callback, jtag_callback_data_t data0) { jtag_add_callback4(jtag_convert_to_callback4, data0, (jtag_callback_data_t)callback, 0, 0); } diff --git a/src/jtag/drivers/dummy.c b/src/jtag/drivers/dummy.c index de216e35ad..471668c3ab 100644 --- a/src/jtag/drivers/dummy.c +++ b/src/jtag/drivers/dummy.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Øyvind Harboe * @@ -14,7 +14,7 @@ #include "hello.h" /* my private tap controller state, which tracks state for calling code */ -static tap_state_t dummy_state = TAP_RESET; +static enum tap_state dummy_state = TAP_RESET; static int dummy_clock; /* edge detector */ @@ -22,7 +22,7 @@ static int clock_count; /* count clocks in any stable state, only stable states static uint32_t dummy_data; -static bb_value_t dummy_read(void) +static enum bb_value dummy_read(void) { int data = 1 & dummy_data; dummy_data = (dummy_data >> 1) | (1 << 31); @@ -34,7 +34,7 @@ static int dummy_write(int tck, int tms, int tdi) /* TAP standard: "state transitions occur on rising edge of clock" */ if (tck != dummy_clock) { if (tck) { - tap_state_t old_state = dummy_state; + enum tap_state old_state = dummy_state; dummy_state = tap_state_transition(old_state, tms); if (old_state != dummy_state) { @@ -72,12 +72,12 @@ static int dummy_reset(int trst, int srst) return ERROR_OK; } -static int dummy_led(int on) +static int dummy_led(bool on) { return ERROR_OK; } -static struct bitbang_interface dummy_bitbang = { +static const struct bitbang_interface dummy_bitbang = { .read = &dummy_read, .write = &dummy_write, .blink = &dummy_led, @@ -140,7 +140,8 @@ static struct jtag_interface dummy_interface = { struct adapter_driver dummy_adapter_driver = { .name = "dummy", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = dummy_command_handlers, .init = &dummy_init, diff --git a/src/jtag/drivers/ep93xx.c b/src/jtag/drivers/ep93xx.c index e7c993b3bc..f3e1676f9f 100644 --- a/src/jtag/drivers/ep93xx.c +++ b/src/jtag/drivers/ep93xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -24,20 +24,20 @@ static uint8_t output_value; static int dev_mem_fd; -static void *gpio_controller; +static uint8_t *gpio_controller; static volatile uint8_t *gpio_data_register; static volatile uint8_t *gpio_data_direction_register; /* low level command set */ -static bb_value_t ep93xx_read(void); +static enum bb_value ep93xx_read(void); static int ep93xx_write(int tck, int tms, int tdi); static int ep93xx_reset(int trst, int srst); static int ep93xx_init(void); static int ep93xx_quit(void); -struct timespec ep93xx_zzzz; +static struct timespec ep93xx_zzzz; static struct jtag_interface ep93xx_interface = { .supported = DEBUG_CAP_TMS_SEQ, @@ -46,7 +46,8 @@ static struct jtag_interface ep93xx_interface = { struct adapter_driver ep93xx_adapter_driver = { .name = "ep93xx", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .init = ep93xx_init, .quit = ep93xx_quit, @@ -55,13 +56,13 @@ struct adapter_driver ep93xx_adapter_driver = { .jtag_ops = &ep93xx_interface, }; -static struct bitbang_interface ep93xx_bitbang = { +static const struct bitbang_interface ep93xx_bitbang = { .read = ep93xx_read, .write = ep93xx_write, - .blink = 0, + .blink = NULL, }; -static bb_value_t ep93xx_read(void) +static enum bb_value ep93xx_read(void) { return (*gpio_data_register & TDO_BIT) ? BB_HIGH : BB_LOW; } @@ -110,19 +111,16 @@ static int ep93xx_reset(int trst, int srst) static int set_gonk_mode(void) { - void *syscon; - uint32_t devicecfg; - - syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE, + void *syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dev_mem_fd, 0x80930000); if (syscon == MAP_FAILED) { LOG_ERROR("mmap: %s", strerror(errno)); return ERROR_JTAG_INIT_FAILED; } - devicecfg = *((volatile int *)(syscon + 0x80)); - *((volatile int *)(syscon + 0xc0)) = 0xaa; - *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000; + uint32_t devicecfg = *((volatile uint32_t *)((uintptr_t)syscon + 0x80)); + *((volatile uint32_t *)((uintptr_t)syscon + 0xc0)) = 0xaa; + *((volatile uint32_t *)((uintptr_t)syscon + 0x80)) = devicecfg | 0x08000000; munmap(syscon, 4096); diff --git a/src/jtag/drivers/esp_usb_jtag.c b/src/jtag/drivers/esp_usb_jtag.c index a73984a3a1..a133035110 100644 --- a/src/jtag/drivers/esp_usb_jtag.c +++ b/src/jtag/drivers/esp_usb_jtag.c @@ -1,20 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Espressif USB to Jtag adapter * * Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd. * - * Author: Jeroen Domburg <jeroen@espressif.com> * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -28,8 +16,6 @@ #include "bitq.h" #include "libusb_helper.h" -#define __packed __attribute__((packed)) - /* Holy Crap, it's protocol documentation, and it's even vendor-provided! @@ -122,7 +108,7 @@ descriptor. struct jtag_proto_caps_hdr { uint8_t proto_ver; /* Protocol version. Expects JTAG_PROTO_CAPS_VER for now. */ uint8_t length; /* of this plus any following descriptors */ -} __packed; +} __attribute__((packed)); /* start of the descriptor headers */ #define JTAG_BUILTIN_DESCR_START_OFF 0 /* Devices with builtin usb jtag */ @@ -145,7 +131,7 @@ of caps header to assume this. If no such caps exist, assume a minimum (in) buff struct jtag_gen_hdr { uint8_t type; uint8_t length; -} __packed; +} __attribute__((packed)); struct jtag_proto_caps_speed_apb { uint8_t type; /* Type, always JTAG_PROTO_CAPS_SPEED_APB_TYPE */ @@ -153,7 +139,7 @@ struct jtag_proto_caps_speed_apb { uint8_t apb_speed_10khz[2]; /* ABP bus speed, in 10KHz increments. Base speed is half this. */ uint8_t div_min[2]; /* minimum divisor (to base speed), inclusive */ uint8_t div_max[2]; /* maximum divisor (to base speed), inclusive */ -} __packed; +} __attribute__((packed)); #define JTAG_PROTO_CAPS_DATA_LEN 255 #define JTAG_PROTO_CAPS_SPEED_APB_TYPE 1 @@ -501,7 +487,7 @@ static int esp_usb_jtag_init(void) bitq_interface->in_rdy = esp_usb_jtag_in_rdy; bitq_interface->in = esp_usb_jtag_in; - int r = jtag_libusb_open(vids, pids, &priv->usb_device, NULL); + int r = jtag_libusb_open(vids, pids, NULL, &priv->usb_device, NULL); if (r != ERROR_OK) { LOG_ERROR("esp_usb_jtag: could not find or open device!"); goto out; @@ -520,11 +506,13 @@ static int esp_usb_jtag_init(void) * 1- With the minimum size required to get to know the total length of that struct, * 2- Then exactly the length of that struct. */ uint8_t jtag_caps_desc[JTAG_PROTO_CAPS_DATA_LEN]; - int jtag_caps_read_len = jtag_libusb_control_transfer(priv->usb_device, + int jtag_caps_read_len; + r = jtag_libusb_control_transfer(priv->usb_device, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_STANDARD | LIBUSB_RECIPIENT_DEVICE, LIBUSB_REQUEST_GET_DESCRIPTOR, esp_usb_jtag_caps, 0, - (char *)jtag_caps_desc, JTAG_PROTO_CAPS_DATA_LEN, LIBUSB_TIMEOUT_MS); - if (jtag_caps_read_len <= 0) { + (char *)jtag_caps_desc, JTAG_PROTO_CAPS_DATA_LEN, LIBUSB_TIMEOUT_MS, + &jtag_caps_read_len); + if (r != ERROR_OK) { LOG_ERROR("esp_usb_jtag: could not retrieve jtag_caps descriptor!"); goto out; } @@ -594,7 +582,8 @@ static int esp_usb_jtag_init(void) 0, NULL, 0, - LIBUSB_TIMEOUT_MS); + LIBUSB_TIMEOUT_MS, + NULL); return ERROR_OK; @@ -651,7 +640,7 @@ static int esp_usb_jtag_speed(int divisor) LOG_DEBUG("esp_usb_jtag: setting divisor %d", divisor); jtag_libusb_control_transfer(priv->usb_device, - LIBUSB_REQUEST_TYPE_VENDOR, VEND_JTAG_SETDIV, divisor, 0, NULL, 0, LIBUSB_TIMEOUT_MS); + LIBUSB_REQUEST_TYPE_VENDOR, VEND_JTAG_SETDIV, divisor, 0, NULL, 0, LIBUSB_TIMEOUT_MS, NULL); return ERROR_OK; } @@ -662,8 +651,8 @@ COMMAND_HANDLER(esp_usb_jtag_tdo_cmd) if (!priv->usb_device) return ERROR_FAIL; int r = jtag_libusb_control_transfer(priv->usb_device, - LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR, VEND_JTAG_GETTDO, 0, 0, &tdo, 1, LIBUSB_TIMEOUT_MS); - if (r < 1) + LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR, VEND_JTAG_GETTDO, 0, 0, &tdo, 1, LIBUSB_TIMEOUT_MS, NULL); + if (r != ERROR_OK) return r; command_print(CMD, "%d", tdo); @@ -699,7 +688,7 @@ COMMAND_HANDLER(esp_usb_jtag_setio_cmd) d |= VEND_JTAG_SETIO_SRST; jtag_libusb_control_transfer(priv->usb_device, - 0x40, VEND_JTAG_SETIO, d, 0, NULL, 0, LIBUSB_TIMEOUT_MS); + 0x40, VEND_JTAG_SETIO, d, 0, NULL, 0, LIBUSB_TIMEOUT_MS, NULL); return ERROR_OK; } @@ -795,7 +784,8 @@ static struct jtag_interface esp_usb_jtag_interface = { struct adapter_driver esp_usb_adapter_driver = { .name = "esp_usb_jtag", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = esp_usb_jtag_commands, .init = esp_usb_jtag_init, diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c index e5d80559d1..f88e4b9408 100644 --- a/src/jtag/drivers/ft232r.c +++ b/src/jtag/drivers/ft232r.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 Serge Vakulenko * @@ -177,7 +177,7 @@ static void ft232r_increase_buf_size(size_t new_buf_size) */ static void ft232r_write(int tck, int tms, int tdi) { - unsigned out_value = (1<<ntrst_gpio) | (1<<nsysrst_gpio); + unsigned int out_value = (1 << ntrst_gpio) | (1 << nsysrst_gpio); if (tck) out_value |= (1<<tck_gpio); if (tms) @@ -201,7 +201,7 @@ static void ft232r_write(int tck, int tms, int tdi) */ static void ft232r_reset(int trst, int srst) { - unsigned out_value = (1<<ntrst_gpio) | (1<<nsysrst_gpio); + unsigned int out_value = (1 << ntrst_gpio) | (1 << nsysrst_gpio); LOG_DEBUG("ft232r_reset(%d,%d)", trst, srst); if (trst == 1) @@ -235,7 +235,7 @@ static int ft232r_speed(int divisor) if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, - SIO_SET_BAUD_RATE, divisor, 0, 0, 0, 1000) != 0) { + SIO_SET_BAUD_RATE, divisor, 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("cannot set baud rate"); return ERROR_JTAG_DEVICE_ERROR; } @@ -246,7 +246,7 @@ static int ft232r_init(void) { uint16_t avids[] = {ft232r_vid, 0}; uint16_t apids[] = {ft232r_pid, 0}; - if (jtag_libusb_open(avids, apids, &adapter, NULL)) { + if (jtag_libusb_open(avids, apids, NULL, &adapter, NULL)) { const char *ft232r_serial_desc = adapter_get_required_serial(); LOG_ERROR("ft232r not found: vid=%04x, pid=%04x, serial=%s\n", ft232r_vid, ft232r_pid, (!ft232r_serial_desc) ? "[any]" : ft232r_serial_desc); @@ -266,7 +266,7 @@ static int ft232r_init(void) /* Reset the device. */ if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, - SIO_RESET, 0, 0, 0, 0, 1000) != 0) { + SIO_RESET, 0, 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("unable to reset device"); return ERROR_JTAG_INIT_FAILED; } @@ -275,26 +275,26 @@ static int ft232r_init(void) if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, SIO_SET_BITMODE, (1<<tck_gpio) | (1<<tdi_gpio) | (1<<tms_gpio) | (1<<ntrst_gpio) | (1<<nsysrst_gpio) | 0x400, - 0, 0, 0, 1000) != 0) { + 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("cannot set sync bitbang mode"); return ERROR_JTAG_INIT_FAILED; } /* Exactly 500 nsec between updates. */ - unsigned divisor = 1; + unsigned int divisor = 1; unsigned char latency_timer = 1; /* Frequency divisor is 14-bit non-zero value. */ if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, SIO_SET_BAUD_RATE, divisor, - 0, 0, 0, 1000) != 0) { + 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("cannot set baud rate"); return ERROR_JTAG_INIT_FAILED; } if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, - SIO_SET_LATENCY_TIMER, latency_timer, 0, 0, 0, 1000) != 0) { + SIO_SET_LATENCY_TIMER, latency_timer, 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("unable to set latency timer"); return ERROR_JTAG_INIT_FAILED; } @@ -315,7 +315,7 @@ static int ft232r_quit(void) if (jtag_libusb_control_transfer(adapter, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, SIO_SET_BITMODE, ft232r_restore_bitmode, - 0, 0, 0, 1000) != 0) { + 0, NULL, 0, 1000, NULL) != ERROR_OK) { LOG_ERROR("cannot set bitmode to restore serial port"); } } @@ -622,7 +622,7 @@ static const struct command_registration ft232r_command_handlers[] = { * Synchronous bitbang protocol implementation. */ -static void syncbb_end_state(tap_state_t state) +static void syncbb_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -654,13 +654,13 @@ static void syncbb_state_move(int skip) */ static int syncbb_execute_tms(struct jtag_command *cmd) { - unsigned num_bits = cmd->cmd.tms->num_bits; + unsigned int num_bits = cmd->cmd.tms->num_bits; const uint8_t *bits = cmd->cmd.tms->bits; - LOG_DEBUG_IO("TMS: %d bits", num_bits); + LOG_DEBUG_IO("TMS: %u bits", num_bits); int tms = 0; - for (unsigned i = 0; i < num_bits; i++) { + for (unsigned int i = 0; i < num_bits; i++) { tms = ((bits[i/8] >> (i % 8)) & 1); ft232r_write(0, tms, 0); ft232r_write(1, tms, 0); @@ -672,7 +672,7 @@ static int syncbb_execute_tms(struct jtag_command *cmd) static void syncbb_path_move(struct pathmove_command *cmd) { - int num_states = cmd->num_states; + unsigned int num_states = cmd->num_states; int state_count; int tms = 0; @@ -702,11 +702,10 @@ static void syncbb_path_move(struct pathmove_command *cmd) tap_set_end_state(tap_get_state()); } -static void syncbb_runtest(int num_cycles) +static void syncbb_runtest(unsigned int num_cycles) { - int i; - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -715,7 +714,7 @@ static void syncbb_runtest(int num_cycles) } /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { ft232r_write(0, 0, 0); ft232r_write(1, 0, 0); } @@ -735,13 +734,12 @@ static void syncbb_runtest(int num_cycles) * this function checks the current stable state to decide on the value of TMS * to use. */ -static void syncbb_stableclocks(int num_cycles) +static void syncbb_stableclocks(unsigned int num_cycles) { int tms = (tap_get_state() == TAP_RESET ? 1 : 0); - int i; /* send num_cycles clocks onto the cable */ - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { ft232r_write(1, tms, 0); ft232r_write(0, tms, 0); } @@ -749,7 +747,7 @@ static void syncbb_stableclocks(int num_cycles) static void syncbb_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size) { - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); int bit_cnt, bit0_index; if (!((!ir_scan && (tap_get_state() == TAP_DRSHIFT)) || (ir_scan && (tap_get_state() == TAP_IRSHIFT)))) { @@ -803,9 +801,9 @@ static void syncbb_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int } } -static int syncbb_execute_queue(void) +static int syncbb_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -832,7 +830,7 @@ static int syncbb_execute_queue(void) break; case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, + LOG_DEBUG_IO("runtest %u cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state)); syncbb_end_state(cmd->cmd.runtest->end_state); @@ -854,7 +852,7 @@ static int syncbb_execute_queue(void) break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %s", cmd->cmd.pathmove->num_states, + LOG_DEBUG_IO("pathmove: %u states, end in %s", cmd->cmd.pathmove->num_states, tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1])); syncbb_path_move(cmd->cmd.pathmove); @@ -902,7 +900,8 @@ static struct jtag_interface ft232r_interface = { struct adapter_driver ft232r_adapter_driver = { .name = "ft232r", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = ft232r_command_handlers, .init = ft232r_init, diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c index 3c902a7974..a8f6f60159 100644 --- a/src/jtag/drivers/ftdi.c +++ b/src/jtag/drivers/ftdi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /************************************************************************** * Copyright (C) 2012 by Andreas Fritiofson * @@ -64,6 +64,7 @@ #include <transport/transport.h> #include <helper/time_support.h> #include <helper/log.h> +#include <helper/nvp.h> #if IS_CYGWIN == 1 #include <windows.h> @@ -181,7 +182,7 @@ static int ftdi_set_signal(const struct signal *s, char value) oe = s->invert_oe; break; default: - assert(0 && "invalid signal level specifier"); + LOG_ERROR("invalid signal level specifier \'%c\'(0x%02x)", value, value); return ERROR_FAIL; } @@ -237,9 +238,9 @@ static int ftdi_get_signal(const struct signal *s, uint16_t *value_out) * * @param goal_state is the destination state for the move. */ -static void move_to_state(tap_state_t goal_state) +static void move_to_state(enum tap_state goal_state) { - tap_state_t start_state = tap_get_state(); + enum tap_state start_state = tap_get_state(); /* goal_state is 1/2 of a tuple/pair of states which allow convenient lookup of the required TMS pattern to move to this state from the @@ -298,7 +299,7 @@ static int ftdi_khz(int khz, int *jtag_speed) return ERROR_OK; } -static void ftdi_end_state(tap_state_t state) +static void ftdi_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -310,10 +311,9 @@ static void ftdi_end_state(tap_state_t state) static void ftdi_execute_runtest(struct jtag_command *cmd) { - int i; uint8_t zero = 0; - LOG_DEBUG_IO("runtest %i cycles, end in %s", + LOG_DEBUG_IO("runtest %u cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state)); @@ -321,10 +321,10 @@ static void ftdi_execute_runtest(struct jtag_command *cmd) move_to_state(TAP_IDLE); /* TODO: Reuse ftdi_execute_stableclocks */ - i = cmd->cmd.runtest->num_cycles; + unsigned int i = cmd->cmd.runtest->num_cycles; while (i > 0) { /* there are no state transitions in this code, so omit state tracking */ - unsigned this_len = i > 7 ? 7 : i; + unsigned int this_len = i > 7 ? 7 : i; mpsse_clock_tms_cs_out(mpsse_ctx, &zero, 0, this_len, false, ftdi_jtag_mode); i -= this_len; } @@ -334,7 +334,7 @@ static void ftdi_execute_runtest(struct jtag_command *cmd) if (tap_get_state() != tap_get_end_state()) move_to_state(tap_get_end_state()); - LOG_DEBUG_IO("runtest: %i, end in %s", + LOG_DEBUG_IO("runtest: %u, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(tap_get_end_state())); } @@ -357,7 +357,7 @@ static void ftdi_execute_statemove(struct jtag_command *cmd) */ static void ftdi_execute_tms(struct jtag_command *cmd) { - LOG_DEBUG_IO("TMS: %d bits", cmd->cmd.tms->num_bits); + LOG_DEBUG_IO("TMS: %u bits", cmd->cmd.tms->num_bits); /* TODO: Missing tap state tracking, also missing from ft2232.c! */ mpsse_clock_tms_cs_out(mpsse_ctx, @@ -370,15 +370,15 @@ static void ftdi_execute_tms(struct jtag_command *cmd) static void ftdi_execute_pathmove(struct jtag_command *cmd) { - tap_state_t *path = cmd->cmd.pathmove->path; - int num_states = cmd->cmd.pathmove->num_states; + enum tap_state *path = cmd->cmd.pathmove->path; + unsigned int num_states = cmd->cmd.pathmove->num_states; - LOG_DEBUG_IO("pathmove: %i states, current: %s end: %s", num_states, + LOG_DEBUG_IO("pathmove: %u states, current: %s end: %s", num_states, tap_state_name(tap_get_state()), tap_state_name(path[num_states-1])); int state_count = 0; - unsigned bit_count = 0; + unsigned int bit_count = 0; uint8_t tms_byte = 0; LOG_DEBUG_IO("-"); @@ -431,7 +431,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd) LOG_DEBUG_IO("discarding trailing empty field"); } - if (cmd->cmd.scan->num_fields == 0) { + if (!cmd->cmd.scan->num_fields) { LOG_DEBUG_IO("empty scan, doing nothing"); return; } @@ -447,11 +447,11 @@ static void ftdi_execute_scan(struct jtag_command *cmd) ftdi_end_state(cmd->cmd.scan->end_state); struct scan_field *field = cmd->cmd.scan->fields; - unsigned scan_size = 0; + unsigned int scan_size = 0; - for (int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { scan_size += field->num_bits; - LOG_DEBUG_IO("%s%s field %d/%d %d bits", + LOG_DEBUG_IO("%s%s field %u/%u %u bits", field->in_value ? "in" : "", field->out_value ? "out" : "", i, @@ -575,7 +575,7 @@ static void ftdi_execute_stableclocks(struct jtag_command *cmd) /* this is only allowed while in a stable state. A check for a stable * state was done in jtag_add_clocks() */ - int num_cycles = cmd->cmd.stableclocks->num_cycles; + unsigned int num_cycles = cmd->cmd.stableclocks->num_cycles; /* 7 bits of either ones or zeros. */ uint8_t tms = tap_get_state() == TAP_RESET ? 0x7f : 0x00; @@ -584,12 +584,12 @@ static void ftdi_execute_stableclocks(struct jtag_command *cmd) * the correct level and remain there during the scan */ while (num_cycles > 0) { /* there are no state transitions in this code, so omit state tracking */ - unsigned this_len = num_cycles > 7 ? 7 : num_cycles; + unsigned int this_len = num_cycles > 7 ? 7 : num_cycles; mpsse_clock_tms_cs_out(mpsse_ctx, &tms, 0, this_len, false, ftdi_jtag_mode); num_cycles -= this_len; } - LOG_DEBUG_IO("clocks %i while in %s", + LOG_DEBUG_IO("clocks %u while in %s", cmd->cmd.stableclocks->num_cycles, tap_state_name(tap_get_state())); } @@ -624,14 +624,14 @@ static void ftdi_execute_command(struct jtag_command *cmd) } } -static int ftdi_execute_queue(void) +static int ftdi_execute_queue(struct jtag_command *cmd_queue) { /* blink, if the current layout has that feature */ struct signal *led = find_signal_by_name("LED"); if (led) ftdi_set_signal(led, '1'); - for (struct jtag_command *cmd = jtag_command_queue; cmd; cmd = cmd->next) { + for (struct jtag_command *cmd = cmd_queue; cmd; cmd = cmd->next) { /* fill the write buffer with the desired command */ ftdi_execute_command(cmd); } @@ -658,13 +658,8 @@ static int ftdi_initialize(void) return ERROR_JTAG_INIT_FAILED; } - for (int i = 0; ftdi_vid[i] || ftdi_pid[i]; i++) { - mpsse_ctx = mpsse_open(&ftdi_vid[i], &ftdi_pid[i], ftdi_device_desc, + mpsse_ctx = mpsse_open(ftdi_vid, ftdi_pid, ftdi_device_desc, adapter_get_required_serial(), adapter_usb_get_location(), ftdi_channel); - if (mpsse_ctx) - break; - } - if (!mpsse_ctx) return ERROR_JTAG_INIT_FAILED; @@ -755,7 +750,7 @@ COMMAND_HANDLER(ftdi_handle_layout_signal_command) uint16_t input_mask = 0; bool invert_oe = false; uint16_t oe_mask = 0; - for (unsigned i = 1; i < CMD_ARGC; i += 2) { + for (unsigned int i = 1; i < CMD_ARGC; i += 2) { if (strcmp("-data", CMD_ARGV[i]) == 0) { invert_data = false; COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i + 1], data_mask); @@ -841,7 +836,7 @@ COMMAND_HANDLER(ftdi_handle_set_signal_command) /* fallthrough */ default: LOG_ERROR("unknown signal level '%s', use 0, 1 or z", CMD_ARGV[1]); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } return mpsse_flush(mpsse_ctx); @@ -856,7 +851,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command) uint16_t sig_data = 0; sig = find_signal_by_name(CMD_ARGV[0]); if (!sig) { - LOG_ERROR("interface configuration doesn't define signal '%s'", CMD_ARGV[0]); + command_print(CMD, "interface configuration doesn't define signal '%s'", CMD_ARGV[0]); return ERROR_FAIL; } @@ -864,7 +859,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command) if (ret != ERROR_OK) return ret; - LOG_USER("Signal %s = %#06x", sig->name, sig_data); + command_print(CMD, "%#06x", sig_data); return ERROR_OK; } @@ -884,7 +879,7 @@ COMMAND_HANDLER(ftdi_handle_vid_pid_command) CMD_ARGC -= 1; } - unsigned i; + unsigned int i; for (i = 0; i < CMD_ARGC; i += 2) { COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i], ftdi_vid[i >> 1]); COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i + 1], ftdi_pid[i >> 1]); @@ -901,22 +896,22 @@ COMMAND_HANDLER(ftdi_handle_vid_pid_command) COMMAND_HANDLER(ftdi_handle_tdo_sample_edge_command) { - struct jim_nvp *n; - static const struct jim_nvp nvp_ftdi_jtag_modes[] = { + const struct nvp *n; + static const struct nvp nvp_ftdi_jtag_modes[] = { { .name = "rising", .value = JTAG_MODE }, { .name = "falling", .value = JTAG_MODE_ALT }, { .name = NULL, .value = -1 }, }; if (CMD_ARGC > 0) { - n = jim_nvp_name2value_simple(nvp_ftdi_jtag_modes, CMD_ARGV[0]); + n = nvp_name2value(nvp_ftdi_jtag_modes, CMD_ARGV[0]); if (!n->name) return ERROR_COMMAND_SYNTAX_ERROR; ftdi_jtag_mode = n->value; } - n = jim_nvp_value2name_simple(nvp_ftdi_jtag_modes, ftdi_jtag_mode); + n = nvp_value2name(nvp_ftdi_jtag_modes, ftdi_jtag_mode); command_print(CMD, "ftdi samples TDO on %s edge of TCK", n->name); return ERROR_OK; @@ -1092,7 +1087,8 @@ static int ftdi_swd_run_queue(void) /* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */ bool check_ack = swd_cmd_returns_ack(swd_cmd_queue[i].cmd); - LOG_DEBUG_IO("%s%s %s %s reg %X = %08"PRIx32, + LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK) ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO, + "%s%s %s %s reg %X = %08" PRIx32, check_ack ? "" : "ack ignored ", ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", swd_cmd_queue[i].cmd & SWD_CMD_APNDP ? "AP" : "DP", @@ -1251,8 +1247,6 @@ static const struct swd_driver ftdi_swd = { .run = ftdi_swd_run_queue, }; -static const char * const ftdi_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface ftdi_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = ftdi_execute_queue, @@ -1260,7 +1254,8 @@ static struct jtag_interface ftdi_interface = { struct adapter_driver ftdi_adapter_driver = { .name = "ftdi", - .transports = ftdi_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = ftdi_command_handlers, .init = ftdi_initialize, diff --git a/src/jtag/drivers/gw16012.c b/src/jtag/drivers/gw16012.c index d5a0b23f00..98f7754223 100644 --- a/src/jtag/drivers/gw16012.c +++ b/src/jtag/drivers/gw16012.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -133,7 +133,7 @@ static void gw16012_reset(int trst, int srst) gw16012_control(0x0b); } -static void gw16012_end_state(tap_state_t state) +static void gw16012_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -185,10 +185,9 @@ static void gw16012_path_move(struct pathmove_command *cmd) tap_set_end_state(tap_get_state()); } -static void gw16012_runtest(int num_cycles) +static void gw16012_runtest(unsigned int num_cycles) { - tap_state_t saved_end_state = tap_get_end_state(); - int i; + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -196,7 +195,7 @@ static void gw16012_runtest(int num_cycles) gw16012_state_move(); } - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { gw16012_control(0x0); /* single-bit mode */ gw16012_data(0x0); /* TMS cycle with TMS low */ } @@ -210,7 +209,7 @@ static void gw16012_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int { int bits_left = scan_size; int bit_count = 0; - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); uint8_t scan_out, scan_in; /* only if we're not already in the correct Shift state */ @@ -270,9 +269,9 @@ static void gw16012_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int } } -static int gw16012_execute_queue(void) +static int gw16012_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -292,7 +291,7 @@ static int gw16012_execute_queue(void) gw16012_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); break; case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); gw16012_end_state(cmd->cmd.runtest->end_state); gw16012_runtest(cmd->cmd.runtest->num_cycles); @@ -462,6 +461,8 @@ static int gw16012_init(void) { uint8_t status_port; + LOG_WARNING("This adapter is deprecated and support will be removed in the next release!"); + if (gw16012_init_device() != ERROR_OK) return ERROR_JTAG_INIT_FAILED; @@ -515,7 +516,8 @@ static struct jtag_interface gw16012_interface = { struct adapter_driver gw16012_adapter_driver = { .name = "gw16012", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = gw16012_command_handlers, .init = gw16012_init, diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c index 734c05ff0a..a4a76ca5a3 100644 --- a/src/jtag/drivers/imx_gpio.c +++ b/src/jtag/drivers/imx_gpio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Grzegorz Kostka, kostka.grzegorz@gmail.com * @@ -72,7 +72,7 @@ static inline bool gpio_level(int g) return pio_base[g / 32].dr >> (g & 0x1F) & 1; } -static bb_value_t imx_gpio_read(void); +static enum bb_value imx_gpio_read(void); static int imx_gpio_write(int tck, int tms, int tdi); static int imx_gpio_swdio_read(void); @@ -82,7 +82,7 @@ static int imx_gpio_swd_write(int swclk, int swdio); static int imx_gpio_init(void); static int imx_gpio_quit(void); -static struct bitbang_interface imx_gpio_bitbang = { +static const struct bitbang_interface imx_gpio_bitbang = { .read = imx_gpio_read, .write = imx_gpio_write, .swdio_read = imx_gpio_swdio_read, @@ -118,7 +118,7 @@ static int speed_coeff = 50000; static int speed_offset = 100; static unsigned int jtag_delay; -static bb_value_t imx_gpio_read(void) +static enum bb_value imx_gpio_read(void) { return gpio_level(tdo_gpio) ? BB_HIGH : BB_LOW; } @@ -417,8 +417,6 @@ static const struct command_registration imx_gpio_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static const char * const imx_gpio_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface imx_gpio_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = bitbang_execute_queue, @@ -426,7 +424,8 @@ static struct jtag_interface imx_gpio_interface = { struct adapter_driver imx_gpio_adapter_driver = { .name = "imx_gpio", - .transports = imx_gpio_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = imx_gpio_command_handlers, .init = imx_gpio_init, diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c index 098bbb2697..f6bb3099d6 100644 --- a/src/jtag/drivers/jlink.c +++ b/src/jtag/drivers/jlink.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Juergen Stuber <juergen@jstuber.net> * @@ -23,6 +23,7 @@ #include <stdint.h> #include <math.h> +#include <string.h> #include <jtag/interface.h> #include <jtag/swd.h> @@ -40,8 +41,6 @@ static struct jaylink_connection connlist[JAYLINK_MAX_CONNECTIONS]; static enum jaylink_jtag_version jtag_command_version; static uint8_t caps[JAYLINK_DEV_EXT_CAPS_SIZE]; -static uint32_t serial_number; -static bool use_serial_number; static bool use_usb_location; static enum jaylink_usb_address usb_address; static bool use_usb_address; @@ -78,11 +77,11 @@ static struct device_config config; static struct device_config tmp_config; /* Queue command functions */ -static void jlink_end_state(tap_state_t state); +static void jlink_end_state(enum tap_state state); static void jlink_state_move(void); -static void jlink_path_move(int num_states, tap_state_t *path); -static void jlink_stableclocks(int num_cycles); -static void jlink_runtest(int num_cycles); +static void jlink_path_move(unsigned int num_states, enum tap_state *path); +static void jlink_stableclocks(unsigned int num_cycles); +static void jlink_runtest(unsigned int num_cycles); static void jlink_reset(int trst, int srst); static int jlink_reset_safe(int trst, int srst); static int jlink_swd_run_queue(void); @@ -104,10 +103,10 @@ static int jlink_flush(void); * @param in_offset A bit offset for TDO data. * @param length Amount of bits to transfer out and in. */ -static void jlink_clock_data(const uint8_t *out, unsigned out_offset, - const uint8_t *tms_out, unsigned tms_offset, - uint8_t *in, unsigned in_offset, - unsigned length); +static void jlink_clock_data(const uint8_t *out, unsigned int out_offset, + const uint8_t *tms_out, unsigned int tms_offset, + uint8_t *in, unsigned int in_offset, + unsigned int length); static enum tap_state jlink_last_state = TAP_RESET; static int queued_retval; @@ -140,7 +139,7 @@ static void jlink_execute_statemove(struct jtag_command *cmd) static void jlink_execute_pathmove(struct jtag_command *cmd) { - LOG_DEBUG_IO("pathmove: %i states, end in %i", + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); @@ -159,7 +158,7 @@ static void jlink_execute_scan(struct jtag_command *cmd) LOG_DEBUG("discarding trailing empty field"); } - if (cmd->cmd.scan->num_fields == 0) { + if (!cmd->cmd.scan->num_fields) { LOG_DEBUG("empty scan, doing nothing"); return; } @@ -179,11 +178,11 @@ static void jlink_execute_scan(struct jtag_command *cmd) jlink_end_state(cmd->cmd.scan->end_state); struct scan_field *field = cmd->cmd.scan->fields; - unsigned scan_size = 0; + unsigned int scan_size = 0; - for (int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++, field++) { scan_size += field->num_bits; - LOG_DEBUG_IO("%s%s field %d/%d %d bits", + LOG_DEBUG_IO("%s%s field %u/%u %u bits", field->in_value ? "in" : "", field->out_value ? "out" : "", i, @@ -276,10 +275,10 @@ static int jlink_execute_command(struct jtag_command *cmd) return ERROR_OK; } -static int jlink_execute_queue(void) +static int jlink_execute_queue(struct jtag_command *cmd_queue) { int ret; - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; while (cmd) { ret = jlink_execute_command(cmd); @@ -561,9 +560,29 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) } use_usb_location = !!adapter_usb_get_location(); + const char *adapter_serial = adapter_get_required_serial(); - if (!use_serial_number && !use_usb_address && !use_usb_location && num_devices > 1) { + if (!adapter_serial && !use_usb_address && !use_usb_location && num_devices > 1) { LOG_ERROR("Multiple devices found, specify the desired device"); + LOG_INFO("Found devices:"); + for (size_t i = 0; devs[i]; i++) { + uint32_t serial; + ret = jaylink_device_get_serial_number(devs[i], &serial); + if (ret == JAYLINK_ERR_NOT_AVAILABLE) { + continue; + } else if (ret != JAYLINK_OK) { + LOG_WARNING("jaylink_device_get_serial_number() failed: %s", + jaylink_strerror(ret)); + continue; + } + char name[JAYLINK_NICKNAME_MAX_LENGTH]; + int name_ret = jaylink_device_get_nickname(devs[i], name); + if (name_ret == JAYLINK_OK) + LOG_INFO("Device %zu serial: %" PRIu32 ", nickname %s", i, serial, name); + else + LOG_INFO("Device %zu serial: %" PRIu32, i, serial); + } + jaylink_free_devices(devs, true); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; @@ -571,23 +590,39 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) *found_device = false; + uint32_t serial_number; + ret = jaylink_parse_serial_number(adapter_serial, &serial_number); + if (ret != JAYLINK_OK) + serial_number = 0; + for (size_t i = 0; devs[i]; i++) { struct jaylink_device *dev = devs[i]; - if (use_serial_number) { - uint32_t tmp; - ret = jaylink_device_get_serial_number(dev, &tmp); - - if (ret == JAYLINK_ERR_NOT_AVAILABLE) { - continue; - } else if (ret != JAYLINK_OK) { - LOG_WARNING("jaylink_device_get_serial_number() failed: %s", - jaylink_strerror(ret)); - continue; + if (adapter_serial) { + /* + * Treat adapter serial as a nickname first as it can also be numeric. + * If it fails to match (optional) device nickname try to compare + * adapter serial with the actual device serial number. + */ + char nickname[JAYLINK_NICKNAME_MAX_LENGTH]; + ret = jaylink_device_get_nickname(dev, nickname); + if (ret != JAYLINK_OK || strcmp(nickname, adapter_serial) != 0) { + if (!serial_number) + continue; + + uint32_t tmp; + ret = jaylink_device_get_serial_number(dev, &tmp); + if (ret == JAYLINK_ERR_NOT_AVAILABLE) { + continue; + } else if (ret != JAYLINK_OK) { + LOG_WARNING("jaylink_device_get_serial_number() failed: %s", + jaylink_strerror(ret)); + continue; + } + + if (serial_number != tmp) + continue; } - - if (serial_number != tmp) - continue; } if (use_usb_address) { @@ -656,29 +691,15 @@ static int jlink_init(void) return ERROR_JTAG_INIT_FAILED; } - const char *serial = adapter_get_required_serial(); - if (serial) { - ret = jaylink_parse_serial_number(serial, &serial_number); - if (ret == JAYLINK_ERR) { - LOG_ERROR("Invalid serial number: %s", serial); - jaylink_exit(jayctx); - return ERROR_JTAG_INIT_FAILED; - } - if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_parse_serial_number() failed: %s", jaylink_strerror(ret)); - jaylink_exit(jayctx); - return ERROR_JTAG_INIT_FAILED; - } - use_serial_number = true; + if (adapter_get_required_serial()) use_usb_address = false; - } bool found_device; ret = jlink_open_device(JAYLINK_HIF_USB, &found_device); if (ret != ERROR_OK) return ret; - if (!found_device && use_serial_number) { + if (!found_device && adapter_get_required_serial()) { ret = jlink_open_device(JAYLINK_HIF_TCP, &found_device); if (ret != ERROR_OK) return ret; @@ -861,7 +882,7 @@ static int jlink_quit(void) /***************************************************************************/ /* Queue command implementations */ -static void jlink_end_state(tap_state_t state) +static void jlink_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -885,12 +906,11 @@ static void jlink_state_move(void) tap_set_state(tap_get_end_state()); } -static void jlink_path_move(int num_states, tap_state_t *path) +static void jlink_path_move(unsigned int num_states, enum tap_state *path) { - int i; uint8_t tms = 0xff; - for (i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (path[i] == tap_state_transition(tap_get_state(), false)) jlink_clock_data(NULL, 0, NULL, 0, NULL, 0, 1); else if (path[i] == tap_state_transition(tap_get_state(), true)) @@ -907,19 +927,17 @@ static void jlink_path_move(int num_states, tap_state_t *path) tap_set_end_state(tap_get_state()); } -static void jlink_stableclocks(int num_cycles) +static void jlink_stableclocks(unsigned int num_cycles) { - int i; - uint8_t tms = tap_get_state() == TAP_RESET; /* Execute num_cycles. */ - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) jlink_clock_data(NULL, 0, &tms, 0, NULL, 0, 1); } -static void jlink_runtest(int num_cycles) +static void jlink_runtest(unsigned int num_cycles) { - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* Only do a state_move when we're not already in IDLE. */ if (tap_get_state() != TAP_IDLE) { @@ -964,25 +982,18 @@ static int jlink_reset_safe(int trst, int srst) COMMAND_HANDLER(jlink_usb_command) { - int tmp; - - if (CMD_ARGC != 1) { - command_print(CMD, "Need exactly one argument for jlink usb"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } - if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) { - command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); - return ERROR_FAIL; - } + unsigned int tmp; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], tmp); - if (tmp < JAYLINK_USB_ADDRESS_0 || tmp > JAYLINK_USB_ADDRESS_3) { + if (tmp > JAYLINK_USB_ADDRESS_3) { command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); - return ERROR_FAIL; + return ERROR_COMMAND_ARGUMENT_INVALID; } usb_address = tmp; - use_usb_address = true; return ERROR_OK; @@ -1040,41 +1051,37 @@ COMMAND_HANDLER(jlink_handle_free_memory_command) COMMAND_HANDLER(jlink_handle_jlink_jtag_command) { - int tmp; - int version; - if (!CMD_ARGC) { + unsigned int version; + switch (jtag_command_version) { - case JAYLINK_JTAG_VERSION_2: - version = 2; - break; - case JAYLINK_JTAG_VERSION_3: - version = 3; - break; - default: - return ERROR_FAIL; + case JAYLINK_JTAG_VERSION_2: + version = 2; + break; + case JAYLINK_JTAG_VERSION_3: + version = 3; + break; + default: + return ERROR_FAIL; } - command_print(CMD, "JTAG command version: %i", version); + command_print(CMD, "JTAG command version: %u", version); } else if (CMD_ARGC == 1) { - if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) { - command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); - return ERROR_COMMAND_SYNTAX_ERROR; - } + uint8_t tmp; + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], tmp); switch (tmp) { - case 2: - jtag_command_version = JAYLINK_JTAG_VERSION_2; - break; - case 3: - jtag_command_version = JAYLINK_JTAG_VERSION_3; - break; - default: - command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); - return ERROR_COMMAND_SYNTAX_ERROR; + case 2: + jtag_command_version = JAYLINK_JTAG_VERSION_2; + break; + case 3: + jtag_command_version = JAYLINK_JTAG_VERSION_3; + break; + default: + command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } } else { - command_print(CMD, "Need exactly one argument for jlink jtag"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1083,13 +1090,8 @@ COMMAND_HANDLER(jlink_handle_jlink_jtag_command) COMMAND_HANDLER(jlink_handle_target_power_command) { - int ret; - int enable; - - if (CMD_ARGC != 1) { - command_print(CMD, "Need exactly one argument for jlink targetpower"); + if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; - } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { command_print(CMD, "Target power supply is not supported by the " @@ -1097,16 +1099,24 @@ COMMAND_HANDLER(jlink_handle_target_power_command) return ERROR_OK; } - if (!strcmp(CMD_ARGV[0], "on")) { - enable = true; - } else if (!strcmp(CMD_ARGV[0], "off")) { - enable = false; - } else { - command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); - return ERROR_FAIL; + if (!CMD_ARGC) { + uint32_t state; + int ret = jaylink_get_hardware_info(devh, JAYLINK_HW_INFO_TARGET_POWER, + &state); + + if (ret != JAYLINK_OK) { + command_print(CMD, "Failed to retrieve target power state"); + return ERROR_FAIL; + } + + command_print(CMD, "%d", (bool)state); + return ERROR_OK; } - ret = jaylink_set_target_power(devh, enable); + bool enable; + COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable); + + int ret = jaylink_set_target_power(devh, enable); if (ret != JAYLINK_OK) { command_print(CMD, "jaylink_set_target_power() failed: %s", @@ -1415,8 +1425,6 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol, COMMAND_HANDLER(jlink_handle_config_usb_address_command) { - uint8_t tmp; - if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " "device"); @@ -1426,19 +1434,16 @@ COMMAND_HANDLER(jlink_handle_config_usb_address_command) if (!CMD_ARGC) { show_config_usb_address(CMD); } else if (CMD_ARGC == 1) { - if (sscanf(CMD_ARGV[0], "%" SCNd8, &tmp) != 1) { - command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); - return ERROR_FAIL; - } + uint8_t tmp; + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], tmp); if (tmp > JAYLINK_USB_ADDRESS_3) { command_print(CMD, "Invalid USB address: %u", tmp); - return ERROR_FAIL; + return ERROR_COMMAND_ARGUMENT_INVALID; } tmp_config.usb_address = tmp; } else { - command_print(CMD, "Need exactly one argument for jlink config usb"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1470,13 +1475,11 @@ COMMAND_HANDLER(jlink_handle_config_target_power_command) enable = false; } else { command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); - return ERROR_FAIL; + return ERROR_COMMAND_ARGUMENT_INVALID; } tmp_config.target_power = enable; } else { - command_print(CMD, "Need exactly one argument for jlink config " - "targetpower"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1510,7 +1513,7 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command) if ((strlen(str) != 17) || (str[2] != ':' || str[5] != ':' || str[8] != ':' || str[11] != ':' || str[14] != ':')) { command_print(CMD, "Invalid MAC address format"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } for (i = 5; i >= 0; i--) { @@ -1520,17 +1523,16 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command) if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) { command_print(CMD, "Invalid MAC address: zero address"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } if (!(0x01 & addr[0])) { command_print(CMD, "Invalid MAC address: multicast address"); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } memcpy(tmp_config.mac_address, addr, sizeof(addr)); } else { - command_print(CMD, "Need exactly one argument for jlink config mac"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1592,20 +1594,26 @@ COMMAND_HANDLER(jlink_handle_config_ip_address_command) if (!CMD_ARGC) { show_config_ip_address(CMD); } else { - if (!string_to_ip(CMD_ARGV[0], ip_address, &i)) - return ERROR_COMMAND_SYNTAX_ERROR; + if (!string_to_ip(CMD_ARGV[0], ip_address, &i)) { + command_print(CMD, "invalid IPv4 address"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } len = strlen(CMD_ARGV[0]); /* Check for format A.B.C.D/E. */ if (i < len) { - if (CMD_ARGV[0][i] != '/') - return ERROR_COMMAND_SYNTAX_ERROR; + if (CMD_ARGV[0][i] != '/') { + command_print(CMD, "missing network mask"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0] + i + 1, subnet_bits); } else if (CMD_ARGC > 1) { - if (!string_to_ip(CMD_ARGV[1], (uint8_t *)&subnet_mask, &i)) - return ERROR_COMMAND_SYNTAX_ERROR; + if (!string_to_ip(CMD_ARGV[1], (uint8_t *)&subnet_mask, &i)) { + command_print(CMD, "invalid subnet mask"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } } if (!subnet_mask) @@ -1886,7 +1894,7 @@ static const struct command_registration jlink_subcommand_handlers[] = { .handler = &jlink_handle_target_power_command, .mode = COMMAND_EXEC, .help = "set the target power supply", - .usage = "<on|off>" + .usage = "[0|1|on|off]" }, { .name = "freemem", @@ -1961,7 +1969,7 @@ static void jlink_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_c /***************************************************************************/ /* J-Link tap functions */ -static unsigned tap_length; +static unsigned int tap_length; /* In SWD mode use tms buffer for direction control */ static uint8_t tms_buffer[JLINK_TAP_BUFFER_SIZE]; static uint8_t tdi_buffer[JLINK_TAP_BUFFER_SIZE]; @@ -1969,13 +1977,15 @@ static uint8_t tdo_buffer[JLINK_TAP_BUFFER_SIZE]; struct pending_scan_result { /** First bit position in tdo_buffer to read. */ - unsigned first; + unsigned int first; /** Number of bits to read. */ - unsigned length; + unsigned int length; /** Location to store the result */ void *buffer; /** Offset in the destination buffer */ - unsigned buffer_offset; + unsigned int buffer_offset; + /** SWD command */ + uint8_t swd_cmd; }; #define MAX_PENDING_SCAN_RESULTS 256 @@ -1991,13 +2001,13 @@ static void jlink_tap_init(void) memset(tdi_buffer, 0, sizeof(tdi_buffer)); } -static void jlink_clock_data(const uint8_t *out, unsigned out_offset, - const uint8_t *tms_out, unsigned tms_offset, - uint8_t *in, unsigned in_offset, - unsigned length) +static void jlink_clock_data(const uint8_t *out, unsigned int out_offset, + const uint8_t *tms_out, unsigned int tms_offset, + uint8_t *in, unsigned int in_offset, + unsigned int length) { do { - unsigned available_length = JLINK_TAP_BUFFER_SIZE - tap_length / 8; + unsigned int available_length = JLINK_TAP_BUFFER_SIZE - tap_length / 8; if (!available_length || (in && pending_scan_results_length == MAX_PENDING_SCAN_RESULTS)) { @@ -2009,7 +2019,7 @@ static void jlink_clock_data(const uint8_t *out, unsigned out_offset, struct pending_scan_result *pending_scan_result = &pending_scan_results_buffer[pending_scan_results_length]; - unsigned scan_length = length > available_length ? + unsigned int scan_length = length > available_length ? available_length : length; if (out) @@ -2109,7 +2119,7 @@ static int jlink_swd_switch_seq(enum swd_special_seq seq) switch (seq) { case LINE_RESET: - LOG_DEBUG("SWD line reset"); + LOG_DEBUG_IO("SWD line reset"); s = swd_seq_line_reset; s_len = swd_seq_line_reset_len; break; @@ -2158,7 +2168,7 @@ static int jlink_swd_run_queue(void) int i; int ret; - LOG_DEBUG("Executing %d queued transactions", pending_scan_results_length); + LOG_DEBUG_IO("Executing %d queued transactions", pending_scan_results_length); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skipping due to previous errors: %d", queued_retval); @@ -2179,12 +2189,13 @@ static int jlink_swd_run_queue(void) } for (i = 0; i < pending_scan_results_length; i++) { + /* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */ + bool check_ack = swd_cmd_returns_ack(pending_scan_results_buffer[i].swd_cmd); int ack = buf_get_u32(tdo_buffer, pending_scan_results_buffer[i].first, 3); - - if (ack != SWD_ACK_OK) { + if (check_ack && ack != SWD_ACK_OK) { LOG_DEBUG("SWD ack not OK: %d %s", ack, ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK"); - queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL; + queued_retval = swd_ack_to_error_code(ack); goto skip; } else if (pending_scan_results_buffer[i].length) { uint32_t data = buf_get_u32(tdo_buffer, 3 + pending_scan_results_buffer[i].first, 32); @@ -2221,6 +2232,7 @@ static void jlink_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint3 if (queued_retval != ERROR_OK) return; + pending_scan_results_buffer[pending_scan_results_length].swd_cmd = cmd; cmd |= SWD_CMD_START | SWD_CMD_PARK; jlink_queue_data_out(&cmd, 8); @@ -2259,15 +2271,14 @@ static const struct swd_driver jlink_swd = { .run = &jlink_swd_run_queue, }; -static const char * const jlink_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface jlink_interface = { .execute_queue = &jlink_execute_queue, }; struct adapter_driver jlink_adapter_driver = { .name = "jlink", - .transports = jlink_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = jlink_command_handlers, .init = &jlink_init, diff --git a/src/jtag/drivers/jtag_dpi.c b/src/jtag/drivers/jtag_dpi.c index 78d4e33e17..d6418d39c7 100644 --- a/src/jtag/drivers/jtag_dpi.c +++ b/src/jtag/drivers/jtag_dpi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * JTAG to DPI driver @@ -163,7 +163,7 @@ static int jtag_dpi_scan(struct scan_command *cmd) return ret; } -static int jtag_dpi_runtest(int cycles) +static int jtag_dpi_runtest(unsigned int num_cycles) { char buf[20]; uint8_t *data_buf = last_ir_buf, *read_scan; @@ -189,7 +189,7 @@ static int jtag_dpi_runtest(int cycles) return ERROR_FAIL; } snprintf(buf, sizeof(buf), "ib %d\n", num_bits); - while (cycles > 0) { + while (num_cycles > 0) { ret = write_sock(buf, strlen(buf)); if (ret != ERROR_OK) { LOG_ERROR("write_sock() fail, file %s, line %d", @@ -209,7 +209,7 @@ static int jtag_dpi_runtest(int cycles) goto out; } - cycles -= num_bits + 6; + num_cycles -= num_bits + 6; } out: @@ -217,17 +217,17 @@ static int jtag_dpi_runtest(int cycles) return ret; } -static int jtag_dpi_stableclocks(int cycles) +static int jtag_dpi_stableclocks(unsigned int num_cycles) { - return jtag_dpi_runtest(cycles); + return jtag_dpi_runtest(num_cycles); } -static int jtag_dpi_execute_queue(void) +static int jtag_dpi_execute_queue(struct jtag_command *cmd_queue) { struct jtag_command *cmd; int ret = ERROR_OK; - for (cmd = jtag_command_queue; ret == ERROR_OK && cmd; + for (cmd = cmd_queue; ret == ERROR_OK && cmd; cmd = cmd->next) { switch (cmd->type) { case JTAG_RUNTEST: @@ -398,7 +398,8 @@ static struct jtag_interface jtag_dpi_interface = { struct adapter_driver jtag_dpi_adapter_driver = { .name = "jtag_dpi", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = jtag_dpi_command_handlers, .init = jtag_dpi_init, .quit = jtag_dpi_quit, diff --git a/src/jtag/drivers/jtag_vpi.c b/src/jtag/drivers/jtag_vpi.c index ea8e46cd7b..fac27b3060 100644 --- a/src/jtag/drivers/jtag_vpi.c +++ b/src/jtag/drivers/jtag_vpi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * JTAG to VPI driver @@ -158,7 +158,7 @@ static int jtag_vpi_send_cmd(struct vpi_cmd *vpi) static int jtag_vpi_receive_cmd(struct vpi_cmd *vpi) { - unsigned bytes_buffered = 0; + unsigned int bytes_buffered = 0; while (bytes_buffered < sizeof(struct vpi_cmd)) { int bytes_to_receive = sizeof(struct vpi_cmd) - bytes_buffered; int retval = read_socket(sockfd, ((char *)vpi) + bytes_buffered, bytes_to_receive); @@ -254,7 +254,7 @@ static int jtag_vpi_path_move(struct pathmove_command *cmd) memset(trans, 0, DIV_ROUND_UP(cmd->num_states, 8)); - for (int i = 0; i < cmd->num_states; i++) { + for (unsigned int i = 0; i < cmd->num_states; i++) { if (tap_state_transition(tap_get_state(), true) == cmd->path[i]) buf_set_u32(trans, i, 1, 1); tap_set_state(cmd->path[i]); @@ -272,7 +272,7 @@ static int jtag_vpi_tms(struct tms_command *cmd) return jtag_vpi_tms_seq(cmd->bits, cmd->num_bits); } -static int jtag_vpi_state_move(tap_state_t state) +static int jtag_vpi_state_move(enum tap_state state) { if (tap_get_state() == state) return ERROR_OK; @@ -440,7 +440,7 @@ static int jtag_vpi_scan(struct scan_command *cmd) return ERROR_OK; } -static int jtag_vpi_runtest(int cycles, tap_state_t state) +static int jtag_vpi_runtest(unsigned int num_cycles, enum tap_state state) { int retval; @@ -448,29 +448,27 @@ static int jtag_vpi_runtest(int cycles, tap_state_t state) if (retval != ERROR_OK) return retval; - retval = jtag_vpi_queue_tdi(NULL, cycles, NO_TAP_SHIFT); + retval = jtag_vpi_queue_tdi(NULL, num_cycles, NO_TAP_SHIFT); if (retval != ERROR_OK) return retval; return jtag_vpi_state_move(state); } -static int jtag_vpi_stableclocks(int cycles) +static int jtag_vpi_stableclocks(unsigned int num_cycles) { uint8_t tms_bits[4]; - int cycles_remain = cycles; + unsigned int cycles_remain = num_cycles; int nb_bits; int retval; - const int CYCLES_ONE_BATCH = sizeof(tms_bits) * 8; - - assert(cycles >= 0); + const unsigned int cycles_one_batch = sizeof(tms_bits) * 8; /* use TMS=1 in TAP RESET state, TMS=0 in all other stable states */ memset(&tms_bits, (tap_get_state() == TAP_RESET) ? 0xff : 0x00, sizeof(tms_bits)); /* send the TMS bits */ while (cycles_remain > 0) { - nb_bits = (cycles_remain < CYCLES_ONE_BATCH) ? cycles_remain : CYCLES_ONE_BATCH; + nb_bits = (cycles_remain < cycles_one_batch) ? cycles_remain : cycles_one_batch; retval = jtag_vpi_tms_seq(tms_bits, nb_bits); if (retval != ERROR_OK) return retval; @@ -480,12 +478,12 @@ static int jtag_vpi_stableclocks(int cycles) return ERROR_OK; } -static int jtag_vpi_execute_queue(void) +static int jtag_vpi_execute_queue(struct jtag_command *cmd_queue) { struct jtag_command *cmd; int retval = ERROR_OK; - for (cmd = jtag_command_queue; retval == ERROR_OK && cmd; + for (cmd = cmd_queue; retval == ERROR_OK && cmd; cmd = cmd->next) { switch (cmd->type) { case JTAG_RESET: @@ -593,10 +591,8 @@ static int jtag_vpi_quit(void) COMMAND_HANDLER(jtag_vpi_set_port) { - if (CMD_ARGC == 0) { - LOG_ERROR("Command \"jtag_vpi set_port\" expects 1 argument (TCP port number)"); + if (CMD_ARGC == 0) return ERROR_COMMAND_SYNTAX_ERROR; - } COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], server_port); LOG_INFO("jtag_vpi: server port set to %u", server_port); @@ -607,10 +603,8 @@ COMMAND_HANDLER(jtag_vpi_set_port) COMMAND_HANDLER(jtag_vpi_set_address) { - if (CMD_ARGC == 0) { - LOG_ERROR("Command \"jtag_vpi set_address\" expects 1 argument (IP address)"); + if (CMD_ARGC == 0) return ERROR_COMMAND_SYNTAX_ERROR; - } free(server_address); server_address = strdup(CMD_ARGV[0]); @@ -621,10 +615,8 @@ COMMAND_HANDLER(jtag_vpi_set_address) COMMAND_HANDLER(jtag_vpi_stop_sim_on_exit_handler) { - if (CMD_ARGC != 1) { - LOG_ERROR("Command \"jtag_vpi stop_sim_on_exit\" expects 1 argument (on|off)"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } COMMAND_PARSE_ON_OFF(CMD_ARGV[0], stop_sim_on_exit); return ERROR_OK; @@ -674,7 +666,8 @@ static struct jtag_interface jtag_vpi_interface = { struct adapter_driver jtag_vpi_adapter_driver = { .name = "jtag_vpi", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = jtag_vpi_command_handlers, .init = jtag_vpi_init, diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c index 0956d3aa6d..88e301cebc 100644 --- a/src/jtag/drivers/kitprog.c +++ b/src/jtag/drivers/kitprog.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Juergen Stuber <juergen@jstuber.net> * @@ -79,8 +79,24 @@ #define HID_COMMAND_CONFIGURE 0x8f #define HID_COMMAND_BOOTLOADER 0xa0 -/* 512 bytes seems to work reliably */ -#define SWD_MAX_BUFFER_LENGTH 512 +/* 512 bytes seemed to work reliably. + * It works with both full queue of mostly reads or mostly writes. + * + * Unfortunately the commit 88f429ead019fd6df96ec15f0d897385f3cef0d0 + * 5321: target/cortex_m: faster reading of all CPU registers + * revealed a serious Kitprog firmware problem: + * If the queue contains more than 63 transactions in the repeated pattern + * one write, two reads, the firmware fails badly. + * Sending 64 transactions makes the adapter to loose the connection with the + * device. Sending 65 or more transactions causes the adapter to stop + * receiving USB HID commands, next kitprog_hid_command() stops in hid_write(). + * + * The problem was detected with KitProg v2.12 and v2.16. + * We can guess the problem is something like a buffer or stack overflow. + * + * Use shorter buffer as a workaround. 300 bytes (= 60 transactions) works. + */ +#define SWD_MAX_BUFFER_LENGTH 300 struct kitprog { hid_device *hid_handle; @@ -259,7 +275,7 @@ static int kitprog_usb_open(void) const uint16_t vids[] = { VID, 0 }; const uint16_t pids[] = { PID, 0 }; - if (jtag_libusb_open(vids, pids, &kitprog_handle->usb_handle, NULL) != ERROR_OK) { + if (jtag_libusb_open(vids, pids, NULL, &kitprog_handle->usb_handle, NULL) != ERROR_OK) { LOG_ERROR("Failed to open or find the device"); return ERROR_FAIL; } @@ -321,9 +337,13 @@ static int kitprog_hid_command(uint8_t *command, size_t command_length, return ERROR_FAIL; } - ret = hid_read(kitprog_handle->hid_handle, data, data_length); - if (ret < 0) { - LOG_DEBUG("HID read returned %i", ret); + ret = hid_read_timeout(kitprog_handle->hid_handle, + data, data_length, LIBUSB_TIMEOUT_MS); + if (ret == 0) { + LOG_ERROR("HID read timed out"); + return ERROR_TIMEOUT_REACHED; + } else if (ret < 0) { + LOG_ERROR("HID read error %ls", hid_error(kitprog_handle->hid_handle)); return ERROR_FAIL; } @@ -394,13 +414,13 @@ static int kitprog_set_protocol(uint8_t protocol) int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (CONTROL_MODE_SET_PROGRAMMER_PROTOCOL << 8) | CONTROL_COMMAND_PROGRAM, - protocol, &status, 1, 0); + protocol, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -420,11 +440,11 @@ static int kitprog_get_status(void) /* Try a maximum of three times */ for (int i = 0; (i < 3) && (transferred == 0); i++) { - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_READ, (CONTROL_MODE_POLL_PROGRAMMER_STATUS << 8) | CONTROL_COMMAND_PROGRAM, - 0, &status, 1, 0); + 0, &status, 1, 0, &transferred); jtag_sleep(1000); } @@ -446,13 +466,13 @@ static int kitprog_set_unknown(void) int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (0x03 << 8) | 0x04, - 0, &status, 1, 0); + 0, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -471,13 +491,13 @@ static int kitprog_acquire_psoc(uint8_t psoc_type, uint8_t acquire_mode, int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (CONTROL_MODE_ACQUIRE_SWD_TARGET << 8) | CONTROL_COMMAND_PROGRAM, - (max_attempts << 8) | (acquire_mode << 4) | psoc_type, &status, 1, 0); + (max_attempts << 8) | (acquire_mode << 4) | psoc_type, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -495,13 +515,13 @@ static int kitprog_reset_target(void) int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (CONTROL_MODE_RESET_TARGET << 8) | CONTROL_COMMAND_PROGRAM, - 0, &status, 1, 0); + 0, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -519,13 +539,13 @@ static int kitprog_swd_sync(void) int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (CONTROL_MODE_SYNCHRONIZE_TRANSFER << 8) | CONTROL_COMMAND_PROGRAM, - 0, &status, 1, 0); + 0, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -543,13 +563,13 @@ static int kitprog_swd_seq(uint8_t seq_type) int transferred; char status = PROGRAMMER_NOK_NACK; - transferred = jtag_libusb_control_transfer(kitprog_handle->usb_handle, + int retval = jtag_libusb_control_transfer(kitprog_handle->usb_handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE, CONTROL_TYPE_WRITE, (CONTROL_MODE_SEND_SWD_SEQUENCE << 8) | CONTROL_COMMAND_PROGRAM, - seq_type, &status, 1, 0); + seq_type, &status, 1, 0, &transferred); - if (transferred == 0) { + if (retval != ERROR_OK || transferred == 0) { LOG_DEBUG("Zero bytes transferred"); return ERROR_FAIL; } @@ -762,7 +782,7 @@ static int kitprog_swd_run_queue(void) if (ack != SWD_ACK_OK || (buffer[read_index] & 0x08)) { LOG_DEBUG("SWD ack not OK: %d %s", i, ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK"); - queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL; + queued_retval = swd_ack_to_error_code(ack); break; } read_index++; @@ -859,6 +879,13 @@ static const struct command_registration kitprog_subcommand_handlers[] = { .usage = "", .help = "try to acquire a PSoC", }, + { + .name = "init_acquire_psoc", + .handler = &kitprog_handle_init_acquire_psoc_command, + .mode = COMMAND_CONFIG, + .help = "try to acquire a PSoC during init", + .usage = "", + }, COMMAND_REGISTRATION_DONE }; @@ -870,13 +897,6 @@ static const struct command_registration kitprog_command_handlers[] = { .usage = "<cmd>", .chain = kitprog_subcommand_handlers, }, - { - .name = "kitprog_init_acquire_psoc", - .handler = &kitprog_handle_init_acquire_psoc_command, - .mode = COMMAND_CONFIG, - .help = "try to acquire a PSoC during init", - .usage = "", - }, COMMAND_REGISTRATION_DONE }; @@ -888,11 +908,10 @@ static const struct swd_driver kitprog_swd = { .run = kitprog_swd_run_queue, }; -static const char * const kitprog_transports[] = { "swd", NULL }; - struct adapter_driver kitprog_adapter_driver = { .name = "kitprog", - .transports = kitprog_transports, + .transport_ids = TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_SWD, .commands = kitprog_command_handlers, .init = kitprog_init, diff --git a/src/jtag/drivers/libjaylink b/src/jtag/drivers/libjaylink index 9aa7a5957c..0d23921a05 160000 --- a/src/jtag/drivers/libjaylink +++ b/src/jtag/drivers/libjaylink @@ -1 +1 @@ -Subproject commit 9aa7a5957c07bb6e862fc1a6d3153d109c7407e4 +Subproject commit 0d23921a05d5d427332a142d154c213d0c306eb1 diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c index 72eed995e0..ee90e78b37 100644 --- a/src/jtag/drivers/libusb_helper.c +++ b/src/jtag/drivers/libusb_helper.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Zachary T Welch <zw@superlucidity.net> * @@ -50,10 +50,10 @@ static int jtag_libusb_error(int err) } } -static bool jtag_libusb_match_ids(struct libusb_device_descriptor *dev_desc, +bool jtag_libusb_match_ids(struct libusb_device_descriptor *dev_desc, const uint16_t vids[], const uint16_t pids[]) { - for (unsigned i = 0; vids[i]; i++) { + for (unsigned int i = 0; vids[i]; i++) { if (dev_desc->idVendor == vids[i] && dev_desc->idProduct == pids[i]) { return true; @@ -146,12 +146,13 @@ static bool jtag_libusb_match_serial(struct libusb_device_handle *device, } int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], - struct libusb_device_handle **out, + const char *product, struct libusb_device_handle **out, adapter_get_alternate_serial_fn adapter_get_alternate_serial) { int cnt, idx, err_code; int retval = ERROR_FAIL; bool serial_mismatch = false; + bool product_mismatch = false; struct libusb_device_handle *libusb_handle = NULL; const char *serial = adapter_get_required_serial(); @@ -188,10 +189,18 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], continue; } + if (product && + !string_descriptor_equal(libusb_handle, dev_desc.iProduct, product)) { + product_mismatch = true; + libusb_close(libusb_handle); + continue; + } + /* Success. */ *out = libusb_handle; retval = ERROR_OK; serial_mismatch = false; + product_mismatch = false; break; } if (cnt >= 0) @@ -200,6 +209,9 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], if (serial_mismatch) LOG_INFO("No device matches the serial string"); + if (product_mismatch) + LOG_INFO("No device matches the product string"); + if (retval != ERROR_OK) libusb_exit(jtag_libusb_context); @@ -216,17 +228,22 @@ void jtag_libusb_close(struct libusb_device_handle *dev) int jtag_libusb_control_transfer(struct libusb_device_handle *dev, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, char *bytes, - uint16_t size, unsigned int timeout) + uint16_t size, unsigned int timeout, int *transferred) { - int transferred = 0; - - transferred = libusb_control_transfer(dev, request_type, request, value, index, + int retval = libusb_control_transfer(dev, request_type, request, value, index, (unsigned char *)bytes, size, timeout); - if (transferred < 0) - transferred = 0; + if (retval < 0) { + LOG_ERROR("libusb_control_transfer error: %s", libusb_error_name(retval)); + if (transferred) + *transferred = 0; + return jtag_libusb_error(retval); + } + + if (transferred) + *transferred = retval; - return transferred; + return ERROR_OK; } int jtag_libusb_bulk_write(struct libusb_device_handle *dev, int ep, char *bytes, @@ -360,3 +377,59 @@ int jtag_libusb_handle_events_completed(int *completed) { return libusb_handle_events_completed(jtag_libusb_context, completed); } + +static enum { + DEV_MEM_NOT_YET_DECIDED, + DEV_MEM_AVAILABLE, + DEV_MEM_FALLBACK_MALLOC +} dev_mem_allocation; + +/* Older libusb does not implement following API calls - define stubs instead */ +#if !defined(LIBUSB_API_VERSION) || (LIBUSB_API_VERSION < 0x01000105) +static uint8_t *libusb_dev_mem_alloc(libusb_device_handle *devh, size_t length) +{ + return NULL; +} + +static int libusb_dev_mem_free(libusb_device_handle *devh, + uint8_t *buffer, size_t length) +{ + return LIBUSB_ERROR_NOT_SUPPORTED; +} +#endif + +uint8_t *oocd_libusb_dev_mem_alloc(libusb_device_handle *devh, + size_t length) +{ + uint8_t *buffer = NULL; + if (dev_mem_allocation != DEV_MEM_FALLBACK_MALLOC) + buffer = libusb_dev_mem_alloc(devh, length); + + if (dev_mem_allocation == DEV_MEM_NOT_YET_DECIDED) + dev_mem_allocation = buffer ? DEV_MEM_AVAILABLE : DEV_MEM_FALLBACK_MALLOC; + + if (dev_mem_allocation == DEV_MEM_FALLBACK_MALLOC) + buffer = malloc(length); + + return buffer; +} + +int oocd_libusb_dev_mem_free(libusb_device_handle *devh, + uint8_t *buffer, size_t length) +{ + if (!buffer) + return ERROR_OK; + + switch (dev_mem_allocation) { + case DEV_MEM_AVAILABLE: + return jtag_libusb_error(libusb_dev_mem_free(devh, buffer, length)); + + case DEV_MEM_FALLBACK_MALLOC: + free(buffer); + return ERROR_OK; + + case DEV_MEM_NOT_YET_DECIDED: + return ERROR_FAIL; + } + return ERROR_FAIL; +} diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h index 172c345981..3cd83c6b38 100644 --- a/src/jtag/drivers/libusb_helper.h +++ b/src/jtag/drivers/libusb_helper.h @@ -30,13 +30,16 @@ typedef char * (*adapter_get_alternate_serial_fn)(struct libusb_device_handle *device, struct libusb_device_descriptor *dev_desc); +bool jtag_libusb_match_ids(struct libusb_device_descriptor *dev_desc, + const uint16_t vids[], const uint16_t pids[]); int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], - struct libusb_device_handle **out, + const char *product, struct libusb_device_handle **out, adapter_get_alternate_serial_fn adapter_get_alternate_serial); void jtag_libusb_close(struct libusb_device_handle *dev); int jtag_libusb_control_transfer(struct libusb_device_handle *dev, uint8_t request_type, uint8_t request, uint16_t value, - uint16_t index, char *bytes, uint16_t size, unsigned int timeout); + uint16_t index, char *bytes, uint16_t size, unsigned int timeout, + int *transferred); int jtag_libusb_bulk_write(struct libusb_device_handle *dev, int ep, char *bytes, int size, int timeout, int *transferred); int jtag_libusb_bulk_read(struct libusb_device_handle *dev, int ep, @@ -64,4 +67,27 @@ int jtag_libusb_choose_interface(struct libusb_device_handle *devh, int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid); int jtag_libusb_handle_events_completed(int *completed); +/** + * Attempts to allocate a block of persistent DMA memory suitable for transfers + * against the USB device. Fall-back to the ordinary heap malloc() + * if the first libusb_dev_mem_alloc() call fails. + * @param devh _libusb_ device handle. + * @param length size of desired data buffer + * @returns a pointer to the newly allocated memory, or NULL on failure + */ +uint8_t *oocd_libusb_dev_mem_alloc(libusb_device_handle *devh, + size_t length); + +/** + * Free device memory allocated with oocd_libusb_dev_mem_alloc(). + * Uses either libusb_dev_mem_free() or free() consistently with + * the used method of allocation. + * @param devh _libusb_ device handle. + * @param buffer pointer to the previously allocated memory + * @param length size of desired data buffer + * @returns Returns ERROR_OK on success, ERROR_FAIL otherwise. + */ +int oocd_libusb_dev_mem_free(libusb_device_handle *devh, + uint8_t *buffer, size_t length); + #endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H */ diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c index 0e96d82e54..36c7e04934 100644 --- a/src/jtag/drivers/linuxgpiod.c +++ b/src/jtag/drivers/linuxgpiod.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Bitbang driver for Linux GPIO descriptors through libgpiod * Copyright (C) 2020 Antonio Borneo <borneo.antonio@gmail.com> @@ -14,67 +14,39 @@ #endif #include <gpiod.h> +#include <jtag/adapter.h> #include <jtag/interface.h> #include <transport/transport.h> #include "bitbang.h" -/* gpio numbers for each gpio. Negative values are invalid */ -static int tck_gpio = -1; -static int tms_gpio = -1; -static int tdi_gpio = -1; -static int tdo_gpio = -1; -static int trst_gpio = -1; -static int srst_gpio = -1; -static int swclk_gpio = -1; -static int swdio_gpio = -1; -static int swdio_dir_gpio = -1; -static int led_gpio = -1; -static int gpiochip = -1; -static int tck_gpiochip = -1; -static int tms_gpiochip = -1; -static int tdi_gpiochip = -1; -static int tdo_gpiochip = -1; -static int trst_gpiochip = -1; -static int srst_gpiochip = -1; -static int swclk_gpiochip = -1; -static int swdio_gpiochip = -1; -static int swdio_dir_gpiochip = -1; -static int led_gpiochip = -1; - -static struct gpiod_chip *gpiod_chip_tck; -static struct gpiod_chip *gpiod_chip_tms; -static struct gpiod_chip *gpiod_chip_tdi; -static struct gpiod_chip *gpiod_chip_tdo; -static struct gpiod_chip *gpiod_chip_trst; -static struct gpiod_chip *gpiod_chip_srst; -static struct gpiod_chip *gpiod_chip_swclk; -static struct gpiod_chip *gpiod_chip_swdio; -static struct gpiod_chip *gpiod_chip_swdio_dir; -static struct gpiod_chip *gpiod_chip_led; - -static struct gpiod_line *gpiod_tck; -static struct gpiod_line *gpiod_tms; -static struct gpiod_line *gpiod_tdi; -static struct gpiod_line *gpiod_tdo; -static struct gpiod_line *gpiod_trst; -static struct gpiod_line *gpiod_swclk; -static struct gpiod_line *gpiod_swdio; -static struct gpiod_line *gpiod_swdio_dir; -static struct gpiod_line *gpiod_srst; -static struct gpiod_line *gpiod_led; +static struct gpiod_chip *gpiod_chip[ADAPTER_GPIO_IDX_NUM] = {}; +static struct gpiod_line *gpiod_line[ADAPTER_GPIO_IDX_NUM] = {}; static int last_swclk; static int last_swdio; static bool last_stored; static bool swdio_input; -static bool swdio_dir_is_active_high = true; + +static const struct adapter_gpio_config *adapter_gpio_config; + +/* + * Helper function to determine if gpio config is valid + * + * Assume here that there will be less than 10000 gpios per gpiochip, and less + * than 1000 gpiochips. + */ +static bool is_gpio_config_valid(enum adapter_gpio_config_index idx) +{ + return adapter_gpio_config[idx].chip_num < 1000 + && adapter_gpio_config[idx].gpio_num < 10000; +} /* Bitbang interface read of TDO */ -static bb_value_t linuxgpiod_read(void) +static enum bb_value linuxgpiod_read(void) { int retval; - retval = gpiod_line_get_value(gpiod_tdo); + retval = gpiod_line_get_value(gpiod_line[ADAPTER_GPIO_IDX_TDO]); if (retval < 0) { LOG_WARNING("reading tdo failed"); return 0; @@ -107,20 +79,20 @@ static int linuxgpiod_write(int tck, int tms, int tdi) } if (tdi != last_tdi) { - retval = gpiod_line_set_value(gpiod_tdi, tdi); + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TDI], tdi); if (retval < 0) LOG_WARNING("writing tdi failed"); } if (tms != last_tms) { - retval = gpiod_line_set_value(gpiod_tms, tms); + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TMS], tms); if (retval < 0) LOG_WARNING("writing tms failed"); } /* write clk last */ if (tck != last_tck) { - retval = gpiod_line_set_value(gpiod_tck, tck); + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TCK], tck); if (retval < 0) LOG_WARNING("writing tck failed"); } @@ -136,7 +108,7 @@ static int linuxgpiod_swdio_read(void) { int retval; - retval = gpiod_line_get_value(gpiod_swdio); + retval = gpiod_line_get_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO]); if (retval < 0) { LOG_WARNING("Fail read swdio"); return 0; @@ -154,23 +126,23 @@ static void linuxgpiod_swdio_drive(bool is_output) * https://stackoverflow.com/questions/58735140/ * this would change in future libgpiod */ - gpiod_line_release(gpiod_swdio); + gpiod_line_release(gpiod_line[ADAPTER_GPIO_IDX_SWDIO]); if (is_output) { - if (gpiod_swdio_dir) { - retval = gpiod_line_set_value(gpiod_swdio_dir, swdio_dir_is_active_high ? 1 : 0); + if (gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR]) { + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR], 1); if (retval < 0) LOG_WARNING("Fail set swdio_dir"); } - retval = gpiod_line_request_output(gpiod_swdio, "OpenOCD", 1); + retval = gpiod_line_request_output(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], "OpenOCD", 1); if (retval < 0) LOG_WARNING("Fail request_output line swdio"); } else { - retval = gpiod_line_request_input(gpiod_swdio, "OpenOCD"); + retval = gpiod_line_request_input(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], "OpenOCD"); if (retval < 0) LOG_WARNING("Fail request_input line swdio"); - if (gpiod_swdio_dir) { - retval = gpiod_line_set_value(gpiod_swdio_dir, swdio_dir_is_active_high ? 0 : 1); + if (gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR]) { + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR], 0); if (retval < 0) LOG_WARNING("Fail set swdio_dir"); } @@ -185,16 +157,16 @@ static int linuxgpiod_swd_write(int swclk, int swdio) int retval; if (!swdio_input) { - if (!last_stored || (swdio != last_swdio)) { - retval = gpiod_line_set_value(gpiod_swdio, swdio); + if (!last_stored || swdio != last_swdio) { + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], swdio); if (retval < 0) LOG_WARNING("Fail set swdio"); } } /* write swclk last */ - if (!last_stored || (swclk != last_swclk)) { - retval = gpiod_line_set_value(gpiod_swclk, swclk); + if (!last_stored || swclk != last_swclk) { + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWCLK], swclk); if (retval < 0) LOG_WARNING("Fail set swclk"); } @@ -206,20 +178,20 @@ static int linuxgpiod_swd_write(int swclk, int swdio) return ERROR_OK; } -static int linuxgpiod_blink(int on) +static int linuxgpiod_blink(bool on) { int retval; - if (!gpiod_led) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_LED)) return ERROR_OK; - retval = gpiod_line_set_value(gpiod_led, on); + retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_LED], on ? 1 : 0); if (retval < 0) LOG_WARNING("Fail set led"); return retval; } -static struct bitbang_interface linuxgpiod_bitbang = { +static const struct bitbang_interface linuxgpiod_bitbang = { .read = linuxgpiod_read, .write = linuxgpiod_write, .swdio_read = linuxgpiod_swdio_read, @@ -239,16 +211,18 @@ static int linuxgpiod_reset(int trst, int srst) LOG_DEBUG("linuxgpiod_reset"); - /* assume active low */ - if (gpiod_srst) { - retval1 = gpiod_line_set_value(gpiod_srst, srst ? 0 : 1); + /* + * active low behaviour handled by "adaptor gpio" command and + * GPIOD_LINE_REQUEST_FLAG_ACTIVE_LOW flag when requesting the line. + */ + if (gpiod_line[ADAPTER_GPIO_IDX_SRST]) { + retval1 = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SRST], srst); if (retval1 < 0) LOG_WARNING("set srst value failed"); } - /* assume active low */ - if (gpiod_trst) { - retval2 = gpiod_line_set_value(gpiod_trst, trst ? 0 : 1); + if (gpiod_line[ADAPTER_GPIO_IDX_TRST]) { + retval2 = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TRST], trst); if (retval2 < 0) LOG_WARNING("set trst value failed"); } @@ -256,109 +230,134 @@ static int linuxgpiod_reset(int trst, int srst) return ((retval1 < 0) || (retval2 < 0)) ? ERROR_FAIL : ERROR_OK; } -/* - * Helper function to determine if gpio number is valid - * - * Assume here that there will be less than 10000 gpios per gpiochip - */ -static bool is_gpio_valid(int gpio) -{ - return gpio >= 0 && gpio < 10000; -} - static bool linuxgpiod_jtag_mode_possible(void) { - if (!is_gpio_valid(tck_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TCK)) return false; - if (!is_gpio_valid(tms_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TMS)) return false; - if (!is_gpio_valid(tdi_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDI)) return false; - if (!is_gpio_valid(tdo_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDO)) return false; return true; } static bool linuxgpiod_swd_mode_possible(void) { - if (!is_gpio_valid(swclk_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWCLK)) return false; - if (!is_gpio_valid(swdio_gpio)) + if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO)) return false; return true; } -static inline void helper_release(struct gpiod_line *line, struct gpiod_chip *chip) +static inline void helper_release(enum adapter_gpio_config_index idx) { - if (line) - gpiod_line_release(line); - if (chip) - gpiod_chip_close(chip); + if (gpiod_line[idx]) { + gpiod_line_release(gpiod_line[idx]); + gpiod_line[idx] = NULL; + } + if (gpiod_chip[idx]) { + gpiod_chip_close(gpiod_chip[idx]); + gpiod_chip[idx] = NULL; + } } static int linuxgpiod_quit(void) { - helper_release(gpiod_led, gpiod_chip_led); - helper_release(gpiod_srst, gpiod_chip_srst); - helper_release(gpiod_swdio, gpiod_chip_swdio); - helper_release(gpiod_swdio_dir, gpiod_chip_swdio_dir); - helper_release(gpiod_swclk, gpiod_chip_swclk); - helper_release(gpiod_trst, gpiod_chip_trst); - helper_release(gpiod_tms, gpiod_chip_tms); - helper_release(gpiod_tck, gpiod_chip_tck); - helper_release(gpiod_tdi, gpiod_chip_tdi); - helper_release(gpiod_tdo, gpiod_chip_tdo); + LOG_DEBUG("linuxgpiod_quit"); + for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) + helper_release(i); return ERROR_OK; } -static struct gpiod_line *helper_get_line(const char *label, - struct gpiod_chip *gpiod_chip, unsigned int offset, - int val, int dir, int flags) +static int helper_get_line(enum adapter_gpio_config_index idx) { - struct gpiod_line *line; - int retval; + if (!is_gpio_config_valid(idx)) + return ERROR_OK; + + int dir = GPIOD_LINE_REQUEST_DIRECTION_INPUT, flags = 0, val = 0, retval; + + gpiod_chip[idx] = gpiod_chip_open_by_number(adapter_gpio_config[idx].chip_num); + if (!gpiod_chip[idx]) { + LOG_ERROR("Cannot open LinuxGPIOD chip %d for %s", adapter_gpio_config[idx].chip_num, + adapter_gpio_get_name(idx)); + return ERROR_JTAG_INIT_FAILED; + } + + gpiod_line[idx] = gpiod_chip_get_line(gpiod_chip[idx], adapter_gpio_config[idx].gpio_num); + if (!gpiod_line[idx]) { + LOG_ERROR("Error get line %s", adapter_gpio_get_name(idx)); + return ERROR_JTAG_INIT_FAILED; + } + + switch (adapter_gpio_config[idx].init_state) { + case ADAPTER_GPIO_INIT_STATE_INPUT: + dir = GPIOD_LINE_REQUEST_DIRECTION_INPUT; + break; + case ADAPTER_GPIO_INIT_STATE_INACTIVE: + dir = GPIOD_LINE_REQUEST_DIRECTION_OUTPUT; + val = 0; + break; + case ADAPTER_GPIO_INIT_STATE_ACTIVE: + dir = GPIOD_LINE_REQUEST_DIRECTION_OUTPUT; + val = 1; + break; + } + + switch (adapter_gpio_config[idx].drive) { + case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL: + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN: + flags |= GPIOD_LINE_REQUEST_FLAG_OPEN_DRAIN; + break; + case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE: + flags |= GPIOD_LINE_REQUEST_FLAG_OPEN_SOURCE; + break; + } - line = gpiod_chip_get_line(gpiod_chip, offset); - if (!line) { - LOG_ERROR("Error get line %s", label); - return NULL; + switch (adapter_gpio_config[idx].pull) { + case ADAPTER_GPIO_PULL_NONE: +#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS + flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_DISABLE; +#endif + break; + case ADAPTER_GPIO_PULL_UP: +#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS + flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_UP; +#else + LOG_WARNING("linuxgpiod: ignoring request for pull-up on %s: not supported by gpiod v%s", + adapter_gpio_get_name(idx), gpiod_version_string()); +#endif + break; + case ADAPTER_GPIO_PULL_DOWN: +#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS + flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_DOWN; +#else + LOG_WARNING("linuxgpiod: ignoring request for pull-down on %s: not supported by gpiod v%s", + adapter_gpio_get_name(idx), gpiod_version_string()); +#endif + break; } + if (adapter_gpio_config[idx].active_low) + flags |= GPIOD_LINE_REQUEST_FLAG_ACTIVE_LOW; + struct gpiod_line_request_config config = { .consumer = "OpenOCD", .request_type = dir, .flags = flags, }; - retval = gpiod_line_request(line, &config, val); + retval = gpiod_line_request(gpiod_line[idx], &config, val); if (retval < 0) { - LOG_ERROR("Error requesting gpio line %s", label); - return NULL; + LOG_ERROR("Error requesting gpio line %s", adapter_gpio_get_name(idx)); + return ERROR_JTAG_INIT_FAILED; } - return line; -} - -static struct gpiod_line *helper_get_input_line(const char *label, - struct gpiod_chip *gpiod_chip, unsigned int offset) -{ - return helper_get_line(label, gpiod_chip, offset, 0, - GPIOD_LINE_REQUEST_DIRECTION_INPUT, 0); -} - -static struct gpiod_line *helper_get_output_line(const char *label, - struct gpiod_chip *gpiod_chip, unsigned int offset, int val) -{ - return helper_get_line(label, gpiod_chip, offset, val, - GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, 0); -} - -static struct gpiod_line *helper_get_open_drain_output_line(const char *label, - struct gpiod_chip *gpiod_chip, unsigned int offset, int val) -{ - return helper_get_line(label, gpiod_chip, offset, val, - GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, GPIOD_LINE_REQUEST_FLAG_OPEN_DRAIN); + return ERROR_OK; } static int linuxgpiod_init(void) @@ -366,11 +365,11 @@ static int linuxgpiod_init(void) LOG_INFO("Linux GPIOD JTAG/SWD bitbang driver"); bitbang_interface = &linuxgpiod_bitbang; + adapter_gpio_config = adapter_gpio_get_config(); /* - * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST - * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high. - * For SWD, SWCLK and SWDIO are configures as output high. + * Configure JTAG/SWD signals. Default directions and initial states are handled + * by adapter.c and "adapter gpio" command. */ if (transport_is_jtag()) { @@ -379,129 +378,44 @@ static int linuxgpiod_init(void) goto out_error; } - gpiod_chip_tdo = gpiod_chip_open_by_number(tdo_gpiochip); - if (!gpiod_chip_tdo) { - LOG_ERROR("Cannot open LinuxGPIOD tdo_gpiochip %d", tdo_gpiochip); - goto out_error; - } - gpiod_chip_tdi = gpiod_chip_open_by_number(tdi_gpiochip); - if (!gpiod_chip_tdi) { - LOG_ERROR("Cannot open LinuxGPIOD tdi_gpiochip %d", tdi_gpiochip); - goto out_error; - } - gpiod_chip_tck = gpiod_chip_open_by_number(tck_gpiochip); - if (!gpiod_chip_tck) { - LOG_ERROR("Cannot open LinuxGPIOD tck_gpiochip %d", tck_gpiochip); - goto out_error; - } - gpiod_chip_tms = gpiod_chip_open_by_number(tms_gpiochip); - if (!gpiod_chip_tms) { - LOG_ERROR("Cannot open LinuxGPIOD tms_gpiochip %d", tms_gpiochip); - goto out_error; - } - - gpiod_tdo = helper_get_input_line("tdo", gpiod_chip_tdo, tdo_gpio); - if (!gpiod_tdo) - goto out_error; - - gpiod_tdi = helper_get_output_line("tdi", gpiod_chip_tdi, tdi_gpio, 0); - if (!gpiod_tdi) + if (helper_get_line(ADAPTER_GPIO_IDX_TDO) != ERROR_OK + || helper_get_line(ADAPTER_GPIO_IDX_TDI) != ERROR_OK + || helper_get_line(ADAPTER_GPIO_IDX_TCK) != ERROR_OK + || helper_get_line(ADAPTER_GPIO_IDX_TMS) != ERROR_OK + || helper_get_line(ADAPTER_GPIO_IDX_TRST) != ERROR_OK) goto out_error; - - gpiod_tck = helper_get_output_line("tck", gpiod_chip_tck, tck_gpio, 0); - if (!gpiod_tck) - goto out_error; - - gpiod_tms = helper_get_output_line("tms", gpiod_chip_tms, tms_gpio, 1); - if (!gpiod_tms) - goto out_error; - - if (is_gpio_valid(trst_gpio)) { - gpiod_chip_trst = gpiod_chip_open_by_number(trst_gpiochip); - if (!gpiod_chip_trst) { - LOG_ERROR("Cannot open LinuxGPIOD trst_gpiochip %d", trst_gpiochip); - goto out_error; - } - - if (jtag_get_reset_config() & RESET_TRST_OPEN_DRAIN) - gpiod_trst = helper_get_open_drain_output_line("trst", gpiod_chip_trst, trst_gpio, 1); - else - gpiod_trst = helper_get_output_line("trst", gpiod_chip_trst, trst_gpio, 1); - - if (!gpiod_trst) - goto out_error; - } } if (transport_is_swd()) { + int retval1, retval2; if (!linuxgpiod_swd_mode_possible()) { LOG_ERROR("Require swclk and swdio gpio for SWD mode"); goto out_error; } - gpiod_chip_swclk = gpiod_chip_open_by_number(swclk_gpiochip); - if (!gpiod_chip_swclk) { - LOG_ERROR("Cannot open LinuxGPIOD swclk_gpiochip %d", swclk_gpiochip); - goto out_error; + /* + * swdio and its buffer should be initialized in the order that prevents + * two outputs from being connected together. This will occur if the + * swdio GPIO is configured as an output while the external buffer is + * configured to send the swdio signal from the target to the GPIO. + */ + if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) { + retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO); + retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR); + } else { + retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR); + retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO); } - gpiod_chip_swdio = gpiod_chip_open_by_number(swdio_gpiochip); - if (!gpiod_chip_swdio) { - LOG_ERROR("Cannot open LinuxGPIOD swdio_gpiochip %d", swdio_gpiochip); + if (retval1 != ERROR_OK || retval2 != ERROR_OK) goto out_error; - } - if (is_gpio_valid(swdio_dir_gpio)) { - gpiod_chip_swdio_dir = gpiod_chip_open_by_number(swdio_dir_gpiochip); - if (!gpiod_chip_swdio_dir) { - LOG_ERROR("Cannot open LinuxGPIOD swdio_dir_gpiochip %d", swdio_dir_gpiochip); - goto out_error; - } - } - - gpiod_swclk = helper_get_output_line("swclk", gpiod_chip_swclk, swclk_gpio, 1); - if (!gpiod_swclk) - goto out_error; - - /* Set buffer direction before making SWDIO an output */ - if (is_gpio_valid(swdio_dir_gpio)) { - gpiod_swdio_dir = helper_get_output_line("swdio_dir", gpiod_chip_swdio_dir, swdio_dir_gpio, - swdio_dir_is_active_high ? 1 : 0); - if (!gpiod_swdio_dir) - goto out_error; - } - - gpiod_swdio = helper_get_output_line("swdio", gpiod_chip_swdio, swdio_gpio, 1); - if (!gpiod_swdio) + if (helper_get_line(ADAPTER_GPIO_IDX_SWCLK) != ERROR_OK) goto out_error; } - if (is_gpio_valid(srst_gpio)) { - gpiod_chip_srst = gpiod_chip_open_by_number(srst_gpiochip); - if (!gpiod_chip_srst) { - LOG_ERROR("Cannot open LinuxGPIOD srst_gpiochip %d", srst_gpiochip); - goto out_error; - } - - if (jtag_get_reset_config() & RESET_SRST_PUSH_PULL) - gpiod_srst = helper_get_output_line("srst", gpiod_chip_srst, srst_gpio, 1); - else - gpiod_srst = helper_get_open_drain_output_line("srst", gpiod_chip_srst, srst_gpio, 1); - - if (!gpiod_srst) - goto out_error; - } - - if (is_gpio_valid(led_gpio)) { - gpiod_chip_led = gpiod_chip_open_by_number(led_gpiochip); - if (!gpiod_chip_led) { - LOG_ERROR("Cannot open LinuxGPIOD led_gpiochip %d", led_gpiochip); - goto out_error; - } - - gpiod_led = helper_get_output_line("led", gpiod_chip_led, led_gpio, 0); - if (!gpiod_led) - goto out_error; - } + if (helper_get_line(ADAPTER_GPIO_IDX_SRST) != ERROR_OK + || helper_get_line(ADAPTER_GPIO_IDX_LED) != ERROR_OK) + goto out_error; return ERROR_OK; @@ -511,243 +425,6 @@ static int linuxgpiod_init(void) return ERROR_JTAG_INIT_FAILED; } -COMMAND_HELPER(linuxgpiod_helper_gpionum, const char *name, int *chip, int *line) -{ - int i = 0; - if (CMD_ARGC > 2) - return ERROR_COMMAND_SYNTAX_ERROR; - if (CMD_ARGC == 2) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], *chip); - i = 1; - } - if (CMD_ARGC > 0) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[i], *line); - command_print(CMD, "LinuxGPIOD %s: chip = %d, num = %d", name, *chip, *line); - return ERROR_OK; -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionums) -{ - if (CMD_ARGC == 4) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(CMD, - "LinuxGPIOD nums: tck = %d, tms = %d, tdi = %d, tdo = %d", - tck_gpio, tms_gpio, tdi_gpio, tdo_gpio); - - return ERROR_OK; -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tck) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tck", &tck_gpiochip, - &tck_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tms) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tms", &tms_gpiochip, - &tms_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdo) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tdo", &tdo_gpiochip, - &tdo_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdi) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tdi", &tdi_gpiochip, - &tdi_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_srst) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "srst", &srst_gpiochip, - &srst_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_trst) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "trst", &trst_gpiochip, - &trst_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_swd_gpionums) -{ - if (CMD_ARGC == 2) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio); - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio); - } else if (CMD_ARGC != 0) { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - command_print(CMD, - "LinuxGPIOD nums: swclk = %d, swdio = %d", - swclk_gpio, swdio_gpio); - - return ERROR_OK; -} - -COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swclk) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swclk", &swclk_gpiochip, - &swclk_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swdio", &swdio_gpiochip, - &swdio_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio_dir) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swdio_dir", &swdio_dir_gpiochip, - &swdio_dir_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_gpionum_led) -{ - return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "led", &led_gpiochip, - &led_gpio); -} - -COMMAND_HANDLER(linuxgpiod_handle_gpiochip) -{ - if (CMD_ARGC == 1) { - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], gpiochip); - tck_gpiochip = gpiochip; - tms_gpiochip = gpiochip; - tdi_gpiochip = gpiochip; - tdo_gpiochip = gpiochip; - trst_gpiochip = gpiochip; - srst_gpiochip = gpiochip; - swclk_gpiochip = gpiochip; - swdio_gpiochip = gpiochip; - swdio_dir_gpiochip = gpiochip; - led_gpiochip = gpiochip; - } - - command_print(CMD, "LinuxGPIOD gpiochip = %d", gpiochip); - return ERROR_OK; -} - -static const struct command_registration linuxgpiod_subcommand_handlers[] = { - { - .name = "jtag_nums", - .handler = linuxgpiod_handle_jtag_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for tck, tms, tdi, tdo. (in that order)", - .usage = "tck tms tdi tdo", - }, - { - .name = "tck_num", - .handler = linuxgpiod_handle_jtag_gpionum_tck, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for tck.", - .usage = "[chip] tck", - }, - { - .name = "tms_num", - .handler = linuxgpiod_handle_jtag_gpionum_tms, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for tms.", - .usage = "[chip] tms", - }, - { - .name = "tdo_num", - .handler = linuxgpiod_handle_jtag_gpionum_tdo, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for tdo.", - .usage = "[chip] tdo", - }, - { - .name = "tdi_num", - .handler = linuxgpiod_handle_jtag_gpionum_tdi, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for tdi.", - .usage = "[chip] tdi", - }, - { - .name = "srst_num", - .handler = linuxgpiod_handle_jtag_gpionum_srst, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for srst.", - .usage = "[chip] srst", - }, - { - .name = "trst_num", - .handler = linuxgpiod_handle_jtag_gpionum_trst, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for trst.", - .usage = "[chip] trst", - }, - { - .name = "swd_nums", - .handler = linuxgpiod_handle_swd_gpionums, - .mode = COMMAND_CONFIG, - .help = "gpio numbers for swclk, swdio. (in that order)", - .usage = "swclk swdio", - }, - { - .name = "swclk_num", - .handler = linuxgpiod_handle_swd_gpionum_swclk, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for swclk.", - .usage = "[chip] swclk", - }, - { - .name = "swdio_num", - .handler = linuxgpiod_handle_swd_gpionum_swdio, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for swdio.", - .usage = "[chip] swdio", - }, - { - .name = "swdio_dir_num", - .handler = linuxgpiod_handle_swd_gpionum_swdio_dir, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for swdio_dir.", - .usage = "[chip] swdio_dir", - }, - { - .name = "led_num", - .handler = linuxgpiod_handle_gpionum_led, - .mode = COMMAND_CONFIG, - .help = "gpio chip number (optional) and gpio number for LED.", - .usage = "[chip] led", - }, - { - .name = "gpiochip", - .handler = linuxgpiod_handle_gpiochip, - .mode = COMMAND_CONFIG, - .help = "number of the gpiochip.", - .usage = "gpiochip", - }, - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration linuxgpiod_command_handlers[] = { - { - .name = "linuxgpiod", - .mode = COMMAND_ANY, - .help = "perform linuxgpiod management", - .chain = linuxgpiod_subcommand_handlers, - .usage = "", - }, - COMMAND_REGISTRATION_DONE -}; - -static const char *const linuxgpiod_transport[] = { "swd", "jtag", NULL }; - static struct jtag_interface linuxgpiod_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = bitbang_execute_queue, @@ -755,8 +432,8 @@ static struct jtag_interface linuxgpiod_interface = { struct adapter_driver linuxgpiod_adapter_driver = { .name = "linuxgpiod", - .transports = linuxgpiod_transport, - .commands = linuxgpiod_command_handlers, + .transport_ids = TRANSPORT_SWD | TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_SWD, .init = linuxgpiod_init, .quit = linuxgpiod_quit, diff --git a/src/jtag/drivers/linuxspidev.c b/src/jtag/drivers/linuxspidev.c new file mode 100644 index 0000000000..396f1a19a9 --- /dev/null +++ b/src/jtag/drivers/linuxspidev.c @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* Copyright (C) 2020 by Lup Yuen Lee <luppy@appkaki.com> + * Copyright (C) 2024 by Richard Pasek <rpasek@google.com> + */ + +/** + * @file + * Implementation of SWD protocol with a Linux SPI device. + */ + +/* Uncomment to log SPI exchanges (very verbose, slows things down a lot) + * + * A quick note on interpreting SPI exchange messages: + * + * This implementation works by performing SPI exchanges with MOSI and MISO + * tied together with a 1K resistor. This combined signal becomes SWDIO. + * + * Since we are performing SPI exchanges, (reading and writing at the same + * time) this means when the target isn't driving SWDIO, what is written by + * the host should also be read by the host. + * + * On SWD writes: + * The TX and RX data should match except for the ACK bits from the target + * swd write reg exchange: len=6 + * tx_buf=C5 02 40 00 02 2C + * rx_buf=C5 42 40 00 02 2C + * ^ + * | + * ACK from target + * + * On SWD reads: + * Only the command byte should match + * swd read reg exchange: len=6 + * tx_buf=B1 00 00 00 00 00 + * rx_buf=B1 40 20 00 00 F8 + * ^^ + * || + * Command packet from host + * + */ +// #define LOG_SPI_EXCHANGE + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stdint.h> +#include <unistd.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <sys/ioctl.h> +#include <linux/spi/spidev.h> +#include <jtag/adapter.h> +#include <jtag/swd.h> +#include <jtag/interface.h> +#include <jtag/commands.h> + +// Number of bits per SPI exchange +#define SPI_BITS 8 + +// Time in uS after the last bit of transfer before deselecting the device +#define SPI_DESELECT_DELAY 0 + +// Maximum number of SWD transactions to queue together in a SPI exchange +#define MAX_QUEUE_ENTRIES 64 + +#define CMD_BITS 8 +#define TURN_BITS 1 +#define ACK_BITS 3 +#define DATA_BITS 32 +#define PARITY_BITS 1 + +#define SWD_WR_BITS (CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS + DATA_BITS + PARITY_BITS) +#define SWD_RD_BITS (CMD_BITS + TURN_BITS + ACK_BITS + DATA_BITS + PARITY_BITS + TURN_BITS) +#define SWD_OP_BITS (MAX(SWD_WR_BITS, SWD_RD_BITS)) +#define SWD_OP_BYTES (DIV_ROUND_UP(SWD_OP_BITS, SPI_BITS)) + +#define AP_DELAY_CLOCKS 8 +#define AP_DELAY_BYTES (DIV_ROUND_UP(AP_DELAY_CLOCKS, SPI_BITS)) + +#define END_IDLE_CLOCKS 8 +#define END_IDLE_BYTES (DIV_ROUND_UP(END_IDLE_CLOCKS, SPI_BITS)) + +// File descriptor for SPI device +static int spi_fd = -1; + +// SPI Configuration +static char *spi_path; +static uint32_t spi_mode = SPI_MODE_3; // Note: SPI in LSB mode is not often supported. We'll flip LSB to MSB ourselves. +static uint32_t spi_speed; + +struct queue_info { + unsigned int buf_idx; + uint32_t *rx_ptr; +}; + +static int queue_retval; +static unsigned int max_queue_entries; +static unsigned int queue_fill; +static unsigned int queue_buf_fill; +static unsigned int queue_buf_size; +static struct queue_info *queue_infos; +static uint8_t *queue_tx_buf; +static uint8_t *queue_rx_buf; +static uint8_t *tx_flip_buf; + +static int spidev_swd_switch_seq(enum swd_special_seq seq); +static void spidev_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk); + +static void spi_exchange(const uint8_t *tx_data, uint8_t *rx_data, unsigned int len) +{ +#ifdef LOG_SPI_EXCHANGE + LOG_OUTPUT("exchange: len=%u\n", len); +#endif // LOG_SPI_EXCHANGE + + if (len == 0) { + LOG_DEBUG("exchange with no length"); + return; + } + + if (!tx_data && !rx_data) { + LOG_DEBUG("exchange with no valid tx or rx pointers"); + return; + } + + if (len > queue_buf_size) { + LOG_ERROR("exchange too large len=%u ", len); + return; + } + + if (tx_data) { + // Reverse LSB to MSB + for (unsigned int i = 0; i < len; i++) + tx_flip_buf[i] = flip_u32(tx_data[i], 8); + +#ifdef LOG_SPI_EXCHANGE + if (len != 0) { + LOG_OUTPUT(" tx_buf="); + for (unsigned int i = 0; i < len; i++) + LOG_OUTPUT("%.2" PRIx8 " ", tx_flip_buf[i]); + } + LOG_OUTPUT("\n"); +#endif // LOG_SPI_EXCHANGE + } + // Transmit the MSB buffer to SPI device. + struct spi_ioc_transfer tr = { + /* The following must be cast to unsigned long to compile correctly on + * 32 and 64 bit machines (as is done in the spidev examples in Linux + * kernel code in tools/spi/). + */ + .tx_buf = (unsigned long)(tx_data ? tx_flip_buf : NULL), + .rx_buf = (unsigned long)rx_data, + .len = len, + .delay_usecs = SPI_DESELECT_DELAY, + .speed_hz = spi_speed, + .bits_per_word = SPI_BITS, + }; + int ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr); + + if (ret < 1) { + LOG_ERROR("exchange failed"); + return; + } + + if (rx_data) { +#ifdef LOG_SPI_EXCHANGE + if (len != 0) { + LOG_OUTPUT(" rx_buf="); + for (unsigned int i = 0; i < len; i++) + LOG_OUTPUT("%.2" PRIx8 " ", rx_data[i]); + } + LOG_OUTPUT("\n"); +#endif // LOG_SPI_EXCHANGE + + // Reverse MSB to LSB + for (unsigned int i = 0; i < len; i++) + rx_data[i] = flip_u32(rx_data[i], 8); + } +} + +static int spidev_speed(int speed) +{ + uint32_t tmp_speed = speed; + + int ret = ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &tmp_speed); + if (ret == -1) { + LOG_ERROR("Failed to set SPI %d speed", speed); + return ERROR_FAIL; + } + + spi_speed = speed; + + return ERROR_OK; +} + +static int spidev_speed_div(int speed, int *khz) +{ + *khz = speed / 1000; + return ERROR_OK; +} + +static int spidev_khz(int khz, int *jtag_speed) +{ + if (khz == 0) { + LOG_DEBUG("RCLK not supported"); + return ERROR_FAIL; + } + + *jtag_speed = khz * 1000; + return ERROR_OK; +} + +static void spidev_free_queue(void) +{ + max_queue_entries = 0; + queue_buf_size = 0; + + free(queue_infos); + queue_infos = NULL; + + free(queue_tx_buf); + queue_tx_buf = NULL; + + free(queue_rx_buf); + queue_rx_buf = NULL; + + free(tx_flip_buf); + tx_flip_buf = NULL; +} + +static void spidev_clear_queue(void) +{ + queue_fill = 0; + queue_buf_fill = 0; + + memset(queue_infos, 0, sizeof(struct queue_info) * max_queue_entries); + memset(queue_tx_buf, 0, queue_buf_size); + memset(queue_rx_buf, 0, queue_buf_size); + memset(tx_flip_buf, 0, queue_buf_size); +} + +static int spidev_alloc_queue(unsigned int new_queue_entries) +{ + if (queue_fill || queue_buf_fill) { + LOG_ERROR("Can't realloc queue when queue is in use"); + return ERROR_FAIL; + } + + unsigned int new_queue_buf_size = + (new_queue_entries * (SWD_OP_BYTES + AP_DELAY_BYTES)) + END_IDLE_BYTES; + + queue_infos = realloc(queue_infos, sizeof(struct queue_info) * new_queue_entries); + if (!queue_infos) + goto realloc_fail; + + queue_tx_buf = realloc(queue_tx_buf, new_queue_buf_size); + if (!queue_tx_buf) + goto realloc_fail; + + queue_rx_buf = realloc(queue_rx_buf, new_queue_buf_size); + if (!queue_rx_buf) + goto realloc_fail; + + tx_flip_buf = realloc(tx_flip_buf, new_queue_buf_size); + if (!tx_flip_buf) + goto realloc_fail; + + max_queue_entries = new_queue_entries; + queue_buf_size = new_queue_buf_size; + + spidev_clear_queue(); + + LOG_DEBUG("Set queue entries to %u (buffers %u bytes)", max_queue_entries, queue_buf_size); + + return ERROR_OK; + +realloc_fail: + spidev_free_queue(); + + LOG_ERROR("Couldn't allocate queue. Out of memory."); + return ERROR_FAIL; +} + +static int spidev_init(void) +{ + LOG_INFO("SPI SWD driver"); + + if (spi_fd >= 0) + return ERROR_OK; + + if (!spi_path) { + LOG_ERROR("Path to spidev not set"); + return ERROR_JTAG_INIT_FAILED; + } + + // Open SPI device. + spi_fd = open(spi_path, O_RDWR); + if (spi_fd < 0) { + LOG_ERROR("Failed to open SPI port at %s", spi_path); + return ERROR_JTAG_INIT_FAILED; + } + + int ret; + // Set SPI mode. +#ifdef SPI_IOC_WR_MODE32 + ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode); +#else + // Linux pre 3.15 does not support MODE32, use 8-bit ioctl + if (spi_mode & ~0xff) { + LOG_ERROR("SPI mode 0x%" PRIx32 ", system permits 8 bits only", spi_mode); + return ERROR_JTAG_INIT_FAILED; + } + + uint8_t mode = (uint8_t)spi_mode; + ret = ioctl(spi_fd, SPI_IOC_WR_MODE, &mode); +#endif + if (ret == -1) { + LOG_ERROR("Failed to set SPI mode 0x%" PRIx32, spi_mode); + return ERROR_JTAG_INIT_FAILED; + } + + // Set SPI bits per word. + uint32_t spi_bits = SPI_BITS; + ret = ioctl(spi_fd, SPI_IOC_WR_BITS_PER_WORD, &spi_bits); + if (ret == -1) { + LOG_ERROR("Failed to set SPI %" PRIu8 " bits per transfer", spi_bits); + return ERROR_JTAG_INIT_FAILED; + } + + LOG_INFO("Opened SPI device at %s in mode 0x%" PRIx32 " with %" PRIu8 " bits ", + spi_path, spi_mode, spi_bits); + + if (max_queue_entries == 0) { + ret = spidev_alloc_queue(MAX_QUEUE_ENTRIES); + if (ret != ERROR_OK) + return ERROR_JTAG_INIT_FAILED; + } + + return ERROR_OK; +} + +static int spidev_quit(void) +{ + spidev_free_queue(); + + if (spi_fd < 0) + return ERROR_OK; + + close(spi_fd); + spi_fd = -1; + + free(spi_path); + spi_path = NULL; + + return ERROR_OK; +} + +static int spidev_swd_init(void) +{ + LOG_DEBUG("spidev_swd_init"); + return ERROR_OK; +} + +static int spidev_swd_execute_queue(unsigned int end_idle_bytes) +{ + LOG_DEBUG_IO("Executing %u queued transactions", queue_fill); + + if (queue_retval != ERROR_OK) { + LOG_DEBUG_IO("Skipping due to previous errors: %d", queue_retval); + goto skip; + } + + /* A transaction must be followed by another transaction or at least 8 idle + * cycles to ensure that data is clocked through the AP. Since the tx + * buffer is zeroed after each queue run, every byte added to the buffer + * fill will add on an additional 8 idle cycles. + */ + queue_buf_fill += end_idle_bytes; + + spi_exchange(queue_tx_buf, queue_rx_buf, queue_buf_fill); + + for (unsigned int queue_idx = 0; queue_idx < queue_fill; queue_idx++) { + unsigned int buf_idx = queue_infos[queue_idx].buf_idx; + uint8_t *tx_ptr = &queue_tx_buf[buf_idx]; + uint8_t *rx_ptr = &queue_rx_buf[buf_idx]; + uint8_t cmd = buf_get_u32(tx_ptr, 0, CMD_BITS); + bool read = cmd & SWD_CMD_RNW ? true : false; + int ack = buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS, ACK_BITS); + uint32_t data = read ? + buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS + ACK_BITS, DATA_BITS) : + buf_get_u32(tx_ptr, CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS, DATA_BITS); + + // Devices do not reply to DP_TARGETSEL write cmd, ignore received ack + bool check_ack = swd_cmd_returns_ack(cmd); + + LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK) ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO, + "%s%s %s %s reg %X = %08" PRIx32, + check_ack ? "" : "ack ignored ", + ack == SWD_ACK_OK ? "OK" : + ack == SWD_ACK_WAIT ? "WAIT" : + ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + read ? "read" : "write", + (cmd & SWD_CMD_A32) >> 1, + data); + + if (ack != SWD_ACK_OK && check_ack) { + queue_retval = swd_ack_to_error_code(ack); + goto skip; + + } else if (read) { + int parity = buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS + ACK_BITS + DATA_BITS, PARITY_BITS); + + if (parity != parity_u32(data)) { + LOG_ERROR("SWD Read data parity mismatch"); + queue_retval = ERROR_FAIL; + goto skip; + } + + if (queue_infos[queue_idx].rx_ptr) + *queue_infos[queue_idx].rx_ptr = data; + } + } + +skip: + spidev_clear_queue(); + + int retval = queue_retval; + queue_retval = ERROR_OK; + + return retval; +} + +static int spidev_swd_run_queue(void) +{ + /* Since we are unsure if another SWD transaction will follow the + * transactions we are just about to execute, we need to add on 8 idle + * cycles. + */ + return spidev_swd_execute_queue(END_IDLE_BYTES); +} + +static void spidev_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint32_t ap_delay_clk) +{ + unsigned int swd_op_bytes = DIV_ROUND_UP(SWD_OP_BITS + ap_delay_clk, SPI_BITS); + + if (queue_fill >= max_queue_entries || + queue_buf_fill + swd_op_bytes + END_IDLE_BYTES > queue_buf_size) { + /* Not enough room in the queue. Run the queue. No idle bytes are + * needed because we are going to execute transactions right after + * the queue is emptied. + */ + queue_retval = spidev_swd_execute_queue(0); + } + + if (queue_retval != ERROR_OK) + return; + + uint8_t *tx_ptr = &queue_tx_buf[queue_buf_fill]; + + cmd |= SWD_CMD_START | SWD_CMD_PARK; + + buf_set_u32(tx_ptr, 0, CMD_BITS, cmd); + + if (cmd & SWD_CMD_RNW) { + // Queue a read transaction + queue_infos[queue_fill].rx_ptr = dst; + } else { + // Queue a write transaction + buf_set_u32(tx_ptr, + CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS, DATA_BITS, data); + buf_set_u32(tx_ptr, + CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS + DATA_BITS, PARITY_BITS, parity_u32(data)); + } + + queue_infos[queue_fill].buf_idx = queue_buf_fill; + + /* Add idle cycles after AP accesses to avoid WAIT. Buffer is already + * zeroed so we just need to advance the pointer to add idle cycles. + */ + queue_buf_fill += swd_op_bytes; + + queue_fill++; +} + +static void spidev_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) +{ + assert(cmd & SWD_CMD_RNW); + spidev_swd_queue_cmd(cmd, value, 0, ap_delay_clk); +} + +static void spidev_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) +{ + assert(!(cmd & SWD_CMD_RNW)); + spidev_swd_queue_cmd(cmd, NULL, value, ap_delay_clk); +} + +static int spidev_swd_switch_seq(enum swd_special_seq seq) +{ + switch (seq) { + case LINE_RESET: + LOG_DEBUG_IO("SWD line reset"); + spi_exchange(swd_seq_line_reset, NULL, swd_seq_line_reset_len / SPI_BITS); + break; + case JTAG_TO_SWD: + LOG_DEBUG("JTAG-to-SWD"); + spi_exchange(swd_seq_jtag_to_swd, NULL, swd_seq_jtag_to_swd_len / SPI_BITS); + break; + case JTAG_TO_DORMANT: + LOG_DEBUG("JTAG-to-DORMANT"); + spi_exchange(swd_seq_jtag_to_dormant, NULL, swd_seq_jtag_to_dormant_len / SPI_BITS); + break; + case SWD_TO_JTAG: + LOG_DEBUG("SWD-to-JTAG"); + spi_exchange(swd_seq_swd_to_jtag, NULL, swd_seq_swd_to_jtag_len / SPI_BITS); + break; + case SWD_TO_DORMANT: + LOG_DEBUG("SWD-to-DORMANT"); + spi_exchange(swd_seq_swd_to_dormant, NULL, swd_seq_swd_to_dormant_len / SPI_BITS); + break; + case DORMANT_TO_SWD: + LOG_DEBUG("DORMANT-to-SWD"); + spi_exchange(swd_seq_dormant_to_swd, NULL, swd_seq_dormant_to_swd_len / SPI_BITS); + break; + case DORMANT_TO_JTAG: + LOG_DEBUG("DORMANT-to-JTAG"); + spi_exchange(swd_seq_dormant_to_jtag, NULL, swd_seq_dormant_to_jtag_len / SPI_BITS); + break; + default: + LOG_ERROR("Sequence %d not supported", seq); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +COMMAND_HANDLER(spidev_handle_path_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + free(spi_path); + spi_path = strdup(CMD_ARGV[0]); + if (!spi_path) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +COMMAND_HANDLER(spidev_handle_mode_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], spi_mode); + return ERROR_OK; +} + +COMMAND_HANDLER(spidev_handle_queue_entries_command) +{ + uint32_t new_queue_entries; + + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_queue_entries); + + return spidev_alloc_queue(new_queue_entries); +} + +const struct swd_driver spidev_swd = { + .init = spidev_swd_init, + .switch_seq = spidev_swd_switch_seq, + .read_reg = spidev_swd_read_reg, + .write_reg = spidev_swd_write_reg, + .run = spidev_swd_run_queue, +}; + +static const struct command_registration spidev_subcommand_handlers[] = { + { + .name = "path", + .handler = &spidev_handle_path_command, + .mode = COMMAND_CONFIG, + .help = "set the path to the spidev device", + .usage = "path_to_spidev", + }, + { + .name = "mode", + .handler = &spidev_handle_mode_command, + .mode = COMMAND_CONFIG, + .help = "set the mode of the spi port with optional bit flags (default=3)", + .usage = "mode", + }, + { + .name = "queue_entries", + .handler = &spidev_handle_queue_entries_command, + .mode = COMMAND_CONFIG, + .help = "set the queue entry size (default=64)", + .usage = "queue_entries", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration spidev_command_handlers[] = { + { + .name = "spidev", + .mode = COMMAND_ANY, + .help = "perform spidev management", + .chain = spidev_subcommand_handlers, + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; + +struct adapter_driver linuxspidev_adapter_driver = { + .name = "linuxspidev", + .transport_ids = TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_SWD, + .commands = spidev_command_handlers, + + .init = spidev_init, + .quit = spidev_quit, + .speed = spidev_speed, + .khz = spidev_khz, + .speed_div = spidev_speed_div, + + .swd_ops = &spidev_swd, +}; diff --git a/src/jtag/drivers/minidriver_imp.h b/src/jtag/drivers/minidriver_imp.h index 7afb46345f..f3582f6e34 100644 --- a/src/jtag/drivers/minidriver_imp.h +++ b/src/jtag/drivers/minidriver_imp.h @@ -13,16 +13,10 @@ static inline void interface_jtag_add_scan_check_alloc(struct scan_field *field) { - unsigned num_bytes = DIV_ROUND_UP(field->num_bits, 8); + unsigned int num_bytes = DIV_ROUND_UP(field->num_bits, 8); field->in_value = cmd_queue_alloc(num_bytes); } -void interface_jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0); - -void interface_jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0, - jtag_callback_data_t data1, jtag_callback_data_t data2, - jtag_callback_data_t data3); - void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3); diff --git a/src/jtag/drivers/mpsse.c b/src/jtag/drivers/mpsse.c index 1db8af9196..38393ad0ae 100644 --- a/src/jtag/drivers/mpsse.c +++ b/src/jtag/drivers/mpsse.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /************************************************************************** * Copyright (C) 2012 by Andreas Fritiofson * @@ -13,6 +13,7 @@ #include "helper/log.h" #include "helper/replacements.h" #include "helper/time_support.h" +#include "libusb_helper.h" #include <libusb.h> /* Compatibility define for older libusb-1.0 */ @@ -63,17 +64,19 @@ struct mpsse_ctx { uint8_t interface; enum ftdi_chip_type type; uint8_t *write_buffer; - unsigned write_size; - unsigned write_count; + unsigned int write_size; + unsigned int write_count; uint8_t *read_buffer; - unsigned read_size; - unsigned read_count; + unsigned int read_size; + unsigned int read_count; uint8_t *read_chunk; - unsigned read_chunk_size; + unsigned int read_chunk_size; struct bit_copy_queue read_queue; int retval; }; +static void mpsse_purge(struct mpsse_ctx *ctx); + /* Returns true if the string descriptor indexed by str_index in device matches string */ static bool string_descriptor_equal(struct libusb_device_handle *device, uint8_t str_index, const char *string) @@ -148,7 +151,7 @@ static bool device_location_equal(struct libusb_device *device, const char *loca * Set any field to 0 as a wildcard. If the device is found true is returned, with ctx containing * the already opened handle. ctx->interface must be set to the desired interface (channel) number * prior to calling this function. */ -static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t *vid, const uint16_t *pid, +static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t vids[], const uint16_t pids[], const char *product, const char *serial, const char *location) { struct libusb_device **list; @@ -169,9 +172,7 @@ static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t *vid, con continue; } - if (vid && *vid != desc.idVendor) - continue; - if (pid && *pid != desc.idProduct) + if (!jtag_libusb_match_ids(&desc, vids, pids)) continue; err = libusb_open(device, &ctx->usb_dev); @@ -203,7 +204,7 @@ static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t *vid, con libusb_free_device_list(list, 1); if (!found) { - LOG_ERROR("no device found"); + /* The caller reports detailed error desc */ return false; } @@ -266,6 +267,27 @@ static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t *vid, con case 0x900: ctx->type = TYPE_FT232H; break; + case 0x2800: + ctx->type = TYPE_FT2233HP; + break; + case 0x2900: + ctx->type = TYPE_FT4233HP; + break; + case 0x3000: + ctx->type = TYPE_FT2232HP; + break; + case 0x3100: + ctx->type = TYPE_FT4232HP; + break; + case 0x3200: + ctx->type = TYPE_FT233HP; + break; + case 0x3300: + ctx->type = TYPE_FT232HP; + break; + case 0x3600: + ctx->type = TYPE_FT4232HA; + break; default: LOG_ERROR("unsupported FTDI chip type: 0x%04x", desc.bcdDevice); goto error; @@ -307,14 +329,14 @@ static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t *vid, con return false; } -struct mpsse_ctx *mpsse_open(const uint16_t *vid, const uint16_t *pid, const char *description, +struct mpsse_ctx *mpsse_open(const uint16_t vids[], const uint16_t pids[], const char *description, const char *serial, const char *location, int channel) { struct mpsse_ctx *ctx = calloc(1, sizeof(*ctx)); int err; if (!ctx) - return 0; + return NULL; bit_copy_queue_init(&ctx->read_queue); ctx->read_chunk_size = 16384; @@ -343,18 +365,13 @@ struct mpsse_ctx *mpsse_open(const uint16_t *vid, const uint16_t *pid, const cha goto error; } - if (!open_matching_device(ctx, vid, pid, description, serial, location)) { - /* Four hex digits plus terminating zero each */ - char vidstr[5]; - char pidstr[5]; - LOG_ERROR("unable to open ftdi device with vid %s, pid %s, description '%s', " + if (!open_matching_device(ctx, vids, pids, description, serial, location)) { + LOG_ERROR("unable to open ftdi device with description '%s', " "serial '%s' at bus location '%s'", - vid ? sprintf(vidstr, "%04x", *vid), vidstr : "*", - pid ? sprintf(pidstr, "%04x", *pid), pidstr : "*", description ? description : "*", serial ? serial : "*", location ? location : "*"); - ctx->usb_dev = 0; + ctx->usb_dev = NULL; goto error; } @@ -384,7 +401,7 @@ struct mpsse_ctx *mpsse_open(const uint16_t *vid, const uint16_t *pid, const cha return ctx; error: mpsse_close(ctx); - return 0; + return NULL; } void mpsse_close(struct mpsse_ctx *ctx) @@ -406,7 +423,7 @@ bool mpsse_is_high_speed(struct mpsse_ctx *ctx) return ctx->type != TYPE_FT2232C; } -void mpsse_purge(struct mpsse_ctx *ctx) +static void mpsse_purge(struct mpsse_ctx *ctx) { int err; LOG_DEBUG("-"); @@ -429,13 +446,13 @@ void mpsse_purge(struct mpsse_ctx *ctx) } } -static unsigned buffer_write_space(struct mpsse_ctx *ctx) +static unsigned int buffer_write_space(struct mpsse_ctx *ctx) { /* Reserve one byte for SEND_IMMEDIATE */ return ctx->write_size - ctx->write_count - 1; } -static unsigned buffer_read_space(struct mpsse_ctx *ctx) +static unsigned int buffer_read_space(struct mpsse_ctx *ctx) { return ctx->read_size - ctx->read_count; } @@ -447,8 +464,8 @@ static void buffer_write_byte(struct mpsse_ctx *ctx, uint8_t data) ctx->write_buffer[ctx->write_count++] = data; } -static unsigned buffer_write(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, - unsigned bit_count) +static unsigned int buffer_write(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, + unsigned int bit_count) { LOG_DEBUG_IO("%d bits", bit_count); assert(ctx->write_count + DIV_ROUND_UP(bit_count, 8) <= ctx->write_size); @@ -457,8 +474,8 @@ static unsigned buffer_write(struct mpsse_ctx *ctx, const uint8_t *out, unsigned return bit_count; } -static unsigned buffer_add_read(struct mpsse_ctx *ctx, uint8_t *in, unsigned in_offset, - unsigned bit_count, unsigned offset) +static unsigned int buffer_add_read(struct mpsse_ctx *ctx, uint8_t *in, unsigned int in_offset, + unsigned int bit_count, unsigned int offset) { LOG_DEBUG_IO("%d bits, offset %d", bit_count, offset); assert(ctx->read_count + DIV_ROUND_UP(bit_count, 8) <= ctx->read_size); @@ -468,20 +485,20 @@ static unsigned buffer_add_read(struct mpsse_ctx *ctx, uint8_t *in, unsigned in_ return bit_count; } -void mpsse_clock_data_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, - unsigned length, uint8_t mode) +void mpsse_clock_data_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, + unsigned int length, uint8_t mode) { - mpsse_clock_data(ctx, out, out_offset, 0, 0, length, mode); + mpsse_clock_data(ctx, out, out_offset, NULL, 0, length, mode); } -void mpsse_clock_data_in(struct mpsse_ctx *ctx, uint8_t *in, unsigned in_offset, unsigned length, +void mpsse_clock_data_in(struct mpsse_ctx *ctx, uint8_t *in, unsigned int in_offset, unsigned int length, uint8_t mode) { - mpsse_clock_data(ctx, 0, 0, in, in_offset, length, mode); + mpsse_clock_data(ctx, NULL, 0, in, in_offset, length, mode); } -void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, uint8_t *in, - unsigned in_offset, unsigned length, uint8_t mode) +void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in, + unsigned int in_offset, unsigned int length, uint8_t mode) { /* TODO: Fix MSB first modes */ LOG_DEBUG_IO("%s%s %d bits", in ? "in" : "", out ? "out" : "", length); @@ -516,7 +533,7 @@ void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_of length = 0; } else { /* Byte transfer */ - unsigned this_bytes = length / 8; + unsigned int this_bytes = length / 8; /* MPSSE command limit */ if (this_bytes > 65536) this_bytes = 65536; @@ -543,7 +560,7 @@ void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_of this_bytes * 8, 0); if (!out && !in) - for (unsigned n = 0; n < this_bytes; n++) + for (unsigned int n = 0; n < this_bytes; n++) buffer_write_byte(ctx, 0x00); length -= this_bytes * 8; } @@ -551,14 +568,14 @@ void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_of } } -void mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, - unsigned length, bool tdi, uint8_t mode) +void mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, + unsigned int length, bool tdi, uint8_t mode) { - mpsse_clock_tms_cs(ctx, out, out_offset, 0, 0, length, tdi, mode); + mpsse_clock_tms_cs(ctx, out, out_offset, NULL, 0, length, tdi, mode); } -void mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, uint8_t *in, - unsigned in_offset, unsigned length, bool tdi, uint8_t mode) +void mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in, + unsigned int in_offset, unsigned int length, bool tdi, uint8_t mode) { LOG_DEBUG_IO("%sout %d bits, tdi=%d", in ? "in" : "", length, tdi); assert(out); @@ -578,7 +595,7 @@ void mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_ ctx->retval = mpsse_flush(ctx); /* Byte transfer */ - unsigned this_bits = length; + unsigned int this_bits = length; /* MPSSE command limit */ /* NOTE: there's a report of an FT2232 bug in this area, where shifting * exactly 7 bits can make problems with TMS signaling for the last @@ -694,7 +711,7 @@ void mpsse_loopback_config(struct mpsse_ctx *ctx, bool enable) single_byte_boolean_helper(ctx, enable, 0x84, 0x85); } -void mpsse_set_divisor(struct mpsse_ctx *ctx, uint16_t divisor) +static void mpsse_set_divisor(struct mpsse_ctx *ctx, uint16_t divisor) { LOG_DEBUG("%d", divisor); @@ -711,7 +728,7 @@ void mpsse_set_divisor(struct mpsse_ctx *ctx, uint16_t divisor) buffer_write_byte(ctx, divisor >> 8); } -int mpsse_divide_by_5_config(struct mpsse_ctx *ctx, bool enable) +static int mpsse_divide_by_5_config(struct mpsse_ctx *ctx, bool enable) { if (!mpsse_is_high_speed(ctx)) return ERROR_FAIL; @@ -722,7 +739,7 @@ int mpsse_divide_by_5_config(struct mpsse_ctx *ctx, bool enable) return ERROR_OK; } -int mpsse_rtck_config(struct mpsse_ctx *ctx, bool enable) +static int mpsse_rtck_config(struct mpsse_ctx *ctx, bool enable) { if (!mpsse_is_high_speed(ctx)) return ERROR_FAIL; @@ -768,7 +785,7 @@ int mpsse_set_frequency(struct mpsse_ctx *ctx, int frequency) struct transfer_result { struct mpsse_ctx *ctx; bool done; - unsigned transferred; + unsigned int transferred; }; static LIBUSB_CALL void read_cb(struct libusb_transfer *transfer) @@ -776,16 +793,16 @@ static LIBUSB_CALL void read_cb(struct libusb_transfer *transfer) struct transfer_result *res = transfer->user_data; struct mpsse_ctx *ctx = res->ctx; - unsigned packet_size = ctx->max_packet_size; + unsigned int packet_size = ctx->max_packet_size; DEBUG_PRINT_BUF(transfer->buffer, transfer->actual_length); /* Strip the two status bytes sent at the beginning of each USB packet * while copying the chunk buffer to the read buffer */ - unsigned num_packets = DIV_ROUND_UP(transfer->actual_length, packet_size); - unsigned chunk_remains = transfer->actual_length; - for (unsigned i = 0; i < num_packets && chunk_remains > 2; i++) { - unsigned this_size = packet_size - 2; + unsigned int num_packets = DIV_ROUND_UP(transfer->actual_length, packet_size); + unsigned int chunk_remains = transfer->actual_length; + for (unsigned int i = 0; i < num_packets && chunk_remains > 2; i++) { + unsigned int this_size = packet_size - 2; if (this_size > chunk_remains - 2) this_size = chunk_remains - 2; if (this_size > ctx->read_count - res->transferred) @@ -848,7 +865,7 @@ int mpsse_flush(struct mpsse_ctx *ctx) if (ctx->write_count == 0) return retval; - struct libusb_transfer *read_transfer = 0; + struct libusb_transfer *read_transfer = NULL; struct transfer_result read_result = { .ctx = ctx, .done = true }; if (ctx->read_count) { buffer_write_byte(ctx, 0x87); /* SEND_IMMEDIATE */ @@ -886,20 +903,6 @@ int mpsse_flush(struct mpsse_ctx *ctx) retval = libusb_handle_events_timeout_completed(ctx->usb_ctx, &timeout_usb, NULL); keep_alive(); - if (retval == LIBUSB_ERROR_NO_DEVICE || retval == LIBUSB_ERROR_INTERRUPTED) - break; - - if (retval != LIBUSB_SUCCESS) { - libusb_cancel_transfer(write_transfer); - if (read_transfer) - libusb_cancel_transfer(read_transfer); - while (!write_result.done || !read_result.done) { - retval = libusb_handle_events_timeout_completed(ctx->usb_ctx, - &timeout_usb, NULL); - if (retval != LIBUSB_SUCCESS) - break; - } - } int64_t now = timeval_ms(); if (now - start > warn_after) { @@ -907,6 +910,15 @@ int mpsse_flush(struct mpsse_ctx *ctx) "ms.", now - start); warn_after *= 2; } + + if (retval == LIBUSB_ERROR_INTERRUPTED) + continue; + + if (retval != LIBUSB_SUCCESS) { + libusb_cancel_transfer(write_transfer); + if (read_transfer) + libusb_cancel_transfer(read_transfer); + } } error_check: diff --git a/src/jtag/drivers/mpsse.h b/src/jtag/drivers/mpsse.h index a017aff002..e95f842c9b 100644 --- a/src/jtag/drivers/mpsse.h +++ b/src/jtag/drivers/mpsse.h @@ -24,6 +24,13 @@ enum ftdi_chip_type { TYPE_FT2232H, TYPE_FT4232H, TYPE_FT232H, + TYPE_FT2233HP, + TYPE_FT4233HP, + TYPE_FT2232HP, + TYPE_FT4232HP, + TYPE_FT233HP, + TYPE_FT232HP, + TYPE_FT4232HA, }; struct mpsse_ctx; @@ -37,24 +44,21 @@ bool mpsse_is_high_speed(struct mpsse_ctx *ctx); /* Command queuing. These correspond to the MPSSE commands with the same names, but no need to care * about bit/byte transfer or data length limitation. Read data is guaranteed to be available only * after the following mpsse_flush(). */ -void mpsse_clock_data_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, - unsigned length, uint8_t mode); -void mpsse_clock_data_in(struct mpsse_ctx *ctx, uint8_t *in, unsigned in_offset, unsigned length, +void mpsse_clock_data_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, + unsigned int length, uint8_t mode); +void mpsse_clock_data_in(struct mpsse_ctx *ctx, uint8_t *in, unsigned int in_offset, unsigned int length, uint8_t mode); -void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, uint8_t *in, - unsigned in_offset, unsigned length, uint8_t mode); -void mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, - unsigned length, bool tdi, uint8_t mode); -void mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned out_offset, uint8_t *in, - unsigned in_offset, unsigned length, bool tdi, uint8_t mode); +void mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in, + unsigned int in_offset, unsigned int length, uint8_t mode); +void mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, + unsigned int length, bool tdi, uint8_t mode); +void mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in, + unsigned int in_offset, unsigned int length, bool tdi, uint8_t mode); void mpsse_set_data_bits_low_byte(struct mpsse_ctx *ctx, uint8_t data, uint8_t dir); void mpsse_set_data_bits_high_byte(struct mpsse_ctx *ctx, uint8_t data, uint8_t dir); void mpsse_read_data_bits_low_byte(struct mpsse_ctx *ctx, uint8_t *data); void mpsse_read_data_bits_high_byte(struct mpsse_ctx *ctx, uint8_t *data); void mpsse_loopback_config(struct mpsse_ctx *ctx, bool enable); -void mpsse_set_divisor(struct mpsse_ctx *ctx, uint16_t divisor); -int mpsse_divide_by_5_config(struct mpsse_ctx *ctx, bool enable); -int mpsse_rtck_config(struct mpsse_ctx *ctx, bool enable); /* Helper to set frequency in Hertz. Returns actual realizable frequency or negative error. * Frequency 0 means RTCK. */ @@ -62,6 +66,5 @@ int mpsse_set_frequency(struct mpsse_ctx *ctx, int frequency); /* Queue handling */ int mpsse_flush(struct mpsse_ctx *ctx); -void mpsse_purge(struct mpsse_ctx *ctx); #endif /* OPENOCD_JTAG_DRIVERS_MPSSE_H */ diff --git a/src/jtag/drivers/nulink_usb.c b/src/jtag/drivers/nulink_usb.c index 0bb5ec4443..66cf25a6d1 100644 --- a/src/jtag/drivers/nulink_usb.c +++ b/src/jtag/drivers/nulink_usb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016-2017 by Nuvoton * @@ -34,7 +34,7 @@ #define NULINK2_USB_PID1 (0x5200) #define NULINK2_USB_PID2 (0x5201) -struct nulink_usb_handle_s { +struct nulink_usb_handle { hid_device *dev_handle; uint16_t max_packet_size; uint8_t usbcmdidx; @@ -87,7 +87,7 @@ enum nulink_connect { static int nulink_usb_xfer_rw(void *handle, uint8_t *buf) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -107,7 +107,7 @@ static int nulink_usb_xfer_rw(void *handle, uint8_t *buf) static int nulink1_usb_xfer(void *handle, uint8_t *buf, int size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -120,7 +120,7 @@ static int nulink1_usb_xfer(void *handle, uint8_t *buf, int size) static int nulink2_usb_xfer(void *handle, uint8_t *buf, int size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -133,7 +133,7 @@ static int nulink2_usb_xfer(void *handle, uint8_t *buf, int size) static void nulink1_usb_init_buffer(void *handle, uint32_t size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; h->cmdidx = 0; @@ -149,7 +149,7 @@ static void nulink1_usb_init_buffer(void *handle, uint32_t size) static void nulink2_usb_init_buffer(void *handle, uint32_t size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; h->cmdidx = 0; @@ -165,7 +165,7 @@ static void nulink2_usb_init_buffer(void *handle, uint32_t size) static inline int nulink_usb_xfer(void *handle, uint8_t *buf, int size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -174,7 +174,7 @@ static inline int nulink_usb_xfer(void *handle, uint8_t *buf, int size) static inline void nulink_usb_init_buffer(void *handle, uint32_t size) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -183,7 +183,7 @@ static inline void nulink_usb_init_buffer(void *handle, uint32_t size) static int nulink_usb_version(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_version"); @@ -219,7 +219,7 @@ static int nulink_usb_version(void *handle) static int nulink_usb_idcode(void *handle, uint32_t *idcode) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_idcode"); @@ -243,7 +243,7 @@ static int nulink_usb_idcode(void *handle, uint32_t *idcode) static int nulink_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_write_debug_reg 0x%08" PRIX32 " 0x%08" PRIX32, addr, val); @@ -278,7 +278,7 @@ static int nulink_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val) static enum target_state nulink_usb_state(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -299,7 +299,7 @@ static enum target_state nulink_usb_state(void *handle) static int nulink_usb_assert_srst(void *handle, int srst) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_assert_srst"); @@ -324,7 +324,7 @@ static int nulink_usb_assert_srst(void *handle, int srst) static int nulink_usb_reset(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_reset"); @@ -349,7 +349,7 @@ static int nulink_usb_reset(void *handle) static int nulink_usb_run(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_run"); @@ -365,7 +365,7 @@ static int nulink_usb_run(void *handle) static int nulink_usb_halt(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_halt"); @@ -385,7 +385,7 @@ static int nulink_usb_halt(void *handle) static int nulink_usb_step(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_step"); @@ -405,7 +405,7 @@ static int nulink_usb_step(void *handle) static int nulink_usb_read_reg(void *handle, unsigned int regsel, uint32_t *val) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -444,7 +444,7 @@ static int nulink_usb_read_reg(void *handle, unsigned int regsel, uint32_t *val) static int nulink_usb_write_reg(void *handle, unsigned int regsel, uint32_t val) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -483,7 +483,7 @@ static int nulink_usb_read_mem8(void *handle, uint32_t addr, uint16_t len, int res = ERROR_OK; uint32_t offset = 0; uint32_t bytes_remaining = 12; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_read_mem8: addr 0x%08" PRIx32 ", len %" PRId16, addr, len); @@ -568,7 +568,7 @@ static int nulink_usb_write_mem8(void *handle, uint32_t addr, uint16_t len, int res = ERROR_OK; uint32_t offset = 0; uint32_t bytes_remaining = 12; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_write_mem8: addr 0x%08" PRIx32 ", len %" PRIu16, addr, len); @@ -675,7 +675,7 @@ static int nulink_usb_read_mem32(void *handle, uint32_t addr, uint16_t len, { int res = ERROR_OK; uint32_t bytes_remaining = 12; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -744,7 +744,7 @@ static int nulink_usb_write_mem32(void *handle, uint32_t addr, uint16_t len, { int res = ERROR_OK; uint32_t bytes_remaining = 12; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; assert(handle); @@ -819,7 +819,7 @@ static int nulink_usb_read_mem(void *handle, uint32_t addr, uint32_t size, uint32_t count, uint8_t *buffer) { int retval = ERROR_OK; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; /* calculate byte count */ count *= size; @@ -879,7 +879,7 @@ static int nulink_usb_write_mem(void *handle, uint32_t addr, uint32_t size, uint32_t count, const uint8_t *buffer) { int retval = ERROR_OK; - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; if (addr < ARM_SRAM_BASE) { LOG_DEBUG("nulink_usb_write_mem: address below ARM_SRAM_BASE, not supported.\n"); @@ -950,7 +950,7 @@ static int nulink_usb_override_target(const char *targetname) static int nulink_speed(void *handle, int khz, bool query) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; unsigned long max_ice_clock = khz; LOG_DEBUG("nulink_speed: query %s", query ? "yes" : "no"); @@ -1004,7 +1004,7 @@ static int nulink_speed(void *handle, int khz, bool query) static int nulink_usb_close(void *handle) { - struct nulink_usb_handle_s *h = handle; + struct nulink_usb_handle *h = handle; LOG_DEBUG("nulink_usb_close"); @@ -1018,7 +1018,7 @@ static int nulink_usb_close(void *handle) return ERROR_OK; } -static int nulink_usb_open(struct hl_interface_param_s *param, void **fd) +static int nulink_usb_open(struct hl_interface_param *param, void **fd) { struct hid_device_info *devs, *cur_dev; uint16_t target_vid = 0; @@ -1040,7 +1040,7 @@ static int nulink_usb_open(struct hl_interface_param_s *param, void **fd) return ERROR_FAIL; } - struct nulink_usb_handle_s *h = calloc(1, sizeof(*h)); + struct nulink_usb_handle *h = calloc(1, sizeof(*h)); if (!h) { LOG_ERROR("Out of memory"); goto error_open; @@ -1154,7 +1154,7 @@ static int nulink_usb_open(struct hl_interface_param_s *param, void **fd) return ERROR_FAIL; } -struct hl_layout_api_s nulink_usb_layout_api = { +struct hl_layout_api nulink_usb_layout_api = { .open = nulink_usb_open, .close = nulink_usb_close, .idcode = nulink_usb_idcode, diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c index 3c3ef4b16e..04626cb1e5 100644 --- a/src/jtag/drivers/opendous.c +++ b/src/jtag/drivers/opendous.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * * @@ -99,15 +99,15 @@ static char *opendous_type; static const struct opendous_probe *opendous_probe; /* External interface functions */ -static int opendous_execute_queue(void); +static int opendous_execute_queue(struct jtag_command *cmd_queue); static int opendous_init(void); static int opendous_quit(void); /* Queue command functions */ -static void opendous_end_state(tap_state_t state); +static void opendous_end_state(enum tap_state state); static void opendous_state_move(void); -static void opendous_path_move(int num_states, tap_state_t *path); -static void opendous_runtest(int num_cycles); +static void opendous_path_move(unsigned int num_states, enum tap_state *path); +static void opendous_runtest(unsigned int num_cycles); static void opendous_scan(int ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command); static void opendous_reset(int trst, int srst); @@ -229,7 +229,8 @@ static struct jtag_interface opendous_interface = { struct adapter_driver opendous_adapter_driver = { .name = "opendous", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = opendous_command_handlers, .init = opendous_init, @@ -238,9 +239,9 @@ struct adapter_driver opendous_adapter_driver = { .jtag_ops = &opendous_interface, }; -static int opendous_execute_queue(void) +static int opendous_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int scan_size; enum scan_type type; uint8_t *buffer; @@ -248,7 +249,7 @@ static int opendous_execute_queue(void) while (cmd) { switch (cmd->type) { case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); if (cmd->cmd.runtest->end_state != -1) @@ -265,7 +266,7 @@ static int opendous_execute_queue(void) break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %i", + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); @@ -347,7 +348,7 @@ static int opendous_init(void) opendous_jtag_handle = opendous_usb_open(); - if (opendous_jtag_handle == 0) { + if (!opendous_jtag_handle) { LOG_ERROR("Cannot find opendous Interface! Please check connection and permissions."); return ERROR_JTAG_INIT_FAILED; } @@ -393,7 +394,7 @@ static int opendous_quit(void) /***************************************************************************/ /* Queue command implementations */ -void opendous_end_state(tap_state_t state) +void opendous_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -419,11 +420,9 @@ void opendous_state_move(void) tap_set_state(tap_get_end_state()); } -void opendous_path_move(int num_states, tap_state_t *path) +void opendous_path_move(unsigned int num_states, enum tap_state *path) { - int i; - - for (i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (path[i] == tap_state_transition(tap_get_state(), false)) opendous_tap_append_step(0, 0); else if (path[i] == tap_state_transition(tap_get_state(), true)) @@ -440,11 +439,9 @@ void opendous_path_move(int num_states, tap_state_t *path) tap_set_end_state(tap_get_state()); } -void opendous_runtest(int num_cycles) +void opendous_runtest(unsigned int num_cycles) { - int i; - - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { @@ -453,7 +450,7 @@ void opendous_runtest(int num_cycles) } /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) opendous_tap_append_step(0, 0); /* finish in end_state */ @@ -464,7 +461,7 @@ void opendous_runtest(int num_cycles) void opendous_scan(int ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command) { - tap_state_t saved_end_state; + enum tap_state saved_end_state; opendous_tap_ensure_space(1, scan_size + 8); @@ -695,7 +692,7 @@ struct opendous_jtag *opendous_usb_open(void) struct opendous_jtag *result; struct libusb_device_handle *devh; - if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, &devh, NULL) != ERROR_OK) + if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, NULL, &devh, NULL) != ERROR_OK) return NULL; jtag_libusb_set_configuration(devh, 0); @@ -735,7 +732,7 @@ int opendous_usb_message(struct opendous_jtag *opendous_jtag, int out_length, in /* Write data from out_buffer to USB. */ int opendous_usb_write(struct opendous_jtag *opendous_jtag, int out_length) { - int result; + int result, transferred; if (out_length > OPENDOUS_OUT_BUFFER_SIZE) { LOG_ERROR("opendous_jtag_write illegal out_length=%d (max=%d)", out_length, OPENDOUS_OUT_BUFFER_SIZE); @@ -748,7 +745,11 @@ int opendous_usb_write(struct opendous_jtag *opendous_jtag, int out_length) if (opendous_probe->CONTROL_TRANSFER) { result = jtag_libusb_control_transfer(opendous_jtag->usb_handle, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_OUT, - FUNC_WRITE_DATA, 0, 0, (char *) usb_out_buffer, out_length, OPENDOUS_USB_TIMEOUT); + FUNC_WRITE_DATA, 0, 0, (char *)usb_out_buffer, out_length, OPENDOUS_USB_TIMEOUT, + &transferred); + /* FIXME: propagate error separately from transferred */ + if (result == ERROR_OK) + result = transferred; } else { jtag_libusb_bulk_write(opendous_jtag->usb_handle, OPENDOUS_WRITE_ENDPOINT, (char *)usb_out_buffer, out_length, OPENDOUS_USB_TIMEOUT, &result); @@ -768,6 +769,8 @@ int opendous_usb_write(struct opendous_jtag *opendous_jtag, int out_length) /* Read data from USB into in_buffer. */ int opendous_usb_read(struct opendous_jtag *opendous_jtag) { + int transferred; + #ifdef _DEBUG_USB_COMMS_ LOG_DEBUG("USB read begin"); #endif @@ -775,7 +778,11 @@ int opendous_usb_read(struct opendous_jtag *opendous_jtag) if (opendous_probe->CONTROL_TRANSFER) { result = jtag_libusb_control_transfer(opendous_jtag->usb_handle, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE | LIBUSB_ENDPOINT_IN, - FUNC_READ_DATA, 0, 0, (char *) usb_in_buffer, OPENDOUS_IN_BUFFER_SIZE, OPENDOUS_USB_TIMEOUT); + FUNC_READ_DATA, 0, 0, (char *)usb_in_buffer, OPENDOUS_IN_BUFFER_SIZE, OPENDOUS_USB_TIMEOUT, + &transferred); + /* FIXME: propagate error separately from transferred */ + if (result == ERROR_OK) + result = transferred; } else { jtag_libusb_bulk_read(opendous_jtag->usb_handle, OPENDOUS_READ_ENDPOINT, (char *)usb_in_buffer, OPENDOUS_IN_BUFFER_SIZE, OPENDOUS_USB_TIMEOUT, &result); @@ -796,17 +803,12 @@ int opendous_usb_read(struct opendous_jtag *opendous_jtag) void opendous_debug_buffer(uint8_t *buffer, int length) { - char line[81]; - char s[4]; - int i; - int j; + char line[8 + 3 * BYTES_PER_LINE + 1]; - for (i = 0; i < length; i += BYTES_PER_LINE) { - snprintf(line, 5, "%04x", i); - for (j = i; j < i + BYTES_PER_LINE && j < length; j++) { - snprintf(s, 4, " %02x", buffer[j]); - strcat(line, s); - } + for (int i = 0; i < length; i += BYTES_PER_LINE) { + int n = snprintf(line, 9, "%04x", i); + for (int j = i; j < i + BYTES_PER_LINE && j < length; j++) + n += snprintf(line + n, 4, " %02x", buffer[j]); LOG_DEBUG("%s", line); } } diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c index d77bdff5e6..943ad854e8 100644 --- a/src/jtag/drivers/openjtag.c +++ b/src/jtag/drivers/openjtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /******************************************************************************* * Driver for OpenJTAG Project (www.openjtag.org) * @@ -50,7 +50,7 @@ static const char * const openjtag_variant_names[] = { /* * OpenJTAG-OpenOCD state conversion */ -typedef enum openjtag_tap_state { +enum openjtag_tap_state { OPENJTAG_TAP_INVALID = -1, OPENJTAG_TAP_RESET = 0, OPENJTAG_TAP_IDLE = 1, @@ -68,7 +68,7 @@ typedef enum openjtag_tap_state { OPENJTAG_TAP_PAUSE_IR = 13, OPENJTAG_TAP_EXIT2_IR = 14, OPENJTAG_TAP_UPDATE_IR = 15, -} openjtag_tap_state_t; +}; /* OPENJTAG access library includes */ #include "libftdi_helper.h" @@ -239,10 +239,10 @@ static int openjtag_buf_write_cy7c65215( ret = jtag_libusb_control_transfer(usbh, CY7C65215_JTAG_REQUEST, CY7C65215_JTAG_WRITE, size, 0, - NULL, 0, CY7C65215_USB_TIMEOUT); - if (ret < 0) { - LOG_ERROR("vendor command failed, error %d", ret); - return ERROR_JTAG_DEVICE_ERROR; + NULL, 0, CY7C65215_USB_TIMEOUT, NULL); + if (ret != ERROR_OK) { + LOG_ERROR("vendor command failed"); + return ret; } if (jtag_libusb_bulk_write(usbh, ep_out, (char *)buf, size, @@ -306,10 +306,10 @@ static int openjtag_buf_read_cy7c65215( ret = jtag_libusb_control_transfer(usbh, CY7C65215_JTAG_REQUEST, CY7C65215_JTAG_READ, qty, 0, - NULL, 0, CY7C65215_USB_TIMEOUT); - if (ret < 0) { - LOG_ERROR("vendor command failed, error %d", ret); - return ERROR_JTAG_DEVICE_ERROR; + NULL, 0, CY7C65215_USB_TIMEOUT, NULL); + if (ret != ERROR_OK) { + LOG_ERROR("vendor command failed"); + return ret; } if (jtag_libusb_bulk_read(usbh, ep_in, (char *)buf, qty, @@ -438,7 +438,7 @@ static int openjtag_init_cy7c65215(void) int ret; usbh = NULL; - ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, &usbh, NULL); + ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, NULL, &usbh, NULL); if (ret != ERROR_OK) { LOG_ERROR("unable to open cy7c65215 device"); goto err; @@ -455,8 +455,8 @@ static int openjtag_init_cy7c65215(void) ret = jtag_libusb_control_transfer(usbh, CY7C65215_JTAG_REQUEST, CY7C65215_JTAG_ENABLE, - 0, 0, NULL, 0, CY7C65215_USB_TIMEOUT); - if (ret < 0) { + 0, 0, NULL, 0, CY7C65215_USB_TIMEOUT, NULL); + if (ret != ERROR_OK) { LOG_ERROR("could not enable JTAG module"); goto err; } @@ -466,7 +466,7 @@ static int openjtag_init_cy7c65215(void) err: if (usbh) jtag_libusb_close(usbh); - return ERROR_JTAG_INIT_FAILED; + return ret; } static int openjtag_init(void) @@ -508,8 +508,8 @@ static int openjtag_quit_cy7c65215(void) ret = jtag_libusb_control_transfer(usbh, CY7C65215_JTAG_REQUEST, CY7C65215_JTAG_DISABLE, - 0, 0, NULL, 0, CY7C65215_USB_TIMEOUT); - if (ret < 0) + 0, 0, NULL, 0, CY7C65215_USB_TIMEOUT, NULL); + if (ret != ERROR_OK) LOG_WARNING("could not disable JTAG module"); jtag_libusb_close(usbh); @@ -530,9 +530,20 @@ static int openjtag_quit(void) static void openjtag_write_tap_buffer(void) { uint32_t written; + uint32_t rx_expected = 0; + + /* calculate expected number of return bytes */ + for (int tx_offs = 0; tx_offs < usb_tx_buf_offs; tx_offs++) { + if ((usb_tx_buf[tx_offs] & 0x0F) == 6) { + rx_expected++; + tx_offs++; + } else if ((usb_tx_buf[tx_offs] & 0x0F) == 2) { + rx_expected++; + } + } openjtag_buf_write(usb_tx_buf, usb_tx_buf_offs, &written); - openjtag_buf_read(usb_rx_buf, usb_tx_buf_offs, &usb_rx_buf_len); + openjtag_buf_read(usb_rx_buf, rx_expected, &usb_rx_buf_len); usb_tx_buf_offs = 0; } @@ -660,14 +671,12 @@ static void openjtag_execute_reset(struct jtag_command *cmd) uint8_t buf = 0x00; - if (cmd->cmd.reset->trst) { - buf = 0x03; - } else { + /* Pull SRST low for 5 TCLK cycles */ + if (cmd->cmd.reset->srst) { buf |= 0x04; buf |= 0x05 << 4; + openjtag_add_byte(buf); } - - openjtag_add_byte(buf); } static void openjtag_execute_sleep(struct jtag_command *cmd) @@ -680,8 +689,14 @@ static void openjtag_set_state(uint8_t openocd_state) uint8_t state = openjtag_get_tap_state(openocd_state); uint8_t buf = 0; - buf = 0x01; - buf |= state << 4; + + if (state != OPENJTAG_TAP_RESET) { + buf = 0x01; + buf |= state << 4; + } else { + /* Force software TLR */ + buf = 0x03; + } openjtag_add_byte(buf); } @@ -733,7 +748,7 @@ static void openjtag_execute_scan(struct jtag_command *cmd) static void openjtag_execute_runtest(struct jtag_command *cmd) { - tap_state_t end_state = cmd->cmd.runtest->end_state; + enum tap_state end_state = cmd->cmd.runtest->end_state; tap_set_end_state(end_state); /* only do a state_move when we're not already in IDLE */ @@ -742,16 +757,20 @@ static void openjtag_execute_runtest(struct jtag_command *cmd) tap_set_state(TAP_IDLE); } - if (cmd->cmd.runtest->num_cycles > 16) - LOG_WARNING("num_cycles > 16 on run test"); - if (openjtag_variant != OPENJTAG_VARIANT_CY7C65215 || cmd->cmd.runtest->num_cycles) { uint8_t command; - command = 7; - command |= ((cmd->cmd.runtest->num_cycles - 1) & 0x0F) << 4; + unsigned int num_cycles = cmd->cmd.runtest->num_cycles; - openjtag_add_byte(command); + do { + const unsigned int num_cycles_cmd = MIN(num_cycles, 16); + + command = 7; + command |= ((num_cycles_cmd - 1) & 0x0F) << 4; + + openjtag_add_byte(command); + num_cycles -= num_cycles_cmd; + } while (num_cycles > 0); } tap_set_end_state(end_state); @@ -788,9 +807,9 @@ static void openjtag_execute_command(struct jtag_command *cmd) } } -static int openjtag_execute_queue(void) +static int openjtag_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; while (cmd) { openjtag_execute_command(cmd); @@ -859,6 +878,17 @@ COMMAND_HANDLER(openjtag_handle_variant_command) return ERROR_OK; } +COMMAND_HANDLER(openjtag_handle_vid_pid_command) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], openjtag_vid); + COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], openjtag_pid); + + return ERROR_OK; +} + static const struct command_registration openjtag_subcommand_handlers[] = { { .name = "device_desc", @@ -874,6 +904,13 @@ static const struct command_registration openjtag_subcommand_handlers[] = { .help = "set the OpenJTAG variant", .usage = "variant-string", }, + { + .name = "vid_pid", + .handler = openjtag_handle_vid_pid_command, + .mode = COMMAND_CONFIG, + .help = "USB VID and PID of the adapter", + .usage = "vid pid", + }, COMMAND_REGISTRATION_DONE }; @@ -894,7 +931,8 @@ static struct jtag_interface openjtag_interface = { struct adapter_driver openjtag_adapter_driver = { .name = "openjtag", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = openjtag_command_handlers, .init = openjtag_init, diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c index 676231b79f..de2e1f8ebe 100644 --- a/src/jtag/drivers/osbdm.c +++ b/src/jtag/drivers/osbdm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2012 by Jan Dakinevich * @@ -363,7 +363,7 @@ static int osbdm_flush(struct osbdm *osbdm, struct queue *queue) static int osbdm_open(struct osbdm *osbdm) { (void)memset(osbdm, 0, sizeof(*osbdm)); - if (jtag_libusb_open(osbdm_vid, osbdm_pid, &osbdm->devh, NULL) != ERROR_OK) + if (jtag_libusb_open(osbdm_vid, osbdm_pid, NULL, &osbdm->devh, NULL) != ERROR_OK) return ERROR_FAIL; if (libusb_claim_interface(osbdm->devh, 0) != ERROR_OK) @@ -380,8 +380,8 @@ static int osbdm_quit(void) static int osbdm_add_pathmove( struct queue *queue, - tap_state_t *path, - int num_states) + enum tap_state *path, + unsigned int num_states) { assert(num_states <= 32); @@ -392,7 +392,7 @@ static int osbdm_add_pathmove( } uint32_t tms = 0; - for (int i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (tap_state_transition(tap_get_state(), 1) == path[i]) { tms |= (1 << i); } else if (tap_state_transition(tap_get_state(), 0) == path[i]) { @@ -415,7 +415,7 @@ static int osbdm_add_pathmove( static int osbdm_add_statemove( struct queue *queue, - tap_state_t new_state, + enum tap_state new_state, int skip_first) { int len = 0; @@ -451,7 +451,7 @@ static int osbdm_add_statemove( static int osbdm_add_stableclocks( struct queue *queue, - int count) + unsigned int count) { if (!tap_is_state_stable(tap_get_state())) { LOG_ERROR("BUG: current state (%s) is not stable", @@ -489,8 +489,8 @@ static int osbdm_add_tms( static int osbdm_add_scan( struct queue *queue, struct scan_field *fields, - int num_fields, - tap_state_t end_state, + unsigned int num_fields, + enum tap_state end_state, bool ir_scan) { /* Move to desired shift state */ @@ -508,7 +508,7 @@ static int osbdm_add_scan( /* Add scan */ tap_set_end_state(end_state); - for (int idx = 0; idx < num_fields; idx++) { + for (unsigned int idx = 0; idx < num_fields; idx++) { struct sequence *next = queue_add_tail(queue, fields[idx].num_bits); if (!next) { LOG_ERROR("Can't allocate bit sequence"); @@ -536,8 +536,8 @@ static int osbdm_add_scan( static int osbdm_add_runtest( struct queue *queue, - int num_cycles, - tap_state_t end_state) + unsigned int num_cycles, + enum tap_state end_state) { if (osbdm_add_statemove(queue, TAP_IDLE, 0) != ERROR_OK) return ERROR_FAIL; @@ -628,7 +628,7 @@ static int osbdm_execute_command( return retval; } -static int osbdm_execute_queue(void) +static int osbdm_execute_queue(struct jtag_command *cmd_queue) { int retval = ERROR_OK; @@ -637,7 +637,7 @@ static int osbdm_execute_queue(void) LOG_ERROR("BUG: can't allocate bit queue"); retval = ERROR_FAIL; } else { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; while (retval == ERROR_OK && cmd) { retval = osbdm_execute_command(&osbdm_context, queue, cmd); @@ -684,7 +684,8 @@ static struct jtag_interface osbdm_interface = { struct adapter_driver osbdm_adapter_driver = { .name = "osbdm", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .init = osbdm_init, .quit = osbdm_quit, diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c index f1687f231b..143f3bde1f 100644 --- a/src/jtag/drivers/parport.c +++ b/src/jtag/drivers/parport.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -45,21 +45,31 @@ #include <windows.h> #endif -/* parallel port cable description - */ +// Parallel port cable description. struct cable { const char *name; - uint8_t TDO_MASK; /* status port bit containing current TDO value */ - uint8_t TRST_MASK; /* data port bit for TRST */ - uint8_t TMS_MASK; /* data port bit for TMS */ - uint8_t TCK_MASK; /* data port bit for TCK */ - uint8_t TDI_MASK; /* data port bit for TDI */ - uint8_t SRST_MASK; /* data port bit for SRST */ - uint8_t OUTPUT_INVERT; /* data port bits that should be inverted */ - uint8_t INPUT_INVERT; /* status port that should be inverted */ - uint8_t PORT_INIT; /* initialize data port with this value */ - uint8_t PORT_EXIT; /* de-initialize data port with this value */ - uint8_t LED_MASK; /* data port bit for LED */ + // Status port bit containing current TDO value. + uint8_t tdo_mask; + // Data port bit for TRST. + uint8_t trst_mask; + // Data port bit for TMD. + uint8_t tms_mask; + // Data port bit for TCK. + uint8_t tck_mask; + // Data port bit for TDI. + uint8_t tdi_mask; + // Data port bit for SRST. + uint8_t srst_mask; + // Data port bits that should be inverted. + uint8_t output_invert; + // Status port that should be inverted. + uint8_t input_invert; + // Initialize data port with this value. + uint8_t port_init; + // De-initialize data port with this value. + uint8_t port_exit; + // Data port bit for LED. + uint8_t led_mask; }; static const struct cable cables[] = { @@ -87,15 +97,14 @@ static const struct cable cables[] = { { NULL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }; -/* configuration */ +// Configuration variables. static char *parport_cable; static uint16_t parport_port; static bool parport_exit; static uint32_t parport_toggling_time_ns = 1000; static int wait_states; -/* interface variables - */ +// Interface variables. static const struct cable *cable; static uint8_t dataport_value; @@ -106,7 +115,7 @@ static unsigned long dataport; static unsigned long statusport; #endif -static bb_value_t parport_read(void) +static enum bb_value parport_read(void) { int data = 0; @@ -116,7 +125,7 @@ static bb_value_t parport_read(void) data = inb(statusport); #endif - if ((data ^ cable->INPUT_INVERT) & cable->TDO_MASK) + if ((data ^ cable->input_invert) & cable->tdo_mask) return BB_HIGH; else return BB_LOW; @@ -125,7 +134,7 @@ static bb_value_t parport_read(void) static inline void parport_write_data(void) { uint8_t output; - output = dataport_value ^ cable->OUTPUT_INVERT; + output = dataport_value ^ cable->output_invert; #if PARPORT_USE_PPDEV == 1 ioctl(device_handle, PPWDATA, &output); @@ -143,19 +152,19 @@ static int parport_write(int tck, int tms, int tdi) int i = wait_states + 1; if (tck) - dataport_value |= cable->TCK_MASK; + dataport_value |= cable->tck_mask; else - dataport_value &= ~cable->TCK_MASK; + dataport_value &= ~cable->tck_mask; if (tms) - dataport_value |= cable->TMS_MASK; + dataport_value |= cable->tms_mask; else - dataport_value &= ~cable->TMS_MASK; + dataport_value &= ~cable->tms_mask; if (tdi) - dataport_value |= cable->TDI_MASK; + dataport_value |= cable->tdi_mask; else - dataport_value &= ~cable->TDI_MASK; + dataport_value &= ~cable->tdi_mask; while (i-- > 0) parport_write_data(); @@ -163,33 +172,32 @@ static int parport_write(int tck, int tms, int tdi) return ERROR_OK; } -/* (1) assert or (0) deassert reset lines */ +// (1) assert or (0) deassert reset lines. static int parport_reset(int trst, int srst) { LOG_DEBUG("trst: %i, srst: %i", trst, srst); if (trst == 0) - dataport_value |= cable->TRST_MASK; + dataport_value |= cable->trst_mask; else if (trst == 1) - dataport_value &= ~cable->TRST_MASK; + dataport_value &= ~cable->trst_mask; if (srst == 0) - dataport_value |= cable->SRST_MASK; + dataport_value |= cable->srst_mask; else if (srst == 1) - dataport_value &= ~cable->SRST_MASK; + dataport_value &= ~cable->srst_mask; parport_write_data(); return ERROR_OK; } -/* turn LED on parport adapter on (1) or off (0) */ -static int parport_led(int on) +static int parport_led(bool on) { if (on) - dataport_value |= cable->LED_MASK; + dataport_value |= cable->led_mask; else - dataport_value &= ~cable->LED_MASK; + dataport_value &= ~cable->led_mask; parport_write_data(); @@ -204,7 +212,7 @@ static int parport_speed(int speed) static int parport_khz(int khz, int *jtag_speed) { - if (khz == 0) { + if (!khz) { LOG_DEBUG("RCLK not supported"); return ERROR_FAIL; } @@ -247,11 +255,11 @@ static int parport_get_giveio_access(void) } #endif -static struct bitbang_interface parport_bitbang = { - .read = &parport_read, - .write = &parport_write, - .blink = &parport_led, - }; +static const struct bitbang_interface parport_bitbang = { + .read = &parport_read, + .write = &parport_write, + .blink = &parport_led, +}; static int parport_init(void) { @@ -268,7 +276,7 @@ static int parport_init(void) } while (cur_cable->name) { - if (strcmp(cur_cable->name, parport_cable) == 0) { + if (!strcmp(cur_cable->name, parport_cable)) { cable = cur_cable; break; } @@ -280,7 +288,7 @@ static int parport_init(void) return ERROR_JTAG_INIT_FAILED; } - dataport_value = cable->PORT_INIT; + dataport_value = cable->port_init; #if PARPORT_USE_PPDEV == 1 if (device_handle > 0) { @@ -332,7 +340,7 @@ static int parport_init(void) #endif /* not __FreeBSD__, __FreeBSD_kernel__ */ #else /* not PARPORT_USE_PPDEV */ - if (parport_port == 0) { + if (!parport_port) { parport_port = 0x378; LOG_WARNING("No parport port specified, using default '0x378' (LPT1)"); } @@ -351,7 +359,7 @@ static int parport_init(void) } LOG_DEBUG("...privileges granted"); - /* make sure parallel port is in right mode (clear tristate and interrupt */ + // Make sure parallel port is in right mode (clear tristate and interrupt. #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) outb(parport_port + 2, 0x0); #else @@ -364,7 +372,7 @@ static int parport_init(void) return ERROR_FAIL; if (parport_write(0, 0, 0) != ERROR_OK) return ERROR_FAIL; - if (parport_led(1) != ERROR_OK) + if (parport_led(true) != ERROR_OK) return ERROR_FAIL; bitbang_interface = &parport_bitbang; @@ -374,11 +382,11 @@ static int parport_init(void) static int parport_quit(void) { - if (parport_led(0) != ERROR_OK) + if (parport_led(false) != ERROR_OK) return ERROR_FAIL; if (parport_exit) { - dataport_value = cable->PORT_EXIT; + dataport_value = cable->port_exit; parport_write_data(); } @@ -388,13 +396,13 @@ static int parport_quit(void) return ERROR_OK; } -COMMAND_HANDLER(parport_handle_parport_port_command) +COMMAND_HANDLER(parport_handle_port_command) { if (CMD_ARGC == 1) { - /* only if the port wasn't overwritten by cmdline */ - if (parport_port == 0) + // Only if the port wasn't overwritten by cmdline. + if (!parport_port) { COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], parport_port); - else { + } else { LOG_ERROR("The parport port was already configured!"); return ERROR_FAIL; } @@ -405,19 +413,23 @@ COMMAND_HANDLER(parport_handle_parport_port_command) return ERROR_OK; } -COMMAND_HANDLER(parport_handle_parport_cable_command) +COMMAND_HANDLER(parport_handle_cable_command) { - if (CMD_ARGC == 0) + if (!CMD_ARGC) return ERROR_OK; - /* only if the cable name wasn't overwritten by cmdline */ - if (parport_cable == 0) { - /* REVISIT first verify that it's listed in cables[] ... */ + // Only if the cable name wasn't overwritten by cmdline. + if (!parport_cable) { + // TODO: REVISIT first verify that it's listed in cables[]. parport_cable = malloc(strlen(CMD_ARGV[0]) + sizeof(char)); + if (!parport_cable) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } strcpy(parport_cable, CMD_ARGV[0]); } - /* REVISIT it's probably worth returning the current value ... */ + // TODO: REVISIT it's probably worth returning the current value. return ERROR_OK; } @@ -432,7 +444,7 @@ COMMAND_HANDLER(parport_handle_write_on_exit_command) return ERROR_OK; } -COMMAND_HANDLER(parport_handle_parport_toggling_time_command) +COMMAND_HANDLER(parport_handle_toggling_time_command) { if (CMD_ARGC == 1) { uint32_t ns; @@ -441,7 +453,7 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command) if (retval != ERROR_OK) return retval; - if (ns == 0) { + if (!ns) { LOG_ERROR("0 ns is not a valid parport toggling time"); return ERROR_FAIL; } @@ -449,9 +461,11 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command) parport_toggling_time_ns = ns; retval = adapter_get_speed(&wait_states); if (retval != ERROR_OK) { - /* if adapter_get_speed fails then the clock_mode - * has not been configured, this happens if parport_toggling_time is - * called before the adapter speed is set */ + /* + * If adapter_get_speed fails then the clock_mode has + * not been configured, this happens if toggling_time is + * called before the adapter speed is set. + */ LOG_INFO("no parport speed set - defaulting to zero wait states"); wait_states = 0; } @@ -466,7 +480,7 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command) static const struct command_registration parport_subcommand_handlers[] = { { .name = "port", - .handler = parport_handle_parport_port_command, + .handler = parport_handle_port_command, .mode = COMMAND_CONFIG, .help = "Display the address of the I/O port (e.g. 0x378) " "or the number of the '/dev/parport' device used. " @@ -475,11 +489,11 @@ static const struct command_registration parport_subcommand_handlers[] = { }, { .name = "cable", - .handler = parport_handle_parport_cable_command, + .handler = parport_handle_cable_command, .mode = COMMAND_CONFIG, .help = "Set the layout of the parallel port cable " "used to connect to the target.", - /* REVISIT there's no way to list layouts we know ... */ + // TODO: REVISIT there's no way to list layouts we know. .usage = "[layout]", }, { @@ -492,7 +506,7 @@ static const struct command_registration parport_subcommand_handlers[] = { }, { .name = "toggling_time", - .handler = parport_handle_parport_toggling_time_command, + .handler = parport_handle_toggling_time_command, .mode = COMMAND_CONFIG, .help = "Displays or assigns how many nanoseconds it " "takes for the hardware to toggle TCK.", @@ -519,7 +533,8 @@ static struct jtag_interface parport_interface = { struct adapter_driver parport_adapter_driver = { .name = "parport", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = parport_command_handlers, .init = parport_init, diff --git a/src/jtag/drivers/presto.c b/src/jtag/drivers/presto.c index 45663647b3..84b881cdc8 100644 --- a/src/jtag/drivers/presto.c +++ b/src/jtag/drivers/presto.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Pavel Chromy * @@ -528,7 +528,8 @@ static struct jtag_interface presto_interface = { struct adapter_driver presto_adapter_driver = { .name = "presto", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .init = presto_jtag_init, .quit = presto_jtag_quit, diff --git a/src/jtag/drivers/remote_bitbang.c b/src/jtag/drivers/remote_bitbang.c index d3118cc5e5..449c616545 100644 --- a/src/jtag/drivers/remote_bitbang.c +++ b/src/jtag/drivers/remote_bitbang.c @@ -1,8 +1,10 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Richard Uhler * * ruhler@mit.edu * + * * + * Copyright (C) 2021 by Manuel Wick <manuel@matronix.de> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -29,6 +31,8 @@ static int remote_bitbang_fd; static uint8_t remote_bitbang_send_buf[512]; static unsigned int remote_bitbang_send_buf_used; +static bool use_remote_sleep; + /* Circular buffer. When start == end, the buffer is empty. */ static char remote_bitbang_recv_buf[256]; static unsigned int remote_bitbang_recv_buf_start; @@ -110,12 +114,18 @@ static int remote_bitbang_fill_buf(enum block_bool block) contiguous_available_space); if (first && block == BLOCK) socket_nonblock(remote_bitbang_fd); - first = false; if (count > 0) { remote_bitbang_recv_buf_end += count; if (remote_bitbang_recv_buf_end == sizeof(remote_bitbang_recv_buf)) remote_bitbang_recv_buf_end = 0; } else if (count == 0) { + /* When read_socket returns 0, socket reached EOF and there is + * no data to read. But if request was blocking, the caller + * expected some data. Such situations should be treated as ERROR. */ + if (first && block == BLOCK) { + LOG_ERROR("remote_bitbang: socket closed by remote"); + return ERROR_FAIL; + } return ERROR_OK; } else if (count < 0) { #ifdef _WIN32 @@ -129,17 +139,18 @@ static int remote_bitbang_fill_buf(enum block_bool block) return ERROR_FAIL; } } + first = false; } return ERROR_OK; } -typedef enum { +enum flush_bool { NO_FLUSH, FLUSH_SEND_BUF -} flush_bool_t; +}; -static int remote_bitbang_queue(int c, flush_bool_t flush) +static int remote_bitbang_queue(int c, enum flush_bool flush) { remote_bitbang_send_buf[remote_bitbang_send_buf_used++] = c; if (flush == FLUSH_SEND_BUF || @@ -165,7 +176,7 @@ static int remote_bitbang_quit(void) return ERROR_OK; } -static bb_value_t char_to_int(int c) +static enum bb_value char_to_int(int c) { switch (c) { case '0': @@ -187,7 +198,7 @@ static int remote_bitbang_sample(void) return remote_bitbang_queue('R', NO_FLUSH); } -static bb_value_t remote_bitbang_read_sample(void) +static enum bb_value remote_bitbang_read_sample(void) { if (remote_bitbang_recv_buf_empty()) { if (remote_bitbang_fill_buf(BLOCK) != ERROR_OK) @@ -214,18 +225,70 @@ static int remote_bitbang_reset(int trst, int srst) return remote_bitbang_queue(c, FLUSH_SEND_BUF); } -static int remote_bitbang_blink(int on) +static int remote_bitbang_sleep(unsigned int microseconds) +{ + if (!use_remote_sleep) { + jtag_sleep(microseconds); + return ERROR_OK; + } + + int tmp; + unsigned int ms = microseconds / 1000; + unsigned int us = microseconds % 1000; + + for (unsigned int i = 0; i < ms; i++) { + tmp = remote_bitbang_queue('Z', NO_FLUSH); + if (tmp != ERROR_OK) + return tmp; + } + + for (unsigned int i = 0; i < us; i++) { + tmp = remote_bitbang_queue('z', NO_FLUSH); + if (tmp != ERROR_OK) + return tmp; + } + + return remote_bitbang_flush(); +} + +static int remote_bitbang_blink(bool on) { char c = on ? 'B' : 'b'; return remote_bitbang_queue(c, FLUSH_SEND_BUF); } -static struct bitbang_interface remote_bitbang_bitbang = { +static void remote_bitbang_swdio_drive(bool is_output) +{ + char c = is_output ? 'O' : 'o'; + if (remote_bitbang_queue(c, FLUSH_SEND_BUF) == ERROR_FAIL) + LOG_ERROR("Error setting direction for swdio"); +} + +static int remote_bitbang_swdio_read(void) +{ + if (remote_bitbang_queue('c', FLUSH_SEND_BUF) != ERROR_FAIL) + return remote_bitbang_read_sample(); + else + return BB_ERROR; +} + +static int remote_bitbang_swd_write(int swclk, int swdio) +{ + char c = 'd' + ((swclk ? 0x2 : 0x0) | (swdio ? 0x1 : 0x0)); + return remote_bitbang_queue(c, NO_FLUSH); +} + +static const struct bitbang_interface remote_bitbang_bitbang = { .buf_size = sizeof(remote_bitbang_recv_buf) - 1, .sample = &remote_bitbang_sample, .read_sample = &remote_bitbang_read_sample, .write = &remote_bitbang_write, + .swdio_read = &remote_bitbang_swdio_read, + .swdio_drive = &remote_bitbang_swdio_drive, + .swd_write = &remote_bitbang_swd_write, .blink = &remote_bitbang_blink, + .sleep = &remote_bitbang_sleep, + .flush = &remote_bitbang_flush, }; static int remote_bitbang_init_tcp(void) @@ -349,6 +412,16 @@ COMMAND_HANDLER(remote_bitbang_handle_remote_bitbang_host_command) return ERROR_COMMAND_SYNTAX_ERROR; } +COMMAND_HANDLER(remote_bitbang_handle_remote_bitbang_use_remote_sleep_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_ON_OFF(CMD_ARGV[0], use_remote_sleep); + + return ERROR_OK; +} + static const struct command_registration remote_bitbang_subcommand_handlers[] = { { .name = "port", @@ -366,7 +439,15 @@ static const struct command_registration remote_bitbang_subcommand_handlers[] = " if port is 0 or unset, this is the name of the unix socket to use.", .usage = "host_name", }, - COMMAND_REGISTRATION_DONE, + { + .name = "use_remote_sleep", + .handler = remote_bitbang_handle_remote_bitbang_use_remote_sleep_command, + .mode = COMMAND_CONFIG, + .help = "Rather than executing sleep locally, include delays in the " + "instruction stream for the remote host.", + .usage = "(on|off)", + }, + COMMAND_REGISTRATION_DONE }; static const struct command_registration remote_bitbang_command_handlers[] = { @@ -380,14 +461,14 @@ static const struct command_registration remote_bitbang_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static int remote_bitbang_execute_queue(void) +static int remote_bitbang_execute_queue(struct jtag_command *cmd_queue) { /* safety: the send buffer must be empty, no leftover characters from * previous transactions */ assert(remote_bitbang_send_buf_used == 0); /* process the JTAG command queue */ - int ret = bitbang_execute_queue(); + int ret = bitbang_execute_queue(cmd_queue); if (ret != ERROR_OK) return ret; @@ -401,7 +482,8 @@ static struct jtag_interface remote_bitbang_interface = { struct adapter_driver remote_bitbang_adapter_driver = { .name = "remote_bitbang", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = remote_bitbang_command_handlers, .init = &remote_bitbang_init, @@ -409,4 +491,5 @@ struct adapter_driver remote_bitbang_adapter_driver = { .reset = &remote_bitbang_reset, .jtag_ops = &remote_bitbang_interface, + .swd_ops = &bitbang_swd, }; diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c index ce02c92551..a818996255 100644 --- a/src/jtag/drivers/rlink.c +++ b/src/jtag/drivers/rlink.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -286,13 +286,13 @@ static uint8_t dtc_entry_download; static int dtc_load_from_buffer(struct libusb_device_handle *hdev_param, const uint8_t *buffer, size_t length) { - struct header_s { + struct header { uint8_t type; uint8_t length; }; int usb_err; - struct header_s *header; + struct header *header; uint8_t lut_start = 0xc0; dtc_entry_download = 0; @@ -311,7 +311,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *hdev_param, const u exit(1); } - header = (struct header_s *)buffer; + header = (struct header *)buffer; buffer += sizeof(*header); length -= sizeof(*header); @@ -632,7 +632,7 @@ static int dtc_queue_run(void) uint8_t dtc_mask, tdo_mask; uint8_t reply_buffer[USB_EP2IN_SIZE]; - assert((dtc_queue.rq_head != 0) == (dtc_queue.reply_index > 0)); + assert((!!dtc_queue.rq_head) == (dtc_queue.reply_index > 0)); assert(dtc_queue.cmd_index < USB_EP2BANK_SIZE); assert(dtc_queue.reply_index <= USB_EP2IN_SIZE); @@ -842,7 +842,7 @@ static int tap_state_queue_append(uint8_t tms) return 0; } -static void rlink_end_state(tap_state_t state) +static void rlink_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -869,7 +869,7 @@ static void rlink_state_move(void) static void rlink_path_move(struct pathmove_command *cmd) { - int num_states = cmd->num_states; + unsigned int num_states = cmd->num_states; int state_count; int tms = 0; @@ -896,11 +896,9 @@ static void rlink_path_move(struct pathmove_command *cmd) tap_set_end_state(tap_get_state()); } -static void rlink_runtest(int num_cycles) +static void rlink_runtest(unsigned int num_cycles) { - int i; - - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); /* only do a state_move when we're not already in RTI */ if (tap_get_state() != TAP_IDLE) { @@ -909,7 +907,7 @@ static void rlink_runtest(int num_cycles) } /* execute num_cycles */ - for (i = 0; i < num_cycles; i++) + for (unsigned int i = 0; i < num_cycles; i++) tap_state_queue_append(0); /* finish in end_state */ @@ -1021,7 +1019,7 @@ static int rlink_scan(struct jtag_command *cmd, enum scan_type type, uint8_t *buffer, int scan_size) { bool ir_scan; - tap_state_t saved_end_state; + enum tap_state saved_end_state; int byte_bits; int extra_bits; int chunk_bits; @@ -1262,9 +1260,9 @@ static int rlink_scan(struct jtag_command *cmd, enum scan_type type, return 0; } -static int rlink_execute_queue(void) +static int rlink_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -1323,7 +1321,7 @@ static int rlink_execute_queue(void) rlink_state_move(); break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %i", + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); rlink_path_move(cmd->cmd.pathmove); @@ -1448,7 +1446,7 @@ static int rlink_init(void) const uint16_t vids[] = { USB_IDVENDOR, 0 }; const uint16_t pids[] = { USB_IDPRODUCT, 0 }; - if (jtag_libusb_open(vids, pids, &hdev, NULL) != ERROR_OK) + if (jtag_libusb_open(vids, pids, NULL, &hdev, NULL) != ERROR_OK) return ERROR_FAIL; struct libusb_device_descriptor descriptor; @@ -1677,7 +1675,8 @@ static struct jtag_interface rlink_interface = { struct adapter_driver rlink_adapter_driver = { .name = "rlink", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .init = rlink_init, .quit = rlink_quit, diff --git a/src/jtag/drivers/rshim.c b/src/jtag/drivers/rshim.c index 86ae682480..89bdadd698 100644 --- a/src/jtag/drivers/rshim.c +++ b/src/jtag/drivers/rshim.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2020, Mellanox Technologies Ltd. - All Rights Reserved @@ -60,14 +60,14 @@ #ifdef HAVE_SYS_IOCTL_H /* Message used to program rshim via ioctl(). */ -typedef struct { +struct rshim_ioctl_msg { uint32_t addr; uint64_t data; -} __attribute__((packed)) rshim_ioctl_msg; +} __attribute__((packed)); enum { - RSH_IOC_READ = _IOWR('R', 0, rshim_ioctl_msg), - RSH_IOC_WRITE = _IOWR('R', 1, rshim_ioctl_msg), + RSH_IOC_READ = _IOWR('R', 0, struct rshim_ioctl_msg), + RSH_IOC_WRITE = _IOWR('R', 1, struct rshim_ioctl_msg), }; #endif @@ -104,7 +104,7 @@ static int rshim_dev_read(int chan, int addr, uint64_t *value) #ifdef HAVE_SYS_IOCTL_H if (rc < 0 && errno == ENOSYS) { - rshim_ioctl_msg msg; + struct rshim_ioctl_msg msg; msg.addr = addr; msg.data = 0; @@ -126,7 +126,7 @@ static int rshim_dev_write(int chan, int addr, uint64_t value) #ifdef HAVE_SYS_IOCTL_H if (rc < 0 && errno == ENOSYS) { - rshim_ioctl_msg msg; + struct rshim_ioctl_msg msg; msg.addr = addr; msg.data = value; @@ -254,8 +254,8 @@ static int rshim_dp_q_write(struct adiv5_dap *dap, unsigned int reg, dp_ctrl_stat = data; break; case DP_SELECT: - ap_sel = (data & DP_SELECT_APSEL) >> 24; - ap_bank = (data & DP_SELECT_APBANK) >> 4; + ap_sel = (data & ADIV5_DP_SELECT_APSEL) >> 24; + ap_bank = (data & ADIV5_DP_SELECT_APBANK) >> 4; break; default: LOG_INFO("Unknown command"); @@ -434,10 +434,8 @@ static void rshim_disconnect(struct adiv5_dap *dap) COMMAND_HANDLER(rshim_dap_device_command) { - if (CMD_ARGC != 1) { - command_print(CMD, "Too many arguments"); + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - } free(rshim_dev_path); rshim_dev_path = strdup(CMD_ARGV[0]); @@ -510,11 +508,10 @@ static const struct dap_ops rshim_dap_ops = { .quit = rshim_disconnect, }; -static const char *const rshim_dap_transport[] = { "dapdirect_swd", NULL }; - struct adapter_driver rshim_dap_adapter_driver = { .name = "rshim", - .transports = rshim_dap_transport, + .transport_ids = TRANSPORT_DAPDIRECT_SWD, + .transport_preferred_id = TRANSPORT_DAPDIRECT_SWD, .commands = rshim_dap_command_handlers, .init = rshim_dap_init, diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 58b71f1086..5ee1f85261 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2020 by Tarek Bochkati * @@ -84,6 +84,8 @@ #define STLINK_V3S_PID (0x374F) #define STLINK_V3_2VCP_PID (0x3753) #define STLINK_V3E_NO_MSD_PID (0x3754) +#define STLINK_V3P_USBLOADER_PID (0x3755) +#define STLINK_V3P_PID (0x3757) /* * ST-Link/V1, ST-Link/V2 and ST-Link/V2.1 are full-speed USB devices and @@ -138,7 +140,7 @@ struct stlink_usb_version { uint32_t flags; }; -struct stlink_usb_priv_s { +struct stlink_usb_priv { /** */ struct libusb_device_handle *fd; /** */ @@ -152,7 +154,7 @@ struct stlink_tcp_version { uint32_t build; }; -struct stlink_tcp_priv_s { +struct stlink_tcp_priv { /** */ int fd; /** */ @@ -169,9 +171,9 @@ struct stlink_tcp_priv_s { struct stlink_tcp_version version; }; -struct stlink_backend_s { +struct stlink_backend { /** */ - int (*open)(void *handle, struct hl_interface_param_s *param); + int (*open)(void *handle, struct hl_interface_param *param); /** */ int (*close)(void *handle); /** */ @@ -243,13 +245,13 @@ struct dap_queue { }; /** */ -struct stlink_usb_handle_s { +struct stlink_usb_handle { /** */ - struct stlink_backend_s *backend; + struct stlink_backend *backend; /** */ union { - struct stlink_usb_priv_s usb_backend_priv; - struct stlink_tcp_priv_s tcp_backend_priv; + struct stlink_usb_priv usb_backend_priv; + struct stlink_tcp_priv tcp_backend_priv; }; /** */ uint8_t rx_ep; @@ -292,22 +294,22 @@ struct stlink_usb_handle_s { }; /** */ -static inline int stlink_usb_open(void *handle, struct hl_interface_param_s *param) +static inline int stlink_usb_open(void *handle, struct hl_interface_param *param) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; return h->backend->open(handle, param); } /** */ static inline int stlink_usb_close(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; return h->backend->close(handle); } /** */ static inline int stlink_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; return h->backend->xfer_noerrcheck(handle, buf, size); } @@ -454,7 +456,7 @@ static inline int stlink_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, i #define STLINK_DEBUG_PORT_ACCESS 0xffff #define STLINK_TRACE_SIZE 4096 -#define STLINK_TRACE_MAX_HZ 2000000 +#define STLINK_TRACE_MAX_HZ 2250000 #define STLINK_V3_TRACE_MAX_HZ 24000000 #define STLINK_V3_MAX_FREQ_NB 10 @@ -565,7 +567,7 @@ static int stlink_usb_open_ap(void *handle, unsigned short apsel); /** */ static unsigned int stlink_usb_block(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -725,7 +727,7 @@ static int jtag_libusb_bulk_transfer_n( /** */ static int stlink_usb_xfer_v1_get_status(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int tr, ret; assert(handle); @@ -760,7 +762,7 @@ static int stlink_usb_xfer_v1_get_status(void *handle) #ifdef USE_LIBUSB_ASYNCIO static int stlink_usb_xfer_rw(void *handle, int cmdsize, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -798,7 +800,7 @@ static int stlink_usb_xfer_rw(void *handle, int cmdsize, const uint8_t *buf, int #else static int stlink_usb_xfer_rw(void *handle, int cmdsize, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int tr, ret; assert(handle); @@ -832,7 +834,7 @@ static int stlink_usb_xfer_rw(void *handle, int cmdsize, const uint8_t *buf, int static int stlink_usb_xfer_v1_get_sense(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -858,7 +860,7 @@ static int stlink_usb_xfer_v1_get_sense(void *handle) /** */ static int stlink_usb_usb_read_trace(void *handle, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int tr, ret; ret = jtag_libusb_bulk_read(h->usb_backend_priv.fd, h->trace_ep, (char *)buf, size, @@ -880,7 +882,7 @@ static int stlink_usb_usb_read_trace(void *handle, const uint8_t *buf, int size) static int stlink_usb_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, int size) { int err, cmdsize = STLINK_CMD_SIZE_V2; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -913,7 +915,7 @@ static int stlink_usb_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, int static int stlink_tcp_send_cmd(void *handle, int send_size, int recv_size, bool check_tcp_status) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -978,7 +980,7 @@ static int stlink_tcp_send_cmd(void *handle, int send_size, int recv_size, bool /** */ static int stlink_tcp_xfer_noerrcheck(void *handle, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int send_size = STLINK_TCP_USB_CMD_SIZE; int recv_size = STLINK_TCP_SS_SIZE; @@ -1038,7 +1040,7 @@ static int stlink_tcp_xfer_noerrcheck(void *handle, const uint8_t *buf, int size /** */ static int stlink_tcp_read_trace(void *handle, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; stlink_usb_init_buffer(h, h->trace_ep, 0); return stlink_tcp_xfer_noerrcheck(handle, buf, size); @@ -1050,7 +1052,7 @@ static int stlink_tcp_read_trace(void *handle, const uint8_t *buf, int size) */ static int stlink_usb_error_check(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1160,7 +1162,7 @@ static int stlink_cmd_allow_retry(void *handle, const uint8_t *buf, int size) { int retries = 0; int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; while (1) { if ((h->st_mode != STLINK_MODE_DEBUG_SWIM) || !retries) { @@ -1189,7 +1191,7 @@ static int stlink_cmd_allow_retry(void *handle, const uint8_t *buf, int size) /** */ static int stlink_usb_read_trace(void *handle, const uint8_t *buf, int size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1204,14 +1206,14 @@ static int stlink_usb_read_trace(void *handle, const uint8_t *buf, int size) */ static void stlink_usb_set_cbw_transfer_datalength(void *handle, uint32_t size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; buf_set_u32(h->cmdbuf+8, 0, 32, size); } static void stlink_usb_xfer_v1_create_cmd(void *handle, uint8_t direction, uint32_t size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; /* fill the send buffer */ strcpy((char *)h->cmdbuf, "USBC"); @@ -1232,7 +1234,7 @@ static void stlink_usb_xfer_v1_create_cmd(void *handle, uint8_t direction, uint3 /** */ static void stlink_usb_init_buffer(void *handle, uint8_t direction, uint32_t size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; h->direction = direction; @@ -1254,7 +1256,7 @@ static int stlink_usb_version(void *handle) uint8_t v, x, y, jtag, swim, msd, bridge = 0; char v_str[5 * (1 + 3) + 1]; /* VvJjMmBbSs */ char *p; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1297,8 +1299,8 @@ static int stlink_usb_version(void *handle) break; } - /* STLINK-V3 requires a specific command */ - if (v == 3 && x == 0 && y == 0) { + /* STLINK-V3 & STLINK-V3P require a specific command */ + if (v >= 3 && x == 0 && y == 0) { stlink_usb_init_buffer(handle, h->rx_ep, 16); h->cmdbuf[h->cmdidx++] = STLINK_APIV3_GET_VERSION_EX; @@ -1414,6 +1416,41 @@ static int stlink_usb_version(void *handle) if (h->version.jtag >= 6) flags |= STLINK_F_HAS_RW8_512BYTES; + break; + case 4: + /* STLINK-V3P use api-v3 */ + h->version.jtag_api = STLINK_JTAG_API_V3; + + /* STLINK-V3P is a superset of ST-LINK/V3 */ + + /* API for trace */ + /* API for target voltage */ + flags |= STLINK_F_HAS_TRACE; + + /* preferred API to get last R/W status */ + flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + + /* API to access DAP registers */ + flags |= STLINK_F_HAS_DAP_REG; + + /* API to read/write memory at 16 bit */ + /* API to write memory without address increment */ + flags |= STLINK_F_HAS_MEM_16BIT; + + /* API required to init AP before any AP access */ + flags |= STLINK_F_HAS_AP_INIT; + + /* API required to return proper error code on close AP */ + flags |= STLINK_F_FIX_CLOSE_AP; + + /* Banked regs (DPv1 & DPv2) support */ + /* API to read memory without address increment */ + /* Memory R/W supports CSW */ + flags |= STLINK_F_HAS_DPBANKSEL; + + /* 8bit read/write max packet size 512 bytes */ + flags |= STLINK_F_HAS_RW8_512BYTES; + break; default: break; @@ -1442,7 +1479,7 @@ static int stlink_usb_version(void *handle) static int stlink_usb_check_voltage(void *handle, float *target_voltage) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; uint32_t adc_results[2]; /* no error message, simply quit with error */ @@ -1474,7 +1511,7 @@ static int stlink_usb_check_voltage(void *handle, float *target_voltage) static int stlink_usb_set_swdclk(void *handle, uint16_t clk_divisor) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1498,7 +1535,7 @@ static int stlink_usb_set_swdclk(void *handle, uint16_t clk_divisor) static int stlink_usb_set_jtagclk(void *handle, uint16_t clk_divisor) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1524,7 +1561,7 @@ static int stlink_usb_set_jtagclk(void *handle, uint16_t clk_divisor) static int stlink_usb_current_mode(void *handle, uint8_t *mode) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1546,7 +1583,7 @@ static int stlink_usb_current_mode(void *handle, uint8_t *mode) static int stlink_usb_mode_enter(void *handle, enum stlink_mode type) { int rx_size = 0; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1594,7 +1631,7 @@ static int stlink_usb_mode_enter(void *handle, enum stlink_mode type) static int stlink_usb_mode_leave(void *handle, enum stlink_mode type) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1688,7 +1725,7 @@ static int stlink_usb_init_mode(void *handle, bool connect_under_reset, int init int res; uint8_t mode; enum stlink_mode emode; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -1792,7 +1829,7 @@ static int stlink_usb_init_mode(void *handle, bool connect_under_reset, int init /* request status from last swim request */ static int stlink_swim_status(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 4); @@ -1812,7 +1849,7 @@ static int stlink_swim_status(void *handle) __attribute__((unused)) static int stlink_swim_cap(void *handle, uint8_t *cap) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 8); @@ -1829,7 +1866,7 @@ static int stlink_swim_cap(void *handle, uint8_t *cap) /* debug dongle assert/deassert sreset line */ static int stlink_swim_assert_reset(void *handle, int reset) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 0); @@ -1850,7 +1887,7 @@ static int stlink_swim_assert_reset(void *handle, int reset) */ static int stlink_swim_enter(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 0); @@ -1865,7 +1902,7 @@ static int stlink_swim_enter(void *handle) /* switch high/low speed swim */ static int stlink_swim_speed(void *handle, int speed) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 0); @@ -1887,7 +1924,7 @@ static int stlink_swim_speed(void *handle, int speed) */ static int stlink_swim_generate_rst(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 0); @@ -1906,7 +1943,7 @@ static int stlink_swim_generate_rst(void *handle) */ static int stlink_swim_resync(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; stlink_usb_init_buffer(handle, h->rx_ep, 0); @@ -1920,7 +1957,7 @@ static int stlink_swim_resync(void *handle) static int stlink_swim_writebytes(void *handle, uint32_t addr, uint32_t len, const uint8_t *data) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; unsigned int i; unsigned int datalen = 0; @@ -1956,7 +1993,7 @@ static int stlink_swim_writebytes(void *handle, uint32_t addr, uint32_t len, con static int stlink_swim_readbytes(void *handle, uint32_t addr, uint32_t len, uint8_t *data) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; if (len > STLINK_SWIM_DATA_SIZE) @@ -1987,7 +2024,7 @@ static int stlink_swim_readbytes(void *handle, uint32_t addr, uint32_t len, uint static int stlink_usb_idcode(void *handle, uint32_t *idcode) { int res, offset; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2024,7 +2061,7 @@ static int stlink_usb_idcode(void *handle, uint32_t *idcode) static int stlink_usb_v2_read_debug_reg(void *handle, uint32_t addr, uint32_t *val) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int res; assert(handle); @@ -2046,7 +2083,7 @@ static int stlink_usb_v2_read_debug_reg(void *handle, uint32_t addr, uint32_t *v static int stlink_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2068,7 +2105,7 @@ static int stlink_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val) /** */ static int stlink_usb_trace_read(void *handle, uint8_t *buf, size_t *size) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2119,7 +2156,7 @@ static enum target_state stlink_usb_v2_get_status(void *handle) static enum target_state stlink_usb_state(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2161,7 +2198,7 @@ static enum target_state stlink_usb_state(void *handle) static int stlink_usb_assert_srst(void *handle, int srst) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2184,7 +2221,7 @@ static int stlink_usb_assert_srst(void *handle, int srst) static void stlink_usb_trace_disable(void *handle) { int res = ERROR_OK; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2206,7 +2243,7 @@ static void stlink_usb_trace_disable(void *handle) static int stlink_usb_trace_enable(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2237,7 +2274,7 @@ static int stlink_usb_trace_enable(void *handle) /** */ static int stlink_usb_reset(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int retval; assert(handle); @@ -2267,7 +2304,7 @@ static int stlink_usb_reset(void *handle) static int stlink_usb_run(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2289,7 +2326,7 @@ static int stlink_usb_run(void *handle) static int stlink_usb_halt(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2310,7 +2347,7 @@ static int stlink_usb_halt(void *handle) /** */ static int stlink_usb_step(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2334,7 +2371,7 @@ static int stlink_usb_step(void *handle) static int stlink_usb_read_regs(void *handle) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2359,7 +2396,7 @@ static int stlink_usb_read_regs(void *handle) static int stlink_usb_read_reg(void *handle, unsigned int regsel, uint32_t *val) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2399,7 +2436,7 @@ static int stlink_usb_read_reg(void *handle, unsigned int regsel, uint32_t *val) /** */ static int stlink_usb_write_reg(void *handle, unsigned int regsel, uint32_t val) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2428,7 +2465,7 @@ static int stlink_usb_write_reg(void *handle, unsigned int regsel, uint32_t val) static int stlink_usb_get_rw_status(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2453,7 +2490,7 @@ static int stlink_usb_read_mem8(void *handle, uint8_t ap_num, uint32_t csw, { int res; uint16_t read_len = len; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2497,7 +2534,7 @@ static int stlink_usb_write_mem8(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, const uint8_t *buffer) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2535,7 +2572,7 @@ static int stlink_usb_read_mem16(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, uint8_t *buffer) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2583,7 +2620,7 @@ static int stlink_usb_write_mem16(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, const uint8_t *buffer) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2629,7 +2666,7 @@ static int stlink_usb_read_mem32(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, uint8_t *buffer) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2674,7 +2711,7 @@ static int stlink_usb_write_mem32(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, const uint8_t *buffer) { int res; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -2715,9 +2752,9 @@ static int stlink_usb_write_mem32(void *handle, uint8_t ap_num, uint32_t csw, static int stlink_usb_read_mem32_noaddrinc(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, uint8_t *buffer) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; - assert(handle != NULL); + assert(handle); if (!(h->version.flags & STLINK_F_HAS_MEM_RD_NO_INC)) return ERROR_COMMAND_NOTFOUND; @@ -2757,9 +2794,9 @@ static int stlink_usb_read_mem32_noaddrinc(void *handle, uint8_t ap_num, uint32_ static int stlink_usb_write_mem32_noaddrinc(void *handle, uint8_t ap_num, uint32_t csw, uint32_t addr, uint16_t len, const uint8_t *buffer) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; - assert(handle != NULL); + assert(handle); if (!(h->version.flags & STLINK_F_HAS_MEM_WR_NO_INC)) return ERROR_COMMAND_NOTFOUND; @@ -2808,7 +2845,7 @@ static int stlink_usb_read_ap_mem(void *handle, uint8_t ap_num, uint32_t csw, int retval = ERROR_OK; uint32_t bytes_remaining; int retries = 0; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; /* calculate byte count */ count *= size; @@ -2893,7 +2930,7 @@ static int stlink_usb_write_ap_mem(void *handle, uint8_t ap_num, uint32_t csw, int retval = ERROR_OK; uint32_t bytes_remaining; int retries = 0; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; /* calculate byte count */ count *= size; @@ -3043,7 +3080,7 @@ static int stlink_match_speed_map(const struct speed_map *map, unsigned int map_ static int stlink_speed_swd(void *handle, int khz, bool query) { int speed_index; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; /* old firmware cannot change it */ if (!(h->version.flags & STLINK_F_HAS_SWD_SET_FREQ)) @@ -3066,7 +3103,7 @@ static int stlink_speed_swd(void *handle, int khz, bool query) static int stlink_speed_jtag(void *handle, int khz, bool query) { int speed_index; - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; /* old firmware cannot change it */ if (!(h->version.flags & STLINK_F_HAS_JTAG_SET_FREQ)) @@ -3098,7 +3135,7 @@ static void stlink_dump_speed_map(const struct speed_map *map, unsigned int map_ static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int i; if (h->version.jtag_api != STLINK_JTAG_API_V3) { @@ -3133,7 +3170,7 @@ static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map static int stlink_set_com_freq(void *handle, bool is_jtag, unsigned int frequency) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; if (h->version.jtag_api != STLINK_JTAG_API_V3) { LOG_ERROR("Unknown command"); @@ -3154,7 +3191,7 @@ static int stlink_set_com_freq(void *handle, bool is_jtag, unsigned int frequenc static int stlink_speed_v3(void *handle, bool is_jtag, int khz, bool query) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int speed_index; struct speed_map map[STLINK_V3_MAX_FREQ_NB]; @@ -3174,7 +3211,7 @@ static int stlink_speed_v3(void *handle, bool is_jtag, int khz, bool query) static int stlink_speed(void *handle, int khz, bool query) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; if (!handle) return khz; @@ -3204,7 +3241,7 @@ static int stlink_speed(void *handle, int khz, bool query) /** */ static int stlink_usb_usb_close(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; if (!h) return ERROR_OK; @@ -3225,7 +3262,7 @@ static int stlink_usb_usb_close(void *handle) /** */ static int stlink_tcp_close(void *handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; if (!h) return ERROR_OK; @@ -3258,7 +3295,7 @@ static int stlink_tcp_close(void *handle) static int stlink_close(void *handle) { if (handle) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; stlink_usb_close(handle); @@ -3348,9 +3385,9 @@ static char *stlink_usb_get_alternate_serial(struct libusb_device_handle *device } /** */ -static int stlink_usb_usb_open(void *handle, struct hl_interface_param_s *param) +static int stlink_usb_usb_open(void *handle, struct hl_interface_param *param) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int err, retry_count = 1; h->cmdbuf = malloc(STLINK_SG_SIZE); @@ -3369,7 +3406,7 @@ static int stlink_usb_usb_open(void *handle, struct hl_interface_param_s *param) in order to become operational. */ do { - if (jtag_libusb_open(param->vid, param->pid, + if (jtag_libusb_open(param->vid, param->pid, NULL, &h->usb_backend_priv.fd, stlink_usb_get_alternate_serial) != ERROR_OK) { LOG_ERROR("open failed"); return ERROR_FAIL; @@ -3402,6 +3439,8 @@ static int stlink_usb_usb_open(void *handle, struct hl_interface_param_s *param) case STLINK_V3S_PID: case STLINK_V3_2VCP_PID: case STLINK_V3E_NO_MSD_PID: + case STLINK_V3P_USBLOADER_PID: + case STLINK_V3P_PID: h->version.stlink = 3; h->tx_ep = STLINK_V2_1_TX_EP; h->trace_ep = STLINK_V2_1_TRACE_EP; @@ -3457,9 +3496,9 @@ static int stlink_usb_usb_open(void *handle, struct hl_interface_param_s *param) } /** */ -static int stlink_tcp_open(void *handle, struct hl_interface_param_s *param) +static int stlink_tcp_open(void *handle, struct hl_interface_param *param) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int ret; /* SWIM is not supported using stlink-server */ @@ -3672,36 +3711,36 @@ static int stlink_tcp_open(void *handle, struct hl_interface_param_s *param) return stlink_usb_version(h); } -static struct stlink_backend_s stlink_usb_backend = { +static struct stlink_backend stlink_usb_backend = { .open = stlink_usb_usb_open, .close = stlink_usb_usb_close, .xfer_noerrcheck = stlink_usb_usb_xfer_noerrcheck, .read_trace = stlink_usb_usb_read_trace, }; -static struct stlink_backend_s stlink_tcp_backend = { +static struct stlink_backend stlink_tcp_backend = { .open = stlink_tcp_open, .close = stlink_tcp_close, .xfer_noerrcheck = stlink_tcp_xfer_noerrcheck, .read_trace = stlink_tcp_read_trace, }; -static int stlink_open(struct hl_interface_param_s *param, enum stlink_mode mode, void **fd) +static int stlink_open(struct hl_interface_param *param, enum stlink_mode mode, void **fd) { - struct stlink_usb_handle_s *h; + struct stlink_usb_handle *h; LOG_DEBUG("stlink_open"); - h = calloc(1, sizeof(struct stlink_usb_handle_s)); + h = calloc(1, sizeof(struct stlink_usb_handle)); - if (h == 0) { + if (!h) { LOG_DEBUG("malloc failed"); return ERROR_FAIL; } h->st_mode = mode; - for (unsigned i = 0; param->vid[i]; i++) { + for (unsigned int i = 0; param->vid[i]; i++) { LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s", h->st_mode, param->vid[i], param->pid[i], adapter_get_required_serial() ? adapter_get_required_serial() : ""); @@ -3742,7 +3781,7 @@ static int stlink_open(struct hl_interface_param_s *param, enum stlink_mode mode } /* initialize the debug hardware */ - err = stlink_usb_init_mode(h, param->connect_under_reset, param->initial_interface_speed); + err = stlink_usb_init_mode(h, param->connect_under_reset, adapter_get_speed_khz()); if (err != ERROR_OK) { LOG_ERROR("init mode failed (unable to connect to the target)"); @@ -3790,7 +3829,7 @@ static int stlink_open(struct hl_interface_param_s *param, enum stlink_mode mode return ERROR_FAIL; } -static int stlink_usb_hl_open(struct hl_interface_param_s *param, void **fd) +static int stlink_usb_hl_open(struct hl_interface_param *param, void **fd) { return stlink_open(param, stlink_get_mode(param->transport), fd); } @@ -3800,7 +3839,7 @@ static int stlink_config_trace(void *handle, bool enabled, unsigned int *trace_freq, unsigned int traceclkin_freq, uint16_t *prescaler) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; if (!(h->version.flags & STLINK_F_HAS_TRACE)) { LOG_ERROR("The attached ST-LINK version doesn't support trace"); @@ -3820,7 +3859,7 @@ static int stlink_config_trace(void *handle, bool enabled, return ERROR_FAIL; } - unsigned int max_trace_freq = (h->version.stlink == 3) ? + unsigned int max_trace_freq = (h->version.stlink >= 3) ? STLINK_V3_TRACE_MAX_HZ : STLINK_TRACE_MAX_HZ; /* Only concern ourselves with the frequency if the STlink is processing it. */ @@ -3861,7 +3900,7 @@ static int stlink_config_trace(void *handle, bool enabled, /** */ static int stlink_usb_init_access_port(void *handle, unsigned char ap_num) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -3880,7 +3919,7 @@ static int stlink_usb_init_access_port(void *handle, unsigned char ap_num) /** */ static int stlink_usb_close_access_port(void *handle, unsigned char ap_num) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -3903,12 +3942,12 @@ static int stlink_usb_close_access_port(void *handle, unsigned char ap_num) static int stlink_usb_rw_misc_out(void *handle, uint32_t items, const uint8_t *buffer) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; unsigned int buflen = ALIGN_UP(items, 4) + 4 * items; LOG_DEBUG_IO("%s(%" PRIu32 ")", __func__, items); - assert(handle != NULL); + assert(handle); if (!(h->version.flags & STLINK_F_HAS_RW_MISC)) return ERROR_COMMAND_NOTFOUND; @@ -3924,12 +3963,12 @@ static int stlink_usb_rw_misc_out(void *handle, uint32_t items, const uint8_t *b static int stlink_usb_rw_misc_in(void *handle, uint32_t items, uint8_t *buffer) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; unsigned int buflen = 2 * 4 * items; LOG_DEBUG_IO("%s(%" PRIu32 ")", __func__, items); - assert(handle != NULL); + assert(handle); if (!(h->version.flags & STLINK_F_HAS_RW_MISC)) return ERROR_COMMAND_NOTFOUND; @@ -3952,7 +3991,7 @@ static int stlink_usb_rw_misc_in(void *handle, uint32_t items, uint8_t *buffer) static int stlink_read_dap_register(void *handle, unsigned short dap_port, unsigned short addr, uint32_t *val) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int retval; assert(handle); @@ -3976,7 +4015,7 @@ static int stlink_read_dap_register(void *handle, unsigned short dap_port, static int stlink_write_dap_register(void *handle, unsigned short dap_port, unsigned short addr, uint32_t val) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; assert(handle); @@ -3994,7 +4033,7 @@ static int stlink_write_dap_register(void *handle, unsigned short dap_port, } /** */ -struct hl_layout_api_s stlink_usb_layout_api = { +struct hl_layout_api stlink_usb_layout_api = { /** */ .open = stlink_usb_hl_open, /** */ @@ -4039,8 +4078,8 @@ struct hl_layout_api_s stlink_usb_layout_api = { * DAP direct interface */ -static struct stlink_usb_handle_s *stlink_dap_handle; -static struct hl_interface_param_s stlink_dap_param; +static struct stlink_usb_handle *stlink_dap_handle; +static struct hl_interface_param stlink_dap_param; static DECLARE_BITMAP(opened_ap, DP_APSEL_MAX + 1); static uint32_t last_csw_default[DP_APSEL_MAX + 1]; static int stlink_dap_error = ERROR_OK; @@ -4068,7 +4107,7 @@ static int stlink_dap_get_error(void) static int stlink_usb_open_ap(void *handle, unsigned short apsel) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; int retval; /* nothing to do on old versions */ @@ -4484,7 +4523,7 @@ static int stlink_usb_buf_rw_segment(void *handle, const struct dap_queue *q, un static int stlink_usb_count_misc_rw_queue(void *handle, const struct dap_queue *q, unsigned int len, unsigned int *pkt_items) { - struct stlink_usb_handle_s *h = handle; + struct stlink_usb_handle *h = handle; unsigned int i, items = 0; uint32_t ap_num = DP_APSEL_INVALID; unsigned int misc_max_items = (h->version.stlink == 2) ? STLINK_V2_RW_MISC_SIZE : STLINK_V3_RW_MISC_SIZE; @@ -5000,7 +5039,7 @@ COMMAND_HANDLER(stlink_dap_backend_command) COMMAND_HANDLER(stlink_dap_cmd_command) { unsigned int rx_n, tx_n; - struct stlink_usb_handle_s *h = stlink_dap_handle; + struct stlink_usb_handle *h = stlink_dap_handle; if (CMD_ARGC < 2) return ERROR_COMMAND_SYNTAX_ERROR; @@ -5104,7 +5143,12 @@ static int stlink_dap_init(void) if ((mode != STLINK_MODE_DEBUG_SWIM) && !(stlink_dap_handle->version.flags & STLINK_F_HAS_DAP_REG)) { - LOG_ERROR("ST-Link version does not support DAP direct transport"); + LOG_ERROR("The firmware in the ST-Link adapter only supports deprecated HLA."); + LOG_ERROR("Please consider updating the ST-Link firmware with a version"); + LOG_ERROR("newer that V2J24 (2015), available for downloading on ST website:"); + LOG_ERROR(" https://www.st.com/en/development-tools/stsw-link007.html"); + LOG_ERROR("In mean time, you can re-run OpenOCD for ST-Link HLA as:"); + LOG_ERROR(" openocd -f interface/stlink-hla.cfg ..."); return ERROR_FAIL; } return ERROR_OK; @@ -5135,7 +5179,6 @@ static int stlink_dap_speed(int speed) return ERROR_JTAG_NOT_IMPLEMENTED; } - stlink_dap_param.initial_interface_speed = speed; stlink_speed(stlink_dap_handle, speed, false); return ERROR_OK; } @@ -5179,11 +5222,10 @@ static const struct swim_driver stlink_swim_ops = { .reconnect = stlink_swim_op_reconnect, }; -static const char *const stlink_dap_transport[] = { "dapdirect_swd", "dapdirect_jtag", "swim", NULL }; - struct adapter_driver stlink_dap_adapter_driver = { .name = "st-link", - .transports = stlink_dap_transport, + .transport_ids = TRANSPORT_DAPDIRECT_SWD | TRANSPORT_DAPDIRECT_JTAG | TRANSPORT_SWIM, + .transport_preferred_id = TRANSPORT_DAPDIRECT_SWD, .commands = stlink_dap_command_handlers, .init = stlink_dap_init, diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c index 0cc4aac7cb..279b35377c 100644 --- a/src/jtag/drivers/sysfsgpio.c +++ b/src/jtag/drivers/sysfsgpio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au * @@ -255,7 +255,7 @@ static int sysfsgpio_swd_write(int swclk, int swdio) * The sysfs value will read back either '0' or '1'. The trick here is to call * lseek to bypass buffering in the sysfs kernel driver. */ -static bb_value_t sysfsgpio_read(void) +static enum bb_value sysfsgpio_read(void) { char buf[1]; @@ -545,8 +545,6 @@ static const struct command_registration sysfsgpio_command_handlers[] = { static int sysfsgpio_init(void); static int sysfsgpio_quit(void); -static const char * const sysfsgpio_transports[] = { "jtag", "swd", NULL }; - static struct jtag_interface sysfsgpio_interface = { .supported = DEBUG_CAP_TMS_SEQ, .execute_queue = bitbang_execute_queue, @@ -554,7 +552,8 @@ static struct jtag_interface sysfsgpio_interface = { struct adapter_driver sysfsgpio_adapter_driver = { .name = "sysfsgpio", - .transports = sysfsgpio_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = sysfsgpio_command_handlers, .init = sysfsgpio_init, @@ -565,13 +564,13 @@ struct adapter_driver sysfsgpio_adapter_driver = { .swd_ops = &bitbang_swd, }; -static struct bitbang_interface sysfsgpio_bitbang = { +static const struct bitbang_interface sysfsgpio_bitbang = { .read = sysfsgpio_read, .write = sysfsgpio_write, .swdio_read = sysfsgpio_swdio_read, .swdio_drive = sysfsgpio_swdio_drive, .swd_write = sysfsgpio_swd_write, - .blink = 0 + .blink = NULL, }; /* helper func to close and cleanup files only if they were valid/ used */ diff --git a/src/jtag/drivers/ti_icdi_usb.c b/src/jtag/drivers/ti_icdi_usb.c index 5c7b77c805..0e01171ea9 100644 --- a/src/jtag/drivers/ti_icdi_usb.c +++ b/src/jtag/drivers/ti_icdi_usb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * * @@ -33,7 +33,7 @@ #define PACKET_START "$" #define PACKET_END "#" -struct icdi_usb_handle_s { +struct icdi_usb_handle { struct libusb_device_handle *usb_dev; char *read_buffer; @@ -108,7 +108,7 @@ static int remote_unescape_input(const char *buffer, int len, char *out_buf, int static int icdi_send_packet(void *handle, int len) { unsigned char cksum = 0; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; int result, retry = 0; int transferred = 0; @@ -220,7 +220,7 @@ static int icdi_send_packet(void *handle, int len) static int icdi_send_cmd(void *handle, const char *cmd) { - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; int cmd_len = snprintf(h->write_buffer, h->max_packet, PACKET_START "%s", cmd); return icdi_send_packet(handle, cmd_len); @@ -228,7 +228,7 @@ static int icdi_send_cmd(void *handle, const char *cmd) static int icdi_send_remote_cmd(void *handle, const char *data) { - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; size_t cmd_len = sprintf(h->write_buffer, PACKET_START "qRcmd,"); cmd_len += hexify(h->write_buffer + cmd_len, (const uint8_t *)data, @@ -239,7 +239,7 @@ static int icdi_send_remote_cmd(void *handle, const char *data) static int icdi_get_cmd_result(void *handle) { - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; int offset = 0; char ch; @@ -284,7 +284,7 @@ static int icdi_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val) static enum target_state icdi_usb_state(void *handle) { int result; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; uint32_t dhcsr; uint8_t buf[4]; @@ -303,7 +303,7 @@ static enum target_state icdi_usb_state(void *handle) static int icdi_usb_version(void *handle) { - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; char version[20]; @@ -335,7 +335,7 @@ static int icdi_usb_query(void *handle) { int result; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; result = icdi_send_cmd(handle, "qSupported"); if (result != ERROR_OK) @@ -369,7 +369,7 @@ static int icdi_usb_query(void *handle) if (h->max_packet != ICDI_PACKET_SIZE) { h->read_buffer = realloc(h->read_buffer, h->max_packet); h->write_buffer = realloc(h->write_buffer, h->max_packet); - if (h->read_buffer == 0 || h->write_buffer == 0) { + if (!h->read_buffer || !h->write_buffer) { LOG_ERROR("unable to reallocate memory"); return ERROR_FAIL; } @@ -468,7 +468,7 @@ static int icdi_usb_read_regs(void *handle) static int icdi_usb_read_reg(void *handle, unsigned int regsel, uint32_t *val) { int result; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; char cmd[10]; snprintf(cmd, sizeof(cmd), "p%x", regsel); @@ -521,7 +521,7 @@ static int icdi_usb_write_reg(void *handle, unsigned int regsel, uint32_t val) static int icdi_usb_read_mem_int(void *handle, uint32_t addr, uint32_t len, uint8_t *buffer) { int result; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; char cmd[20]; snprintf(cmd, sizeof(cmd), "x%" PRIx32 ",%" PRIx32, addr, len); @@ -549,7 +549,7 @@ static int icdi_usb_read_mem_int(void *handle, uint32_t addr, uint32_t len, uint static int icdi_usb_write_mem_int(void *handle, uint32_t addr, uint32_t len, const uint8_t *buffer) { int result; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; size_t cmd_len = snprintf(h->write_buffer, h->max_packet, PACKET_START "X%" PRIx32 ",%" PRIx32 ":", addr, len); @@ -581,7 +581,7 @@ static int icdi_usb_read_mem(void *handle, uint32_t addr, uint32_t size, uint32_t count, uint8_t *buffer) { int retval = ERROR_OK; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; uint32_t bytes_remaining; /* calculate byte count */ @@ -609,7 +609,7 @@ static int icdi_usb_write_mem(void *handle, uint32_t addr, uint32_t size, uint32_t count, const uint8_t *buffer) { int retval = ERROR_OK; - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; uint32_t bytes_remaining; /* calculate byte count */ @@ -640,7 +640,7 @@ static int icdi_usb_override_target(const char *targetname) static int icdi_usb_close(void *handle) { - struct icdi_usb_handle_s *h = handle; + struct icdi_usb_handle *h = handle; if (!h) return ERROR_OK; @@ -654,17 +654,17 @@ static int icdi_usb_close(void *handle) return ERROR_OK; } -static int icdi_usb_open(struct hl_interface_param_s *param, void **fd) +static int icdi_usb_open(struct hl_interface_param *param, void **fd) { /* TODO: Convert remaining libusb_ calls to jtag_libusb_ */ int retval; - struct icdi_usb_handle_s *h; + struct icdi_usb_handle *h; LOG_DEBUG("icdi_usb_open"); - h = calloc(1, sizeof(struct icdi_usb_handle_s)); + h = calloc(1, sizeof(struct icdi_usb_handle)); - if (h == 0) { + if (!h) { LOG_ERROR("unable to allocate memory"); return ERROR_FAIL; } @@ -675,7 +675,7 @@ static int icdi_usb_open(struct hl_interface_param_s *param, void **fd) /* TI (Stellaris) ICDI provides its serial number in the USB descriptor; no need to provide a callback here. */ - jtag_libusb_open(param->vid, param->pid, &h->usb_dev, NULL); + jtag_libusb_open(param->vid, param->pid, NULL, &h->usb_dev, NULL); if (!h->usb_dev) { LOG_ERROR("open failed"); @@ -712,7 +712,7 @@ static int icdi_usb_open(struct hl_interface_param_s *param, void **fd) h->write_buffer = malloc(ICDI_PACKET_SIZE); h->max_packet = ICDI_PACKET_SIZE; - if (h->read_buffer == 0 || h->write_buffer == 0) { + if (!h->read_buffer || !h->write_buffer) { LOG_DEBUG("malloc failed"); goto error_open; } @@ -743,7 +743,7 @@ static int icdi_usb_open(struct hl_interface_param_s *param, void **fd) return ERROR_FAIL; } -struct hl_layout_api_s icdi_usb_layout_api = { +struct hl_layout_api icdi_usb_layout_api = { .open = icdi_usb_open, .close = icdi_usb_close, .idcode = icdi_usb_idcode, diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c index f4351f0819..417d560cde 100644 --- a/src/jtag/drivers/ulink.c +++ b/src/jtag/drivers/ulink.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011-2013 by Martin Schmoelzer * @@ -212,7 +212,7 @@ static int ulink_append_test_cmd(struct ulink *device); static int ulink_calculate_delay(enum ulink_delay_type type, long f, int *delay); /* Interface between OpenULINK and OpenOCD */ -static void ulink_set_end_state(tap_state_t endstate); +static void ulink_set_end_state(enum tap_state endstate); static int ulink_queue_statemove(struct ulink *device); static int ulink_queue_scan(struct ulink *device, struct jtag_command *cmd); @@ -227,7 +227,7 @@ static int ulink_post_process_scan(struct ulink_cmd *ulink_cmd); static int ulink_post_process_queue(struct ulink *device); /* adapter driver functions */ -static int ulink_execute_queue(void); +static int ulink_execute_queue(struct jtag_command *cmd_queue); static int ulink_khz(int khz, int *jtag_speed); static int ulink_speed(int speed); static int ulink_speed_div(int speed, int *khz); @@ -606,7 +606,7 @@ static void ulink_clear_queue(struct ulink *device) /* IN payload MUST be freed ONLY if no other commands use the * payload_in_start buffer */ - if (current->free_payload_in_start == true) { + if (current->free_payload_in_start) { free(current->payload_in_start); current->payload_in_start = NULL; current->payload_in = NULL; @@ -1393,7 +1393,7 @@ static long ulink_calculate_frequency(enum ulink_delay_type type, int delay) * * @param endstate the state the end state follower should be set to. */ -static void ulink_set_end_state(tap_state_t endstate) +static void ulink_set_end_state(enum tap_state endstate) { if (tap_is_state_stable(endstate)) tap_set_end_state(endstate); @@ -1473,7 +1473,7 @@ static int ulink_queue_scan(struct ulink *device, struct jtag_command *cmd) /* Allocate TDO buffer if required */ if ((type == SCAN_IN) || (type == SCAN_IO)) { - tdo_buffer_start = calloc(sizeof(uint8_t), scan_size_bytes); + tdo_buffer_start = calloc(scan_size_bytes, sizeof(uint8_t)); if (!tdo_buffer_start) return ERROR_FAIL; @@ -1701,15 +1701,17 @@ static int ulink_queue_reset(struct ulink *device, struct jtag_command *cmd) */ static int ulink_queue_pathmove(struct ulink *device, struct jtag_command *cmd) { - int ret, i, num_states, batch_size, state_count; - tap_state_t *path; + int ret, state_count; + enum tap_state *path; uint8_t tms_sequence; - num_states = cmd->cmd.pathmove->num_states; + unsigned int num_states = cmd->cmd.pathmove->num_states; path = cmd->cmd.pathmove->path; state_count = 0; while (num_states > 0) { + unsigned int batch_size; + tms_sequence = 0; /* Determine batch size */ @@ -1718,7 +1720,7 @@ static int ulink_queue_pathmove(struct ulink *device, struct jtag_command *cmd) else batch_size = num_states; - for (i = 0; i < batch_size; i++) { + for (unsigned int i = 0; i < batch_size; i++) { if (tap_state_transition(tap_get_state(), false) == path[state_count]) { /* Append '0' transition: clear bit 'i' in tms_sequence */ buf_set_u32(&tms_sequence, i, 1, 0x0); @@ -1774,14 +1776,13 @@ static int ulink_queue_sleep(struct ulink *device, struct jtag_command *cmd) static int ulink_queue_stableclocks(struct ulink *device, struct jtag_command *cmd) { int ret; - unsigned num_cycles; if (!tap_is_state_stable(tap_get_state())) { LOG_ERROR("JTAG_STABLECLOCKS: state not stable"); return ERROR_FAIL; } - num_cycles = cmd->cmd.stableclocks->num_cycles; + unsigned int num_cycles = cmd->cmd.stableclocks->num_cycles; /* TMS stays either high (Test Logic Reset state) or low (all other states) */ if (tap_get_state() == TAP_RESET) @@ -1860,7 +1861,7 @@ static int ulink_post_process_queue(struct ulink *device) /* Check if a corresponding OpenOCD command is stored for this * OpenULINK command */ - if ((current->needs_postprocessing == true) && (openocd_cmd)) { + if (current->needs_postprocessing && openocd_cmd) { switch (openocd_cmd->type) { case JTAG_SCAN: ret = ulink_post_process_scan(current); @@ -1905,9 +1906,9 @@ static int ulink_post_process_queue(struct ulink *device) * @return on success: ERROR_OK * @return on failure: ERROR_FAIL */ -static int ulink_execute_queue(void) +static int ulink_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int ret; while (cmd) { @@ -2130,7 +2131,7 @@ static int ulink_init(void) download_firmware = true; } - if (download_firmware == true) { + if (download_firmware) { LOG_INFO("Loading OpenULINK firmware. This is reversible by power-cycling" " ULINK device."); ret = ulink_load_firmware_and_renumerate(&ulink_handle, @@ -2270,7 +2271,8 @@ static struct jtag_interface ulink_interface = { struct adapter_driver ulink_adapter_driver = { .name = "ulink", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = ulink_command_handlers, .init = ulink_init, diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c index 212720280e..8f0ed96f34 100644 --- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c +++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for USB-JTAG, Altera USB-Blaster II and compatibles @@ -30,7 +30,7 @@ #define SECTION_BUFFERSIZE 16384 static int ublast2_libusb_read(struct ublast_lowlevel *low, uint8_t *buf, - unsigned size, uint32_t *bytes_read) + unsigned int size, uint32_t *bytes_read) { int ret, tmp = 0; @@ -103,7 +103,8 @@ static int ublast2_write_firmware_section(struct libusb_device_handle *libusb_de 0, (char *)data_ptr, chunk_size, - 100); + 100, + NULL); bytes_remaining -= chunk_size; addr += chunk_size; @@ -154,7 +155,8 @@ static int load_usb_blaster_firmware(struct libusb_device_handle *libusb_dev, 0, &value, 1, - 100); + 100, + NULL); /* Download all sections in the image to ULINK */ for (unsigned int i = 0; i < ublast2_firmware_image.num_sections; i++) { @@ -175,7 +177,8 @@ static int load_usb_blaster_firmware(struct libusb_device_handle *libusb_dev, 0, &value, 1, - 100); + 100, + NULL); error_close_firmware: image_close(&ublast2_firmware_image); @@ -199,7 +202,7 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low) bool renumeration = false; int ret; - if (jtag_libusb_open(vids, pids, &temp, NULL) == ERROR_OK) { + if (jtag_libusb_open(vids, pids, NULL, &temp, NULL) == ERROR_OK) { LOG_INFO("Altera USB-Blaster II (uninitialized) found"); LOG_INFO("Loading firmware..."); ret = load_usb_blaster_firmware(temp, low); @@ -212,14 +215,14 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low) const uint16_t vids_renum[] = { low->ublast_vid, 0 }; const uint16_t pids_renum[] = { low->ublast_pid, 0 }; - if (renumeration == false) { - if (jtag_libusb_open(vids_renum, pids_renum, &low->libusb_dev, NULL) != ERROR_OK) { + if (!renumeration) { + if (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev, NULL) != ERROR_OK) { LOG_ERROR("Altera USB-Blaster II not found"); return ERROR_FAIL; } } else { int retry = 10; - while (jtag_libusb_open(vids_renum, pids_renum, &low->libusb_dev, NULL) != ERROR_OK && retry--) { + while (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev, NULL) != ERROR_OK && retry--) { usleep(1000000); LOG_INFO("Waiting for reenumerate..."); } @@ -245,7 +248,8 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low) 0, buffer, 5, - 100); + 100, + NULL); LOG_INFO("Altera USB-Blaster II found (Firm. rev. = %s)", buffer); diff --git a/src/jtag/drivers/usb_blaster/ublast_access.h b/src/jtag/drivers/usb_blaster/ublast_access.h index 3e138bd23b..e9c9268131 100644 --- a/src/jtag/drivers/usb_blaster/ublast_access.h +++ b/src/jtag/drivers/usb_blaster/ublast_access.h @@ -30,7 +30,7 @@ struct ublast_lowlevel { int (*write)(struct ublast_lowlevel *low, uint8_t *buf, int size, uint32_t *bytes_written); - int (*read)(struct ublast_lowlevel *low, uint8_t *buf, unsigned size, + int (*read)(struct ublast_lowlevel *low, uint8_t *buf, unsigned int size, uint32_t *bytes_read); int (*open)(struct ublast_lowlevel *low); int (*close)(struct ublast_lowlevel *low); diff --git a/src/jtag/drivers/usb_blaster/ublast_access_ftdi.c b/src/jtag/drivers/usb_blaster/ublast_access_ftdi.c index 11b0e65d75..9647f2b82c 100644 --- a/src/jtag/drivers/usb_blaster/ublast_access_ftdi.c +++ b/src/jtag/drivers/usb_blaster/ublast_access_ftdi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for USB-JTAG, Altera USB-Blaster and compatibles @@ -28,7 +28,7 @@ static struct ftdi_context *ublast_getftdic(struct ublast_lowlevel *low) } static int ublast_ftdi_read(struct ublast_lowlevel *low, uint8_t *buf, - unsigned size, uint32_t *bytes_read) + unsigned int size, uint32_t *bytes_read) { int retval; int timeout = 100; diff --git a/src/jtag/drivers/usb_blaster/usb_blaster.c b/src/jtag/drivers/usb_blaster/usb_blaster.c index 50da09642c..81344664e2 100644 --- a/src/jtag/drivers/usb_blaster/usb_blaster.c +++ b/src/jtag/drivers/usb_blaster/usb_blaster.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for USB-JTAG, Altera USB-Blaster and compatibles @@ -158,7 +158,7 @@ static char *hexdump(uint8_t *buf, unsigned int size) return str; } -static int ublast_buf_read(uint8_t *buf, unsigned size, uint32_t *bytes_read) +static int ublast_buf_read(uint8_t *buf, unsigned int size, uint32_t *bytes_read) { int ret = info.drv->read(info.drv, buf, size, bytes_read); char *str = hexdump(buf, *bytes_read); @@ -474,11 +474,9 @@ static void ublast_tms(struct tms_command *cmd) */ static void ublast_path_move(struct pathmove_command *cmd) { - int i; - - LOG_DEBUG_IO("(num_states=%d, last_state=%d)", + LOG_DEBUG_IO("(num_states=%u, last_state=%d)", cmd->num_states, cmd->path[cmd->num_states - 1]); - for (i = 0; i < cmd->num_states; i++) { + for (unsigned int i = 0; i < cmd->num_states; i++) { if (tap_state_transition(tap_get_state(), false) == cmd->path[i]) ublast_clock_tms(0); if (tap_state_transition(tap_get_state(), true) == cmd->path[i]) @@ -496,7 +494,7 @@ static void ublast_path_move(struct pathmove_command *cmd) * Input the correct TMS sequence to the JTAG TAP so that we end up in the * target state. This assumes the current state (tap_get_state()) is correct. */ -static void ublast_state_move(tap_state_t state, int skip) +static void ublast_state_move(enum tap_state state, int skip) { uint8_t tms_scan; int tms_len; @@ -675,19 +673,19 @@ static void ublast_queue_tdi(uint8_t *bits, int nb_bits, enum scan_type scan) ublast_idle_clock(); } -static void ublast_runtest(int cycles, tap_state_t state) +static void ublast_runtest(unsigned int num_cycles, enum tap_state state) { - LOG_DEBUG_IO("%s(cycles=%i, end_state=%d)", __func__, cycles, state); + LOG_DEBUG_IO("%s(cycles=%u, end_state=%d)", __func__, num_cycles, state); ublast_state_move(TAP_IDLE, 0); - ublast_queue_tdi(NULL, cycles, SCAN_OUT); + ublast_queue_tdi(NULL, num_cycles, SCAN_OUT); ublast_state_move(state, 0); } -static void ublast_stableclocks(int cycles) +static void ublast_stableclocks(unsigned int num_cycles) { - LOG_DEBUG_IO("%s(cycles=%i)", __func__, cycles); - ublast_queue_tdi(NULL, cycles, SCAN_OUT); + LOG_DEBUG_IO("%s(cycles=%u)", __func__, num_cycles); + ublast_queue_tdi(NULL, num_cycles, SCAN_OUT); } /** @@ -765,7 +763,7 @@ static void ublast_initial_wipeout(void) tap_set_state(TAP_RESET); } -static int ublast_execute_queue(void) +static int ublast_execute_queue(struct jtag_command *cmd_queue) { struct jtag_command *cmd; static int first_call = 1; @@ -776,7 +774,7 @@ static int ublast_execute_queue(void) ublast_initial_wipeout(); } - for (cmd = jtag_command_queue; ret == ERROR_OK && cmd; + for (cmd = cmd_queue; ret == ERROR_OK && cmd; cmd = cmd->next) { switch (cmd->type) { case JTAG_RESET: @@ -1059,7 +1057,8 @@ static struct jtag_interface usb_blaster_interface = { struct adapter_driver usb_blaster_adapter_driver = { .name = "usb_blaster", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .commands = ublast_command_handlers, .init = ublast_init, diff --git a/src/jtag/drivers/usbprog.c b/src/jtag/drivers/usbprog.c index 061c0161ff..264b45f721 100644 --- a/src/jtag/drivers/usbprog.c +++ b/src/jtag/drivers/usbprog.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Benedikt Sauter * @@ -34,10 +34,10 @@ #define TCK_BIT 2 #define TMS_BIT 1 -static void usbprog_end_state(tap_state_t state); +static void usbprog_end_state(enum tap_state state); static void usbprog_state_move(void); static void usbprog_path_move(struct pathmove_command *cmd); -static void usbprog_runtest(int num_cycles); +static void usbprog_runtest(unsigned int num_cycles); static void usbprog_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size); #define UNKNOWN_COMMAND 0x00 @@ -83,9 +83,9 @@ static void usbprog_jtag_write_slice(struct usbprog_jtag *usbprog_jtag, unsigned static void usbprog_jtag_set_bit(struct usbprog_jtag *usbprog_jtag, int bit, int value); /* static int usbprog_jtag_get_bit(struct usbprog_jtag *usbprog_jtag, int bit); */ -static int usbprog_execute_queue(void) +static int usbprog_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; /* currently processed command */ + struct jtag_command *cmd = cmd_queue; /* currently processed command */ int scan_size; enum scan_type type; uint8_t *buffer; @@ -101,7 +101,7 @@ static int usbprog_execute_queue(void) usbprog_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); break; case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %i", + LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); usbprog_end_state(cmd->cmd.runtest->end_state); @@ -113,7 +113,7 @@ static int usbprog_execute_queue(void) usbprog_state_move(); break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %i", + LOG_DEBUG_IO("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); usbprog_path_move(cmd->cmd.pathmove); @@ -148,7 +148,7 @@ static int usbprog_init(void) usbprog_jtag_handle = usbprog_jtag_open(); tms_chain_index = 0; - if (usbprog_jtag_handle == 0) { + if (!usbprog_jtag_handle) { LOG_ERROR("Can't find USB JTAG Interface! Please check connection and permissions."); return ERROR_JTAG_INIT_FAILED; } @@ -168,7 +168,7 @@ static int usbprog_quit(void) } /*************** jtag execute commands **********************/ -static void usbprog_end_state(tap_state_t state) +static void usbprog_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -189,7 +189,7 @@ static void usbprog_state_move(void) static void usbprog_path_move(struct pathmove_command *cmd) { - int num_states = cmd->num_states; + unsigned int num_states = cmd->num_states; int state_count; /* There may be queued transitions, and before following a specified @@ -222,10 +222,8 @@ static void usbprog_path_move(struct pathmove_command *cmd) tap_set_end_state(tap_get_state()); } -static void usbprog_runtest(int num_cycles) +static void usbprog_runtest(unsigned int num_cycles) { - int i; - /* only do a state_move when we're not already in IDLE */ if (tap_get_state() != TAP_IDLE) { usbprog_end_state(TAP_IDLE); @@ -241,7 +239,7 @@ static void usbprog_runtest(int num_cycles) /* LOG_INFO("NUM CYCLES %i",num_cycles); */ } - for (i = 0; i < num_cycles; i++) { + for (unsigned int i = 0; i < num_cycles; i++) { usbprog_write(1, 0, 0); usbprog_write(0, 0, 0); } @@ -259,7 +257,7 @@ static void usbprog_runtest(int num_cycles) static void usbprog_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size) { - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); if (ir_scan) usbprog_end_state(TAP_IRSHIFT); @@ -335,15 +333,13 @@ static void usbprog_reset(int trst, int srst) /*************** jtag lowlevel functions ********************/ -struct usb_bus *busses; - struct usbprog_jtag *usbprog_jtag_open(void) { const uint16_t vids[] = { VID, 0 }; const uint16_t pids[] = { PID, 0 }; struct libusb_device_handle *dev; - if (jtag_libusb_open(vids, pids, &dev, NULL) != ERROR_OK) + if (jtag_libusb_open(vids, pids, NULL, &dev, NULL) != ERROR_OK) return NULL; struct usbprog_jtag *tmp = malloc(sizeof(struct usbprog_jtag)); @@ -594,7 +590,8 @@ static struct jtag_interface usbprog_interface = { struct adapter_driver usbprog_adapter_driver = { .name = "usbprog", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_JTAG, .init = usbprog_init, .quit = usbprog_quit, diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c index a81740cb18..29bfa8360d 100644 --- a/src/jtag/drivers/vdebug.c +++ b/src/jtag/drivers/vdebug.c @@ -1,35 +1,14 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ -/*---------------------------------------------------------------------------- - * Copyright 2020-2021 Cadence Design Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - *---------------------------------------------------------------------------- - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------- -*/ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) + +/* Copyright 2020-2022 Cadence Design Systems, Inc. */ /*! * @file * * @brief the virtual debug interface provides a connection between a sw debugger - * and the simulated, emulated core over a soft connection, implemented by DPI - * The vdebug debug driver currently supports JTAG transport - * TODO: implement support and test big endian platforms + * and the simulated, emulated core. The openOCD client connects via TCP sockets + * with vdebug server and over DPI-based transactor with the emulation or simulation + * The vdebug debug driver supports JTAG and DAP-level transports * */ @@ -68,24 +47,28 @@ #include "jtag/interface.h" #include "jtag/commands.h" #include "transport/transport.h" +#include "target/target.h" +#include "target/arm_adi_v5.h" #include "helper/time_support.h" #include "helper/replacements.h" #include "helper/log.h" +#include "helper/list.h" -#define VD_VERSION 43 +#define VD_VERSION 50 #define VD_BUFFER_LEN 4024 #define VD_CHEADER_LEN 24 #define VD_SHEADER_LEN 16 -#define VD_MAX_MEMORIES 4 -#define VD_POLL_INTERVAL 500 +#define VD_MAX_MEMORIES 20 +#define VD_POLL_INTERVAL 1000 #define VD_SCALE_PSTOMS 1000000000 /** * @brief List of transactor types */ enum { - VD_BFM_JTDP = 0x0001, /* transactor DAP JTAG DP */ + VD_BFM_TPIU = 0x0000, /* transactor trace TPIU */ + VD_BFM_DAP6 = 0x0001, /* transactor DAP ADI V6 */ VD_BFM_SWDP = 0x0002, /* transactor DAP SWD DP */ VD_BFM_AHB = 0x0003, /* transactor AMBA AHB */ VD_BFM_APB = 0x0004, /* transactor AMBA APB */ @@ -149,12 +132,21 @@ enum { VD_CMD_SIGSET = 0x0a, VD_CMD_SIGGET = 0x0b, VD_CMD_JTAGCLOCK = 0x0f, + VD_CMD_REGWRITE = 0x15, + VD_CMD_REGREAD = 0x16, VD_CMD_JTAGSHTAP = 0x1a, VD_CMD_MEMOPEN = 0x21, VD_CMD_MEMCLOSE = 0x22, VD_CMD_MEMWRITE = 0x23, }; +enum { + VD_ASPACE_AP = 0x01, + VD_ASPACE_DP = 0x02, + VD_ASPACE_ID = 0x03, + VD_ASPACE_AB = 0x04, +}; + enum { VD_BATCH_NO = 0, VD_BATCH_WO = 1, @@ -165,37 +157,32 @@ struct vd_shm { struct { /* VD_CHEADER_LEN written by client */ uint8_t cmd; /* 000; command */ uint8_t type; /* 001; interface type */ - uint16_t waddr; /* 002; write pointer */ - uint16_t wbytes; /* 004; data bytes */ - uint16_t rbytes; /* 006; data bytes to read */ - uint16_t wwords; /* 008; data words */ - uint16_t rwords; /* 00a; data words to read */ - uint32_t rwdata; /* 00c; read/write data */ - uint32_t offset; /* 010; address offset */ - uint16_t offseth; /* 014; address offset 47:32 */ - uint16_t wid; /* 016; request id*/ - }; - union { /* 018; */ - uint8_t wd8[VD_BUFFER_LEN]; - uint16_t wd16[VD_BUFFER_LEN / 2]; - uint32_t wd32[VD_BUFFER_LEN / 4]; - uint64_t wd64[VD_BUFFER_LEN / 8]; + uint8_t waddr[2]; /* 002; write pointer */ + uint8_t wbytes[2]; /* 004; data bytes */ + uint8_t rbytes[2]; /* 006; data bytes to read */ + uint8_t wwords[2]; /* 008; data words */ + uint8_t rwords[2]; /* 00a; data words to read */ + uint8_t rwdata[4]; /* 00c; read/write data */ + uint8_t offset[4]; /* 010; address offset */ + uint8_t offseth[2]; /* 014; address offset 47:32 */ + uint8_t wid[2]; /* 016; request id*/ }; + uint8_t wd8[VD_BUFFER_LEN]; /* 018; */ struct { /* VD_SHEADER_LEN written by server */ - uint16_t rid; /* fd0: request id read */ - uint16_t awords; /* fd2: actual data words read back */ - int32_t status; /* fd4; */ - uint64_t duttime; /* fd8; */ + uint8_t rid[2]; /* fd0: request id read */ + uint8_t awords[2]; /* fd2: actual data words read back */ + uint8_t status[4]; /* fd4; */ + uint8_t duttime[8]; /* fd8; */ }; - union { /* fe0: */ - uint8_t rd8[VD_BUFFER_LEN]; - uint16_t rd16[VD_BUFFER_LEN / 2]; - uint32_t rd32[VD_BUFFER_LEN / 4]; - uint64_t rd64[VD_BUFFER_LEN / 8]; - }; - uint32_t state; /* 1f98; connection state */ - uint32_t count; /* 1f9c; */ + uint8_t rd8[VD_BUFFER_LEN]; /* fe0: */ + uint8_t state[4]; /* 1f98; connection state */ + uint8_t count[4]; /* 1f9c; */ uint8_t dummy[96]; /* 1fa0; 48+40B+8B; */ +} __attribute__((packed)); + +struct vd_rdata { + struct list_head lh; + uint8_t *rdata; }; struct vd_client { @@ -219,10 +206,11 @@ struct vd_client { uint32_t poll_max; uint32_t targ_time; int hsocket; + int64_t poll_ts; char server_name[32]; char bfm_path[128]; char mem_path[VD_MAX_MEMORIES][128]; - uint8_t *tdo; + struct vd_rdata rdataq; }; struct vd_jtag_hdr { @@ -234,6 +222,16 @@ struct vd_jtag_hdr { uint64_t rlen:16; }; +struct vd_reg_hdr { + uint64_t prot:3; + uint64_t nonincr:1; + uint64_t haddr:12; + uint64_t tlen:11; + uint64_t asize:3; + uint64_t cmd:2; + uint64_t addr:32; +}; + static struct vd_shm *pbuf; static struct vd_client vdc; @@ -256,8 +254,13 @@ static int vdebug_socket_open(char *server_addr, uint32_t port) #ifdef _WIN32 hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP); - if (hsock == INVALID_SOCKET) + if (hsock < 0) rc = vdebug_socket_error(); +#elif defined __CYGWIN__ + /* SO_RCVLOWAT unsupported on CYGWIN */ + hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP); + if (hsock < 0) + rc = errno; #else uint32_t rcvwat = VD_SHEADER_LEN; /* size of the rcv header, as rcv min watermark */ hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP); @@ -277,7 +280,7 @@ static int vdebug_socket_open(char *server_addr, uint32_t port) LOG_ERROR("socket_open: cannot resolve address %s, error %d", server_addr, vdebug_socket_error()); rc = VD_ERR_SOC_ADDR; } else { - ((struct sockaddr_in *)(ainfo->ai_addr))->sin_port = htons(port); + h_u16_to_be((uint8_t *)ainfo->ai_addr->sa_data, port); if (connect(hsock, ainfo->ai_addr, sizeof(struct sockaddr)) < 0) { LOG_ERROR("socket_open: cannot connect to %s:%d, error %d", server_addr, port, vdebug_socket_error()); rc = VD_ERR_SOC_CONN; @@ -299,8 +302,8 @@ static int vdebug_socket_receive(int hsock, struct vd_shm *pmem) { int rc; int dreceived = 0; - int offset = (uint8_t *)&pmem->rid - &pmem->cmd; - int to_receive = VD_SHEADER_LEN + pmem->rbytes; + int offset = &pmem->rid[0] - &pmem->cmd; + int to_receive = VD_SHEADER_LEN + le_to_h_u16(pmem->rbytes); char *pb = (char *)pmem; do { @@ -320,7 +323,7 @@ static int vdebug_socket_receive(int hsock, struct vd_shm *pmem) static int vdebug_socket_send(int hsock, struct vd_shm *pmem) { - int rc = send(hsock, (const char *)&pmem->cmd, VD_CHEADER_LEN + pmem->wbytes, 0); + int rc = send(hsock, (const char *)&pmem->cmd, VD_CHEADER_LEN + le_to_h_u16(pmem->wbytes), 0); if (rc <= 0) LOG_WARNING("socket_send: send failed, error %d", vdebug_socket_error()); else @@ -333,6 +336,7 @@ static uint32_t vdebug_wait_server(int hsock, struct vd_shm *pmem) { if (!hsock) return VD_ERR_SOC_OPEN; + int st = vdebug_socket_send(hsock, pmem); if (st <= 0) return VD_ERR_SOC_SEND; @@ -341,14 +345,14 @@ static uint32_t vdebug_wait_server(int hsock, struct vd_shm *pmem) if (rd <= 0) return VD_ERR_SOC_RECV; - int rc = pmem->status; + int rc = le_to_h_u32(pmem->status); LOG_DEBUG_IO("wait_server: cmd %02" PRIx8 " done, sent %d, rcvd %d, status %d", - pmem->cmd, st, rd, rc); + pmem->cmd, st, rd, rc); return rc; } -int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm, unsigned int count) +static int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm, unsigned int count) { uint8_t num_pre, num_post, tdi, tms; unsigned int num, anum, bytes, hwords, words; @@ -356,22 +360,23 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm, unsigned int count) int64_t ts, te; uint8_t *tdo; int rc; - struct vd_jtag_hdr *hdr; + uint64_t jhdr; + struct vd_rdata *rd; req = 0; /* beginning of request */ waddr = 0; rwords = 0; - pm->wbytes = pm->wwords * vdc.buf_width; - pm->rbytes = pm->rwords * vdc.buf_width; + h_u16_to_le(pm->wbytes, le_to_h_u16(pm->wwords) * vdc.buf_width); + h_u16_to_le(pm->rbytes, le_to_h_u16(pm->rwords) * vdc.buf_width); ts = timeval_ms(); rc = vdebug_wait_server(hsock, pm); while (!rc && (req < count)) { /* loop over requests to read data and print out */ - hdr = (struct vd_jtag_hdr *)&pm->wd8[waddr * 4]; - hwords = hdr->wlen; - words = hdr->rlen; - anum = hdr->tlen; - num_pre = hdr->pre; - num_post = hdr->post; + jhdr = le_to_h_u64(&pm->wd8[waddr * 4]); + words = jhdr >> 48; + hwords = (jhdr >> 32) & 0xffff; + anum = jhdr & 0xffffff; + num_pre = (jhdr >> 27) & 0x7; + num_post = (jhdr >> 24) & 0x7; if (num_post) num = anum - num_pre - num_post + 1; else @@ -379,21 +384,29 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm, unsigned int count) bytes = (num + 7) / 8; vdc.trans_last = (req + 1) < count ? 0 : 1; vdc.trans_first = waddr ? 0 : 1; - if (hdr->cmd == 3) { /* read */ - tdo = vdc.tdo; + if (((jhdr >> 30) & 0x3) == 3) { /* cmd is read */ + if (!rwords) { + rd = &vdc.rdataq; + tdo = rd->rdata; + } else { + rd = list_first_entry(&vdc.rdataq.lh, struct vd_rdata, lh); + tdo = rd->rdata; + list_del(&rd->lh); + free(rd); + } for (unsigned int j = 0; j < bytes; j++) { tdo[j] = (pm->rd8[rwords * 8 + j] >> num_pre) | (pm->rd8[rwords * 8 + j + 1] << (8 - num_pre)); - LOG_DEBUG_IO("%04x D0[%02x]:%02x", pm->wid - count + req, j, tdo[j]); + LOG_DEBUG_IO("%04x D0[%02x]:%02x", le_to_h_u16(pm->wid) - count + req, j, tdo[j]); } rwords += words; /* read data offset */ } else { tdo = NULL; } - waddr += sizeof(struct vd_jtag_hdr) / 4; /* waddr past header */ + waddr += sizeof(uint64_t) / 4; /* waddr past header */ tdi = (pm->wd8[waddr * 4] >> num_pre) | (pm->wd8[waddr * 4 + 1] << (8 - num_pre)); tms = (pm->wd8[waddr * 4 + 4] >> num_pre) | (pm->wd8[waddr * 4 + 4 + 1] << (8 - num_pre)); - LOG_DEBUG("%04x L:%02d O:%05x @%03x DI:%02x MS:%02x DO:%02x", - pm->wid - count + req, num, (vdc.trans_first << 14) | (vdc.trans_last << 15), + LOG_DEBUG_IO("%04x L:%02d O:%05x @%03x DI:%02x MS:%02x DO:%02x", + le_to_h_u16(pm->wid) - count + req, num, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr - 2, tdi, tms, (tdo ? tdo[0] : 0xdd)); waddr += hwords * 2; /* start of next request */ req += 1; @@ -406,10 +419,83 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm, unsigned int count) te = timeval_ms(); vdc.targ_time += (uint32_t)(te - ts); - pm->offseth = 0; /* reset buffer write address */ - pm->offset = 0; - pm->rwords = 0; - pm->waddr = 0; + h_u16_to_le(pm->offseth, 0); /* reset buffer write address */ + h_u32_to_le(pm->offset, 0); + h_u16_to_le(pm->rwords, 0); + h_u16_to_le(pm->waddr, 0); + assert(list_empty(&vdc.rdataq.lh));/* list should be empty after run queue */ + + return rc; +} + +static int vdebug_run_reg_queue(int hsock, struct vd_shm *pm, unsigned int count) +{ + unsigned int num, awidth, wwidth; + unsigned int req, waddr, rwords; + uint8_t aspace; + uint32_t addr; + int64_t ts, te; + uint8_t *data; + int rc; + uint64_t rhdr; + struct vd_rdata *rd; + + req = 0; /* beginning of request */ + waddr = 0; + rwords = 0; + h_u16_to_le(pm->wbytes, le_to_h_u16(pm->wwords) * vdc.buf_width); + h_u16_to_le(pm->rbytes, le_to_h_u16(pm->rwords) * vdc.buf_width); + ts = timeval_ms(); + rc = vdebug_wait_server(hsock, pm); + while (!rc && (req < count)) { /* loop over requests to read data and print out */ + rhdr = le_to_h_u64(&pm->wd8[waddr * 4]); + addr = rhdr >> 32; /* reconstruct data for a single request */ + num = (rhdr >> 16) & 0x7ff; + aspace = rhdr & 0x3; + awidth = (1 << ((rhdr >> 27) & 0x7)); + wwidth = (awidth + vdc.buf_width - 1) / vdc.buf_width; + vdc.trans_last = (req + 1) < count ? 0 : 1; + vdc.trans_first = waddr ? 0 : 1; + if (((rhdr >> 30) & 0x3) == 2) { /* cmd is read */ + if (num) { + if (!rwords) { + rd = &vdc.rdataq; + data = rd->rdata; + } else { + rd = list_first_entry(&vdc.rdataq.lh, struct vd_rdata, lh); + data = rd->rdata; + list_del(&rd->lh); + free(rd); + } + for (unsigned int j = 0; j < num; j++) + memcpy(&data[j * awidth], &pm->rd8[(rwords + j) * awidth], awidth); + } + LOG_DEBUG("read %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req, + aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr, + (num ? le_to_h_u32(&pm->rd8[rwords * 4]) : 0xdead)); + rwords += num * wwidth; + waddr += sizeof(uint64_t) / 4; /* waddr past header */ + } else { + LOG_DEBUG("write %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req, + aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr, + le_to_h_u32(&pm->wd8[(waddr + num + 1) * 4])); + waddr += sizeof(uint64_t) / 4 + (num * wwidth * awidth + 3) / 4; + } + req += 1; + } + + if (rc) { + LOG_ERROR("0x%x executing transaction", rc); + rc = ERROR_FAIL; + } + + te = timeval_ms(); + vdc.targ_time += (uint32_t)(te - ts); + h_u16_to_le(pm->offseth, 0); /* reset buffer write address */ + h_u32_to_le(pm->offset, 0); + h_u16_to_le(pm->rwords, 0); + h_u16_to_le(pm->waddr, 0); + assert(list_empty(&vdc.rdataq.lh));/* list should be empty after run queue */ return rc; } @@ -420,35 +506,35 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const char *path, int rc = VD_ERR_NOT_OPEN; pm->cmd = VD_CMD_OPEN; - pm->wid = VD_VERSION; /* client version */ - pm->wbytes = 0; - pm->rbytes = 0; - pm->wwords = 0; - pm->rwords = 0; + h_u16_to_le(pm->wid, VD_VERSION); /* client version */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); rc = vdebug_wait_server(hsock, pm); if (rc != 0) { /* communication problem */ LOG_ERROR("0x%x connecting to server", rc); - } else if (pm->rid < pm->wid) { - LOG_ERROR("server version %d too old for the client %d", pm->rid, pm->wid); + } else if (le_to_h_u16(pm->rid) < le_to_h_u16(pm->wid)) { + LOG_ERROR("server version %d too old for the client %d", le_to_h_u16(pm->rid), le_to_h_u16(pm->wid)); pm->cmd = VD_CMD_CLOSE; /* let server close the connection */ vdebug_wait_server(hsock, pm); rc = VD_ERR_VERSION; } else { pm->cmd = VD_CMD_CONNECT; - pm->type = type; /* BFM type to connect to, here JTAG */ - pm->rwdata = sig_mask | VD_SIG_BUF | (VD_SIG_BUF << 16); - pm->wbytes = strlen(path) + 1; - pm->rbytes = 12; - pm->wid = 0; /* reset wid for transaction ID */ - pm->wwords = 0; - pm->rwords = 0; - memcpy(pm->wd8, path, pm->wbytes + 1); + pm->type = type; /* BFM type to connect to */ + h_u32_to_le(pm->rwdata, sig_mask | VD_SIG_BUF | (VD_SIG_BUF << 16)); + h_u16_to_le(pm->wbytes, strlen(path) + 1); + h_u16_to_le(pm->rbytes, 12); + h_u16_to_le(pm->wid, 0); /* reset wid for transaction ID */ + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); + memcpy(pm->wd8, path, le_to_h_u16(pm->wbytes)); rc = vdebug_wait_server(hsock, pm); - vdc.sig_read = pm->rwdata >> 16; /* signal read mask */ - vdc.sig_write = pm->rwdata; /* signal write mask */ + vdc.sig_read = le_to_h_u32(pm->rwdata) >> 16; /* signal read mask */ + vdc.sig_write = le_to_h_u32(pm->rwdata); /* signal write mask */ vdc.bfm_period = period_ps; - vdc.buf_width = pm->rd32[0] / 8;/* access width in bytes */ - vdc.addr_bits = pm->rd32[2]; /* supported address bits */ + vdc.buf_width = le_to_h_u32(&pm->rd8[0]) / 8;/* access width in bytes */ + vdc.addr_bits = le_to_h_u32(&pm->rd8[2 * 4]); /* supported address bits */ } if (rc) { @@ -456,6 +542,7 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const char *path, return ERROR_FAIL; } + INIT_LIST_HEAD(&vdc.rdataq.lh); LOG_DEBUG("%s type %0x, period %dps, buffer %dx%dB signals r%04xw%04x", path, type, vdc.bfm_period, VD_BUFFER_LEN / vdc.buf_width, vdc.buf_width, vdc.sig_read, vdc.sig_write); @@ -467,17 +554,17 @@ static int vdebug_close(int hsock, struct vd_shm *pm, uint8_t type) { pm->cmd = VD_CMD_DISCONNECT; pm->type = type; /* BFM type, here JTAG */ - pm->wbytes = 0; - pm->rbytes = 0; - pm->wwords = 0; - pm->rwords = 0; + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); vdebug_wait_server(hsock, pm); pm->cmd = VD_CMD_CLOSE; - pm->wid = VD_VERSION; /* client version */ - pm->wbytes = 0; - pm->rbytes = 0; - pm->wwords = 0; - pm->rwords = 0; + h_u16_to_le(pm->wid, VD_VERSION); /* client version */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); vdebug_wait_server(hsock, pm); LOG_DEBUG("type %0x", type); @@ -488,9 +575,9 @@ static int vdebug_wait(int hsock, struct vd_shm *pm, uint32_t cycles) { if (cycles) { pm->cmd = VD_CMD_WAIT; - pm->wbytes = 0; - pm->rbytes = 0; - pm->rwdata = cycles; /* clock sycles to wait */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u32_to_le(pm->rwdata, cycles); /* clock sycles to wait */ int rc = vdebug_wait_server(hsock, pm); if (rc) { LOG_ERROR("0x%x waiting %" PRIx32 " cycles", rc, cycles); @@ -505,9 +592,9 @@ static int vdebug_wait(int hsock, struct vd_shm *pm, uint32_t cycles) static int vdebug_sig_set(int hsock, struct vd_shm *pm, uint32_t write_mask, uint32_t value) { pm->cmd = VD_CMD_SIGSET; - pm->wbytes = 0; - pm->rbytes = 0; - pm->rwdata = (write_mask << 16) | (value & 0xffff); /* mask and value of signals to set */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u32_to_le(pm->rwdata, (write_mask << 16) | (value & 0xffff)); /* mask and value of signals to set */ int rc = vdebug_wait_server(hsock, pm); if (rc) { LOG_ERROR("0x%x setting signals %04" PRIx32, rc, write_mask); @@ -522,9 +609,9 @@ static int vdebug_sig_set(int hsock, struct vd_shm *pm, uint32_t write_mask, uin static int vdebug_jtag_clock(int hsock, struct vd_shm *pm, uint32_t value) { pm->cmd = VD_CMD_JTAGCLOCK; - pm->wbytes = 0; - pm->rbytes = 0; - pm->rwdata = value; /* divider value */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u32_to_le(pm->rwdata, value); /* divider value */ int rc = vdebug_wait_server(hsock, pm); if (rc) { LOG_ERROR("0x%x setting jtag_clock", rc); @@ -546,11 +633,11 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm *pm, uint8_t num_pre, int rc = 0; pm->cmd = VD_CMD_JTAGSHTAP; - vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO) || tdo; + vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO); if (vdc.trans_first) waddr = 0; /* reset buffer offset */ else - waddr = pm->offseth; /* continue from the previous transaction */ + waddr = le_to_h_u32(pm->offseth); /* continue from the previous transaction */ if (num_post) /* actual number of bits to shift */ anum = num + num_pre + num_post - 1; else @@ -559,25 +646,22 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm *pm, uint8_t num_pre, words = (hwords + 1) / 2; /* in 8B TDO words to read */ bytes = (num + 7) / 8; /* data only portion in bytes */ /* buffer overflow check and flush */ - if (4 * waddr + sizeof(struct vd_jtag_hdr) + 8 * hwords + 64 > VD_BUFFER_LEN) { + if (4 * waddr + sizeof(uint64_t) + 8 * hwords + 64 > VD_BUFFER_LEN) { vdc.trans_last = 1; /* force flush within 64B of buffer end */ - } else if (4 * waddr + sizeof(struct vd_jtag_hdr) + 8 * hwords > VD_BUFFER_LEN) { + } else if (4 * waddr + sizeof(uint64_t) + 8 * hwords > VD_BUFFER_LEN) { /* this req does not fit, discard it */ LOG_ERROR("%04x L:%02d O:%05x @%04x too many bits to shift", - pm->wid, anum, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr); + le_to_h_u16(pm->wid), anum, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr); rc = ERROR_FAIL; } if (!rc && anum) { - uint16_t i, j; - struct vd_jtag_hdr *hdr = (struct vd_jtag_hdr *)&pm->wd8[4 * waddr]; /* 8 bytes header */ - hdr->cmd = (tdo ? 3 : 1); /* R and W bits */ - hdr->pre = num_pre; - hdr->post = num_post; - hdr->tlen = anum; - hdr->wlen = hwords; - hdr->rlen = words; - pm->wid++; /* transaction ID */ + uint16_t i, j; /* portability requires to use bit operations for 8B JTAG header */ + uint64_t jhdr = (tdo ? ((uint64_t)(words) << 48) : 0) + ((uint64_t)(hwords) << 32) + + ((tdo ? 3UL : 1UL) << 30) + (num_pre << 27) + (num_post << 24) + anum; + h_u64_to_le(&pm->wd8[4 * waddr], jhdr); + + h_u16_to_le(pm->wid, le_to_h_u16(pm->wid) + 1); /* transaction ID */ waddr += 2; /* waddr past header */ /* TDI/TMS data follows as 32 bit word pairs {TMS,TDI} */ pm->wd8[4 * waddr] = (tdi ? (tdi[0] << num_pre) : 0); @@ -615,19 +699,102 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm *pm, uint8_t num_pre, } if (tdo) { - pm->rwords += words; /* keep track of the words to read */ - vdc.tdo = tdo; + struct vd_rdata *rd; + if (le_to_h_u16(pm->rwords) == 0) { + rd = &vdc.rdataq; + } else { + rd = calloc(1, sizeof(struct vd_rdata)); + if (!rd) /* check allocation for 24B */ + return ERROR_FAIL; + list_add_tail(&rd->lh, &vdc.rdataq.lh); + } + rd->rdata = tdo; + h_u16_to_le(pm->rwords, le_to_h_u16(pm->rwords) + words);/* keep track of the words to read */ } - pm->wwords = waddr / 2 + hwords; /* payload size *2 to include both TDI and TMS data */ - pm->waddr++; + h_u16_to_le(pm->wwords, waddr / 2 + hwords); /* payload size *2 to include both TDI and TMS data */ + h_u16_to_le(pm->waddr, le_to_h_u16(pm->waddr) + 1); } if (!waddr) /* flush issued, but buffer empty */ ; else if (!vdc.trans_last) /* buffered request */ - pm->offseth = waddr + hwords * 2; /* offset for next transaction, must be even */ + h_u16_to_le(pm->offseth, waddr + hwords * 2); /* offset for next transaction, must be even */ else /* execute batch of requests */ - rc = vdebug_run_jtag_queue(hsock, pm, pm->waddr); + rc = vdebug_run_jtag_queue(hsock, pm, le_to_h_u16(pm->waddr)); + vdc.trans_first = vdc.trans_last; /* flush forces trans_first flag */ + + return rc; +} + +static int vdebug_reg_write(int hsock, struct vd_shm *pm, const uint32_t reg, + const uint32_t data, uint8_t aspace, uint8_t f_last) +{ + uint32_t waddr; + int rc = ERROR_OK; + + pm->cmd = VD_CMD_REGWRITE; + vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO); + if (vdc.trans_first) + waddr = 0; /* reset buffer offset */ + else + waddr = le_to_h_u16(pm->offseth); /* continue from the previous transaction */ + + if (4 * waddr + 2 * sizeof(uint64_t) + 4 > VD_BUFFER_LEN) + vdc.trans_last = 1; /* force flush, no room for next request */ + + uint64_t rhdr = ((uint64_t)reg << 32) + (1UL << 30) + (2UL << 27) + (1UL << 16) + aspace; + h_u64_to_le(&pm->wd8[4 * waddr], rhdr); + h_u32_to_le(&pm->wd8[4 * (waddr + 2)], data); + h_u16_to_le(pm->wid, le_to_h_u16(pm->wid) + 1); + h_u16_to_le(pm->wwords, waddr + 3); + h_u16_to_le(pm->waddr, le_to_h_u16(pm->waddr) + 1); + if (!vdc.trans_last) /* buffered request */ + h_u16_to_le(pm->offseth, waddr + 3); + else + rc = vdebug_run_reg_queue(hsock, pm, le_to_h_u16(pm->waddr)); + vdc.trans_first = vdc.trans_last; /* flush forces trans_first flag */ + + return rc; +} + +static int vdebug_reg_read(int hsock, struct vd_shm *pm, const uint32_t reg, + uint32_t *data, uint8_t aspace, uint8_t f_last) +{ + uint32_t waddr; + int rc = ERROR_OK; + + pm->cmd = VD_CMD_REGREAD; + vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO); + if (vdc.trans_first) + waddr = 0; /* reset buffer offset */ + else + waddr = le_to_h_u16(pm->offseth); /* continue from the previous transaction */ + + if (4 * waddr + 2 * sizeof(uint64_t) + 4 > VD_BUFFER_LEN) + vdc.trans_last = 1; /* force flush, no room for next request */ + + uint64_t rhdr = ((uint64_t)reg << 32) + (2UL << 30) + (2UL << 27) + ((data ? 1UL : 0UL) << 16) + aspace; + h_u64_to_le(&pm->wd8[4 * waddr], rhdr); + h_u16_to_le(pm->wid, le_to_h_u16(pm->wid) + 1); + if (data) { + struct vd_rdata *rd; + if (le_to_h_u16(pm->rwords) == 0) { + rd = &vdc.rdataq; + } else { + rd = calloc(1, sizeof(struct vd_rdata)); + if (!rd) /* check allocation for 24B */ + return ERROR_FAIL; + list_add_tail(&rd->lh, &vdc.rdataq.lh); + } + rd->rdata = (uint8_t *)data; + h_u16_to_le(pm->rwords, le_to_h_u16(pm->rwords) + 1); + } + h_u16_to_le(pm->wwords, waddr + 2); + h_u16_to_le(pm->waddr, le_to_h_u16(pm->waddr) + 1); + if (!vdc.trans_last) /* buffered request */ + h_u16_to_le(pm->offseth, waddr + 2); + else + rc = vdebug_run_reg_queue(hsock, pm, le_to_h_u16(pm->waddr)); vdc.trans_first = vdc.trans_last; /* flush forces trans_first flag */ return rc; @@ -641,19 +808,19 @@ static int vdebug_mem_open(int hsock, struct vd_shm *pm, const char *path, uint8 return ERROR_OK; pm->cmd = VD_CMD_MEMOPEN; - pm->wbytes = strlen(path) + 1; /* includes terminating 0 */ - pm->rbytes = 8; - pm->wwords = 0; - pm->rwords = 0; - memcpy(pm->wd8, path, pm->wbytes); + h_u16_to_le(pm->wbytes, strlen(path) + 1); /* includes terminating 0 */ + h_u16_to_le(pm->rbytes, 8); + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); + memcpy(pm->wd8, path, le_to_h_u16(pm->wbytes)); rc = vdebug_wait_server(hsock, pm); if (rc) { LOG_ERROR("0x%x opening memory %s", rc, path); - } else if (ndx != pm->rd16[1]) { - LOG_WARNING("Invalid memory index %" PRIu16 " returned. Direct memory access disabled", pm->rd16[1]); + } else if (ndx != pm->rd8[2]) { + LOG_WARNING("Invalid memory index %" PRIu16 " returned. Direct memory access disabled", pm->rd8[2]); } else { - vdc.mem_width[ndx] = pm->rd16[0] / 8; /* memory width in bytes */ - vdc.mem_depth[ndx] = pm->rd32[1]; /* memory depth in words */ + vdc.mem_width[ndx] = le_to_h_u16(&pm->rd8[0]) / 8; /* memory width in bytes */ + vdc.mem_depth[ndx] = le_to_h_u32(&pm->rd8[4]); /* memory depth in words */ LOG_DEBUG("%" PRIx8 ": %s memory %" PRIu32 "x%" PRIu32 "B, buffer %" PRIu32 "x%" PRIu32 "B", ndx, path, vdc.mem_depth[ndx], vdc.mem_width[ndx], VD_BUFFER_LEN / vdc.mem_width[ndx], vdc.mem_width[ndx]); } @@ -664,15 +831,45 @@ static int vdebug_mem_open(int hsock, struct vd_shm *pm, const char *path, uint8 static void vdebug_mem_close(int hsock, struct vd_shm *pm, uint8_t ndx) { pm->cmd = VD_CMD_MEMCLOSE; - pm->rwdata = ndx; /* which memory */ - pm->wbytes = 0; - pm->rbytes = 0; - pm->wwords = 0; - pm->rwords = 0; + h_u32_to_le(pm->rwdata, ndx); /* which memory */ + h_u16_to_le(pm->wbytes, 0); + h_u16_to_le(pm->rbytes, 0); + h_u16_to_le(pm->wwords, 0); + h_u16_to_le(pm->rwords, 0); vdebug_wait_server(hsock, pm); LOG_DEBUG("%" PRIx8 ": %s", ndx, vdc.mem_path[ndx]); } + +/* function gets invoked through a callback every VD_POLL_INTERVAL ms + * if the idle time, measured by VD_POLL_INTERVAL - targ_time is more than poll_min + * the wait function is called and its time measured and wait cycles adjusted. + * The wait allows hardware to advance, when no data activity from the vdebug occurs + */ +static int vdebug_poll(void *priv) +{ + int64_t ts, te; + + ts = timeval_ms(); + if (ts - vdc.poll_ts - vdc.targ_time >= vdc.poll_min) { + vdebug_wait(vdc.hsocket, pbuf, vdc.poll_cycles); + te = timeval_ms(); + LOG_DEBUG("poll after %" PRId64 "ms, busy %" PRIu32 "ms; wait %" PRIu32 " %" PRId64 "ms", + ts - vdc.poll_ts, vdc.targ_time, vdc.poll_cycles, te - ts); + + if (te - ts + vdc.targ_time < vdc.poll_max / 2) + vdc.poll_cycles *= 2; + else if (te - ts + vdc.targ_time > vdc.poll_max) + vdc.poll_cycles /= 2; + } else { + LOG_DEBUG("poll after %" PRId64 "ms, busy %" PRIu32 "ms", ts - vdc.poll_ts, vdc.targ_time); + } + vdc.poll_ts = ts; + vdc.targ_time = 0; /* reset target time counter */ + + return ERROR_OK; +} + static int vdebug_init(void) { vdc.hsocket = vdebug_socket_open(vdc.server_name, vdc.server_port); @@ -680,7 +877,7 @@ static int vdebug_init(void) if (!pbuf) { close_socket(vdc.hsocket); vdc.hsocket = 0; - LOG_ERROR("cannot allocate %lu bytes", sizeof(struct vd_shm)); + LOG_ERROR("cannot allocate %zu bytes", sizeof(struct vd_shm)); return ERROR_FAIL; } if (vdc.hsocket <= 0) { @@ -692,10 +889,14 @@ static int vdebug_init(void) } vdc.trans_first = 1; vdc.poll_cycles = vdc.poll_max; - uint32_t sig_mask = VD_SIG_RESET | VD_SIG_TRST | VD_SIG_TCKDIV; + vdc.poll_ts = timeval_ms(); + uint32_t sig_mask = VD_SIG_RESET; + if (transport_is_jtag()) + sig_mask |= VD_SIG_TRST | VD_SIG_TCKDIV; + int rc = vdebug_open(vdc.hsocket, pbuf, vdc.bfm_path, vdc.bfm_type, vdc.bfm_period, sig_mask); if (rc != 0) { - LOG_ERROR("cannot connect to %s, rc 0x%x", vdc.bfm_path, rc); + LOG_ERROR("0x%x cannot connect to %s", rc, vdc.bfm_path); close_socket(vdc.hsocket); vdc.hsocket = 0; free(pbuf); @@ -704,9 +905,11 @@ static int vdebug_init(void) for (uint8_t i = 0; i < vdc.mem_ndx; i++) { rc = vdebug_mem_open(vdc.hsocket, pbuf, vdc.mem_path[i], i); if (rc != 0) - LOG_ERROR("cannot connect to %s, rc 0x%x", vdc.mem_path[i], rc); + LOG_ERROR("0x%x cannot connect to %s", rc, vdc.mem_path[i]); } + target_register_timer_callback(vdebug_poll, VD_POLL_INTERVAL, + TARGET_TIMER_TYPE_PERIODIC, &vdc); LOG_INFO("vdebug %d connected to %s through %s:%" PRIu16, VD_VERSION, vdc.bfm_path, vdc.server_name, vdc.server_port); } @@ -716,6 +919,8 @@ static int vdebug_init(void) static int vdebug_quit(void) { + target_unregister_timer_callback(vdebug_poll, &vdc); + for (uint8_t i = 0; i < vdc.mem_ndx; i++) if (vdc.mem_width[i]) vdebug_mem_close(vdc.hsocket, pbuf, i); @@ -754,7 +959,7 @@ static int vdebug_reset(int trst, int srst) static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush) { - LOG_INFO("tms len:%d tms:%x", num, *(const uint32_t *)tms); + LOG_DEBUG_IO("tms len:%d tms:%x", num, *tms); return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num, *tms, 0, NULL, 0, 0, NULL, f_flush); } @@ -762,11 +967,11 @@ static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush) static int vdebug_jtag_path_move(struct pathmove_command *cmd, uint8_t f_flush) { uint8_t tms[DIV_ROUND_UP(cmd->num_states, 8)]; - LOG_INFO("path num states %d", cmd->num_states); + LOG_DEBUG_IO("path num states %u", cmd->num_states); memset(tms, 0, DIV_ROUND_UP(cmd->num_states, 8)); - for (uint8_t i = 0; i < cmd->num_states; i++) { + for (unsigned int i = 0; i < cmd->num_states; i++) { if (tap_state_transition(tap_get_state(), true) == cmd->path[i]) buf_set_u32(tms, i, 1, 1); tap_set_state(cmd->path[i]); @@ -775,14 +980,14 @@ static int vdebug_jtag_path_move(struct pathmove_command *cmd, uint8_t f_flush) return vdebug_jtag_tms_seq(tms, cmd->num_states, f_flush); } -static int vdebug_jtag_tlr(tap_state_t state, uint8_t f_flush) +static int vdebug_jtag_tlr(enum tap_state state, uint8_t f_flush) { int rc = ERROR_OK; - uint8_t cur = tap_get_state(); + enum tap_state cur = tap_get_state(); uint8_t tms_pre = tap_get_tms_path(cur, state); uint8_t num_pre = tap_get_tms_path_len(cur, state); - LOG_INFO("tlr from %" PRIx8 " to %" PRIx8, cur, state); + LOG_DEBUG_IO("tlr from %x to %x", cur, state); if (cur != state) { rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, 0, NULL, 0, 0, NULL, f_flush); tap_set_state(state); @@ -795,24 +1000,24 @@ static int vdebug_jtag_scan(struct scan_command *cmd, uint8_t f_flush) { int rc = ERROR_OK; - uint8_t cur = tap_get_state(); + enum tap_state cur = tap_get_state(); uint8_t state = cmd->ir_scan ? TAP_IRSHIFT : TAP_DRSHIFT; uint8_t tms_pre = tap_get_tms_path(cur, state); uint8_t num_pre = tap_get_tms_path_len(cur, state); uint8_t tms_post = tap_get_tms_path(state, cmd->end_state); uint8_t num_post = tap_get_tms_path_len(state, cmd->end_state); - int num_bits = jtag_scan_size(cmd); - LOG_DEBUG("scan len:%d fields:%d ir/!dr:%d state cur:%x end:%x", + const unsigned int num_bits = jtag_scan_size(cmd); + LOG_DEBUG_IO("scan len:%u fields:%u ir/!dr:%d state cur:%x end:%x", num_bits, cmd->num_fields, cmd->ir_scan, cur, cmd->end_state); - for (int i = 0; i < cmd->num_fields; i++) { + for (unsigned int i = 0; i < cmd->num_fields; i++) { uint8_t cur_num_pre = i == 0 ? num_pre : 0; uint8_t cur_tms_pre = i == 0 ? tms_pre : 0; uint8_t cur_num_post = i == cmd->num_fields - 1 ? num_post : 0; uint8_t cur_tms_post = i == cmd->num_fields - 1 ? tms_post : 0; uint8_t cur_flush = i == cmd->num_fields - 1 ? f_flush : 0; rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, cur_num_pre, cur_tms_pre, - cmd->fields[i].num_bits, cmd->fields[i].out_value, cur_num_post, cur_tms_post, - cmd->fields[i].in_value, cur_flush); + cmd->fields[i].num_bits, cmd->fields[i].out_value, cur_num_post, cur_tms_post, + cmd->fields[i].in_value, cur_flush); if (rc) break; } @@ -823,24 +1028,24 @@ static int vdebug_jtag_scan(struct scan_command *cmd, uint8_t f_flush) return rc; } -static int vdebug_jtag_runtest(int cycles, tap_state_t state, uint8_t f_flush) +static int vdebug_jtag_runtest(unsigned int num_cycles, enum tap_state state, uint8_t f_flush) { - uint8_t cur = tap_get_state(); + enum tap_state cur = tap_get_state(); uint8_t tms_pre = tap_get_tms_path(cur, state); uint8_t num_pre = tap_get_tms_path_len(cur, state); - LOG_DEBUG("idle len:%d state cur:%x end:%x", cycles, cur, state); - int rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, cycles, NULL, 0, 0, NULL, f_flush); + LOG_DEBUG_IO("idle len:%u state cur:%x end:%x", num_cycles, cur, state); + int rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, num_cycles, NULL, 0, 0, NULL, f_flush); if (cur != state) tap_set_state(state); return rc; } -static int vdebug_jtag_stableclocks(int num, uint8_t f_flush) +static int vdebug_jtag_stableclocks(unsigned int num_cycles, uint8_t f_flush) { - LOG_INFO("stab len:%d state cur:%x", num, tap_get_state()); + LOG_DEBUG("stab len:%u state cur:%x", num_cycles, tap_get_state()); - return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, 0, 0, num, NULL, 0, 0, NULL, f_flush); + return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, 0, 0, num_cycles, NULL, 0, 0, NULL, f_flush); } static int vdebug_sleep(int us) @@ -877,11 +1082,11 @@ static int vdebug_jtag_div(int speed, int *khz) return ERROR_OK; } -static int vdebug_jtag_execute_queue(void) +static int vdebug_jtag_execute_queue(struct jtag_command *cmd_queue) { int rc = ERROR_OK; - for (struct jtag_command *cmd = jtag_command_queue; rc == ERROR_OK && cmd; cmd = cmd->next) { + for (struct jtag_command *cmd = cmd_queue; rc == ERROR_OK && cmd; cmd = cmd->next) { switch (cmd->type) { case JTAG_RUNTEST: rc = vdebug_jtag_runtest(cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state, !cmd->next); @@ -913,6 +1118,101 @@ static int vdebug_jtag_execute_queue(void) return rc; } +static int vdebug_dap_bankselect(struct adiv5_ap *ap, unsigned int reg) +{ + int rc = ERROR_OK; + uint64_t sel; + + if (is_adiv6(ap->dap)) { + sel = ap->ap_num | (reg & 0x00000FF0); + if (sel != (ap->dap->select & ~0xfull)) { + sel |= ap->dap->select & DP_SELECT_DPBANK; + if (ap->dap->asize > 32) + sel |= (DP_SELECT1 >> 4) & DP_SELECT_DPBANK; + ap->dap->select = sel; + ap->dap->select_valid = true; + rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0); + if (rc == ERROR_OK) { + ap->dap->select_valid = true; + if (ap->dap->asize > 32) + rc = vdebug_reg_write(vdc.hsocket, pbuf, (DP_SELECT1 & DP_SELECT_DPBANK) >> 2, + (uint32_t)(sel >> 32), VD_ASPACE_DP, 0); + if (rc == ERROR_OK) + ap->dap->select1_valid = true; + } + } + } else { /* ADIv5 */ + sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK); + if (sel != ap->dap->select) { + ap->dap->select = sel; + rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0); + if (rc == ERROR_OK) + ap->dap->select_valid = true; + } + } + return rc; +} + +static int vdebug_dap_connect(struct adiv5_dap *dap) +{ + return dap_dp_init(dap); +} + +static int vdebug_dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq) +{ + return ERROR_OK; +} + +static int vdebug_dap_queue_dp_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data) +{ + if (reg != DP_SELECT && reg != DP_RDBUFF + && (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) { + dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK); + vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0); + dap->select_valid = true; + } + return vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0); +} + +static int vdebug_dap_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data) +{ + if (reg != DP_SELECT && reg != DP_RDBUFF + && (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) { + dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK); + vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0); + dap->select_valid = true; + } + return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0); +} + +static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data) +{ + vdebug_dap_bankselect(ap, reg); + + vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, NULL, VD_ASPACE_AP, 0); + + return vdebug_reg_read(vdc.hsocket, pbuf, DP_RDBUFF >> 2, data, VD_ASPACE_DP, 0); +} + +static int vdebug_dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data) +{ + vdebug_dap_bankselect(ap, reg); + return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_AP, 0); +} + +static int vdebug_dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) +{ + return vdebug_reg_write(vdc.hsocket, pbuf, 0, 0x1, VD_ASPACE_AB, 0); +} + +static int vdebug_dap_run(struct adiv5_dap *dap) +{ + if (le_to_h_u16(pbuf->waddr)) + return vdebug_run_reg_queue(vdc.hsocket, pbuf, le_to_h_u16(pbuf->waddr)); + + return ERROR_OK; +} + COMMAND_HANDLER(vdebug_set_server) { if ((CMD_ARGC != 1) || !strchr(CMD_ARGV[0], ':')) @@ -951,7 +1251,10 @@ COMMAND_HANDLER(vdebug_set_bfm) default: break; } - vdc.bfm_type = VD_BFM_JTAG; + if (transport_is_dapdirect_swd()) + vdc.bfm_type = strstr(vdc.bfm_path, "dap6") ? VD_BFM_DAP6 : VD_BFM_SWDP; + else + vdc.bfm_type = VD_BFM_JTAG; LOG_DEBUG("bfm_path: %s clk_period %ups", vdc.bfm_path, vdc.bfm_period); return ERROR_OK; @@ -1025,23 +1328,23 @@ static const struct command_registration vdebug_command_handlers[] = { { .name = "mem_path", .handler = &vdebug_set_mem, - .mode = COMMAND_ANY, + .mode = COMMAND_CONFIG, .help = "set the design memory for the code load", .usage = "<path> <base_address> <size>", }, { .name = "batching", .handler = &vdebug_set_batching, - .mode = COMMAND_CONFIG, + .mode = COMMAND_ANY, .help = "set the transaction batching no|wr|rd [0|1|2]", .usage = "<level>", }, { .name = "polling", .handler = &vdebug_set_polling, - .mode = COMMAND_CONFIG, - .help = "set the polling pause, executing hardware cycles between min and max", - .usage = "<min cycles> <max cycles>", + .mode = COMMAND_ANY, + .help = "set the min idle time and max wait time in ms", + .usage = "<min_idle> <max_wait>", }, COMMAND_REGISTRATION_DONE }; @@ -1062,9 +1365,23 @@ static struct jtag_interface vdebug_jtag_ops = { .execute_queue = vdebug_jtag_execute_queue, }; +static const struct dap_ops vdebug_dap_ops = { + .connect = vdebug_dap_connect, + .send_sequence = vdebug_dap_send_sequence, + .queue_dp_read = vdebug_dap_queue_dp_read, + .queue_dp_write = vdebug_dap_queue_dp_write, + .queue_ap_read = vdebug_dap_queue_ap_read, + .queue_ap_write = vdebug_dap_queue_ap_write, + .queue_ap_abort = vdebug_dap_queue_ap_abort, + .run = vdebug_dap_run, + .sync = NULL, /* optional */ + .quit = NULL, /* optional */ +}; + struct adapter_driver vdebug_adapter_driver = { .name = "vdebug", - .transports = jtag_only, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_DAPDIRECT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .speed = vdebug_jtag_speed, .khz = vdebug_jtag_khz, .speed_div = vdebug_jtag_div, @@ -1073,4 +1390,5 @@ struct adapter_driver vdebug_adapter_driver = { .quit = vdebug_quit, .reset = vdebug_reset, .jtag_ops = &vdebug_jtag_ops, + .dap_swd_ops = &vdebug_dap_ops, }; diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtogpio.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtogpio.c index a15fe93439..ac5b1a2454 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtogpio.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtogpio.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtojtagraw.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtojtagraw.c index 4d6ab0df14..be2d8c303a 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtojtagraw.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtojtagraw.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtopwr.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtopwr.c index c1b034b452..941680a44a 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtopwr.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtopwr.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtoswd.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtoswd.c index 7d2696c497..42c8023cfc 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtoswd.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtoswd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c index 49a079e51c..070f68c1ed 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c index 659873a9af..48d317436b 100644 --- a/src/jtag/drivers/versaloon/versaloon.c +++ b/src/jtag/drivers/versaloon/versaloon.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 - 2010 by Simon Qian <SimonQian@SimonQian.com> * diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c index 8153d5010b..145f0682ac 100644 --- a/src/jtag/drivers/vsllink.c +++ b/src/jtag/drivers/vsllink.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009-2010 by Simon Qian <SimonQian@SimonQian.com> * @@ -41,12 +41,12 @@ static struct pending_scan_result pending_scan_results_buffer[MAX_PENDING_SCAN_RESULTS]; /* Queue command functions */ -static void vsllink_end_state(tap_state_t state); +static void vsllink_end_state(enum tap_state state); static void vsllink_state_move(void); -static void vsllink_path_move(int num_states, tap_state_t *path); +static void vsllink_path_move(unsigned int num_states, enum tap_state *path); static void vsllink_tms(int num_bits, const uint8_t *bits); -static void vsllink_runtest(int num_cycles); -static void vsllink_stableclocks(int num_cycles, int tms); +static void vsllink_runtest(unsigned int num_cycles); +static void vsllink_stableclocks(unsigned int num_cycles, int tms); static void vsllink_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command); static int vsllink_reset(int trst, int srst); @@ -84,9 +84,9 @@ static bool swd_mode; static struct vsllink *vsllink_handle; -static int vsllink_execute_queue(void) +static int vsllink_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int scan_size; enum scan_type type; uint8_t *buffer; @@ -98,7 +98,7 @@ static int vsllink_execute_queue(void) while (cmd) { switch (cmd->type) { case JTAG_RUNTEST: - LOG_DEBUG_IO("runtest %i cycles, end in %s", + LOG_DEBUG_IO("runtest %u cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state)); @@ -115,7 +115,7 @@ static int vsllink_execute_queue(void) break; case JTAG_PATHMOVE: - LOG_DEBUG_IO("pathmove: %i states, end in %s", + LOG_DEBUG_IO("pathmove: %u states, end in %s", cmd->cmd.pathmove->num_states, tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1])); @@ -161,7 +161,7 @@ static int vsllink_execute_queue(void) break; case JTAG_STABLECLOCKS: - LOG_DEBUG_IO("add %d clocks", + LOG_DEBUG_IO("add %u clocks", cmd->cmd.stableclocks->num_cycles); switch (tap_get_state()) { @@ -346,7 +346,7 @@ static int vsllink_init(void) /************************************************************************** * Queue command implementations */ -static void vsllink_end_state(tap_state_t state) +static void vsllink_end_state(enum tap_state state) { if (tap_is_state_stable(state)) tap_set_end_state(state); @@ -371,9 +371,9 @@ static void vsllink_state_move(void) tap_set_state(tap_get_end_state()); } -static void vsllink_path_move(int num_states, tap_state_t *path) +static void vsllink_path_move(unsigned int num_states, enum tap_state *path) { - for (int i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (path[i] == tap_state_transition(tap_get_state(), false)) vsllink_tap_append_step(0, 0); else if (path[i] == tap_state_transition(tap_get_state(), true)) @@ -397,7 +397,7 @@ static void vsllink_tms(int num_bits, const uint8_t *bits) vsllink_tap_append_step((bits[i / 8] >> (i % 8)) & 1, 0); } -static void vsllink_stableclocks(int num_cycles, int tms) +static void vsllink_stableclocks(unsigned int num_cycles, int tms) { while (num_cycles > 0) { vsllink_tap_append_step(tms, 0); @@ -405,9 +405,9 @@ static void vsllink_stableclocks(int num_cycles, int tms) } } -static void vsllink_runtest(int num_cycles) +static void vsllink_runtest(unsigned int num_cycles) { - tap_state_t saved_end_state = tap_get_end_state(); + enum tap_state saved_end_state = tap_get_end_state(); if (tap_get_state() != TAP_IDLE) { /* enter IDLE state */ @@ -427,7 +427,7 @@ static void vsllink_runtest(int num_cycles) static void vsllink_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size, struct scan_command *command) { - tap_state_t saved_end_state; + enum tap_state saved_end_state; saved_end_state = tap_get_end_state(); @@ -913,8 +913,6 @@ static const struct command_registration vsllink_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static const char * const vsllink_transports[] = {"jtag", "swd", NULL}; - static const struct swd_driver vsllink_swd_driver = { .init = vsllink_swd_init, .switch_seq = vsllink_swd_switch_seq, @@ -930,7 +928,8 @@ static struct jtag_interface vsllink_interface = { struct adapter_driver vsllink_adapter_driver = { .name = "vsllink", - .transports = vsllink_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = vsllink_command_handlers, .init = vsllink_init, diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index d6e663997e..d1bb705908 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Texas Instruments, Inc. * @@ -172,7 +172,7 @@ #define CMD_RUNTEST 3 #define CMD_STABLECLOCKS 4 -/* Array to convert from OpenOCD tap_state_t to XDS JTAG state */ +/* Array to convert from OpenOCD enum tap_state to XDS JTAG state */ static const uint32_t xds_jtag_state[] = { XDS_JTAG_STATE_EXIT2_DR, /* TAP_DREXIT2 = 0x0 */ XDS_JTAG_STATE_EXIT1_DR, /* TAP_DREXIT1 = 0x1 */ @@ -579,9 +579,6 @@ static bool usb_get_response(uint32_t *total_bytes_read, uint32_t timeout) static bool usb_send_command(uint16_t size) { - int written; - bool success = true; - /* Check the packet length */ if (size > USB_PAYLOAD_SIZE) return false; @@ -596,13 +593,7 @@ static bool usb_send_command(uint16_t size) size += 3; /* Send the data via the USB connection */ - success = usb_write(xds110.write_packet, (int)size, &written); - - /* Check if the correct number of bytes was written */ - if (written != (int)size) - success = false; - - return success; + return usb_write(xds110.write_packet, (int)size, NULL); } /*************************************************************************** @@ -1300,7 +1291,7 @@ static int xds110_swd_run_queue(void) /* Transfer results into caller's buffers */ for (result = 0; result < xds110.txn_result_count; result++) - if (xds110.txn_dap_results[result] != 0) + if (xds110.txn_dap_results[result]) *xds110.txn_dap_results[result] = dap_results[result]; xds110.txn_request_size = 0; @@ -1354,11 +1345,13 @@ static void xds110_swd_queue_cmd(uint8_t cmd, uint32_t *value) static void xds110_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { + assert(cmd & SWD_CMD_RNW); xds110_swd_queue_cmd(cmd, value); } static void xds110_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { + assert(!(cmd & SWD_CMD_RNW)); xds110_swd_queue_cmd(cmd, &value); } @@ -1609,7 +1602,7 @@ static void xds110_flush(void) } bits = 0; } - if (xds110.txn_scan_results[result].buffer != 0) + if (xds110.txn_scan_results[result].buffer) bit_copy(xds110.txn_scan_results[result].buffer, 0, data_pntr, bits, xds110.txn_scan_results[result].num_bits); bits += xds110.txn_scan_results[result].num_bits; @@ -1676,7 +1669,6 @@ static void xds110_execute_tlr_reset(struct jtag_command *cmd) static void xds110_execute_pathmove(struct jtag_command *cmd) { - uint32_t i; uint32_t num_states; uint8_t *path; @@ -1685,14 +1677,14 @@ static void xds110_execute_pathmove(struct jtag_command *cmd) if (num_states == 0) return; - path = (uint8_t *)malloc(num_states * sizeof(uint8_t)); - if (path == 0) { + path = malloc(num_states * sizeof(uint8_t)); + if (!path) { LOG_ERROR("XDS110: unable to allocate memory"); return; } /* Convert requested path states into XDS API states */ - for (i = 0; i < num_states; i++) + for (unsigned int i = 0; i < num_states; i++) path[i] = (uint8_t)xds_jtag_state[cmd->cmd.pathmove->path[i]]; if (xds110.firmware >= OCD_FIRMWARE_VERSION) { @@ -1711,7 +1703,6 @@ static void xds110_execute_pathmove(struct jtag_command *cmd) static void xds110_queue_scan(struct jtag_command *cmd) { - int i; uint32_t offset; uint32_t total_fields; uint32_t total_bits; @@ -1722,7 +1713,7 @@ static void xds110_queue_scan(struct jtag_command *cmd) /* Calculate the total number of bits to scan */ total_bits = 0; total_fields = 0; - for (i = 0; i < cmd->cmd.scan->num_fields; i++) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++) { total_fields++; total_bits += (uint32_t)cmd->cmd.scan->fields[i].num_bits; } @@ -1763,8 +1754,8 @@ static void xds110_queue_scan(struct jtag_command *cmd) buffer = &xds110.txn_requests[xds110.txn_request_size]; /* Clear data out buffer to default value of all zeros */ memset((void *)buffer, 0x00, total_bytes); - for (i = 0; i < cmd->cmd.scan->num_fields; i++) { - if (cmd->cmd.scan->fields[i].out_value != 0) { + for (unsigned int i = 0; i < cmd->cmd.scan->num_fields; i++) { + if (cmd->cmd.scan->fields[i].out_value) { /* Copy over data to scan out into request buffer */ bit_copy(buffer, offset, cmd->cmd.scan->fields[i].out_value, 0, cmd->cmd.scan->fields[i].num_bits); @@ -1782,7 +1773,7 @@ static void xds110_queue_scan(struct jtag_command *cmd) static void xds110_queue_runtest(struct jtag_command *cmd) { - uint32_t clocks = (uint32_t)cmd->cmd.stableclocks->num_cycles; + uint32_t clocks = cmd->cmd.stableclocks->num_cycles; uint8_t end_state = (uint8_t)xds_jtag_state[cmd->cmd.runtest->end_state]; /* Check if new request would be too large to fit */ @@ -1801,7 +1792,7 @@ static void xds110_queue_runtest(struct jtag_command *cmd) static void xds110_queue_stableclocks(struct jtag_command *cmd) { - uint32_t clocks = (uint32_t)cmd->cmd.stableclocks->num_cycles; + uint32_t clocks = cmd->cmd.stableclocks->num_cycles; /* Check if new request would be too large to fit */ if ((xds110.txn_request_size + 1 + sizeof(clocks) + 1) > MAX_DATA_BLOCK) @@ -1847,9 +1838,9 @@ static void xds110_execute_command(struct jtag_command *cmd) } } -static int xds110_execute_queue(void) +static int xds110_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; while (cmd) { xds110_execute_command(cmd); @@ -1896,7 +1887,7 @@ static int xds110_speed(int speed) } else { - const double XDS110_TCK_PULSE_INCREMENT = 66.0; + const double xds110_tck_pulse_increment = 66.0; freq_to_use = speed * 1000; /* Hz */ delay_count = 0; @@ -1917,7 +1908,7 @@ static int xds110_speed(int speed) double current_value = max_freq_pulse_duration; while (current_value < freq_to_pulse_width_in_ns) { - current_value += XDS110_TCK_PULSE_INCREMENT; + current_value += xds110_tck_pulse_increment; ++delay_count; } @@ -1928,9 +1919,9 @@ static int xds110_speed(int speed) if (delay_count) { double diff_freq_1 = freq_to_use - (one_giga / (max_freq_pulse_duration + - (XDS110_TCK_PULSE_INCREMENT * delay_count))); + (xds110_tck_pulse_increment * delay_count))); double diff_freq_2 = (one_giga / (max_freq_pulse_duration + - (XDS110_TCK_PULSE_INCREMENT * (delay_count - 1)))) - + (xds110_tck_pulse_increment * (delay_count - 1)))) - freq_to_use; /* One less count value yields a better match */ @@ -2067,15 +2058,14 @@ static const struct swd_driver xds110_swd_driver = { .run = xds110_swd_run_queue, }; -static const char * const xds110_transport[] = { "swd", "jtag", NULL }; - static struct jtag_interface xds110_interface = { .execute_queue = xds110_execute_queue, }; struct adapter_driver xds110_adapter_driver = { .name = "xds110", - .transports = xds110_transport, + .transport_ids = TRANSPORT_SWD | TRANSPORT_JTAG, + .transport_preferred_id = TRANSPORT_SWD, .commands = xds110_command_handlers, .init = xds110_init, diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c index 1fc571d2c7..5208e2b871 100644 --- a/src/jtag/drivers/xlnx-pcie-xvc.c +++ b/src/jtag/drivers/xlnx-pcie-xvc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019 Google, LLC. @@ -43,7 +43,7 @@ struct xlnx_pcie_xvc { int fd; - unsigned offset; + unsigned int offset; char *device; }; @@ -128,7 +128,7 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd) size_t write; int err; - LOG_DEBUG("stableclocks %i cycles", cmd->cmd.runtest->num_cycles); + LOG_DEBUG("stableclocks %u cycles", cmd->cmd.runtest->num_cycles); while (left) { write = MIN(XLNX_XVC_MAX_BITS, left); @@ -167,11 +167,11 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd) { int err = ERROR_OK; - LOG_DEBUG("runtest %i cycles, end in %i", + LOG_DEBUG("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state); - tap_state_t tmp_state = tap_get_end_state(); + enum tap_state tmp_state = tap_get_end_state(); if (tap_get_state() != TAP_IDLE) { tap_set_end_state(TAP_IDLE); @@ -200,20 +200,19 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd) static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd) { - size_t num_states = cmd->cmd.pathmove->num_states; - tap_state_t *path = cmd->cmd.pathmove->path; + unsigned int num_states = cmd->cmd.pathmove->num_states; + enum tap_state *path = cmd->cmd.pathmove->path; int err = ERROR_OK; - size_t i; - LOG_DEBUG("pathmove: %i states, end in %i", + LOG_DEBUG("pathmove: %u states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); - for (i = 0; i < num_states; i++) { + for (unsigned int i = 0; i < num_states; i++) { if (path[i] == tap_state_transition(tap_get_state(), false)) { - err = xlnx_pcie_xvc_transact(1, 1, 0, NULL); - } else if (path[i] == tap_state_transition(tap_get_state(), true)) { err = xlnx_pcie_xvc_transact(1, 0, 0, NULL); + } else if (path[i] == tap_state_transition(tap_get_state(), true)) { + err = xlnx_pcie_xvc_transact(1, 1, 0, NULL); } else { LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.", tap_state_name(tap_get_state()), @@ -233,7 +232,7 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd) static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd) { enum scan_type type = jtag_scan_type(cmd->cmd.scan); - tap_state_t saved_end_state = cmd->cmd.scan->end_state; + enum tap_state saved_end_state = cmd->cmd.scan->end_state; bool ir_scan = cmd->cmd.scan->ir_scan; uint32_t tdi, tms, tdo; uint8_t *buf, *rd_ptr; @@ -362,9 +361,9 @@ static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd) return ERROR_OK; } -static int xlnx_pcie_xvc_execute_queue(void) +static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue) { - struct jtag_command *cmd = jtag_command_queue; + struct jtag_command *cmd = cmd_queue; int ret; while (cmd) { @@ -691,11 +690,10 @@ static const struct swd_driver xlnx_pcie_xvc_swd_ops = { .run = xlnx_pcie_xvc_swd_run_queue, }; -static const char * const xlnx_pcie_xvc_transports[] = { "jtag", "swd", NULL }; - struct adapter_driver xlnx_pcie_xvc_adapter_driver = { .name = "xlnx_pcie_xvc", - .transports = xlnx_pcie_xvc_transports, + .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD, + .transport_preferred_id = TRANSPORT_JTAG, .commands = xlnx_pcie_xvc_command_handlers, .init = &xlnx_pcie_xvc_init, diff --git a/src/jtag/hla/Makefile.am b/src/jtag/hla/Makefile.am index 41117868ad..ea6e11dd63 100644 --- a/src/jtag/hla/Makefile.am +++ b/src/jtag/hla/Makefile.am @@ -4,10 +4,8 @@ noinst_LTLIBRARIES += %D%/libocdhla.la %C%_libocdhla_la_SOURCES = \ %D%/hla_transport.c \ - %D%/hla_tcl.c \ %D%/hla_interface.c \ %D%/hla_layout.c \ %D%/hla_transport.h \ %D%/hla_interface.h \ - %D%/hla_layout.h \ - %D%/hla_tcl.h + %D%/hla_layout.h diff --git a/src/jtag/hla/hla_interface.c b/src/jtag/hla/hla_interface.c index 667f2a7c0b..a9d196ccec 100644 --- a/src/jtag/hla/hla_interface.c +++ b/src/jtag/hla/hla_interface.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * @@ -17,21 +17,19 @@ #include <transport/transport.h> #include <helper/time_support.h> -#include <jtag/hla/hla_tcl.h> #include <jtag/hla/hla_layout.h> #include <jtag/hla/hla_transport.h> #include <jtag/hla/hla_interface.h> #include <target/target.h> -static struct hl_interface_s hl_if = { +static struct hl_interface hl_if = { .param = { .device_desc = NULL, .vid = { 0 }, .pid = { 0 }, .transport = HL_TRANSPORT_UNKNOWN, .connect_under_reset = false, - .initial_interface_speed = -1, .use_stlink_tcp = false, .stlink_tcp_port = 7184, }, @@ -77,7 +75,7 @@ int hl_interface_init_target(struct target *t) if (res != ERROR_OK) return res; - unsigned ii, limit = t->tap->expected_ids_cnt; + unsigned int ii, limit = t->tap->expected_ids_cnt; int found = 0; for (ii = 0; ii < limit; ii++) { @@ -101,7 +99,7 @@ int hl_interface_init_target(struct target *t) } t->tap->priv = &hl_if; - t->tap->hasidcode = 1; + t->tap->has_idcode = true; return ERROR_OK; } @@ -166,11 +164,8 @@ static int hl_interface_speed(int speed) if (!hl_if.layout->api->speed) return ERROR_OK; - if (!hl_if.handle) { - /* pass speed as initial param as interface not open yet */ - hl_if.param.initial_interface_speed = speed; + if (!hl_if.handle) return ERROR_OK; - } hl_if.layout->api->speed(hl_if.handle, speed, false); @@ -265,7 +260,7 @@ COMMAND_HANDLER(hl_interface_handle_vid_pid_command) return ERROR_COMMAND_SYNTAX_ERROR; } - unsigned i; + unsigned int i; for (i = 0; i < CMD_ARGC; i += 2) { COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i], hl_if.param.vid[i / 2]); COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i + 1], hl_if.param.pid[i / 2]); @@ -320,37 +315,37 @@ COMMAND_HANDLER(interface_handle_hla_command) return ERROR_OK; } -static const struct command_registration hl_interface_command_handlers[] = { +static const struct command_registration hl_interface_subcommand_handlers[] = { { - .name = "hla_device_desc", + .name = "device_desc", .handler = &hl_interface_handle_device_desc_command, .mode = COMMAND_CONFIG, .help = "set the device description of the adapter", .usage = "description_string", }, { - .name = "hla_layout", + .name = "layout", .handler = &hl_interface_handle_layout_command, .mode = COMMAND_CONFIG, .help = "set the layout of the adapter", .usage = "layout_name", }, { - .name = "hla_vid_pid", + .name = "vid_pid", .handler = &hl_interface_handle_vid_pid_command, .mode = COMMAND_CONFIG, .help = "the vendor and product ID of the adapter", .usage = "(vid pid)*", }, { - .name = "hla_stlink_backend", + .name = "stlink_backend", .handler = &hl_interface_handle_stlink_backend_command, .mode = COMMAND_CONFIG, .help = "select which ST-Link backend to use", .usage = "usb | tcp [port]", }, - { - .name = "hla_command", + { + .name = "command", .handler = &interface_handle_hla_command, .mode = COMMAND_EXEC, .help = "execute a custom adapter-specific command", @@ -359,9 +354,21 @@ static const struct command_registration hl_interface_command_handlers[] = { COMMAND_REGISTRATION_DONE }; +static const struct command_registration hl_interface_command_handlers[] = { + { + .name = "hla", + .mode = COMMAND_ANY, + .help = "perform hla management", + .chain = hl_interface_subcommand_handlers, + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; + struct adapter_driver hl_adapter_driver = { .name = "hla", - .transports = hl_transports, + .transport_ids = TRANSPORT_HLA_SWD | TRANSPORT_HLA_JTAG, + .transport_preferred_id = TRANSPORT_HLA_SWD, .commands = hl_interface_command_handlers, .init = hl_interface_init, diff --git a/src/jtag/hla/hla_interface.h b/src/jtag/hla/hla_interface.h index fa4965806b..c0ee05498d 100644 --- a/src/jtag/hla/hla_interface.h +++ b/src/jtag/hla/hla_interface.h @@ -15,12 +15,10 @@ struct target; /** */ enum e_hl_transports; -/** */ -extern const char *hl_transports[]; #define HLA_MAX_USB_IDS 16 -struct hl_interface_param_s { +struct hl_interface_param { /** */ const char *device_desc; /** List of recognised VIDs */ @@ -31,17 +29,15 @@ struct hl_interface_param_s { enum hl_transports transport; /** */ bool connect_under_reset; - /** Initial interface clock clock speed */ - int initial_interface_speed; /** */ bool use_stlink_tcp; /** */ uint16_t stlink_tcp_port; }; -struct hl_interface_s { +struct hl_interface { /** */ - struct hl_interface_param_s param; + struct hl_interface_param param; /** */ const struct hl_layout *layout; /** */ diff --git a/src/jtag/hla/hla_layout.c b/src/jtag/hla/hla_layout.c index aa0041b31c..04c963f0e8 100644 --- a/src/jtag/hla/hla_layout.c +++ b/src/jtag/hla/hla_layout.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * @@ -18,11 +18,10 @@ #include <helper/time_support.h> #include <jtag/hla/hla_layout.h> -#include <jtag/hla/hla_tcl.h> #include <jtag/hla/hla_transport.h> #include <jtag/hla/hla_interface.h> -static int hl_layout_open(struct hl_interface_s *adapter) +static int hl_layout_open(struct hl_interface *adapter) { int res; @@ -40,7 +39,7 @@ static int hl_layout_open(struct hl_interface_s *adapter) return ERROR_OK; } -static int hl_layout_close(struct hl_interface_s *adapter) +static int hl_layout_close(struct hl_interface *adapter) { return ERROR_OK; } @@ -79,7 +78,7 @@ const struct hl_layout *hl_layout_get_list(void) return hl_layouts; } -int hl_layout_init(struct hl_interface_s *adapter) +int hl_layout_init(struct hl_interface *adapter) { LOG_DEBUG("hl_layout_init"); diff --git a/src/jtag/hla/hla_layout.h b/src/jtag/hla/hla_layout.h index e13da6531c..71a7563e1f 100644 --- a/src/jtag/hla/hla_layout.h +++ b/src/jtag/hla/hla_layout.h @@ -15,18 +15,18 @@ #include <target/arm_tpiu_swo.h> /** */ -struct hl_interface_s; -struct hl_interface_param_s; +struct hl_interface; +struct hl_interface_param; /** */ -extern struct hl_layout_api_s stlink_usb_layout_api; -extern struct hl_layout_api_s icdi_usb_layout_api; -extern struct hl_layout_api_s nulink_usb_layout_api; +extern struct hl_layout_api stlink_usb_layout_api; +extern struct hl_layout_api icdi_usb_layout_api; +extern struct hl_layout_api nulink_usb_layout_api; /** */ -struct hl_layout_api_s { +struct hl_layout_api { /** */ - int (*open)(struct hl_interface_param_s *param, void **handle); + int (*open)(struct hl_interface_param *param, void **handle); /** */ int (*close)(void *handle); /** */ @@ -121,16 +121,16 @@ struct hl_layout { /** */ char *name; /** */ - int (*open)(struct hl_interface_s *adapter); + int (*open)(struct hl_interface *adapter); /** */ - int (*close)(struct hl_interface_s *adapter); + int (*close)(struct hl_interface *adapter); /** */ - struct hl_layout_api_s *api; + struct hl_layout_api *api; }; /** */ const struct hl_layout *hl_layout_get_list(void); /** */ -int hl_layout_init(struct hl_interface_s *adapter); +int hl_layout_init(struct hl_interface *adapter); #endif /* OPENOCD_JTAG_HLA_HLA_LAYOUT_H */ diff --git a/src/jtag/hla/hla_tcl.c b/src/jtag/hla/hla_tcl.c deleted file mode 100644 index e35f2ac81b..0000000000 --- a/src/jtag/hla/hla_tcl.c +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2011 by Mathias Kuester * - * Mathias Kuester <kesmtp@freenet.de> * - * * - * Copyright (C) 2012 by Spencer Oliver * - * spen@spen-soft.co.uk * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -/* project specific includes */ -#include <jtag/interface.h> -#include <transport/transport.h> -#include <helper/time_support.h> - -static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, - struct jtag_tap *tap) -{ - jim_wide w; - int e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", - n->name); - return e; - } - - uint32_t *p = realloc(tap->expected_ids, - (tap->expected_ids_cnt + 1) * sizeof(uint32_t)); - if (!p) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; - } - - tap->expected_ids = p; - tap->expected_ids[tap->expected_ids_cnt++] = w; - - return JIM_OK; -} - -#define NTAP_OPT_IRLEN 0 -#define NTAP_OPT_IRMASK 1 -#define NTAP_OPT_IRCAPTURE 2 -#define NTAP_OPT_ENABLED 3 -#define NTAP_OPT_DISABLED 4 -#define NTAP_OPT_EXPECTED_ID 5 -#define NTAP_OPT_VERSION 6 -#define NTAP_OPT_BYPASS 7 - -static int jim_hl_newtap_cmd(struct jim_getopt_info *goi) -{ - struct jtag_tap *tap; - int x; - int e; - struct jim_nvp *n; - char *cp; - const struct jim_nvp opts[] = { - { .name = "-irlen", .value = NTAP_OPT_IRLEN }, - { .name = "-irmask", .value = NTAP_OPT_IRMASK }, - { .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE }, - { .name = "-enable", .value = NTAP_OPT_ENABLED }, - { .name = "-disable", .value = NTAP_OPT_DISABLED }, - { .name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID }, - { .name = "-ignore-version", .value = NTAP_OPT_VERSION }, - { .name = "-ignore-bypass", .value = NTAP_OPT_BYPASS }, - { .name = NULL, .value = -1}, - }; - - tap = calloc(1, sizeof(struct jtag_tap)); - if (!tap) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; - } - - /* - * we expect CHIP + TAP + OPTIONS - * */ - if (goi->argc < 3) { - Jim_SetResultFormatted(goi->interp, - "Missing CHIP TAP OPTIONS ...."); - free(tap); - return JIM_ERR; - } - - const char *tmp; - jim_getopt_string(goi, &tmp, NULL); - tap->chip = strdup(tmp); - - jim_getopt_string(goi, &tmp, NULL); - tap->tapname = strdup(tmp); - - /* name + dot + name + null */ - x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1; - cp = malloc(x); - sprintf(cp, "%s.%s", tap->chip, tap->tapname); - tap->dotted_name = cp; - - LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params", - tap->chip, tap->tapname, tap->dotted_name, goi->argc); - - while (goi->argc) { - e = jim_getopt_nvp(goi, opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, opts, 0); - free(cp); - free(tap); - return e; - } - LOG_DEBUG("Processing option: %s", n->name); - switch (n->value) { - case NTAP_OPT_EXPECTED_ID: - e = jim_newtap_expected_id(n, goi, tap); - if (e != JIM_OK) { - free(cp); - free(tap); - return e; - } - break; - case NTAP_OPT_IRLEN: - case NTAP_OPT_IRMASK: - case NTAP_OPT_IRCAPTURE: - /* dummy read to ignore the next argument */ - jim_getopt_wide(goi, NULL); - break; - } /* switch (n->value) */ - } /* while (goi->argc) */ - - /* default is enabled-after-reset */ - tap->enabled = !tap->disabled_after_reset; - - jtag_tap_init(tap); - return JIM_OK; -} - -int jim_hl_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - return jim_hl_newtap_cmd(&goi); -} diff --git a/src/jtag/hla/hla_tcl.h b/src/jtag/hla/hla_tcl.h deleted file mode 100644 index b028e4b502..0000000000 --- a/src/jtag/hla/hla_tcl.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2011 by Mathias Kuester * - * Mathias Kuester <kesmtp@freenet.de> * - * * - * Copyright (C) 2012 by Spencer Oliver * - * spen@spen-soft.co.uk * - ***************************************************************************/ - -#ifndef OPENOCD_JTAG_HLA_HLA_TCL_H -#define OPENOCD_JTAG_HLA_HLA_TCL_H - -/** */ -int jim_hl_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv); - -#endif /* OPENOCD_JTAG_HLA_HLA_TCL_H */ diff --git a/src/jtag/hla/hla_transport.c b/src/jtag/hla/hla_transport.c index 06db35a1f9..d8ece0776b 100644 --- a/src/jtag/hla/hla_transport.c +++ b/src/jtag/hla/hla_transport.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * @@ -18,7 +18,6 @@ #include <transport/transport.h> #include <helper/time_support.h> #include <target/target.h> -#include <jtag/hla/hla_tcl.h> #include <jtag/hla/hla_transport.h> #include <jtag/hla/hla_interface.h> @@ -38,8 +37,16 @@ static const struct command_registration hl_swd_transport_subcommand_handlers[] { .name = "newdap", .mode = COMMAND_CONFIG, - .jim_handler = jim_hl_newtap, + .handler = handle_jtag_newtap, .help = "declare a new SWD DAP", + .usage = "basename dap_type ['-irlen' count] " + "['-enable'|'-disable'] " + "['-expected_id' number] " + "['-ignore-version'] " + "['-ignore-bypass'] " + "['-ircapture' number] " + "['-ir-bypass' number] " + "['-mask' number]", }, COMMAND_REGISTRATION_DONE }; @@ -59,11 +66,17 @@ static const struct command_registration hl_transport_jtag_subcommand_handlers[] { .name = "newtap", .mode = COMMAND_CONFIG, - .jim_handler = jim_hl_newtap, + .handler = handle_jtag_newtap, .help = "Create a new TAP instance named basename.tap_type, " "and appends it to the scan chain.", .usage = "basename tap_type '-irlen' count " - "['-expected_id' number]", + "['-enable'|'-disable'] " + "['-expected_id' number] " + "['-ignore-version'] " + "['-ignore-bypass'] " + "['-ircapture' number] " + "['-ir-bypass' number] " + "['-mask' number]", }, { .name = "init", @@ -86,12 +99,18 @@ static const struct command_registration hl_transport_jtag_subcommand_handlers[] { .name = "tapisenabled", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, + .help = "Returns a Tcl boolean (0/1) indicating whether " + "the TAP is enabled (1) or not (0).", + .usage = "tap_name", }, { .name = "tapenable", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, + .help = "Try to enable the specified TAP using the " + "'tap-enable' TAP event.", + .usage = "tap_name", }, { .name = "tapdisable", @@ -108,7 +127,8 @@ static const struct command_registration hl_transport_jtag_subcommand_handlers[] { .name = "cget", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_configure, + .handler = handle_jtag_configure, + .usage = "", }, { .name = "names", @@ -157,15 +177,20 @@ static int hl_transport_init(struct command_context *cmd_ctx) return ERROR_FAIL; } - LOG_DEBUG("current transport %s", transport->name); + LOG_DEBUG("current transport %s", get_current_transport_name()); /* get selected transport as enum */ - tr = HL_TRANSPORT_UNKNOWN; - - if (strcmp(transport->name, "hla_swd") == 0) + switch (transport->id) { + case TRANSPORT_HLA_SWD: tr = HL_TRANSPORT_SWD; - else if (strcmp(transport->name, "hla_jtag") == 0) + break; + case TRANSPORT_HLA_JTAG: tr = HL_TRANSPORT_JTAG; + break; + default: + tr = HL_TRANSPORT_UNKNOWN; + break; + } int retval = hl_interface_open(tr); @@ -193,21 +218,19 @@ static int hl_swd_transport_select(struct command_context *cmd_ctx) } static struct transport hl_swd_transport = { - .name = "hla_swd", + .id = TRANSPORT_HLA_SWD, .select = hl_swd_transport_select, .init = hl_transport_init, .override_target = hl_interface_override_target, }; static struct transport hl_jtag_transport = { - .name = "hla_jtag", + .id = TRANSPORT_HLA_JTAG, .select = hl_jtag_transport_select, .init = hl_transport_init, .override_target = hl_interface_override_target, }; -const char *hl_transports[] = { "hla_swd", "hla_jtag", NULL }; - static void hl_constructor(void) __attribute__ ((constructor)); static void hl_constructor(void) { diff --git a/src/jtag/interface.c b/src/jtag/interface.c index c0e433ec63..92c88ca934 100644 --- a/src/jtag/interface.c +++ b/src/jtag/interface.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -26,15 +26,15 @@ * @see tap_set_state() and tap_get_state() accessors. * Actual name is not important since accessors hide it. */ -static tap_state_t state_follower = TAP_RESET; +static enum tap_state state_follower = TAP_RESET; -void tap_set_state_impl(tap_state_t new_state) +void tap_set_state_impl(enum tap_state new_state) { /* this is the state we think the TAPs are in now, was cur_state */ state_follower = new_state; } -tap_state_t tap_get_state(void) +enum tap_state tap_get_state(void) { return state_follower; } @@ -43,9 +43,9 @@ tap_state_t tap_get_state(void) * @see tap_set_end_state() and tap_get_end_state() accessors. * Actual name is not important because accessors hide it. */ -static tap_state_t end_state_follower = TAP_RESET; +static enum tap_state end_state_follower = TAP_RESET; -void tap_set_end_state(tap_state_t new_end_state) +void tap_set_end_state(enum tap_state new_end_state) { /* this is the state we think the TAPs will be in at completion of the * current TAP operation, was end_state @@ -53,12 +53,12 @@ void tap_set_end_state(tap_state_t new_end_state) end_state_follower = new_end_state; } -tap_state_t tap_get_end_state(void) +enum tap_state tap_get_end_state(void) { return end_state_follower; } -int tap_move_ndx(tap_state_t astate) +int tap_move_ndx(enum tap_state astate) { /* given a stable state, return the index into the tms_seqs[] * array within tap_get_tms_path() @@ -187,17 +187,17 @@ typedef const struct tms_sequences tms_table[6][6]; static tms_table *tms_seqs = &short_tms_seqs; -int tap_get_tms_path(tap_state_t from, tap_state_t to) +int tap_get_tms_path(enum tap_state from, enum tap_state to) { return (*tms_seqs)[tap_move_ndx(from)][tap_move_ndx(to)].bits; } -int tap_get_tms_path_len(tap_state_t from, tap_state_t to) +int tap_get_tms_path_len(enum tap_state from, enum tap_state to) { return (*tms_seqs)[tap_move_ndx(from)][tap_move_ndx(to)].bit_count; } -bool tap_is_state_stable(tap_state_t astate) +bool tap_is_state_stable(enum tap_state astate) { bool is_stable; @@ -220,9 +220,9 @@ bool tap_is_state_stable(tap_state_t astate) return is_stable; } -tap_state_t tap_state_transition(tap_state_t cur_state, bool tms) +enum tap_state tap_state_transition(enum tap_state cur_state, bool tms) { - tap_state_t new_state; + enum tap_state new_state; /* A switch is used because it is symbol dependent and not value dependent * like an array. Also it can check for out of range conditions. @@ -341,9 +341,9 @@ static const struct name_mapping { { TAP_IDLE, "IDLE", }, }; -const char *tap_state_name(tap_state_t state) +const char *tap_state_name(enum tap_state state) { - unsigned i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(tap_name_mapping); i++) { if (tap_name_mapping[i].symbol == state) @@ -352,9 +352,9 @@ const char *tap_state_name(tap_state_t state) return "???"; } -tap_state_t tap_state_by_name(const char *name) +enum tap_state tap_state_by_name(const char *name) { - unsigned i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(tap_name_mapping); i++) { /* be nice to the human */ @@ -371,20 +371,20 @@ tap_state_t tap_state_by_name(const char *name) LOG_DEBUG_IO("TAP/SM: %9s -> %5s\tTMS: %s\tTDI: %s", \ tap_state_name(a), tap_state_name(b), astr, bstr) -tap_state_t jtag_debug_state_machine_(const void *tms_buf, const void *tdi_buf, - unsigned tap_bits, tap_state_t next_state) +enum tap_state jtag_debug_state_machine_(const void *tms_buf, const void *tdi_buf, + unsigned int tap_bits, enum tap_state next_state) { const uint8_t *tms_buffer; const uint8_t *tdi_buffer; - unsigned tap_bytes; - unsigned cur_byte; - unsigned cur_bit; + unsigned int tap_bytes; + unsigned int cur_byte; + unsigned int cur_bit; - unsigned tap_out_bits; + unsigned int tap_out_bits; char tms_str[33]; char tdi_str[33]; - tap_state_t last_state; + enum tap_state last_state; /* set startstate (and possibly last, if tap_bits == 0) */ last_state = next_state; @@ -400,7 +400,7 @@ tap_state_t jtag_debug_state_machine_(const void *tms_buf, const void *tdi_buf, for (cur_byte = 0; cur_byte < tap_bytes; cur_byte++) { for (cur_bit = 0; cur_bit < 8; cur_bit++) { /* make sure we do not run off the end of the buffers */ - unsigned tap_bit = cur_byte * 8 + cur_bit; + unsigned int tap_bit = cur_byte * 8 + cur_bit; if (tap_bit == tap_bits) break; diff --git a/src/jtag/interface.h b/src/jtag/interface.h index a8d9ee47e9..8349973613 100644 --- a/src/jtag/interface.h +++ b/src/jtag/interface.h @@ -17,6 +17,7 @@ #include <jtag/jtag.h> #include <jtag/swim.h> #include <target/arm_tpiu_swo.h> +#include <transport/transport.h> /* @file * The "Cable Helper API" is what the cable drivers can use to help @@ -28,7 +29,7 @@ /** implementation of wrapper function tap_set_state() */ -void tap_set_state_impl(tap_state_t new_state); +void tap_set_state_impl(enum tap_state new_state); /** * This function sets the state of a "state follower" which tracks the @@ -55,9 +56,9 @@ void tap_set_state_impl(tap_state_t new_state); /** * This function gets the state of the "state follower" which tracks the * state of the TAPs connected to the cable. @see tap_set_state @return - * tap_state_t The state the TAPs are in now. + * enum tap_state The state the TAPs are in now. */ -tap_state_t tap_get_state(void); +enum tap_state tap_get_state(void); /** * This function sets the state of an "end state follower" which tracks @@ -70,13 +71,13 @@ tap_state_t tap_get_state(void); * @param new_end_state The state the TAPs should enter at completion of * a pending TAP operation. */ -void tap_set_end_state(tap_state_t new_end_state); +void tap_set_end_state(enum tap_state new_end_state); /** * For more information, @see tap_set_end_state - * @return tap_state_t - The state the TAPs should be in at completion of the current TAP operation. + * @return enum tap_state - The state the TAPs should be in at completion of the current TAP operation. */ -tap_state_t tap_get_end_state(void); +enum tap_state tap_get_end_state(void); /** * This function provides a "bit sequence" indicating what has to be @@ -91,7 +92,7 @@ tap_state_t tap_get_end_state(void); * @return int The required TMS bit sequence, with the first bit in the * sequence at bit 0. */ -int tap_get_tms_path(tap_state_t from, tap_state_t to); +int tap_get_tms_path(enum tap_state from, enum tap_state to); /** * Function int tap_get_tms_path_len @@ -109,7 +110,7 @@ int tap_get_tms_path(tap_state_t from, tap_state_t to); * @param to is the resultant or final state * @return int - the total number of bits in a transition. */ -int tap_get_tms_path_len(tap_state_t from, tap_state_t to); +int tap_get_tms_path_len(enum tap_state from, enum tap_state to); /** @@ -125,28 +126,30 @@ int tap_get_tms_path_len(tap_state_t from, tap_state_t to); * and terminate. * @return int - the array (or sequence) index as described above */ -int tap_move_ndx(tap_state_t astate); +int tap_move_ndx(enum tap_state astate); /** * Function tap_is_state_stable * returns true if the \a astate is stable. */ -bool tap_is_state_stable(tap_state_t astate); +bool tap_is_state_stable(enum tap_state astate); /** * Function tap_state_transition * takes a current TAP state and returns the next state according to the tms value. * @param current_state is the state of a TAP currently. * @param tms is either zero or non-zero, just like a real TMS line in a jtag interface. - * @return tap_state_t - the next state a TAP would enter. + * @return enum tap_state - the next state a TAP would enter. */ -tap_state_t tap_state_transition(tap_state_t current_state, bool tms); +enum tap_state tap_state_transition(enum tap_state current_state, bool tms); /** Allow switching between old and new TMS tables. @see tap_get_tms_path */ void tap_use_new_tms_table(bool use_new); /** @returns True if new TMS table is active; false otherwise. */ bool tap_uses_new_tms_table(void); +enum tap_state jtag_debug_state_machine_(const void *tms_buf, const void *tdi_buf, + unsigned int tap_len, enum tap_state start_tap_state); /** * @brief Prints verbose TAP state transitions for the given TMS/TDI buffers. @@ -156,13 +159,9 @@ bool tap_uses_new_tms_table(void); * @param start_tap_state must specify the current TAP state. * @returns the final TAP state; pass as @a start_tap_state in following call. */ -static inline tap_state_t jtag_debug_state_machine(const void *tms_buf, - const void *tdi_buf, unsigned tap_len, tap_state_t start_tap_state) +static inline enum tap_state jtag_debug_state_machine(const void *tms_buf, + const void *tdi_buf, unsigned int tap_len, enum tap_state start_tap_state) { - /* Private declaration */ - tap_state_t jtag_debug_state_machine_(const void *tms_buf, const void *tdi_buf, - unsigned tap_len, tap_state_t start_tap_state); - if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) return jtag_debug_state_machine_(tms_buf, tdi_buf, tap_len, start_tap_state); else @@ -185,14 +184,16 @@ struct jtag_interface { /** * Bit vector listing capabilities exposed by this driver. */ - unsigned supported; + unsigned int supported; #define DEBUG_CAP_TMS_SEQ (1 << 0) /** - * Execute queued commands. + * Execute commands in the supplied queue + * @param cmd_queue - a linked list of commands to execute * @returns ERROR_OK on success, or an error code on failure. */ - int (*execute_queue)(void); + + int (*execute_queue)(struct jtag_command *cmd_queue); }; /** @@ -208,8 +209,16 @@ struct adapter_driver { /** The name of the interface driver. */ const char * const name; - /** transports supported in C code (NULL terminated vector) */ - const char * const *transports; + /** + * Bitmask of transport IDs supported in C code. + */ + unsigned int transport_ids; + + /** + * ID of transport that gets auto-selected when not specified by the user. + * The auto-selection of transport is DEPRECATED. + */ + unsigned int transport_preferred_id; /** * The interface driver may register additional commands to expose @@ -354,8 +363,6 @@ struct adapter_driver { const struct swim_driver *swim_ops; }; -extern const char * const jtag_only[]; - int adapter_resets(int assert_trst, int assert_srst); int adapter_assert_reset(void); int adapter_deassert_reset(void); @@ -364,4 +371,46 @@ int adapter_config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol, unsigned int traceclkin_freq, uint16_t *prescaler); int adapter_poll_trace(uint8_t *buf, size_t *size); +// Keep in alphabetic order this list of drivers +extern struct adapter_driver am335xgpio_adapter_driver; +extern struct adapter_driver amt_jtagaccel_adapter_driver; +extern struct adapter_driver angie_adapter_driver; +extern struct adapter_driver armjtagew_adapter_driver; +extern struct adapter_driver at91rm9200_adapter_driver; +extern struct adapter_driver bcm2835gpio_adapter_driver; +extern struct adapter_driver buspirate_adapter_driver; +extern struct adapter_driver cmsis_dap_adapter_driver; +extern struct adapter_driver dmem_dap_adapter_driver; +extern struct adapter_driver dummy_adapter_driver; +extern struct adapter_driver ep93xx_adapter_driver; +extern struct adapter_driver esp_usb_adapter_driver; +extern struct adapter_driver ft232r_adapter_driver; +extern struct adapter_driver ftdi_adapter_driver; +extern struct adapter_driver gw16012_adapter_driver; +extern struct adapter_driver hl_adapter_driver; +extern struct adapter_driver imx_gpio_adapter_driver; +extern struct adapter_driver jlink_adapter_driver; +extern struct adapter_driver jtag_dpi_adapter_driver; +extern struct adapter_driver jtag_vpi_adapter_driver; +extern struct adapter_driver kitprog_adapter_driver; +extern struct adapter_driver linuxgpiod_adapter_driver; +extern struct adapter_driver linuxspidev_adapter_driver; +extern struct adapter_driver opendous_adapter_driver; +extern struct adapter_driver openjtag_adapter_driver; +extern struct adapter_driver osbdm_adapter_driver; +extern struct adapter_driver parport_adapter_driver; +extern struct adapter_driver presto_adapter_driver; +extern struct adapter_driver remote_bitbang_adapter_driver; +extern struct adapter_driver rlink_adapter_driver; +extern struct adapter_driver rshim_dap_adapter_driver; +extern struct adapter_driver stlink_dap_adapter_driver; +extern struct adapter_driver sysfsgpio_adapter_driver; +extern struct adapter_driver ulink_adapter_driver; +extern struct adapter_driver usb_blaster_adapter_driver; +extern struct adapter_driver usbprog_adapter_driver; +extern struct adapter_driver vdebug_adapter_driver; +extern struct adapter_driver vsllink_adapter_driver; +extern struct adapter_driver xds110_adapter_driver; +extern struct adapter_driver xlnx_pcie_xvc_adapter_driver; + #endif /* OPENOCD_JTAG_INTERFACE_H */ diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c index e1d2a673f4..834247245b 100644 --- a/src/jtag/interfaces.c +++ b/src/jtag/interfaces.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -24,246 +24,140 @@ #include "interfaces.h" /** @file - * This file includes declarations for all built-in jtag interfaces, - * which are then listed in the adapter_drivers array. + * This file collects all the built-in JTAG interfaces in the adapter_drivers + * array. * * Dynamic loading can be implemented be searching for shared libraries * that contain an adapter_driver structure that can added to this list. */ -#if BUILD_PARPORT == 1 -extern struct adapter_driver parport_adapter_driver; -#endif -#if BUILD_DUMMY == 1 -extern struct adapter_driver dummy_adapter_driver; -#endif -#if BUILD_FTDI == 1 -extern struct adapter_driver ftdi_adapter_driver; -#endif -#if BUILD_USB_BLASTER == 1 || BUILD_USB_BLASTER_2 == 1 -extern struct adapter_driver usb_blaster_adapter_driver; -#endif -#if BUILD_ESP_USB_JTAG == 1 -extern struct adapter_driver esp_usb_adapter_driver; -#endif -#if BUILD_JTAG_VPI == 1 -extern struct adapter_driver jtag_vpi_adapter_driver; -#endif -#if BUILD_VDEBUG == 1 -extern struct adapter_driver vdebug_adapter_driver; -#endif -#if BUILD_JTAG_DPI == 1 -extern struct adapter_driver jtag_dpi_adapter_driver; -#endif -#if BUILD_FT232R == 1 -extern struct adapter_driver ft232r_adapter_driver; +/** + * The list of built-in JTAG interfaces, containing entries for those + * drivers that were enabled by the @c configure script. + */ +struct adapter_driver *adapter_drivers[] = { + // Keep in alphabetic order this list of drivers + +#if BUILD_AM335XGPIO == 1 + &am335xgpio_adapter_driver, #endif #if BUILD_AMTJTAGACCEL == 1 -extern struct adapter_driver amt_jtagaccel_adapter_driver; -#endif -#if BUILD_EP93XX == 1 -extern struct adapter_driver ep93xx_adapter_driver; -#endif -#if BUILD_AT91RM9200 == 1 -extern struct adapter_driver at91rm9200_adapter_driver; -#endif -#if BUILD_GW16012 == 1 -extern struct adapter_driver gw16012_adapter_driver; -#endif -#if BUILD_PRESTO -extern struct adapter_driver presto_adapter_driver; -#endif -#if BUILD_USBPROG == 1 -extern struct adapter_driver usbprog_adapter_driver; -#endif -#if BUILD_OPENJTAG == 1 -extern struct adapter_driver openjtag_adapter_driver; -#endif -#if BUILD_JLINK == 1 -extern struct adapter_driver jlink_adapter_driver; -#endif -#if BUILD_VSLLINK == 1 -extern struct adapter_driver vsllink_adapter_driver; -#endif -#if BUILD_RLINK == 1 -extern struct adapter_driver rlink_adapter_driver; + &amt_jtagaccel_adapter_driver, #endif -#if BUILD_ULINK == 1 -extern struct adapter_driver ulink_adapter_driver; +#if BUILD_ANGIE == 1 + &angie_adapter_driver, #endif #if BUILD_ARMJTAGEW == 1 -extern struct adapter_driver armjtagew_adapter_driver; -#endif -#if BUILD_BUSPIRATE == 1 -extern struct adapter_driver buspirate_adapter_driver; -#endif -#if BUILD_REMOTE_BITBANG == 1 -extern struct adapter_driver remote_bitbang_adapter_driver; -#endif -#if BUILD_HLADAPTER == 1 -extern struct adapter_driver hl_adapter_driver; -#endif -#if BUILD_OSBDM == 1 -extern struct adapter_driver osbdm_adapter_driver; -#endif -#if BUILD_OPENDOUS == 1 -extern struct adapter_driver opendous_adapter_driver; -#endif -#if BUILD_SYSFSGPIO == 1 -extern struct adapter_driver sysfsgpio_adapter_driver; -#endif -#if BUILD_LINUXGPIOD == 1 -extern struct adapter_driver linuxgpiod_adapter_driver; -#endif -#if BUILD_XLNX_PCIE_XVC == 1 -extern struct adapter_driver xlnx_pcie_xvc_adapter_driver; + &armjtagew_adapter_driver, #endif -#if BUILD_AICE == 1 -extern struct adapter_driver aice_adapter_driver; +#if BUILD_AT91RM9200 == 1 + &at91rm9200_adapter_driver, #endif #if BUILD_BCM2835GPIO == 1 -extern struct adapter_driver bcm2835gpio_adapter_driver; -#endif -#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1 -extern struct adapter_driver cmsis_dap_adapter_driver; -#endif -#if BUILD_KITPROG == 1 -extern struct adapter_driver kitprog_adapter_driver; + &bcm2835gpio_adapter_driver, #endif -#if BUILD_IMX_GPIO == 1 -extern struct adapter_driver imx_gpio_adapter_driver; +#if BUILD_BUS_PIRATE == 1 + &buspirate_adapter_driver, #endif -#if BUILD_XDS110 == 1 -extern struct adapter_driver xds110_adapter_driver; +#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1 + &cmsis_dap_adapter_driver, #endif -#if BUILD_HLADAPTER_STLINK == 1 -extern struct adapter_driver stlink_dap_adapter_driver; +#if BUILD_DMEM == 1 + &dmem_dap_adapter_driver, #endif -#if BUILD_RSHIM == 1 -extern struct adapter_driver rshim_dap_adapter_driver; +#if BUILD_DUMMY == 1 + &dummy_adapter_driver, #endif -#if BUILD_AM335XGPIO == 1 -extern struct adapter_driver am335xgpio_adapter_driver; +#if BUILD_EP93XX == 1 + &ep93xx_adapter_driver, #endif - -/** - * The list of built-in JTAG interfaces, containing entries for those - * drivers that were enabled by the @c configure script. - */ -struct adapter_driver *adapter_drivers[] = { -#if BUILD_PARPORT == 1 - &parport_adapter_driver, +#if BUILD_ESP_USB_JTAG == 1 + &esp_usb_adapter_driver, #endif -#if BUILD_DUMMY == 1 - &dummy_adapter_driver, +#if BUILD_FT232R == 1 + &ft232r_adapter_driver, #endif #if BUILD_FTDI == 1 &ftdi_adapter_driver, #endif -#if BUILD_USB_BLASTER || BUILD_USB_BLASTER_2 == 1 - &usb_blaster_adapter_driver, +#if BUILD_GW16012 == 1 + &gw16012_adapter_driver, #endif -#if BUILD_ESP_USB_JTAG == 1 - &esp_usb_adapter_driver, +#if BUILD_HLADAPTER == 1 + &hl_adapter_driver, #endif -#if BUILD_JTAG_VPI == 1 - &jtag_vpi_adapter_driver, +#if BUILD_IMX_GPIO == 1 + &imx_gpio_adapter_driver, #endif -#if BUILD_VDEBUG == 1 - &vdebug_adapter_driver, +#if BUILD_JLINK == 1 + &jlink_adapter_driver, #endif #if BUILD_JTAG_DPI == 1 &jtag_dpi_adapter_driver, #endif -#if BUILD_FT232R == 1 - &ft232r_adapter_driver, -#endif -#if BUILD_AMTJTAGACCEL == 1 - &amt_jtagaccel_adapter_driver, -#endif -#if BUILD_EP93XX == 1 - &ep93xx_adapter_driver, +#if BUILD_JTAG_VPI == 1 + &jtag_vpi_adapter_driver, #endif -#if BUILD_AT91RM9200 == 1 - &at91rm9200_adapter_driver, +#if BUILD_KITPROG == 1 + &kitprog_adapter_driver, #endif -#if BUILD_GW16012 == 1 - &gw16012_adapter_driver, +#if BUILD_LINUXGPIOD == 1 + &linuxgpiod_adapter_driver, #endif -#if BUILD_PRESTO - &presto_adapter_driver, +#if BUILD_LINUXSPIDEV == 1 + &linuxspidev_adapter_driver, #endif -#if BUILD_USBPROG == 1 - &usbprog_adapter_driver, +#if BUILD_OPENDOUS == 1 + &opendous_adapter_driver, #endif #if BUILD_OPENJTAG == 1 &openjtag_adapter_driver, #endif -#if BUILD_JLINK == 1 - &jlink_adapter_driver, -#endif -#if BUILD_VSLLINK == 1 - &vsllink_adapter_driver, -#endif -#if BUILD_RLINK == 1 - &rlink_adapter_driver, -#endif -#if BUILD_ULINK == 1 - &ulink_adapter_driver, +#if BUILD_OSBDM == 1 + &osbdm_adapter_driver, #endif -#if BUILD_ARMJTAGEW == 1 - &armjtagew_adapter_driver, +#if BUILD_PARPORT == 1 + &parport_adapter_driver, #endif -#if BUILD_BUSPIRATE == 1 - &buspirate_adapter_driver, +#if BUILD_PRESTO == 1 + &presto_adapter_driver, #endif #if BUILD_REMOTE_BITBANG == 1 &remote_bitbang_adapter_driver, #endif -#if BUILD_HLADAPTER == 1 - &hl_adapter_driver, +#if BUILD_RLINK == 1 + &rlink_adapter_driver, #endif -#if BUILD_OSBDM == 1 - &osbdm_adapter_driver, +#if BUILD_RSHIM == 1 + &rshim_dap_adapter_driver, #endif -#if BUILD_OPENDOUS == 1 - &opendous_adapter_driver, +#if BUILD_HLADAPTER_STLINK == 1 + &stlink_dap_adapter_driver, #endif #if BUILD_SYSFSGPIO == 1 &sysfsgpio_adapter_driver, #endif -#if BUILD_LINUXGPIOD == 1 - &linuxgpiod_adapter_driver, -#endif -#if BUILD_XLNX_PCIE_XVC == 1 - &xlnx_pcie_xvc_adapter_driver, -#endif -#if BUILD_AICE == 1 - &aice_adapter_driver, +#if BUILD_ULINK == 1 + &ulink_adapter_driver, #endif -#if BUILD_BCM2835GPIO == 1 - &bcm2835gpio_adapter_driver, +#if BUILD_USB_BLASTER == 1 || BUILD_USB_BLASTER_2 == 1 + &usb_blaster_adapter_driver, #endif -#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1 - &cmsis_dap_adapter_driver, +#if BUILD_USBPROG == 1 + &usbprog_adapter_driver, #endif -#if BUILD_KITPROG == 1 - &kitprog_adapter_driver, +#if BUILD_VDEBUG == 1 + &vdebug_adapter_driver, #endif -#if BUILD_IMX_GPIO == 1 - &imx_gpio_adapter_driver, +#if BUILD_VSLLINK == 1 + &vsllink_adapter_driver, #endif #if BUILD_XDS110 == 1 &xds110_adapter_driver, #endif -#if BUILD_HLADAPTER_STLINK == 1 - &stlink_dap_adapter_driver, -#endif -#if BUILD_RSHIM == 1 - &rshim_dap_adapter_driver, -#endif -#if BUILD_AM335XGPIO == 1 - &am335xgpio_adapter_driver, +#if BUILD_XLNX_PCIE_XVC == 1 + &xlnx_pcie_xvc_adapter_driver, #endif + NULL, - }; +}; diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h index 18e09ced34..47efdff37c 100644 --- a/src/jtag/jtag.h +++ b/src/jtag/jtag.h @@ -12,6 +12,7 @@ #define OPENOCD_JTAG_JTAG_H #include <helper/binarybuffer.h> +#include <helper/command.h> #include <helper/log.h> #include <helper/replacements.h> @@ -33,7 +34,7 @@ * Fix those drivers to map as appropriate ... then pick some * sane set of numbers here (where 0/uninitialized == INVALID). */ -typedef enum tap_state { +enum tap_state { TAP_INVALID = -1, /* Proper ARM recommended numbers */ @@ -53,7 +54,7 @@ typedef enum tap_state { TAP_IRUPDATE = 0xd, TAP_IRCAPTURE = 0xe, TAP_RESET = 0x0f, -} tap_state_t; +}; /** * Defines arguments for reset functions @@ -67,13 +68,13 @@ typedef enum tap_state { * Function tap_state_name * Returns a string suitable for display representing the JTAG tap_state */ -const char *tap_state_name(tap_state_t state); +const char *tap_state_name(enum tap_state state); /** Provides user-friendly name lookup of TAP states. */ -tap_state_t tap_state_by_name(const char *name); +enum tap_state tap_state_by_name(const char *name); /** The current TAP state of the pending JTAG command queue. */ -extern tap_state_t cmd_queue_cur_state; +extern enum tap_state cmd_queue_cur_state; /** * This structure defines a single scan field in the scan. It provides @@ -85,7 +86,7 @@ extern tap_state_t cmd_queue_cur_state; */ struct scan_field { /** The number of bits this field specifies */ - int num_bits; + unsigned int num_bits; /** A pointer to value to be scanned into the device */ const uint8_t *out_value; /** A pointer to a 32-bit memory location for data scanned out */ @@ -101,12 +102,12 @@ struct jtag_tap { char *chip; char *tapname; char *dotted_name; - int abs_chain_position; + unsigned int abs_chain_position; /** Is this TAP disabled after JTAG reset? */ bool disabled_after_reset; /** Is this TAP currently enabled? */ bool enabled; - int ir_length; /**< size of instruction register */ + unsigned int ir_length; /**< size of instruction register */ uint32_t ir_capture_value; uint8_t *expected; /**< Capture-IR expected value */ uint32_t ir_capture_mask; @@ -114,7 +115,7 @@ struct jtag_tap { uint32_t idcode; /**< device identification code */ /** not all devices have idcode, * we'll discover this during chain examination */ - bool hasidcode; + bool has_idcode; /** Array of expected identification codes */ uint32_t *expected_ids; @@ -130,7 +131,10 @@ struct jtag_tap { /** current instruction */ uint8_t *cur_instr; /** Bypass register selected */ - int bypass; + bool bypass; + + /** Bypass instruction value */ + uint64_t ir_bypass_value; struct jtag_tap_event_action *event_action; @@ -146,10 +150,9 @@ struct jtag_tap *jtag_all_taps(void); const char *jtag_tap_name(const struct jtag_tap *tap); struct jtag_tap *jtag_tap_by_string(const char *dotted_name); struct jtag_tap *jtag_tap_by_jim_obj(Jim_Interp *interp, Jim_Obj *obj); -struct jtag_tap *jtag_tap_by_position(unsigned abs_position); +struct jtag_tap *jtag_tap_by_position(unsigned int abs_position); struct jtag_tap *jtag_tap_next_enabled(struct jtag_tap *p); -unsigned jtag_tap_count_enabled(void); -unsigned jtag_tap_count(void); +unsigned int jtag_tap_count_enabled(void); /* * - TRST_ASSERTED triggers two sets of callbacks, after operations to @@ -225,17 +228,17 @@ enum reset_types { enum reset_types jtag_get_reset_config(void); void jtag_set_reset_config(enum reset_types type); -void jtag_set_nsrst_delay(unsigned delay); -unsigned jtag_get_nsrst_delay(void); +void jtag_set_nsrst_delay(unsigned int delay); +unsigned int jtag_get_nsrst_delay(void); -void jtag_set_ntrst_delay(unsigned delay); -unsigned jtag_get_ntrst_delay(void); +void jtag_set_ntrst_delay(unsigned int delay); +unsigned int jtag_get_ntrst_delay(void); -void jtag_set_nsrst_assert_width(unsigned delay); -unsigned jtag_get_nsrst_assert_width(void); +void jtag_set_nsrst_assert_width(unsigned int delay); +unsigned int jtag_get_nsrst_assert_width(void); -void jtag_set_ntrst_assert_width(unsigned delay); -unsigned jtag_get_ntrst_assert_width(void); +void jtag_set_ntrst_assert_width(unsigned int delay); +unsigned int jtag_get_ntrst_assert_width(void); /** @returns The current state of TRST. */ int jtag_get_trst(void); @@ -292,20 +295,20 @@ int jtag_init_inner(struct command_context *cmd_ctx); * */ void jtag_add_ir_scan(struct jtag_tap *tap, - struct scan_field *fields, tap_state_t endstate); + struct scan_field *fields, enum tap_state endstate); /** * The same as jtag_add_ir_scan except no verification is performed out * the output values. */ void jtag_add_ir_scan_noverify(struct jtag_tap *tap, - const struct scan_field *fields, tap_state_t state); + const struct scan_field *fields, enum tap_state state); /** * Scan out the bits in ir scan mode. * * If in_bits == NULL, discard incoming bits. */ void jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, - tap_state_t endstate); + enum tap_state endstate); /** * Generate a DR SCAN using the fields passed to the function. @@ -314,17 +317,17 @@ void jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_b * 1-bit field. The bypass status of TAPs is set by jtag_add_ir_scan(). */ void jtag_add_dr_scan(struct jtag_tap *tap, int num_fields, - const struct scan_field *fields, tap_state_t endstate); + const struct scan_field *fields, enum tap_state endstate); /** A version of jtag_add_dr_scan() that uses the check_value/mask fields */ void jtag_add_dr_scan_check(struct jtag_tap *tap, int num_fields, - struct scan_field *fields, tap_state_t endstate); + struct scan_field *fields, enum tap_state endstate); /** * Scan out the bits in ir scan mode. * * If in_bits == NULL, discard incoming bits. */ void jtag_add_plain_dr_scan(int num_bits, - const uint8_t *out_bits, uint8_t *in_bits, tap_state_t endstate); + const uint8_t *out_bits, uint8_t *in_bits, enum tap_state endstate); /** * Defines the type of data passed to the jtag_callback_t interface. @@ -432,7 +435,7 @@ void jtag_add_tlr(void); * - ERROR_JTAG_TRANSITION_INVALID -- The path includes invalid * state transitions. */ -void jtag_add_pathmove(int num_states, const tap_state_t *path); +void jtag_add_pathmove(unsigned int num_states, const enum tap_state *path); /** * jtag_add_statemove() moves from the current state to @a goal_state. @@ -443,7 +446,7 @@ void jtag_add_pathmove(int num_states, const tap_state_t *path); * Moves from the current state to the goal \a state. * Both states must be stable. */ -int jtag_add_statemove(tap_state_t goal_state); +int jtag_add_statemove(enum tap_state goal_state); /** * Goes to TAP_IDLE (if we're not already there), cycle @@ -455,7 +458,7 @@ int jtag_add_statemove(tap_state_t goal_state); * via TAP_IDLE. * @param endstate The final state. */ -void jtag_add_runtest(int num_cycles, tap_state_t endstate); +void jtag_add_runtest(unsigned int num_cycles, enum tap_state endstate); /** * A reset of the TAP state machine can be requested. @@ -484,14 +487,14 @@ void jtag_add_reset(int req_tlr_or_trst, int srst); void jtag_add_sleep(uint32_t us); -int jtag_add_tms_seq(unsigned nbits, const uint8_t *seq, enum tap_state t); +int jtag_add_tms_seq(unsigned int nbits, const uint8_t *seq, enum tap_state t); /** * Function jtag_add_clocks * first checks that the state in which the clocks are to be issued is * stable, then queues up num_cycles clocks for transmission. */ -void jtag_add_clocks(int num_cycles); +void jtag_add_clocks(unsigned int num_cycles); /** * For software FIFO implementations, the queued commands can be executed @@ -519,7 +522,7 @@ int jtag_execute_queue(void); void jtag_execute_queue_noclear(void); /** @returns the number of times the scan queue has been flushed */ -int jtag_get_flush_queue_count(void); +unsigned int jtag_get_flush_queue_count(void); /** Report Tcl event to all TAPs */ void jtag_notify_event(enum jtag_event); @@ -564,11 +567,6 @@ void jtag_sleep(uint32_t us); * called with a non-zero error code. */ void jtag_set_error(int error); -/** - * Resets jtag_error to ERROR_OK, returning its previous value. - * @returns The previous value of @c jtag_error. - */ -int jtag_error_clear(void); /** * Return true if it's safe for a background polling task to access the @@ -587,8 +585,21 @@ bool jtag_poll_get_enabled(void); */ void jtag_poll_set_enabled(bool value); +/** + * Mask (disable) polling and return the current mask status that should be + * feed to jtag_poll_unmask() to restore it. + * Multiple nested calls to jtag_poll_mask() are allowed, each balanced with + * its call to jtag_poll_unmask(). + */ +bool jtag_poll_mask(void); + +/** + * Restore saved mask for polling. + */ +void jtag_poll_unmask(bool saved); + #include <jtag/minidriver.h> -int jim_jtag_newtap(Jim_Interp *interp, int argc, Jim_Obj *const *argv); +__COMMAND_HANDLER(handle_jtag_newtap); #endif /* OPENOCD_JTAG_JTAG_H */ diff --git a/src/jtag/minidriver.h b/src/jtag/minidriver.h index a40cffa2bd..4b61bf1250 100644 --- a/src/jtag/minidriver.h +++ b/src/jtag/minidriver.h @@ -38,23 +38,23 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field *fields, - tap_state_t endstate); + enum tap_state endstate); int interface_jtag_add_plain_ir_scan( int num_bits, const uint8_t *out_bits, uint8_t *in_bits, - tap_state_t endstate); + enum tap_state endstate); int interface_jtag_add_dr_scan(struct jtag_tap *active, int num_fields, const struct scan_field *fields, - tap_state_t endstate); + enum tap_state endstate); int interface_jtag_add_plain_dr_scan( int num_bits, const uint8_t *out_bits, uint8_t *in_bits, - tap_state_t endstate); + enum tap_state endstate); int interface_jtag_add_tlr(void); -int interface_jtag_add_pathmove(int num_states, const tap_state_t *path); -int interface_jtag_add_runtest(int num_cycles, tap_state_t endstate); +int interface_jtag_add_pathmove(unsigned int num_states, const enum tap_state *path); +int interface_jtag_add_runtest(unsigned int num_cycles, enum tap_state endstate); -int interface_add_tms_seq(unsigned num_bits, +int interface_add_tms_seq(unsigned int num_bits, const uint8_t *bits, enum tap_state state); /** @@ -67,7 +67,7 @@ int interface_add_tms_seq(unsigned num_bits, */ int interface_jtag_add_reset(int trst, int srst); int interface_jtag_add_sleep(uint32_t us); -int interface_jtag_add_clocks(int num_cycles); +int interface_jtag_add_clocks(unsigned int num_cycles); int interface_jtag_execute_queue(void); /** diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl index 238342061f..2d8ebf0410 100644 --- a/src/jtag/startup.tcl +++ b/src/jtag/startup.tcl @@ -122,6 +122,66 @@ proc jtag_ntrst_assert_width args { # # FIXME phase these aids out after some releases # +lappend _telnet_autocomplete_skip adapter_gpio_helper_with_caller +# Helper for deprecated driver functions that should call "adapter gpio XXX". + +# Call this function as: +# adapter_gpio_helper_with_caller caller sig_name +# adapter_gpio_helper_with_caller caller sig_name gpio_num +# adapter_gpio_helper_with_caller caller sig_name chip_num gpio_num +proc adapter_gpio_helper_with_caller {caller sig_name args} { + echo "DEPRECATED! use 'adapter gpio $sig_name' not '$caller'" + switch [llength $args] { + 0 {} + 1 {eval adapter gpio $sig_name $args} + 2 {eval adapter gpio $sig_name [lindex $args 1] -chip [lindex $args 0]} + default {return -code 1 -level 1 "$caller: syntax error"} + } + eval adapter gpio $sig_name +} + +lappend _telnet_autocomplete_skip adapter_gpio_helper +# Call this function as: +# adapter_gpio_helper sig_name +# adapter_gpio_helper sig_name gpio_num +# adapter_gpio_helper sig_name chip_num gpio_num +proc adapter_gpio_helper {sig_name args} { + set caller [lindex [info level -1] 0] + eval adapter_gpio_helper_with_caller {"$caller"} $sig_name $args +} + +lappend _telnet_autocomplete_skip adapter_gpio_jtag_nums_with_caller +# Helper for deprecated driver functions that implemented jtag_nums +proc adapter_gpio_jtag_nums_with_caller {caller tck_num tms_num tdi_num tdo_num} { + echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not '$caller'" + eval adapter gpio tck $tck_num + eval adapter gpio tms $tms_num + eval adapter gpio tdi $tdi_num + eval adapter gpio tdo $tdo_num +} + +lappend _telnet_autocomplete_skip adapter_gpio_jtag_nums +# Helper for deprecated driver functions that implemented jtag_nums +proc adapter_gpio_jtag_nums {args} { + set caller [lindex [info level -1] 0] + eval adapter_gpio_jtag_nums_with_caller {"$caller"} $args +} + +lappend _telnet_autocomplete_skip adapter_gpio_swd_nums_with_caller +# Helper for deprecated driver functions that implemented swd_nums +proc adapter_gpio_swd_nums_with_caller {caller swclk_num swdio_num} { + echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not '$caller'" + eval adapter gpio swclk $swclk_num + eval adapter gpio swdio $swdio_num +} + +lappend _telnet_autocomplete_skip adapter_gpio_swd_nums +# Helper for deprecated driver functions that implemented jtag_nums +proc adapter_gpio_swd_nums {args} { + set caller [lindex [info level -1] 0] + eval adapter_gpio_swd_nums_with_caller {"$caller"} $args +} + lappend _telnet_autocomplete_skip jtag_reset proc jtag_reset args { echo "DEPRECATED! use 'adapter \[de\]assert' not 'jtag_reset'" @@ -395,70 +455,140 @@ proc vsllink_usb_interface args { eval vsllink usb_interface $args } + +lappend _telnet_autocomplete_skip bcm2835_gpio_helper +proc bcm2835_gpio_helper {sig_name args} { + set caller [lindex [info level -1] 0] + echo "DEPRECATED! use 'adapter gpio $sig_name' not '$caller'" + switch [llength $args] { + 0 {} + 1 {eval adapter gpio $sig_name $args -chip 0} + 2 {eval adapter gpio $sig_name [lindex $args 1] -chip [lindex $args 0]} + default {return -code 1 -level 1 "$caller: syntax error"} + } + eval adapter gpio $sig_name +} + lappend _telnet_autocomplete_skip bcm2835gpio_jtag_nums -proc bcm2835gpio_jtag_nums args { - echo "DEPRECATED! use 'bcm2835gpio jtag_nums' not 'bcm2835gpio_jtag_nums'" - eval bcm2835gpio jtag_nums $args +proc bcm2835gpio_jtag_nums {tck_num tms_num tdi_num tdo_num} { + echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'bcm2835gpio_jtag_nums'" + eval adapter gpio tck $tck_num -chip 0 + eval adapter gpio tms $tms_num -chip 0 + eval adapter gpio tdi $tdi_num -chip 0 + eval adapter gpio tdo $tdo_num -chip 0 } lappend _telnet_autocomplete_skip bcm2835gpio_tck_num proc bcm2835gpio_tck_num args { - echo "DEPRECATED! use 'bcm2835gpio tck_num' not 'bcm2835gpio_tck_num'" - eval bcm2835gpio tck_num $args + eval bcm2835_gpio_helper tck $args } lappend _telnet_autocomplete_skip bcm2835gpio_tms_num proc bcm2835gpio_tms_num args { - echo "DEPRECATED! use 'bcm2835gpio tms_num' not 'bcm2835gpio_tms_num'" - eval bcm2835gpio tms_num $args + eval bcm2835_gpio_helper tms $args } lappend _telnet_autocomplete_skip bcm2835gpio_tdo_num proc bcm2835gpio_tdo_num args { - echo "DEPRECATED! use 'bcm2835gpio tdo_num' not 'bcm2835gpio_tdo_num'" - eval bcm2835gpio tdo_num $args + eval bcm2835_gpio_helper tdo $args } lappend _telnet_autocomplete_skip bcm2835gpio_tdi_num proc bcm2835gpio_tdi_num args { - echo "DEPRECATED! use 'bcm2835gpio tdi_num' not 'bcm2835gpio_tdi_num'" - eval bcm2835gpio tdi_num $args + eval bcm2835_gpio_helper tdi $args } lappend _telnet_autocomplete_skip bcm2835gpio_swd_nums -proc bcm2835gpio_swd_nums args { - echo "DEPRECATED! use 'bcm2835gpio swd_nums' not 'bcm2835gpio_swd_nums'" - eval bcm2835gpio swd_nums $args +proc bcm2835gpio_swd_nums {swclk_num swdio_num} { + echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'bcm2835gpio_swd_nums'" + eval adapter gpio swclk $swclk_num -chip 0 + eval adapter gpio swdio $swdio_num -chip 0 } lappend _telnet_autocomplete_skip bcm2835gpio_swclk_num proc bcm2835gpio_swclk_num args { - echo "DEPRECATED! use 'bcm2835gpio swclk_num' not 'bcm2835gpio_swclk_num'" - eval bcm2835gpio swclk_num $args + eval bcm2835_gpio_helper swclk $args } lappend _telnet_autocomplete_skip bcm2835gpio_swdio_num proc bcm2835gpio_swdio_num args { - echo "DEPRECATED! use 'bcm2835gpio swdio_num' not 'bcm2835gpio_swdio_num'" - eval bcm2835gpio swdio_num $args + eval bcm2835_gpio_helper swdio $args } lappend _telnet_autocomplete_skip bcm2835gpio_swdio_dir_num proc bcm2835gpio_swdio_dir_num args { - echo "DEPRECATED! use 'bcm2835gpio swdio_dir_num' not 'bcm2835gpio_swdio_dir_num'" - eval bcm2835gpio swdio_dir_num $args + eval bcm2835_gpio_helper swdio_dir $args } lappend _telnet_autocomplete_skip bcm2835gpio_srst_num proc bcm2835gpio_srst_num args { - echo "DEPRECATED! use 'bcm2835gpio srst_num' not 'bcm2835gpio_srst_num'" - eval bcm2835gpio srst_num $args + eval bcm2835_gpio_helper srst $args } lappend _telnet_autocomplete_skip bcm2835gpio_trst_num proc bcm2835gpio_trst_num args { - echo "DEPRECATED! use 'bcm2835gpio trst_num' not 'bcm2835gpio_trst_num'" - eval bcm2835gpio trst_num $args + eval bcm2835_gpio_helper trst $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio jtag_nums" +proc "bcm2835gpio jtag_nums" {tck_num tms_num tdi_num tdo_num} { + echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'bcm2835gpio jtag_nums'" + eval adapter gpio tck $tck_num -chip 0 + eval adapter gpio tms $tms_num -chip 0 + eval adapter gpio tdi $tdi_num -chip 0 + eval adapter gpio tdo $tdo_num -chip 0 +} + +lappend _telnet_autocomplete_skip "bcm2835gpio tck_num" +proc "bcm2835gpio tck_num" args { + eval bcm2835_gpio_helper tck $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio tms_num" +proc "bcm2835gpio tms_num" args { + eval bcm2835_gpio_helper tms $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio tdo_num" +proc "bcm2835gpio tdo_num" args { + eval bcm2835_gpio_helper tdo $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio tdi_num" +proc "bcm2835gpio tdi_num" args { + eval bcm2835_gpio_helper tdi $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio swd_nums" +proc "bcm2835gpio swd_nums" {swclk_num swdio_num} { + echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'bcm2835gpio swd_nums'" + eval adapter gpio swclk $swclk_num -chip 0 + eval adapter gpio swdio $swdio_num -chip 0 +} + +lappend _telnet_autocomplete_skip "bcm2835gpio swclk_num" +proc "bcm2835gpio swclk_num" args { + eval bcm2835_gpio_helper swclk $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio swdio_num" +proc "bcm2835gpio swdio_num" args { + eval bcm2835_gpio_helper swdio $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio swdio_dir_num" +proc "bcm2835gpio swdio_dir_num" args { + eval bcm2835_gpio_helper swdio_dir $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio srst_num" +proc "bcm2835gpio srst_num" args { + eval bcm2835_gpio_helper srst $args +} + +lappend _telnet_autocomplete_skip "bcm2835gpio trst_num" +proc "bcm2835gpio trst_num" args { + eval bcm2835_gpio_helper trst $args } lappend _telnet_autocomplete_skip bcm2835gpio_speed_coeffs @@ -475,74 +605,72 @@ proc bcm2835gpio_peripheral_base args { lappend _telnet_autocomplete_skip linuxgpiod_jtag_nums proc linuxgpiod_jtag_nums args { - echo "DEPRECATED! use 'linuxgpiod jtag_nums' not 'linuxgpiod_jtag_nums'" - eval linuxgpiod jtag_nums $args + eval adapter_gpio_jtag_nums $args } lappend _telnet_autocomplete_skip linuxgpiod_tck_num proc linuxgpiod_tck_num args { - echo "DEPRECATED! use 'linuxgpiod tck_num' not 'linuxgpiod_tck_num'" - eval linuxgpiod tck_num $args + eval adapter_gpio_helper tck $args } lappend _telnet_autocomplete_skip linuxgpiod_tms_num proc linuxgpiod_tms_num args { - echo "DEPRECATED! use 'linuxgpiod tms_num' not 'linuxgpiod_tms_num'" - eval linuxgpiod tms_num $args + eval adapter_gpio_helper tms $args } lappend _telnet_autocomplete_skip linuxgpiod_tdo_num proc linuxgpiod_tdo_num args { - echo "DEPRECATED! use 'linuxgpiod tdo_num' not 'linuxgpiod_tdo_num'" - eval linuxgpiod tdo_num $args + eval adapter_gpio_helper tdo $args } lappend _telnet_autocomplete_skip linuxgpiod_tdi_num proc linuxgpiod_tdi_num args { - echo "DEPRECATED! use 'linuxgpiod tdi_num' not 'linuxgpiod_tdi_num'" - eval linuxgpiod tdi_num $args + eval adapter_gpio_helper tdi $args } lappend _telnet_autocomplete_skip linuxgpiod_srst_num proc linuxgpiod_srst_num args { - echo "DEPRECATED! use 'linuxgpiod srst_num' not 'linuxgpiod_srst_num'" - eval linuxgpiod srst_num $args + eval adapter_gpio_helper srst $args } lappend _telnet_autocomplete_skip linuxgpiod_trst_num proc linuxgpiod_trst_num args { - echo "DEPRECATED! use 'linuxgpiod trst_num' not 'linuxgpiod_trst_num'" - eval linuxgpiod trst_num $args + eval adapter_gpio_helper trst $args } lappend _telnet_autocomplete_skip linuxgpiod_swd_nums proc linuxgpiod_swd_nums args { - echo "DEPRECATED! use 'linuxgpiod swd_nums' not 'linuxgpiod_swd_nums'" - eval linuxgpiod swd_nums $args + eval adapter_gpio_swd_nums $args } lappend _telnet_autocomplete_skip linuxgpiod_swclk_num proc linuxgpiod_swclk_num args { - echo "DEPRECATED! use 'linuxgpiod swclk_num' not 'linuxgpiod_swclk_num'" - eval linuxgpiod swclk_num $args + eval adapter_gpio_helper swclk $args } lappend _telnet_autocomplete_skip linuxgpiod_swdio_num proc linuxgpiod_swdio_num args { - echo "DEPRECATED! use 'linuxgpiod swdio_num' not 'linuxgpiod_swdio_num'" - eval linuxgpiod swdio_num $args + eval adapter_gpio_helper swdio $args } lappend _telnet_autocomplete_skip linuxgpiod_led_num proc linuxgpiod_led_num args { - echo "DEPRECATED! use 'linuxgpiod led_num' not 'linuxgpiod_led_num'" - eval linuxgpiod led_num $args + eval adapter_gpio_helper led $args } lappend _telnet_autocomplete_skip linuxgpiod_gpiochip proc linuxgpiod_gpiochip args { - echo "DEPRECATED! use 'linuxgpiod gpiochip' not 'linuxgpiod_gpiochip'" - eval linuxgpiod gpiochip $args + echo "DEPRECATED! use 'adapter <signal_name> -chip' not 'linuxgpiod_gpiochip'" + switch [llength $args] { + 0 { } + 1 { + foreach sig_name {tck tms tdi tdo trst srst swclk swdio swdio_dir led} { + eval adapter gpio $sig_name -chip $args + } + } + default {return -code 1 -level 1 "linuxgpiod_gpiochip: syntax error"} + } + eval adapter gpio } lappend _telnet_autocomplete_skip sysfsgpio_jtag_nums @@ -737,12 +865,6 @@ proc ft232r_restore_serial args { eval ft232r restore_serial $args } -lappend _telnet_autocomplete_skip "aice serial" -proc "aice serial" {args} { - echo "DEPRECATED! use 'adapter serial' not 'aice serial'" - eval adapter serial $args -} - lappend _telnet_autocomplete_skip cmsis_dap_serial proc cmsis_dap_serial args { echo "DEPRECATED! use 'adapter serial' not 'cmsis_dap_serial'" @@ -803,4 +925,383 @@ proc "xds110 serial" {args} { eval adapter serial $args } +lappend _telnet_autocomplete_skip linuxgpiod +# linuxgpiod command completely removed, this is required for the sub-commands to work +proc linuxgpiod {subcommand args} { + eval {"linuxgpiod $subcommand"} $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod tck_num" +proc "linuxgpiod tck_num" {args} { + eval adapter_gpio_helper tck $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod tms_num" +proc "linuxgpiod tms_num" {args} { + eval adapter_gpio_helper tms $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod tdi_num" +proc "linuxgpiod tdi_num" {args} { + eval adapter_gpio_helper tdi $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod tdo_num" +proc "linuxgpiod tdo_num" {args} { + eval adapter_gpio_helper tdo $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod trst_num" +proc "linuxgpiod trst_num" {args} { + eval adapter_gpio_helper trst $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod srst_num" +proc "linuxgpiod srst_num" {args} { + eval adapter_gpio_helper srst $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod swclk_num" +proc "linuxgpiod swclk_num" {args} { + eval adapter_gpio_helper swclk $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod swdio_num" +proc "linuxgpiod swdio_num" {args} { + eval adapter_gpio_helper swdio $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod swdio_dir_num" +proc "linuxgpiod swdio_dir_num" {args} { + eval adapter_gpio_helper swdio_dir $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod led_num" +proc "linuxgpiod led_num" {args} { + eval adapter_gpio_helper led $args +} + +lappend _telnet_autocomplete_skip "linuxgpiod gpiochip" +proc "linuxgpiod gpiochip" {num} { + echo "DEPRECATED! use 'adapter <signal_name> -chip' not 'linuxgpiod gpiochip'" + foreach sig_name {tck tms tdi tdo trst srst swclk swdio swdio_dir led} { + eval adapter gpio $sig_name -chip $num + } + eval adapter gpio +} + +lappend _telnet_autocomplete_skip "linuxgpiod jtag_nums" +proc "linuxgpiod jtag_nums" {tck_num tms_num tdi_num tdo_num} { + echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'linuxgpiod jtag_nums'" + eval adapter gpio tck $tck_num + eval adapter gpio tms $tms_num + eval adapter gpio tdi $tdi_num + eval adapter gpio tdo $tdo_num +} + +lappend _telnet_autocomplete_skip "linuxgpiod swd_nums" +proc "linuxgpiod swd_nums" {swclk swdio} { + echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'linuxgpiod jtag_nums'" + eval adapter gpio swclk $swclk + eval adapter gpio swdio $swdio +} + +lappend _telnet_autocomplete_skip "am335xgpio jtag_nums" +proc "am335xgpio jtag_nums" {tck_num tms_num tdi_num tdo_num} { + echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'am335xgpio jtag_nums'" + eval adapter gpio tck [expr {$tck_num % 32}] -chip [expr {$tck_num / 32}] + eval adapter gpio tms [expr {$tms_num % 32}] -chip [expr {$tms_num / 32}] + eval adapter gpio tdi [expr {$tdi_num % 32}] -chip [expr {$tdi_num / 32}] + eval adapter gpio tdo [expr {$tdo_num % 32}] -chip [expr {$tdo_num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio tck_num" +proc "am335xgpio tck_num" {num} { + echo "DEPRECATED! use 'adapter gpio tck' not 'am335xgpio tck_num'" + eval adapter gpio tck [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio tms_num" +proc "am335xgpio tms_num" {num} { + echo "DEPRECATED! use 'adapter gpio tms' not 'am335xgpio tms_num'" + eval adapter gpio tms [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio tdi_num" +proc "am335xgpio tdi_num" {num} { + echo "DEPRECATED! use 'adapter gpio tdi' not 'am335xgpio tdi_num'" + eval adapter gpio tdi [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio tdo_num" +proc "am335xgpio tdo_num" {num} { + echo "DEPRECATED! use 'adapter gpio tdo' not 'am335xgpio tdo_num'" + eval adapter gpio tdo [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio swd_nums" +proc "am335xgpio swd_nums" {swclk swdio} { + echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'am335xgpio jtag_nums'" + eval adapter gpio swclk [expr {$swclk % 32}] -chip [expr {$swclk / 32}] + eval adapter gpio swdio [expr {$swdio % 32}] -chip [expr {$swdio / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio swclk_num" +proc "am335xgpio swclk_num" {num} { + echo "DEPRECATED! use 'adapter gpio swclk' not 'am335xgpio swclk_num'" + eval adapter gpio swclk [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio swdio_num" +proc "am335xgpio swdio_num" {num} { + echo "DEPRECATED! use 'adapter gpio swdio' not 'am335xgpio swdio_num'" + eval adapter gpio swdio [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio swdio_dir_num" +proc "am335xgpio swdio_dir_num" {num} { + echo "DEPRECATED! use 'adapter gpio swdio_dir' not 'am335xgpio swdio_dir_num'" + eval adapter gpio swdio_dir [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio swdio_dir_output_state" +proc "am335xgpio swdio_dir_output_state" {state} { + echo "DEPRECATED! use 'adapter gpio swdio_dir -active-high' or 'adapter gpio swdio_dir -active-low', not 'am335xgpio swdio_dir_output_state'" + switch $state { + "high" + {eval adapter gpio swdio_dir -active-high} + "low" + {eval adapter gpio swdio_dir -active-low} + default + {return -code 1 -level 1 "am335xgpio swdio_dir_output_state: syntax error"} + } +} + +lappend _telnet_autocomplete_skip "am335xgpio srst_num" +proc "am335xgpio srst_num" {num} { + echo "DEPRECATED! use 'adapter gpio srst' not 'am335xgpio srst_num'" + eval adapter gpio srst [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio trst_num" +proc "am335xgpio trst_num" {num} { + echo "DEPRECATED! use 'adapter gpio trst' not 'am335xgpio trst_num'" + eval adapter gpio trst [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio led_num" +proc "am335xgpio led_num" {num} { + echo "DEPRECATED! use 'adapter gpio led' not 'am335xgpio led_num'" + eval adapter gpio led [expr {$num % 32}] -chip [expr {$num / 32}] +} + +lappend _telnet_autocomplete_skip "am335xgpio led_on_state" +proc "am335xgpio led_on_state" {state} { + echo "DEPRECATED! use 'adapter gpio led -active-high' or 'adapter gpio led -active-low', not 'am335xgpio led_on_state'" + switch $state { + "high" + {eval adapter gpio led -active-high} + "low" + {eval adapter gpio led -active-low} + default + {return -code 1 -level 1 "am335xgpio led_on_state: syntax error"} + } +} + +lappend _telnet_autocomplete_skip "cmsis_dap_backend" +proc "cmsis_dap_backend" {backend} { + echo "DEPRECATED! use 'cmsis-dap backend', not 'cmsis_dap_backend'" + eval cmsis-dap backend $backend +} + +lappend _telnet_autocomplete_skip "cmsis_dap_vid_pid" +proc "cmsis_dap_vid_pid" {args} { + echo "DEPRECATED! use 'cmsis-dap vid_pid', not 'cmsis_dap_vid_pid'" + eval cmsis-dap vid_pid $args +} + +lappend _telnet_autocomplete_skip "cmsis_dap_usb" +proc "cmsis_dap_usb" {args} { + echo "DEPRECATED! use 'cmsis-dap usb', not 'cmsis_dap_usb'" + eval cmsis-dap usb $args +} + +lappend _telnet_autocomplete_skip "hla_layout" +proc "hla_layout" {layout} { + echo "DEPRECATED! use 'hla layout', not 'hla_layout'" + eval hla layout $layout +} + +lappend _telnet_autocomplete_skip "hla_device_desc" +proc "hla_device_desc" {desc} { + echo "DEPRECATED! use 'hla device_desc', not 'hla_device_desc'" + eval hla device_desc $desc +} + +lappend _telnet_autocomplete_skip "hla_vid_pid" +proc "hla_vid_pid" {args} { + echo "DEPRECATED! use 'hla vid_pid', not 'hla_vid_pid'" + eval hla vid_pid $args +} + +lappend _telnet_autocomplete_skip "hla_command" +proc "hla_command" {command} { + echo "DEPRECATED! use 'hla command', not 'hla_command'" + eval hla command $command +} + +lappend _telnet_autocomplete_skip "hla_stlink_backend" +proc "hla_stlink_backend" {args} { + echo "DEPRECATED! use 'hla stlink_backend', not 'hla_stlink_backend'" + eval hla stlink_backend $args +} + +lappend _telnet_autocomplete_skip "kitprog_init_acquire_psoc" +proc "kitprog_init_acquire_psoc" {} { + echo "DEPRECATED! use 'kitprog init_acquire_psoc', not 'kitprog_init_acquire_psoc'" + eval kitprog init_acquire_psoc +} + +lappend _telnet_autocomplete_skip "pld device" +proc "pld device" {driver tap_name {opt 0}} { + echo "DEPRECATED! use 'pld create ...', not 'pld device ...'" + if {[string is integer -strict $opt]} { + if {$opt == 0} { + eval pld create [lindex [split $tap_name .] 0].pld $driver -chain-position $tap_name + } else { + eval pld create [lindex [split $tap_name .] 0].pld $driver -chain-position $tap_name -no_jstart + } + } else { + eval pld create [lindex [split $tap_name .] 0].pld $driver -chain-position $tap_name -family $opt + } +} + +lappend _telnet_autocomplete_skip "ipdbg -start" +proc "ipdbg -start" {args} { + echo "DEPRECATED! use 'ipdbg create-hub' and 'chip.ipdbghub ipdbg start ...', not 'ipdbg -start ...'" + set tap_name "" + set pld_name "" + set tool_num "1" + set port_num "4242" + set idx 0 + set num_args [llength $args] + while {$idx < $num_args} { + set arg [lindex $args $idx] + switch -- $arg { + "-tap" { + incr idx + if {$idx >= $num_args || [string index [lindex $args $idx] 0] == "-"} { + echo "no TAP name given" + return + } + set tap_name [lindex $args $idx] + } + "-pld" { + incr idx + if {$idx >= $num_args || [string index [lindex $args $idx] 0] == "-"} { + echo "no PLD name given" + return + } + set pld_name [lindex $args $idx] + } + "-tool" { + if {[expr {$idx + 1}] < $num_args && [string index [lindex $args [expr {$idx + 1}]] 0] != "-"} { + set tool_num [lindex $args [expr {$idx + 1}]] + set args [lreplace $args [expr {$idx + 1}] [expr {$idx + 1}]] + incr num_args -1 + } + set args [lreplace $args $idx $idx] + incr num_args -1 + incr idx -1 + } + "-port" { + if {[expr {$idx + 1}] < $num_args && [string index [lindex $args [expr {$idx + 1}]] 0] != "-"} { + set port_num [lindex $args [expr {$idx + 1}]] + set args [lreplace $args [expr {$idx + 1}] [expr {$idx + 1}]] + incr num_args -1 + } + set args [lreplace $args $idx $idx] + incr num_args -1 + incr idx -1 + } + "-hub" { + set args [lreplace $args $idx $idx "-ir" ] + } + default { +# don't touch remaining arguments + } + } + incr idx + } + + set hub_name "" + if {$tap_name != ""} { + set hub_name [lindex [split $tap_name .] 0].ipdbghub + } elseif {$pld_name != ""} { + set hub_name [lindex [split $pld_name .] 0].ipdbghub + } else { + echo "parsing arguments failed: no tap and no pld given." + return + } + + echo "name: $hub_name" + echo "ipdbg create-hub $hub_name $args" + + catch {eval ipdbg create-hub $hub_name $args} + + eval $hub_name ipdbg start -tool $tool_num -port $port_num +} + +lappend _telnet_autocomplete_skip "ipdbg -stop" +proc "ipdbg -stop" {args} { + echo "DEPRECATED! use 'chip.ipdbghub ipdbg stop ...', not 'ipdbg -stop ...'" + set tap_name "" + set pld_name "" + set tool_num "1" + set idx 0 + set num_args [llength $args] + while {$idx < $num_args} { + set arg [lindex $args $idx] + switch -- $arg { + "-tap" { + incr idx + if {$idx >= $num_args || [string index [lindex $args $idx] 0] == "-"} { + echo "no TAP name given" + return + } + set tap_name [lindex $args $idx] + } + "-pld" { + incr idx + if {$idx >= $num_args || [string index [lindex $args $idx] 0] == "-"} { + echo "no PLD name given" + return + } + set pld_name [lindex $args $idx] + } + "-tool" { + if {[expr {$idx + 1}] < $num_args && [string index [lindex $args [expr {$idx + 1}]] 0] != "-"} { + set tool_num [lindex $args [expr {$idx + 1}]] + } + } + default { +# don't touch remaining arguments + } + } + incr idx + } + + set hub_name "" + if {$tap_name != ""} { + set hub_name [lindex [split $tap_name .] 0].ipdbghub + } elseif {$pld_name != ""} { + set hub_name [lindex [split $pld_name .] 0].ipdbghub + } else { + echo "parsing arguments failed: no tap and no pld given." + return + } + + eval $hub_name ipdbg stop -tool $tool_num +} + # END MIGRATION AIDS diff --git a/src/jtag/swd.h b/src/jtag/swd.h index 5f626c1bf8..c4b6215abd 100644 --- a/src/jtag/swd.h +++ b/src/jtag/swd.h @@ -101,7 +101,7 @@ static const uint8_t swd_seq_line_reset[] = { /* At least 2 idle (low) cycles */ 0x00, }; -static const unsigned swd_seq_line_reset_len = 64; +static const unsigned int swd_seq_line_reset_len = 64; /** * JTAG-to-SWD sequence. @@ -122,7 +122,7 @@ static const uint8_t swd_seq_jtag_to_swd[] = { /* At least 2 idle (low) cycles */ 0x00, }; -static const unsigned swd_seq_jtag_to_swd_len = 136; +static const unsigned int swd_seq_jtag_to_swd_len = 136; /** * SWD-to-JTAG sequence. @@ -141,7 +141,7 @@ static const uint8_t swd_seq_swd_to_jtag[] = { /* At least 5 TCK/SWCLK cycles with TMS/SWDIO high */ 0xff, }; -static const unsigned swd_seq_swd_to_jtag_len = 80; +static const unsigned int swd_seq_swd_to_jtag_len = 80; /** * SWD-to-dormant sequence. @@ -156,7 +156,7 @@ static const uint8_t swd_seq_swd_to_dormant[] = { /* Switching sequence from SWD to dormant */ 0xbc, 0xe3, }; -static const unsigned swd_seq_swd_to_dormant_len = 72; +static const unsigned int swd_seq_swd_to_dormant_len = 72; /** * Dormant-to-SWD sequence. @@ -187,7 +187,7 @@ static const uint8_t swd_seq_dormant_to_swd[] = { /* At least 2 idle (low) cycles */ 0x00, }; -static const unsigned swd_seq_dormant_to_swd_len = 224; +static const unsigned int swd_seq_dormant_to_swd_len = 224; /** * JTAG-to-dormant sequence. @@ -208,7 +208,7 @@ static const uint8_t swd_seq_jtag_to_dormant[] = { 0x77, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */ 0x67, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0x33 << 1) & GENMASK(7, 1)) */ }; -static const unsigned swd_seq_jtag_to_dormant_len = 40; +static const unsigned int swd_seq_jtag_to_dormant_len = 40; /** * Dormant-to-JTAG sequence. @@ -241,7 +241,7 @@ static const uint8_t swd_seq_dormant_to_jtag[] = { /* put the TAP in Run/Test Idle */ 0x00, }; -static const unsigned swd_seq_dormant_to_jtag_len = 160; +static const unsigned int swd_seq_dormant_to_jtag_len = 160; struct swd_driver { /** @@ -270,6 +270,7 @@ struct swd_driver { * @param Where to store value to read from register * @param ap_delay_hint Number of idle cycles that may be * needed after an AP access to avoid WAITs + * or zero in case of DP read. */ void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint); @@ -280,6 +281,7 @@ struct swd_driver { * @param Value to be written to the register * @param ap_delay_hint Number of idle cycles that may be * needed after an AP access to avoid WAITs + * or zero in case of DP write. */ void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint); diff --git a/src/jtag/swim.c b/src/jtag/swim.c index 936268b25a..004a9fd4f2 100644 --- a/src/jtag/swim.c +++ b/src/jtag/swim.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2020 by Antonio Borneo <borneo.antonio@gmail.com @@ -136,7 +136,7 @@ static int swim_transport_init(struct command_context *cmd_ctx) } static struct transport swim_transport = { - .name = "swim", + .id = TRANSPORT_SWIM, .select = swim_transport_select, .init = swim_transport_init, }; diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 37a0285ce1..8b0bc7affb 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -31,6 +31,8 @@ #include <strings.h> #endif +#include <helper/command.h> +#include <helper/nvp.h> #include <helper/time_support.h> #include "transport/transport.h" @@ -39,7 +41,7 @@ * Holds support for accessing JTAG-specific mechanisms from TCl scripts. */ -static const struct jim_nvp nvp_jtag_tap_event[] = { +static const struct nvp nvp_jtag_tap_event[] = { { .value = JTAG_TRST_ASSERTED, .name = "post-reset" }, { .value = JTAG_TAP_EVENT_SETUP, .name = "setup" }, { .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" }, @@ -59,7 +61,7 @@ struct jtag_tap *jtag_tap_by_jim_obj(Jim_Interp *interp, Jim_Obj *o) return t; } -static bool scan_is_safe(tap_state_t state) +static bool scan_is_safe(enum tap_state state) { switch (state) { case TAP_RESET: @@ -72,189 +74,148 @@ static bool scan_is_safe(tap_state_t state) } } -static int jim_command_drscan(Jim_Interp *interp, int argc, Jim_Obj * const *args) +static COMMAND_HELPER(handle_jtag_command_drscan_fields, struct scan_field *fields) { - int retval; - struct scan_field *fields; - int num_fields; - int field_count = 0; - int i, e; - struct jtag_tap *tap; - tap_state_t endstate; + unsigned int field_count = 0; + for (unsigned int i = 1; i < CMD_ARGC; i += 2) { + unsigned int bits; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[i], bits); + fields[field_count].num_bits = bits; - /* args[1] = device - * args[2] = num_bits - * args[3] = hex string - * ... repeat num bits and hex string ... - * - * .. optionally: - * args[N-2] = "-endstate" - * args[N-1] = statename - */ - if ((argc < 4) || ((argc % 2) != 0)) { - Jim_WrongNumArgs(interp, 1, args, "wrong arguments"); - return JIM_ERR; + void *t = malloc(DIV_ROUND_UP(bits, 8)); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + fields[field_count].out_value = t; + int ret = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[i + 1], t, bits); + if (ret != ERROR_OK) + return ret; + fields[field_count].in_value = t; + field_count++; } - endstate = TAP_IDLE; + return ERROR_OK; +} - /* validate arguments as numbers */ - e = JIM_OK; - for (i = 2; i < argc; i += 2) { - long bits; - const char *cp; +COMMAND_HANDLER(handle_jtag_command_drscan) +{ + /* + * CMD_ARGV[0] = device + * CMD_ARGV[1] = num_bits + * CMD_ARGV[2] = hex string + * ... repeat num bits and hex string ... + * + * ... optionally: + * CMD_ARGV[CMD_ARGC-2] = "-endstate" + * CMD_ARGV[CMD_ARGC-1] = statename + */ - e = Jim_GetLong(interp, args[i], &bits); - /* If valid - try next arg */ - if (e == JIM_OK) - continue; + if (CMD_ARGC < 3 || (CMD_ARGC % 2) != 1) + return ERROR_COMMAND_SYNTAX_ERROR; - /* Not valid.. are we at the end? */ - if (((i + 2) != argc)) { - /* nope, then error */ - return e; - } + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[0]); + if (!tap) { + command_print(CMD, "Tap '%s' could not be found", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - /* it could be: "-endstate FOO" - * e.g. DRPAUSE so we can issue more instructions - * before entering RUN/IDLE and executing them. - */ + if (tap->bypass) { + command_print(CMD, "Can't execute as the selected tap is in BYPASS"); + return ERROR_FAIL; + } - /* get arg as a string. */ - cp = Jim_GetString(args[i], NULL); - /* is it the magic? */ - if (strcmp("-endstate", cp) == 0) { - /* is the statename valid? */ - cp = Jim_GetString(args[i + 1], NULL); - - /* see if it is a valid state name */ - endstate = tap_state_by_name(cp); - if (endstate < 0) { - /* update the error message */ - Jim_SetResultFormatted(interp, "endstate: %s invalid", cp); - } else { - if (!scan_is_safe(endstate)) - LOG_WARNING("drscan with unsafe " - "endstate \"%s\"", cp); - - /* valid - so clear the error */ - e = JIM_OK; - /* and remove the last 2 args */ - argc -= 2; - } + enum tap_state endstate = TAP_IDLE; + if (CMD_ARGC > 3 && !strcmp("-endstate", CMD_ARGV[CMD_ARGC - 2])) { + const char *state_name = CMD_ARGV[CMD_ARGC - 1]; + endstate = tap_state_by_name(state_name); + if (endstate < 0) { + command_print(CMD, "endstate: %s invalid", state_name); + return ERROR_COMMAND_ARGUMENT_INVALID; } - /* Still an error? */ - if (e != JIM_OK) - return e; /* too bad */ - } /* validate args */ + if (!scan_is_safe(endstate)) + LOG_WARNING("drscan with unsafe endstate \"%s\"", state_name); - assert(e == JIM_OK); - - tap = jtag_tap_by_jim_obj(interp, args[1]); - if (!tap) - return JIM_ERR; - - num_fields = (argc-2)/2; - if (num_fields <= 0) { - Jim_SetResultString(interp, "drscan: no scan fields supplied", -1); - return JIM_ERR; + CMD_ARGC -= 2; } - fields = malloc(sizeof(struct scan_field) * num_fields); - for (i = 2; i < argc; i += 2) { - long bits; - int len; - const char *str; - - Jim_GetLong(interp, args[i], &bits); - str = Jim_GetString(args[i + 1], &len); - fields[field_count].num_bits = bits; - void *t = malloc(DIV_ROUND_UP(bits, 8)); - fields[field_count].out_value = t; - str_to_buf(str, len, t, bits, 0); - fields[field_count].in_value = t; - field_count++; + unsigned int num_fields = (CMD_ARGC - 1) / 2; + struct scan_field *fields = calloc(num_fields, sizeof(struct scan_field)); + if (!fields) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } + int retval = CALL_COMMAND_HANDLER(handle_jtag_command_drscan_fields, fields); + if (retval != ERROR_OK) + goto fail; + jtag_add_dr_scan(tap, num_fields, fields, endstate); retval = jtag_execute_queue(); if (retval != ERROR_OK) { - Jim_SetResultString(interp, "drscan: jtag execute failed", -1); - - for (i = 0; i < field_count; i++) - free(fields[i].in_value); - free(fields); - - return JIM_ERR; + command_print(CMD, "drscan: jtag execute failed"); + goto fail; } - field_count = 0; - Jim_Obj *list = Jim_NewListObj(interp, NULL, 0); - for (i = 2; i < argc; i += 2) { - long bits; - char *str; - - Jim_GetLong(interp, args[i], &bits); - str = buf_to_hex_str(fields[field_count].in_value, bits); - free(fields[field_count].in_value); - - Jim_ListAppendElement(interp, list, Jim_NewStringObj(interp, str, strlen(str))); + for (unsigned int i = 0; i < num_fields; i++) { + char *str = buf_to_hex_str(fields[i].in_value, fields[i].num_bits); + command_print(CMD, "%s", str); free(str); - field_count++; } - Jim_SetResult(interp, list); - +fail: + for (unsigned int i = 0; i < num_fields; i++) + free(fields[i].in_value); free(fields); - return JIM_OK; + return retval; } - -static int jim_command_pathmove(Jim_Interp *interp, int argc, Jim_Obj * const *args) +COMMAND_HANDLER(handle_jtag_command_pathmove) { - tap_state_t states[8]; + enum tap_state states[8]; - if ((argc < 2) || ((size_t)argc > (ARRAY_SIZE(states) + 1))) { - Jim_WrongNumArgs(interp, 1, args, "wrong arguments"); - return JIM_ERR; - } + if (CMD_ARGC < 1 || CMD_ARGC > ARRAY_SIZE(states)) + return ERROR_COMMAND_SYNTAX_ERROR; - int i; - for (i = 0; i < argc-1; i++) { - const char *cp; - cp = Jim_GetString(args[i + 1], NULL); - states[i] = tap_state_by_name(cp); + for (unsigned int i = 0; i < CMD_ARGC; i++) { + states[i] = tap_state_by_name(CMD_ARGV[i]); if (states[i] < 0) { - /* update the error message */ - Jim_SetResultFormatted(interp, "endstate: %s invalid", cp); - return JIM_ERR; + command_print(CMD, "endstate: %s invalid", CMD_ARGV[i]); + return ERROR_COMMAND_ARGUMENT_INVALID; } } - if ((jtag_add_statemove(states[0]) != ERROR_OK) || (jtag_execute_queue() != ERROR_OK)) { - Jim_SetResultString(interp, "pathmove: jtag execute failed", -1); - return JIM_ERR; + int retval = jtag_add_statemove(states[0]); + if (retval == ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + command_print(CMD, "pathmove: jtag execute failed"); + return retval; } - jtag_add_pathmove(argc - 2, states + 1); - - if (jtag_execute_queue() != ERROR_OK) { - Jim_SetResultString(interp, "pathmove: failed", -1); - return JIM_ERR; + jtag_add_pathmove(CMD_ARGC - 1, states + 1); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + command_print(CMD, "pathmove: failed"); + return retval; } - return JIM_OK; + return ERROR_OK; } - -static int jim_command_flush_count(Jim_Interp *interp, int argc, Jim_Obj * const *args) +COMMAND_HANDLER(handle_jtag_flush_count) { - Jim_SetResult(interp, Jim_NewIntObj(interp, jtag_get_flush_queue_count())); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - return JIM_OK; + const unsigned int count = jtag_get_flush_queue_count(); + command_print_sameline(CMD, "%u", count); + + return ERROR_OK; } /* REVISIT Just what about these should "move" ... ? @@ -271,22 +232,23 @@ static const struct command_registration jtag_command_handlers_to_move[] = { { .name = "drscan", .mode = COMMAND_EXEC, - .jim_handler = jim_command_drscan, + .handler = handle_jtag_command_drscan, .help = "Execute Data Register (DR) scan for one TAP. " "Other TAPs must be in BYPASS mode.", - .usage = "tap_name [num_bits value]* ['-endstate' state_name]", + .usage = "tap_name (num_bits value)+ ['-endstate' state_name]", }, { .name = "flush_count", .mode = COMMAND_EXEC, - .jim_handler = jim_command_flush_count, + .handler = handle_jtag_flush_count, .help = "Returns the number of times the JTAG queue " "has been flushed.", + .usage = "", }, { .name = "pathmove", .mode = COMMAND_EXEC, - .jim_handler = jim_command_pathmove, + .handler = handle_jtag_command_pathmove, .usage = "start_state state1 [state2 [state3 ...]]", .help = "Move JTAG state machine from current state " "(start_state) to state1, then state2, state3, etc.", @@ -300,156 +262,104 @@ enum jtag_tap_cfg_param { JCFG_IDCODE, }; -static struct jim_nvp nvp_config_opts[] = { +static struct nvp nvp_config_opts[] = { { .name = "-event", .value = JCFG_EVENT }, { .name = "-idcode", .value = JCFG_IDCODE }, { .name = NULL, .value = -1 } }; -static int jtag_tap_configure_event(struct jim_getopt_info *goi, struct jtag_tap *tap) +static int jtag_tap_set_event(struct command_context *cmd_ctx, struct jtag_tap *tap, + const struct nvp *event, Jim_Obj *body) { - if (goi->argc == 0) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event <event-name> ..."); - return JIM_ERR; - } + struct jtag_tap_event_action *jteap = tap->event_action; - struct jim_nvp *n; - int e = jim_getopt_nvp(goi, nvp_jtag_tap_event, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, nvp_jtag_tap_event, 1); - return e; - } - - if (goi->isconfigure) { - if (goi->argc != 1) { - Jim_WrongNumArgs(goi->interp, - goi->argc, - goi->argv, - "-event <event-name> <event-body>"); - return JIM_ERR; - } - } else { - if (goi->argc != 0) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event <event-name>"); - return JIM_ERR; - } - } - - struct jtag_tap_event_action *jteap = tap->event_action; - /* replace existing event body */ - bool found = false; while (jteap) { - if (jteap->event == (enum jtag_event)n->value) { - found = true; + if (jteap->event == (enum jtag_event)event->value) break; - } jteap = jteap->next; } - Jim_SetEmptyResult(goi->interp); - - if (goi->isconfigure) { - if (!found) - jteap = calloc(1, sizeof(*jteap)); - else if (jteap->body) - Jim_DecrRefCount(goi->interp, jteap->body); + if (!jteap) { + jteap = calloc(1, sizeof(*jteap)); + if (!jteap) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } - jteap->interp = goi->interp; - jteap->event = n->value; + /* add to head of event list */ + jteap->next = tap->event_action; + tap->event_action = jteap; + } else { + Jim_DecrRefCount(cmd_ctx->interp, jteap->body); + } - Jim_Obj *o; - jim_getopt_obj(goi, &o); - jteap->body = Jim_DuplicateObj(goi->interp, o); - Jim_IncrRefCount(jteap->body); + jteap->interp = cmd_ctx->interp; + jteap->event = (enum jtag_event)event->value; + jteap->body = Jim_DuplicateObj(cmd_ctx->interp, body); + Jim_IncrRefCount(jteap->body); - if (!found) { - /* add to head of event list */ - jteap->next = tap->event_action; - tap->event_action = jteap; - } - } else if (found) { - jteap->interp = goi->interp; - Jim_SetResult(goi->interp, - Jim_DuplicateObj(goi->interp, jteap->body)); - } - return JIM_OK; + return ERROR_OK; } -static int jtag_tap_configure_cmd(struct jim_getopt_info *goi, struct jtag_tap *tap) +__COMMAND_HANDLER(handle_jtag_configure) { - /* parse config or cget options */ - while (goi->argc > 0) { - Jim_SetEmptyResult(goi->interp); - - struct jim_nvp *n; - int e = jim_getopt_nvp(goi, nvp_config_opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, nvp_config_opts, 0); - return e; - } + bool is_configure = !strcmp(CMD_NAME, "configure"); - switch (n->value) { - case JCFG_EVENT: - e = jtag_tap_configure_event(goi, tap); - if (e != JIM_OK) - return e; - break; - case JCFG_IDCODE: - if (goi->isconfigure) { - Jim_SetResultFormatted(goi->interp, - "not settable: %s", n->name); - return JIM_ERR; - } else { - if (goi->argc != 0) { - Jim_WrongNumArgs(goi->interp, - goi->argc, goi->argv, - "NO PARAMS"); - return JIM_ERR; - } - } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, tap->idcode)); - break; - default: - Jim_SetResultFormatted(goi->interp, "unknown value: %s", n->name); - return JIM_ERR; - } - } + if (CMD_ARGC < (is_configure ? 3 : 2)) + return ERROR_COMMAND_SYNTAX_ERROR; - return JIM_OK; -} + /* FIXME: rework jtag_tap_by_jim_obj */ + struct jtag_tap *tap = jtag_tap_by_jim_obj(CMD_CTX->interp, CMD_JIMTCL_ARGV[0]); + if (!tap) + return ERROR_FAIL; -static int is_bad_irval(int ir_length, jim_wide w) -{ - jim_wide v = 1; + for (unsigned int i = 1; i < CMD_ARGC; i++) { + const struct nvp *n = nvp_name2value(nvp_config_opts, CMD_ARGV[i]); + switch (n->value) { + case JCFG_EVENT: + if (i + (is_configure ? 2 : 1) >= CMD_ARGC) { + command_print(CMD, "wrong # args: should be \"-event <event-name>%s\"", + is_configure ? " <event-body>" : ""); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - v <<= ir_length; - v -= 1; - v = ~v; - return (w & v) != 0; -} + const struct nvp *event = nvp_name2value(nvp_jtag_tap_event, CMD_ARGV[i + 1]); + if (!event->name) { + nvp_unknown_command_print(CMD, nvp_jtag_tap_event, CMD_ARGV[i], CMD_ARGV[i + 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } -static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, - struct jtag_tap *tap) -{ - jim_wide w; - int e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", n->name); - return e; - } + if (is_configure) { + int retval = jtag_tap_set_event(CMD_CTX, tap, event, CMD_JIMTCL_ARGV[i + 2]); + if (retval != ERROR_OK) + return retval; + } else { + struct jtag_tap_event_action *jteap = tap->event_action; + while (jteap) { + if (jteap->event == (enum jtag_event)event->value) { + command_print(CMD, "%s", Jim_GetString(jteap->body, NULL)); + break; + } + jteap = jteap->next; + } + } - uint32_t *p = realloc(tap->expected_ids, - (tap->expected_ids_cnt + 1) * sizeof(uint32_t)); - if (!p) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; + i += is_configure ? 2 : 1; + break; + case JCFG_IDCODE: + if (is_configure) { + command_print(CMD, "not settable: %s", n->name); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + command_print(CMD, "0x%08x", tap->idcode); + break; + default: + nvp_unknown_command_print(CMD, nvp_config_opts, NULL, CMD_ARGV[i]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } } - - tap->expected_ids = p; - tap->expected_ids[tap->expected_ids_cnt++] = w; - - return JIM_OK; + return ERROR_OK; } #define NTAP_OPT_IRLEN 0 @@ -460,174 +370,167 @@ static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi #define NTAP_OPT_EXPECTED_ID 5 #define NTAP_OPT_VERSION 6 #define NTAP_OPT_BYPASS 7 +#define NTAP_OPT_IRBYPASS 8 + +static const struct nvp jtag_newtap_opts[] = { + { .name = "-irlen", .value = NTAP_OPT_IRLEN }, + { .name = "-irmask", .value = NTAP_OPT_IRMASK }, + { .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE }, + { .name = "-enable", .value = NTAP_OPT_ENABLED }, + { .name = "-disable", .value = NTAP_OPT_DISABLED }, + { .name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID }, + { .name = "-ignore-version", .value = NTAP_OPT_VERSION }, + { .name = "-ignore-bypass", .value = NTAP_OPT_BYPASS }, + { .name = "-ir-bypass", .value = NTAP_OPT_IRBYPASS }, + { .name = NULL, .value = -1 }, +}; -static int jim_newtap_ir_param(struct jim_nvp *n, struct jim_getopt_info *goi, - struct jtag_tap *tap) +static COMMAND_HELPER(handle_jtag_newtap_args, struct jtag_tap *tap) { - jim_wide w; - int e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi->interp, - "option: %s bad parameter", n->name); - return e; + /* we expect CHIP + TAP + OPTIONS */ + if (CMD_ARGC < 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + tap->chip = strdup(CMD_ARGV[0]); + tap->tapname = strdup(CMD_ARGV[1]); + tap->dotted_name = alloc_printf("%s.%s", CMD_ARGV[0], CMD_ARGV[1]); + if (!tap->chip || !tap->tapname || !tap->dotted_name) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } - switch (n->value) { - case NTAP_OPT_IRLEN: - if (w > (jim_wide) (8 * sizeof(tap->ir_capture_value))) { - LOG_WARNING("%s: huge IR length %d", - tap->dotted_name, (int) w); - } - tap->ir_length = w; - break; - case NTAP_OPT_IRMASK: - if (is_bad_irval(tap->ir_length, w)) { - LOG_ERROR("%s: IR mask %x too big", - tap->dotted_name, - (int) w); - return JIM_ERR; - } - if ((w & 3) != 3) - LOG_WARNING("%s: nonstandard IR mask", tap->dotted_name); - tap->ir_capture_mask = w; + CMD_ARGC -= 2; + CMD_ARGV += 2; + + LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params", + tap->chip, tap->tapname, tap->dotted_name, CMD_ARGC); + + /* + * IEEE specifies that the two LSBs of an IR scan are 01, so make + * that the default. The "-ircapture" and "-irmask" options are only + * needed to cope with nonstandard TAPs, or to specify more bits. + */ + tap->ir_capture_mask = 0x03; + tap->ir_capture_value = 0x01; + + while (CMD_ARGC) { + const struct nvp *n = nvp_name2value(jtag_newtap_opts, CMD_ARGV[0]); + CMD_ARGC--; + CMD_ARGV++; + switch (n->value) { + case NTAP_OPT_ENABLED: + tap->disabled_after_reset = false; break; - case NTAP_OPT_IRCAPTURE: - if (is_bad_irval(tap->ir_length, w)) { - LOG_ERROR("%s: IR capture %x too big", - tap->dotted_name, (int) w); - return JIM_ERR; - } - if ((w & 3) != 1) - LOG_WARNING("%s: nonstandard IR value", - tap->dotted_name); - tap->ir_capture_value = w; + + case NTAP_OPT_DISABLED: + tap->disabled_after_reset = true; break; - default: - return JIM_ERR; - } - return JIM_OK; -} -static int jim_newtap_cmd(struct jim_getopt_info *goi) -{ - struct jtag_tap *tap; - int x; - int e; - struct jim_nvp *n; - char *cp; - const struct jim_nvp opts[] = { - { .name = "-irlen", .value = NTAP_OPT_IRLEN }, - { .name = "-irmask", .value = NTAP_OPT_IRMASK }, - { .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE }, - { .name = "-enable", .value = NTAP_OPT_ENABLED }, - { .name = "-disable", .value = NTAP_OPT_DISABLED }, - { .name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID }, - { .name = "-ignore-version", .value = NTAP_OPT_VERSION }, - { .name = "-ignore-bypass", .value = NTAP_OPT_BYPASS }, - { .name = NULL, .value = -1 }, - }; - - tap = calloc(1, sizeof(struct jtag_tap)); - if (!tap) { - Jim_SetResultFormatted(goi->interp, "no memory"); - return JIM_ERR; - } + case NTAP_OPT_EXPECTED_ID: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; - /* - * we expect CHIP + TAP + OPTIONS - * */ - if (goi->argc < 3) { - Jim_SetResultFormatted(goi->interp, "Missing CHIP TAP OPTIONS ...."); - free(tap); - return JIM_ERR; - } + tap->expected_ids = realloc(tap->expected_ids, + (tap->expected_ids_cnt + 1) * sizeof(uint32_t)); + if (!tap->expected_ids) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } - const char *tmp; - jim_getopt_string(goi, &tmp, NULL); - tap->chip = strdup(tmp); + uint32_t id; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], id); + CMD_ARGC--; + CMD_ARGV++; + tap->expected_ids[tap->expected_ids_cnt++] = id; - jim_getopt_string(goi, &tmp, NULL); - tap->tapname = strdup(tmp); + break; - /* name + dot + name + null */ - x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1; - cp = malloc(x); - sprintf(cp, "%s.%s", tap->chip, tap->tapname); - tap->dotted_name = cp; + case NTAP_OPT_IRLEN: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; - LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params", - tap->chip, tap->tapname, tap->dotted_name, goi->argc); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], tap->ir_length); + CMD_ARGC--; + CMD_ARGV++; + if (tap->ir_length > (8 * sizeof(tap->ir_capture_value))) + LOG_WARNING("%s: huge IR length %u", tap->dotted_name, tap->ir_length); + break; - if (!transport_is_jtag()) { - /* SWD doesn't require any JTAG tap parameters */ - tap->enabled = true; - jtag_tap_init(tap); - return JIM_OK; - } + case NTAP_OPT_IRMASK: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; - /* IEEE specifies that the two LSBs of an IR scan are 01, so make - * that the default. The "-ircapture" and "-irmask" options are only - * needed to cope with nonstandard TAPs, or to specify more bits. - */ - tap->ir_capture_mask = 0x03; - tap->ir_capture_value = 0x01; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], tap->ir_capture_mask); + CMD_ARGC--; + CMD_ARGV++; + if ((tap->ir_capture_mask & 3) != 3) + LOG_WARNING("%s: nonstandard IR mask", tap->dotted_name); + break; + + case NTAP_OPT_IRCAPTURE: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], tap->ir_capture_value); + CMD_ARGC--; + CMD_ARGV++; + if ((tap->ir_capture_value & 3) != 1) + LOG_WARNING("%s: nonstandard IR value", tap->dotted_name); + break; + + case NTAP_OPT_VERSION: + tap->ignore_version = true; + break; - while (goi->argc) { - e = jim_getopt_nvp(goi, opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, opts, 0); - free(cp); - free(tap); - return e; + case NTAP_OPT_BYPASS: + tap->ignore_bypass = true; + break; + + case NTAP_OPT_IRBYPASS: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], tap->ir_bypass_value); + CMD_ARGC--; + CMD_ARGV++; + break; + + default: + nvp_unknown_command_print(CMD, jtag_newtap_opts, NULL, CMD_ARGV[-1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - LOG_DEBUG("Processing option: %s", n->name); - switch (n->value) { - case NTAP_OPT_ENABLED: - tap->disabled_after_reset = false; - break; - case NTAP_OPT_DISABLED: - tap->disabled_after_reset = true; - break; - case NTAP_OPT_EXPECTED_ID: - e = jim_newtap_expected_id(n, goi, tap); - if (e != JIM_OK) { - free(cp); - free(tap); - return e; - } - break; - case NTAP_OPT_IRLEN: - case NTAP_OPT_IRMASK: - case NTAP_OPT_IRCAPTURE: - e = jim_newtap_ir_param(n, goi, tap); - if (e != JIM_OK) { - free(cp); - free(tap); - return e; - } - break; - case NTAP_OPT_VERSION: - tap->ignore_version = true; - break; - case NTAP_OPT_BYPASS: - tap->ignore_bypass = true; - break; - } /* switch (n->value) */ - } /* while (goi->argc) */ + } /* default is enabled-after-reset */ tap->enabled = !tap->disabled_after_reset; - /* Did all the required option bits get cleared? */ - if (tap->ir_length != 0) { - jtag_tap_init(tap); - return JIM_OK; + if (transport_is_jtag() && tap->ir_length == 0) { + command_print(CMD, "newtap: %s missing IR length", tap->dotted_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + return ERROR_OK; +} + +__COMMAND_HANDLER(handle_jtag_newtap) +{ + struct jtag_tap *tap = calloc(1, sizeof(struct jtag_tap)); + if (!tap) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } - Jim_SetResultFormatted(goi->interp, - "newtap: %s missing IR length", - tap->dotted_name); - jtag_tap_free(tap); - return JIM_ERR; + int retval = CALL_COMMAND_HANDLER(handle_jtag_newtap_args, tap); + if (retval != ERROR_OK) { + free(tap->chip); + free(tap->tapname); + free(tap->dotted_name); + free(tap->expected_ids); + free(tap); + return retval; + } + + jtag_tap_init(tap); + return ERROR_OK; } static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e) @@ -639,7 +542,7 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e) if (jteap->event != e) continue; - struct jim_nvp *nvp = jim_nvp_value2name_simple(nvp_jtag_tap_event, e); + const struct nvp *nvp = nvp_value2name(nvp_jtag_tap_event, e); LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s", tap->dotted_name, e, nvp->name, Jim_GetString(jteap->body, NULL)); @@ -671,58 +574,32 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e) } } -static int jim_jtag_arp_init(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_jtag_arp_init) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)"); - return JIM_ERR; - } - struct command_context *context = current_command_context(interp); - int e = jtag_init_inner(context); - if (e != ERROR_OK) { - Jim_Obj *obj = Jim_NewIntObj(goi.interp, e); - Jim_SetResultFormatted(goi.interp, "error: %#s", obj); - return JIM_ERR; - } - return JIM_OK; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + return jtag_init_inner(CMD_CTX); } -static int jim_jtag_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_jtag_arp_init_reset) { - int e = ERROR_OK; - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)"); - return JIM_ERR; - } - struct command_context *context = current_command_context(interp); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + if (transport_is_jtag()) - e = jtag_init_reset(context); - else if (transport_is_swd()) - e = swd_init_reset(context); - - if (e != ERROR_OK) { - Jim_Obj *obj = Jim_NewIntObj(goi.interp, e); - Jim_SetResultFormatted(goi.interp, "error: %#s", obj); - return JIM_ERR; - } - return JIM_OK; -} + return jtag_init_reset(CMD_CTX); -int jim_jtag_newtap(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - return jim_newtap_cmd(&goi); + if (transport_is_swd()) + return swd_init_reset(CMD_CTX); + + return ERROR_OK; } static bool jtag_tap_enable(struct jtag_tap *t) { if (t->enabled) - return false; + return true; jtag_tap_handle_event(t, JTAG_TAP_EVENT_ENABLE); if (!t->enabled) return false; @@ -737,7 +614,7 @@ static bool jtag_tap_enable(struct jtag_tap *t) static bool jtag_tap_disable(struct jtag_tap *t) { if (!t->enabled) - return false; + return true; jtag_tap_handle_event(t, JTAG_TAP_EVENT_DISABLE); if (t->enabled) return false; @@ -750,86 +627,47 @@ static bool jtag_tap_disable(struct jtag_tap *t) return true; } -int jim_jtag_tap_enabler(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +__COMMAND_HANDLER(handle_jtag_tap_enabler) { - struct command *c = jim_to_command(interp); - const char *cmd_name = c->name; - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - if (goi.argc != 1) { - Jim_SetResultFormatted(goi.interp, "usage: %s <name>", cmd_name); - return JIM_ERR; - } - - struct jtag_tap *t; + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; - t = jtag_tap_by_jim_obj(goi.interp, goi.argv[0]); - if (!t) - return JIM_ERR; + struct jtag_tap *t = jtag_tap_by_string(CMD_ARGV[0]); + if (!t) { + command_print(CMD, "Tap '%s' could not be found", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - if (strcasecmp(cmd_name, "tapisenabled") == 0) { + if (strcmp(CMD_NAME, "tapisenabled") == 0) { /* do nothing, just return the value */ - } else if (strcasecmp(cmd_name, "tapenable") == 0) { + } else if (strcmp(CMD_NAME, "tapenable") == 0) { if (!jtag_tap_enable(t)) { - LOG_WARNING("failed to enable tap %s", t->dotted_name); - return JIM_ERR; + command_print(CMD, "failed to enable tap %s", t->dotted_name); + return ERROR_FAIL; } - } else if (strcasecmp(cmd_name, "tapdisable") == 0) { + } else if (strcmp(CMD_NAME, "tapdisable") == 0) { if (!jtag_tap_disable(t)) { - LOG_WARNING("failed to disable tap %s", t->dotted_name); - return JIM_ERR; + command_print(CMD, "failed to disable tap %s", t->dotted_name); + return ERROR_FAIL; } } else { - LOG_ERROR("command '%s' unknown", cmd_name); - return JIM_ERR; - } - bool e = t->enabled; - Jim_SetResult(goi.interp, Jim_NewIntObj(goi.interp, e)); - return JIM_OK; -} - -int jim_jtag_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct command *c = jim_to_command(interp); - const char *cmd_name = c->name; - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - goi.isconfigure = !strcmp(cmd_name, "configure"); - if (goi.argc < 2 + goi.isconfigure) { - Jim_WrongNumArgs(goi.interp, 0, NULL, - "<tap_name> <attribute> ..."); - return JIM_ERR; + command_print(CMD, "command '%s' unknown", CMD_NAME); + return ERROR_FAIL; } - struct jtag_tap *t; - - Jim_Obj *o; - jim_getopt_obj(&goi, &o); - t = jtag_tap_by_jim_obj(goi.interp, o); - if (!t) - return JIM_ERR; - - return jtag_tap_configure_cmd(&goi, t); + command_print(CMD, "%d", t->enabled ? 1 : 0); + return ERROR_OK; } -static int jim_jtag_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_jtag_names) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc-1, argv + 1); - if (goi.argc != 0) { - Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(goi.interp, Jim_NewListObj(goi.interp, NULL, 0)); - struct jtag_tap *tap; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - for (tap = jtag_all_taps(); tap; tap = tap->next_tap) { - Jim_ListAppendElement(goi.interp, - Jim_GetResult(goi.interp), - Jim_NewStringObj(goi.interp, - tap->dotted_name, -1)); - } - return JIM_OK; + for (struct jtag_tap *tap = jtag_all_taps(); tap; tap = tap->next_tap) + command_print(CMD, "%s", tap->dotted_name); + + return ERROR_OK; } COMMAND_HANDLER(handle_jtag_init_command) @@ -859,22 +697,24 @@ static const struct command_registration jtag_subcommand_handlers[] = { { .name = "arp_init", .mode = COMMAND_ANY, - .jim_handler = jim_jtag_arp_init, + .handler = handle_jtag_arp_init, .help = "Validates JTAG scan chain against the list of " "declared TAPs using just the four standard JTAG " "signals.", + .usage = "", }, { .name = "arp_init-reset", .mode = COMMAND_ANY, - .jim_handler = jim_jtag_arp_init_reset, + .handler = handle_jtag_arp_init_reset, .help = "Uses TRST and SRST to try resetting everything on " - "the JTAG scan chain, then performs 'jtag arp_init'." + "the JTAG scan chain, then performs 'jtag arp_init'.", + .usage = "", }, { .name = "newtap", .mode = COMMAND_CONFIG, - .jim_handler = jim_jtag_newtap, + .handler = handle_jtag_newtap, .help = "Create a new TAP instance named basename.tap_type, " "and appends it to the scan chain.", .usage = "basename tap_type '-irlen' count " @@ -883,12 +723,13 @@ static const struct command_registration jtag_subcommand_handlers[] = { "['-ignore-version'] " "['-ignore-bypass'] " "['-ircapture' number] " + "['-ir-bypass' number] " "['-mask' number]", }, { .name = "tapisenabled", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, .help = "Returns a Tcl boolean (0/1) indicating whether " "the TAP is enabled (1) or not (0).", .usage = "tap_name", @@ -896,7 +737,7 @@ static const struct command_registration jtag_subcommand_handlers[] = { { .name = "tapenable", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, .help = "Try to enable the specified TAP using the " "'tap-enable' TAP event.", .usage = "tap_name", @@ -904,7 +745,7 @@ static const struct command_registration jtag_subcommand_handlers[] = { { .name = "tapdisable", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, .help = "Try to disable the specified TAP using the " "'tap-disable' TAP event.", .usage = "tap_name", @@ -912,7 +753,7 @@ static const struct command_registration jtag_subcommand_handlers[] = { { .name = "configure", .mode = COMMAND_ANY, - .jim_handler = jim_jtag_configure, + .handler = handle_jtag_configure, .help = "Provide a Tcl handler for the specified " "TAP event.", .usage = "tap_name '-event' event_name handler", @@ -920,16 +761,18 @@ static const struct command_registration jtag_subcommand_handlers[] = { { .name = "cget", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_configure, + .handler = handle_jtag_configure, .help = "Return any Tcl handler for the specified " - "TAP event.", - .usage = "tap_name '-event' event_name", + "TAP event or the value of the IDCODE found in hardware.", + .usage = "tap_name '-event' event_name | " + "tap_name '-idcode'", }, { .name = "names", .mode = COMMAND_ANY, - .jim_handler = jim_jtag_names, + .handler = handle_jtag_names, .help = "Returns list of all JTAG tap names.", + .usage = "", }, { .chain = jtag_command_handlers_to_move, @@ -960,10 +803,8 @@ COMMAND_HANDLER(handle_scan_chain_command) while (tap) { uint32_t expected, expected_mask, ii; - snprintf(expected_id, sizeof(expected_id), "0x%08x", - (unsigned)((tap->expected_ids_cnt > 0) - ? tap->expected_ids[0] - : 0)); + snprintf(expected_id, sizeof(expected_id), "0x%08" PRIx32, + (tap->expected_ids_cnt > 0) ? tap->expected_ids[0] : 0); if (tap->ignore_version) expected_id[2] = '*'; @@ -971,19 +812,18 @@ COMMAND_HANDLER(handle_scan_chain_command) expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length); command_print(CMD, - "%2d %-18s %c 0x%08x %s %5d 0x%02x 0x%02x", + "%2u %-18s %c 0x%08x %s %5u 0x%02x 0x%02x", tap->abs_chain_position, tap->dotted_name, tap->enabled ? 'Y' : 'n', (unsigned int)(tap->idcode), expected_id, - (unsigned int)(tap->ir_length), + tap->ir_length, (unsigned int)(expected), (unsigned int)(expected_mask)); for (ii = 1; ii < tap->expected_ids_cnt; ii++) { - snprintf(expected_id, sizeof(expected_id), "0x%08x", - (unsigned) tap->expected_ids[ii]); + snprintf(expected_id, sizeof(expected_id), "0x%08" PRIx32, tap->expected_ids[ii]); if (tap->ignore_version) expected_id[2] = '*'; @@ -1003,7 +843,7 @@ COMMAND_HANDLER(handle_jtag_ntrst_delay_command) if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; if (CMD_ARGC == 1) { - unsigned delay; + unsigned int delay; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], delay); jtag_set_ntrst_delay(delay); @@ -1017,7 +857,7 @@ COMMAND_HANDLER(handle_jtag_ntrst_assert_width_command) if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; if (CMD_ARGC == 1) { - unsigned delay; + unsigned int delay; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], delay); jtag_set_ntrst_assert_width(delay); @@ -1033,7 +873,7 @@ COMMAND_HANDLER(handle_jtag_rclk_command) int retval = ERROR_OK; if (CMD_ARGC == 1) { - unsigned khz = 0; + unsigned int khz = 0; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz); retval = adapter_config_rclk(khz); @@ -1059,7 +899,7 @@ COMMAND_HANDLER(handle_runtest_command) if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned num_clocks; + unsigned int num_clocks; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num_clocks); jtag_add_runtest(num_clocks, TAP_IDLE); @@ -1079,7 +919,7 @@ COMMAND_HANDLER(handle_irscan_command) int i; struct scan_field *fields; struct jtag_tap *tap = NULL; - tap_state_t endstate; + enum tap_state endstate; if ((CMD_ARGC < 2) || (CMD_ARGC % 2)) return ERROR_COMMAND_SYNTAX_ERROR; @@ -1129,7 +969,7 @@ COMMAND_HANDLER(handle_irscan_command) if (retval != ERROR_OK) goto error_return; - int field_size = tap->ir_length; + unsigned int field_size = tap->ir_length; fields[i].num_bits = field_size; uint8_t *v = calloc(1, DIV_ROUND_UP(field_size, 8)); if (!v) { diff --git a/src/jtag/tcl.h b/src/jtag/tcl.h index d67c085e53..4e49e8579f 100644 --- a/src/jtag/tcl.h +++ b/src/jtag/tcl.h @@ -18,9 +18,9 @@ #ifndef OPENOCD_JTAG_TCL_H #define OPENOCD_JTAG_TCL_H -int jim_jtag_configure(Jim_Interp *interp, int argc, - Jim_Obj * const *argv); -int jim_jtag_tap_enabler(Jim_Interp *interp, int argc, - Jim_Obj * const *argv); +#include <helper/command.h> + +__COMMAND_HANDLER(handle_jtag_configure); +__COMMAND_HANDLER(handle_jtag_tap_enabler); #endif /* OPENOCD_JTAG_TCL_H */ diff --git a/src/main.c b/src/main.c index 3bc859a0bf..a36e6b55fa 100644 --- a/src/main.c +++ b/src/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/openocd.c b/src/openocd.c index 43c8523056..e63a9661a3 100644 --- a/src/openocd.c +++ b/src/openocd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -51,24 +51,23 @@ static const char openocd_startup_tcl[] = { }; /* Give scripts and TELNET a way to find out what version this is */ -static int jim_version_command(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handler_version_command) { - if (argc > 2) - return JIM_ERR; - const char *str = ""; - char *version_str; - version_str = OPENOCD_VERSION; + char *version_str = OPENOCD_VERSION; - if (argc == 2) - str = Jim_GetString(argv[1], NULL); + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 1) { + if (strcmp("git", CMD_ARGV[0])) + return ERROR_COMMAND_ARGUMENT_INVALID; - if (strcmp("git", str) == 0) version_str = GITVERSION; + } - Jim_SetResult(interp, Jim_NewStringObj(interp, version_str, -1)); + command_print(CMD, "%s", version_str); - return JIM_OK; + return ERROR_OK; } static int log_target_callback_event_handler(struct target *target, @@ -119,6 +118,8 @@ COMMAND_HANDLER(handle_init_command) initialized = 1; + bool save_poll_mask = jtag_poll_mask(); + retval = command_run_line(CMD_CTX, "target init"); if (retval != ERROR_OK) return ERROR_FAIL; @@ -166,8 +167,11 @@ COMMAND_HANDLER(handle_init_command) if (command_run_line(CMD_CTX, "tpiu init") != ERROR_OK) return ERROR_FAIL; + jtag_poll_unmask(save_poll_mask); + /* initialize telnet subsystem */ - gdb_target_add_all(all_targets); + if (gdb_target_add_all(all_targets) != ERROR_OK) + return ERROR_FAIL; target_register_event_callback(log_target_callback_event_handler, CMD_CTX); @@ -190,9 +194,10 @@ COMMAND_HANDLER(handle_add_script_search_dir_command) static const struct command_registration openocd_command_handlers[] = { { .name = "version", - .jim_handler = jim_version_command, + .handler = handler_version_command, .mode = COMMAND_ANY, .help = "show program version", + .usage = "[git]", }, { .name = "noinit", @@ -226,67 +231,25 @@ static int openocd_register_commands(struct command_context *cmd_ctx) return register_commands(cmd_ctx, NULL, openocd_command_handlers); } -/* - * TODO: to be removed after v0.12.0 - * workaround for syntax change of "expr" in jimtcl 0.81 - * replace "expr" with openocd version that prints the deprecated msg - */ -struct jim_scriptobj { - void *token; - Jim_Obj *filename_obj; - int len; - int subst_flags; - int in_use; - int firstline; - int linenr; - int missing; -}; - -static int jim_expr_command(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - if (argc == 2) - return Jim_EvalExpression(interp, argv[1]); - - if (argc > 2) { - Jim_Obj *obj = Jim_ConcatObj(interp, argc - 1, argv + 1); - Jim_IncrRefCount(obj); - const char *s = Jim_String(obj); - struct jim_scriptobj *script = Jim_GetIntRepPtr(interp->currentScriptObj); - if (interp->currentScriptObj == interp->emptyObj || - strcmp(interp->currentScriptObj->typePtr->name, "script") || - script->subst_flags || - script->filename_obj == interp->emptyObj) - LOG_WARNING("DEPRECATED! use 'expr { %s }' not 'expr %s'", s, s); - else - LOG_WARNING("DEPRECATED! (%s:%d) use 'expr { %s }' not 'expr %s'", - Jim_String(script->filename_obj), script->linenr, s, s); - int retcode = Jim_EvalExpression(interp, obj); - Jim_DecrRefCount(interp, obj); - return retcode; - } - - Jim_WrongNumArgs(interp, 1, argv, "expression ?...?"); - return JIM_ERR; -} +struct command_context *global_cmd_ctx; -static const struct command_registration expr_handler[] = { - { - .name = "expr", - .jim_handler = jim_expr_command, - .mode = COMMAND_ANY, - .help = "", - .usage = "", - }, - COMMAND_REGISTRATION_DONE +static int (* const command_registrants[])(struct command_context *cmd_ctx_value) = { + openocd_register_commands, + server_register_commands, + gdb_register_commands, + log_register_commands, + rtt_server_register_commands, + transport_register_commands, + adapter_register_commands, + target_register_commands, + flash_register_commands, + nand_register_commands, + pld_register_commands, + cti_register_commands, + dap_register_commands, + arm_tpiu_swo_register_commands, }; -static int workaround_for_jimtcl_expr(struct command_context *cmd_ctx) -{ - return register_commands(cmd_ctx, NULL, expr_handler); -} - -struct command_context *global_cmd_ctx; - static struct command_context *setup_command_handler(Jim_Interp *interp) { log_init(); @@ -295,26 +258,7 @@ static struct command_context *setup_command_handler(Jim_Interp *interp) struct command_context *cmd_ctx = command_init(openocd_startup_tcl, interp); /* register subsystem commands */ - typedef int (*command_registrant_t)(struct command_context *cmd_ctx_value); - static const command_registrant_t command_registrants[] = { - &workaround_for_jimtcl_expr, - &openocd_register_commands, - &server_register_commands, - &gdb_register_commands, - &log_register_commands, - &rtt_server_register_commands, - &transport_register_commands, - &adapter_register_commands, - &target_register_commands, - &flash_register_commands, - &nand_register_commands, - &pld_register_commands, - &cti_register_commands, - &dap_register_commands, - &arm_tpiu_swo_register_commands, - NULL - }; - for (unsigned i = 0; command_registrants[i]; i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(command_registrants); i++) { int retval = (*command_registrants[i])(cmd_ctx); if (retval != ERROR_OK) { command_done(cmd_ctx); @@ -431,6 +375,13 @@ int openocd_main(int argc, char *argv[]) log_exit(); +#if USE_GCOV + /* Always explicitly dump coverage data before terminating. + * Otherwise coverage would not be dumped when exit_on_signal occurs. */ + void __gcov_dump(void); + __gcov_dump(); +#endif + if (ret == ERROR_FAIL) return EXIT_FAILURE; else if (ret != ERROR_OK) diff --git a/src/pld/Makefile.am b/src/pld/Makefile.am index 14786afbfc..69e457c96a 100644 --- a/src/pld/Makefile.am +++ b/src/pld/Makefile.am @@ -2,9 +2,26 @@ noinst_LTLIBRARIES += %D%/libpld.la %C%_libpld_la_SOURCES = \ + %D%/certus.c \ + %D%/ecp2_3.c \ + %D%/ecp5.c \ + %D%/efinix.c \ + %D%/gatemate.c \ + %D%/gowin.c \ + %D%/intel.c \ + %D%/lattice.c \ + %D%/lattice_bit.c \ %D%/pld.c \ + %D%/raw_bit.c \ %D%/xilinx_bit.c \ %D%/virtex2.c \ + %D%/certus.h \ + %D%/ecp2_3.h \ + %D%/ecp5.h \ + %D%/lattice.h \ + %D%/lattice_bit.h \ + %D%/lattice_cmd.h \ %D%/pld.h \ + %D%/raw_bit.h \ %D%/xilinx_bit.h \ %D%/virtex2.h diff --git a/src/pld/certus.c b/src/pld/certus.c new file mode 100644 index 0000000000..ccb3feb90c --- /dev/null +++ b/src/pld/certus.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "certus.h" +#include "lattice.h" +#include "lattice_cmd.h" + +#define LSC_ENABLE_X 0x74 +#define LSC_REFRESH 0x79 +#define LSC_DEVICE_CTRL 0x7D + +int lattice_certus_read_status(struct jtag_tap *tap, uint64_t *status, uint64_t out) +{ + return lattice_read_u64_register(tap, LSC_READ_STATUS, status, out); +} + +int lattice_certus_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out) +{ + return lattice_read_u32_register(tap, READ_USERCODE, usercode, out, false); +} + +int lattice_certus_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode) +{ + LOG_ERROR("Not supported to write usercode on certus devices"); + return ERROR_FAIL; +} + +static int lattice_certus_enable_transparent_mode(struct jtag_tap *tap) +{ + struct scan_field field; + + int retval = lattice_set_instr(tap, LSC_ENABLE_X, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + uint8_t buffer = 0x0; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + + return jtag_execute_queue(); +} + +static int lattice_certus_erase_device(struct lattice_pld_device *lattice_device) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, LSC_DEVICE_CTRL, TAP_IRPAUSE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer = 8; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, LSC_DEVICE_CTRL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + buffer = 0; + field.num_bits = 8; + field.out_value = &buffer; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, ISC_ERASE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + buffer = 0; + field.num_bits = 8; + field.out_value = &buffer; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(100, TAP_IDLE); + jtag_add_sleep(5000); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + /* check done is cleared and fail is cleared */ + const uint64_t status_done_flag = 0x100; + const uint64_t status_fail_flag = 0x2000; + return lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_done_flag | status_fail_flag); +} + +static int lattice_certus_enable_programming(struct jtag_tap *tap) +{ + struct scan_field field; + + int retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + uint8_t buffer = 0; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + return jtag_execute_queue(); +} + +static int lattice_certus_init_address(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, LSC_INIT_ADDRESS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + return jtag_execute_queue(); +} + +static int lattice_certus_exit_programming_mode(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(100, TAP_IDLE); + return jtag_execute_queue(); +} + +static int lattice_certus_program_config_map(struct jtag_tap *tap, struct lattice_bit_file *bit_file) +{ + struct scan_field field; + + int retval = lattice_set_instr(tap, LSC_BITSTREAM_BURST, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + field.num_bits = (bit_file->raw_bit.length - bit_file->offset) * 8; + field.out_value = bit_file->raw_bit.data + bit_file->offset; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + + return jtag_execute_queue(); +} + +int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + /* check password protection is disabled */ + const uint64_t status_pwd_protection = 0x20000; + retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_pwd_protection); + if (retval != ERROR_OK) { + LOG_ERROR("Password protection is set"); + return retval; + } + + retval = lattice_certus_enable_transparent_mode(tap); + if (retval != ERROR_OK) + return retval; + + /* Check the SRAM Erase Lock */ + const uint64_t status_otp = 0x40; + retval = lattice_verify_status_register_u64(lattice_device, 0x0, status_otp, status_otp); + if (retval != ERROR_OK) { + LOG_ERROR("NV User Feature Sector OTP is Set"); + return retval; + } + + /* Check the SRAM Lock */ + const uint64_t status_write_protected = 0x400; + retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_write_protected); + if (retval != ERROR_OK) { + LOG_ERROR("NV User Feature Sector OTP is Set"); + return retval; + } + + retval = lattice_certus_enable_programming(tap); + if (retval != ERROR_OK) { + LOG_ERROR("failed to enable programming mode"); + return retval; + } + + retval = lattice_certus_erase_device(lattice_device); + if (retval != ERROR_OK) { + LOG_ERROR("erasing device failed"); + return retval; + } + + retval = lattice_certus_init_address(tap); + if (retval != ERROR_OK) + return retval; + + retval = lattice_certus_program_config_map(tap, bit_file); + if (retval != ERROR_OK) + return retval; + const uint32_t expected = 0x100; // done + const uint32_t mask = expected | + 0x3000 | // Busy Flag and Fail Flag + 0xf000000; // BSE Error + retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x100, mask); + if (retval != ERROR_OK) + return retval; + + return lattice_certus_exit_programming_mode(tap); +} + +int lattice_certus_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == PROGRAM_SPI) + return ERROR_OK; + + // erase configuration + int retval = lattice_preload(pld_device_info); + if (retval != ERROR_OK) + return retval; + + retval = lattice_certus_enable_programming(tap); + if (retval != ERROR_OK) + return retval; + + retval = lattice_certus_erase_device(pld_device_info); + if (retval != ERROR_OK) { + LOG_ERROR("erasing device failed"); + return retval; + } + + retval = lattice_certus_exit_programming_mode(tap); + if (retval != ERROR_OK) + return retval; + + // connect jtag to spi pins + retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer[2] = {0xfe, 0x68}; + field.num_bits = 16; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + + return jtag_execute_queue(); +} + +int lattice_certus_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + /* Connecting it again takes way too long to do it multiple times for writing + a bitstream (ca. 0.4s each access). + We just leave it connected since SCS will not be active when not in shift_dr state. + So there is no need to change instruction, just make sure we are not in shift dr state. */ + jtag_add_runtest(2, TAP_IDLE); + return jtag_execute_queue(); +} + +int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits) +{ + if (!pld_device_info) + return ERROR_FAIL; + + *facing_read_bits = 0; + + return ERROR_OK; +} + +int lattice_certus_refresh(struct lattice_pld_device *lattice_device) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(200000); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(100, TAP_IDLE); + jtag_add_sleep(1000); + + return jtag_execute_queue(); +} diff --git a/src/pld/certus.h b/src/pld/certus.h new file mode 100644 index 0000000000..0fbfdef45c --- /dev/null +++ b/src/pld/certus.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_CERTUS_H +#define OPENOCD_PLD_CERTUS_H + +#include "lattice.h" + +int lattice_certus_read_status(struct jtag_tap *tap, uint64_t *status, uint64_t out); +int lattice_certus_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out); +int lattice_certus_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode); +int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file); +int lattice_certus_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info); +int lattice_certus_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info); +int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits); +int lattice_certus_refresh(struct lattice_pld_device *lattice_device); + +#endif /* OPENOCD_PLD_CERTUS_H */ diff --git a/src/pld/ecp2_3.c b/src/pld/ecp2_3.c new file mode 100644 index 0000000000..5dfea9a277 --- /dev/null +++ b/src/pld/ecp2_3.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "ecp2_3.h" +#include "lattice.h" + +#define LSCC_REFRESH 0x23 +#define ISC_ENABLE 0x15 +#define LSCC_RESET_ADDRESS 0x21 +#define ISC_PROGRAM_USERCODE 0x1A +#define ISC_ERASE 0x03 +#define READ_USERCODE 0x17 +#define ISC_DISABLE 0x1E +#define LSCC_READ_STATUS 0x53 +#define LSCC_BITSTREAM_BURST 0x02 +#define PROGRAM_SPI 0x3A + +#define STATUS_DONE_BIT 0x00020000 +#define STATUS_ERROR_BITS_ECP2 0x00040003 +#define STATUS_ERROR_BITS_ECP3 0x00040007 +#define REGISTER_ALL_BITS_1 0xffffffff +#define REGISTER_ALL_BITS_0 0x00000000 + +int lattice_ecp2_3_read_status(struct jtag_tap *tap, uint32_t *status, uint32_t out, bool do_idle) +{ + return lattice_read_u32_register(tap, LSCC_READ_STATUS, status, out, do_idle); +} + +int lattice_ecp2_3_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out) +{ + return lattice_read_u32_register(tap, READ_USERCODE, usercode, out, false); +} + +int lattice_ecp2_3_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(20000); + + retval = lattice_set_instr(tap, ISC_PROGRAM_USERCODE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer[4]; + h_u32_to_le(buffer, usercode); + field.num_bits = 32; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(2000); + + retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(200000); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + return lattice_verify_usercode(lattice_device, 0x0, usercode, REGISTER_ALL_BITS_1); +} + +static int lattice_ecp2_3_erase_device(struct lattice_pld_device *lattice_device) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + /* program user code with all bits set */ + int retval = lattice_set_instr(tap, ISC_PROGRAM_USERCODE, TAP_IRPAUSE); + if (retval != ERROR_OK) + return retval; + struct scan_field field; + uint8_t buffer[4] = {0xff, 0xff, 0xff, 0xff}; + field.num_bits = 32; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(2000); + + /* verify every bit is set */ + const uint32_t out = REGISTER_ALL_BITS_1; + const uint32_t mask = REGISTER_ALL_BITS_1; + const uint32_t expected_pre = REGISTER_ALL_BITS_1; + retval = lattice_verify_usercode(lattice_device, out, expected_pre, mask); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, ISC_ERASE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + if (lattice_device->family == LATTICE_ECP2) + jtag_add_sleep(100000); + else + jtag_add_sleep(2000000); + + retval = lattice_set_instr(tap, LSCC_RESET_ADDRESS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(2000); + + /* after erasing check all bits in user register are cleared */ + const uint32_t expected_post = REGISTER_ALL_BITS_0; + return lattice_verify_usercode(lattice_device, out, expected_post, mask); +} + +static int lattice_ecp2_3_program_config_map(struct lattice_pld_device *lattice_device, + struct lattice_bit_file *bit_file) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, LSCC_RESET_ADDRESS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(2000); + + struct scan_field field; + retval = lattice_set_instr(tap, LSCC_BITSTREAM_BURST, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + field.num_bits = (bit_file->raw_bit.length - bit_file->offset) * 8; + field.out_value = bit_file->raw_bit.data + bit_file->offset; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(256, TAP_IDLE); + jtag_add_sleep(2000); + return jtag_execute_queue(); +} + +static int lattice_ecp2_3_exit_programming_mode(struct lattice_pld_device *lattice_device) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(200000); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(100, TAP_IDLE); + jtag_add_sleep(1000); + return jtag_execute_queue(); +} + +int lattice_ecp2_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + /* Enable the programming mode */ + retval = lattice_set_instr(tap, LSCC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(20000); + + /* Erase the device */ + retval = lattice_ecp2_3_erase_device(lattice_device); + if (retval != ERROR_OK) + return retval; + + /* Program Fuse Map */ + retval = lattice_ecp2_3_program_config_map(lattice_device, bit_file); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp2_3_exit_programming_mode(lattice_device); + if (retval != ERROR_OK) + return retval; + + const uint32_t out = REGISTER_ALL_BITS_1; + const uint32_t mask = STATUS_DONE_BIT | STATUS_ERROR_BITS_ECP2; + const uint32_t expected = STATUS_DONE_BIT; + return lattice_verify_status_register_u32(lattice_device, out, expected, mask, false); +} + +int lattice_ecp3_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + /* Program Bscan register */ + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + /* Enable the programming mode */ + retval = lattice_set_instr(tap, LSCC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(500000); + retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(20000); + + retval = lattice_ecp2_3_erase_device(lattice_device); + if (retval != ERROR_OK) + return retval; + + /* Program Fuse Map */ + retval = lattice_ecp2_3_program_config_map(lattice_device, bit_file); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp2_3_exit_programming_mode(lattice_device); + if (retval != ERROR_OK) + return retval; + + const uint32_t out = REGISTER_ALL_BITS_1; + const uint32_t mask = STATUS_DONE_BIT | STATUS_ERROR_BITS_ECP3; + const uint32_t expected = STATUS_DONE_BIT; + return lattice_verify_status_register_u32(lattice_device, out, expected, mask, false); +} + +int lattice_ecp2_3_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + // erase configuration + int retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = lattice_set_instr(tap, ISC_ERASE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + // connect jtag to spi pins + retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + return jtag_execute_queue(); +} + +int lattice_ecp2_3_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + return jtag_execute_queue(); +} + +int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits) +{ + if (!pld_device_info) + return ERROR_FAIL; + + *facing_read_bits = 1; + + return ERROR_OK; +} + +int lattice_ecp2_3_refresh(struct lattice_pld_device *lattice_device) +{ + if (!lattice_device || !lattice_device->tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(lattice_device->tap, LSCC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + return jtag_execute_queue(); +} diff --git a/src/pld/ecp2_3.h b/src/pld/ecp2_3.h new file mode 100644 index 0000000000..d3f7464e12 --- /dev/null +++ b/src/pld/ecp2_3.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_ECP2_3_H +#define OPENOCD_PLD_ECP2_3_H + +#include "lattice.h" + +int lattice_ecp2_3_read_status(struct jtag_tap *tap, uint32_t *status, uint32_t out, bool do_idle); +int lattice_ecp2_3_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out); +int lattice_ecp2_3_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode); +int lattice_ecp2_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file); +int lattice_ecp3_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file); +int lattice_ecp2_3_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info); +int lattice_ecp2_3_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info); +int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits); +int lattice_ecp2_3_refresh(struct lattice_pld_device *lattice_device); + +#endif /* OPENOCD_PLD_ECP2_3_H */ diff --git a/src/pld/ecp5.c b/src/pld/ecp5.c new file mode 100644 index 0000000000..f8ba33eaff --- /dev/null +++ b/src/pld/ecp5.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "ecp5.h" +#include "lattice.h" +#include "lattice_cmd.h" + +#define ISC_PROGRAM_USERCODE 0xC2 + +#define STATUS_DONE_BIT 0x00000100 +#define STATUS_ERROR_BITS 0x00020040 +#define STATUS_FEA_OTP 0x00004000 +#define STATUS_FAIL_FLAG 0x00002000 +#define STATUS_BUSY_FLAG 0x00001000 +#define REGISTER_ALL_BITS_1 0xffffffff + +int lattice_ecp5_read_status(struct jtag_tap *tap, uint32_t *status, uint32_t out, bool do_idle) +{ + return lattice_read_u32_register(tap, LSC_READ_STATUS, status, out, do_idle); +} + +int lattice_ecp5_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out) +{ + return lattice_read_u32_register(tap, READ_USERCODE, usercode, out, true); +} + +int lattice_ecp5_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(20000); + + retval = lattice_set_instr(tap, ISC_PROGRAM_USERCODE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + uint8_t buffer[4]; + struct scan_field field; + h_u32_to_le(buffer, usercode); + field.num_bits = 32; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(2000); + + retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(5, TAP_IDLE); + jtag_add_sleep(200000); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + return lattice_verify_usercode(lattice_device, 0x0, usercode, REGISTER_ALL_BITS_1); +} + +static int lattice_ecp5_enable_sram_programming(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer = 0x0; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(10000); + + return jtag_execute_queue(); +} + +static int lattice_ecp5_erase_sram(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, ISC_ERASE, TAP_IRPAUSE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer = 1; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(200000); + return jtag_execute_queue(); +} + +static int lattice_ecp5_init_address(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, LSC_INIT_ADDRESS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer = 1; + field.num_bits = 8; + field.out_value = &buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(10000); + return jtag_execute_queue(); +} + +static int lattice_ecp5_program_config_map(struct jtag_tap *tap, struct lattice_bit_file *bit_file) +{ + int retval = lattice_set_instr(tap, LSC_BITSTREAM_BURST, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(10000); + + struct scan_field field; + field.num_bits = (bit_file->raw_bit.length - bit_file->offset) * 8; + field.out_value = bit_file->raw_bit.data + bit_file->offset; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(100, TAP_IDLE); + jtag_add_sleep(10000); + + return jtag_execute_queue(); +} + +static int lattice_ecp5_exit_programming_mode(struct jtag_tap *tap) +{ + int retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(200000); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(1000); + return jtag_execute_queue(); +} + +int lattice_ecp5_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_enable_sram_programming(tap); + if (retval != ERROR_OK) + return retval; + + const uint32_t out = 0x0; + const uint32_t expected1 = 0x0; + const uint32_t mask1 = STATUS_ERROR_BITS | STATUS_FEA_OTP; + retval = lattice_verify_status_register_u32(lattice_device, out, expected1, mask1, true); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_erase_sram(tap); + if (retval != ERROR_OK) + return retval; + + const uint32_t mask2 = STATUS_FAIL_FLAG | STATUS_BUSY_FLAG; + retval = lattice_verify_status_register_u32(lattice_device, out, expected1, mask2, false); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_init_address(tap); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_program_config_map(tap, bit_file); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_exit_programming_mode(tap); + if (retval != ERROR_OK) + return retval; + + const uint32_t expected2 = STATUS_DONE_BIT; + const uint32_t mask3 = STATUS_DONE_BIT | STATUS_FAIL_FLAG; + return lattice_verify_status_register_u32(lattice_device, out, expected2, mask3, false); +} + +int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == PROGRAM_SPI) + return ERROR_OK; + + // erase configuration + int retval = lattice_preload(pld_device_info); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_enable_sram_programming(tap); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_erase_sram(tap); + if (retval != ERROR_OK) + return retval; + + retval = lattice_ecp5_exit_programming_mode(tap); + if (retval != ERROR_OK) + return retval; + + // connect jtag to spi pins + retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + + struct scan_field field; + uint8_t buffer[2] = {0xfe, 0x68}; + field.num_bits = 16; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + + return jtag_execute_queue(); +} + +int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info) +{ + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + /* Connecting it again takes way too long to do it multiple times for writing + a bitstream (ca. 0.4s each access). + We just leave it connected since SCS will not be active when not in shift_dr state. + So there is no need to change instruction, just make sure we are not in shift dr state. */ + jtag_add_runtest(2, TAP_IDLE); + return jtag_execute_queue(); +} + +int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits) +{ + if (!pld_device_info) + return ERROR_FAIL; + + *facing_read_bits = 0; + + return ERROR_OK; +} + +int lattice_ecp5_refresh(struct lattice_pld_device *lattice_device) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + int retval = lattice_preload(lattice_device); + if (retval != ERROR_OK) + return retval; + + retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(200000); + retval = lattice_set_instr(tap, BYPASS, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(100, TAP_IDLE); + jtag_add_sleep(1000); + + return jtag_execute_queue(); +} diff --git a/src/pld/ecp5.h b/src/pld/ecp5.h new file mode 100644 index 0000000000..975678ece3 --- /dev/null +++ b/src/pld/ecp5.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_ECP5_H +#define OPENOCD_PLD_ECP5_H + +#include "lattice.h" + +int lattice_ecp5_read_status(struct jtag_tap *tap, uint32_t *status, uint32_t out, bool do_idle); +int lattice_ecp5_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out); +int lattice_ecp5_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode); +int lattice_ecp5_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file); +int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info); +int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info); +int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits); +int lattice_ecp5_refresh(struct lattice_pld_device *lattice_device); + +#endif /* OPENOCD_PLD_ECP5_H */ diff --git a/src/pld/efinix.c b/src/pld/efinix.c new file mode 100644 index 0000000000..b6e5f9e477 --- /dev/null +++ b/src/pld/efinix.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <jtag/jtag.h> + +#include "pld.h" +#include "raw_bit.h" + +#define PROGRAM 0x4 +#define ENTERUSER 0x7 +#define USER1 0x8 +#define USER2 0x9 +#define USER3 0xa +#define USER4 0xb + +enum efinix_family_e { + EFINIX_TRION, + EFINIX_TITANIUM, + EFINIX_UNKNOWN +}; + +#define TRAILING_ZEROS 4000 +#define RUNTEST_START_CYCLES 100 +#define RUNTEST_FINISH_CYCLES 100 + +struct efinix_device { + uint32_t idcode; + int num_user; +}; + +struct efinix_pld_device { + struct jtag_tap *tap; + enum efinix_family_e family; +}; + +static int efinix_read_bit_file(struct raw_bit_file *bit_file, const char *filename) +{ + FILE *input_file = fopen(filename, "r"); + if (!input_file) { + LOG_ERROR("couldn't open %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + fseek(input_file, 0, SEEK_END); + long length = ftell(input_file); + fseek(input_file, 0, SEEK_SET); + + if (length < 0 || ((length % 3))) { + fclose(input_file); + LOG_ERROR("Failed to get length from file %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + bit_file->length = DIV_ROUND_UP(length, 3); + + bit_file->data = malloc(bit_file->length); + if (!bit_file->data) { + fclose(input_file); + LOG_ERROR("Out of memory"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + bool end_detected = false; + char buffer[3]; + for (size_t idx = 0; !end_detected && idx < bit_file->length; ++idx) { + size_t read_count = fread(buffer, sizeof(char), 3, input_file); + end_detected = feof(input_file); + if ((read_count == 3 && buffer[2] != '\n') || + (read_count != 3 && !end_detected) || + (read_count != 2 && end_detected)) { + fclose(input_file); + free(bit_file->data); + bit_file->data = NULL; + LOG_ERROR("unexpected line length"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (!isxdigit(buffer[0]) || !isxdigit(buffer[1])) { + fclose(input_file); + free(bit_file->data); + bit_file->data = NULL; + LOG_ERROR("unexpected char in hex string"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + unhexify(&bit_file->data[idx], buffer, 2); + } + + fclose(input_file); + + return ERROR_OK; +} + +static int efinix_read_file(struct raw_bit_file *bit_file, const char *filename) +{ + if (!filename || !bit_file) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* check if binary .bin or ascii .bit/.hex */ + const char *file_ending_pos = strrchr(filename, '.'); + if (!file_ending_pos) { + LOG_ERROR("Unable to detect filename suffix"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (strcasecmp(file_ending_pos, ".bin") == 0) { + return cpld_read_raw_bit_file(bit_file, filename); + } else if ((strcasecmp(file_ending_pos, ".bit") == 0) || + (strcasecmp(file_ending_pos, ".hex") == 0)) { + return efinix_read_bit_file(bit_file, filename); + } + + LOG_ERROR("Unable to detect filetype"); + return ERROR_PLD_FILE_LOAD_FAILED; +} + +static int efinix_set_instr(struct jtag_tap *tap, uint8_t new_instr) +{ + struct scan_field field; + field.num_bits = tap->ir_length; + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); + field.in_value = NULL; + jtag_add_ir_scan(tap, &field, TAP_IDLE); + free(t); + return ERROR_OK; +} + +static int efinix_load(struct pld_device *pld_device, const char *filename) +{ + struct raw_bit_file bit_file; + struct scan_field field[2]; + + if (!pld_device || !pld_device->driver_priv) + return ERROR_FAIL; + + struct efinix_pld_device *efinix_info = pld_device->driver_priv; + if (!efinix_info || !efinix_info->tap) + return ERROR_FAIL; + struct jtag_tap *tap = efinix_info->tap; + + jtag_add_tlr(); + + int retval = efinix_set_instr(tap, PROGRAM); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(RUNTEST_START_CYCLES, TAP_IDLE); + retval = efinix_set_instr(tap, PROGRAM); /* fix for T20 */ + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + retval = efinix_read_file(&bit_file, filename); + if (retval != ERROR_OK) + return retval; + + for (size_t i = 0; i < bit_file.length; i++) + bit_file.data[i] = flip_u32(bit_file.data[i], 8); + + /* shift in the bitstream */ + field[0].num_bits = bit_file.length * 8; + field[0].out_value = bit_file.data; + field[0].in_value = NULL; + + /* followed by zeros */ + field[1].num_bits = TRAILING_ZEROS; + uint8_t *buf = calloc(TRAILING_ZEROS / 8, 1); + if (!buf) { + free(bit_file.data); + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field[1].out_value = buf; + field[1].in_value = NULL; + + jtag_add_dr_scan(tap, 2, field, TAP_DRPAUSE); + retval = jtag_execute_queue(); + free(bit_file.data); + free(buf); + if (retval != ERROR_OK) + return retval; + + retval = efinix_set_instr(tap, ENTERUSER); + if (retval != ERROR_OK) + return retval; + + /* entering RUN/TEST for 100 cycles */ + jtag_add_runtest(RUNTEST_FINISH_CYCLES, TAP_IDLE); + retval = jtag_execute_queue(); + + return retval; +} + +static int efinix_get_ipdbg_hub(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub) +{ + if (!pld_device) + return ERROR_FAIL; + + struct efinix_pld_device *pld_device_info = pld_device->driver_priv; + + if (!pld_device_info || !pld_device_info->tap) + return ERROR_FAIL; + + hub->tap = pld_device_info->tap; + + if (pld_device_info->family == EFINIX_UNKNOWN) { + LOG_ERROR("family unknown, please specify for 'pld create'"); + return ERROR_FAIL; + } + int num_user = 2; /* trion */ + if (pld_device_info->family == EFINIX_TITANIUM) + num_user = 4; + + if (user_num > num_user) { + LOG_ERROR("Devices has only user register 1 to %d", num_user); + return ERROR_FAIL; + } + + switch (user_num) { + case 1: + hub->user_ir_code = USER1; + break; + case 2: + hub->user_ir_code = USER2; + break; + case 3: + hub->user_ir_code = USER3; + break; + case 4: + hub->user_ir_code = USER4; + break; + default: + LOG_ERROR("efinix devices only have user register 1 to %d", num_user); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int efinix_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir) +{ + *ir = USER1; + return ERROR_OK; +} + +PLD_CREATE_COMMAND_HANDLER(efinix_pld_create_command) +{ + if (CMD_ARGC != 4 && CMD_ARGC != 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); + if (!tap) { + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; + } + + enum efinix_family_e family = EFINIX_UNKNOWN; + if (CMD_ARGC == 6) { + if (strcmp(CMD_ARGV[4], "-family") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[5], "trion") == 0) { + family = EFINIX_TRION; + } else if (strcmp(CMD_ARGV[5], "titanium") == 0) { + family = EFINIX_TITANIUM; + } else { + command_print(CMD, "unknown family"); + return ERROR_FAIL; + } + } + + struct efinix_pld_device *efinix_info = malloc(sizeof(struct efinix_pld_device)); + if (!efinix_info) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + efinix_info->tap = tap; + efinix_info->family = family; + + pld->driver_priv = efinix_info; + + return ERROR_OK; +} + +struct pld_driver efinix_pld = { + .name = "efinix", + .pld_create_command = &efinix_pld_create_command, + .load = &efinix_load, + .get_ipdbg_hub = efinix_get_ipdbg_hub, + .get_jtagspi_userircode = efinix_get_jtagspi_userircode, +}; diff --git a/src/pld/gatemate.c b/src/pld/gatemate.c new file mode 100644 index 0000000000..f35b39ad21 --- /dev/null +++ b/src/pld/gatemate.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <jtag/jtag.h> +#include <jtag/adapter.h> +#include "pld.h" +#include "raw_bit.h" + +#define JTAG_CONFIGURE 0x06 +#define JTAG_SPI_BYPASS 0x05 +#define BYPASS 0x3F + +struct gatemate_pld_device { + struct jtag_tap *tap; +}; + +struct gatemate_bit_file { + struct raw_bit_file raw_file; + size_t capacity; +}; + +static int gatemate_add_byte_to_bitfile(struct gatemate_bit_file *bit_file, uint8_t byte) +{ + const size_t chunk_size = 8192; + if (bit_file->raw_file.length + 1 > bit_file->capacity) { + uint8_t *buffer; + if (bit_file->raw_file.data) + buffer = realloc(bit_file->raw_file.data, bit_file->capacity + chunk_size); + else + buffer = malloc(chunk_size); + if (!buffer) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + bit_file->raw_file.data = buffer; + bit_file->capacity += chunk_size; + } + + bit_file->raw_file.data[bit_file->raw_file.length++] = byte; + + return ERROR_OK; +} + +static int gatemate_read_cfg_line(struct gatemate_bit_file *bit_file, const char *line_buffer, size_t nread) +{ + for (size_t idx = 0; idx < nread; ++idx) { + if (line_buffer[idx] == ' ') { + continue; + } else if (line_buffer[idx] == 0) { + break; + } else if (idx + 1 < nread) { + if (isxdigit(line_buffer[idx]) && isxdigit(line_buffer[idx + 1])) { + uint8_t byte; + unhexify(&byte, line_buffer + idx, 2); + int retval = gatemate_add_byte_to_bitfile(bit_file, byte); + if (retval != ERROR_OK) + return retval; + } else if (line_buffer[idx] == '/' && line_buffer[idx + 1] == '/') { + break; + } + ++idx; + } else { + LOG_ERROR("parsing failed"); + return ERROR_FAIL; + } + } + return ERROR_OK; +} + +static int gatemate_getline(char **buffer, size_t *buf_size, FILE *input_file) +{ + const size_t chunk_size = 32; + if (!*buffer) + *buf_size = 0; + + size_t read = 0; + do { + if (read + 1 > *buf_size) { + char *new_buffer; + if (*buffer) + new_buffer = realloc(*buffer, *buf_size + chunk_size); + else + new_buffer = malloc(chunk_size); + if (!new_buffer) { + LOG_ERROR("Out of memory"); + return -1; + } + *buffer = new_buffer; + *buf_size += chunk_size; + } + + int c = fgetc(input_file); + if ((c == EOF && read) || (char)c == '\n') { + (*buffer)[read++] = 0; + return read; + } else if (c == EOF) { + return -1; + } + + (*buffer)[read++] = (char)c; + } while (1); + + return -1; +} + +static int gatemate_read_cfg_file(struct gatemate_bit_file *bit_file, const char *filename) +{ + FILE *input_file = fopen(filename, "r"); + + if (!input_file) { + LOG_ERROR("Couldn't open %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + int retval = ERROR_OK; + char *line_buffer = NULL; + size_t buffer_length = 0; + int nread; + while (((nread = gatemate_getline(&line_buffer, &buffer_length, input_file)) != -1) && (retval == ERROR_OK)) + retval = gatemate_read_cfg_line(bit_file, line_buffer, (size_t)nread); + + if (line_buffer) + free(line_buffer); + + fclose(input_file); + if (retval != ERROR_OK) + free(bit_file->raw_file.data); + return retval; +} + +static int gatemate_read_file(struct gatemate_bit_file *bit_file, const char *filename) +{ + memset(bit_file, 0, sizeof(struct gatemate_bit_file)); + + if (!filename || !bit_file) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* check if binary .bit or ascii .cfg */ + const char *file_suffix_pos = strrchr(filename, '.'); + if (!file_suffix_pos) { + LOG_ERROR("Unable to detect filename suffix"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (strcasecmp(file_suffix_pos, ".bit") == 0) + return cpld_read_raw_bit_file(&bit_file->raw_file, filename); + else if (strcasecmp(file_suffix_pos, ".cfg") == 0) + return gatemate_read_cfg_file(bit_file, filename); + + LOG_ERROR("Filetype not supported, expecting .bit or .cfg file"); + return ERROR_PLD_FILE_LOAD_FAILED; +} + +static int gatemate_set_instr(struct jtag_tap *tap, uint8_t new_instr) +{ + struct scan_field field; + field.num_bits = tap->ir_length; + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); + field.in_value = NULL; + jtag_add_ir_scan(tap, &field, TAP_IDLE); + jtag_add_runtest(3, TAP_IDLE); + free(t); + return ERROR_OK; +} + +static int gatemate_load(struct pld_device *pld_device, const char *filename) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gatemate_pld_device *gatemate_info = pld_device->driver_priv; + + if (!gatemate_info || !gatemate_info->tap) + return ERROR_FAIL; + struct jtag_tap *tap = gatemate_info->tap; + + struct gatemate_bit_file bit_file; + int retval = gatemate_read_file(&bit_file, filename); + if (retval != ERROR_OK) + return retval; + + retval = gatemate_set_instr(tap, JTAG_CONFIGURE); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + struct scan_field field; + field.num_bits = bit_file.raw_file.length * 8; + field.out_value = bit_file.raw_file.data; + field.in_value = NULL; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + + retval = jtag_execute_queue(); + free(bit_file.raw_file.data); + + return retval; +} + +static int gatemate_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction) +{ + *has_instruction = true; + return ERROR_OK; +} + +static int gatemate_connect_spi_to_jtag(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gatemate_pld_device *pld_device_info = pld_device->driver_priv; + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == JTAG_SPI_BYPASS) + return ERROR_OK; + + gatemate_set_instr(tap, JTAG_SPI_BYPASS); + + return jtag_execute_queue(); +} + +static int gatemate_disconnect_spi_from_jtag(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gatemate_pld_device *pld_device_info = pld_device->driver_priv; + if (!pld_device_info) + return ERROR_FAIL; + + struct jtag_tap *tap = pld_device_info->tap; + if (!tap) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != JTAG_SPI_BYPASS) + return ERROR_OK; + + gatemate_set_instr(tap, BYPASS); + + return jtag_execute_queue(); +} + +static int gatemate_get_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits, + unsigned int *trailing_write_bits) +{ + if (!pld_device) + return ERROR_FAIL; + + *facing_read_bits = 1; + *trailing_write_bits = 1; + + return ERROR_OK; +} + +PLD_CREATE_COMMAND_HANDLER(gatemate_pld_create_command) +{ + if (CMD_ARGC != 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); + if (!tap) { + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; + } + + struct gatemate_pld_device *gatemate_info = malloc(sizeof(struct gatemate_pld_device)); + if (!gatemate_info) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + gatemate_info->tap = tap; + + pld->driver_priv = gatemate_info; + + return ERROR_OK; +} + +struct pld_driver gatemate_pld = { + .name = "gatemate", + .pld_create_command = &gatemate_pld_create_command, + .load = &gatemate_load, + .has_jtagspi_instruction = gatemate_has_jtagspi_instruction, + .connect_spi_to_jtag = gatemate_connect_spi_to_jtag, + .disconnect_spi_from_jtag = gatemate_disconnect_spi_from_jtag, + .get_stuff_bits = gatemate_get_stuff_bits, +}; diff --git a/src/pld/gowin.c b/src/pld/gowin.c new file mode 100644 index 0000000000..bbc2fe15f6 --- /dev/null +++ b/src/pld/gowin.c @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <jtag/jtag.h> +#include <jtag/adapter.h> +#include <helper/bits.h> +#include "pld.h" +#include "raw_bit.h" + +#define NO_OP 0x02 +#define ERASE_SRAM 0x05 +#define SRAM_ERASE_DONE 0x09 +#define IDCODE 0x11 +#define ADDRESS_INITIALIZATION 0x12 +#define READ_USERCODE 0x13 +#define CONFIG_ENABLE 0x15 +#define TRANSFER_CONFIGURATION_DATA 0x17 +#define CONFIG_DISABLE 0x3A +#define RELOAD 0x3C +#define STATUS_REGISTER 0x41 +#define ERASE_FLASH 0x75 +#define ENABLE_2ND_FLASH 0x78 + +#define USER1 0x42 +#define USER2 0x43 + +#define STAUS_MASK_MEMORY_ERASE BIT(5) +#define STAUS_MASK_SYSTEM_EDIT_MODE BIT(7) + +struct gowin_pld_device { + struct jtag_tap *tap; +}; + +struct gowin_bit_file { + struct raw_bit_file raw_file; + size_t capacity; + uint32_t id; + uint16_t stored_checksum; + int compressed; + int crc_en; + uint16_t checksum; + uint8_t replace8x; + uint8_t replace4x; + uint8_t replace2x; +}; + +static uint64_t gowin_read_fs_file_bitsequence(const char *bits, int length) +{ + uint64_t res = 0; + for (int i = 0; i < length; i++) + res = (res << 1) | (*bits++ == '1' ? 1 : 0); + return res; +} + +static int gowin_add_byte_to_bit_file(struct gowin_bit_file *bit_file, uint8_t byte) +{ + if (bit_file->raw_file.length + 1 > bit_file->capacity) { + uint8_t *buffer; + if (bit_file->raw_file.data) + buffer = realloc(bit_file->raw_file.data, bit_file->capacity + 8192); + else + buffer = malloc(8192); + if (!buffer) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + bit_file->raw_file.data = buffer; + bit_file->capacity += 8192; + } + + bit_file->raw_file.data[bit_file->raw_file.length++] = byte; + + return ERROR_OK; +} + +static int gowin_read_fs_file_header(struct gowin_bit_file *bit_file, FILE *stream) +{ + if (!bit_file) + return ERROR_FAIL; + + int end_of_header = 0; + while (!end_of_header) { + char buffer[256]; + char *line = fgets(buffer, 256, stream); + if (!line || feof(stream) || ferror(stream)) + return ERROR_FAIL; + + if (line[0] == '/') + continue; + + size_t line_length = strlen(line); + if (line[line_length - 1] != '\n') + return ERROR_FAIL; + line_length--; + + for (unsigned int i = 0; i < line_length; i += 8) { + uint8_t byte = gowin_read_fs_file_bitsequence(line + i, 8); + int retval = gowin_add_byte_to_bit_file(bit_file, byte); + if (retval != ERROR_OK) + return retval; + } + + uint8_t key = gowin_read_fs_file_bitsequence(line, 8); + line += 8; + uint64_t value = gowin_read_fs_file_bitsequence(line, line_length - 8); + + if (key == 0x06) { + bit_file->id = value & 0xffffffff; + } else if (key == 0x3B) { + end_of_header = 1; + bit_file->crc_en = (value & BIT(23)) ? 1 : 0; + } + } + + return ERROR_OK; +} + +static int gowin_read_fs_file(struct gowin_bit_file *bit_file, const char *filename) +{ + FILE *input_file = fopen(filename, "r"); + + if (!input_file) { + LOG_ERROR("Couldn't open %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + int retval = gowin_read_fs_file_header(bit_file, input_file); + if (retval != ERROR_OK) { + free(bit_file->raw_file.data); + fclose(input_file); + return retval; + } + + char digits_buffer[9]; /* 8 + 1 trailing zero */ + do { + char *digits = fgets(digits_buffer, 9, input_file); + if (feof(input_file)) + break; + if (!digits || ferror(input_file)) { + free(bit_file->raw_file.data); + fclose(input_file); + return ERROR_FAIL; + } + if (digits[0] == '\n') + continue; + + if (strlen(digits) != 8) { + free(bit_file->raw_file.data); + fclose(input_file); + return ERROR_FAIL; + } + uint8_t byte = gowin_read_fs_file_bitsequence(digits, 8); + retval = gowin_add_byte_to_bit_file(bit_file, byte); + if (retval != ERROR_OK) { + free(bit_file->raw_file.data); + fclose(input_file); + return ERROR_FAIL; + } + } while (1); + + fclose(input_file); + return ERROR_OK; +} + +static int gowin_read_file(struct gowin_bit_file *bit_file, const char *filename, bool *is_fs) +{ + memset(bit_file, 0, sizeof(struct gowin_bit_file)); + + if (!filename || !bit_file) + return ERROR_COMMAND_SYNTAX_ERROR; + + const char *file_suffix_pos = strrchr(filename, '.'); + if (!file_suffix_pos) { + LOG_ERROR("Unable to detect filename suffix"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + /* check if binary .bin or ascii .fs */ + if (strcasecmp(file_suffix_pos, ".bin") == 0) { + *is_fs = false; + return cpld_read_raw_bit_file(&bit_file->raw_file, filename); + } else if (strcasecmp(file_suffix_pos, ".fs") == 0) { + *is_fs = true; + return gowin_read_fs_file(bit_file, filename); + } + + LOG_ERROR("Filetype not supported, expecting .fs or .bin file"); + return ERROR_PLD_FILE_LOAD_FAILED; +} + +static int gowin_set_instr(struct jtag_tap *tap, uint8_t new_instr) +{ + struct scan_field field; + field.num_bits = tap->ir_length; + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); + field.in_value = NULL; + jtag_add_ir_scan(tap, &field, TAP_IDLE); + jtag_add_runtest(3, TAP_IDLE); + free(t); + return ERROR_OK; +} + +static int gowin_read_register(struct jtag_tap *tap, uint32_t reg, uint32_t *result) +{ + struct scan_field field; + + int retval = gowin_set_instr(tap, reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + uint8_t buf[4] = {0}; + field.check_mask = NULL; + field.check_value = NULL; + field.num_bits = 32; + field.out_value = buf; + field.in_value = buf; + + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + retval = jtag_execute_queue(); + *result = le_to_h_u32(buf); + return retval; +} + +static int gowin_check_status_flag(struct jtag_tap *tap, uint32_t mask, uint32_t flag) +{ + uint32_t status = 0; + + int retries = 0; + do { + int retval = gowin_read_register(tap, STATUS_REGISTER, &status); + if (retval != ERROR_OK) + return retval; + if (retries++ == 100000) + return ERROR_FAIL; + } while ((status & mask) != flag); + + return ERROR_OK; +} + +static int gowin_enable_config(struct jtag_tap *tap) +{ + int retval = gowin_set_instr(tap, CONFIG_ENABLE); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + return gowin_check_status_flag(tap, STAUS_MASK_SYSTEM_EDIT_MODE, STAUS_MASK_SYSTEM_EDIT_MODE); +} + +static int gowin_disable_config(struct jtag_tap *tap) +{ + int retval = gowin_set_instr(tap, CONFIG_DISABLE); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + return gowin_check_status_flag(tap, STAUS_MASK_SYSTEM_EDIT_MODE, 0); +} + +static int gowin_reload(struct jtag_tap *tap) +{ + int retval = gowin_set_instr(tap, RELOAD); + if (retval != ERROR_OK) + return retval; + retval = gowin_set_instr(tap, NO_OP); + if (retval != ERROR_OK) + return retval; + return jtag_execute_queue(); +} + +static int gowin_runtest_idle(struct jtag_tap *tap, unsigned int frac_sec) +{ + int speed = adapter_get_speed_khz() * 1000; + int cycles = DIV_ROUND_UP(speed, frac_sec); + jtag_add_runtest(cycles, TAP_IDLE); + return jtag_execute_queue(); +} + +static int gowin_erase_sram(struct jtag_tap *tap, bool tx_erase_done) +{ + /* config is already enabled */ + int retval = gowin_set_instr(tap, ERASE_SRAM); + if (retval != ERROR_OK) + return retval; + retval = gowin_set_instr(tap, NO_OP); + if (retval != ERROR_OK) + return retval; + + /* Delay or Run Test 2~10ms */ + /* 10 ms is worst case for GW2A-55 */ + jtag_add_sleep(10000); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + retval = gowin_check_status_flag(tap, STAUS_MASK_MEMORY_ERASE, + STAUS_MASK_MEMORY_ERASE); + if (retval != ERROR_OK) + return retval; + + if (tx_erase_done) { + retval = gowin_set_instr(tap, SRAM_ERASE_DONE); + if (retval != ERROR_OK) + return retval; + retval = gowin_set_instr(tap, NO_OP); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + /* gen clock cycles in RUN/IDLE for 500us -> 1/500us = 2000/s */ + retval = gowin_runtest_idle(tap, 2000); + if (retval != ERROR_OK) + return retval; + } + + retval = gowin_set_instr(tap, NO_OP); + if (retval != ERROR_OK) + return retval; + return jtag_execute_queue(); +} + +static int gowin_load_to_sram(struct pld_device *pld_device, const char *filename) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gowin_pld_device *gowin_info = pld_device->driver_priv; + + if (!gowin_info || !gowin_info->tap) + return ERROR_FAIL; + struct jtag_tap *tap = gowin_info->tap; + + bool is_fs = false; + struct gowin_bit_file bit_file; + int retval = gowin_read_file(&bit_file, filename, &is_fs); + if (retval != ERROR_OK) + return retval; + + for (unsigned int i = 0; i < bit_file.raw_file.length; i++) + bit_file.raw_file.data[i] = flip_u32(bit_file.raw_file.data[i], 8); + + uint32_t id; + retval = gowin_read_register(tap, IDCODE, &id); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + if (is_fs && id != bit_file.id) { + free(bit_file.raw_file.data); + LOG_ERROR("Id on device (0x%8.8" PRIx32 ") and id in bit-stream (0x%8.8" PRIx32 ") don't match.", + id, bit_file.id); + return ERROR_FAIL; + } + + retval = gowin_enable_config(tap); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + retval = gowin_erase_sram(tap, false); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + retval = gowin_set_instr(tap, ADDRESS_INITIALIZATION); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + retval = gowin_set_instr(tap, TRANSFER_CONFIGURATION_DATA); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + /* scan out the bitstream */ + struct scan_field field; + field.num_bits = bit_file.raw_file.length * 8; + field.out_value = bit_file.raw_file.data; + field.in_value = bit_file.raw_file.data; + jtag_add_dr_scan(gowin_info->tap, 1, &field, TAP_IDLE); + jtag_add_runtest(3, TAP_IDLE); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + free(bit_file.raw_file.data); + return retval; + } + + retval = gowin_disable_config(tap); + free(bit_file.raw_file.data); + if (retval != ERROR_OK) + return retval; + + retval = gowin_set_instr(gowin_info->tap, NO_OP); + if (retval != ERROR_OK) + return retval; + + retval = jtag_execute_queue(); + + return retval; +} + +static int gowin_read_register_command(struct pld_device *pld_device, uint32_t cmd, uint32_t *value) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gowin_pld_device *gowin_info = pld_device->driver_priv; + + if (!gowin_info || !gowin_info->tap) + return ERROR_FAIL; + + return gowin_read_register(gowin_info->tap, cmd, value); +} + +static int gowin_reload_command(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gowin_pld_device *gowin_info = pld_device->driver_priv; + + if (!gowin_info || !gowin_info->tap) + return ERROR_FAIL; + + return gowin_reload(gowin_info->tap); +} + +static int gowin_get_ipdbg_hub(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub) +{ + if (!pld_device) + return ERROR_FAIL; + + struct gowin_pld_device *pld_device_info = pld_device->driver_priv; + + if (!pld_device_info || !pld_device_info->tap) + return ERROR_FAIL; + + hub->tap = pld_device_info->tap; + + if (user_num == 1) { + hub->user_ir_code = USER1; + } else if (user_num == 2) { + hub->user_ir_code = USER2; + } else { + LOG_ERROR("gowin devices only have user register 1 & 2"); + return ERROR_FAIL; + } + return ERROR_OK; +} + +COMMAND_HANDLER(gowin_read_status_command_handler) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + uint32_t status = 0; + int retval = gowin_read_register_command(device, STATUS_REGISTER, &status); + + if (retval == ERROR_OK) + command_print(CMD, "0x%8.8" PRIx32, status); + + return retval; +} + +COMMAND_HANDLER(gowin_read_user_register_command_handler) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + uint32_t user_reg = 0; + int retval = gowin_read_register_command(device, READ_USERCODE, &user_reg); + + if (retval == ERROR_OK) + command_print(CMD, "0x%8.8" PRIx32, user_reg); + + return retval; +} + +COMMAND_HANDLER(gowin_reload_command_handler) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + return gowin_reload_command(device); +} + +static const struct command_registration gowin_exec_command_handlers[] = { + { + .name = "read_status", + .mode = COMMAND_EXEC, + .handler = gowin_read_status_command_handler, + .help = "reading status register from FPGA", + .usage = "pld_name", + }, { + .name = "read_user", + .mode = COMMAND_EXEC, + .handler = gowin_read_user_register_command_handler, + .help = "reading user register from FPGA", + .usage = "pld_name", + }, { + .name = "refresh", + .mode = COMMAND_EXEC, + .handler = gowin_reload_command_handler, + .help = "reload bitstream from flash to SRAM", + .usage = "pld_name", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration gowin_command_handler[] = { + { + .name = "gowin", + .mode = COMMAND_ANY, + .help = "gowin specific commands", + .usage = "", + .chain = gowin_exec_command_handlers + }, + COMMAND_REGISTRATION_DONE +}; + +PLD_CREATE_COMMAND_HANDLER(gowin_pld_create_command) +{ + if (CMD_ARGC != 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); + if (!tap) { + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; + } + + struct gowin_pld_device *gowin_info = malloc(sizeof(struct gowin_pld_device)); + if (!gowin_info) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + gowin_info->tap = tap; + + pld->driver_priv = gowin_info; + + return ERROR_OK; +} + +struct pld_driver gowin_pld = { + .name = "gowin", + .commands = gowin_command_handler, + .pld_create_command = &gowin_pld_create_command, + .load = &gowin_load_to_sram, + .get_ipdbg_hub = gowin_get_ipdbg_hub, +}; diff --git a/src/pld/intel.c b/src/pld/intel.c new file mode 100644 index 0000000000..a4bdabe26f --- /dev/null +++ b/src/pld/intel.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <jtag/jtag.h> +#include <jtag/adapter.h> +#include <helper/system.h> +#include <helper/log.h> + +#include "pld.h" +#include "raw_bit.h" + +#define BYPASS 0x3FF +#define USER0 0x00C +#define USER1 0x00E + +enum intel_family_e { + INTEL_CYCLONEIII, + INTEL_CYCLONEIV, + INTEL_CYCLONEV, + INTEL_CYCLONE10, + INTEL_ARRIAII, + INTEL_UNKNOWN +}; + +struct intel_pld_device { + struct jtag_tap *tap; + unsigned int boundary_scan_length; + int checkpos; + enum intel_family_e family; +}; + +static int intel_check_config(struct intel_pld_device *intel_info) +{ + if (intel_info->boundary_scan_length == 0) { + LOG_ERROR("unknown boundary scan length. Please specify with 'intel set_bscan'."); + return ERROR_FAIL; + } + + if (intel_info->checkpos >= 0 && (unsigned int)intel_info->checkpos >= intel_info->boundary_scan_length) { + LOG_ERROR("checkpos has to be smaller than scan length %d < %u", + intel_info->checkpos, intel_info->boundary_scan_length); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +static int intel_read_file(struct raw_bit_file *bit_file, const char *filename) +{ + if (!filename || !bit_file) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* check if binary .bin or ascii .bit/.hex */ + const char *file_ending_pos = strrchr(filename, '.'); + if (!file_ending_pos) { + LOG_ERROR("Unable to detect filename suffix"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (strcasecmp(file_ending_pos, ".rbf") == 0) + return cpld_read_raw_bit_file(bit_file, filename); + + LOG_ERROR("Unable to detect filetype"); + return ERROR_PLD_FILE_LOAD_FAILED; +} + +static int intel_set_instr(struct jtag_tap *tap, uint16_t new_instr) +{ + struct scan_field field; + field.num_bits = tap->ir_length; + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); + field.in_value = NULL; + jtag_add_ir_scan(tap, &field, TAP_IDLE); + free(t); + return ERROR_OK; +} + + +static int intel_load(struct pld_device *pld_device, const char *filename) +{ + unsigned int speed = adapter_get_speed_khz(); + if (speed < 1) + speed = 1; + + unsigned int cycles = DIV_ROUND_UP(speed, 200); + if (cycles < 1) + cycles = 1; + + if (!pld_device || !pld_device->driver_priv) + return ERROR_FAIL; + + struct intel_pld_device *intel_info = pld_device->driver_priv; + if (!intel_info || !intel_info->tap) + return ERROR_FAIL; + struct jtag_tap *tap = intel_info->tap; + + int retval = intel_check_config(intel_info); + if (retval != ERROR_OK) + return retval; + + struct raw_bit_file bit_file; + retval = intel_read_file(&bit_file, filename); + if (retval != ERROR_OK) + return retval; + + retval = intel_set_instr(tap, 0x002); + if (retval != ERROR_OK) { + free(bit_file.data); + return retval; + } + jtag_add_runtest(speed, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + free(bit_file.data); + return retval; + } + + /* shift in the bitstream */ + struct scan_field field; + field.num_bits = bit_file.length * 8; + field.out_value = bit_file.data; + field.in_value = NULL; + + jtag_add_dr_scan(tap, 1, &field, TAP_DRPAUSE); + retval = jtag_execute_queue(); + free(bit_file.data); + if (retval != ERROR_OK) + return retval; + + retval = intel_set_instr(tap, 0x004); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(cycles, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + + if (intel_info->boundary_scan_length != 0) { + uint8_t *buf = calloc(DIV_ROUND_UP(intel_info->boundary_scan_length, 8), 1); + if (!buf) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + field.num_bits = intel_info->boundary_scan_length; + field.out_value = buf; + field.in_value = buf; + jtag_add_dr_scan(tap, 1, &field, TAP_DRPAUSE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + free(buf); + return retval; + } + + if (intel_info->checkpos != -1) + retval = ((buf[intel_info->checkpos / 8] & (1 << (intel_info->checkpos % 8)))) ? + ERROR_OK : ERROR_FAIL; + free(buf); + if (retval != ERROR_OK) { + LOG_ERROR("Check failed"); + return ERROR_FAIL; + } + } else { + LOG_INFO("unable to check. Please specify with position 'intel set_check_pos'."); + } + + retval = intel_set_instr(tap, 0x003); + if (retval != ERROR_OK) + return retval; + switch (intel_info->family) { + case INTEL_CYCLONEIII: + case INTEL_CYCLONEIV: + jtag_add_runtest(5 * speed + 512, TAP_IDLE); + break; + case INTEL_CYCLONEV: + jtag_add_runtest(5 * speed + 512, TAP_IDLE); + break; + case INTEL_CYCLONE10: + jtag_add_runtest(DIV_ROUND_UP(512ul * speed, 125ul) + 512, TAP_IDLE); + break; + case INTEL_ARRIAII: + jtag_add_runtest(DIV_ROUND_UP(64ul * speed, 125ul) + 512, TAP_IDLE); + break; + case INTEL_UNKNOWN: + LOG_ERROR("unknown family"); + return ERROR_FAIL; + } + + retval = intel_set_instr(tap, BYPASS); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(speed, TAP_IDLE); + return jtag_execute_queue(); +} + +static int intel_get_ipdbg_hub(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub) +{ + if (!pld_device) + return ERROR_FAIL; + + struct intel_pld_device *pld_device_info = pld_device->driver_priv; + + if (!pld_device_info || !pld_device_info->tap) + return ERROR_FAIL; + + hub->tap = pld_device_info->tap; + + if (user_num == 0) { + hub->user_ir_code = USER0; + } else if (user_num == 1) { + hub->user_ir_code = USER1; + } else { + LOG_ERROR("intel devices only have user register 0 & 1"); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int intel_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir) +{ + *ir = USER1; + return ERROR_OK; +} + +COMMAND_HANDLER(intel_set_bscan_command_handler) +{ + unsigned int boundary_scan_length; + + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *pld_device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!pld_device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], boundary_scan_length); + + struct intel_pld_device *intel_info = pld_device->driver_priv; + + if (!intel_info) + return ERROR_FAIL; + + intel_info->boundary_scan_length = boundary_scan_length; + + return ERROR_OK; +} + +COMMAND_HANDLER(intel_set_check_pos_command_handler) +{ + int checkpos; + + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *pld_device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!pld_device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], checkpos); + + struct intel_pld_device *intel_info = pld_device->driver_priv; + + if (!intel_info) + return ERROR_FAIL; + + intel_info->checkpos = checkpos; + + return ERROR_OK; +} + +PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command) +{ + if (CMD_ARGC != 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); + if (!tap) { + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; + } + + enum intel_family_e family = INTEL_UNKNOWN; + + if (strcmp(CMD_ARGV[4], "-family") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[5], "cycloneiii") == 0) { + family = INTEL_CYCLONEIII; + } else if (strcmp(CMD_ARGV[5], "cycloneiv") == 0) { + family = INTEL_CYCLONEIV; + } else if (strcmp(CMD_ARGV[5], "cyclonev") == 0) { + family = INTEL_CYCLONEV; + } else if (strcmp(CMD_ARGV[5], "cyclone10") == 0) { + family = INTEL_CYCLONE10; + } else if (strcmp(CMD_ARGV[5], "arriaii") == 0) { + family = INTEL_ARRIAII; + } else { + command_print(CMD, "unknown family"); + return ERROR_FAIL; + } + + struct intel_pld_device *intel_info = malloc(sizeof(struct intel_pld_device)); + if (!intel_info) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + intel_info->tap = tap; + intel_info->boundary_scan_length = 0; + intel_info->checkpos = -1; + intel_info->family = family; + + pld->driver_priv = intel_info; + + return ERROR_OK; +} + +static const struct command_registration intel_exec_command_handlers[] = { + { + .name = "set_bscan", + .mode = COMMAND_ANY, + .handler = intel_set_bscan_command_handler, + .help = "set boundary scan register length of FPGA", + .usage = "pld_name len", + }, { + .name = "set_check_pos", + .mode = COMMAND_ANY, + .handler = intel_set_check_pos_command_handler, + .help = "set check_pos of FPGA", + .usage = "pld_name pos", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration intel_command_handler[] = { + { + .name = "intel", + .mode = COMMAND_ANY, + .help = "intel specific commands", + .usage = "", + .chain = intel_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +struct pld_driver intel_pld = { + .name = "intel", + .commands = intel_command_handler, + .pld_create_command = &intel_pld_create_command, + .load = &intel_load, + .get_ipdbg_hub = intel_get_ipdbg_hub, + .get_jtagspi_userircode = intel_get_jtagspi_userircode, +}; diff --git a/src/pld/lattice.c b/src/pld/lattice.c new file mode 100644 index 0000000000..93ef3565c9 --- /dev/null +++ b/src/pld/lattice.c @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "lattice.h" +#include <jtag/jtag.h> +#include "pld.h" +#include "lattice_bit.h" +#include "ecp2_3.h" +#include "ecp5.h" +#include "certus.h" + +#define PRELOAD 0x1C +#define USER1 0x32 +#define USER2 0x38 + + +struct lattice_devices_elem { + uint32_t id; + size_t preload_length; + enum lattice_family_e family; +}; + +static const struct lattice_devices_elem lattice_devices[] = { + {0x01270043, 654, LATTICE_ECP2 /* ecp2-6e */}, + {0x01271043, 643, LATTICE_ECP2 /* ecp2-12e */}, + {0x01272043, 827, LATTICE_ECP2 /* ecp2-20e */}, + {0x01274043, 1011, LATTICE_ECP2 /* ecp2-35e */}, + {0x01273043, 1219, LATTICE_ECP2 /* ecp2-50e */}, + {0x01275043, 654, LATTICE_ECP2 /* ecp2-70e */}, + {0x01279043, 680, LATTICE_ECP2 /* ecp2m20e */}, + {0x0127A043, 936, LATTICE_ECP2 /* ecp2m35e */}, + {0x0127B043, 1056, LATTICE_ECP2 /* ecp2m50e */}, + {0x0127C043, 1039, LATTICE_ECP2 /* ecp2m70e */}, + {0x0127D043, 1311, LATTICE_ECP2 /* ecp2m100e */}, + {0x01010043, 467, LATTICE_ECP3 /* ecp3 lae3-17ea & lfe3-17ea*/}, + {0x01012043, 675, LATTICE_ECP3 /* ecp3 lae3-35ea & lfe3-35ea*/}, + {0x01014043, 1077, LATTICE_ECP3 /* ecp3 lfe3-70ea & lfe3-70e & lfe3-95ea && lfe3-95e*/}, + {0x01015043, 1326, LATTICE_ECP3 /* ecp3 lfe3-150e*/}, + {0x21111043, 409, LATTICE_ECP5 /* "LAE5U-12F & LFE5U-12F" */}, + {0x41111043, 409, LATTICE_ECP5 /* "LFE5U-25F" */}, + {0x41112043, 510, LATTICE_ECP5 /* "LFE5U-45F" */}, + {0x41113043, 750, LATTICE_ECP5 /* "LFE5U-85F" */}, + {0x81111043, 409, LATTICE_ECP5 /* "LFE5UM5G-25F" */}, + {0x81112043, 510, LATTICE_ECP5 /* "LFE5UM5G-45F" */}, + {0x81113043, 750, LATTICE_ECP5 /* "LFE5UM5G-85F" */}, + {0x01111043, 409, LATTICE_ECP5 /* "LAE5UM-25F" */}, + {0x01112043, 510, LATTICE_ECP5 /* "LAE5UM-45F" */}, + {0x01113043, 750, LATTICE_ECP5 /* "LAE5UM-85F" */}, + {0x310f0043, 362, LATTICE_CERTUS /* LFD2NX-17 */}, + {0x310f1043, 362, LATTICE_CERTUS /* LFD2NX-40 */}, + {0x010f4043, 362, LATTICE_CERTUS /* LFCPNX-100 */}, +}; + +int lattice_set_instr(struct jtag_tap *tap, uint8_t new_instr, enum tap_state endstate) +{ + struct scan_field field; + field.num_bits = tap->ir_length; + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); + field.in_value = NULL; + jtag_add_ir_scan(tap, &field, endstate); + free(t); + return ERROR_OK; +} + +static int lattice_check_device_family(struct lattice_pld_device *lattice_device) +{ + if (lattice_device->family != LATTICE_UNKNOWN && lattice_device->preload_length != 0) + return ERROR_OK; + + if (!lattice_device->tap || !lattice_device->tap->has_idcode) + return ERROR_FAIL; + + for (size_t i = 0; i < ARRAY_SIZE(lattice_devices); ++i) { + if (lattice_devices[i].id == lattice_device->tap->idcode) { + if (lattice_device->family == LATTICE_UNKNOWN) + lattice_device->family = lattice_devices[i].family; + if (lattice_device->preload_length == 0) + lattice_device->preload_length = lattice_devices[i].preload_length; + return ERROR_OK; + } + } + LOG_ERROR("Unknown id! Specify family and preload-length manually."); + return ERROR_FAIL; +} + +int lattice_read_u32_register(struct jtag_tap *tap, uint8_t cmd, uint32_t *in_val, + uint32_t out_val, bool do_idle) +{ + struct scan_field field; + uint8_t buffer[4]; + + int retval = lattice_set_instr(tap, cmd, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + if (do_idle) { + jtag_add_runtest(2, TAP_IDLE); + jtag_add_sleep(1000); + } + + h_u32_to_le(buffer, out_val); + field.num_bits = 32; + field.out_value = buffer; + field.in_value = buffer; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval == ERROR_OK) + *in_val = le_to_h_u32(buffer); + + return retval; +} + +int lattice_read_u64_register(struct jtag_tap *tap, uint8_t cmd, uint64_t *in_val, + uint64_t out_val) +{ + struct scan_field field; + uint8_t buffer[8]; + + int retval = lattice_set_instr(tap, cmd, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + h_u64_to_le(buffer, out_val); + field.num_bits = 64; + field.out_value = buffer; + field.in_value = buffer; + jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval == ERROR_OK) + *in_val = le_to_h_u64(buffer); + + return retval; +} + +int lattice_preload(struct lattice_pld_device *lattice_device) +{ + struct scan_field field; + size_t sz_bytes = DIV_ROUND_UP(lattice_device->preload_length, 8); + + int retval = lattice_set_instr(lattice_device->tap, PRELOAD, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + uint8_t *buffer = malloc(sz_bytes); + if (!buffer) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + memset(buffer, 0xff, sz_bytes); + + field.num_bits = lattice_device->preload_length; + field.out_value = buffer; + field.in_value = NULL; + jtag_add_dr_scan(lattice_device->tap, 1, &field, TAP_IDLE); + retval = jtag_execute_queue(); + free(buffer); + return retval; +} + +static int lattice_read_usercode(struct lattice_pld_device *lattice_device, uint32_t *usercode, uint32_t out) +{ + struct jtag_tap *tap = lattice_device->tap; + if (!tap) + return ERROR_FAIL; + + if (lattice_device->family == LATTICE_ECP2 || lattice_device->family == LATTICE_ECP3) + return lattice_ecp2_3_read_usercode(tap, usercode, out); + else if (lattice_device->family == LATTICE_ECP5) + return lattice_ecp5_read_usercode(tap, usercode, out); + else if (lattice_device->family == LATTICE_CERTUS) + return lattice_certus_read_usercode(tap, usercode, out); + + return ERROR_FAIL; +} + +int lattice_verify_usercode(struct lattice_pld_device *lattice_device, uint32_t out, + uint32_t expected, uint32_t mask) +{ + uint32_t usercode; + + int retval = lattice_read_usercode(lattice_device, &usercode, out); + if (retval != ERROR_OK) + return retval; + + if ((usercode & mask) != expected) { + LOG_ERROR("verifying user code register failed got: 0x%08" PRIx32 " expected: 0x%08" PRIx32, + usercode & mask, expected); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int lattice_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode) +{ + if (lattice_device->family == LATTICE_ECP2 || lattice_device->family == LATTICE_ECP3) + return lattice_ecp2_3_write_usercode(lattice_device, usercode); + else if (lattice_device->family == LATTICE_ECP5) + return lattice_ecp5_write_usercode(lattice_device, usercode); + else if (lattice_device->family == LATTICE_CERTUS) + return lattice_certus_write_usercode(lattice_device, usercode); + + return ERROR_FAIL; +} + +static int lattice_read_status_u32(struct lattice_pld_device *lattice_device, uint32_t *status, + uint32_t out, bool do_idle) +{ + if (!lattice_device->tap) + return ERROR_FAIL; + + if (lattice_device->family == LATTICE_ECP2 || lattice_device->family == LATTICE_ECP3) + return lattice_ecp2_3_read_status(lattice_device->tap, status, out, do_idle); + else if (lattice_device->family == LATTICE_ECP5) + return lattice_ecp5_read_status(lattice_device->tap, status, out, do_idle); + + return ERROR_FAIL; +} +static int lattice_read_status_u64(struct lattice_pld_device *lattice_device, uint64_t *status, + uint64_t out) +{ + if (!lattice_device->tap) + return ERROR_FAIL; + + if (lattice_device->family == LATTICE_CERTUS) + return lattice_certus_read_status(lattice_device->tap, status, out); + + return ERROR_FAIL; +} + +int lattice_verify_status_register_u32(struct lattice_pld_device *lattice_device, uint32_t out, + uint32_t expected, uint32_t mask, bool do_idle) +{ + uint32_t status; + int retval = lattice_read_status_u32(lattice_device, &status, out, do_idle); + if (retval != ERROR_OK) + return retval; + + if ((status & mask) != expected) { + LOG_ERROR("verifying status register failed got: 0x%08" PRIx32 " expected: 0x%08" PRIx32, + status & mask, expected); + return ERROR_FAIL; + } + return ERROR_OK; +} + +int lattice_verify_status_register_u64(struct lattice_pld_device *lattice_device, uint64_t out, + uint64_t expected, uint64_t mask) +{ + uint64_t status; + int retval = lattice_read_status_u64(lattice_device, &status, out); + if (retval != ERROR_OK) + return retval; + + if ((status & mask) != expected) { + LOG_ERROR("verifying status register failed got: 0x%08" PRIx64 " expected: 0x%08" PRIx64, + status & mask, expected); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int lattice_load_command(struct pld_device *pld_device, const char *filename) +{ + if (!pld_device) + return ERROR_FAIL; + + struct lattice_pld_device *lattice_device = pld_device->driver_priv; + if (!lattice_device || !lattice_device->tap) + return ERROR_FAIL; + struct jtag_tap *tap = lattice_device->tap; + + if (!tap || !tap->has_idcode) + return ERROR_FAIL; + + int retval = lattice_check_device_family(lattice_device); + if (retval != ERROR_OK) + return retval; + + struct lattice_bit_file bit_file; + retval = lattice_read_file(&bit_file, filename, lattice_device->family); + if (retval != ERROR_OK) + return retval; + + uint32_t id = tap->idcode; + retval = ERROR_FAIL; + switch (lattice_device->family) { + case LATTICE_ECP2: + retval = lattice_ecp2_load(lattice_device, &bit_file); + break; + case LATTICE_ECP3: + retval = lattice_ecp3_load(lattice_device, &bit_file); + break; + case LATTICE_ECP5: + case LATTICE_CERTUS: + if (bit_file.has_id && id != bit_file.idcode) + LOG_WARNING("Id on device (0x%8.8" PRIx32 ") and id in bit-stream (0x%8.8" PRIx32 ") don't match.", + id, bit_file.idcode); + if (lattice_device->family == LATTICE_ECP5) + retval = lattice_ecp5_load(lattice_device, &bit_file); + else + retval = lattice_certus_load(lattice_device, &bit_file); + break; + default: + LOG_ERROR("loading unknown device family"); + break; + } + free(bit_file.raw_bit.data); + return retval; +} + +static int lattice_get_ipdbg_hub(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub) +{ + if (!pld_device) + return ERROR_FAIL; + + struct lattice_pld_device *pld_device_info = pld_device->driver_priv; + + if (!pld_device_info || !pld_device_info->tap) + return ERROR_FAIL; + + hub->tap = pld_device_info->tap; + + if (user_num == 1) { + hub->user_ir_code = USER1; + } else if (user_num == 2) { + hub->user_ir_code = USER2; + } else { + LOG_ERROR("lattice devices only have user register 1 & 2"); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int lattice_connect_spi_to_jtag(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct lattice_pld_device *pld_device_info = pld_device->driver_priv; + + int retval = lattice_check_device_family(pld_device_info); + if (retval != ERROR_OK) + return retval; + + if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3) + return lattice_ecp2_3_connect_spi_to_jtag(pld_device_info); + else if (pld_device_info->family == LATTICE_ECP5) + return lattice_ecp5_connect_spi_to_jtag(pld_device_info); + else if (pld_device_info->family == LATTICE_CERTUS) + return lattice_certus_connect_spi_to_jtag(pld_device_info); + + return ERROR_FAIL; +} + +static int lattice_disconnect_spi_from_jtag(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct lattice_pld_device *pld_device_info = pld_device->driver_priv; + + int retval = lattice_check_device_family(pld_device_info); + if (retval != ERROR_OK) + return retval; + + if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3) + return lattice_ecp2_3_disconnect_spi_from_jtag(pld_device_info); + else if (pld_device_info->family == LATTICE_ECP5) + return lattice_ecp5_disconnect_spi_from_jtag(pld_device_info); + else if (pld_device_info->family == LATTICE_CERTUS) + return lattice_certus_disconnect_spi_from_jtag(pld_device_info); + + return ERROR_FAIL; +} + +static int lattice_get_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits, + unsigned int *trailing_write_bits) +{ + if (!pld_device) + return ERROR_FAIL; + + struct lattice_pld_device *pld_device_info = pld_device->driver_priv; + + int retval = lattice_check_device_family(pld_device_info); + if (retval != ERROR_OK) + return retval; + + if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3) + return lattice_ecp2_3_get_facing_read_bits(pld_device_info, facing_read_bits); + else if (pld_device_info->family == LATTICE_ECP5) + return lattice_ecp5_get_facing_read_bits(pld_device_info, facing_read_bits); + else if (pld_device_info->family == LATTICE_CERTUS) + return lattice_certus_get_facing_read_bits(pld_device_info, facing_read_bits); + + return ERROR_FAIL; +} + +static int lattice_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction) +{ + *has_instruction = true; + return ERROR_OK; +} + +PLD_CREATE_COMMAND_HANDLER(lattice_pld_create_command) +{ + if (CMD_ARGC != 4 && CMD_ARGC != 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); + if (!tap) { + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; + } + + /* id is not known yet -> postpone lattice_check_device_family() */ + enum lattice_family_e family = LATTICE_UNKNOWN; + if (CMD_ARGC == 6) { + if (strcmp(CMD_ARGV[4], "-family") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcasecmp(CMD_ARGV[5], "ecp2") == 0) { + family = LATTICE_ECP2; + } else if (strcasecmp(CMD_ARGV[5], "ecp3") == 0) { + family = LATTICE_ECP3; + } else if (strcasecmp(CMD_ARGV[5], "ecp5") == 0) { + family = LATTICE_ECP5; + } else if (strcasecmp(CMD_ARGV[5], "certus") == 0) { + family = LATTICE_CERTUS; + } else { + command_print(CMD, "unknown family"); + return ERROR_FAIL; + } + } + + struct lattice_pld_device *lattice_device = malloc(sizeof(struct lattice_pld_device)); + if (!lattice_device) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + lattice_device->tap = tap; + lattice_device->family = family; + lattice_device->preload_length = 0; + + pld->driver_priv = lattice_device; + + return ERROR_OK; +} + +COMMAND_HANDLER(lattice_read_usercode_register_command_handler) +{ + uint32_t usercode; + + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct lattice_pld_device *lattice_device = device->driver_priv; + if (!lattice_device) + return ERROR_FAIL; + + int retval = lattice_check_device_family(lattice_device); + if (retval != ERROR_OK) + return retval; + + retval = lattice_read_usercode(lattice_device, &usercode, 0x0); + if (retval == ERROR_OK) + command_print(CMD, "0x%8.8" PRIx32, usercode); + + return retval; +} + +COMMAND_HANDLER(lattice_set_preload_command_handler) +{ + unsigned int preload_length; + + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], preload_length); + + struct lattice_pld_device *lattice_device = device->driver_priv; + + if (!lattice_device) + return ERROR_FAIL; + + lattice_device->preload_length = preload_length; + + return ERROR_OK; +} + +COMMAND_HANDLER(lattice_write_usercode_register_command_handler) +{ + uint32_t usercode; + + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], usercode); + + struct lattice_pld_device *lattice_device = device->driver_priv; + if (!lattice_device) + return ERROR_FAIL; + + int retval = lattice_check_device_family(lattice_device); + if (retval != ERROR_OK) + return retval; + + return lattice_write_usercode(lattice_device, usercode); +} + +COMMAND_HANDLER(lattice_read_status_command_handler) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct lattice_pld_device *lattice_device = device->driver_priv; + if (!lattice_device) + return ERROR_FAIL; + + int retval = lattice_check_device_family(lattice_device); + if (retval != ERROR_OK) + return retval; + + if (lattice_device->family == LATTICE_CERTUS) { + uint64_t status; + retval = lattice_read_status_u64(lattice_device, &status, 0x0); + if (retval == ERROR_OK) + command_print(CMD, "0x%016" PRIx64, status); + } else { + uint32_t status; + const bool do_idle = lattice_device->family == LATTICE_ECP5; + retval = lattice_read_status_u32(lattice_device, &status, 0x0, do_idle); + if (retval == ERROR_OK) + command_print(CMD, "0x%8.8" PRIx32, status); + } + + return retval; +} + +COMMAND_HANDLER(lattice_refresh_command_handler) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct lattice_pld_device *lattice_device = device->driver_priv; + if (!lattice_device) + return ERROR_FAIL; + + int retval = lattice_check_device_family(lattice_device); + if (retval != ERROR_OK) + return retval; + + if (lattice_device->family == LATTICE_ECP2 || lattice_device->family == LATTICE_ECP3) + return lattice_ecp2_3_refresh(lattice_device); + else if (lattice_device->family == LATTICE_ECP5) + return lattice_ecp5_refresh(lattice_device); + else if (lattice_device->family == LATTICE_CERTUS) + return lattice_certus_refresh(lattice_device); + + return ERROR_FAIL; +} + +static const struct command_registration lattice_exec_command_handlers[] = { + { + .name = "read_status", + .mode = COMMAND_EXEC, + .handler = lattice_read_status_command_handler, + .help = "reading status register from FPGA", + .usage = "pld_name", + }, { + .name = "read_user", + .mode = COMMAND_EXEC, + .handler = lattice_read_usercode_register_command_handler, + .help = "reading usercode register from FPGA", + .usage = "pld_name", + }, { + .name = "write_user", + .mode = COMMAND_EXEC, + .handler = lattice_write_usercode_register_command_handler, + .help = "writing usercode register to FPGA", + .usage = "pld_name value", + }, { + .name = "set_preload", + .mode = COMMAND_ANY, + .handler = lattice_set_preload_command_handler, + .help = "set length for preload (device specific)", + .usage = "pld_name value", + }, { + .name = "refresh", + .mode = COMMAND_EXEC, + .handler = lattice_refresh_command_handler, + .help = "refresh from configuration memory", + .usage = "pld_name", + }, + COMMAND_REGISTRATION_DONE +}; + +static const struct command_registration lattice_command_handler[] = { + { + .name = "lattice", + .mode = COMMAND_ANY, + .help = "lattice specific commands", + .usage = "", + .chain = lattice_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +struct pld_driver lattice_pld = { + .name = "lattice", + .commands = lattice_command_handler, + .pld_create_command = &lattice_pld_create_command, + .load = &lattice_load_command, + .get_ipdbg_hub = lattice_get_ipdbg_hub, + .has_jtagspi_instruction = lattice_has_jtagspi_instruction, + .connect_spi_to_jtag = lattice_connect_spi_to_jtag, + .disconnect_spi_from_jtag = lattice_disconnect_spi_from_jtag, + .get_stuff_bits = lattice_get_stuff_bits, +}; diff --git a/src/pld/lattice.h b/src/pld/lattice.h new file mode 100644 index 0000000000..c215989669 --- /dev/null +++ b/src/pld/lattice.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_LATTICE_H +#define OPENOCD_PLD_LATTICE_H + +#include <jtag/jtag.h> +#include "pld.h" +#include "lattice_bit.h" + +#define BYPASS 0xFF + +struct lattice_pld_device { + struct jtag_tap *tap; + size_t preload_length; + enum lattice_family_e family; +}; + +int lattice_set_instr(struct jtag_tap *tap, uint8_t new_instr, enum tap_state endstate); +int lattice_read_u32_register(struct jtag_tap *tap, uint8_t cmd, uint32_t *in_val, + uint32_t out_val, bool do_idle); +int lattice_read_u64_register(struct jtag_tap *tap, uint8_t cmd, uint64_t *in_val, + uint64_t out_val); +int lattice_verify_usercode(struct lattice_pld_device *lattice_device, uint32_t out, + uint32_t expected, uint32_t mask); +int lattice_verify_status_register_u32(struct lattice_pld_device *lattice_device, uint32_t out, + uint32_t expected, uint32_t mask, bool do_idle); +int lattice_verify_status_register_u64(struct lattice_pld_device *lattice_device, uint64_t out, + uint64_t expected, uint64_t mask); +int lattice_preload(struct lattice_pld_device *lattice_device); + +#endif /* OPENOCD_PLD_LATTICE_H */ diff --git a/src/pld/lattice_bit.c b/src/pld/lattice_bit.c new file mode 100644 index 0000000000..796adce975 --- /dev/null +++ b/src/pld/lattice_bit.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "lattice_bit.h" +#include "raw_bit.h" +#include "pld.h" +#include <helper/system.h> +#include <helper/log.h> +#include <helper/binarybuffer.h> + +enum read_bit_state { + SEEK_HEADER_START, + SEEK_HEADER_END, + SEEK_PREAMBLE, + SEEK_ID, + DONE, +}; + +static int lattice_read_bit_file(struct lattice_bit_file *bit_file, const char *filename, enum lattice_family_e family) +{ + int retval = cpld_read_raw_bit_file(&bit_file->raw_bit, filename); + if (retval != ERROR_OK) + return retval; + + bit_file->part = NULL; + bit_file->has_id = false; + enum read_bit_state state = SEEK_HEADER_START; + for (size_t pos = 1; pos < bit_file->raw_bit.length && state != DONE; ++pos) { + switch (state) { + case SEEK_HEADER_START: + if (bit_file->raw_bit.data[pos] == 0 && bit_file->raw_bit.data[pos - 1] == 0xff) + state = SEEK_HEADER_END; + break; + case SEEK_HEADER_END: + if (pos + 6 < bit_file->raw_bit.length && + strncmp((const char *)(bit_file->raw_bit.data + pos), "Part: ", 6) == 0) { + bit_file->part = (const char *)bit_file->raw_bit.data + pos + 6; + LOG_INFO("part found: %s\n", bit_file->part); + } else if (bit_file->raw_bit.data[pos] == 0xff && bit_file->raw_bit.data[pos - 1] == 0) { + bit_file->offset = pos; + state = (family != LATTICE_ECP2 && family != LATTICE_ECP3) ? SEEK_PREAMBLE : DONE; + } + break; + case SEEK_PREAMBLE: + if (pos >= 4) { + uint32_t preamble = be_to_h_u32(bit_file->raw_bit.data + pos - 3); + switch (preamble) { + case 0xffffbdb3: + state = SEEK_ID; + break; + case 0xffffbfb3: + case 0xffffbeb3: + state = DONE; + break; + } + } + break; + case SEEK_ID: + if (pos + 7 < bit_file->raw_bit.length && bit_file->raw_bit.data[pos] == 0xe2) { + bit_file->idcode = be_to_h_u32(&bit_file->raw_bit.data[pos + 4]); + bit_file->has_id = true; + state = DONE; + } + break; + default: + break; + } + } + + if (state != DONE) { + LOG_ERROR("parsing bitstream failed"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + for (size_t i = bit_file->offset; i < bit_file->raw_bit.length; i++) + bit_file->raw_bit.data[i] = flip_u32(bit_file->raw_bit.data[i], 8); + + return ERROR_OK; +} + +int lattice_read_file(struct lattice_bit_file *bit_file, const char *filename, enum lattice_family_e family) +{ + if (!filename || !bit_file) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* check if binary .bin or ascii .bit/.hex */ + const char *file_suffix_pos = strrchr(filename, '.'); + if (!file_suffix_pos) { + LOG_ERROR("Unable to detect filename suffix"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (strcasecmp(file_suffix_pos, ".bit") == 0) + return lattice_read_bit_file(bit_file, filename, family); + + LOG_ERROR("Filetype not supported"); + return ERROR_PLD_FILE_LOAD_FAILED; +} diff --git a/src/pld/lattice_bit.h b/src/pld/lattice_bit.h new file mode 100644 index 0000000000..33f1b347f1 --- /dev/null +++ b/src/pld/lattice_bit.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_LATTICE_BIT_H +#define OPENOCD_PLD_LATTICE_BIT_H + +#include "helper/types.h" +#include "raw_bit.h" + + +struct lattice_bit_file { + struct raw_bit_file raw_bit; + size_t offset; + uint32_t idcode; + const char *part; /* reuses memory in raw_bit_file */ + bool has_id; +}; + +enum lattice_family_e { + LATTICE_ECP2, + LATTICE_ECP3, + LATTICE_ECP5, + LATTICE_CERTUS, + LATTICE_UNKNOWN, +}; + +int lattice_read_file(struct lattice_bit_file *bit_file, const char *filename, enum lattice_family_e family); + +#endif /* OPENOCD_PLD_LATTICE_BIT_H */ diff --git a/src/pld/lattice_cmd.h b/src/pld/lattice_cmd.h new file mode 100644 index 0000000000..0c10625832 --- /dev/null +++ b/src/pld/lattice_cmd.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_LATTICE_CMD_H +#define OPENOCD_PLD_LATTICE_CMD_H + +#define ISC_ERASE 0x0E +#define ISC_DISABLE 0x26 +#define PROGRAM_SPI 0x3A +#define LSC_READ_STATUS 0x3C +#define LSC_INIT_ADDRESS 0x46 +#define LSC_REFRESH 0x79 +#define LSC_BITSTREAM_BURST 0x7A +#define READ_USERCODE 0xC0 +#define ISC_ENABLE 0xC6 + +#endif /* OPENOCD_PLD_LATTICE_CMD_H */ diff --git a/src/pld/pld.c b/src/pld/pld.c index 9d8375cb61..edd7796139 100644 --- a/src/pld/pld.c +++ b/src/pld/pld.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -10,90 +10,221 @@ #endif #include "pld.h" +#include <sys/stat.h> #include <helper/log.h> #include <helper/replacements.h> #include <helper/time_support.h> -/* pld drivers - */ -extern struct pld_driver virtex2_pld; - static struct pld_driver *pld_drivers[] = { + &efinix_pld, + &gatemate_pld, + &gowin_pld, + &intel_pld, + &lattice_pld, &virtex2_pld, NULL, }; static struct pld_device *pld_devices; -struct pld_device *get_pld_device_by_num(int num) +static struct pld_device *get_pld_device_by_num(int num) { struct pld_device *p; int i = 0; for (p = pld_devices; p; p = p->next) { - if (i++ == num) + if (i++ == num) { + LOG_WARNING("DEPRECATED: use pld name \"%s\" instead of number %d", p->name, num); + return p; + } + } + + return NULL; +} + +struct pld_device *get_pld_device_by_name(const char *name) +{ + for (struct pld_device *p = pld_devices; p; p = p->next) { + if (strcmp(p->name, name) == 0) return p; } return NULL; } -/* pld device <driver> [driver_options ...] - */ -COMMAND_HANDLER(handle_pld_device_command) +struct pld_device *get_pld_device_by_name_or_numstr(const char *str) +{ + struct pld_device *dev = get_pld_device_by_name(str); + if (dev) + return dev; + + char *end; + unsigned long dev_num = strtoul(str, &end, 0); + if (*end || dev_num > INT_MAX) { + LOG_ERROR("Invalid argument"); + return NULL; + } + + return get_pld_device_by_num(dev_num); +} + + +int pld_has_jtagspi_instruction(struct pld_device *pld_device, bool *has_instruction) +{ + *has_instruction = false; /* default is using a proxy bitstream */ + + if (!pld_device) + return ERROR_FAIL; + + struct pld_driver *pld_driver = pld_device->driver; + if (!pld_driver) { + LOG_ERROR("pld device has no associated driver"); + return ERROR_FAIL; + } + + if (pld_driver->has_jtagspi_instruction) + return pld_driver->has_jtagspi_instruction(pld_device, has_instruction); + /* else, take the default (proxy bitstream) */ + return ERROR_OK; +} + +int pld_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir) +{ + if (!pld_device) + return ERROR_FAIL; + + struct pld_driver *pld_driver = pld_device->driver; + if (!pld_driver) { + LOG_ERROR("pld device has no associated driver"); + return ERROR_FAIL; + } + + if (pld_driver->get_jtagspi_userircode) + return pld_driver->get_jtagspi_userircode(pld_device, ir); + + return ERROR_FAIL; +} + +int pld_get_jtagspi_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits, + unsigned int *trailing_write_bits) +{ + if (!pld_device) + return ERROR_FAIL; + + struct pld_driver *pld_driver = pld_device->driver; + if (!pld_driver) { + LOG_ERROR("pld device has no associated driver"); + return ERROR_FAIL; + } + + if (pld_driver->get_stuff_bits) + return pld_driver->get_stuff_bits(pld_device, facing_read_bits, trailing_write_bits); + + return ERROR_OK; +} + +int pld_connect_spi_to_jtag(struct pld_device *pld_device) { - int i; - int found = 0; + if (!pld_device) + return ERROR_FAIL; - if (CMD_ARGC < 1) + struct pld_driver *pld_driver = pld_device->driver; + if (!pld_driver) { + LOG_ERROR("pld device has no associated driver"); + return ERROR_FAIL; + } + + if (pld_driver->connect_spi_to_jtag) + return pld_driver->connect_spi_to_jtag(pld_device); + + return ERROR_FAIL; +} + +int pld_disconnect_spi_from_jtag(struct pld_device *pld_device) +{ + if (!pld_device) + return ERROR_FAIL; + + struct pld_driver *pld_driver = pld_device->driver; + if (!pld_driver) { + LOG_ERROR("pld device has no associated driver"); + return ERROR_FAIL; + } + + if (pld_driver->disconnect_spi_from_jtag) + return pld_driver->disconnect_spi_from_jtag(pld_device); + + return ERROR_FAIL; +} + +COMMAND_HANDLER(handle_pld_create_command) +{ + if (CMD_ARGC < 2) return ERROR_COMMAND_SYNTAX_ERROR; - for (i = 0; pld_drivers[i]; i++) { - if (strcmp(CMD_ARGV[0], pld_drivers[i]->name) == 0) { - struct pld_device *p, *c; - - /* register pld specific commands */ - int retval; - if (pld_drivers[i]->commands) { - retval = register_commands(CMD_CTX, NULL, pld_drivers[i]->commands); - if (retval != ERROR_OK) { - LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]); - return ERROR_FAIL; - } - } - - c = malloc(sizeof(struct pld_device)); - c->driver = pld_drivers[i]; - c->next = NULL; - - retval = CALL_COMMAND_HANDLER( - pld_drivers[i]->pld_device_command, c); - if (retval != ERROR_OK) { - LOG_ERROR("'%s' driver rejected pld device", - CMD_ARGV[0]); - free(c); - return ERROR_OK; - } - - /* put pld device in linked list */ - if (pld_devices) { - /* find last pld device */ - for (p = pld_devices; p && p->next; p = p->next) - ; - if (p) - p->next = c; - } else - pld_devices = c; - - found = 1; + struct pld_driver *pld_driver = NULL; + + for (int i = 0; pld_drivers[i]; i++) { + if (strcmp(CMD_ARGV[1], pld_drivers[i]->name) == 0) { + pld_driver = pld_drivers[i]; + break; + } + } + + if (!pld_driver) { + LOG_ERROR("pld driver '%s' not found", CMD_ARGV[1]); + return ERROR_FAIL; /* exit(-1); */ + } + + if (get_pld_device_by_name(CMD_ARGV[0])) { + LOG_ERROR("pld device with name '%s' already exists", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct pld_device *pld_device = malloc(sizeof(struct pld_device)); + if (!pld_device) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + pld_device->driver = pld_driver; + pld_device->next = NULL; + + int retval = CALL_COMMAND_HANDLER(pld_driver->pld_create_command, pld_device); + if (retval != ERROR_OK) { + LOG_ERROR("'%s' driver rejected pld device", + CMD_ARGV[1]); + free(pld_device); + return ERROR_OK; + } + pld_device->name = strdup(CMD_ARGV[0]); + if (!pld_device->name) { + LOG_ERROR("Out of memory"); + free(pld_device); + return ERROR_FAIL; + } + + /* register pld specific commands */ + if (pld_driver->commands) { + retval = register_commands(CMD_CTX, NULL, pld_driver->commands); + if (retval != ERROR_OK) { + LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[1]); + free(pld_device->name); + free(pld_device); + return ERROR_FAIL; } } - /* no matching pld driver found */ - if (!found) { - LOG_ERROR("pld driver '%s' not found", CMD_ARGV[0]); - exit(-1); + if (pld_devices) { + /* find last pld device */ + struct pld_device *p = pld_devices; + for (; p && p->next; p = p->next) + ; + if (p) + p->next = pld_device; + } else { + pld_devices = pld_device; } return ERROR_OK; @@ -110,7 +241,7 @@ COMMAND_HANDLER(handle_pld_devices_command) } for (p = pld_devices; p; p = p->next) - command_print(CMD, "#%i: %s", i++, p->driver->name); + command_print(CMD, "#%i: %s (driver: %s)", i++, p->name, p->driver->name); return ERROR_OK; } @@ -126,27 +257,39 @@ COMMAND_HANDLER(handle_pld_load_command) if (CMD_ARGC < 2) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned dev_id; - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], dev_id); - p = get_pld_device_by_num(dev_id); + p = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); if (!p) { - command_print(CMD, "pld device '#%s' is out of bounds", CMD_ARGV[0]); + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); return ERROR_OK; } + struct stat input_stat; + if (stat(CMD_ARGV[1], &input_stat) == -1) { + LOG_ERROR("couldn't stat() %s: %s", CMD_ARGV[1], strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (S_ISDIR(input_stat.st_mode)) { + LOG_ERROR("%s is a directory", CMD_ARGV[1]); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + if (input_stat.st_size == 0) { + LOG_ERROR("Empty file %s", CMD_ARGV[1]); + return ERROR_PLD_FILE_LOAD_FAILED; + } + retval = p->driver->load(p, CMD_ARGV[1]); if (retval != ERROR_OK) { - command_print(CMD, "failed loading file %s to pld device %u", - CMD_ARGV[1], dev_id); - switch (retval) { - } + command_print(CMD, "failed loading file %s to pld device %s", + CMD_ARGV[1], CMD_ARGV[0]); return retval; } else { gettimeofday(&end, NULL); timeval_subtract(&duration, &end, &start); - command_print(CMD, "loaded file %s to pld device %u in %jis %jius", - CMD_ARGV[1], dev_id, + command_print(CMD, "loaded file %s to pld device %s in %jis %jius", + CMD_ARGV[1], CMD_ARGV[0], (intmax_t)duration.tv_sec, (intmax_t)duration.tv_usec); } @@ -166,7 +309,7 @@ static const struct command_registration pld_exec_command_handlers[] = { .handler = handle_pld_load_command, .mode = COMMAND_EXEC, .help = "load configuration file into PLD", - .usage = "pld_num filename", + .usage = "pld_name filename", }, COMMAND_REGISTRATION_DONE }; @@ -197,11 +340,11 @@ COMMAND_HANDLER(handle_pld_init_command) static const struct command_registration pld_config_command_handlers[] = { { - .name = "device", + .name = "create", .mode = COMMAND_CONFIG, - .handler = handle_pld_device_command, - .help = "configure a PLD device", - .usage = "driver_name [driver_args ... ]", + .handler = handle_pld_create_command, + .help = "create a PLD device", + .usage = "name.pld driver_name [driver_args ... ]", }, { .name = "init", diff --git a/src/pld/pld.h b/src/pld/pld.h index a7cd20f641..a6e2e0fc8d 100644 --- a/src/pld/pld.h +++ b/src/pld/pld.h @@ -12,30 +12,59 @@ struct pld_device; -#define __PLD_DEVICE_COMMAND(name) \ +#define __PLD_CREATE_COMMAND(name) \ COMMAND_HELPER(name, struct pld_device *pld) +struct pld_ipdbg_hub { + struct jtag_tap *tap; + unsigned int user_ir_code; +}; + +int pld_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction); +int pld_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir); + +int pld_get_jtagspi_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits, + unsigned int *trailing_write_bits); +int pld_connect_spi_to_jtag(struct pld_device *pld_device); +int pld_disconnect_spi_from_jtag(struct pld_device *pld_device); + struct pld_driver { const char *name; - __PLD_DEVICE_COMMAND((*pld_device_command)); + __PLD_CREATE_COMMAND((*pld_create_command)); const struct command_registration *commands; int (*load)(struct pld_device *pld_device, const char *filename); + int (*get_ipdbg_hub)(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub); + int (*has_jtagspi_instruction)(struct pld_device *device, bool *has_instruction); + int (*get_jtagspi_userircode)(struct pld_device *pld_device, unsigned int *ir); + int (*connect_spi_to_jtag)(struct pld_device *pld_device); + int (*disconnect_spi_from_jtag)(struct pld_device *pld_device); + int (*get_stuff_bits)(struct pld_device *pld_device, unsigned int *facing_read_bits, + unsigned int *trailing_write_bits); }; -#define PLD_DEVICE_COMMAND_HANDLER(name) \ - static __PLD_DEVICE_COMMAND(name) +#define PLD_CREATE_COMMAND_HANDLER(name) \ + static __PLD_CREATE_COMMAND(name) struct pld_device { struct pld_driver *driver; void *driver_priv; struct pld_device *next; + char *name; }; int pld_register_commands(struct command_context *cmd_ctx); -struct pld_device *get_pld_device_by_num(int num); +struct pld_device *get_pld_device_by_name(const char *name); +struct pld_device *get_pld_device_by_name_or_numstr(const char *str); #define ERROR_PLD_DEVICE_INVALID (-1000) #define ERROR_PLD_FILE_LOAD_FAILED (-1001) +extern struct pld_driver efinix_pld; +extern struct pld_driver gatemate_pld; +extern struct pld_driver gowin_pld; +extern struct pld_driver intel_pld; +extern struct pld_driver lattice_pld; +extern struct pld_driver virtex2_pld; + #endif /* OPENOCD_PLD_PLD_H */ diff --git a/src/pld/raw_bit.c b/src/pld/raw_bit.c new file mode 100644 index 0000000000..0c3b92e7e9 --- /dev/null +++ b/src/pld/raw_bit.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "raw_bit.h" +#include "pld.h" + +#include <helper/system.h> +#include <helper/log.h> + + +int cpld_read_raw_bit_file(struct raw_bit_file *bit_file, const char *filename) +{ + FILE *input_file = fopen(filename, "rb"); + + if (!input_file) { + LOG_ERROR("Couldn't open %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + fseek(input_file, 0, SEEK_END); + long length = ftell(input_file); + fseek(input_file, 0, SEEK_SET); + + if (length < 0) { + fclose(input_file); + LOG_ERROR("Failed to get length of file %s: %s", filename, strerror(errno)); + return ERROR_PLD_FILE_LOAD_FAILED; + } + bit_file->length = (size_t)length; + + bit_file->data = malloc(bit_file->length); + if (!bit_file->data) { + fclose(input_file); + LOG_ERROR("Out of memory"); + return ERROR_PLD_FILE_LOAD_FAILED; + } + + size_t read_count = fread(bit_file->data, sizeof(char), bit_file->length, input_file); + fclose(input_file); + if (read_count != bit_file->length) { + free(bit_file->data); + bit_file->data = NULL; + return ERROR_PLD_FILE_LOAD_FAILED; + } + + return ERROR_OK; +} diff --git a/src/pld/raw_bit.h b/src/pld/raw_bit.h new file mode 100644 index 0000000000..583ff76e99 --- /dev/null +++ b/src/pld/raw_bit.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2022 by Daniel Anselmi * + * danselmi@gmx.ch * + ***************************************************************************/ + +#ifndef OPENOCD_PLD_RAW_BIN_H +#define OPENOCD_PLD_RAW_BIN_H + +#include <stddef.h> +#include <stdint.h> + +struct raw_bit_file { + size_t length; + uint8_t *data; +}; + +int cpld_read_raw_bit_file(struct raw_bit_file *bit_file, const char *filename); + +#endif /* OPENOCD_PLD_RAW_BIN_H */ diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c index b73f5d123c..3dff90621a 100644 --- a/src/pld/virtex2.c +++ b/src/pld/virtex2.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -13,18 +13,33 @@ #include "xilinx_bit.h" #include "pld.h" -static int virtex2_set_instr(struct jtag_tap *tap, uint32_t new_instr) +static const struct virtex2_command_set virtex2_default_commands = { + .cfg_out = 0x04, + .cfg_in = 0x05, + .jprog_b = 0x0b, + .jstart = 0x0c, + .jshutdown = 0x0d, + .bypass = 0x3f, + .user = {0x02, 0x03}, + .num_user = 2, /* virtex II has only 2 user instructions */ +}; + +static int virtex2_set_instr(struct jtag_tap *tap, uint64_t new_instr) { if (!tap) return ERROR_FAIL; - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { + if (buf_get_u64(tap->cur_instr, 0, tap->ir_length) != new_instr) { struct scan_field field; field.num_bits = tap->ir_length; void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } field.out_value = t; - buf_set_u32(t, 0, field.num_bits, new_instr); + buf_set_u64(t, 0, field.num_bits, new_instr); field.in_value = NULL; jtag_add_ir_scan(tap, &field, TAP_IDLE); @@ -44,6 +59,10 @@ static int virtex2_send_32(struct pld_device *pld_device, int i; values = malloc(num_words * 4); + if (!values) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } scan_field.num_bits = num_words * 32; scan_field.out_value = values; @@ -52,7 +71,11 @@ static int virtex2_send_32(struct pld_device *pld_device, for (i = 0; i < num_words; i++) buf_set_u32(values + 4 * i, 0, 32, flip_u32(*words++, 32)); - virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */ + int retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.cfg_in); + if (retval != ERROR_OK) { + free(values); + return retval; + } jtag_add_dr_scan(virtex2_info->tap, 1, &scan_field, TAP_DRPAUSE); @@ -77,7 +100,9 @@ static int virtex2_receive_32(struct pld_device *pld_device, scan_field.out_value = NULL; scan_field.in_value = NULL; - virtex2_set_instr(virtex2_info->tap, 0x4); /* CFG_OUT */ + int retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.cfg_out); + if (retval != ERROR_OK) + return retval; while (num_words--) { scan_field.in_value = (uint8_t *)words; @@ -103,15 +128,101 @@ static int virtex2_read_stat(struct pld_device *pld_device, uint32_t *status) data[2] = 0x20000000; /* NOOP (Type 1, read, address 0, 0 words */ data[3] = 0x20000000; /* NOOP */ data[4] = 0x20000000; /* NOOP */ - virtex2_send_32(pld_device, 5, data); + int retval = virtex2_send_32(pld_device, 5, data); + if (retval != ERROR_OK) + return retval; - virtex2_receive_32(pld_device, 1, status); + retval = virtex2_receive_32(pld_device, 1, status); + if (retval != ERROR_OK) + return retval; - jtag_execute_queue(); + retval = jtag_execute_queue(); + if (retval == ERROR_OK) + LOG_DEBUG("status: 0x%8.8" PRIx32, *status); - LOG_DEBUG("status: 0x%8.8" PRIx32 "", *status); + return retval; +} - return ERROR_OK; +static int virtex2_program(struct pld_device *pld_device) +{ + struct virtex2_pld_device *virtex2_info = pld_device->driver_priv; + if (!virtex2_info) + return ERROR_FAIL; + + int retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jshutdown); + if (retval != ERROR_OK) + return retval; + + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jprog_b); + if (retval != ERROR_OK) + return retval; + + jtag_add_runtest(62000, TAP_IDLE); + if (!(virtex2_info->no_jstart)) { + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jstart); + if (retval != ERROR_OK) + return retval; + } + + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.bypass); + if (retval != ERROR_OK) + return retval; + jtag_add_runtest(2000, TAP_IDLE); + + return jtag_execute_queue(); +} + +static int virtex2_load_prepare(struct pld_device *pld_device) +{ + struct virtex2_pld_device *virtex2_info = pld_device->driver_priv; + int retval; + + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jprog_b); + if (retval != ERROR_OK) + return retval; + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + jtag_add_sleep(1000); + + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.cfg_in); + if (retval != ERROR_OK) + return retval; + + return jtag_execute_queue(); +} + +static int virtex2_load_cleanup(struct pld_device *pld_device) +{ + struct virtex2_pld_device *virtex2_info = pld_device->driver_priv; + int retval; + + jtag_add_tlr(); + + if (!(virtex2_info->no_jstart)) { + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jstart); + if (retval != ERROR_OK) + return retval; + } + jtag_add_runtest(13, TAP_IDLE); + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.bypass); + if (retval != ERROR_OK) + return retval; + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.bypass); + if (retval != ERROR_OK) + return retval; + if (!(virtex2_info->no_jstart)) { + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.jstart); + if (retval != ERROR_OK) + return retval; + } + jtag_add_runtest(13, TAP_IDLE); + retval = virtex2_set_instr(virtex2_info->tap, virtex2_info->command_set.bypass); + if (retval != ERROR_OK) + return retval; + + return jtag_execute_queue(); } static int virtex2_load(struct pld_device *pld_device, const char *filename) @@ -128,12 +239,11 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename) if (retval != ERROR_OK) return retval; - virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */ - jtag_execute_queue(); - jtag_add_sleep(1000); - - virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */ - jtag_execute_queue(); + retval = virtex2_load_prepare(pld_device); + if (retval != ERROR_OK) { + xilinx_free_bit_file(&bit_file); + return retval; + } for (i = 0; i < bit_file.length; i++) bit_file.data[i] = flip_u32(bit_file.data[i], 8); @@ -142,22 +252,33 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename) field.out_value = bit_file.data; jtag_add_dr_scan(virtex2_info->tap, 1, &field, TAP_DRPAUSE); - jtag_execute_queue(); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + xilinx_free_bit_file(&bit_file); + return retval; + } - jtag_add_tlr(); + retval = virtex2_load_cleanup(pld_device); - if (!(virtex2_info->no_jstart)) - virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ - jtag_add_runtest(13, TAP_IDLE); - virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ - virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ - if (!(virtex2_info->no_jstart)) - virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ - jtag_add_runtest(13, TAP_IDLE); - virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ - jtag_execute_queue(); + xilinx_free_bit_file(&bit_file); - return ERROR_OK; + return retval; +} + +COMMAND_HANDLER(virtex2_handle_refresh_command) +{ + struct pld_device *device; + + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + return virtex2_program(device); } COMMAND_HANDLER(virtex2_handle_read_stat_command) @@ -168,42 +289,139 @@ COMMAND_HANDLER(virtex2_handle_read_stat_command) if (CMD_ARGC < 1) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned dev_id; - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], dev_id); - device = get_pld_device_by_num(dev_id); + device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]); if (!device) { - command_print(CMD, "pld device '#%s' is out of bounds", CMD_ARGV[0]); - return ERROR_OK; + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + int retval = virtex2_read_stat(device, &status); + if (retval != ERROR_OK) { + command_print(CMD, "cannot read virtex2 status register"); + return retval; } - virtex2_read_stat(device, &status); + command_print(CMD, "virtex2 status register: 0x%8.8" PRIx32, status); - command_print(CMD, "virtex2 status register: 0x%8.8" PRIx32 "", status); + return ERROR_OK; +} + +static int xilinx_get_ipdbg_hub(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub) +{ + if (!pld_device) + return ERROR_FAIL; + + struct virtex2_pld_device *pld_device_info = pld_device->driver_priv; + + if (!pld_device_info || !pld_device_info->tap) + return ERROR_FAIL; + + hub->tap = pld_device_info->tap; + if (user_num < 1 || (unsigned int)user_num > pld_device_info->command_set.num_user) { + LOG_ERROR("device has only user register 1 to %d", pld_device_info->command_set.num_user); + return ERROR_FAIL; + } + hub->user_ir_code = pld_device_info->command_set.user[user_num - 1]; return ERROR_OK; } -PLD_DEVICE_COMMAND_HANDLER(virtex2_pld_device_command) +static int xilinx_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir) { - struct jtag_tap *tap; + if (!pld_device || !pld_device->driver_priv) + return ERROR_FAIL; + struct virtex2_pld_device *pld_device_info = pld_device->driver_priv; - struct virtex2_pld_device *virtex2_info; + if (pld_device_info->command_set.num_user < 1) { + LOG_ERROR("code for command 'select user1' is unknown"); + return ERROR_FAIL; + } - if (CMD_ARGC < 2) + *ir = pld_device_info->command_set.user[0]; + return ERROR_OK; +} + +COMMAND_HANDLER(virtex2_handle_set_instuction_codes_command) +{ + if (CMD_ARGC < 6 || CMD_ARGC > (6 + VIRTEX2_MAX_USER_INSTRUCTIONS)) return ERROR_COMMAND_SYNTAX_ERROR; - tap = jtag_tap_by_string(CMD_ARGV[1]); + struct pld_device *device = get_pld_device_by_name(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct virtex2_pld_device *virtex2_info = device->driver_priv; + if (!virtex2_info) + return ERROR_FAIL; + + struct virtex2_command_set instr_codes; + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], instr_codes.cfg_out); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[2], instr_codes.cfg_in); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], instr_codes.jprog_b); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[4], instr_codes.jstart); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[5], instr_codes.jshutdown); + instr_codes.bypass = 0xffffffffffffffffULL; + + unsigned int num_user = CMD_ARGC - 6; + for (unsigned int i = 0; i < num_user; ++i) + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[6 + i], instr_codes.user[i]); + instr_codes.num_user = num_user; + + virtex2_info->command_set = instr_codes; + return ERROR_OK; +} + +COMMAND_HANDLER(virtex2_handle_set_user_codes_command) +{ + if (CMD_ARGC < 2 || CMD_ARGC > (1 + VIRTEX2_MAX_USER_INSTRUCTIONS)) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct pld_device *device = get_pld_device_by_name(CMD_ARGV[0]); + if (!device) { + command_print(CMD, "pld device '#%s' is unknown", CMD_ARGV[0]); + return ERROR_FAIL; + } + + struct virtex2_pld_device *virtex2_info = device->driver_priv; + if (!virtex2_info) + return ERROR_FAIL; + + uint64_t user[VIRTEX2_MAX_USER_INSTRUCTIONS]; + unsigned int num_user = CMD_ARGC - 1; + for (unsigned int i = 0; i < num_user; ++i) + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1 + i], user[i]); + virtex2_info->command_set.num_user = num_user; + memcpy(virtex2_info->command_set.user, user, num_user * sizeof(uint64_t)); + return ERROR_OK; +} + +PLD_CREATE_COMMAND_HANDLER(virtex2_pld_create_command) +{ + if (CMD_ARGC < 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (strcmp(CMD_ARGV[2], "-chain-position") != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[3]); if (!tap) { - command_print(CMD, "Tap: %s does not exist", CMD_ARGV[1]); - return ERROR_OK; + command_print(CMD, "Tap: %s does not exist", CMD_ARGV[3]); + return ERROR_FAIL; } - virtex2_info = malloc(sizeof(struct virtex2_pld_device)); + struct virtex2_pld_device *virtex2_info = malloc(sizeof(struct virtex2_pld_device)); + if (!virtex2_info) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } virtex2_info->tap = tap; + virtex2_info->command_set = virtex2_default_commands; virtex2_info->no_jstart = 0; - if (CMD_ARGC >= 3) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], virtex2_info->no_jstart); + if (CMD_ARGC >= 5 && strcmp(CMD_ARGV[4], "-no_jstart") == 0) + virtex2_info->no_jstart = 1; pld->driver_priv = virtex2_info; @@ -216,10 +434,30 @@ static const struct command_registration virtex2_exec_command_handlers[] = { .mode = COMMAND_EXEC, .handler = virtex2_handle_read_stat_command, .help = "read status register", - .usage = "pld_num", + .usage = "pld_name", + }, { + .name = "set_instr_codes", + .mode = COMMAND_ANY, + .handler = virtex2_handle_set_instuction_codes_command, + .help = "set instructions codes used for loading the bitstream/refreshing/jtag-hub", + .usage = "pld_name cfg_out cfg_in jprogb jstart jshutdown" + " [user1 [user2 [user3 [user4]]]]", + }, { + .name = "set_user_codes", + .mode = COMMAND_ANY, + .handler = virtex2_handle_set_user_codes_command, + .help = "set instructions codes used for jtag-hub", + .usage = "pld_name user1 [user2 [user3 [user4]]]", + }, { + .name = "refresh", + .mode = COMMAND_EXEC, + .handler = virtex2_handle_refresh_command, + .help = "start loading of configuration (program)", + .usage = "pld_name", }, COMMAND_REGISTRATION_DONE }; + static const struct command_registration virtex2_command_handler[] = { { .name = "virtex2", @@ -234,6 +472,8 @@ static const struct command_registration virtex2_command_handler[] = { struct pld_driver virtex2_pld = { .name = "virtex2", .commands = virtex2_command_handler, - .pld_device_command = &virtex2_pld_device_command, + .pld_create_command = &virtex2_pld_create_command, .load = &virtex2_load, + .get_ipdbg_hub = xilinx_get_ipdbg_hub, + .get_jtagspi_userircode = xilinx_get_jtagspi_userircode, }; diff --git a/src/pld/virtex2.h b/src/pld/virtex2.h index 05558f709d..b69e3c97a9 100644 --- a/src/pld/virtex2.h +++ b/src/pld/virtex2.h @@ -10,9 +10,23 @@ #include <jtag/jtag.h> +#define VIRTEX2_MAX_USER_INSTRUCTIONS 4 + +struct virtex2_command_set { + uint64_t cfg_out; + uint64_t cfg_in; + uint64_t jprog_b; + uint64_t jstart; + uint64_t jshutdown; + uint64_t bypass; + uint64_t user[VIRTEX2_MAX_USER_INSTRUCTIONS]; + unsigned int num_user; +}; + struct virtex2_pld_device { struct jtag_tap *tap; int no_jstart; + struct virtex2_command_set command_set; }; #endif /* OPENOCD_PLD_VIRTEX2_H */ diff --git a/src/pld/xilinx_bit.c b/src/pld/xilinx_bit.c index 361c11b9db..e4cc52ef97 100644 --- a/src/pld/xilinx_bit.c +++ b/src/pld/xilinx_bit.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -13,7 +13,6 @@ #include "pld.h" #include <helper/log.h> -#include <sys/stat.h> #include <helper/system.h> static int read_section(FILE *input_file, int length_size, char section, @@ -60,53 +59,59 @@ static int read_section(FILE *input_file, int length_size, char section, int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename) { FILE *input_file; - struct stat input_stat; int read_count; if (!filename || !bit_file) return ERROR_COMMAND_SYNTAX_ERROR; - if (stat(filename, &input_stat) == -1) { - LOG_ERROR("couldn't stat() %s: %s", filename, strerror(errno)); - return ERROR_PLD_FILE_LOAD_FAILED; - } - - if (S_ISDIR(input_stat.st_mode)) { - LOG_ERROR("%s is a directory", filename); - return ERROR_PLD_FILE_LOAD_FAILED; - } - - if (input_stat.st_size == 0) { - LOG_ERROR("Empty file %s", filename); - return ERROR_PLD_FILE_LOAD_FAILED; - } - input_file = fopen(filename, "rb"); if (!input_file) { LOG_ERROR("couldn't open %s: %s", filename, strerror(errno)); return ERROR_PLD_FILE_LOAD_FAILED; } + bit_file->source_file = NULL; + bit_file->part_name = NULL; + bit_file->date = NULL; + bit_file->time = NULL; + bit_file->data = NULL; + read_count = fread(bit_file->unknown_header, 1, 13, input_file); if (read_count != 13) { LOG_ERROR("couldn't read unknown_header from file '%s'", filename); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; } - if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK) + if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK) { + xilinx_free_bit_file(bit_file); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; + } - if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK) + if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK) { + xilinx_free_bit_file(bit_file); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; + } - if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK) + if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK) { + xilinx_free_bit_file(bit_file); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; + } - if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK) + if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK) { + xilinx_free_bit_file(bit_file); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; + } - if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK) + if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK) { + xilinx_free_bit_file(bit_file); + fclose(input_file); return ERROR_PLD_FILE_LOAD_FAILED; + } LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name, bit_file->date, bit_file->time, bit_file->length); @@ -115,3 +120,12 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename) return ERROR_OK; } + +void xilinx_free_bit_file(struct xilinx_bit_file *bit_file) +{ + free(bit_file->source_file); + free(bit_file->part_name); + free(bit_file->date); + free(bit_file->time); + free(bit_file->data); +} diff --git a/src/pld/xilinx_bit.h b/src/pld/xilinx_bit.h index e30ed23377..f443bf70eb 100644 --- a/src/pld/xilinx_bit.h +++ b/src/pld/xilinx_bit.h @@ -22,4 +22,6 @@ struct xilinx_bit_file { int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename); +void xilinx_free_bit_file(struct xilinx_bit_file *bit_file); + #endif /* OPENOCD_PLD_XILINX_BIT_H */ diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am index f00d7194ed..5267fea248 100644 --- a/src/rtos/Makefile.am +++ b/src/rtos/Makefile.am @@ -10,16 +10,18 @@ noinst_LTLIBRARIES += %D%/librtos.la %D%/rtos_mqx_stackings.c \ %D%/rtos_ucos_iii_stackings.c \ %D%/rtos_riot_stackings.c \ - %D%/FreeRTOS.c \ - %D%/ThreadX.c \ - %D%/eCos.c \ + %D%/rtos_nuttx_stackings.c \ + %D%/freertos.c \ + %D%/threadx.c \ + %D%/ecos.c \ %D%/linux.c \ %D%/chibios.c \ %D%/chromium-ec.c \ - %D%/embKernel.c \ + %D%/embkernel.c \ %D%/mqx.c \ - %D%/uCOS-III.c \ + %D%/ucos_iii.c \ %D%/nuttx.c \ + %D%/rtkernel.c \ %D%/hwthread.c \ %D%/zephyr.c \ %D%/riot.c \ @@ -32,4 +34,4 @@ noinst_LTLIBRARIES += %D%/librtos.la %D%/rtos_mqx_stackings.h \ %D%/rtos_riot_stackings.h \ %D%/rtos_ucos_iii_stackings.h \ - %D%/nuttx_header.h + %D%/rtos_nuttx_stackings.h diff --git a/src/rtos/chibios.c b/src/rtos/chibios.c index 001abfa24c..0cd99e4720 100644 --- a/src/rtos/chibios.c +++ b/src/rtos/chibios.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2012 by Matthias Blaicher * @@ -15,7 +15,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "target/armv7m.h" #include "target/cortex_m.h" #include "rtos.h" @@ -32,7 +31,7 @@ struct chibios_chdebug { char ch_identifier[4]; /**< @brief Always set to "main". */ uint8_t ch_zero; /**< @brief Must be zero. */ uint8_t ch_size; /**< @brief Size of this structure. */ - uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */ + uint8_t ch_version[2]; /**< @brief Encoded ChibiOS/RT version. */ uint8_t ch_ptrsize; /**< @brief Size of a pointer. */ uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */ uint8_t ch_threadsize; /**< @brief Size of a @p Thread struct. */ @@ -80,12 +79,12 @@ struct chibios_params { static struct chibios_params chibios_params_list[] = { { "cortex_m", /* target_name */ - 0, + NULL, NULL, /* stacking_info */ }, { "hla_target", /* target_name */ - 0, + NULL, NULL, /* stacking_info */ } }; @@ -97,7 +96,7 @@ static int chibios_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); static int chibios_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct rtos_type chibios_rtos = { +const struct rtos_type chibios_rtos = { .name = "chibios", .detect_rtos = chibios_detect_rtos, @@ -172,13 +171,7 @@ static int chibios_update_memory_signature(struct rtos *rtos) " expected. Assuming compatibility..."); } - /* Convert endianness of version field */ - const uint8_t *versiontarget = (const uint8_t *) - &signature->ch_version; - signature->ch_version = rtos->target->endianness == TARGET_LITTLE_ENDIAN ? - le_to_h_u32(versiontarget) : be_to_h_u32(versiontarget); - - const uint16_t ch_version = signature->ch_version; + const uint16_t ch_version = target_buffer_get_u16(rtos->target, signature->ch_version); LOG_INFO("Successfully loaded memory map of ChibiOS/RT target " "running version %i.%i.%i", GET_CH_KERNEL_MAJOR(ch_version), GET_CH_KERNEL_MINOR(ch_version), GET_CH_KERNEL_PATCH(ch_version)); @@ -198,7 +191,7 @@ static int chibios_update_memory_signature(struct rtos *rtos) errfree: /* Error reading the ChibiOS memory structure */ free(signature); - param->signature = 0; + param->signature = NULL; return -1; } @@ -428,9 +421,11 @@ static int chibios_update_threads(struct rtos *rtos) else state_desc = "Unknown"; - curr_thrd_details->extra_info_str = malloc(strlen( - state_desc)+8); - sprintf(curr_thrd_details->extra_info_str, "State: %s", state_desc); + curr_thrd_details->extra_info_str = alloc_printf("State: %s", state_desc); + if (!curr_thrd_details->extra_info_str) { + LOG_ERROR("Could not allocate space for thread state description"); + return -1; + } curr_thrd_details->exists = true; @@ -468,9 +463,9 @@ static int chibios_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, return -1; /* Update stacking if it can only be determined from runtime information */ - if ((param->stacking_info == 0) && + if (!param->stacking_info && (chibios_update_stacking(rtos) != ERROR_OK)) { - LOG_ERROR("Failed to determine exact stacking for the target type %s", rtos->target->type->name); + LOG_ERROR("Failed to determine exact stacking for the target type %s", target_type_name(rtos->target)); return -1; } @@ -518,12 +513,12 @@ static bool chibios_detect_rtos(struct target *target) static int chibios_create(struct target *target) { for (unsigned int i = 0; i < ARRAY_SIZE(chibios_params_list); i++) - if (strcmp(chibios_params_list[i].target_name, target->type->name) == 0) { + if (strcmp(chibios_params_list[i].target_name, target_type_name(target)) == 0) { target->rtos->rtos_specific_params = (void *)&chibios_params_list[i]; - return 0; + return ERROR_OK; } LOG_WARNING("Could not find target \"%s\" in ChibiOS compatibility " - "list", target->type->name); - return -1; + "list", target_type_name(target)); + return ERROR_FAIL; } diff --git a/src/rtos/chromium-ec.c b/src/rtos/chromium-ec.c index 782a4620a9..dbfe3b3c68 100644 --- a/src/rtos/chromium-ec.c +++ b/src/rtos/chromium-ec.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018 National Instruments Corp @@ -14,7 +14,6 @@ #include <helper/bits.h> #include <rtos/rtos.h> #include <target/target.h> -#include <target/target_type.h> #include "rtos_standard_stackings.h" @@ -120,7 +119,7 @@ static int chromium_ec_create(struct target *target) size_t t; for (t = 0; t < ARRAY_SIZE(chromium_ec_params_list); t++) - if (!strcmp(chromium_ec_params_list[t].target_name, target->type->name)) { + if (!strcmp(chromium_ec_params_list[t].target_name, target_type_name(target))) { params = malloc(sizeof(*params)); if (!params) { LOG_ERROR("Chromium-EC: out of memory"); @@ -133,11 +132,11 @@ static int chromium_ec_create(struct target *target) target->rtos->thread_details = NULL; target->rtos->thread_count = 0; - LOG_INFO("Chromium-EC: Using target: %s", target->type->name); + LOG_INFO("Chromium-EC: Using target: %s", target_type_name(target)); return ERROR_OK; } - LOG_ERROR("Chromium-EC: target not supported: %s", target->type->name); + LOG_ERROR("Chromium-EC: target not supported: %s", target_type_name(target)); return ERROR_FAIL; } diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c deleted file mode 100644 index 8e982dacb4..0000000000 --- a/src/rtos/eCos.c +++ /dev/null @@ -1,375 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/time_support.h> -#include <jtag/jtag.h> -#include "target/target.h" -#include "target/target_type.h" -#include "rtos.h" -#include "helper/log.h" -#include "helper/types.h" -#include "rtos_ecos_stackings.h" - -static bool ecos_detect_rtos(struct target *target); -static int ecos_create(struct target *target); -static int ecos_update_threads(struct rtos *rtos); -static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); -static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); - -struct ecos_thread_state { - int value; - const char *desc; -}; - -static const struct ecos_thread_state ecos_thread_states[] = { - { 0, "Ready" }, - { 1, "Sleeping" }, - { 2, "Countsleep" }, - { 4, "Suspended" }, - { 8, "Creating" }, - { 16, "Exited" } -}; - -#define ECOS_NUM_STATES ARRAY_SIZE(ecos_thread_states) - -struct ecos_params { - const char *target_name; - unsigned char pointer_width; - unsigned char thread_stack_offset; - unsigned char thread_name_offset; - unsigned char thread_state_offset; - unsigned char thread_next_offset; - unsigned char thread_uniqueid_offset; - const struct rtos_register_stacking *stacking_info; -}; - -static const struct ecos_params ecos_params_list[] = { - { - "cortex_m", /* target_name */ - 4, /* pointer_width; */ - 0x0c, /* thread_stack_offset; */ - 0x9c, /* thread_name_offset; */ - 0x3c, /* thread_state_offset; */ - 0xa0, /* thread_next_offset */ - 0x4c, /* thread_uniqueid_offset */ - &rtos_ecos_cortex_m3_stacking /* stacking_info */ - } -}; - -enum ecos_symbol_values { - ECOS_VAL_THREAD_LIST = 0, - ECOS_VAL_CURRENT_THREAD_PTR = 1 -}; - -static const char * const ecos_symbol_list[] = { - "Cyg_Thread::thread_list", - "Cyg_Scheduler_Base::current_thread", - NULL -}; - -const struct rtos_type ecos_rtos = { - .name = "eCos", - - .detect_rtos = ecos_detect_rtos, - .create = ecos_create, - .update_threads = ecos_update_threads, - .get_thread_reg_list = ecos_get_thread_reg_list, - .get_symbol_list_to_lookup = ecos_get_symbol_list_to_lookup, - -}; - -static int ecos_update_threads(struct rtos *rtos) -{ - int retval; - int tasks_found = 0; - int thread_list_size = 0; - const struct ecos_params *param; - - if (!rtos) - return -1; - - if (!rtos->rtos_specific_params) - return -3; - - param = (const struct ecos_params *) rtos->rtos_specific_params; - - if (!rtos->symbols) { - LOG_ERROR("No symbols for eCos"); - return -4; - } - - if (rtos->symbols[ECOS_VAL_THREAD_LIST].address == 0) { - LOG_ERROR("Don't have the thread list head"); - return -2; - } - - /* wipe out previous thread details if any */ - rtos_free_threadlist(rtos); - - /* determine the number of current threads */ - uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; - uint32_t thread_index; - target_read_buffer(rtos->target, - thread_list_head, - param->pointer_width, - (uint8_t *) &thread_index); - uint32_t first_thread = thread_index; - do { - thread_list_size++; - retval = target_read_buffer(rtos->target, - thread_index + param->thread_next_offset, - param->pointer_width, - (uint8_t *) &thread_index); - if (retval != ERROR_OK) - return retval; - } while (thread_index != first_thread); - - /* read the current thread id */ - uint32_t current_thread_addr; - retval = target_read_buffer(rtos->target, - rtos->symbols[ECOS_VAL_CURRENT_THREAD_PTR].address, - 4, - (uint8_t *)¤t_thread_addr); - if (retval != ERROR_OK) - return retval; - rtos->current_thread = 0; - retval = target_read_buffer(rtos->target, - current_thread_addr + param->thread_uniqueid_offset, - 2, - (uint8_t *)&rtos->current_thread); - if (retval != ERROR_OK) { - LOG_ERROR("Could not read eCos current thread from target"); - return retval; - } - - if ((thread_list_size == 0) || (rtos->current_thread == 0)) { - /* Either : No RTOS threads - there is always at least the current execution though */ - /* OR : No current thread - all threads suspended - show the current execution - * of idling */ - char tmp_str[] = "Current Execution"; - thread_list_size++; - tasks_found++; - rtos->thread_details = malloc( - sizeof(struct thread_detail) * thread_list_size); - rtos->thread_details->threadid = 1; - rtos->thread_details->exists = true; - rtos->thread_details->extra_info_str = NULL; - rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str)); - strcpy(rtos->thread_details->thread_name_str, tmp_str); - - if (thread_list_size == 0) { - rtos->thread_count = 1; - return ERROR_OK; - } - } else { - /* create space for new thread details */ - rtos->thread_details = malloc( - sizeof(struct thread_detail) * thread_list_size); - } - - /* loop over all threads */ - thread_index = first_thread; - do { - - #define ECOS_THREAD_NAME_STR_SIZE (200) - char tmp_str[ECOS_THREAD_NAME_STR_SIZE]; - unsigned int i = 0; - uint32_t name_ptr = 0; - uint32_t prev_thread_ptr; - - /* Save the thread pointer */ - uint16_t thread_id; - retval = target_read_buffer(rtos->target, - thread_index + param->thread_uniqueid_offset, - 2, - (uint8_t *)&thread_id); - if (retval != ERROR_OK) { - LOG_ERROR("Could not read eCos thread id from target"); - return retval; - } - rtos->thread_details[tasks_found].threadid = thread_id; - - /* read the name pointer */ - retval = target_read_buffer(rtos->target, - thread_index + param->thread_name_offset, - param->pointer_width, - (uint8_t *)&name_ptr); - if (retval != ERROR_OK) { - LOG_ERROR("Could not read eCos thread name pointer from target"); - return retval; - } - - /* Read the thread name */ - retval = - target_read_buffer(rtos->target, - name_ptr, - ECOS_THREAD_NAME_STR_SIZE, - (uint8_t *)&tmp_str); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading thread name from eCos target"); - return retval; - } - tmp_str[ECOS_THREAD_NAME_STR_SIZE-1] = '\x00'; - - if (tmp_str[0] == '\x00') - strcpy(tmp_str, "No Name"); - - rtos->thread_details[tasks_found].thread_name_str = - malloc(strlen(tmp_str)+1); - strcpy(rtos->thread_details[tasks_found].thread_name_str, tmp_str); - - /* Read the thread status */ - int64_t thread_status = 0; - retval = target_read_buffer(rtos->target, - thread_index + param->thread_state_offset, - 4, - (uint8_t *)&thread_status); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading thread state from eCos target"); - return retval; - } - - for (i = 0; (i < ECOS_NUM_STATES) && (ecos_thread_states[i].value != thread_status); i++) { - /* - * empty - */ - } - - const char *state_desc; - if (i < ECOS_NUM_STATES) - state_desc = ecos_thread_states[i].desc; - else - state_desc = "Unknown state"; - - rtos->thread_details[tasks_found].extra_info_str = malloc(strlen( - state_desc)+8); - sprintf(rtos->thread_details[tasks_found].extra_info_str, "State: %s", state_desc); - - rtos->thread_details[tasks_found].exists = true; - - tasks_found++; - prev_thread_ptr = thread_index; - - /* Get the location of the next thread structure. */ - thread_index = rtos->symbols[ECOS_VAL_THREAD_LIST].address; - retval = target_read_buffer(rtos->target, - prev_thread_ptr + param->thread_next_offset, - param->pointer_width, - (uint8_t *) &thread_index); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading next thread pointer in eCos thread list"); - return retval; - } - } while (thread_index != first_thread); - - rtos->thread_count = tasks_found; - return 0; -} - -static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, - struct rtos_reg **reg_list, int *num_regs) -{ - int retval; - const struct ecos_params *param; - - if (!rtos) - return -1; - - if (thread_id == 0) - return -2; - - if (!rtos->rtos_specific_params) - return -3; - - param = (const struct ecos_params *) rtos->rtos_specific_params; - - /* Find the thread with that thread id */ - uint16_t id = 0; - uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; - uint32_t thread_index; - target_read_buffer(rtos->target, thread_list_head, param->pointer_width, - (uint8_t *)&thread_index); - bool done = false; - while (!done) { - retval = target_read_buffer(rtos->target, - thread_index + param->thread_uniqueid_offset, - 2, - (uint8_t *)&id); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading unique id from eCos thread"); - return retval; - } - - if (id == thread_id) { - done = true; - break; - } - target_read_buffer(rtos->target, - thread_index + param->thread_next_offset, - param->pointer_width, - (uint8_t *) &thread_index); - } - - if (done) { - /* Read the stack pointer */ - int64_t stack_ptr = 0; - retval = target_read_buffer(rtos->target, - thread_index + param->thread_stack_offset, - param->pointer_width, - (uint8_t *)&stack_ptr); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading stack frame from eCos thread"); - return retval; - } - - return rtos_generic_stack_read(rtos->target, - param->stacking_info, - stack_ptr, - reg_list, - num_regs); - } - - return -1; -} - -static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) -{ - unsigned int i; - *symbol_list = calloc( - ARRAY_SIZE(ecos_symbol_list), sizeof(struct symbol_table_elem)); - - for (i = 0; i < ARRAY_SIZE(ecos_symbol_list); i++) - (*symbol_list)[i].symbol_name = ecos_symbol_list[i]; - - return 0; -} - -static bool ecos_detect_rtos(struct target *target) -{ - if ((target->rtos->symbols) && - (target->rtos->symbols[ECOS_VAL_THREAD_LIST].address != 0)) { - /* looks like eCos */ - return true; - } - return false; -} - -static int ecos_create(struct target *target) -{ - for (unsigned int i = 0; i < ARRAY_SIZE(ecos_params_list); i++) - if (strcmp(ecos_params_list[i].target_name, target->type->name) == 0) { - target->rtos->rtos_specific_params = (void *)&ecos_params_list[i]; - target->rtos->current_thread = 0; - target->rtos->thread_details = NULL; - return 0; - } - - LOG_ERROR("Could not find target in eCos compatibility list"); - return -1; -} diff --git a/src/rtos/ecos.c b/src/rtos/ecos.c new file mode 100644 index 0000000000..a70084b4fb --- /dev/null +++ b/src/rtos/ecos.c @@ -0,0 +1,1224 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/time_support.h> +#include <jtag/jtag.h> +#include "target/target.h" +#include "target/armv7m.h" +#include "rtos.h" +#include "helper/log.h" +#include "helper/types.h" +#include "helper/bits.h" +#include "rtos_standard_stackings.h" +#include "rtos_ecos_stackings.h" +#include "server/gdb_server.h" + +/* Unfortunately for the moment we are limited to returning the hardwired + * register count (ARMV7M_NUM_CORE_REGS for Cortex-M) since the openocd RTOS + * support does not yet support accessing all per-thread "stacked" + * registers. e.g. For Cortex-M under eCos we have a per-thread BASEPRI, and for + * all eCos targets we may have per-thread VFP/FPU register state. + * + * So, for the moment, we continue to use the hardwired limit for the depth of + * the returned register description vector. The current openocd + * rtos_standard_stackings.c just provides the main core regs for the Cortex_M* + * targets regardless of whether FPU is present/enabled. + * + * However, this code is written with the expectation that we may eventually be + * able to provide more register information ("m-system" and "vfp" for example) + * and also with the expectation of supporting different register sets being + * returned depending on the per-thread Cortex-M eCos contex_m for + * example. Hence the fact that the eCos_stack_layout_*() functions below allow + * for the stack context descriptor vector to be returned by those calls + * allowing for eventual support where this code will potentially cache + * different sets of register descriptors for the different shapes of contexts + * in a *single* application/binary run-time. + * + * TODO: Extend openocd generic RTOS support to allow thread-specific system and + * FPU register state to be returned. */ + +struct ecos_params; + +static bool ecos_detect_rtos(struct target *target); +static int ecos_create(struct target *target); +static int ecos_update_threads(struct rtos *rtos); +static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); +static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); +static int ecos_stack_layout_cortexm(struct rtos *rtos, struct ecos_params *param, + int64_t stack_ptr, const struct rtos_register_stacking **si); +static int ecos_stack_layout_arm(struct rtos *rtos, struct ecos_params *param, + int64_t stack_ptr, const struct rtos_register_stacking **si); + +/* The current eCos thread IDentifier uses 0 as an unused (not a valid thread + * ID) value. Currently the unique_id field is 16-bits, but the eCos SMP support + * convention is that only 12-bits of the ID will be used. This + * ECOS_MAX_THREAD_COUNT manifest is provided to limit the potential for + * interpreting stale/inconsistent thread list state when the debug host scans + * the thread list before the target RTOS has completed its initialisation. This + * support will need to revisited when eCos is re-engineered to support more + * than 16 CPU SMP setups. */ +#define ECOS_MAX_THREAD_COUNT (4095) + +struct ecos_thread_state { + int value; + const char *desc; +}; + +/* The status is actually a logical-OR bitmask of states: */ +enum ecos_thread_state_flags { + RUNNING = 0, /* explicit no-bits-set value */ + SLEEPING = BIT(0), + COUNTSLEEP = BIT(1), + SUSPENDED = BIT(2), + CREATING = BIT(3), + EXITED = BIT(4), + SLEEPSET = (SLEEPING | COUNTSLEEP) +}; + +/* Cyg_Thread:: reason codes for wake and sleep fields: */ +static const struct ecos_thread_state ecos_thread_reasons[] = { + { 0, "NONE" }, /* normally indicates "not yet started" */ + { 1, "WAIT" }, /* wait with no timeout */ + { 2, "DELAY" }, /* simple time delay */ + { 3, "TIMEOUT" }, /* wait with timeout *or* timeout expired */ + { 4, "BREAK" }, /* forced break out of sleep */ + { 5, "DESTRUCT" }, /* wait on object being destroyed */ + { 6, "EXIT" }, /* forced termination */ + { 7, "DONE" } /* wait/delay completed */ +}; + +static const char * const target_cortex_m[] = { + "cortex_m", + "hla_target", + NULL +}; + +static const char * const target_arm[] = { + "cortex_a", + "arm7tdmi", + "arm720t", + "arm9tdmi", + "arm920t", + "arm926ejs", + "arm946e", + "arm966e", + "arm11", + NULL +}; + +/* Since individual eCos application configurations may have different thread + * object structure layouts depending on the actual build-time enabled features + * we provide support for applications built containing the relevant symbolic + * support to match the actual application binary being debugged, rather than + * relying on a set of default/fixed (and potentially incorrect) + * offsets. However, for backwards compatibility, we do *NOT* enforce the + * requirement for the common extra helper symbols to be present to allow the + * fallback to the simple fixed CM3 model to avoid affecting existing users of + * older eCos worlds. Similarly we need to provide support for per-thread + * register context offsets, as well as for per-application-configurations, + * since some targets can have different stacked state on a per-thread basis + * (e.g. "cortex_m"). This is why the stacking_info is now set at run-time + * rather than being fixed. */ + +struct ecos_params { + const char * const *target_names; /* NULL terminated list of targets */ + int (*target_stack_layout)(struct rtos *rtos, struct ecos_params *param, + int64_t stack_ptr, const struct rtos_register_stacking **si); + bool flush_common; + unsigned char pointer_width; + unsigned char uid_width; + unsigned char state_width; + unsigned int thread_stack_offset; + unsigned int thread_name_offset; + unsigned int thread_state_offset; + unsigned int thread_next_offset; + unsigned int thread_uniqueid_offset; + const struct rtos_register_stacking *stacking_info; +}; + +/* As mentioned above we provide default offset values for the "cortex_m" + * targets for backwards compatibility with older eCos application builds and + * previous users of this RTOS specific support that do not have the + * configuration specific offsets provided in the symbol table. The support for + * other targets (e.g. "cortex_a") we do expect the application to provide the + * required symbolic information. We do not populate the stacking_info reference + * until we have had a chance to interrogate the symbol table. */ + +static struct ecos_params ecos_params_list[] = { + { + .target_names = target_cortex_m, + .pointer_width = 4, + .uid_width = 2, + .state_width = 4, + .thread_stack_offset = 0x0c, + .thread_name_offset = 0x9c, + .thread_state_offset = 0x3c, + .thread_next_offset = 0xa0, + .thread_uniqueid_offset = 0x4c, + .target_stack_layout = ecos_stack_layout_cortexm, + .stacking_info = NULL + }, + { + .target_names = target_arm, + .pointer_width = 0, + .uid_width = 0, + .state_width = 0, + .thread_stack_offset = 0, + .thread_name_offset = 0, + .thread_state_offset = 0, + .thread_next_offset = 0, + .thread_uniqueid_offset = 0, + .target_stack_layout = ecos_stack_layout_arm, + .stacking_info = NULL + } +}; + +#define ECOS_NUM_PARAMS ARRAY_SIZE(ecos_params_list) + +/* To eventually allow for more than just the ARMV7M_NUM_CORE_REGS to be + * returned by the Cortex-M support, and to avoid run-time lookups we manually + * maintain our own mapping for the supplied stack register vector entries. This + * enum needs to match the rtos_ecos_regoff_cortexm[] vector. Admittedly the + * initial indices just match the corresponding ARMV7M_R* definitions, but after + * the base registers the ARMV7M_* number space does not match the vector we + * wish to populate in this eCos support code. */ +enum ecos_reglist_cortexm { + ECOS_REGLIST_R0 = 0, + ECOS_REGLIST_R1, + ECOS_REGLIST_R2, + ECOS_REGLIST_R3, + ECOS_REGLIST_R4, + ECOS_REGLIST_R5, + ECOS_REGLIST_R6, + ECOS_REGLIST_R7, + ECOS_REGLIST_R8, + ECOS_REGLIST_R9, + ECOS_REGLIST_R10, + ECOS_REGLIST_R11, + ECOS_REGLIST_R12, + ECOS_REGLIST_R13, + ECOS_REGLIST_R14, + ECOS_REGLIST_PC, + ECOS_REGLIST_XPSR, /* ARMV7M_NUM_CORE_REGS */ + ECOS_REGLIST_BASEPRI, + ECOS_REGLIST_FPSCR, /* Following for FPU contexts */ + ECOS_REGLIST_D0, + ECOS_REGLIST_D1, + ECOS_REGLIST_D2, + ECOS_REGLIST_D3, + ECOS_REGLIST_D4, + ECOS_REGLIST_D5, + ECOS_REGLIST_D6, + ECOS_REGLIST_D7, + ECOS_REGLIST_D8, + ECOS_REGLIST_D9, + ECOS_REGLIST_D10, + ECOS_REGLIST_D11, + ECOS_REGLIST_D12, + ECOS_REGLIST_D13, + ECOS_REGLIST_D14, + ECOS_REGLIST_D15 +}; + +#define ECOS_CORTEXM_BASE_NUMREGS (ARMV7M_NUM_CORE_REGS) + +/* NOTE: The offsets in this vector are overwritten by the architecture specific + * layout functions depending on the specific application configuration. The + * ordering of this vector MUST match eCos_reglist. */ +static struct stack_register_offset rtos_ecos_regoff_cortexm[] = { + { ARMV7M_R0, -1, 32 }, /* r0 */ + { ARMV7M_R1, -1, 32 }, /* r1 */ + { ARMV7M_R2, -1, 32 }, /* r2 */ + { ARMV7M_R3, -1, 32 }, /* r3 */ + { ARMV7M_R4, -1, 32 }, /* r4 */ + { ARMV7M_R5, -1, 32 }, /* r5 */ + { ARMV7M_R6, -1, 32 }, /* r6 */ + { ARMV7M_R7, -1, 32 }, /* r7 */ + { ARMV7M_R8, -1, 32 }, /* r8 */ + { ARMV7M_R9, -1, 32 }, /* r9 */ + { ARMV7M_R10, -1, 32 }, /* r10 */ + { ARMV7M_R11, -1, 32 }, /* r11 */ + { ARMV7M_R12, -1, 32 }, /* r12 */ + { ARMV7M_R13, -1, 32 }, /* sp */ + { ARMV7M_R14, -1, 32 }, /* lr */ + { ARMV7M_PC, -1, 32 }, /* pc */ + { ARMV7M_XPSR, -1, 32 }, /* xPSR */ + { ARMV7M_BASEPRI, -1, 32 }, /* BASEPRI */ + { ARMV7M_FPSCR, -1, 32 }, /* FPSCR */ + { ARMV7M_D0, -1, 64 }, /* D0 (S0/S1) */ + { ARMV7M_D1, -1, 64 }, /* D1 (S2/S3) */ + { ARMV7M_D2, -1, 64 }, /* D2 (S4/S5) */ + { ARMV7M_D3, -1, 64 }, /* D3 (S6/S7) */ + { ARMV7M_D4, -1, 64 }, /* D4 (S8/S9) */ + { ARMV7M_D5, -1, 64 }, /* D5 (S10/S11) */ + { ARMV7M_D6, -1, 64 }, /* D6 (S12/S13) */ + { ARMV7M_D7, -1, 64 }, /* D7 (S14/S15) */ + { ARMV7M_D8, -1, 64 }, /* D8 (S16/S17) */ + { ARMV7M_D9, -1, 64 }, /* D9 (S18/S19) */ + { ARMV7M_D10, -1, 64 }, /* D10 (S20/S21) */ + { ARMV7M_D11, -1, 64 }, /* D11 (S22/S23) */ + { ARMV7M_D12, -1, 64 }, /* D12 (S24/S25) */ + { ARMV7M_D13, -1, 64 }, /* D13 (S26/S27) */ + { ARMV7M_D14, -1, 64 }, /* D14 (S28/S29) */ + { ARMV7M_D15, -1, 64 }, /* D15 (S30/S31) */ +}; + +static struct stack_register_offset rtos_ecos_regoff_arm[] = { + { 0, -1, 32 }, /* r0 */ + { 1, -1, 32 }, /* r1 */ + { 2, -1, 32 }, /* r2 */ + { 3, -1, 32 }, /* r3 */ + { 4, -1, 32 }, /* r4 */ + { 5, -1, 32 }, /* r5 */ + { 6, -1, 32 }, /* r6 */ + { 7, -1, 32 }, /* r7 */ + { 8, -1, 32 }, /* r8 */ + { 9, -1, 32 }, /* r9 */ + { 10, -1, 32 }, /* r10 */ + { 11, -1, 32 }, /* r11 (fp) */ + { 12, -1, 32 }, /* r12 (ip) */ + { 13, -1, 32 }, /* sp (r13) */ + { 14, -1, 32 }, /* lr (r14) */ + { 15, -1, 32 }, /* pc (r15) */ + { 16, -1, 32 }, /* xPSR */ +}; + +static struct rtos_register_stacking rtos_ecos_stacking = { + .stack_registers_size = 0, + .stack_growth_direction = -1, + .num_output_registers = 0, + .calculate_process_stack = NULL, /* stack_alignment */ + .register_offsets = NULL +}; + +/* To avoid the run-time cost of matching explicit symbol names we push the + * lookup offsets to this *manually* maintained enumeration which must match the + * ecos_symbol_list[] order below. */ +enum ecos_symbol_values { + ECOS_VAL_THREAD_LIST = 0, + ECOS_VAL_CURRENT_THREAD_PTR, + ECOS_VAL_COMMON_THREAD_NEXT_OFF, + ECOS_VAL_COMMON_THREAD_NEXT_SIZE, + ECOS_VAL_COMMON_THREAD_STATE_OFF, + ECOS_VAL_COMMON_THREAD_STATE_SIZE, + ECOS_VAL_COMMON_THREAD_SLEEP_OFF, + ECOS_VAL_COMMON_THREAD_SLEEP_SIZE, + ECOS_VAL_COMMON_THREAD_WAKE_OFF, + ECOS_VAL_COMMON_THREAD_WAKE_SIZE, + ECOS_VAL_COMMON_THREAD_ID_OFF, + ECOS_VAL_COMMON_THREAD_ID_SIZE, + ECOS_VAL_COMMON_THREAD_NAME_OFF, + ECOS_VAL_COMMON_THREAD_NAME_SIZE, + ECOS_VAL_COMMON_THREAD_PRI_OFF, + ECOS_VAL_COMMON_THREAD_PRI_SIZE, + ECOS_VAL_COMMON_THREAD_STACK_OFF, + ECOS_VAL_COMMON_THREAD_STACK_SIZE, + ECOS_VAL_CORTEXM_THREAD_SAVED, + ECOS_VAL_CORTEXM_CTX_THREAD_SIZE, + ECOS_VAL_CORTEXM_CTX_TYPE_OFF, + ECOS_VAL_CORTEXM_CTX_TYPE_SIZE, + ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF, + ECOS_VAL_CORTEXM_CTX_BASEPRI_SIZE, + ECOS_VAL_CORTEXM_CTX_SP_OFF, + ECOS_VAL_CORTEXM_CTX_SP_SIZE, + ECOS_VAL_CORTEXM_CTX_REG_OFF, + ECOS_VAL_CORTEXM_CTX_REG_SIZE, + ECOS_VAL_CORTEXM_CTX_PC_OFF, + ECOS_VAL_CORTEXM_CTX_PC_SIZE, + ECOS_VAL_CORTEXM_VAL_EXCEPTION, + ECOS_VAL_CORTEXM_VAL_THREAD, + ECOS_VAL_CORTEXM_VAL_INTERRUPT, + ECOS_VAL_CORTEXM_VAL_FPU, + ECOS_VAL_CORTEXM_CTX_FPSCR_OFF, + ECOS_VAL_CORTEXM_CTX_FPSCR_SIZE, + ECOS_VAL_CORTEXM_CTX_S_OFF, + ECOS_VAL_CORTEXM_CTX_S_SIZE, + ECOS_VAL_ARM_REGSIZE, + ECOS_VAL_ARM_CTX_R0_OFF, + ECOS_VAL_ARM_CTX_R1_OFF, + ECOS_VAL_ARM_CTX_R2_OFF, + ECOS_VAL_ARM_CTX_R3_OFF, + ECOS_VAL_ARM_CTX_R4_OFF, + ECOS_VAL_ARM_CTX_R5_OFF, + ECOS_VAL_ARM_CTX_R6_OFF, + ECOS_VAL_ARM_CTX_R7_OFF, + ECOS_VAL_ARM_CTX_R8_OFF, + ECOS_VAL_ARM_CTX_R9_OFF, + ECOS_VAL_ARM_CTX_R10_OFF, + ECOS_VAL_ARM_CTX_FP_OFF, + ECOS_VAL_ARM_CTX_IP_OFF, + ECOS_VAL_ARM_CTX_SP_OFF, + ECOS_VAL_ARM_CTX_LR_OFF, + ECOS_VAL_ARM_CTX_PC_OFF, + ECOS_VAL_ARM_CTX_CPSR_OFF, + ECOS_VAL_ARM_FPUSIZE, + ECOS_VAL_ARM_CTX_FPSCR_OFF, + ECOS_VAL_ARM_SCOUNT, + ECOS_VAL_ARM_CTX_SVEC_OFF, + ECOS_VAL_ARM_VFPCOUNT, + ECOS_VAL_ARM_CTX_VFPVEC_OFF +}; + +struct symbols { + const char *name; + const char * const *target_names; /* non-NULL when for a specific architecture */ + bool optional; +}; + +#define ECOSSYM(_n, _o, _t) { .name = _n, .optional = (_o), .target_names = _t } + +/* Some of offset/size helper symbols are common to all eCos + * targets. Unfortunately, for historical reasons, some information is in + * architecture specific namespaces leading to some duplication and a larger + * vector below. */ +static const struct symbols ecos_symbol_list[] = { + ECOSSYM("Cyg_Thread::thread_list", false, NULL), + ECOSSYM("Cyg_Scheduler_Base::current_thread", false, NULL), + /* Following symbols *are* required for generic application-specific + * configuration support, but we mark as optional for backwards + * compatibility with the previous fixed Cortex-M3 only RTOS plugin + * implementation. */ + ECOSSYM("__ecospro_syminfo.off.cyg_thread.list_next", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.list_next", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.state", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.state", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.sleep_reason", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.sleep_reason", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.wake_reason", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.wake_reason", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.unique_id", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.unique_id", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.name", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.name", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.priority", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.priority", true, NULL), + ECOSSYM("__ecospro_syminfo.off.cyg_thread.stack_ptr", true, NULL), + ECOSSYM("__ecospro_syminfo.size.cyg_thread.stack_ptr", true, NULL), + /* optional Cortex-M: */ + ECOSSYM("__ecospro_syminfo.cortexm.thread.saved", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.Thread", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.type", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.type", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.r", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.r", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.EXCEPTION", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.THREAD", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.INTERRUPT", true, target_cortex_m), + /* optional Cortex-M with H/W FPU configured: */ + ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.WITH_FPU", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.s", true, target_cortex_m), + ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.s", true, target_cortex_m), + /* optional ARM: */ + ECOSSYM("ARMREG_SIZE", true, target_arm), + ECOSSYM("armreg_r0", true, target_arm), + ECOSSYM("armreg_r1", true, target_arm), + ECOSSYM("armreg_r2", true, target_arm), + ECOSSYM("armreg_r3", true, target_arm), + ECOSSYM("armreg_r4", true, target_arm), + ECOSSYM("armreg_r5", true, target_arm), + ECOSSYM("armreg_r6", true, target_arm), + ECOSSYM("armreg_r7", true, target_arm), + ECOSSYM("armreg_r8", true, target_arm), + ECOSSYM("armreg_r9", true, target_arm), + ECOSSYM("armreg_r10", true, target_arm), + ECOSSYM("armreg_fp", true, target_arm), + ECOSSYM("armreg_ip", true, target_arm), + ECOSSYM("armreg_sp", true, target_arm), + ECOSSYM("armreg_lr", true, target_arm), + ECOSSYM("armreg_pc", true, target_arm), + ECOSSYM("armreg_cpsr", true, target_arm), + /* optional ARM FPU common: */ + ECOSSYM("ARMREG_FPUCONTEXT_SIZE", true, target_arm), + ECOSSYM("armreg_fpscr", true, target_arm), + /* optional ARM FPU single-precision: */ + ECOSSYM("ARMREG_S_COUNT", true, target_arm), + ECOSSYM("armreg_s_vec", true, target_arm), + /* optional ARM FPU double-precision: */ + ECOSSYM("ARMREG_VFP_COUNT", true, target_arm), + ECOSSYM("armreg_vfp_vec", true, target_arm), +}; + +const struct rtos_type ecos_rtos = { + .name = "eCos", + + .detect_rtos = ecos_detect_rtos, + .create = ecos_create, + .update_threads = ecos_update_threads, + .get_thread_reg_list = ecos_get_thread_reg_list, + .get_symbol_list_to_lookup = ecos_get_symbol_list_to_lookup, + +}; + +static symbol_address_t ecos_value(struct rtos *rtos, unsigned int idx) +{ + if (idx < ARRAY_SIZE(ecos_symbol_list)) + return rtos->symbols[idx].address; + + /* We do not terminate, just return 0 in this case. */ + LOG_ERROR("eCos: Invalid symbol index %u", idx); + return 0; +} + +#define XMLENTRY(_c, _s) { .xc = (_c), .rs = (_s), .rlen = (sizeof(_s) - 1) } + +static const struct { + char xc; + const char *rs; + size_t rlen; +} xmlchars[] = { + XMLENTRY('<', "<"), + XMLENTRY('&', "&"), + XMLENTRY('>', ">"), + XMLENTRY('\'', "'"), + XMLENTRY('"', """) +}; + +/** Escape any XML reserved characters in a string. */ +static bool ecos_escape_string(const char *raw, char *out, size_t limit) +{ + static const char *tokens = "<&>\'\""; + bool escaped = false; + + if (!out || !limit) + return false; + + (void)memset(out, '\0', limit); + + while (raw && *raw && limit) { + size_t lok = strcspn(raw, tokens); + if (lok) { + size_t tocopy; + tocopy = ((limit < lok) ? limit : lok); + (void)memcpy(out, raw, tocopy); + limit -= tocopy; + out += tocopy; + raw += lok; + continue; + } + + char *fidx = strchr(tokens, *raw); + if (!fidx) { + /* Should never happen assuming xmlchars + * vector and tokens string match. */ + LOG_ERROR("eCos: Unexpected XML char %c", *raw); + continue; + } + + uint32_t cidx = (fidx - tokens); + size_t tocopy = xmlchars[cidx].rlen; + if (limit < tocopy) + break; + + escaped = true; + (void)memcpy(out, xmlchars[cidx].rs, tocopy); + limit -= tocopy; + out += tocopy; + raw++; + } + + return escaped; +} + +static int ecos_check_app_info(struct rtos *rtos, struct ecos_params *param) +{ + if (!rtos || !param) + return -1; + + if (param->flush_common) { + if (debug_level >= LOG_LVL_DEBUG) { + for (unsigned int idx = 0; idx < ARRAY_SIZE(ecos_symbol_list); idx++) { + LOG_DEBUG("eCos: %s 0x%016" PRIX64 " %s", + rtos->symbols[idx].optional ? "OPTIONAL" : " ", + rtos->symbols[idx].address, rtos->symbols[idx].symbol_name); + } + } + + /* If "__ecospro_syminfo.size.cyg_thread.list_next" is non-zero then we + * expect all of the generic thread structure symbols to have been + * provided. */ + symbol_address_t thread_next_size = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NEXT_SIZE); + if (thread_next_size != 0) { + param->pointer_width = thread_next_size; + param->uid_width = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_ID_SIZE); + param->state_width = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STATE_SIZE); + param->thread_stack_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STACK_OFF); + param->thread_name_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NAME_OFF); + param->thread_state_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STATE_OFF); + param->thread_next_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NEXT_OFF); + param->thread_uniqueid_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_ID_OFF); + } + + if (param->uid_width != sizeof(uint16_t)) { + /* Currently all eCos configurations use a 16-bit field to hold the + * unique thread ID. */ + LOG_WARNING("eCos: Unexpected unique_id width %" PRIu8, param->uid_width); + param->uid_width = (unsigned char)sizeof(uint16_t); + } + + param->stacking_info = NULL; + param->flush_common = false; + } + + return ERROR_OK; +} + +/* The Cortex-M eCosPro "thread" contexts have a "type" indicator, which tracks + * the context state of (THREAD | EXCEPTION | INTERRUPT) and whether FPU + * registers are saved. + * + * For thread-aware debugging from GDB we are only interested in THREAD states + * and so do not need to implement support for INTERRUPT or EXCEPTION thread + * contexts since this code does not expose those stack contexts via the + * constructed thread list support. */ +static int ecos_stack_layout_cortexm(struct rtos *rtos, + struct ecos_params *param, int64_t stack_ptr, + const struct rtos_register_stacking **si) +{ + int retval = ERROR_OK; + + /* CONSIDER: We could return + * ecos_value(rtos, ECOS_VAL_CORTEXM_THREAD_SAVED) as the actual PC + * address of a context switch, with the LR being set to the context PC + * field to give a true representation of where the thread switch + * occurs. However that would require extending the common + * rtos_generic_stack_read() code with suitable support for applying a + * supplied value, or just implementing our own version of that code that + * can inject data into what is passed onwards to GDB. */ + + /* UPDATE: When we can return VFP register state then we will NOT be + * basing the cached state on the single param->stacking_info value, + * since we will need a different stacking_info structure returned for + * each thread type when FPU support is enabled. The use of the single + * param->stacking_info is a holder whilst we are limited to the fixed + * ARMV7M_NUM_CORE_REGS set of descriptors. */ + + if (!param->stacking_info && + ecos_value(rtos, ECOS_VAL_CORTEXM_THREAD_SAVED) && + ecos_value(rtos, ECOS_VAL_CORTEXM_VAL_THREAD)) { + unsigned char numoutreg = ECOS_CORTEXM_BASE_NUMREGS; + + rtos_ecos_stacking.stack_registers_size = ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_THREAD_SIZE); + rtos_ecos_stacking.calculate_process_stack = rtos_generic_stack_align8; + rtos_ecos_stacking.register_offsets = rtos_ecos_regoff_cortexm; + + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R0].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x00); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R1].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x04); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R2].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x08); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R3].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x0C); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R4].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x10); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R5].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x14); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R6].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x18); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R7].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x1C); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R8].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x20); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R9].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x24); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R10].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x28); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R11].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x2C); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R12].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x30); + /* Rather than using the stacked ECOS_VAL_CORTEXM_CTX_SP_OFF + * value we force the reported sp to be after the stacked + * register context. */ + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R13].offset = -2; + rtos_ecos_regoff_cortexm[ECOS_REGLIST_R14].offset = -1; + rtos_ecos_regoff_cortexm[ECOS_REGLIST_PC].offset = ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_PC_OFF); + rtos_ecos_regoff_cortexm[ECOS_REGLIST_XPSR].offset = -1; + + param->stacking_info = &rtos_ecos_stacking; + + /* Common Cortex-M thread register offsets for the current + * symbol table: */ + if (retval == ERROR_OK && param->stacking_info) { + if (numoutreg > ECOS_REGLIST_BASEPRI) { + rtos_ecos_regoff_cortexm[ECOS_REGLIST_BASEPRI].offset = + ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF); + } + + rtos_ecos_stacking.num_output_registers = numoutreg; + } + } + + if (si) + *si = param->stacking_info; + + return retval; +} + +static int ecos_stack_layout_arm(struct rtos *rtos, struct ecos_params *param, + int64_t stack_ptr, const struct rtos_register_stacking **si) +{ + int retval = ERROR_OK; + + if (!param->stacking_info && ecos_value(rtos, ECOS_VAL_ARM_REGSIZE)) { + /* When OpenOCD is extended to allow FPU registers to be returned from a + * stacked thread context we can check: + * if (0 != ecos_value(rtos, ECOS_VAL_ARM_FPUSIZE)) { FPU } + * for presence of FPU registers in the context. */ + + rtos_ecos_stacking.stack_registers_size = ecos_value(rtos, ECOS_VAL_ARM_REGSIZE); + rtos_ecos_stacking.num_output_registers = ARRAY_SIZE(rtos_ecos_regoff_arm); + rtos_ecos_stacking.register_offsets = rtos_ecos_regoff_arm; + + rtos_ecos_regoff_arm[0].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R0_OFF); + rtos_ecos_regoff_arm[1].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R1_OFF); + rtos_ecos_regoff_arm[2].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R2_OFF); + rtos_ecos_regoff_arm[3].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R3_OFF); + rtos_ecos_regoff_arm[4].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R4_OFF); + rtos_ecos_regoff_arm[5].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R5_OFF); + rtos_ecos_regoff_arm[6].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R6_OFF); + rtos_ecos_regoff_arm[7].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R7_OFF); + rtos_ecos_regoff_arm[8].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R8_OFF); + rtos_ecos_regoff_arm[9].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R9_OFF); + rtos_ecos_regoff_arm[10].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R10_OFF); + rtos_ecos_regoff_arm[11].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_FP_OFF); + rtos_ecos_regoff_arm[12].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_IP_OFF); + rtos_ecos_regoff_arm[13].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_SP_OFF); + rtos_ecos_regoff_arm[14].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_LR_OFF); + rtos_ecos_regoff_arm[15].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_PC_OFF); + rtos_ecos_regoff_arm[16].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_CPSR_OFF); + + param->stacking_info = &rtos_ecos_stacking; + } + + if (si) + *si = param->stacking_info; + + return retval; +} + +/* We see this function called on a new connection, it looks like before and + * after the "tar rem"/"tar extended-remote". It might be the only point we can + * decide to cache information (to check if the symbol table has changed). */ +static int ecos_update_threads(struct rtos *rtos) +{ + int retval; + int tasks_found = 0; + int thread_list_size = 0; + struct ecos_params *param; + + if (!rtos) + return -1; + + /* wipe out previous thread details if any */ + rtos_free_threadlist(rtos); + + if (!rtos->rtos_specific_params) + return -3; + + param = rtos->rtos_specific_params; + + if (!rtos->symbols) { + /* NOTE: We only see this when connecting from GDB the first + * time before the application image is loaded. So it is not a + * hook for detecting an application change. */ + param->flush_common = true; + LOG_ERROR("No symbols for eCos"); + return -4; + } + + retval = ecos_check_app_info(rtos, param); + if (retval != ERROR_OK) + return retval; + + if (rtos->symbols[ECOS_VAL_THREAD_LIST].address == 0) { + LOG_ERROR("Don't have the thread list head"); + return -2; + } + + /* determine the number of current threads */ + uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; + uint32_t thread_index; + target_read_buffer(rtos->target, + thread_list_head, + param->pointer_width, + (uint8_t *) &thread_index); + uint32_t first_thread = thread_index; + + /* Even if 0==first_thread indicates a system with no defined eCos + * threads, instead of early exiting here we fall through the code to + * allow the creation of a faked "Current Execution" descriptor as + * needed. */ + + if (first_thread) { + /* Since the OpenOCD RTOS support can attempt to obtain thread + * information on initial connection when the system *may* have + * undefined memory state it is possible for a simple thread count scan + * to produce invalid results. To avoid blocking indefinitely when + * encountering an invalid closed loop we limit the number of threads to + * the maximum possible, and if we pass that limit then something is + * wrong so treat the system as having no threads defined. */ + do { + thread_list_size++; + if (thread_list_size > ECOS_MAX_THREAD_COUNT) { + /* Treat as "no threads" case: */ + first_thread = 0; + thread_list_size = 0; + break; + } + retval = target_read_buffer(rtos->target, + thread_index + param->thread_next_offset, + param->pointer_width, + (uint8_t *)&thread_index); + if (retval != ERROR_OK) + return retval; + } while (thread_index != first_thread); + } + + /* read the current thread id */ + rtos->current_thread = 0; + + uint32_t current_thread_addr; + retval = target_read_buffer(rtos->target, + rtos->symbols[ECOS_VAL_CURRENT_THREAD_PTR].address, + param->pointer_width, + (uint8_t *)¤t_thread_addr); + if (retval != ERROR_OK) { + LOG_ERROR("Reading active thread address"); + return retval; + } + + if (current_thread_addr) { + uint16_t id = 0; + retval = target_read_buffer(rtos->target, + current_thread_addr + param->thread_uniqueid_offset, + param->uid_width, + (uint8_t *)&id); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read eCos current thread from target"); + return retval; + } + rtos->current_thread = (threadid_t)id; + } + + if (thread_list_size == 0 || rtos->current_thread == 0) { + /* Either : No RTOS threads - there is always at least the current execution though */ + /* OR : No current thread - all threads suspended - show the current execution + * of idling */ + static const char tmp_str[] = "Current Execution"; + thread_list_size++; + tasks_found++; + rtos->thread_details = malloc( + sizeof(struct thread_detail) * thread_list_size); + /* 1 is a valid eCos thread id, so we return 0 for this faked + * "current" CPU state: */ + rtos->thread_details->threadid = 0; + rtos->thread_details->exists = true; + rtos->thread_details->extra_info_str = NULL; + rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str)); + strcpy(rtos->thread_details->thread_name_str, tmp_str); + + /* Early exit if current CPU state our only "thread": */ + if (thread_list_size == 1) { + rtos->thread_count = 1; + return ERROR_OK; + } + } else { + /* create space for new thread details */ + rtos->thread_details = malloc( + sizeof(struct thread_detail) * thread_list_size); + } + + /* loop over all threads */ + thread_index = first_thread; + do { + #define ECOS_THREAD_NAME_STR_SIZE (200) + char tmp_str[ECOS_THREAD_NAME_STR_SIZE]; + uint32_t name_ptr = 0; + uint32_t prev_thread_ptr; + + /* Save the thread ID. For eCos the thread has a unique ID distinct from + * the thread_index descriptor pointer. We present this scheduler ID + * instead of the descriptor memory address. */ + uint16_t thread_id = 0; + retval = target_read_buffer(rtos->target, + thread_index + param->thread_uniqueid_offset, + param->uid_width, + (uint8_t *)&thread_id); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read eCos thread id from target"); + return retval; + } + rtos->thread_details[tasks_found].threadid = thread_id; + + /* Read the name pointer */ + retval = target_read_buffer(rtos->target, + thread_index + param->thread_name_offset, + param->pointer_width, + (uint8_t *)&name_ptr); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read eCos thread name pointer from target"); + return retval; + } + + /* Read the thread name */ + retval = + target_read_buffer(rtos->target, + name_ptr, + ECOS_THREAD_NAME_STR_SIZE, + (uint8_t *)&tmp_str); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading thread name from eCos target"); + return retval; + } + tmp_str[ECOS_THREAD_NAME_STR_SIZE-1] = '\x00'; + + /* Since eCos can have arbitrary C string names we can sometimes + * get an internal warning from GDB about "not well-formed + * (invalid token)" since the XML post-processing done by GDB on + * the OpenOCD returned response containing the thread strings + * is not escaped. For example the eCos kernel testsuite + * application tm_basic uses the thread name "<<NULL>>" which + * will trigger this failure unless escaped. */ + if (tmp_str[0] == '\x00') { + snprintf(tmp_str, ECOS_THREAD_NAME_STR_SIZE, "NoName:[0x%08" PRIX32 "]", thread_index); + } else { + /* The following is a workaround to avoid any issues + * from arbitrary eCos thread names causing GDB/OpenOCD + * issues. We limit the escaped thread name passed to + * GDB to the same length as the un-escaped just to + * avoid overly long strings. */ + char esc_str[ECOS_THREAD_NAME_STR_SIZE]; + bool escaped = ecos_escape_string(tmp_str, esc_str, sizeof(esc_str)); + if (escaped) + strcpy(tmp_str, esc_str); + } + + rtos->thread_details[tasks_found].thread_name_str = + malloc(strlen(tmp_str)+1); + strcpy(rtos->thread_details[tasks_found].thread_name_str, tmp_str); + + /* Read the thread status */ + int64_t thread_status = 0; + retval = target_read_buffer(rtos->target, + thread_index + param->thread_state_offset, + param->state_width, + (uint8_t *)&thread_status); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading thread state from eCos target"); + return retval; + } + + /* The thread_status is a BITMASK */ + char state_desc[21]; /* Enough for "suspended+countsleep\0" maximum */ + + if (thread_status & SUSPENDED) + strcpy(state_desc, "suspended+"); + else + state_desc[0] = '\0'; + + switch (thread_status & ~SUSPENDED) { + case RUNNING: + if (thread_index == current_thread_addr) + strcat(state_desc, "running"); + else if (thread_status & SUSPENDED) + state_desc[9] = '\0'; /* Drop '+' from "suspended+" */ + else + strcat(state_desc, "ready"); + break; + case SLEEPING: + strcat(state_desc, "sleeping"); + break; + case SLEEPSET: + case COUNTSLEEP: + strcat(state_desc, "counted sleep"); + break; + case CREATING: + strcpy(state_desc, "creating"); + break; + case EXITED: + strcpy(state_desc, "exited"); + break; + default: + strcpy(state_desc, "unknown state"); + break; + } + + /* For the moment we do not bother decoding the wake reason for the + * active "running" thread, but it is useful providing the sleep reason + * for stacked threads. */ + int64_t sleep_reason = 0; /* sleep reason */ + + if (thread_index != current_thread_addr && + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_SIZE)) { + retval = target_read_buffer(rtos->target, + (thread_index + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_OFF)), + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_SIZE), + (uint8_t *)&sleep_reason); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading thread sleep reason from eCos target"); + return retval; + } + if (sleep_reason < 0 || + sleep_reason > (int64_t)ARRAY_SIZE(ecos_thread_reasons)) { + sleep_reason = 0; + } + } + + /* We do not display anything for the Cyg_Thread::NONE reason */ + size_t tr_extra = 0; + const char *reason_desc = NULL; + if (sleep_reason) + reason_desc = ecos_thread_reasons[sleep_reason].desc; + if (reason_desc) + tr_extra = 2 + strlen(reason_desc) + 1; + + /* Display thread priority if available: */ + int64_t priority = 0; + size_t pri_extra = 0; + if (ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_SIZE)) { + retval = target_read_buffer(rtos->target, + (thread_index + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_OFF)), + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_SIZE), + (uint8_t *)&priority); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading thread priority from eCos target"); + return retval; + } + pri_extra = (12 + 20); /* worst-case ", Priority: " */ + } + + size_t eilen = (8 + strlen(state_desc) + tr_extra + pri_extra); + char *eistr = malloc(eilen); + /* We do not need to treat a malloc failure as a fatal error here since + * the code below will just not report extra thread information if NULL, + * thus allowing all of the threads to be enumerated even with reduced + * information when the host is low on memory. However... */ + if (!eistr) { + LOG_ERROR("OOM allocating extra information buffer"); + return ERROR_FAIL; + } + + int soff = snprintf(eistr, eilen, "State: %s", state_desc); + if (tr_extra && reason_desc) + soff += snprintf(&eistr[soff], (eilen - soff), " (%s)", reason_desc); + if (pri_extra) + (void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64 "", priority); + rtos->thread_details[tasks_found].extra_info_str = eistr; + + rtos->thread_details[tasks_found].exists = true; + + tasks_found++; + prev_thread_ptr = thread_index; + + /* Get the location of the next thread structure. */ + thread_index = rtos->symbols[ECOS_VAL_THREAD_LIST].address; + retval = target_read_buffer(rtos->target, + prev_thread_ptr + param->thread_next_offset, + param->pointer_width, + (uint8_t *) &thread_index); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading next thread pointer in eCos thread list"); + return retval; + } + } while (thread_index != first_thread); + + rtos->thread_count = tasks_found; + return ERROR_OK; +} + +static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, + struct rtos_reg **reg_list, int *num_regs) +{ + int retval; + struct ecos_params *param; + + if (!rtos) + return -1; + + if (thread_id == 0) + return -2; + + if (!rtos->rtos_specific_params) + return -3; + + param = rtos->rtos_specific_params; + + retval = ecos_check_app_info(rtos, param); + if (retval != ERROR_OK) + return retval; + + /* We can get memory access errors reported by this function on + * re-connecting to a board with stale thread information in memory. The + * initial ecos_update_threads() is called twice and may read + * stale/invalid information depending on the memory state. This happens + * as part of the "target remote" connection so cannot be avoided by GDB + * scripting. It is not critical and allowing the application to run and + * initialise its BSS etc. will allow correct thread and register + * information to be obtained. This really only affects debug sessions + * where "info thr" is used before the initial run-time initialisation + * has occurred. */ + + /* Find the thread with that thread id */ + uint16_t id = 0; + uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; + uint32_t thread_index; + target_read_buffer(rtos->target, thread_list_head, param->pointer_width, + (uint8_t *)&thread_index); + bool done = false; + while (!done) { + retval = target_read_buffer(rtos->target, + thread_index + param->thread_uniqueid_offset, + param->uid_width, + (uint8_t *)&id); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32 "", thread_index); + return retval; + } + + if (id == thread_id) { + done = true; + break; + } + target_read_buffer(rtos->target, + thread_index + param->thread_next_offset, + param->pointer_width, + (uint8_t *) &thread_index); + } + + if (done) { + /* Read the stack pointer */ + int64_t stack_ptr = 0; + retval = target_read_buffer(rtos->target, + thread_index + param->thread_stack_offset, + param->pointer_width, + (uint8_t *)&stack_ptr); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading stack frame from eCos thread"); + return retval; + } + + if (!stack_ptr) { + LOG_ERROR("NULL stack pointer in thread %" PRIu64, thread_id); + return -5; + } + + const struct rtos_register_stacking *stacking_info = NULL; + if (param->target_stack_layout) { + retval = param->target_stack_layout(rtos, param, stack_ptr, &stacking_info); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading stack layout for eCos thread"); + return retval; + } + } + if (!stacking_info) + stacking_info = &rtos_ecos_cortex_m3_stacking; + + return rtos_generic_stack_read(rtos->target, + stacking_info, + stack_ptr, + reg_list, + num_regs); + } + + return -1; +} + +/* NOTE: This is only called once when the first GDB connection is made to + * OpenOCD and not on subsequent connections (when the application symbol table + * may have changed, affecting the offsets of critical fields and the stacked + * context shape). */ +static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +{ + unsigned int i; + *symbol_list = calloc( + ARRAY_SIZE(ecos_symbol_list), sizeof(struct symbol_table_elem)); + + /* If the target reference was passed into this function we could limit + * the symbols we need to lookup to the target_type_name(target) based + * range. For the moment we need to provide a single vector with all of + * the symbols across all of the supported architectures. */ + for (i = 0; i < ARRAY_SIZE(ecos_symbol_list); i++) { + (*symbol_list)[i].symbol_name = ecos_symbol_list[i].name; + (*symbol_list)[i].optional = ecos_symbol_list[i].optional; + } + + return 0; +} + +/* NOTE: Only called by rtos.c:rtos_qsymbol() when auto-detecting the RTOS. If + * the target configuration uses the explicit "-rtos" config option then this + * detection routine is NOT called. */ +static bool ecos_detect_rtos(struct target *target) +{ + if ((target->rtos->symbols) && + (target->rtos->symbols[ECOS_VAL_THREAD_LIST].address != 0)) { + /* looks like eCos */ + return true; + } + return false; +} + +/* Since we should never have 0 as a valid eCos thread ID we use $Hg0 as the + * indicator of a new session as regards flushing any cached state. */ +static int ecos_packet_hook(struct connection *connection, + const char *packet, int packet_size) +{ + int64_t current_threadid; + + if (packet[0] == 'H' && packet[1] == 'g') { + int numscan = sscanf(packet, "Hg%16" SCNx64, ¤t_threadid); + if (numscan == 1 && current_threadid == 0) { + struct target *target = get_target_from_connection(connection); + if (target && target->rtos && target->rtos->rtos_specific_params) { + struct ecos_params *param; + param = target->rtos->rtos_specific_params; + param->flush_common = true; + } + } + } + + return rtos_thread_packet(connection, packet, packet_size); +} + +/* Called at start of day when eCos detected or specified in config file. */ +static int ecos_create(struct target *target) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(ecos_params_list); i++) { + const char * const *tnames = ecos_params_list[i].target_names; + while (*tnames) { + if (strcmp(*tnames, target_type_name(target)) == 0) { + /* LOG_DEBUG("eCos: matched target \"%s\"", target_type_name(target)); */ + target->rtos->rtos_specific_params = (void *)&ecos_params_list[i]; + ecos_params_list[i].flush_common = true; + ecos_params_list[i].stacking_info = NULL; + target->rtos->current_thread = 0; + target->rtos->thread_details = NULL; + + /* We use the $Hg0 packet as a new GDB connection "start-of-day" hook to + * force a re-cache of information. It is possible for a single OpenOCD + * session to be connected to a target with multiple GDB debug sessions + * started/stopped. With eCos it is possible for those GDB sessions to + * present applications with different offsets within a thread + * descriptor for fields used by this module, and for the stacked + * context within the connected target architecture to differ between + * applications and even between threads in a single application. So we + * need to ensure any information we cache is flushed on an application + * change, and GDB referencing an invalid eCos thread ID (0) is a good + * enough point, since we can accept the re-cache hit if that packet + * appears during an established session, whilst benefiting from not + * re-loading information on every update_threads or get_thread_reg_list + * call. */ + target->rtos->gdb_thread_packet = ecos_packet_hook; + /* We do not currently use the target->rtos->gdb_target_for_threadid + * hook. */ + return ERROR_OK; + } + tnames++; + } + } + + LOG_ERROR("Could not find target in eCos compatibility list"); + return ERROR_FAIL; +} diff --git a/src/rtos/embKernel.c b/src/rtos/embkernel.c similarity index 97% rename from src/rtos/embKernel.c rename to src/rtos/embkernel.c index 23e7bc64b8..7ad937be59 100644 --- a/src/rtos/embKernel.c +++ b/src/rtos/embkernel.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -12,7 +12,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -27,7 +26,7 @@ static int embkernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); static int embkernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct rtos_type embkernel_rtos = { +const struct rtos_type embkernel_rtos = { .name = "embKernel", .detect_rtos = embkernel_detect_rtos, .create = embkernel_create, @@ -110,17 +109,17 @@ static int embkernel_create(struct target *target) { size_t i = 0; while ((i < ARRAY_SIZE(embkernel_params_list)) && - (strcmp(embkernel_params_list[i].target_name, target->type->name) != 0)) + (strcmp(embkernel_params_list[i].target_name, target_type_name(target)) != 0)) i++; if (i >= ARRAY_SIZE(embkernel_params_list)) { LOG_WARNING("Could not find target \"%s\" in embKernel compatibility " - "list", target->type->name); - return -1; + "list", target_type_name(target)); + return ERROR_FAIL; } target->rtos->rtos_specific_params = (void *) &embkernel_params_list[i]; - return 0; + return ERROR_OK; } static int embkernel_get_tasks_details(struct rtos *rtos, int64_t iterable, const struct embkernel_params *param, diff --git a/src/rtos/FreeRTOS.c b/src/rtos/freertos.c similarity index 90% rename from src/rtos/FreeRTOS.c rename to src/rtos/freertos.c index 499759ab3e..5a9224ec08 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/freertos.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -12,7 +12,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -31,12 +30,12 @@ struct freertos_params { const char *target_name; const unsigned char thread_count_width; const unsigned char pointer_width; - const unsigned char list_next_offset; - const unsigned char list_width; - const unsigned char list_elem_next_offset; - const unsigned char list_elem_content_offset; - const unsigned char thread_stack_offset; - const unsigned char thread_name_offset; + const unsigned char list_next_offset; /* offsetof(List_t, xListEnd.pxNext) */ + const unsigned char list_width; /* sizeof(List_t) */ + const unsigned char list_elem_next_offset; /* offsetof(ListItem_t, pxNext) */ + const unsigned char list_elem_content_offset; /* offsetof(ListItem_t, pvOwner) */ + const unsigned char thread_stack_offset; /* offsetof(TCB_t, pxTopOfStack) */ + const unsigned char thread_name_offset; /* offsetof(TCB_t, pcTaskName) */ const struct rtos_register_stacking *stacking_info_cm3; const struct rtos_register_stacking *stacking_info_cm4f; const struct rtos_register_stacking *stacking_info_cm4f_fpu; @@ -47,9 +46,9 @@ static const struct freertos_params freertos_params_list[] = { "cortex_m", /* target_name */ 4, /* thread_count_width; */ 4, /* pointer_width; */ - 16, /* list_next_offset; */ + 12, /* list_next_offset; */ 20, /* list_width; */ - 8, /* list_elem_next_offset; */ + 4, /* list_elem_next_offset; */ 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ @@ -61,9 +60,9 @@ static const struct freertos_params freertos_params_list[] = { "hla_target", /* target_name */ 4, /* thread_count_width; */ 4, /* pointer_width; */ - 16, /* list_next_offset; */ + 12, /* list_next_offset; */ 20, /* list_width; */ - 8, /* list_elem_next_offset; */ + 4, /* list_elem_next_offset; */ 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ @@ -71,20 +70,6 @@ static const struct freertos_params freertos_params_list[] = { &rtos_standard_cortex_m4f_stacking, &rtos_standard_cortex_m4f_fpu_stacking, }, - { - "nds32_v3", /* target_name */ - 4, /* thread_count_width; */ - 4, /* pointer_width; */ - 16, /* list_next_offset; */ - 20, /* list_width; */ - 8, /* list_elem_next_offset; */ - 12, /* list_elem_content_offset */ - 0, /* thread_stack_offset; */ - 52, /* thread_name_offset; */ - &rtos_standard_nds32_n1068_stacking, /* stacking_info */ - &rtos_standard_cortex_m4f_stacking, - &rtos_standard_cortex_m4f_fpu_stacking, - }, }; static bool freertos_detect_rtos(struct target *target); @@ -94,7 +79,7 @@ static int freertos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); static int freertos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct rtos_type freertos_rtos = { +const struct rtos_type freertos_rtos = { .name = "FreeRTOS", .detect_rtos = freertos_detect_rtos, @@ -116,6 +101,7 @@ enum freertos_symbol_values { FREERTOS_VAL_X_SUSPENDED_TASK_LIST = 8, FREERTOS_VAL_UX_CURRENT_NUMBER_OF_TASKS = 9, FREERTOS_VAL_UX_TOP_USED_PRIORITY = 10, + FREERTOS_VAL_X_SCHEDULER_RUNNING = 11, }; struct symbols { @@ -135,6 +121,7 @@ static const struct symbols freertos_symbol_list[] = { { "xSuspendedTaskList", true }, /* Only if INCLUDE_vTaskSuspend */ { "uxCurrentNumberOfTasks", false }, { "uxTopUsedPriority", true }, /* Unavailable since v7.5.3 */ + { "xSchedulerRunning", false }, { NULL, false } }; @@ -194,7 +181,20 @@ static int freertos_update_threads(struct rtos *rtos) rtos->symbols[FREERTOS_VAL_PX_CURRENT_TCB].address, rtos->current_thread); - if ((thread_list_size == 0) || (rtos->current_thread == 0)) { + /* read scheduler running */ + uint32_t scheduler_running; + retval = target_read_u32(rtos->target, + rtos->symbols[FREERTOS_VAL_X_SCHEDULER_RUNNING].address, + &scheduler_running); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading FreeRTOS scheduler state"); + return retval; + } + LOG_DEBUG("FreeRTOS: Read xSchedulerRunning at 0x%" PRIx64 ", value 0x%" PRIx32, + rtos->symbols[FREERTOS_VAL_X_SCHEDULER_RUNNING].address, + scheduler_running); + + if ((thread_list_size == 0) || (rtos->current_thread == 0) || (scheduler_running != 1)) { /* Either : No RTOS threads - there is always at least the current execution though */ /* OR : No current thread - all threads suspended - show the current execution * of idling */ @@ -207,7 +207,8 @@ static int freertos_update_threads(struct rtos *rtos) LOG_ERROR("Error allocating memory for %d threads", thread_list_size); return ERROR_FAIL; } - rtos->thread_details->threadid = 1; + rtos->current_thread = 1; + rtos->thread_details->threadid = rtos->current_thread; rtos->thread_details->exists = true; rtos->thread_details->extra_info_str = NULL; rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str)); @@ -310,7 +311,6 @@ static int freertos_update_threads(struct rtos *rtos) (list_elem_ptr != prev_list_elem_ptr) && (tasks_found < thread_list_size)) { /* Get the location of the thread structure. */ - rtos->thread_details[tasks_found].threadid = 0; retval = target_read_u32(rtos->target, list_elem_ptr + param->list_elem_content_offset, &pointer_casts_are_bad); @@ -363,6 +363,7 @@ static int freertos_update_threads(struct rtos *rtos) tasks_found++; list_thread_count--; + rtos->thread_count = tasks_found; prev_list_elem_ptr = list_elem_ptr; list_elem_ptr = 0; @@ -381,7 +382,6 @@ static int freertos_update_threads(struct rtos *rtos) } free(list_of_lists); - rtos->thread_count = tasks_found; return 0; } @@ -421,7 +421,8 @@ static int freertos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, int cm4_fpu_enabled = 0; struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { - if (armv7m_target->fp_feature == FPV4_SP) { + if ((armv7m_target->fp_feature == FPV4_SP) || (armv7m_target->fp_feature == FPV5_SP) || + (armv7m_target->fp_feature == FPV5_DP)) { /* Found ARM v7m target which includes a FPU */ uint32_t cpacr; @@ -531,11 +532,11 @@ static bool freertos_detect_rtos(struct target *target) static int freertos_create(struct target *target) { for (unsigned int i = 0; i < ARRAY_SIZE(freertos_params_list); i++) - if (strcmp(freertos_params_list[i].target_name, target->type->name) == 0) { + if (strcmp(freertos_params_list[i].target_name, target_type_name(target)) == 0) { target->rtos->rtos_specific_params = (void *)&freertos_params_list[i]; - return 0; + return ERROR_OK; } LOG_ERROR("Could not find target in FreeRTOS compatibility list"); - return -1; + return ERROR_FAIL; } diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c index db44b00947..b2a45ade9f 100644 --- a/src/rtos/hwthread.c +++ b/src/rtos/hwthread.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #ifdef HAVE_CONFIG_H #include "config.h" @@ -7,7 +7,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "target/register.h" #include <target/smp.h> #include "rtos.h" @@ -32,11 +31,20 @@ static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address, #define HW_THREAD_NAME_STR_SIZE (32) -extern int rtos_thread_packet(struct connection *connection, const char *packet, int packet_size); - static inline threadid_t threadid_from_target(const struct target *target) { - return target->coreid + 1; + if (!target->smp) + return 1; + + threadid_t threadid = 1; + struct target_list *head; + foreach_smp_target(head, target->smp_targets) { + if (target == head->target) + return threadid; + ++threadid; + } + assert(0 && "Target is not found in it's own SMP group!"); + return -1; } const struct rtos_type hwthread_rtos = { @@ -57,14 +65,13 @@ struct hwthread_params { int dummy_param; }; -static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thread_num) +static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thread_num, threadid_t tid) { char tmp_str[HW_THREAD_NAME_STR_SIZE]; - threadid_t tid = threadid_from_target(curr); memset(tmp_str, 0, HW_THREAD_NAME_STR_SIZE); - /* thread-id is the core-id of this core inside the SMP group plus 1 */ + /* thread-id is the index of this core inside the SMP group plus 1 */ rtos->thread_details[thread_num].threadid = tid; /* create the thread name */ rtos->thread_details[thread_num].exists = true; @@ -82,6 +89,7 @@ static int hwthread_update_threads(struct rtos *rtos) struct target_list *head; struct target *target; int64_t current_thread = 0; + int64_t current_threadid = rtos->current_threadid; /* thread selected by GDB */ enum target_debug_reason current_reason = DBG_REASON_UNDEFINED; if (!rtos) @@ -97,7 +105,8 @@ static int hwthread_update_threads(struct rtos *rtos) foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - if (!target_was_examined(curr)) + if (!target_was_examined(curr) || + curr->state == TARGET_UNAVAILABLE) continue; ++thread_list_size; @@ -105,6 +114,15 @@ static int hwthread_update_threads(struct rtos *rtos) } else thread_list_size = 1; + /* restore the threadid which is currently selected by GDB + * because rtos_free_threadlist() wipes out it + * (GDB thread id is 1-based indexing) */ + if (current_threadid <= thread_list_size) + rtos->current_threadid = current_threadid; + else + LOG_TARGET_WARNING(target, "SMP node change, disconnect GDB from core/thread %" PRId64, + current_threadid); + /* create space for new thread details */ rtos->thread_details = malloc(sizeof(struct thread_detail) * thread_list_size); @@ -113,12 +131,12 @@ static int hwthread_update_threads(struct rtos *rtos) foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - if (!target_was_examined(curr)) + if (!target_was_examined(curr) || + curr->state == TARGET_UNAVAILABLE) continue; threadid_t tid = threadid_from_target(curr); - - hwthread_fill_thread(rtos, curr, threads_found); + hwthread_fill_thread(rtos, curr, threads_found, tid); /* find an interesting thread to set as current */ switch (current_reason) { @@ -138,9 +156,8 @@ static int hwthread_update_threads(struct rtos *rtos) if (curr->debug_reason == DBG_REASON_SINGLESTEP) { current_reason = curr->debug_reason; current_thread = tid; - } else - /* multiple breakpoints, prefer gdbs' threadid */ - if (curr->debug_reason == DBG_REASON_BREAKPOINT) { + } else if (curr->debug_reason == DBG_REASON_BREAKPOINT) { + /* multiple breakpoints, prefer gdbs' threadid */ if (tid == rtos->current_threadid) current_thread = tid; } @@ -160,8 +177,7 @@ static int hwthread_update_threads(struct rtos *rtos) curr->debug_reason == DBG_REASON_BREAKPOINT) { current_reason = curr->debug_reason; current_thread = tid; - } else - if (curr->debug_reason == DBG_REASON_DBGRQ) { + } else if (curr->debug_reason == DBG_REASON_DBGRQ) { if (tid == rtos->current_threadid) current_thread = tid; } @@ -175,8 +191,8 @@ static int hwthread_update_threads(struct rtos *rtos) threads_found++; } } else { - hwthread_fill_thread(rtos, target, threads_found); - current_thread = threadid_from_target(target); + current_thread = 1; + hwthread_fill_thread(rtos, target, threads_found, current_thread); threads_found++; } @@ -190,7 +206,8 @@ static int hwthread_update_threads(struct rtos *rtos) else rtos->current_thread = threadid_from_target(target); - LOG_DEBUG("%s current_thread=%i", __func__, (int)rtos->current_thread); + LOG_TARGET_DEBUG(target, "current_thread=%" PRId64 ", threads_found=%d", + rtos->current_thread, threads_found); return 0; } @@ -199,19 +216,17 @@ static int hwthread_smp_init(struct target *target) return hwthread_update_threads(target->rtos); } -static struct target *hwthread_find_thread(struct target *target, int64_t thread_id) +static struct target *hwthread_find_thread(struct target *target, threadid_t thread_id) { - /* Find the thread with that thread_id */ - if (!target) - return NULL; - if (target->smp) { - struct target_list *head; - foreach_smp_target(head, target->smp_targets) { - if (thread_id == threadid_from_target(head->target)) - return head->target; - } - } else if (thread_id == threadid_from_target(target)) { + /* Find the thread with that thread_id (index in SMP group plus 1)*/ + if (!(target && target->smp)) return target; + struct target_list *head; + threadid_t tid = 1; + foreach_smp_target(head, target->smp_targets) { + if (thread_id == tid) + return head->target; + ++tid; } return NULL; } @@ -240,7 +255,7 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, int j = 0; for (int i = 0; i < reg_list_size; i++) { - if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden) continue; j++; } @@ -253,12 +268,22 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, j = 0; for (int i = 0; i < reg_list_size; i++) { - if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden) continue; - (*rtos_reg_list)[j].number = (*reg_list)[i].number; - (*rtos_reg_list)[j].size = (*reg_list)[i].size; - memcpy((*rtos_reg_list)[j].value, (*reg_list)[i].value, - ((*reg_list)[i].size + 7) / 8); + if (!reg_list[i]->valid) { + retval = reg_list[i]->type->get(reg_list[i]); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(curr, "Couldn't get register %s", + reg_list[i]->name); + free(reg_list); + free(*rtos_reg_list); + return retval; + } + } + (*rtos_reg_list)[j].number = reg_list[i]->number; + (*rtos_reg_list)[j].size = reg_list[i]->size; + memcpy((*rtos_reg_list)[j].value, reg_list[i]->value, + DIV_ROUND_UP(reg_list[i]->size, 8)); j++; } free(reg_list); @@ -276,19 +301,20 @@ static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id, struct target *curr = hwthread_find_thread(target, thread_id); if (!curr) { - LOG_ERROR("Couldn't find RTOS thread for id %" PRId64 ".", thread_id); + LOG_TARGET_ERROR(target, "Couldn't find RTOS thread for id %" PRId64, + thread_id); return ERROR_FAIL; } if (!target_was_examined(curr)) { - LOG_ERROR("Target %d hasn't been examined yet.", curr->coreid); + LOG_TARGET_ERROR(curr, "Target hasn't been examined yet."); return ERROR_FAIL; } struct reg *reg = register_get_by_number(curr->reg_cache, reg_num, true); if (!reg) { - LOG_ERROR("Couldn't find register %" PRIu32 " in thread %" PRId64 ".", reg_num, - thread_id); + LOG_TARGET_ERROR(curr, "Couldn't find register %" PRIu32 " in thread %" PRId64, + reg_num, thread_id); return ERROR_FAIL; } @@ -297,7 +323,7 @@ static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id, rtos_reg->number = reg->number; rtos_reg->size = reg->size; - unsigned bytes = (reg->size + 7) / 8; + unsigned int bytes = (reg->size + 7) / 8; assert(bytes <= sizeof(rtos_reg->value)); memcpy(rtos_reg->value, reg->value, bytes); @@ -351,24 +377,24 @@ static bool hwthread_detect_rtos(struct target *target) static int hwthread_thread_packet(struct connection *connection, const char *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); - - struct target *curr = NULL; - int64_t current_threadid; - if (packet[0] == 'H' && packet[1] == 'g') { + int64_t current_threadid; sscanf(packet, "Hg%16" SCNx64, ¤t_threadid); + struct target *target = get_target_from_connection(connection); + if (current_threadid > 0) { + struct target *curr = NULL; if (hwthread_target_for_threadid(connection, current_threadid, &curr) != ERROR_OK) { - LOG_ERROR("hwthread: cannot find thread id %"PRId64, current_threadid); + LOG_TARGET_ERROR(target, "hwthread: cannot find thread id %" PRId64, + current_threadid); gdb_put_packet(connection, "E01", 3); return ERROR_FAIL; } target->rtos->current_thread = current_threadid; - } else - if (current_threadid == 0 || current_threadid == -1) + } else if (current_threadid == 0 || current_threadid == -1) { target->rtos->current_thread = threadid_from_target(target); + } target->rtos->current_threadid = current_threadid; @@ -381,14 +407,14 @@ static int hwthread_thread_packet(struct connection *connection, const char *pac static int hwthread_create(struct target *target) { - LOG_INFO("Hardware thread awareness created"); + LOG_TARGET_INFO(target, "Hardware thread awareness created"); target->rtos->rtos_specific_params = NULL; target->rtos->current_thread = 0; target->rtos->thread_details = NULL; target->rtos->gdb_target_for_threadid = hwthread_target_for_threadid; target->rtos->gdb_thread_packet = hwthread_thread_packet; - return 0; + return ERROR_OK; } static int hwthread_read_buffer(struct rtos *rtos, target_addr_t address, diff --git a/src/rtos/linux.c b/src/rtos/linux.c index 3fdcb4383f..4ca02605ed 100644 --- a/src/rtos/linux.c +++ b/src/rtos/linux.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by STEricsson * @@ -123,7 +123,7 @@ static int linux_read_memory(struct target *target, target->rtos->rtos_specific_params; uint32_t pa = (address & linux_os->phys_mask) + linux_os->phys_base; #endif - if (address < 0xc000000) { + if (address < 0xc0000000) { LOG_ERROR("linux awareness : address in user space"); return ERROR_FAIL; } @@ -624,7 +624,7 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads { t->next = NULL; - if (!*last) + if (!*last) { if (!task_list) { task_list = t; return task_list; @@ -637,7 +637,8 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads temp->next = t; *last = t; return task_list; - } else { + } + } else { (*last)->next = t; *last = t; return task_list; @@ -1039,6 +1040,10 @@ static int linux_gdb_thread_packet(struct target *target, return ERROR_TARGET_FAILURE; char *out_str = calloc(MAX_THREADS * 17 + 10, 1); + if (!out_str) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } char *tmp_str = out_str; tmp_str += sprintf(tmp_str, "m"); struct threads *temp = linux_os->thread_list; @@ -1115,23 +1120,13 @@ static int linux_thread_extra_info(struct target *target, while (temp) { if (temp->threadid == threadid) { - char *pid = " PID: "; - char *pid_current = "*PID: "; - char *name = "Name: "; - int str_size = strlen(pid) + strlen(name); - char *tmp_str = calloc(1, str_size + 50); - char *tmp_str_ptr = tmp_str; - - /* discriminate current task */ - if (temp->status == 3) - tmp_str_ptr += sprintf(tmp_str_ptr, "%s", - pid_current); - else - tmp_str_ptr += sprintf(tmp_str_ptr, "%s", pid); - - tmp_str_ptr += sprintf(tmp_str_ptr, "%d, ", (int)temp->pid); - sprintf(tmp_str_ptr, "%s", name); - sprintf(tmp_str_ptr, "%s", temp->name); + char *tmp_str = alloc_printf("%cPID: %" PRIu32 ", Name: %s", + temp->status == 3 ? '*' : ' ', + temp->pid, temp->name); + if (!tmp_str) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } char *hex_str = calloc(1, strlen(tmp_str) * 2 + 1); size_t pkt_len = hexify(hex_str, (const uint8_t *)tmp_str, strlen(tmp_str), strlen(tmp_str) * 2 + 1); @@ -1429,7 +1424,7 @@ static int linux_os_create(struct target *target) /* initialize a default virt 2 phys translation */ os_linux->phys_mask = ~0xc0000000; os_linux->phys_base = 0x0; - return JIM_OK; + return ERROR_OK; } static char *linux_ps_command(struct target *target) diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index a724db0039..dbb48952f2 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2014 by Marian Cingel * @@ -13,7 +13,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -249,14 +248,14 @@ static int mqx_create( { /* check target name against supported architectures */ for (unsigned int i = 0; i < ARRAY_SIZE(mqx_params_list); i++) { - if (strcmp(mqx_params_list[i].target_name, target->type->name) == 0) { + if (strcmp(mqx_params_list[i].target_name, target_type_name(target)) == 0) { target->rtos->rtos_specific_params = (void *)&mqx_params_list[i]; - /* LOG_DEBUG("MQX RTOS - valid architecture: %s", target->type->name); */ - return 0; + /* LOG_DEBUG("MQX RTOS - valid architecture: %s", target_type_name(target)); */ + return ERROR_OK; } } - LOG_ERROR("MQX RTOS - could not find target \"%s\" in MQX compatibility list", target->type->name); - return -1; + LOG_ERROR("MQX RTOS - could not find target \"%s\" in MQX compatibility list", target_type_name(target)); + return ERROR_FAIL; } /* @@ -320,7 +319,7 @@ static int mqx_update_threads( i < (uint32_t)rtos->thread_count; i++ ) { - uint8_t task_name[MQX_THREAD_NAME_LENGTH + 1]; + char task_name[MQX_THREAD_NAME_LENGTH + 1]; uint32_t task_addr = 0, task_template = 0, task_state = 0; uint32_t task_name_addr = 0, task_id = 0, task_errno = 0; uint32_t state_index = 0; @@ -381,10 +380,9 @@ static int mqx_update_threads( rtos->thread_details[i].threadid = task_id; rtos->thread_details[i].exists = true; /* set thread name */ - rtos->thread_details[i].thread_name_str = malloc(strlen((void *)task_name) + 1); + rtos->thread_details[i].thread_name_str = strdup(task_name); if (!rtos->thread_details[i].thread_name_str) return ERROR_FAIL; - strcpy(rtos->thread_details[i].thread_name_str, (void *)task_name); /* set thread extra info * - task state * - task address @@ -498,7 +496,7 @@ static int mqx_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[] return ERROR_OK; } -struct rtos_type mqx_rtos = { +const struct rtos_type mqx_rtos = { .name = "mqx", .detect_rtos = mqx_detect_rtos, .create = mqx_create, diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c index 3afad3d029..27bf086c83 100644 --- a/src/rtos/nuttx.c +++ b/src/rtos/nuttx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright 2016,2017 Sony Video & Sound Products Inc. * @@ -12,59 +12,57 @@ #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "target/armv7m.h" #include "target/cortex_m.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" -#include "server/gdb_server.h" +#include "target/register.h" +#include "rtos_nuttx_stackings.h" -#include "nuttx_header.h" +#define NAME_SIZE 32 +#define EXTRAINFO_SIZE 256 +/* Only 32-bit CPUs are supported by the current implementation. Supporting + * other CPUs will require reading this information from the target and + * adapting the code accordingly. + */ +#define PTR_WIDTH 4 -int rtos_thread_packet(struct connection *connection, const char *packet, int packet_size); - -#ifdef CONFIG_DISABLE_SIGNALS -#define SIG_QUEUE_NUM 0 -#else -#define SIG_QUEUE_NUM 1 -#endif /* CONFIG_DISABLE_SIGNALS */ - -#ifdef CONFIG_DISABLE_MQUEUE -#define M_QUEUE_NUM 0 -#else -#define M_QUEUE_NUM 2 -#endif /* CONFIG_DISABLE_MQUEUE */ - -#ifdef CONFIG_PAGING -#define PAGING_QUEUE_NUM 1 -#else -#define PAGING_QUEUE_NUM 0 -#endif /* CONFIG_PAGING */ - - -#define TASK_QUEUE_NUM (6 + SIG_QUEUE_NUM + M_QUEUE_NUM + PAGING_QUEUE_NUM) - +struct nuttx_params { + const char *target_name; + const struct rtos_register_stacking *stacking; +}; -/* see nuttx/sched/os_start.c */ -static char *nuttx_symbol_list[] = { - "g_readytorun", /* 0: must be top of this array */ - "g_tasklisttable", - NULL +/* + * struct tcbinfo_s is located in the sched.h + * https://github.com/apache/nuttx/blob/master/include/nuttx/sched.h + */ +#define TCBINFO_TARGET_SIZE 22 +struct tcbinfo { + uint16_t pid_off; /* Offset of tcb.pid */ + uint16_t state_off; /* Offset of tcb.task_state */ + uint16_t pri_off; /* Offset of tcb.sched_priority */ + uint16_t name_off; /* Offset of tcb.name */ + uint16_t regs_off; /* Offset of tcb.regs */ + uint16_t basic_num; /* Num of genernal regs */ + uint16_t total_num; /* Num of regs in tcbinfo.reg_offs */ + target_addr_t xcpreg_off; /* Offset pointer of xcp.regs */ }; -/* see nuttx/include/nuttx/sched.h */ -struct tcb { - uint32_t flink; - uint32_t blink; - uint8_t dat[512]; +struct symbols { + const char *name; + bool optional; }; -static struct { - uint32_t addr; - uint32_t prio; -} g_tasklist[TASK_QUEUE_NUM]; +static const struct symbols nuttx_symbol_list[] = { + { "g_readytorun", false }, + { "g_pidhash", false }, + { "g_npidhash", false }, + { "g_tcbinfo", false }, + { "g_reg_offs", false}, + { NULL, false } +}; static char *task_state_str[] = { "INVALID", @@ -73,317 +71,333 @@ static char *task_state_str[] = { "RUNNING", "INACTIVE", "WAIT_SEM", -#ifndef CONFIG_DISABLE_SIGNALS "WAIT_SIG", -#endif /* CONFIG_DISABLE_SIGNALS */ -#ifndef CONFIG_DISABLE_MQUEUE "WAIT_MQNOTEMPTY", "WAIT_MQNOTFULL", -#endif /* CONFIG_DISABLE_MQUEUE */ -#ifdef CONFIG_PAGING "WAIT_PAGEFILL", -#endif /* CONFIG_PAGING */ + "STOPPED", }; -/* see arch/arm/include/armv7-m/irq_cmnvector.h */ -static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = { - { ARMV7M_R0, 0x28, 32 }, /* r0 */ - { ARMV7M_R1, 0x2c, 32 }, /* r1 */ - { ARMV7M_R2, 0x30, 32 }, /* r2 */ - { ARMV7M_R3, 0x34, 32 }, /* r3 */ - { ARMV7M_R4, 0x08, 32 }, /* r4 */ - { ARMV7M_R5, 0x0c, 32 }, /* r5 */ - { ARMV7M_R6, 0x10, 32 }, /* r6 */ - { ARMV7M_R7, 0x14, 32 }, /* r7 */ - { ARMV7M_R8, 0x18, 32 }, /* r8 */ - { ARMV7M_R9, 0x1c, 32 }, /* r9 */ - { ARMV7M_R10, 0x20, 32 }, /* r10 */ - { ARMV7M_R11, 0x24, 32 }, /* r11 */ - { ARMV7M_R12, 0x38, 32 }, /* r12 */ - { ARMV7M_R13, 0, 32 }, /* sp */ - { ARMV7M_R14, 0x3c, 32 }, /* lr */ - { ARMV7M_PC, 0x40, 32 }, /* pc */ - { ARMV7M_xPSR, 0x44, 32 }, /* xPSR */ +static const struct nuttx_params nuttx_params_list[] = { + { + .target_name = "cortex_m", + .stacking = &nuttx_stacking_cortex_m, + }, + { + .target_name = "hla_target", + .stacking = &nuttx_stacking_cortex_m, + }, + { + .target_name = "esp32", + .stacking = &nuttx_esp32_stacking, + }, + { + .target_name = "esp32s2", + .stacking = &nuttx_esp32s2_stacking, + }, + { + .target_name = "esp32s3", + .stacking = &nuttx_esp32s3_stacking, + }, + { + .target_name = "esp32c3", + .stacking = &nuttx_riscv_stacking, + }, }; - -static const struct rtos_register_stacking nuttx_stacking_cortex_m = { - .stack_registers_size = 0x48, - .stack_growth_direction = -1, - .num_output_registers = 17, - .register_offsets = nuttx_stack_offsets_cortex_m -}; - -static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = { - { ARMV7M_R0, 0x6c, 32 }, /* r0 */ - { ARMV7M_R1, 0x70, 32 }, /* r1 */ - { ARMV7M_R2, 0x74, 32 }, /* r2 */ - { ARMV7M_R3, 0x78, 32 }, /* r3 */ - { ARMV7M_R4, 0x08, 32 }, /* r4 */ - { ARMV7M_R5, 0x0c, 32 }, /* r5 */ - { ARMV7M_R6, 0x10, 32 }, /* r6 */ - { ARMV7M_R7, 0x14, 32 }, /* r7 */ - { ARMV7M_R8, 0x18, 32 }, /* r8 */ - { ARMV7M_R9, 0x1c, 32 }, /* r9 */ - { ARMV7M_R10, 0x20, 32 }, /* r10 */ - { ARMV7M_R11, 0x24, 32 }, /* r11 */ - { ARMV7M_R12, 0x7c, 32 }, /* r12 */ - { ARMV7M_R13, 0, 32 }, /* sp */ - { ARMV7M_R14, 0x80, 32 }, /* lr */ - { ARMV7M_PC, 0x84, 32 }, /* pc */ - { ARMV7M_xPSR, 0x88, 32 }, /* xPSR */ -}; - -static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = { - .stack_registers_size = 0x8c, - .stack_growth_direction = -1, - .num_output_registers = 17, - .register_offsets = nuttx_stack_offsets_cortex_m_fpu -}; - -static int pid_offset = PID; -static int state_offset = STATE; -static int name_offset = NAME; -static int xcpreg_offset = XCPREG; -static int name_size = NAME_SIZE; - -static int rcmd_offset(const char *cmd, const char *name) +static bool nuttx_detect_rtos(struct target *target) { - if (strncmp(cmd, name, strlen(name))) - return -1; - - if (strlen(cmd) <= strlen(name) + 1) - return -1; - - return atoi(cmd + strlen(name)); + if (target->rtos->symbols && + target->rtos->symbols[NX_SYM_READYTORUN].address != 0 && + target->rtos->symbols[NX_SYM_PIDHASH].address != 0) + return true; + return false; } -static int nuttx_thread_packet(struct connection *connection, - char const *packet, int packet_size) +static int nuttx_create(struct target *target) { - char cmd[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for null-termination */ - - if (!strncmp(packet, "qRcmd", 5)) { - size_t len = unhexify((uint8_t *)cmd, packet + 6, sizeof(cmd)); - int offset; - - if (len <= 0) - goto pass; - - offset = rcmd_offset(cmd, "nuttx.pid_offset"); - - if (offset >= 0) { - LOG_INFO("pid_offset: %d", offset); - pid_offset = offset; - goto retok; - } - - offset = rcmd_offset(cmd, "nuttx.state_offset"); - - if (offset >= 0) { - LOG_INFO("state_offset: %d", offset); - state_offset = offset; - goto retok; - } - - offset = rcmd_offset(cmd, "nuttx.name_offset"); + const struct nuttx_params *param; + unsigned int i; - if (offset >= 0) { - LOG_INFO("name_offset: %d", offset); - name_offset = offset; - goto retok; + for (i = 0; i < ARRAY_SIZE(nuttx_params_list); i++) { + param = &nuttx_params_list[i]; + if (strcmp(target_type_name(target), param->target_name) == 0) { + LOG_INFO("Detected target \"%s\"", param->target_name); + break; } + } - offset = rcmd_offset(cmd, "nuttx.xcpreg_offset"); - - if (offset >= 0) { - LOG_INFO("xcpreg_offset: %d", offset); - xcpreg_offset = offset; - goto retok; - } + if (i >= ARRAY_SIZE(nuttx_params_list)) { + LOG_ERROR("Could not find \"%s\" target in NuttX compatibility list", target_type_name(target)); + return ERROR_FAIL; + } - offset = rcmd_offset(cmd, "nuttx.name_size"); + /* We found a target in our list, copy its reference. */ + target->rtos->rtos_specific_params = (void *)param; - if (offset >= 0) { - LOG_INFO("name_size: %d", offset); - name_size = offset; - goto retok; - } - } -pass: - return rtos_thread_packet(connection, packet, packet_size); -retok: - gdb_put_packet(connection, "OK", 2); return ERROR_OK; } - -static bool nuttx_detect_rtos(struct target *target) +static int nuttx_smp_init(struct target *target) { - if ((target->rtos->symbols) && - (target->rtos->symbols[0].address != 0) && - (target->rtos->symbols[1].address != 0)) { - return true; - } - return false; + /* Return OK for now so that the initialisation sequence doesn't stop. + * SMP case will be implemented later. */ + return ERROR_OK; } -static int nuttx_create(struct target *target) +static target_addr_t target_buffer_get_addr(struct target *target, const uint8_t *buffer) { - - target->rtos->gdb_thread_packet = nuttx_thread_packet; - LOG_INFO("target type name = %s", target->type->name); - return 0; +#if PTR_WIDTH == 8 + return target_buffer_get_u64(target, buffer); +#else + return target_buffer_get_u32(target, buffer); +#endif } static int nuttx_update_threads(struct rtos *rtos) { - uint32_t thread_count; - struct tcb tcb; - int ret; - uint32_t head; - uint32_t tcb_addr; - uint32_t i; + struct tcbinfo tcbinfo; + uint32_t pidhashaddr, npidhash, tcbaddr; + uint16_t pid; uint8_t state; if (!rtos->symbols) { - LOG_ERROR("No symbols for NuttX"); - return -3; + LOG_ERROR("No symbols for nuttx"); + return ERROR_FAIL; } - /* free previous thread details */ + /* Free previous thread details */ rtos_free_threadlist(rtos); - ret = target_read_buffer(rtos->target, rtos->symbols[1].address, - sizeof(g_tasklist), (uint8_t *)&g_tasklist); - if (ret) { - LOG_ERROR("target_read_buffer : ret = %d\n", ret); + /* NuttX provides a hash table that keeps track of all the TCBs. + * We first read its size from g_npidhash and its address from g_pidhash. + * Its content is then read from these values. + */ + int ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_NPIDHASH].address, &npidhash); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read g_npidhash: ret = %d", ret); + return ERROR_FAIL; + } + + LOG_DEBUG("Hash table size (g_npidhash) = %" PRId32, npidhash); + + ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_PIDHASH].address, &pidhashaddr); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read g_pidhash address: ret = %d", ret); return ERROR_FAIL; } - thread_count = 0; + LOG_DEBUG("Hash table address (g_pidhash) = %" PRIx32, pidhashaddr); + + uint8_t *pidhash = malloc(npidhash * PTR_WIDTH); + if (!pidhash) { + LOG_ERROR("Failed to allocate pidhash"); + return ERROR_FAIL; + } - for (i = 0; i < TASK_QUEUE_NUM; i++) { + ret = target_read_buffer(rtos->target, pidhashaddr, PTR_WIDTH * npidhash, pidhash); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read tcbhash: ret = %d", ret); + goto errout; + } - if (g_tasklist[i].addr == 0) + /* NuttX provides a struct that contains TCB offsets for required members. + * Read its content from g_tcbinfo. + */ + uint8_t buff[TCBINFO_TARGET_SIZE]; + ret = target_read_buffer(rtos->target, rtos->symbols[NX_SYM_TCB_INFO].address, sizeof(buff), buff); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read tcbinfo: ret = %d", ret); + goto errout; + } + tcbinfo.pid_off = target_buffer_get_u16(rtos->target, buff); + tcbinfo.state_off = target_buffer_get_u16(rtos->target, buff + 2); + tcbinfo.pri_off = target_buffer_get_u16(rtos->target, buff + 4); + tcbinfo.name_off = target_buffer_get_u16(rtos->target, buff + 6); + tcbinfo.regs_off = target_buffer_get_u16(rtos->target, buff + 8); + tcbinfo.basic_num = target_buffer_get_u16(rtos->target, buff + 10); + tcbinfo.total_num = target_buffer_get_u16(rtos->target, buff + 12); + tcbinfo.xcpreg_off = target_buffer_get_addr(rtos->target, buff + 14); + + /* The head of the g_readytorun list is the currently running task. + * Reading in a temporary variable first to avoid endianness issues, + * rtos->current_thread is int64_t. */ + uint32_t current_thread; + ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_READYTORUN].address, ¤t_thread); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read g_readytorun: ret = %d", ret); + goto errout; + } + rtos->current_thread = current_thread; + + uint32_t thread_count = 0; + + for (unsigned int i = 0; i < npidhash; i++) { + tcbaddr = target_buffer_get_u32(rtos->target, &pidhash[i * PTR_WIDTH]); + + if (!tcbaddr) continue; - ret = target_read_u32(rtos->target, g_tasklist[i].addr, - &head); + ret = target_read_u16(rtos->target, tcbaddr + tcbinfo.pid_off, &pid); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read PID of TCB@0x%x from pidhash[%d]: ret = %d", + tcbaddr, i, ret); + goto errout; + } - if (ret) { - LOG_ERROR("target_read_u32 : ret = %d\n", ret); - return ERROR_FAIL; + ret = target_read_u8(rtos->target, tcbaddr + tcbinfo.state_off, &state); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read state of TCB@0x%x from pidhash[%d]: ret = %d", + tcbaddr, i, ret); + goto errout; } - /* readytorun head is current thread */ - if (g_tasklist[i].addr == rtos->symbols[0].address) - rtos->current_thread = head; + struct thread_detail *new_thread_details = realloc(rtos->thread_details, + sizeof(struct thread_detail) * (thread_count + 1)); + if (!new_thread_details) { + ret = ERROR_FAIL; + goto errout; + } + struct thread_detail *thread = &new_thread_details[thread_count]; + thread->threadid = tcbaddr; + thread->exists = true; + thread->extra_info_str = NULL; - tcb_addr = head; - while (tcb_addr) { - struct thread_detail *thread; - ret = target_read_buffer(rtos->target, tcb_addr, - sizeof(tcb), (uint8_t *)&tcb); - if (ret) { - LOG_ERROR("target_read_buffer : ret = %d\n", - ret); - return ERROR_FAIL; - } - thread_count++; - - rtos->thread_details = realloc(rtos->thread_details, - sizeof(struct thread_detail) * thread_count); - thread = &rtos->thread_details[thread_count - 1]; - thread->threadid = tcb_addr; - thread->exists = true; - - state = tcb.dat[state_offset - 8]; - thread->extra_info_str = NULL; - if (state < ARRAY_SIZE(task_state_str)) { - thread->extra_info_str = malloc(256); - snprintf(thread->extra_info_str, 256, "pid:%d, %s", - tcb.dat[pid_offset - 8] | - tcb.dat[pid_offset - 8 + 1] << 8, - task_state_str[state]); - } + rtos->thread_details = new_thread_details; + thread_count++; - if (name_offset) { - thread->thread_name_str = malloc(name_size + 1); - snprintf(thread->thread_name_str, name_size, - "%s", (char *)&tcb.dat[name_offset - 8]); - } else { - thread->thread_name_str = malloc(sizeof("None")); - strcpy(thread->thread_name_str, "None"); + if (state < ARRAY_SIZE(task_state_str)) { + thread->extra_info_str = malloc(EXTRAINFO_SIZE); + if (!thread->extra_info_str) { + ret = ERROR_FAIL; + goto errout; } + snprintf(thread->extra_info_str, EXTRAINFO_SIZE, "pid:%d, %s", + pid, + task_state_str[state]); + } - tcb_addr = tcb.flink; + if (tcbinfo.name_off) { + thread->thread_name_str = calloc(NAME_SIZE + 1, sizeof(char)); + if (!thread->thread_name_str) { + ret = ERROR_FAIL; + goto errout; + } + ret = target_read_buffer(rtos->target, tcbaddr + tcbinfo.name_off, + sizeof(char) * NAME_SIZE, (uint8_t *)thread->thread_name_str); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read thread's name: ret = %d", ret); + goto errout; + } + } else { + thread->thread_name_str = strdup("None"); } } - rtos->thread_count = thread_count; - return 0; + ret = ERROR_OK; + rtos->thread_count = thread_count; +errout: + free(pidhash); + return ret; } +static int nuttx_getreg_current_thread(struct rtos *rtos, + struct rtos_reg **reg_list, int *num_regs) +{ + struct reg **gdb_reg_list; + + /* Registers for currently running thread are not on task's stack and + * should be retrieved from reg caches via target_get_gdb_reg_list */ + int ret = target_get_gdb_reg_list(rtos->target, &gdb_reg_list, num_regs, + REG_CLASS_GENERAL); + if (ret != ERROR_OK) { + LOG_ERROR("target_get_gdb_reg_list failed %d", ret); + return ret; + } -/* - * thread_id = tcb address; - */ -static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, + *reg_list = calloc(*num_regs, sizeof(struct rtos_reg)); + if (!(*reg_list)) { + LOG_ERROR("Failed to alloc memory for %d", *num_regs); + free(gdb_reg_list); + return ERROR_FAIL; + } + + for (int i = 0; i < *num_regs; i++) { + (*reg_list)[i].number = gdb_reg_list[i]->number; + (*reg_list)[i].size = gdb_reg_list[i]->size; + memcpy((*reg_list)[i].value, gdb_reg_list[i]->value, ((*reg_list)[i].size + 7) / 8); + } + + free(gdb_reg_list); + + return ERROR_OK; +} + +static int nuttx_getregs_fromstack(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs) { - int retval; - - /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */ - bool cm4_fpu_enabled = false; - struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); - if (is_armv7m(armv7m_target)) { - if (armv7m_target->fp_feature == FPV4_SP) { - /* Found ARM v7m target which includes a FPU */ - uint32_t cpacr; - - retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr); - if (retval != ERROR_OK) { - LOG_ERROR("Could not read CPACR register to check FPU state"); - return -1; - } + uint16_t regs_off; + uint32_t regsaddr; + const struct nuttx_params *priv = rtos->rtos_specific_params; + const struct rtos_register_stacking *stacking = priv->stacking; - /* Check if CP10 and CP11 are set to full access. */ - if (cpacr & 0x00F00000) { - /* Found target with enabled FPU */ - cm4_fpu_enabled = 1; - } - } + if (!stacking) { + LOG_ERROR("Can't find a way to get stacking info"); + return ERROR_FAIL; } - const struct rtos_register_stacking *stacking; - if (cm4_fpu_enabled) - stacking = &nuttx_stacking_cortex_m_fpu; - else - stacking = &nuttx_stacking_cortex_m; + int ret = target_read_u16(rtos->target, + rtos->symbols[NX_SYM_TCB_INFO].address + offsetof(struct tcbinfo, regs_off), + ®s_off); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read registers' offset: ret = %d", ret); + return ERROR_FAIL; + } + + ret = target_read_u32(rtos->target, thread_id + regs_off, ®saddr); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read registers' address: ret = %d", ret); + return ERROR_FAIL; + } - return rtos_generic_stack_read(rtos->target, stacking, - (uint32_t)thread_id + xcpreg_offset, reg_list, num_regs); + return rtos_generic_stack_read(rtos->target, stacking, regsaddr, reg_list, num_regs); } -static int nuttx_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, + struct rtos_reg **reg_list, int *num_regs) { - unsigned int i; + if (!rtos) { + LOG_ERROR("NUTTX: out of memory"); + return ERROR_FAIL; + } + + if (thread_id == rtos->current_thread) + return nuttx_getreg_current_thread(rtos, reg_list, num_regs); + return nuttx_getregs_fromstack(rtos, thread_id, reg_list, num_regs); +} - *symbol_list = (struct symbol_table_elem *) calloc(1, - sizeof(struct symbol_table_elem) * ARRAY_SIZE(nuttx_symbol_list)); +static int nuttx_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +{ + *symbol_list = calloc(ARRAY_SIZE(nuttx_symbol_list), sizeof(**symbol_list)); + if (!*symbol_list) { + LOG_ERROR("NUTTX: out of memory"); + return ERROR_FAIL; + } - for (i = 0; i < ARRAY_SIZE(nuttx_symbol_list); i++) - (*symbol_list)[i].symbol_name = nuttx_symbol_list[i]; + for (unsigned int i = 0; i < ARRAY_SIZE(nuttx_symbol_list); i++) { + (*symbol_list)[i].symbol_name = nuttx_symbol_list[i].name; + (*symbol_list)[i].optional = nuttx_symbol_list[i].optional; + } - return 0; + return ERROR_OK; } -struct rtos_type nuttx_rtos = { +const struct rtos_type nuttx_rtos = { .name = "nuttx", .detect_rtos = nuttx_detect_rtos, .create = nuttx_create, + .smp_init = nuttx_smp_init, .update_threads = nuttx_update_threads, .get_thread_reg_list = nuttx_get_thread_reg_list, .get_symbol_list_to_lookup = nuttx_get_symbol_list_to_lookup, diff --git a/src/rtos/nuttx_header.h b/src/rtos/nuttx_header.h deleted file mode 100644 index 3436df1eb5..0000000000 --- a/src/rtos/nuttx_header.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright 2016,2017 Sony Video & Sound Products Inc. * - * Masatoshi Tateishi - Masatoshi.Tateishi@jp.sony.com * - * Masayuki Ishikawa - Masayuki.Ishikawa@jp.sony.com * - ***************************************************************************/ - -#ifndef OPENOCD_RTOS_NUTTX_HEADER_H -#define OPENOCD_RTOS_NUTTX_HEADER_H - -/* gdb script to update the header file - according to kernel version and build option - before executing function awareness - kernel symbol must be loaded : symbol nuttx - -define awareness - set logging off - set logging file nuttx_header.h - set logging on - - printf "#define PID %p\n",&((struct tcb_s *)(0))->pid - printf "#define XCPREG %p\n",&((struct tcb_s *)(0))->xcp.regs - printf "#define STATE %p\n",&((struct tcb_s *)(0))->task_state - printf "#define NAME %p\n",&((struct tcb_s *)(0))->name - printf "#define NAME_SIZE %d\n",sizeof(((struct tcb_s *)(0))->name) - end - - - OR ~/.gdbinit - - -define hookpost-file - - if &g_readytorun != 0 - eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid - eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs - eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state - eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name - eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name) - end - -end - -*/ - -/* default offset */ -#define PID 0xc -#define XCPREG 0x70 -#define STATE 0x19 -#define NAME 0xb8 -#define NAME_SIZE 32 - -/* defconfig of nuttx */ -/* #define CONFIG_DISABLE_SIGNALS */ -#define CONFIG_DISABLE_MQUEUE -/* #define CONFIG_PAGING */ - - -#endif /* OPENOCD_RTOS_NUTTX_HEADER_H */ diff --git a/src/rtos/riot.c b/src/rtos/riot.c index 6717085d59..b90b069148 100644 --- a/src/rtos/riot.c +++ b/src/rtos/riot.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Daniel Krebs * @@ -12,7 +12,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -391,7 +390,7 @@ static int riot_create(struct target *target) /* lookup if target is supported by RIOT */ while ((i < RIOT_NUM_PARAMS) && - (strcmp(riot_params_list[i].target_name, target->type->name) != 0)) { + (strcmp(riot_params_list[i].target_name, target_type_name(target)) != 0)) { i++; } if (i >= RIOT_NUM_PARAMS) { diff --git a/src/rtos/rtkernel.c b/src/rtos/rtkernel.c new file mode 100644 index 0000000000..2be1996fcd --- /dev/null +++ b/src/rtos/rtkernel.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2016-2023 by Andreas Fritiofson * + * andreas.fritiofson@gmail.com * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/time_support.h> +#include <jtag/jtag.h> +#include "target/target.h" +#include "rtos.h" +#include "helper/log.h" +#include "helper/types.h" +#include "rtos_standard_stackings.h" +#include "target/armv7m.h" +#include "target/cortex_m.h" + +#define ST_DEAD BIT(0) /* Task is waiting to be deleted */ +#define ST_WAIT BIT(1) /* Task is blocked: */ +#define ST_SEM BIT(2) /* on semaphore */ +#define ST_MTX BIT(3) /* on mutex */ +#define ST_SIG BIT(4) /* on signal */ +#define ST_DLY BIT(5) /* on timer */ +#define ST_FLAG BIT(6) /* on flag */ +#define ST_FLAG_ALL BIT(7) /* on flag and flag mode is "ALL" */ +#define ST_MBOX BIT(8) /* on mailbox */ +#define ST_STP BIT(9) /* self stopped */ +#define ST_SUSPEND BIT(10) /* Task is suspended */ +#define ST_TT BIT(11) /* Time triggered task */ +#define ST_TT_YIELD BIT(12) /* Time triggered task that yields */ +#define ST_CREATE BIT(13) /* Task was created by task_create() */ + +struct rtkernel_params { + const char *target_name; + const struct rtos_register_stacking *stacking_info_cm3; + const struct rtos_register_stacking *stacking_info_cm4f; + const struct rtos_register_stacking *stacking_info_cm4f_fpu; +}; + +static const struct rtkernel_params rtkernel_params_list[] = { + { + "cortex_m", /* target_name */ + &rtos_standard_cortex_m3_stacking, /* stacking_info */ + &rtos_standard_cortex_m4f_stacking, + &rtos_standard_cortex_m4f_fpu_stacking, + }, + { + "hla_target", /* target_name */ + &rtos_standard_cortex_m3_stacking, /* stacking_info */ + &rtos_standard_cortex_m4f_stacking, + &rtos_standard_cortex_m4f_fpu_stacking, + }, +}; + +enum rtkernel_symbol_values { + sym_os_state = 0, + sym___off_os_state2chain = 1, + sym___off_os_state2current = 2, + sym___off_task2chain = 3, + sym___off_task2magic = 4, + sym___off_task2stack = 5, + sym___off_task2state = 6, + sym___off_task2name = 7, + sym___val_task_magic = 8, +}; + +struct symbols { + const char *name; + bool optional; +}; + +static const struct symbols rtkernel_symbol_list[] = { + { "os_state", false }, + { "__off_os_state2chain", false }, + { "__off_os_state2current", false }, + { "__off_task2chain", false }, + { "__off_task2magic", false }, + { "__off_task2stack", false }, + { "__off_task2state", false }, + { "__off_task2name", false }, + { "__val_task_magic", false }, + { NULL, false } +}; + +static void *realloc_preserve(void *ptr, size_t old_size, size_t new_size) +{ + void *new_ptr = malloc(new_size); + + if (new_ptr) { + memcpy(new_ptr, ptr, MIN(old_size, new_size)); + free(ptr); + } + + return new_ptr; +} + +static int rtkernel_add_task(struct rtos *rtos, uint32_t task, uint32_t current_task) +{ + int retval; + int new_thread_count = rtos->thread_count + 1; + struct thread_detail *new_thread_details = realloc_preserve(rtos->thread_details, + rtos->thread_count * sizeof(struct thread_detail), + new_thread_count * sizeof(struct thread_detail)); + if (!new_thread_details) { + LOG_ERROR("Error growing memory to %d threads", new_thread_count); + return ERROR_FAIL; + } + rtos->thread_details = new_thread_details; + struct thread_detail *thread = &new_thread_details[rtos->thread_count]; + + *thread = (struct thread_detail){ .threadid = task, .exists = true }; + + /* Read the task name */ + uint32_t name; + retval = target_read_u32(rtos->target, task + rtos->symbols[sym___off_task2name].address, &name); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read task name pointer from target"); + return retval; + } + uint8_t tmp_str[33]; + retval = target_read_buffer(rtos->target, name, sizeof(tmp_str) - 1, tmp_str); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading task name from target"); + return retval; + } + tmp_str[sizeof(tmp_str) - 1] = '\0'; + LOG_DEBUG("task name at 0x%" PRIx32 ", value \"%s\"", name, tmp_str); + + if (tmp_str[0] != '\0') + thread->thread_name_str = strdup((char *)tmp_str); + else + thread->thread_name_str = strdup("No Name"); + + /* Read the task state */ + uint16_t state; + retval = target_read_u16(rtos->target, task + rtos->symbols[sym___off_task2state].address, &state); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read task state from target"); + return retval; + } + + LOG_DEBUG("task state 0x%" PRIx16, state); + + char state_str[64] = ""; + if (state & ST_TT) + strcat(state_str, "TT|"); + if (task == current_task) { + strcat(state_str, "RUN"); + } else { + if (state & (ST_TT | ST_TT_YIELD)) + strcat(state_str, "YIELD"); + else if (state & ST_DEAD) + strcat(state_str, "DEAD"); + else if (state & ST_WAIT) + strcat(state_str, "WAIT"); + else if (state & ST_SUSPEND) + strcat(state_str, "SUSP"); + else + strcat(state_str, "READY"); + } + if (state & ST_SEM) + strcat(state_str, "|SEM"); + if (state & ST_MTX) + strcat(state_str, "|MTX"); + if (state & ST_SIG) + strcat(state_str, "|SIG"); + if (state & ST_DLY) + strcat(state_str, "|DLY"); + if ((state & ST_FLAG) || (state & ST_FLAG_ALL)) + strcat(state_str, "|FLAG"); + if (state & ST_FLAG_ALL) + strcat(state_str, "_ALL"); + if (state & ST_MBOX) + strcat(state_str, "|MBOX"); + if (state & ST_STP) + strcat(state_str, "|STP"); + + thread->extra_info_str = strdup(state_str); + + rtos->thread_count = new_thread_count; + if (task == current_task) + rtos->current_thread = task; + return ERROR_OK; +} + +static int rtkernel_verify_task(struct rtos *rtos, uint32_t task) +{ + int retval; + uint32_t magic; + retval = target_read_u32(rtos->target, task + rtos->symbols[sym___off_task2magic].address, &magic); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read task magic from target"); + return retval; + } + if (magic != rtos->symbols[sym___val_task_magic].address) { + LOG_ERROR("Invalid task found (magic=0x%" PRIx32 ")", magic); + return ERROR_FAIL; + } + return retval; +} + +static int rtkernel_update_threads(struct rtos *rtos) +{ + /* wipe out previous thread details if any */ + /* do this first because rtos layer does not check our retval */ + rtos_free_threadlist(rtos); + rtos->current_thread = 0; + + if (!rtos->symbols) { + LOG_ERROR("No symbols for rt-kernel"); + return -3; + } + + /* read the current task */ + uint32_t current_task; + int retval = target_read_u32(rtos->target, + rtos->symbols[sym_os_state].address + rtos->symbols[sym___off_os_state2current].address, + ¤t_task); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading current task"); + return retval; + } + LOG_DEBUG("current task is 0x%" PRIx32, current_task); + + retval = rtkernel_verify_task(rtos, current_task); + if (retval != ERROR_OK) { + LOG_ERROR("Current task is invalid"); + return retval; + } + + /* loop through kernel task list */ + uint32_t chain = rtos->symbols[sym_os_state].address + rtos->symbols[sym___off_os_state2chain].address; + LOG_DEBUG("chain start at 0x%" PRIx32, chain); + + uint32_t next = chain; + for (;;) { + retval = target_read_u32(rtos->target, next, &next); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read rt-kernel data structure from target"); + return retval; + } + LOG_DEBUG("next entry at 0x%" PRIx32, next); + if (next == chain) { + LOG_DEBUG("end of chain detected"); + break; + } + uint32_t task = next - rtos->symbols[sym___off_task2chain].address; + LOG_DEBUG("found task at 0x%" PRIx32, task); + + retval = rtkernel_verify_task(rtos, task); + if (retval != ERROR_OK) { + LOG_ERROR("Invalid task found"); + return retval; + } + + retval = rtkernel_add_task(rtos, task, current_task); + if (retval != ERROR_OK) { + LOG_ERROR("Could not add task to rtos system"); + return retval; + } + } + return ERROR_OK; +} + +static int rtkernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, + struct rtos_reg **reg_list, int *num_regs) +{ + uint32_t stack_ptr = 0; + + if (!rtos) + return -1; + + if (thread_id == 0) + return -2; + + if (!rtos->rtos_specific_params) + return -1; + + const struct rtkernel_params *param = rtos->rtos_specific_params; + + /* Read the stack pointer */ + int retval = target_read_u32(rtos->target, thread_id + rtos->symbols[sym___off_task2stack].address, &stack_ptr); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading stack pointer from rtkernel thread"); + return retval; + } + LOG_DEBUG("stack pointer at 0x%" PRIx64 ", value 0x%" PRIx32, + thread_id + rtos->symbols[sym___off_task2stack].address, + stack_ptr); + + /* Adjust stack pointer to ignore non-standard BASEPRI register stacking */ + stack_ptr += 4; + + /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */ + bool cm4_fpu_enabled = false; + struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); + if (is_armv7m(armv7m_target)) { + if (armv7m_target->fp_feature != FP_NONE) { + /* Found ARM v7m target which includes a FPU */ + uint32_t cpacr; + + retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read CPACR register to check FPU state"); + return -1; + } + + /* Check if CP10 and CP11 are set to full access. */ + if (cpacr & 0x00F00000) { + /* Found target with enabled FPU */ + cm4_fpu_enabled = true; + } + } + } + + if (!cm4_fpu_enabled) { + LOG_DEBUG("cm3 stacking"); + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3, stack_ptr, reg_list, num_regs); + } + + /* Read the LR to decide between stacking with or without FPU */ + uint32_t lr_svc; + retval = target_read_u32(rtos->target, stack_ptr + 0x20, &lr_svc); + if (retval != ERROR_OK) { + LOG_OUTPUT("Error reading stack frame from rtkernel thread\r\n"); + return retval; + } + + if ((lr_svc & 0x10) == 0) { + LOG_DEBUG("cm4f_fpu stacking"); + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu, stack_ptr, reg_list, num_regs); + } + + LOG_DEBUG("cm4f stacking"); + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f, stack_ptr, reg_list, num_regs); +} + +static int rtkernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +{ + *symbol_list = calloc(ARRAY_SIZE(rtkernel_symbol_list), sizeof(struct symbol_table_elem)); + if (!*symbol_list) + return ERROR_FAIL; + + for (size_t i = 0; i < ARRAY_SIZE(rtkernel_symbol_list); i++) { + (*symbol_list)[i].symbol_name = rtkernel_symbol_list[i].name; + (*symbol_list)[i].optional = rtkernel_symbol_list[i].optional; + } + + return ERROR_OK; +} + +static bool rtkernel_detect_rtos(struct target *target) +{ + return (target->rtos->symbols) && + (target->rtos->symbols[sym___off_os_state2chain].address != 0); +} + +static int rtkernel_create(struct target *target) +{ + for (size_t i = 0; i < ARRAY_SIZE(rtkernel_params_list); i++) { + if (strcmp(rtkernel_params_list[i].target_name, target_type_name(target)) == 0) { + target->rtos->rtos_specific_params = (void *)&rtkernel_params_list[i]; + return ERROR_OK; + } + } + + LOG_ERROR("Could not find target in rt-kernel compatibility list"); + return ERROR_FAIL; +} + +const struct rtos_type rtkernel_rtos = { + .name = "rtkernel", + + .detect_rtos = rtkernel_detect_rtos, + .create = rtkernel_create, + .update_threads = rtkernel_update_threads, + .get_thread_reg_list = rtkernel_get_thread_reg_list, + .get_symbol_list_to_lookup = rtkernel_get_symbol_list_to_lookup, +}; diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 013080bb0c..2ccccf1b0d 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -13,45 +13,29 @@ #include "target/target.h" #include "helper/log.h" #include "helper/binarybuffer.h" +#include "helper/types.h" #include "server/gdb_server.h" -/* RTOSs */ -extern struct rtos_type freertos_rtos; -extern struct rtos_type threadx_rtos; -extern struct rtos_type ecos_rtos; -extern struct rtos_type linux_rtos; -extern struct rtos_type chibios_rtos; -extern struct rtos_type chromium_ec_rtos; -extern struct rtos_type embkernel_rtos; -extern struct rtos_type mqx_rtos; -extern struct rtos_type ucos_iii_rtos; -extern struct rtos_type nuttx_rtos; -extern struct rtos_type hwthread_rtos; -extern struct rtos_type riot_rtos; -extern struct rtos_type zephyr_rtos; - -static struct rtos_type *rtos_types[] = { - &threadx_rtos, - &freertos_rtos, - &ecos_rtos, - &linux_rtos, +static const struct rtos_type *rtos_types[] = { + // Keep in alphabetic order this list of rtos, except hwthread &chibios_rtos, &chromium_ec_rtos, + &ecos_rtos, &embkernel_rtos, + &freertos_rtos, + &linux_rtos, &mqx_rtos, - &ucos_iii_rtos, &nuttx_rtos, &riot_rtos, + &rtkernel_rtos, + &threadx_rtos, + &ucos_iii_rtos, &zephyr_rtos, - /* keep this as last, as it always matches with rtos auto */ + + // keep this as last, as it always matches with rtos auto &hwthread_rtos, - NULL }; -static int rtos_try_next(struct target *target); - -int rtos_thread_packet(struct connection *connection, const char *packet, int packet_size); - int rtos_smp_init(struct target *target) { if (target->rtos->type->smp_init) @@ -68,12 +52,12 @@ static int rtos_target_for_threadid(struct connection *connection, int64_t threa return ERROR_OK; } -static int os_alloc(struct target *target, struct rtos_type *ostype) +static int os_alloc(struct target *target, const struct rtos_type *ostype) { struct rtos *os = target->rtos = calloc(1, sizeof(struct rtos)); if (!os) - return JIM_ERR; + return ERROR_FAIL; os->type = ostype; os->current_threadid = -1; @@ -85,7 +69,7 @@ static int os_alloc(struct target *target, struct rtos_type *ostype) os->gdb_thread_packet = rtos_thread_packet; os->gdb_target_for_threadid = rtos_target_for_threadid; - return JIM_OK; + return ERROR_OK; } static void os_free(struct target *target) @@ -94,42 +78,34 @@ static void os_free(struct target *target) return; free(target->rtos->symbols); + rtos_free_threadlist(target->rtos); free(target->rtos); target->rtos = NULL; } -static int os_alloc_create(struct target *target, struct rtos_type *ostype) +static int os_alloc_create(struct target *target, const struct rtos_type *ostype) { int ret = os_alloc(target, ostype); + if (ret != ERROR_OK) + return ret; - if (ret == JIM_OK) { - ret = target->rtos->type->create(target); - if (ret != JIM_OK) - os_free(target); - } + ret = target->rtos->type->create(target); + if (ret != ERROR_OK) + os_free(target); return ret; } -int rtos_create(struct jim_getopt_info *goi, struct target *target) +int rtos_create(struct command_invocation *cmd, struct target *target, + const char *rtos_name) { - int x; - const char *cp; - Jim_Obj *res; - int e; - - if (!goi->isconfigure && goi->argc != 0) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS"); - return JIM_ERR; - } - os_free(target); + target->rtos_auto_detect = false; - e = jim_getopt_string(goi, &cp, NULL); - if (e != JIM_OK) - return e; + if (strcmp(rtos_name, "none") == 0) + return ERROR_OK; - if (strcmp(cp, "auto") == 0) { + if (strcmp(rtos_name, "auto") == 0) { /* Auto detect tries to look up all symbols for each RTOS, * and runs the RTOS driver's _detect() function when GDB * finds all symbols for any RTOS. See rtos_qsymbol(). */ @@ -140,17 +116,29 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target) return os_alloc(target, rtos_types[0]); } - for (x = 0; rtos_types[x]; x++) - if (strcmp(cp, rtos_types[x]->name) == 0) + for (size_t x = 0; x < ARRAY_SIZE(rtos_types); x++) + if (strcmp(rtos_name, rtos_types[x]->name) == 0) return os_alloc_create(target, rtos_types[x]); - Jim_SetResultFormatted(goi->interp, "Unknown RTOS type %s, try one of: ", cp); - res = Jim_GetResult(goi->interp); - for (x = 0; rtos_types[x]; x++) - Jim_AppendStrings(goi->interp, res, rtos_types[x]->name, ", ", NULL); - Jim_AppendStrings(goi->interp, res, " or auto", NULL); + char *all = NULL; + for (size_t x = 0; x < ARRAY_SIZE(rtos_types); x++) { + char *prev = all; + if (all) + all = alloc_printf("%s, %s", all, rtos_types[x]->name); + else + all = alloc_printf("%s", rtos_types[x]->name); + free(prev); + if (!all) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + } + + command_print(cmd, "Unknown RTOS type %s, try one of: %s, auto or none", + rtos_name, all); + free(all); - return JIM_ERR; + return ERROR_COMMAND_ARGUMENT_INVALID; } void rtos_destroy(struct target *target) @@ -167,35 +155,55 @@ int gdb_thread_packet(struct connection *connection, char const *packet, int pac return target->rtos->gdb_thread_packet(connection, packet, packet_size); } -static struct symbol_table_elem *next_symbol(struct rtos *os, char *cur_symbol, uint64_t cur_addr) +static bool rtos_try_next(struct target *target) { - struct symbol_table_elem *s; + struct rtos *os = target->rtos; - if (!os->symbols) - os->type->get_symbol_list_to_lookup(&os->symbols); + if (!os) + return false; - if (!cur_symbol[0]) - return &os->symbols[0]; + for (size_t x = 0; x < ARRAY_SIZE(rtos_types) - 1; x++) { + if (os->type == rtos_types[x]) { + // Use next RTOS in the list + os->type = rtos_types[x + 1]; + + free(os->symbols); + os->symbols = NULL; + + return true; + } + } + + // No next RTOS to try + return false; +} + +static struct symbol_table_elem *find_symbol(const struct rtos *os, const char *symbol) +{ + struct symbol_table_elem *s; for (s = os->symbols; s->symbol_name; s++) - if (!strcmp(s->symbol_name, cur_symbol)) { - s->address = cur_addr; - s++; + if (!strcmp(s->symbol_name, symbol)) return s; - } return NULL; } -/* searches for 'symbol' in the lookup table for 'os' and returns TRUE, - * if 'symbol' is not declared optional */ -static bool is_symbol_mandatory(const struct rtos *os, const char *symbol) +static struct symbol_table_elem *next_symbol(struct rtos *os, char *cur_symbol, uint64_t cur_addr) { - for (struct symbol_table_elem *s = os->symbols; s->symbol_name; ++s) { - if (!strcmp(s->symbol_name, symbol)) - return !s->optional; - } - return false; + if (!os->symbols) + os->type->get_symbol_list_to_lookup(&os->symbols); + + if (!cur_symbol[0]) + return &os->symbols[0]; + + struct symbol_table_elem *s = find_symbol(os, cur_symbol); + if (!s) + return NULL; + + s->address = cur_addr; + s++; + return s; } /* rtos_qsymbol() processes and replies to all qSymbol packets from GDB. @@ -215,6 +223,12 @@ static bool is_symbol_mandatory(const struct rtos *os, const char *symbol) * specified explicitly, then no further symbol lookup is done. When * auto-detecting, the RTOS driver _detect() function must return success. * + * The symbol is tried twice to handle the -flto case with gcc. The first + * attempt uses the symbol as-is, and the second attempt tries the symbol + * with ".lto_priv.0" appended to it. We only consider the first static + * symbol here from the -flto case. (Each subsequent static symbol with + * the same name is exported as .lto_priv.1, .lto_priv.2, etc.) + * * rtos_qsymbol() returns 1 if an RTOS has been detected, or 0 otherwise. */ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_size) @@ -223,7 +237,7 @@ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_s uint64_t addr = 0; size_t reply_len; char reply[GDB_BUFFER_SIZE + 1], cur_sym[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for null-termination */ - struct symbol_table_elem *next_sym; + struct symbol_table_elem *next_sym = NULL; struct target *target = get_target_from_connection(connection); struct rtos *os = target->rtos; @@ -236,33 +250,60 @@ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_s size_t len = unhexify((uint8_t *)cur_sym, strchr(packet + 8, ':') + 1, strlen(strchr(packet + 8, ':') + 1)); cur_sym[len] = 0; + const char no_suffix[] = ""; + const char lto_suffix[] = ".lto_priv.0"; + const size_t lto_suffix_len = strlen(lto_suffix); + + const char *cur_suffix; + const char *next_suffix; + + /* Detect what suffix was used during the previous symbol lookup attempt, and + * speculatively determine the next suffix (only used for the unknown address case) */ + if (len > lto_suffix_len && !strcmp(cur_sym + len - lto_suffix_len, lto_suffix)) { + /* Trim the suffix from cur_sym for comparison purposes below */ + cur_sym[len - lto_suffix_len] = '\0'; + cur_suffix = lto_suffix; + next_suffix = NULL; + } else { + cur_suffix = no_suffix; + next_suffix = lto_suffix; + } + if ((strcmp(packet, "qSymbol::") != 0) && /* GDB is not offering symbol lookup for the first time */ - (!sscanf(packet, "qSymbol:%" SCNx64 ":", &addr)) && /* GDB did not find an address for a symbol */ - is_symbol_mandatory(os, cur_sym)) { /* the symbol is mandatory for this RTOS */ + (!sscanf(packet, "qSymbol:%" SCNx64 ":", &addr))) { /* GDB did not find an address for a symbol */ /* GDB could not find an address for the previous symbol */ - if (!target->rtos_auto_detect) { - LOG_WARNING("RTOS %s not detected. (GDB could not find symbol \'%s\')", os->type->name, cur_sym); - goto done; - } else { - /* Autodetecting RTOS - try next RTOS */ - if (!rtos_try_next(target)) { - LOG_WARNING("No RTOS could be auto-detected!"); + struct symbol_table_elem *sym = find_symbol(os, cur_sym); + + if (next_suffix) { + next_sym = sym; + } else if (sym && !sym->optional) { /* the symbol is mandatory for this RTOS */ + if (!target->rtos_auto_detect) { + LOG_WARNING("RTOS %s not detected. (GDB could not find symbol \'%s\')", os->type->name, cur_sym); goto done; - } + } else { + /* Autodetecting RTOS - try next RTOS */ + if (!rtos_try_next(target)) { + LOG_WARNING("No RTOS could be auto-detected!"); + goto done; + } - /* Next RTOS selected - invalidate current symbol */ - cur_sym[0] = '\x00'; + /* Next RTOS selected - invalidate current symbol */ + cur_sym[0] = '\x00'; + } } } - LOG_DEBUG("RTOS: Address of symbol '%s' is 0x%" PRIx64, cur_sym, addr); + LOG_DEBUG("RTOS: Address of symbol '%s%s' is 0x%" PRIx64, cur_sym, cur_suffix, addr); - next_sym = next_symbol(os, cur_sym, addr); + if (!next_sym) { + next_sym = next_symbol(os, cur_sym, addr); + next_suffix = no_suffix; + } /* Should never happen unless the debugger misbehaves */ if (!next_sym) { - LOG_WARNING("RTOS: Debugger sent us qSymbol with '%s' that we did not ask for", cur_sym); + LOG_WARNING("RTOS: Debugger sent us qSymbol with '%s%s' that we did not ask for", cur_sym, cur_suffix); goto done; } @@ -284,17 +325,26 @@ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_s } } - if (8 + (strlen(next_sym->symbol_name) * 2) + 1 > sizeof(reply)) { - LOG_ERROR("ERROR: RTOS symbol '%s' name is too long for GDB!", next_sym->symbol_name); + assert(next_suffix); + + reply_len = 8; /* snprintf(..., "qSymbol:") */ + reply_len += 2 * strlen(next_sym->symbol_name); /* hexify(..., next_sym->symbol_name, ...) */ + reply_len += 2 * strlen(next_suffix); /* hexify(..., next_suffix, ...) */ + reply_len += 1; /* Terminating NUL */ + if (reply_len > sizeof(reply)) { + LOG_ERROR("RTOS symbol '%s%s' name is too long for GDB", next_sym->symbol_name, next_suffix); goto done; } - LOG_DEBUG("RTOS: Requesting symbol lookup of '%s' from the debugger", next_sym->symbol_name); + LOG_DEBUG("RTOS: Requesting symbol lookup of '%s%s' from the debugger", next_sym->symbol_name, next_suffix); reply_len = snprintf(reply, sizeof(reply), "qSymbol:"); reply_len += hexify(reply + reply_len, (const uint8_t *)next_sym->symbol_name, strlen(next_sym->symbol_name), sizeof(reply) - reply_len); + reply_len += hexify(reply + reply_len, + (const uint8_t *)next_suffix, strlen(next_suffix), + sizeof(reply) - reply_len); done: gdb_put_packet(connection, reply, reply_len); @@ -335,6 +385,10 @@ int rtos_thread_packet(struct connection *connection, char const *packet, int pa str_size += strlen(detail->extra_info_str); char *tmp_str = calloc(str_size + 9, sizeof(char)); + if (!tmp_str) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } char *tmp_str_ptr = tmp_str; if (detail->thread_name_str) @@ -362,7 +416,7 @@ int rtos_thread_packet(struct connection *connection, char const *packet, int pa return ERROR_OK; } else if (strncmp(packet, "qSymbol", 7) == 0) { if (rtos_qsymbol(connection, packet, packet_size) == 1) { - if (target->rtos_auto_detect == true) { + if (target->rtos_auto_detect) { target->rtos_auto_detect = false; target->rtos->type->create(target); } @@ -581,7 +635,7 @@ int rtos_generic_stack_read(struct target *target, int retval; if (stack_ptr == 0) { - LOG_ERROR("Error: null stack pointer in thread"); + LOG_ERROR("null stack pointer in thread"); return -5; } /* Read the stack */ @@ -590,7 +644,10 @@ int rtos_generic_stack_read(struct target *target, if (stacking->stack_growth_direction == 1) address -= stacking->stack_registers_size; - retval = target_read_buffer(target, address, stacking->stack_registers_size, stack_data); + if (stacking->read_stack) + retval = stacking->read_stack(target, address, stacking, stack_data); + else + retval = target_read_buffer(target, address, stacking->stack_registers_size, stack_data); if (retval != ERROR_OK) { free(stack_data); LOG_ERROR("Error reading stack frame from thread"); @@ -633,28 +690,6 @@ int rtos_generic_stack_read(struct target *target, return ERROR_OK; } -static int rtos_try_next(struct target *target) -{ - struct rtos *os = target->rtos; - struct rtos_type **type = rtos_types; - - if (!os) - return 0; - - while (*type && os->type != *type) - type++; - - if (!*type || !*(++type)) - return 0; - - os->type = *type; - - free(os->symbols); - os->symbols = NULL; - - return 1; -} - int rtos_update_threads(struct target *target) { if ((target->rtos) && (target->rtos->type)) diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h index ace57514af..dbaa7e8ce8 100644 --- a/src/rtos/rtos.h +++ b/src/rtos/rtos.h @@ -10,7 +10,6 @@ #include "server/server.h" #include "target/target.h" -#include <helper/jim-nvp.h> typedef int64_t threadid_t; typedef int64_t symbol_address_t; @@ -102,11 +101,19 @@ struct rtos_register_stacking { const struct rtos_register_stacking *stacking, target_addr_t stack_ptr); const struct stack_register_offset *register_offsets; + /* Optional field for targets which may have to implement their own stack read function. + * Because stack format can be weird or stack data needed to be edited before passing to the gdb. + */ + int (*read_stack)(struct target *target, + int64_t stack_ptr, + const struct rtos_register_stacking *stacking, + uint8_t *stack_data); }; #define GDB_THREAD_PACKET_NOT_CONSUMED (-40) -int rtos_create(struct jim_getopt_info *goi, struct target *target); +int rtos_create(struct command_invocation *cmd, struct target *target, + const char *rtos_name); void rtos_destroy(struct target *target); int rtos_set_reg(struct connection *connection, int reg_num, uint8_t *reg_value); @@ -116,6 +123,7 @@ int rtos_generic_stack_read(struct target *target, struct rtos_reg **reg_list, int *num_regs); int gdb_thread_packet(struct connection *connection, char const *packet, int packet_size); +int rtos_thread_packet(struct connection *connection, const char *packet, int packet_size); int rtos_get_gdb_reg(struct connection *connection, int reg_num); int rtos_get_gdb_reg_list(struct connection *connection); int rtos_update_threads(struct target *target); @@ -128,4 +136,20 @@ int rtos_read_buffer(struct target *target, target_addr_t address, int rtos_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer); +// Keep in alphabetic order this list of rtos +extern const struct rtos_type chibios_rtos; +extern const struct rtos_type chromium_ec_rtos; +extern const struct rtos_type ecos_rtos; +extern const struct rtos_type embkernel_rtos; +extern const struct rtos_type freertos_rtos; +extern const struct rtos_type hwthread_rtos; +extern const struct rtos_type linux_rtos; +extern const struct rtos_type mqx_rtos; +extern const struct rtos_type nuttx_rtos; +extern const struct rtos_type riot_rtos; +extern const struct rtos_type rtkernel_rtos; +extern const struct rtos_type threadx_rtos; +extern const struct rtos_type ucos_iii_rtos; +extern const struct rtos_type zephyr_rtos; + #endif /* OPENOCD_RTOS_RTOS_H */ diff --git a/src/rtos/rtos_chibios_stackings.c b/src/rtos/rtos_chibios_stackings.c index bd17171612..c0816ac3cf 100644 --- a/src/rtos/rtos_chibios_stackings.c +++ b/src/rtos/rtos_chibios_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2012 by Matthias Blaicher * @@ -14,6 +14,7 @@ #include "rtos.h" #include "target/armv7m.h" +#include "rtos_chibios_stackings.h" static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, -1, 32 }, /* r0 */ @@ -32,7 +33,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARM { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, -1, 32 }, /* lr */ { ARMV7M_PC, 0x20, 32 }, /* pc */ - { ARMV7M_xPSR, -1, 32 }, /* xPSR */ + { ARMV7M_XPSR, -1, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = { @@ -59,7 +60,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_f { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, -1, 32 }, /* lr */ { ARMV7M_PC, 0x60, 32 }, /* pc */ - { ARMV7M_xPSR, -1, 32 }, /* xPSR */ + { ARMV7M_XPSR, -1, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = { diff --git a/src/rtos/rtos_chibios_stackings.h b/src/rtos/rtos_chibios_stackings.h index 23ad44ae3b..e909451e25 100644 --- a/src/rtos/rtos_chibios_stackings.h +++ b/src/rtos/rtos_chibios_stackings.h @@ -8,10 +8,6 @@ #ifndef OPENOCD_RTOS_RTOS_CHIBIOS_STACKINGS_H #define OPENOCD_RTOS_RTOS_CHIBIOS_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking; diff --git a/src/rtos/rtos_ecos_stackings.c b/src/rtos/rtos_ecos_stackings.c index f5c08fe736..cae271270a 100644 --- a/src/rtos/rtos_ecos_stackings.c +++ b/src/rtos/rtos_ecos_stackings.c @@ -1,13 +1,21 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "rtos.h" -#include "rtos_standard_stackings.h" #include "target/armv7m.h" +#include "rtos_standard_stackings.h" +#include "rtos_ecos_stackings.h" + +/* For Cortex-M eCos applications the actual thread context register layout can + * be different between active threads of an application depending on whether + * the FPU is in use, configured for lazy FPU context saving, etc. */ +/* Default fixed thread register context description used for older eCos + * application builds without the necessary symbolic information describing the + * actual configuration-dependent offsets. */ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x0c, 32 }, /* r0 */ { ARMV7M_R1, 0x10, 32 }, /* r1 */ @@ -25,7 +33,7 @@ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, -1, 32 }, /* lr */ { ARMV7M_PC, 0x40, 32 }, /* pc */ - { ARMV7M_xPSR, -1, 32 }, /* xPSR */ + { ARMV7M_XPSR, -1, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = { diff --git a/src/rtos/rtos_ecos_stackings.h b/src/rtos/rtos_ecos_stackings.h index 0375e2d1c5..a6bcf1acbb 100644 --- a/src/rtos/rtos_ecos_stackings.h +++ b/src/rtos/rtos_ecos_stackings.h @@ -3,10 +3,6 @@ #ifndef OPENOCD_RTOS_RTOS_ECOS_STACKINGS_H #define OPENOCD_RTOS_RTOS_ECOS_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking; diff --git a/src/rtos/rtos_embkernel_stackings.c b/src/rtos/rtos_embkernel_stackings.c index 46e13bc2fc..b98628a136 100644 --- a/src/rtos/rtos_embkernel_stackings.c +++ b/src/rtos/rtos_embkernel_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -12,6 +12,7 @@ #include "rtos.h" #include "target/armv7m.h" #include "rtos_standard_stackings.h" +#include "rtos_embkernel_stackings.h" static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x24, 32 }, /* r0 */ @@ -30,7 +31,7 @@ static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[ { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x38, 32 }, /* lr */ { ARMV7M_PC, 0x3c, 32 }, /* pc */ - { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = { diff --git a/src/rtos/rtos_embkernel_stackings.h b/src/rtos/rtos_embkernel_stackings.h index 972bce66d9..87bd0e73b8 100644 --- a/src/rtos/rtos_embkernel_stackings.h +++ b/src/rtos/rtos_embkernel_stackings.h @@ -8,10 +8,6 @@ #ifndef OPENOCD_RTOS_RTOS_EMBKERNEL_STACKINGS_H #define OPENOCD_RTOS_RTOS_EMBKERNEL_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking; diff --git a/src/rtos/rtos_mqx_stackings.c b/src/rtos/rtos_mqx_stackings.c index 90a2e0161a..5ab743bf30 100644 --- a/src/rtos/rtos_mqx_stackings.c +++ b/src/rtos/rtos_mqx_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2014 by Marian Cingel * @@ -11,7 +11,7 @@ #include "rtos.h" #include "target/armv7m.h" - +#include "rtos_mqx_stackings.h" /* * standard exception stack @@ -56,7 +56,7 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_ { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x28, 32 }, /* lr */ { ARMV7M_PC, 0x44, 32 }, /* pc */ - { ARMV7M_xPSR, 0x48, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x48, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = { diff --git a/src/rtos/rtos_mqx_stackings.h b/src/rtos/rtos_mqx_stackings.h index f86c05a40d..faa741de60 100644 --- a/src/rtos/rtos_mqx_stackings.h +++ b/src/rtos/rtos_mqx_stackings.h @@ -8,10 +8,6 @@ #ifndef OPENOCD_RTOS_RTOS_MQX_STACKINGS_H #define OPENOCD_RTOS_RTOS_MQX_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking; diff --git a/src/rtos/rtos_nuttx_stackings.c b/src/rtos/rtos_nuttx_stackings.c new file mode 100644 index 0000000000..6faa56a668 --- /dev/null +++ b/src/rtos/rtos_nuttx_stackings.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "rtos.h" +#include "target/armv7m.h" +#include "rtos_nuttx_stackings.h" +#include "rtos_standard_stackings.h" +#include <target/riscv/riscv.h> +#include <helper/bits.h> + +/* The cortex_m target uses nuttx_tcbinfo_stack_read which uses a symbol + * provided by Nuttx to read the registers from memory and place them directly + * in the order we need. This is because the register offsets change with + * different versions of Nuttx, FPU vs non-FPU and ARMv7 vs ARMv8. + * This allows a single function to work with many versions. + */ +static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = { + { ARMV7M_R0, 0, 32 }, /* r0 */ + { ARMV7M_R1, 4, 32 }, /* r1 */ + { ARMV7M_R2, 8, 32 }, /* r2 */ + { ARMV7M_R3, 12, 32 }, /* r3 */ + { ARMV7M_R4, 16, 32 }, /* r4 */ + { ARMV7M_R5, 20, 32 }, /* r5 */ + { ARMV7M_R6, 24, 32 }, /* r6 */ + { ARMV7M_R7, 28, 32 }, /* r7 */ + { ARMV7M_R8, 32, 32 }, /* r8 */ + { ARMV7M_R9, 36, 32 }, /* r9 */ + { ARMV7M_R10, 40, 32 }, /* r10 */ + { ARMV7M_R11, 44, 32 }, /* r11 */ + { ARMV7M_R12, 48, 32 }, /* r12 */ + { ARMV7M_R13, 52, 32 }, /* sp */ + { ARMV7M_R14, 56, 32 }, /* lr */ + { ARMV7M_PC, 60, 32 }, /* pc */ + { ARMV7M_XPSR, 64, 32 }, /* xPSR */ +}; + +/* The Nuttx stack frame for most architectures has some registers placed + * by hardware and some by software. The hardware register order and number does not change + * but the software registers may change with different versions of Nuttx. + * For example with ARMv7, nuttx-12.3.0 added a new register which changed all + * the offsets. We can either create separate offset tables for each version of Nuttx + * which will break again in the future, or read the offsets from the TCB info. + * Nuttx provides a symbol (g_reg_offs) which holds all the offsets for each stored register. + * This offset table is stored in GDB org.gnu.gdb.xxx feature order. + * The same order we need. + * Please refer: + * https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Features.html + * https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html + */ +static int nuttx_cortex_m_tcbinfo_stack_read(struct target *target, + int64_t stack_ptr, const struct rtos_register_stacking *stacking, + uint8_t *stack_data) +{ + struct rtos *rtos = target->rtos; + target_addr_t xcpreg_off = rtos->symbols[NX_SYM_REG_OFFSETS].address; + + for (int i = 0; i < stacking->num_output_registers; ++i) { + uint16_t stack_reg_offset; + int ret = target_read_u16(rtos->target, xcpreg_off + 2 * i, &stack_reg_offset); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read stack_reg_offset: ret = %d", ret); + return ret; + } + if (stack_reg_offset != UINT16_MAX && stacking->register_offsets[i].offset >= 0) { + ret = target_read_buffer(target, + stack_ptr + stack_reg_offset, + stacking->register_offsets[i].width_bits / 8, + &stack_data[stacking->register_offsets[i].offset]); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to read register: ret = %d", ret); + return ret; + } + } + } + + /* Offset match nuttx_stack_offsets_cortex_m */ + const int XPSR_OFFSET = 64; + const int SP_OFFSET = 52; + /* Nuttx stack frames (produced in exception_common) store the SP of the ISR minus + * the hardware stack frame size. This SP may include an additional 4 byte alignment + * depending in xPSR[9]. The Nuttx stack frame stores post alignment since the + * hardware will add/remove automatically on both enter/exit. + * We need to adjust the SP to get the real SP of the stack. + * See Arm Reference manual "Stack alignment on exception entry" + */ + uint32_t xpsr = target_buffer_get_u32(target, &stack_data[XPSR_OFFSET]); + if (xpsr & BIT(9)) { + uint32_t sp = target_buffer_get_u32(target, &stack_data[SP_OFFSET]); + target_buffer_set_u32(target, &stack_data[SP_OFFSET], sp - 4 * stacking->stack_growth_direction); + } + + return ERROR_OK; +} + +const struct rtos_register_stacking nuttx_stacking_cortex_m = { + /* nuttx_tcbinfo_stack_read transforms the stack into just output registers */ + .stack_registers_size = ARRAY_SIZE(nuttx_stack_offsets_cortex_m) * 4, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(nuttx_stack_offsets_cortex_m), + .read_stack = nuttx_cortex_m_tcbinfo_stack_read, + .calculate_process_stack = NULL, /* Stack alignment done in nuttx_cortex_m_tcbinfo_stack_read */ + .register_offsets = nuttx_stack_offsets_cortex_m, +}; + +static const struct stack_register_offset nuttx_stack_offsets_riscv[] = { + { GDB_REGNO_ZERO, -1, 32 }, + { GDB_REGNO_RA, 0x04, 32 }, + { GDB_REGNO_SP, 0x08, 32 }, + { GDB_REGNO_GP, 0x0c, 32 }, + { GDB_REGNO_TP, 0x10, 32 }, + { GDB_REGNO_T0, 0x14, 32 }, + { GDB_REGNO_T1, 0x18, 32 }, + { GDB_REGNO_T2, 0x1c, 32 }, + { GDB_REGNO_FP, 0x20, 32 }, + { GDB_REGNO_S1, 0x24, 32 }, + { GDB_REGNO_A0, 0x28, 32 }, + { GDB_REGNO_A1, 0x2c, 32 }, + { GDB_REGNO_A2, 0x30, 32 }, + { GDB_REGNO_A3, 0x34, 32 }, + { GDB_REGNO_A4, 0x38, 32 }, + { GDB_REGNO_A5, 0x3c, 32 }, + { GDB_REGNO_A6, 0x40, 32 }, + { GDB_REGNO_A7, 0x44, 32 }, + { GDB_REGNO_S2, 0x48, 32 }, + { GDB_REGNO_S3, 0x4c, 32 }, + { GDB_REGNO_S4, 0x50, 32 }, + { GDB_REGNO_S5, 0x54, 32 }, + { GDB_REGNO_S6, 0x58, 32 }, + { GDB_REGNO_S7, 0x5c, 32 }, + { GDB_REGNO_S8, 0x60, 32 }, + { GDB_REGNO_S9, 0x64, 32 }, + { GDB_REGNO_S10, 0x68, 32 }, + { GDB_REGNO_S11, 0x6c, 32 }, + { GDB_REGNO_T3, 0x70, 32 }, + { GDB_REGNO_T4, 0x74, 32 }, + { GDB_REGNO_T5, 0x78, 32 }, + { GDB_REGNO_T6, 0x7c, 32 }, + { GDB_REGNO_PC, 0x00, 32 }, +}; + +const struct rtos_register_stacking nuttx_riscv_stacking = { + .stack_registers_size = 33 * 4, + .stack_growth_direction = -1, + .num_output_registers = 33, + .calculate_process_stack = rtos_generic_stack_align8, + .register_offsets = nuttx_stack_offsets_riscv, +}; + +static int nuttx_esp_xtensa_stack_read(struct target *target, + int64_t stack_ptr, const struct rtos_register_stacking *stacking, + uint8_t *stack_data) +{ + int retval = target_read_buffer(target, stack_ptr, stacking->stack_registers_size, stack_data); + if (retval != ERROR_OK) + return retval; + + stack_data[4] &= ~0x10; /* Clear exception bit in PS */ + + return ERROR_OK; +} + +static const struct stack_register_offset nuttx_stack_offsets_esp32[] = { + { 0, 0x00, 32 }, /* PC */ + { 1, 0x08, 32 }, /* A0 */ + { 2, 0x0c, 32 }, /* A1 */ + { 3, 0x10, 32 }, /* A2 */ + { 4, 0x14, 32 }, /* A3 */ + { 5, 0x18, 32 }, /* A4 */ + { 6, 0x1c, 32 }, /* A5 */ + { 7, 0x20, 32 }, /* A6 */ + { 8, 0x24, 32 }, /* A7 */ + { 9, 0x28, 32 }, /* A8 */ + { 10, 0x2c, 32 }, /* A9 */ + { 11, 0x30, 32 }, /* A10 */ + { 12, 0x34, 32 }, /* A11 */ + { 13, 0x38, 32 }, /* A12 */ + { 14, 0x3c, 32 }, /* A13 */ + { 15, 0x40, 32 }, /* A14 */ + { 16, 0x44, 32 }, /* A15 */ + /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */ + { 17, -1, 32 }, /* A16 */ + { 18, -1, 32 }, /* A17 */ + { 19, -1, 32 }, /* A18 */ + { 20, -1, 32 }, /* A19 */ + { 21, -1, 32 }, /* A20 */ + { 22, -1, 32 }, /* A21 */ + { 23, -1, 32 }, /* A22 */ + { 24, -1, 32 }, /* A23 */ + { 25, -1, 32 }, /* A24 */ + { 26, -1, 32 }, /* A25 */ + { 27, -1, 32 }, /* A26 */ + { 28, -1, 32 }, /* A27 */ + { 29, -1, 32 }, /* A28 */ + { 30, -1, 32 }, /* A29 */ + { 31, -1, 32 }, /* A30 */ + { 32, -1, 32 }, /* A31 */ + { 33, -1, 32 }, /* A32 */ + { 34, -1, 32 }, /* A33 */ + { 35, -1, 32 }, /* A34 */ + { 36, -1, 32 }, /* A35 */ + { 37, -1, 32 }, /* A36 */ + { 38, -1, 32 }, /* A37 */ + { 39, -1, 32 }, /* A38 */ + { 40, -1, 32 }, /* A39 */ + { 41, -1, 32 }, /* A40 */ + { 42, -1, 32 }, /* A41 */ + { 43, -1, 32 }, /* A42 */ + { 44, -1, 32 }, /* A43 */ + { 45, -1, 32 }, /* A44 */ + { 46, -1, 32 }, /* A45 */ + { 47, -1, 32 }, /* A46 */ + { 48, -1, 32 }, /* A47 */ + { 49, -1, 32 }, /* A48 */ + { 50, -1, 32 }, /* A49 */ + { 51, -1, 32 }, /* A50 */ + { 52, -1, 32 }, /* A51 */ + { 53, -1, 32 }, /* A52 */ + { 54, -1, 32 }, /* A53 */ + { 55, -1, 32 }, /* A54 */ + { 56, -1, 32 }, /* A55 */ + { 57, -1, 32 }, /* A56 */ + { 58, -1, 32 }, /* A57 */ + { 59, -1, 32 }, /* A58 */ + { 60, -1, 32 }, /* A59 */ + { 61, -1, 32 }, /* A60 */ + { 62, -1, 32 }, /* A61 */ + { 63, -1, 32 }, /* A62 */ + { 64, -1, 32 }, /* A63 */ + { 65, 0x58, 32 }, /* lbeg */ + { 66, 0x5c, 32 }, /* lend */ + { 67, 0x60, 32 }, /* lcount */ + { 68, 0x48, 32 }, /* SAR */ + { 69, -1, 32 }, /* windowbase */ + { 70, -1, 32 }, /* windowstart */ + { 71, -1, 32 }, /* configid0 */ + { 72, -1, 32 }, /* configid1 */ + { 73, 0x04, 32 }, /* PS */ + { 74, -1, 32 }, /* threadptr */ + { 75, -1, 32 }, /* br */ + { 76, 0x54, 32 }, /* scompare1 */ + { 77, -1, 32 }, /* acclo */ + { 78, -1, 32 }, /* acchi */ + { 79, -1, 32 }, /* m0 */ + { 80, -1, 32 }, /* m1 */ + { 81, -1, 32 }, /* m2 */ + { 82, -1, 32 }, /* m3 */ + { 83, -1, 32 }, /* expstate */ + { 84, -1, 32 }, /* f64r_lo */ + { 85, -1, 32 }, /* f64r_hi */ + { 86, -1, 32 }, /* f64s */ + { 87, -1, 32 }, /* f0 */ + { 88, -1, 32 }, /* f1 */ + { 89, -1, 32 }, /* f2 */ + { 90, -1, 32 }, /* f3 */ + { 91, -1, 32 }, /* f4 */ + { 92, -1, 32 }, /* f5 */ + { 93, -1, 32 }, /* f6 */ + { 94, -1, 32 }, /* f7 */ + { 95, -1, 32 }, /* f8 */ + { 96, -1, 32 }, /* f9 */ + { 97, -1, 32 }, /* f10 */ + { 98, -1, 32 }, /* f11 */ + { 99, -1, 32 }, /* f12 */ + { 100, -1, 32 }, /* f13 */ + { 101, -1, 32 }, /* f14 */ + { 102, -1, 32 }, /* f15 */ + { 103, -1, 32 }, /* fcr */ + { 104, -1, 32 }, /* fsr */ +}; + +const struct rtos_register_stacking nuttx_esp32_stacking = { + .stack_registers_size = 26 * 4, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(nuttx_stack_offsets_esp32), + .calculate_process_stack = rtos_generic_stack_align8, + .register_offsets = nuttx_stack_offsets_esp32, + .read_stack = nuttx_esp_xtensa_stack_read, +}; + +static const struct stack_register_offset nuttx_stack_offsets_esp32s2[] = { + { 0, 0x00, 32 }, /* PC */ + { 1, 0x08, 32 }, /* A0 */ + { 2, 0x0c, 32 }, /* A1 */ + { 3, 0x10, 32 }, /* A2 */ + { 4, 0x14, 32 }, /* A3 */ + { 5, 0x18, 32 }, /* A4 */ + { 6, 0x1c, 32 }, /* A5 */ + { 7, 0x20, 32 }, /* A6 */ + { 8, 0x24, 32 }, /* A7 */ + { 9, 0x28, 32 }, /* A8 */ + { 10, 0x2c, 32 }, /* A9 */ + { 11, 0x30, 32 }, /* A10 */ + { 12, 0x34, 32 }, /* A11 */ + { 13, 0x38, 32 }, /* A12 */ + { 14, 0x3c, 32 }, /* A13 */ + { 15, 0x40, 32 }, /* A14 */ + { 16, 0x44, 32 }, /* A15 */ + /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */ + { 17, -1, 32 }, /* A16 */ + { 18, -1, 32 }, /* A17 */ + { 19, -1, 32 }, /* A18 */ + { 20, -1, 32 }, /* A19 */ + { 21, -1, 32 }, /* A20 */ + { 22, -1, 32 }, /* A21 */ + { 23, -1, 32 }, /* A22 */ + { 24, -1, 32 }, /* A23 */ + { 25, -1, 32 }, /* A24 */ + { 26, -1, 32 }, /* A25 */ + { 27, -1, 32 }, /* A26 */ + { 28, -1, 32 }, /* A27 */ + { 29, -1, 32 }, /* A28 */ + { 30, -1, 32 }, /* A29 */ + { 31, -1, 32 }, /* A30 */ + { 32, -1, 32 }, /* A31 */ + { 33, -1, 32 }, /* A32 */ + { 34, -1, 32 }, /* A33 */ + { 35, -1, 32 }, /* A34 */ + { 36, -1, 32 }, /* A35 */ + { 37, -1, 32 }, /* A36 */ + { 38, -1, 32 }, /* A37 */ + { 39, -1, 32 }, /* A38 */ + { 40, -1, 32 }, /* A39 */ + { 41, -1, 32 }, /* A40 */ + { 42, -1, 32 }, /* A41 */ + { 43, -1, 32 }, /* A42 */ + { 44, -1, 32 }, /* A43 */ + { 45, -1, 32 }, /* A44 */ + { 46, -1, 32 }, /* A45 */ + { 47, -1, 32 }, /* A46 */ + { 48, -1, 32 }, /* A47 */ + { 49, -1, 32 }, /* A48 */ + { 50, -1, 32 }, /* A49 */ + { 51, -1, 32 }, /* A50 */ + { 52, -1, 32 }, /* A51 */ + { 53, -1, 32 }, /* A52 */ + { 54, -1, 32 }, /* A53 */ + { 55, -1, 32 }, /* A54 */ + { 56, -1, 32 }, /* A55 */ + { 57, -1, 32 }, /* A56 */ + { 58, -1, 32 }, /* A57 */ + { 59, -1, 32 }, /* A58 */ + { 60, -1, 32 }, /* A59 */ + { 61, -1, 32 }, /* A60 */ + { 62, -1, 32 }, /* A61 */ + { 63, -1, 32 }, /* A62 */ + { 64, -1, 32 }, /* A63 */ + { 65, 0x48, 32 }, /* SAR */ + { 66, -1, 32 }, /* windowbase */ + { 67, -1, 32 }, /* windowstart */ + { 68, -1, 32 }, /* configid0 */ + { 69, -1, 32 }, /* configid1 */ + { 70, 0x04, 32 }, /* PS */ + { 71, -1, 32 }, /* threadptr */ + { 72, -1, 32 }, /* gpio_out */ +}; + +const struct rtos_register_stacking nuttx_esp32s2_stacking = { + .stack_registers_size = 25 * 4, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(nuttx_stack_offsets_esp32s2), + .calculate_process_stack = rtos_generic_stack_align8, + .register_offsets = nuttx_stack_offsets_esp32s2, + .read_stack = nuttx_esp_xtensa_stack_read, +}; + +static const struct stack_register_offset nuttx_stack_offsets_esp32s3[] = { + { 0, 0x00, 32 }, /* PC */ + { 1, 0x08, 32 }, /* A0 */ + { 2, 0x0c, 32 }, /* A1 */ + { 3, 0x10, 32 }, /* A2 */ + { 4, 0x14, 32 }, /* A3 */ + { 5, 0x18, 32 }, /* A4 */ + { 6, 0x1c, 32 }, /* A5 */ + { 7, 0x20, 32 }, /* A6 */ + { 8, 0x24, 32 }, /* A7 */ + { 9, 0x28, 32 }, /* A8 */ + { 10, 0x2c, 32 }, /* A9 */ + { 11, 0x30, 32 }, /* A10 */ + { 12, 0x34, 32 }, /* A11 */ + { 13, 0x38, 32 }, /* A12 */ + { 14, 0x3c, 32 }, /* A13 */ + { 15, 0x40, 32 }, /* A14 */ + { 16, 0x44, 32 }, /* A15 */ + /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */ + { 17, -1, 32 }, /* A16 */ + { 18, -1, 32 }, /* A17 */ + { 19, -1, 32 }, /* A18 */ + { 20, -1, 32 }, /* A19 */ + { 21, -1, 32 }, /* A20 */ + { 22, -1, 32 }, /* A21 */ + { 23, -1, 32 }, /* A22 */ + { 24, -1, 32 }, /* A23 */ + { 25, -1, 32 }, /* A24 */ + { 26, -1, 32 }, /* A25 */ + { 27, -1, 32 }, /* A26 */ + { 28, -1, 32 }, /* A27 */ + { 29, -1, 32 }, /* A28 */ + { 30, -1, 32 }, /* A29 */ + { 31, -1, 32 }, /* A30 */ + { 32, -1, 32 }, /* A31 */ + { 33, -1, 32 }, /* A32 */ + { 34, -1, 32 }, /* A33 */ + { 35, -1, 32 }, /* A34 */ + { 36, -1, 32 }, /* A35 */ + { 37, -1, 32 }, /* A36 */ + { 38, -1, 32 }, /* A37 */ + { 39, -1, 32 }, /* A38 */ + { 40, -1, 32 }, /* A39 */ + { 41, -1, 32 }, /* A40 */ + { 42, -1, 32 }, /* A41 */ + { 43, -1, 32 }, /* A42 */ + { 44, -1, 32 }, /* A43 */ + { 45, -1, 32 }, /* A44 */ + { 46, -1, 32 }, /* A45 */ + { 47, -1, 32 }, /* A46 */ + { 48, -1, 32 }, /* A47 */ + { 49, -1, 32 }, /* A48 */ + { 50, -1, 32 }, /* A49 */ + { 51, -1, 32 }, /* A50 */ + { 52, -1, 32 }, /* A51 */ + { 53, -1, 32 }, /* A52 */ + { 54, -1, 32 }, /* A53 */ + { 55, -1, 32 }, /* A54 */ + { 56, -1, 32 }, /* A55 */ + { 57, -1, 32 }, /* A56 */ + { 58, -1, 32 }, /* A57 */ + { 59, -1, 32 }, /* A58 */ + { 60, -1, 32 }, /* A59 */ + { 61, -1, 32 }, /* A60 */ + { 62, -1, 32 }, /* A61 */ + { 63, -1, 32 }, /* A62 */ + { 64, -1, 32 }, /* A63 */ + { 65, 0x58, 32 }, /* lbeg */ + { 66, 0x5c, 32 }, /* lend */ + { 67, 0x60, 32 }, /* lcount */ + { 68, 0x48, 32 }, /* SAR */ + { 69, -1, 32 }, /* windowbase */ + { 70, -1, 32 }, /* windowstart */ + { 71, -1, 32 }, /* configid0 */ + { 72, -1, 32 }, /* configid1 */ + { 73, 0x04, 32 }, /* PS */ + { 74, -1, 32 }, /* threadptr */ + { 75, -1, 32 }, /* br */ + { 76, 0x54, 32 }, /* scompare1 */ + { 77, -1, 32 }, /* acclo */ + { 78, -1, 32 }, /* acchi */ + { 79, -1, 32 }, /* m0 */ + { 80, -1, 32 }, /* m1 */ + { 81, -1, 32 }, /* m2 */ + { 82, -1, 32 }, /* m3 */ + { 83, -1, 32 }, /* gpio_out */ + { 84, -1, 32 }, /* f0 */ + { 85, -1, 32 }, /* f1 */ + { 86, -1, 32 }, /* f2 */ + { 87, -1, 32 }, /* f3 */ + { 88, -1, 32 }, /* f4 */ + { 89, -1, 32 }, /* f5 */ + { 90, -1, 32 }, /* f6 */ + { 91, -1, 32 }, /* f7 */ + { 92, -1, 32 }, /* f8 */ + { 93, -1, 32 }, /* f9 */ + { 94, -1, 32 }, /* f10 */ + { 95, -1, 32 }, /* f11 */ + { 96, -1, 32 }, /* f12 */ + { 97, -1, 32 }, /* f13 */ + { 98, -1, 32 }, /* f14 */ + { 99, -1, 32 }, /* f15 */ + { 100, -1, 32 }, /* fcr */ + { 101, -1, 32 }, /* fsr */ + { 102, -1, 32 }, /* accx_0 */ + { 103, -1, 32 }, /* accx_1 */ + { 104, -1, 32 }, /* qacc_h_0 */ + { 105, -1, 32 }, /* qacc_h_1 */ + { 106, -1, 32 }, /* qacc_h_2 */ + { 107, -1, 32 }, /* qacc_h_3 */ + { 108, -1, 32 }, /* qacc_h_4 */ + { 109, -1, 32 }, /* qacc_l_0 */ + { 110, -1, 32 }, /* qacc_l_1 */ + { 111, -1, 32 }, /* qacc_l_2 */ + { 112, -1, 32 }, /* qacc_l_3 */ + { 113, -1, 32 }, /* qacc_l_4 */ + { 114, -1, 32 }, /* sar_byte */ + { 115, -1, 32 }, /* fft_bit_width */ + { 116, -1, 32 }, /* ua_state_0 */ + { 117, -1, 32 }, /* ua_state_1 */ + { 118, -1, 32 }, /* ua_state_2 */ + { 119, -1, 32 }, /* ua_state_3 */ + { 120, -1, 128 }, /* q0 */ + { 121, -1, 128 }, /* q1 */ + { 122, -1, 128 }, /* q2 */ + { 123, -1, 128 }, /* q3 */ + { 124, -1, 128 }, /* q4 */ + { 125, -1, 128 }, /* q5 */ + { 126, -1, 128 }, /* q6 */ + { 127, -1, 128 }, /* q7 */ +}; + +const struct rtos_register_stacking nuttx_esp32s3_stacking = { + .stack_registers_size = 26 * 4, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(nuttx_stack_offsets_esp32s3), + .calculate_process_stack = rtos_generic_stack_align8, + .register_offsets = nuttx_stack_offsets_esp32s3, + .read_stack = nuttx_esp_xtensa_stack_read, +}; diff --git a/src/rtos/rtos_nuttx_stackings.h b/src/rtos/rtos_nuttx_stackings.h new file mode 100644 index 0000000000..5d55e75458 --- /dev/null +++ b/src/rtos/rtos_nuttx_stackings.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef INCLUDED_RTOS_NUTTX_STACKINGS_H +#define INCLUDED_RTOS_NUTTX_STACKINGS_H + +#include "rtos.h" + +/* Used to index the list of retrieved symbols. See nuttx_symbol_list for the order. */ +enum nuttx_symbol_vals { + NX_SYM_READYTORUN = 0, + NX_SYM_PIDHASH, + NX_SYM_NPIDHASH, + NX_SYM_TCB_INFO, + NX_SYM_REG_OFFSETS, +}; + +extern const struct rtos_register_stacking nuttx_stacking_cortex_m; +extern const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu; +extern const struct rtos_register_stacking nuttx_riscv_stacking; +extern const struct rtos_register_stacking nuttx_esp32_stacking; +extern const struct rtos_register_stacking nuttx_esp32s2_stacking; +extern const struct rtos_register_stacking nuttx_esp32s3_stacking; + +#endif /* INCLUDED_RTOS_NUTTX_STACKINGS_H */ diff --git a/src/rtos/rtos_riot_stackings.c b/src/rtos/rtos_riot_stackings.c index 30eecd6b77..e467621684 100644 --- a/src/rtos/rtos_riot_stackings.c +++ b/src/rtos/rtos_riot_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Daniel Krebs * @@ -12,6 +12,7 @@ #include "rtos.h" #include "target/armv7m.h" #include "rtos_standard_stackings.h" +#include "rtos_riot_stackings.h" /* This works for the M0 and M34 stackings as xPSR is in a fixed * location @@ -43,7 +44,7 @@ static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x38, 32 }, /* lr */ { ARMV7M_PC, 0x3c, 32 }, /* pc */ - { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = { @@ -72,7 +73,7 @@ static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARM { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x38, 32 }, /* lr */ { ARMV7M_PC, 0x3c, 32 }, /* pc */ - { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */ }; const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = { diff --git a/src/rtos/rtos_riot_stackings.h b/src/rtos/rtos_riot_stackings.h index 3b6c5f41c0..ebd5337568 100644 --- a/src/rtos/rtos_riot_stackings.h +++ b/src/rtos/rtos_riot_stackings.h @@ -8,14 +8,9 @@ #ifndef OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H #define OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_riot_cortex_m0_stacking; extern const struct rtos_register_stacking rtos_riot_cortex_m34_stacking; #endif /* OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H */ - diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index ebdc64c2a0..99cd1540f0 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -11,6 +11,7 @@ #include "rtos.h" #include "target/armv7m.h" +#include "rtos_standard_stackings.h" static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x20, 32 }, /* r0 */ @@ -29,7 +30,7 @@ static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x34, 32 }, /* lr */ { ARMV7M_PC, 0x38, 32 }, /* pc */ - { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */ }; static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = { @@ -49,7 +50,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x38, 32 }, /* lr */ { ARMV7M_PC, 0x3c, 32 }, /* pc */ - { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */ }; static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = { @@ -69,7 +70,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_off { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x78, 32 }, /* lr */ { ARMV7M_PC, 0x7c, 32 }, /* pc */ - { ARMV7M_xPSR, 0x80, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x80, 32 }, /* xPSR */ }; @@ -102,45 +103,6 @@ static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets[ { 26, 0x04, 32 }, /* CSPR */ }; -static const struct stack_register_offset rtos_standard_nds32_n1068_stack_offsets[] = { - { 0, 0x88, 32 }, /* R0 */ - { 1, 0x8C, 32 }, /* R1 */ - { 2, 0x14, 32 }, /* R2 */ - { 3, 0x18, 32 }, /* R3 */ - { 4, 0x1C, 32 }, /* R4 */ - { 5, 0x20, 32 }, /* R5 */ - { 6, 0x24, 32 }, /* R6 */ - { 7, 0x28, 32 }, /* R7 */ - { 8, 0x2C, 32 }, /* R8 */ - { 9, 0x30, 32 }, /* R9 */ - { 10, 0x34, 32 }, /* R10 */ - { 11, 0x38, 32 }, /* R11 */ - { 12, 0x3C, 32 }, /* R12 */ - { 13, 0x40, 32 }, /* R13 */ - { 14, 0x44, 32 }, /* R14 */ - { 15, 0x48, 32 }, /* R15 */ - { 16, 0x4C, 32 }, /* R16 */ - { 17, 0x50, 32 }, /* R17 */ - { 18, 0x54, 32 }, /* R18 */ - { 19, 0x58, 32 }, /* R19 */ - { 20, 0x5C, 32 }, /* R20 */ - { 21, 0x60, 32 }, /* R21 */ - { 22, 0x64, 32 }, /* R22 */ - { 23, 0x68, 32 }, /* R23 */ - { 24, 0x6C, 32 }, /* R24 */ - { 25, 0x70, 32 }, /* R25 */ - { 26, 0x74, 32 }, /* R26 */ - { 27, 0x78, 32 }, /* R27 */ - { 28, 0x7C, 32 }, /* R28 */ - { 29, 0x80, 32 }, /* R29 */ - { 30, 0x84, 32 }, /* R30 (LP) */ - { 31, 0x00, 32 }, /* R31 (SP) */ - { 32, 0x04, 32 }, /* PSW */ - { 33, 0x08, 32 }, /* IPC */ - { 34, 0x0C, 32 }, /* IPSW */ - { 35, 0x10, 32 }, /* IFC_LP */ -}; - static target_addr_t rtos_generic_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, target_addr_t stack_ptr, int align) @@ -198,9 +160,7 @@ target_addr_t rtos_cortex_m_stack_align(struct target *target, new_stack_ptr = stack_ptr - stacking->stack_growth_direction * stacking->stack_registers_size; - xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ? - le_to_h_u32(&stack_data[xpsr_offset]) : - be_to_h_u32(&stack_data[xpsr_offset]); + xpsr = target_buffer_get_u32(target, &stack_data[xpsr_offset]); if ((xpsr & ALIGN_NEEDED) != 0) { LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n", xpsr); @@ -268,11 +228,3 @@ const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = { .calculate_process_stack = rtos_generic_stack_align8, .register_offsets = rtos_standard_cortex_r4_stack_offsets }; - -const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = { - .stack_registers_size = 0x90, - .stack_growth_direction = -1, - .num_output_registers = 32, - .calculate_process_stack = rtos_generic_stack_align8, - .register_offsets = rtos_standard_nds32_n1068_stack_offsets -}; diff --git a/src/rtos/rtos_standard_stackings.h b/src/rtos/rtos_standard_stackings.h index 83ca07f9e4..99fbe07e48 100644 --- a/src/rtos/rtos_standard_stackings.h +++ b/src/rtos/rtos_standard_stackings.h @@ -8,17 +8,12 @@ #ifndef OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H #define OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "rtos.h" extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking; extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking; extern const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking; extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking; -extern const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking; target_addr_t rtos_generic_stack_align8(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, target_addr_t stack_ptr); diff --git a/src/rtos/rtos_ucos_iii_stackings.c b/src/rtos/rtos_ucos_iii_stackings.c index 8662518209..f1e248231e 100644 --- a/src/rtos/rtos_ucos_iii_stackings.c +++ b/src/rtos/rtos_ucos_iii_stackings.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Square, Inc. * @@ -9,11 +9,11 @@ #include "config.h" #endif -#include <helper/types.h> -#include <rtos/rtos.h> -#include <rtos/rtos_standard_stackings.h> -#include <target/armv7m.h> -#include <target/esirisc.h> +#include "rtos.h" +#include "target/armv7m.h" +#include "target/esirisc.h" +#include "rtos_standard_stackings.h" +#include "rtos_ucos_iii_stackings.h" static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] = { { ARMV7M_R0, 0x20, 32 }, /* r0 */ @@ -32,7 +32,7 @@ static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] { ARMV7M_R13, -2, 32 }, /* sp */ { ARMV7M_R14, 0x34, 32 }, /* lr */ { ARMV7M_PC, 0x38, 32 }, /* pc */ - { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */ + { ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */ }; static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = { diff --git a/src/rtos/rtos_ucos_iii_stackings.h b/src/rtos/rtos_ucos_iii_stackings.h index 831c68e1c9..dfe60b27b4 100644 --- a/src/rtos/rtos_ucos_iii_stackings.h +++ b/src/rtos/rtos_ucos_iii_stackings.h @@ -8,11 +8,7 @@ #ifndef OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H #define OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <rtos/rtos.h> +#include "rtos.h" extern const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking; extern const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking; diff --git a/src/rtos/ThreadX.c b/src/rtos/threadx.c similarity index 95% rename from src/rtos/ThreadX.c rename to src/rtos/threadx.c index a60d5f8bb0..620f43cc8e 100644 --- a/src/rtos/ThreadX.c +++ b/src/rtos/threadx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Broadcom Corporation * @@ -12,7 +12,6 @@ #include <helper/time_support.h> #include <jtag/jtag.h> #include "target/target.h" -#include "target/target_type.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -320,6 +319,12 @@ static int threadx_update_threads(struct rtos *rtos) rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str)); strcpy(rtos->thread_details->thread_name_str, tmp_str); + /* If we just invented thread 1 to represent the current execution, we + * need to make sure the RTOS object also claims it's the current thread + * so that threadx_get_thread_reg_list() doesn't attempt to read a + * thread control block at 0x00000001. */ + rtos->current_thread = 1; + if (thread_list_size == 0) { rtos->thread_count = 1; return ERROR_OK; @@ -364,16 +369,21 @@ static int threadx_update_threads(struct rtos *rtos) } /* Read the thread name */ - retval = - target_read_buffer(rtos->target, - name_ptr, - THREADX_THREAD_NAME_STR_SIZE, - (uint8_t *)&tmp_str); - if (retval != ERROR_OK) { - LOG_ERROR("Error reading thread name from ThreadX target"); - return retval; + tmp_str[0] = '\x00'; + + /* Check if thread has a valid name */ + if (name_ptr != 0) { + retval = + target_read_buffer(rtos->target, + name_ptr, + THREADX_THREAD_NAME_STR_SIZE, + (uint8_t *)&tmp_str); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading thread name from ThreadX target"); + return retval; + } + tmp_str[THREADX_THREAD_NAME_STR_SIZE - 1] = '\x00'; } - tmp_str[THREADX_THREAD_NAME_STR_SIZE-1] = '\x00'; if (tmp_str[0] == '\x00') strcpy(tmp_str, "No Name"); @@ -597,13 +607,13 @@ static int threadx_get_thread_detail(struct rtos *rtos, static int threadx_create(struct target *target) { for (unsigned int i = 0; i < ARRAY_SIZE(threadx_params_list); i++) - if (strcmp(threadx_params_list[i].target_name, target->type->name) == 0) { + if (strcmp(threadx_params_list[i].target_name, target_type_name(target)) == 0) { target->rtos->rtos_specific_params = (void *)&threadx_params_list[i]; target->rtos->current_thread = 0; target->rtos->thread_details = NULL; - return 0; + return ERROR_OK; } LOG_ERROR("Could not find target in ThreadX compatibility list"); - return -1; + return ERROR_FAIL; } diff --git a/src/rtos/uCOS-III.c b/src/rtos/ucos_iii.c similarity index 84% rename from src/rtos/uCOS-III.c rename to src/rtos/ucos_iii.c index 754fe064b0..f19d06e3c0 100644 --- a/src/rtos/uCOS-III.c +++ b/src/rtos/ucos_iii.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Square, Inc. * @@ -14,7 +14,6 @@ #include <helper/types.h> #include <rtos/rtos.h> #include <target/target.h> -#include <target/target_type.h> #include "rtos_ucos_iii_stackings.h" @@ -29,6 +28,12 @@ struct ucos_iii_params { const char *target_name; const unsigned char pointer_width; + size_t threadid_start; + const struct rtos_register_stacking *stacking_info; +}; + +struct ucos_iii_private { + const struct ucos_iii_params *params; symbol_address_t thread_stack_offset; symbol_address_t thread_name_offset; symbol_address_t thread_state_offset; @@ -36,40 +41,22 @@ struct ucos_iii_params { symbol_address_t thread_prev_offset; symbol_address_t thread_next_offset; bool thread_offsets_updated; - size_t threadid_start; - const struct rtos_register_stacking *stacking_info; size_t num_threads; - symbol_address_t threads[]; + symbol_address_t threads[UCOS_III_MAX_THREADS]; }; static const struct ucos_iii_params ucos_iii_params_list[] = { { - "cortex_m", /* target_name */ - sizeof(uint32_t), /* pointer_width */ - 0, /* thread_stack_offset */ - 0, /* thread_name_offset */ - 0, /* thread_state_offset */ - 0, /* thread_priority_offset */ - 0, /* thread_prev_offset */ - 0, /* thread_next_offset */ - false, /* thread_offsets_updated */ - 1, /* threadid_start */ - &rtos_ucos_iii_cortex_m_stacking, /* stacking_info */ - 0, /* num_threads */ + .target_name = "cortex_m", + .pointer_width = sizeof(uint32_t), + .threadid_start = 1, + .stacking_info = &rtos_ucos_iii_cortex_m_stacking, }, { - "esirisc", /* target_name */ - sizeof(uint32_t), /* pointer_width */ - 0, /* thread_stack_offset */ - 0, /* thread_name_offset */ - 0, /* thread_state_offset */ - 0, /* thread_priority_offset */ - 0, /* thread_prev_offset */ - 0, /* thread_next_offset */ - false, /* thread_offsets_updated */ - 1, /* threadid_start */ - &rtos_ucos_iii_esi_risc_stacking, /* stacking_info */ - 0, /* num_threads */ + .target_name = "esirisc", + .pointer_width = sizeof(uint32_t), + .threadid_start = 1, + .stacking_info = &rtos_ucos_iii_esi_risc_stacking, }, }; @@ -118,7 +105,7 @@ static const char * const ucos_iii_thread_state_list[] = { static int ucos_iii_find_or_create_thread(struct rtos *rtos, symbol_address_t thread_address, threadid_t *threadid) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; size_t thread_index; for (thread_index = 0; thread_index < params->num_threads; thread_index++) @@ -133,17 +120,17 @@ static int ucos_iii_find_or_create_thread(struct rtos *rtos, symbol_address_t th params->threads[thread_index] = thread_address; params->num_threads++; found: - *threadid = thread_index + params->threadid_start; + *threadid = thread_index + params->params->threadid_start; return ERROR_OK; } static int ucos_iii_find_thread_address(struct rtos *rtos, threadid_t threadid, symbol_address_t *thread_address) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; size_t thread_index; - thread_index = threadid - params->threadid_start; + thread_index = threadid - params->params->threadid_start; if (thread_index >= params->num_threads) { LOG_ERROR("uCOS-III: failed to find thread address"); return ERROR_FAIL; @@ -155,7 +142,7 @@ static int ucos_iii_find_thread_address(struct rtos *rtos, threadid_t threadid, static int ucos_iii_find_last_thread_address(struct rtos *rtos, symbol_address_t *thread_address) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; int retval; /* read the thread list head */ @@ -163,7 +150,7 @@ static int ucos_iii_find_last_thread_address(struct rtos *rtos, symbol_address_t retval = target_read_memory(rtos->target, rtos->symbols[UCOS_III_VAL_OS_TASK_DBG_LIST_PTR].address, - params->pointer_width, + params->params->pointer_width, 1, (void *)&thread_list_address); if (retval != ERROR_OK) { @@ -177,7 +164,7 @@ static int ucos_iii_find_last_thread_address(struct rtos *rtos, symbol_address_t retval = target_read_memory(rtos->target, thread_list_address + params->thread_next_offset, - params->pointer_width, + params->params->pointer_width, 1, (void *)&thread_list_address); if (retval != ERROR_OK) { @@ -191,7 +178,7 @@ static int ucos_iii_find_last_thread_address(struct rtos *rtos, symbol_address_t static int ucos_iii_update_thread_offsets(struct rtos *rtos) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; if (params->thread_offsets_updated) return ERROR_OK; @@ -231,7 +218,7 @@ static int ucos_iii_update_thread_offsets(struct rtos *rtos) int retval = target_read_memory(rtos->target, rtos->symbols[thread_offset_map->symbol_value].address, - params->pointer_width, + params->params->pointer_width, 1, (void *)thread_offset_map->thread_offset); if (retval != ERROR_OK) { @@ -252,7 +239,7 @@ static bool ucos_iii_detect_rtos(struct target *target) static int ucos_iii_reset_handler(struct target *target, enum target_reset_mode reset_mode, void *priv) { - struct ucos_iii_params *params = target->rtos->rtos_specific_params; + struct ucos_iii_private *params = target->rtos->rtos_specific_params; params->thread_offsets_updated = false; params->num_threads = 0; @@ -262,17 +249,17 @@ static int ucos_iii_reset_handler(struct target *target, enum target_reset_mode static int ucos_iii_create(struct target *target) { - struct ucos_iii_params *params; + struct ucos_iii_private *params; for (size_t i = 0; i < ARRAY_SIZE(ucos_iii_params_list); i++) - if (strcmp(ucos_iii_params_list[i].target_name, target->type->name) == 0) { - params = malloc(sizeof(*params) + (UCOS_III_MAX_THREADS * sizeof(*params->threads))); + if (strcmp(ucos_iii_params_list[i].target_name, target_type_name(target)) == 0) { + params = calloc(1, sizeof(*params)); if (!params) { LOG_ERROR("uCOS-III: out of memory"); return ERROR_FAIL; } - memcpy(params, &ucos_iii_params_list[i], sizeof(ucos_iii_params_list[i])); + params->params = &ucos_iii_params_list[i]; target->rtos->rtos_specific_params = (void *)params; target_register_reset_callback(ucos_iii_reset_handler, NULL); @@ -280,13 +267,13 @@ static int ucos_iii_create(struct target *target) return ERROR_OK; } - LOG_ERROR("uCOS-III: target not supported: %s", target->type->name); + LOG_ERROR("uCOS-III: target not supported: %s", target_type_name(target)); return ERROR_FAIL; } static int ucos_iii_update_threads(struct rtos *rtos) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; int retval; if (!rtos->symbols) { @@ -340,7 +327,7 @@ static int ucos_iii_update_threads(struct rtos *rtos) retval = target_read_memory(rtos->target, rtos->symbols[UCOS_III_VAL_OS_TCB_CUR_PTR].address, - params->pointer_width, + params->params->pointer_width, 1, (void *)¤t_thread_address); if (retval != ERROR_OK) { @@ -396,7 +383,7 @@ static int ucos_iii_update_threads(struct rtos *rtos) retval = target_read_memory(rtos->target, thread_address + params->thread_name_offset, - params->pointer_width, + params->params->pointer_width, 1, (void *)&thread_name_address); if (retval != ERROR_OK) { @@ -450,7 +437,7 @@ static int ucos_iii_update_threads(struct rtos *rtos) /* read previous thread address */ retval = target_read_memory(rtos->target, thread_address + params->thread_prev_offset, - params->pointer_width, + params->params->pointer_width, 1, (void *)&thread_address); if (retval != ERROR_OK) { @@ -465,7 +452,7 @@ static int ucos_iii_update_threads(struct rtos *rtos) static int ucos_iii_get_thread_reg_list(struct rtos *rtos, threadid_t threadid, struct rtos_reg **reg_list, int *num_regs) { - struct ucos_iii_params *params = rtos->rtos_specific_params; + struct ucos_iii_private *params = rtos->rtos_specific_params; int retval; /* find thread address for threadid */ @@ -482,7 +469,7 @@ static int ucos_iii_get_thread_reg_list(struct rtos *rtos, threadid_t threadid, retval = target_read_memory(rtos->target, thread_address + params->thread_stack_offset, - params->pointer_width, + params->params->pointer_width, 1, (void *)&stack_address); if (retval != ERROR_OK) { @@ -491,7 +478,7 @@ static int ucos_iii_get_thread_reg_list(struct rtos *rtos, threadid_t threadid, } return rtos_generic_stack_read(rtos->target, - params->stacking_info, + params->params->stacking_info, stack_address, reg_list, num_regs); diff --git a/src/rtos/zephyr.c b/src/rtos/zephyr.c index 6276236e29..023db60c9e 100644 --- a/src/rtos/zephyr.c +++ b/src/rtos/zephyr.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2017 by Intel Corporation @@ -20,7 +20,6 @@ #include "rtos.h" #include "rtos_standard_stackings.h" #include "target/target.h" -#include "target/target_type.h" #include "target/armv7m.h" #include "target/arc.h" @@ -57,6 +56,7 @@ enum zephyr_offsets { OFFSET_T_ARCH, OFFSET_T_PREEMPT_FLOAT, OFFSET_T_COOP_FLOAT, + OFFSET_T_ARM_EXC_RETURN, OFFSET_MAX }; @@ -136,7 +136,7 @@ static const struct stack_register_offset arm_cpu_saved[] = { { ARMV7M_R13, -2, 32 }, { ARMV7M_R14, 20, 32 }, { ARMV7M_PC, 24, 32 }, - { ARMV7M_xPSR, 28, 32 }, + { ARMV7M_XPSR, 28, 32 }, }; static struct stack_register_offset arc_cpu_saved[] = { @@ -785,7 +785,7 @@ static int zephyr_get_symbol_list_to_lookup(struct symbol_table_elem **symbol_li return ERROR_OK; } -struct rtos_type zephyr_rtos = { +const struct rtos_type zephyr_rtos = { .name = "Zephyr", .detect_rtos = zephyr_detect_rtos, diff --git a/src/rtt/rtt.c b/src/rtt/rtt.c index 7e755718f1..15b9a373a5 100644 --- a/src/rtt/rtt.c +++ b/src/rtt/rtt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016-2020 by Marc Schink <dev@zapb.de> @@ -140,8 +140,8 @@ int rtt_start(void) addr); rtt.ctrl.address = addr; } else { - LOG_INFO("rtt: No control block found"); - return ERROR_OK; + LOG_ERROR("rtt: No control block found"); + return ERROR_FAIL; } } @@ -297,11 +297,6 @@ int rtt_write_channel(unsigned int channel_index, const uint8_t *buffer, length, NULL); } -bool rtt_started(void) -{ - return rtt.started; -} - bool rtt_configured(void) { return rtt.configured; diff --git a/src/rtt/rtt.h b/src/rtt/rtt.h index a5630a9515..d84fdb40b3 100644 --- a/src/rtt/rtt.h +++ b/src/rtt/rtt.h @@ -95,35 +95,27 @@ enum rtt_channel_type { RTT_CHANNEL_TYPE_DOWN }; -typedef int (*rtt_source_find_ctrl_block)(struct target *target, +/** RTT source. */ +struct rtt_source { + int (*find_cb)(struct target *target, target_addr_t *address, size_t size, const char *id, bool *found, void *user_data); -typedef int (*rtt_source_read_ctrl_block)(struct target *target, + int (*read_cb)(struct target *target, target_addr_t address, struct rtt_control *ctrl_block, void *user_data); -typedef int (*rtt_source_read_channel_info)(struct target *target, + int (*read_channel_info)(struct target *target, const struct rtt_control *ctrl, unsigned int channel, enum rtt_channel_type type, struct rtt_channel_info *info, void *user_data); -typedef int (*rtt_source_start)(struct target *target, + int (*start)(struct target *target, const struct rtt_control *ctrl, void *user_data); -typedef int (*rtt_source_stop)(struct target *target, void *user_data); -typedef int (*rtt_source_read)(struct target *target, + int (*stop)(struct target *target, void *user_data); + int (*read)(struct target *target, const struct rtt_control *ctrl, struct rtt_sink_list **sinks, size_t num_channels, void *user_data); -typedef int (*rtt_source_write)(struct target *target, + int (*write)(struct target *target, struct rtt_control *ctrl, unsigned int channel, const uint8_t *buffer, size_t *length, void *user_data); - -/** RTT source. */ -struct rtt_source { - rtt_source_find_ctrl_block find_cb; - rtt_source_read_ctrl_block read_cb; - rtt_source_read_channel_info read_channel_info; - rtt_source_start start; - rtt_source_stop stop; - rtt_source_read read; - rtt_source_write write; }; /** @@ -194,13 +186,6 @@ int rtt_get_polling_interval(unsigned int *interval); */ int rtt_set_polling_interval(unsigned int interval); -/** - * Get whether RTT is started. - * - * @returns Whether RTT is started. - */ -bool rtt_started(void); - /** * Get whether RTT is configured. * diff --git a/src/rtt/tcl.c b/src/rtt/tcl.c index 1726d60e53..bae71b6ce5 100644 --- a/src/rtt/tcl.c +++ b/src/rtt/tcl.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2019-2020 by Marc Schink <dev@zapb.de> @@ -17,10 +17,16 @@ COMMAND_HANDLER(handle_rtt_setup_command) { -struct rtt_source source; + struct rtt_source source; - if (CMD_ARGC != 3) + const char *DEFAULT_ID = "SEGGER RTT"; + const char *selected_id; + if (CMD_ARGC < 2 || CMD_ARGC > 3) return ERROR_COMMAND_SYNTAX_ERROR; + if (CMD_ARGC == 2) + selected_id = DEFAULT_ID; + else + selected_id = CMD_ARGV[2]; source.find_cb = &target_rtt_find_control_block; source.read_cb = &target_rtt_read_control_block; @@ -38,7 +44,7 @@ struct rtt_source source; rtt_register_source(source, get_current_target(CMD_CTX)); - if (rtt_setup(address, size, CMD_ARGV[2]) != ERROR_OK) + if (rtt_setup(address, size, selected_id) != ERROR_OK) return ERROR_FAIL; return ERROR_OK; @@ -150,17 +156,17 @@ COMMAND_HANDLER(handle_rtt_channels_command) return ERROR_OK; } -static int jim_channel_list(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handle_channel_list) { - Jim_Obj *list; - Jim_Obj *channel_list; char channel_name[CHANNEL_NAME_SIZE]; const struct rtt_control *ctrl; struct rtt_channel_info info; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + if (!rtt_found_cb()) { - Jim_SetResultFormatted(interp, "rtt: Control block not available"); + command_print(CMD, "rtt: Control block not available"); return ERROR_FAIL; } @@ -169,81 +175,47 @@ static int jim_channel_list(Jim_Interp *interp, int argc, info.name = channel_name; info.name_length = sizeof(channel_name); - list = Jim_NewListObj(interp, NULL, 0); - channel_list = Jim_NewListObj(interp, NULL, 0); + command_print(CMD, "{"); for (unsigned int i = 0; i < ctrl->num_up_channels; i++) { - int ret; - Jim_Obj *tmp; - - ret = rtt_read_channel_info(i, RTT_CHANNEL_TYPE_UP, &info); - + int ret = rtt_read_channel_info(i, RTT_CHANNEL_TYPE_UP, &info); if (ret != ERROR_OK) return ret; if (!info.size) continue; - tmp = Jim_NewListObj(interp, NULL, 0); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "name", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - info.name, -1)); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "size", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewIntObj(interp, - info.size)); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "flags", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewIntObj(interp, - info.flags)); - - Jim_ListAppendElement(interp, channel_list, tmp); + command_print(CMD, + " {\n" + " name %s\n" + " size 0x%" PRIx32 "\n" + " flags 0x%" PRIx32 "\n" + " }", + info.name, info.size, info.flags); } - Jim_ListAppendElement(interp, list, channel_list); - - channel_list = Jim_NewListObj(interp, NULL, 0); + command_print(CMD, "}\n{"); for (unsigned int i = 0; i < ctrl->num_down_channels; i++) { - int ret; - Jim_Obj *tmp; - - ret = rtt_read_channel_info(i, RTT_CHANNEL_TYPE_DOWN, &info); - + int ret = rtt_read_channel_info(i, RTT_CHANNEL_TYPE_DOWN, &info); if (ret != ERROR_OK) return ret; if (!info.size) continue; - tmp = Jim_NewListObj(interp, NULL, 0); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "name", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - info.name, -1)); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "size", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewIntObj(interp, - info.size)); - - Jim_ListAppendElement(interp, tmp, Jim_NewStringObj(interp, - "flags", -1)); - Jim_ListAppendElement(interp, tmp, Jim_NewIntObj(interp, - info.flags)); - - Jim_ListAppendElement(interp, channel_list, tmp); + command_print(CMD, + " {\n" + " name %s\n" + " size 0x%" PRIx32 "\n" + " flags 0x%" PRIx32 "\n" + " }", + info.name, info.size, info.flags); } - Jim_ListAppendElement(interp, list, channel_list); - Jim_SetResult(interp, list); + command_print(CMD, "}"); - return JIM_OK; + return ERROR_OK; } static const struct command_registration rtt_subcommand_handlers[] = { @@ -252,7 +224,7 @@ static const struct command_registration rtt_subcommand_handlers[] = { .handler = handle_rtt_setup_command, .mode = COMMAND_ANY, .help = "setup RTT", - .usage = "<address> <size> <ID>" + .usage = "<address> <size> [ID]" }, { .name = "start", @@ -284,7 +256,7 @@ static const struct command_registration rtt_subcommand_handlers[] = { }, { .name = "channellist", - .jim_handler = jim_channel_list, + .handler = handle_channel_list, .mode = COMMAND_EXEC, .help = "list available channels", .usage = "" diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index 2e6c7304dd..3eba15070e 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -50,9 +50,13 @@ * found in most modern embedded processors. */ +#define CTRL(c) ((c) - '@') + enum gdb_output_flag { /* GDB doesn't accept 'O' packets */ GDB_OUTPUT_NO, + /* GDB doesn't accept 'O' packets but accepts notifications */ + GDB_OUTPUT_NOTIF, /* GDB accepts 'O' packets */ GDB_OUTPUT_ALL, }; @@ -71,6 +75,8 @@ struct gdb_connection { enum target_state frontend_state; struct image *vflash_image; bool closed; + /* set to prevent re-entrance from log messages during gdb_get_packet() + * and gdb_put_packet(). */ bool busy; int noack_mode; /* set flag to true if you want the next stepi to return immediately. @@ -95,6 +101,8 @@ struct gdb_connection { char *thread_list; /* flag to mask the output from gdb_log_callback() */ enum gdb_output_flag output_flag; + /* Unique index for this GDB connection. */ + unsigned int unique_index; }; #if 0 @@ -110,21 +118,21 @@ static int gdb_error(struct connection *connection, int retval); static char *gdb_port; static char *gdb_port_next; -static void gdb_log_callback(void *priv, const char *file, unsigned line, +static void gdb_log_callback(void *priv, const char *file, unsigned int line, const char *function, const char *string); static void gdb_sig_halted(struct connection *connection); /* number of gdb connections, mainly to suppress gdb related debugging spam * in helper/log.c when no gdb connections are actually active */ -int gdb_actual_connections; +static int gdb_actual_connections; /* set if we are sending a memory map to gdb * via qXfer:memory-map:read packet */ /* enabled by default*/ -static int gdb_use_memory_map = 1; +static bool gdb_use_memory_map = true; /* enabled by default*/ -static int gdb_flash_program = 1; +static bool gdb_flash_program = true; /* if set, data aborts cause an error to be reported in memory read packets * see the code in gdb_read_memory_packet() for further explanations. @@ -138,13 +146,39 @@ static int gdb_report_register_access_error; /* set if we are sending target descriptions to gdb * via qXfer:features:read packet */ /* enabled by default */ -static int gdb_use_target_description = 1; +static bool gdb_use_target_description = true; /* current processing free-run type, used by file-I/O */ static char gdb_running_type; +/* Find an available target in the SMP group that gdb is connected to. For + * commands that affect an entire SMP group (like memory access and run control) + * this will give better results than returning the unavailable target and having + * the command fail. If gdb was aware that targets can be unavailable we + * wouldn't need this logic. + */ +struct target *get_available_target_from_connection(struct connection *connection) +{ + struct gdb_service *gdb_service = connection->service->priv; + struct target *target = gdb_service->target; + if (target->state == TARGET_UNAVAILABLE && target->smp) { + struct target_list *tlist; + foreach_smp_target(tlist, target->smp_targets) { + struct target *t = tlist->target; + if (t->state != TARGET_UNAVAILABLE) + return t; + } + /* If we can't find an available target, just return the + * original. */ + } + return target; +} + static int gdb_last_signal(struct target *target) { + LOG_TARGET_DEBUG(target, "Debug reason is: %s", + target_debug_reason_str(target->debug_reason)); + switch (target->debug_reason) { case DBG_REASON_DBGRQ: return 0x2; /* SIGINT */ @@ -159,8 +193,9 @@ static int gdb_last_signal(struct target *target) case DBG_REASON_NOTHALTED: return 0x0; /* no signal... shouldn't happen */ default: - LOG_USER("undefined debug reason %d - target needs reset", - target->debug_reason); + LOG_USER("undefined debug reason %d (%s) - target needs reset", + target->debug_reason, + target_debug_reason_str(target->debug_reason)); return 0x0; } } @@ -231,39 +266,20 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char) } #ifdef _WIN32 - errno = WSAGetLastError(); - - switch (errno) { - case WSAEWOULDBLOCK: - usleep(1000); - break; - case WSAECONNABORTED: - gdb_con->closed = true; - return ERROR_SERVER_REMOTE_CLOSED; - case WSAECONNRESET: - gdb_con->closed = true; - return ERROR_SERVER_REMOTE_CLOSED; - default: - LOG_ERROR("read: %d", errno); - exit(-1); - } + bool retry = (WSAGetLastError() == WSAEWOULDBLOCK); #else - switch (errno) { - case EAGAIN: - usleep(1000); - break; - case ECONNABORTED: - gdb_con->closed = true; - return ERROR_SERVER_REMOTE_CLOSED; - case ECONNRESET: - gdb_con->closed = true; - return ERROR_SERVER_REMOTE_CLOSED; - default: - LOG_ERROR("read: %s", strerror(errno)); - gdb_con->closed = true; - return ERROR_SERVER_REMOTE_CLOSED; - } + bool retry = (errno == EAGAIN); #endif + + if (retry) { + // Try again after a delay + usleep(1000); + } else { + // Print error and close the socket + log_socket_error("GDB"); + gdb_con->closed = true; + return ERROR_SERVER_REMOTE_CLOSED; + } } #ifdef _DEBUG_GDB_IO_ @@ -344,7 +360,7 @@ static int gdb_putback_char(struct connection *connection, int last_char) /* The only way we can detect that the socket is closed is the first time * we write to it, we will fail. Subsequent write operations will * succeed. Shudder! */ -static int gdb_write(struct connection *connection, void *data, int len) +static int gdb_write(struct connection *connection, const void *data, int len) { struct gdb_connection *gdb_con = connection->priv; if (gdb_con->closed) { @@ -360,15 +376,16 @@ static int gdb_write(struct connection *connection, void *data, int len) return ERROR_SERVER_REMOTE_CLOSED; } -static void gdb_log_incoming_packet(struct connection *connection, char *packet) +static void gdb_log_incoming_packet(struct connection *connection, const char *packet) { if (!LOG_LEVEL_IS(LOG_LVL_DEBUG)) return; struct target *target = get_target_from_connection(connection); + struct gdb_connection *gdb_connection = connection->priv; /* Avoid dumping non-printable characters to the terminal */ - const unsigned packet_len = strlen(packet); + const unsigned int packet_len = strlen(packet); const char *nonprint = find_nonprint_char(packet, packet_len); if (nonprint) { /* Does packet at least have a prefix that is printable? @@ -380,35 +397,37 @@ static void gdb_log_incoming_packet(struct connection *connection, char *packet) if (packet_prefix_printable) { const unsigned int prefix_len = colon - packet + 1; /* + 1 to include the ':' */ const unsigned int payload_len = packet_len - prefix_len; - LOG_TARGET_DEBUG(target, "received packet: %.*s<binary-data-%u-bytes>", prefix_len, - packet, payload_len); + LOG_TARGET_DEBUG(target, "{%d} received packet: %.*s<binary-data-%u-bytes>", + gdb_connection->unique_index, prefix_len, packet, payload_len); } else { - LOG_TARGET_DEBUG(target, "received packet: <binary-data-%u-bytes>", packet_len); + LOG_TARGET_DEBUG(target, "{%d} received packet: <binary-data-%u-bytes>", + gdb_connection->unique_index, packet_len); } } else { /* All chars printable, dump the packet as is */ - LOG_TARGET_DEBUG(target, "received packet: %s", packet); + LOG_TARGET_DEBUG(target, "{%d} received packet: %s", gdb_connection->unique_index, packet); } } -static void gdb_log_outgoing_packet(struct connection *connection, char *packet_buf, +static void gdb_log_outgoing_packet(struct connection *connection, const char *packet_buf, unsigned int packet_len, unsigned char checksum) { if (!LOG_LEVEL_IS(LOG_LVL_DEBUG)) return; struct target *target = get_target_from_connection(connection); + struct gdb_connection *gdb_connection = connection->priv; if (find_nonprint_char(packet_buf, packet_len)) - LOG_TARGET_DEBUG(target, "sending packet: $<binary-data-%u-bytes>#%2.2x", - packet_len, checksum); + LOG_TARGET_DEBUG(target, "{%d} sending packet: $<binary-data-%u-bytes>#%2.2x", + gdb_connection->unique_index, packet_len, checksum); else - LOG_TARGET_DEBUG(target, "sending packet: $%.*s#%2.2x", packet_len, packet_buf, - checksum); + LOG_TARGET_DEBUG(target, "{%d} sending packet: $%.*s#%2.2x", + gdb_connection->unique_index, packet_len, packet_buf, checksum); } static int gdb_put_packet_inner(struct connection *connection, - char *buffer, int len) + const char *buffer, int len) { int i; unsigned char my_checksum = 0; @@ -440,6 +459,10 @@ static int gdb_put_packet_inner(struct connection *connection, gdb_putback_char(connection, reply); LOG_DEBUG("Unexpected start of new packet"); break; + } else if (reply == CTRL('C')) { + /* do not discard Ctrl-C */ + gdb_putback_char(connection, reply); + break; } LOG_WARNING("Discard unexpected char %c", reply); @@ -488,7 +511,7 @@ static int gdb_put_packet_inner(struct connection *connection, gdb_con->output_flag = GDB_OUTPUT_NO; gdb_log_incoming_packet(connection, "-"); LOG_WARNING("negative reply, retrying"); - } else if (reply == 0x3) { + } else if (reply == CTRL('C')) { gdb_con->ctrl_c = true; gdb_log_incoming_packet(connection, "<Ctrl-C>"); retval = gdb_get_char(connection, &reply); @@ -528,7 +551,7 @@ static int gdb_put_packet_inner(struct connection *connection, return ERROR_OK; } -int gdb_put_packet(struct connection *connection, char *buffer, int len) +int gdb_put_packet(struct connection *connection, const char *buffer, int len) { struct gdb_connection *gdb_con = connection->priv; gdb_con->busy = true; @@ -698,7 +721,7 @@ static int gdb_get_packet_inner(struct connection *connection, gdb_log_incoming_packet(connection, "-"); LOG_WARNING("negative acknowledgment, but no packet pending"); break; - case 0x3: + case CTRL('C'): gdb_log_incoming_packet(connection, "<Ctrl-C>"); gdb_con->ctrl_c = true; *len = 0; @@ -798,6 +821,7 @@ static void gdb_signal_reply(struct target *target, struct connection *connectio } if (gdb_connection->ctrl_c) { + LOG_TARGET_DEBUG(target, "Responding with signal 2 (SIGINT) to debugger due to Ctrl-C"); signal_var = 0x2; } else signal_var = gdb_last_signal(ct); @@ -914,7 +938,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio /* encounter unknown syscall, continue */ gdb_connection->frontend_state = TARGET_RUNNING; - target_resume(target, 1, 0x0, 0, 0); + target_resume(target, true, 0x0, false, false); return; } @@ -924,7 +948,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio if (program_exited) { /* Use target_resume() to let target run its own exit syscall handler. */ gdb_connection->frontend_state = TARGET_RUNNING; - target_resume(target, 1, 0x0, 0, 0); + target_resume(target, true, 0x0, false, false); } else { gdb_connection->frontend_state = TARGET_HALTED; rtos_update_threads(target); @@ -960,9 +984,9 @@ static int gdb_target_callback_event_handler(struct target *target, enum target_event event, void *priv) { struct connection *connection = priv; - struct gdb_service *gdb_service = connection->service->priv; + struct target *gdb_target = get_available_target_from_connection(connection); - if (gdb_service->target != target) + if (gdb_target != target) return ERROR_OK; switch (event) { @@ -985,6 +1009,7 @@ static int gdb_new_connection(struct connection *connection) struct target *target; int retval; int initial_ack; + static unsigned int next_unique_id = 1; target = get_target_from_connection(connection); connection->priv = gdb_connection; @@ -1007,9 +1032,7 @@ static int gdb_new_connection(struct connection *connection) gdb_connection->target_desc.tdesc_length = 0; gdb_connection->thread_list = NULL; gdb_connection->output_flag = GDB_OUTPUT_NO; - - /* send ACK to GDB for debug request */ - gdb_write(connection, "+", 1); + gdb_connection->unique_index = next_unique_id++; /* output goes through gdb connection */ command_set_output_handler(connection->cmd_ctx, gdb_output, connection); @@ -1065,24 +1088,23 @@ static int gdb_new_connection(struct connection *connection) } } - gdb_actual_connections++; log_printf_lf(all_targets->next ? LOG_LVL_INFO : LOG_LVL_DEBUG, __FILE__, __LINE__, __func__, "New GDB Connection: %d, Target %s, state: %s", - gdb_actual_connections, + gdb_connection->unique_index, target_name(target), target_state_name(target)); if (!target_was_examined(target)) { - LOG_ERROR("Target %s not examined yet, refuse gdb connection %d!", - target_name(target), gdb_actual_connections); - gdb_actual_connections--; + LOG_TARGET_ERROR(target, "Target not examined yet, refuse gdb connection %d!", + gdb_connection->unique_index); return ERROR_TARGET_NOT_EXAMINED; } + gdb_actual_connections++; if (target->state != TARGET_HALTED) - LOG_WARNING("GDB connection %d on target %s not halted", - gdb_actual_connections, target_name(target)); + LOG_TARGET_WARNING(target, "GDB connection %d not halted", + gdb_actual_connections); /* DANGER! If we fail subsequently, we must remove this handler, * otherwise we occasionally see crashes as the timer can invoke the @@ -1109,8 +1131,8 @@ static int gdb_connection_closed(struct connection *connection) log_remove_callback(gdb_log_callback, connection); gdb_actual_connections--; - LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d", - target_name(target), + LOG_TARGET_DEBUG(target, "{%d} GDB Close, state: %s, gdb_actual_connections=%d", + gdb_connection->unique_index, target_state_name(target), gdb_actual_connections); @@ -1210,7 +1232,7 @@ static void gdb_target_to_reg(struct target *target, int i; for (i = 0; i < str_len; i += 2) { - unsigned t; + unsigned int t; if (sscanf(tstr + i, "%02x", &t) != 1) { LOG_ERROR("BUG: unable to convert register value"); exit(-1); @@ -1221,6 +1243,29 @@ static void gdb_target_to_reg(struct target *target, } } +/* get register value if needed and fill the buffer accordingly */ +static int gdb_get_reg_value_as_str(struct target *target, char *tstr, struct reg *reg) +{ + int retval = ERROR_OK; + + if (!reg->valid) + retval = reg->type->get(reg); + + const unsigned int len = DIV_ROUND_UP(reg->size, 8) * 2; + switch (retval) { + case ERROR_OK: + gdb_str_to_target(target, tstr, reg); + return ERROR_OK; + case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: + memset(tstr, 'x', len); + tstr[len] = '\0'; + return ERROR_OK; + } + memset(tstr, '0', len); + tstr[len] = '\0'; + return ERROR_FAIL; +} + static int gdb_get_registers_packet(struct connection *connection, char const *packet, int packet_size) { @@ -1246,7 +1291,7 @@ static int gdb_get_registers_packet(struct connection *connection, return gdb_error(connection, retval); for (i = 0; i < reg_list_size; i++) { - if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden) continue; reg_packet_size += DIV_ROUND_UP(reg_list[i]->size, 8) * 2; } @@ -1260,18 +1305,15 @@ static int gdb_get_registers_packet(struct connection *connection, reg_packet_p = reg_packet; for (i = 0; i < reg_list_size; i++) { - if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden) continue; - if (!reg_list[i]->valid) { - retval = reg_list[i]->type->get(reg_list[i]); - if (retval != ERROR_OK && gdb_report_register_access_error) { - LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name); - free(reg_packet); - free(reg_list); - return gdb_error(connection, retval); - } + retval = gdb_get_reg_value_as_str(target, reg_packet_p, reg_list[i]); + if (retval != ERROR_OK && gdb_report_register_access_error) { + LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name); + free(reg_packet); + free(reg_list); + return gdb_error(connection, retval); } - gdb_str_to_target(target, reg_packet_p, reg_list[i]); reg_packet_p += DIV_ROUND_UP(reg_list[i]->size, 8) * 2; } @@ -1323,6 +1365,8 @@ static int gdb_set_registers_packet(struct connection *connection, packet_p = packet; for (i = 0; i < reg_list_size; i++) { uint8_t *bin_buf; + if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden) + continue; int chars = (DIV_ROUND_UP(reg_list[i]->size, 8) * 2); if (packet_p + chars > packet + packet_size) @@ -1375,23 +1419,21 @@ static int gdb_get_register_packet(struct connection *connection, if (retval != ERROR_OK) return gdb_error(connection, retval); - if (reg_list_size <= reg_num) { + if ((reg_list_size <= reg_num) || !reg_list[reg_num] || + !reg_list[reg_num]->exist || reg_list[reg_num]->hidden) { LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num); return ERROR_SERVER_REMOTE_CLOSED; } - if (!reg_list[reg_num]->valid) { - retval = reg_list[reg_num]->type->get(reg_list[reg_num]); - if (retval != ERROR_OK && gdb_report_register_access_error) { - LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name); - free(reg_list); - return gdb_error(connection, retval); - } - } - reg_packet = calloc(DIV_ROUND_UP(reg_list[reg_num]->size, 8) * 2 + 1, 1); /* plus one for string termination null */ - gdb_str_to_target(target, reg_packet, reg_list[reg_num]); + retval = gdb_get_reg_value_as_str(target, reg_packet, reg_list[reg_num]); + if (retval != ERROR_OK && gdb_report_register_access_error) { + LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name); + free(reg_packet); + free(reg_list); + return gdb_error(connection, retval); + } gdb_put_packet(connection, reg_packet, DIV_ROUND_UP(reg_list[reg_num]->size, 8) * 2); @@ -1437,7 +1479,8 @@ static int gdb_set_register_packet(struct connection *connection, return gdb_error(connection, retval); } - if (reg_list_size <= reg_num) { + if ((reg_list_size <= reg_num) || !reg_list[reg_num] || + !reg_list[reg_num]->exist || reg_list[reg_num]->hidden) { LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num); free(bin_buf); free(reg_list); @@ -1481,13 +1524,10 @@ static int gdb_error(struct connection *connection, int retval) return ERROR_OK; } -/* We don't have to worry about the default 2 second timeout for GDB packets, - * because GDB breaks up large memory reads into smaller reads. - */ static int gdb_read_memory_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); char *separator; uint64_t addr = 0; uint32_t len = 0; @@ -1537,7 +1577,7 @@ static int gdb_read_memory_packet(struct connection *connection, * cmd = view%20audit-trail&database = gdb&pr = 2395 * * For now, the default is to fix up things to make current GDB versions work. - * This can be overwritten using the gdb_report_data_abort <'enable'|'disable'> command. + * This can be overwritten using the "gdb report_data_abort <'enable'|'disable'>" command. */ memset(buffer, 0, len); retval = ERROR_OK; @@ -1562,7 +1602,7 @@ static int gdb_read_memory_packet(struct connection *connection, static int gdb_write_memory_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); char *separator; uint64_t addr = 0; uint32_t len = 0; @@ -1613,7 +1653,7 @@ static int gdb_write_memory_packet(struct connection *connection, static int gdb_write_memory_binary_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); char *separator; uint64_t addr = 0; uint32_t len = 0; @@ -1692,8 +1732,8 @@ static int gdb_write_memory_binary_packet(struct connection *connection, static int gdb_step_continue_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); - int current = 0; + struct target *target = get_available_target_from_connection(connection); + bool current = false; uint64_t address = 0x0; int retval = ERROR_OK; @@ -1702,17 +1742,17 @@ static int gdb_step_continue_packet(struct connection *connection, if (packet_size > 1) address = strtoull(packet + 1, NULL, 16); else - current = 1; + current = true; gdb_running_type = packet[0]; if (packet[0] == 'c') { LOG_DEBUG("continue"); /* resume at current address, don't handle breakpoints, not debugging */ - retval = target_resume(target, current, address, 0, 0); + retval = target_resume(target, current, address, false, false); } else if (packet[0] == 's') { LOG_DEBUG("step"); /* step at current or address, don't handle breakpoints */ - retval = target_step(target, current, address, 0); + retval = target_step(target, current, address, false); } return retval; } @@ -1720,7 +1760,7 @@ static int gdb_step_continue_packet(struct connection *connection, static int gdb_breakpoint_watchpoint_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); int type; enum breakpoint_type bp_type = BKPT_SOFT /* dummy init to avoid warning */; enum watchpoint_rw wp_type = WPT_READ /* dummy init to avoid warning */; @@ -1770,15 +1810,9 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection, case 1: if (packet[0] == 'Z') { retval = breakpoint_add(target, address, size, bp_type); - if (retval != ERROR_OK) { - retval = gdb_error(connection, retval); - if (retval != ERROR_OK) - return retval; - } else - gdb_put_packet(connection, "OK", 2); } else { - breakpoint_remove(target, address); - gdb_put_packet(connection, "OK", 2); + assert(packet[0] == 'z'); + retval = breakpoint_remove(target, address); } break; case 2: @@ -1786,24 +1820,27 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection, case 4: { if (packet[0] == 'Z') { - retval = watchpoint_add(target, address, size, wp_type, 0, 0xffffffffu); - if (retval != ERROR_OK) { - retval = gdb_error(connection, retval); - if (retval != ERROR_OK) - return retval; - } else - gdb_put_packet(connection, "OK", 2); + retval = watchpoint_add(target, address, size, wp_type, 0, WATCHPOINT_IGNORE_DATA_VALUE_MASK); } else { - watchpoint_remove(target, address); - gdb_put_packet(connection, "OK", 2); + assert(packet[0] == 'z'); + retval = watchpoint_remove(target, address); } break; } default: + { + retval = ERROR_NOT_IMPLEMENTED; break; + } } - return ERROR_OK; + if (retval == ERROR_NOT_IMPLEMENTED) { + /* Send empty reply to report that watchpoints of this type are not supported */ + return gdb_put_packet(connection, "", 0); + } + if (retval != ERROR_OK) + return gdb_error(connection, retval); + return gdb_put_packet(connection, "OK", 2); } /* print out a string and allocate more space as needed, @@ -1896,7 +1933,7 @@ static int gdb_memory_map(struct connection *connection, * have to regenerate it a couple of times. */ - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); struct flash_bank *p; char *xml = NULL; int size = 0; @@ -1940,8 +1977,8 @@ static int gdb_memory_map(struct connection *connection, compare_bank); for (unsigned int i = 0; i < target_flash_banks; i++) { - unsigned sector_size = 0; - unsigned group_len = 0; + unsigned int sector_size = 0; + unsigned int group_len = 0; p = banks[i]; @@ -2246,7 +2283,7 @@ static int get_reg_features_list(struct target *target, char const **feature_lis *feature_list = calloc(1, sizeof(char *)); for (int i = 0; i < reg_list_size; i++) { - if (reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i]->exist || reg_list[i]->hidden) continue; if (reg_list[i]->feature @@ -2332,12 +2369,13 @@ static int smp_reg_list_noread(struct target *target, } } if (!found) { - LOG_DEBUG("[%s] %s not found in combined list", target_name(target), a->name); + LOG_TARGET_DEBUG(target, "%s not found in combined list", a->name); if (local_list_size >= combined_allocated) { combined_allocated *= 2; local_list = realloc(local_list, combined_allocated * sizeof(struct reg *)); if (!local_list) { LOG_ERROR("realloc(%zu) failed", combined_allocated * sizeof(struct reg *)); + free(reg_list); return ERROR_FAIL; } } @@ -2379,9 +2417,8 @@ static int smp_reg_list_noread(struct target *target, } } if (!found) { - LOG_WARNING("Register %s does not exist in %s, which is part of an SMP group where " - "this register does exist.", - a->name, target_name(head->target)); + LOG_TARGET_WARNING(head->target, "Register %s does not exist, which is part of an SMP group where " + "this register does exist.", a->name); } } free(reg_list); @@ -2456,7 +2493,7 @@ static int gdb_generate_target_description(struct target *target, char **tdesc_o int i; for (i = 0; i < reg_list_size; i++) { - if (reg_list[i]->exist == false || reg_list[i]->hidden) + if (!reg_list[i]->exist || reg_list[i]->hidden) continue; if (strcmp(reg_list[i]->feature->name, features[current_feature])) @@ -2586,7 +2623,7 @@ static int gdb_get_target_description_chunk(struct target *target, struct target return ERROR_OK; } -static int gdb_target_description_supported(struct target *target, int *supported) +static int gdb_target_description_supported(struct target *target, bool *supported) { int retval = ERROR_OK; struct reg **reg_list = NULL; @@ -2618,9 +2655,9 @@ static int gdb_target_description_supported(struct target *target, int *supporte if (supported) { if (architecture || feature_list_size) - *supported = 1; + *supported = true; else - *supported = 0; + *supported = false; } error: @@ -2832,7 +2869,9 @@ static int gdb_query_packet(struct connection *connection, len = strtoul(separator + 1, NULL, 16); + gdb_connection->output_flag = GDB_OUTPUT_NOTIF; retval = target_checksum_memory(target, addr, len, &checksum); + gdb_connection->output_flag = GDB_OUTPUT_NO; if (retval == ERROR_OK) { snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum); @@ -2852,20 +2891,20 @@ static int gdb_query_packet(struct connection *connection, char *buffer = NULL; int pos = 0; int size = 0; - int gdb_target_desc_supported = 0; + bool gdb_target_desc_supported = false; /* we need to test that the target supports target descriptions */ retval = gdb_target_description_supported(target, &gdb_target_desc_supported); if (retval != ERROR_OK) { LOG_INFO("Failed detecting Target Description Support, disabling"); - gdb_target_desc_supported = 0; + gdb_target_desc_supported = false; } /* support may be disabled globally */ - if (gdb_use_target_description == 0) { + if (!gdb_use_target_description) { if (gdb_target_desc_supported) LOG_WARNING("Target Descriptions Supported, but disabled"); - gdb_target_desc_supported = 0; + gdb_target_desc_supported = false; } xml_printf(&retval, @@ -2874,8 +2913,8 @@ static int gdb_query_packet(struct connection *connection, &size, "PacketSize=%x;qXfer:memory-map:read%c;qXfer:features:read%c;qXfer:threads:read+;QStartNoAckMode+;vContSupported+", GDB_BUFFER_SIZE, - ((gdb_use_memory_map == 1) && (flash_get_bank_count() > 0)) ? '+' : '-', - (gdb_target_desc_supported == 1) ? '+' : '-'); + (gdb_use_memory_map && (flash_get_bank_count() > 0)) ? '+' : '-', + gdb_target_desc_supported ? '+' : '-'); if (retval != ERROR_OK) { gdb_send_error(connection, 01); @@ -2955,16 +2994,22 @@ static int gdb_query_packet(struct connection *connection, gdb_connection->noack_mode = 1; gdb_put_packet(connection, "OK", 2); return ERROR_OK; + } else if (target->type->gdb_query_custom) { + char *buffer = NULL; + int ret = target->type->gdb_query_custom(target, packet, &buffer); + gdb_put_packet(connection, buffer, strlen(buffer)); + return ret; } gdb_put_packet(connection, "", 0); return ERROR_OK; } -static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet, int packet_size) +static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet, + __attribute__((unused)) int packet_size) { struct gdb_connection *gdb_connection = connection->priv; - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); const char *parse = packet; int retval; @@ -2980,23 +3025,22 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p if (parse[0] == ';') { ++parse; - --packet_size; } /* simple case, a continue packet */ if (parse[0] == 'c') { gdb_running_type = 'c'; - LOG_DEBUG("target %s continue", target_name(target)); + LOG_TARGET_DEBUG(target, "target continue"); gdb_connection->output_flag = GDB_OUTPUT_ALL; - retval = target_resume(target, 1, 0, 0, 0); + retval = target_resume(target, true, 0, false, false); if (retval == ERROR_TARGET_NOT_HALTED) - LOG_INFO("target %s was not halted when resume was requested", target_name(target)); + LOG_TARGET_INFO(target, "target was not halted when resume was requested"); /* poll target in an attempt to make its internal state consistent */ if (retval != ERROR_OK) { retval = target_poll(target); if (retval != ERROR_OK) - LOG_DEBUG("error polling target %s after failed resume", target_name(target)); + LOG_TARGET_DEBUG(target, "error polling target after failed resume"); } /* @@ -3015,128 +3059,123 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p gdb_running_type = 's'; bool fake_step = false; - if (strncmp(parse, "s:", 2) == 0) { - struct target *ct = target; - int current_pc = 1; - int64_t thread_id; + struct target *ct = target; + bool current_pc = true; + int64_t thread_id; + parse++; + if (parse[0] == ':') { char *endp; - - parse += 2; - packet_size -= 2; - + parse++; thread_id = strtoll(parse, &endp, 16); if (endp) { - packet_size -= endp - parse; parse = endp; } + } else { + thread_id = 0; + } - if (target->rtos) { - /* FIXME: why is this necessary? rtos state should be up-to-date here already! */ - rtos_update_threads(target); + if (target->rtos) { + /* FIXME: why is this necessary? rtos state should be up-to-date here already! */ + rtos_update_threads(target); - target->rtos->gdb_target_for_threadid(connection, thread_id, &ct); + target->rtos->gdb_target_for_threadid(connection, thread_id, &ct); - /* - * check if the thread to be stepped is the current rtos thread - * if not, we must fake the step - */ - if (target->rtos->current_thread != thread_id) - fake_step = true; - } + /* + * check if the thread to be stepped is the current rtos thread + * if not, we must fake the step + */ + if (target->rtos->current_thread != thread_id) + fake_step = true; + } + + if (parse[0] == ';') { + ++parse; - if (parse[0] == ';') { - ++parse; - --packet_size; + if (parse[0] == 'c') { + parse += 1; - if (parse[0] == 'c') { + /* check if thread-id follows */ + if (parse[0] == ':') { + int64_t tid; parse += 1; - /* check if thread-id follows */ - if (parse[0] == ':') { - int64_t tid; - parse += 1; - - tid = strtoll(parse, &endp, 16); - if (tid == thread_id) { - /* - * Special case: only step a single thread (core), - * keep the other threads halted. Currently, only - * aarch64 target understands it. Other target types don't - * care (nobody checks the actual value of 'current') - * and it doesn't really matter. This deserves - * a symbolic constant and a formal interface documentation - * at a later time. - */ - LOG_DEBUG("request to step current core only"); - /* uncomment after checking that indeed other targets are safe */ - /*current_pc = 2;*/ - } + tid = strtoll(parse, NULL, 16); + if (tid == thread_id) { + /* + * Special case: only step a single thread (core), + * keep the other threads halted. Currently, only + * aarch64 target understands it. Other target types don't + * care (nobody checks the actual value of 'current') + * and it doesn't really matter. This deserves + * a symbolic constant and a formal interface documentation + * at a later time. + */ + LOG_DEBUG("request to step current core only"); + /* uncomment after checking that indeed other targets are safe */ + /*current_pc = 2;*/ } } } + } - LOG_DEBUG("target %s single-step thread %"PRIx64, target_name(ct), thread_id); - gdb_connection->output_flag = GDB_OUTPUT_ALL; - target_call_event_callbacks(ct, TARGET_EVENT_GDB_START); - - /* - * work around an annoying gdb behaviour: when the current thread - * is changed in gdb, it assumes that the target can follow and also - * make the thread current. This is an assumption that cannot hold - * for a real target running a multi-threading OS. We just fake - * the step to not trigger an internal error in gdb. See - * https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details - */ - if (fake_step) { - int sig_reply_len; - char sig_reply[128]; - - LOG_DEBUG("fake step thread %"PRIx64, thread_id); + LOG_TARGET_DEBUG(ct, "single-step thread %" PRIx64, thread_id); + gdb_connection->output_flag = GDB_OUTPUT_ALL; + target_call_event_callbacks(ct, TARGET_EVENT_GDB_START); - sig_reply_len = snprintf(sig_reply, sizeof(sig_reply), - "T05thread:%016"PRIx64";", thread_id); + /* + * work around an annoying gdb behaviour: when the current thread + * is changed in gdb, it assumes that the target can follow and also + * make the thread current. This is an assumption that cannot hold + * for a real target running a multi-threading OS. We just fake + * the step to not trigger an internal error in gdb. See + * https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details + */ + if (fake_step) { + int sig_reply_len; + char sig_reply[128]; - gdb_put_packet(connection, sig_reply, sig_reply_len); - gdb_connection->output_flag = GDB_OUTPUT_NO; + LOG_DEBUG("fake step thread %"PRIx64, thread_id); - return true; - } + sig_reply_len = snprintf(sig_reply, sizeof(sig_reply), + "T05thread:%016"PRIx64";", thread_id); - /* support for gdb_sync command */ - if (gdb_connection->sync) { - gdb_connection->sync = false; - if (ct->state == TARGET_HALTED) { - LOG_DEBUG("stepi ignored. GDB will now fetch the register state " - "from the target."); - gdb_sig_halted(connection); - gdb_connection->output_flag = GDB_OUTPUT_NO; - } else - gdb_connection->frontend_state = TARGET_RUNNING; - return true; - } + gdb_put_packet(connection, sig_reply, sig_reply_len); + gdb_connection->output_flag = GDB_OUTPUT_NO; - retval = target_step(ct, current_pc, 0, 0); - if (retval == ERROR_TARGET_NOT_HALTED) - LOG_INFO("target %s was not halted when step was requested", target_name(ct)); + return true; + } - /* if step was successful send a reply back to gdb */ - if (retval == ERROR_OK) { - retval = target_poll(ct); - if (retval != ERROR_OK) - LOG_DEBUG("error polling target %s after successful step", target_name(ct)); - /* send back signal information */ - gdb_signal_reply(ct, connection); - /* stop forwarding log packets! */ + /* support for gdb_sync command */ + if (gdb_connection->sync) { + gdb_connection->sync = false; + if (ct->state == TARGET_HALTED) { + LOG_DEBUG("stepi ignored. GDB will now fetch the register state " + "from the target."); + gdb_sig_halted(connection); gdb_connection->output_flag = GDB_OUTPUT_NO; } else gdb_connection->frontend_state = TARGET_RUNNING; - } else { - LOG_ERROR("Unknown vCont packet"); - return false; + return true; } + + retval = target_step(ct, current_pc, 0, false); + if (retval == ERROR_TARGET_NOT_HALTED) + LOG_TARGET_INFO(ct, "target was not halted when step was requested"); + + /* if step was successful send a reply back to gdb */ + if (retval == ERROR_OK) { + retval = target_poll(ct); + if (retval != ERROR_OK) + LOG_TARGET_DEBUG(ct, "error polling target after successful step"); + /* send back signal information */ + gdb_signal_reply(ct, connection); + /* stop forwarding log packets! */ + gdb_connection->output_flag = GDB_OUTPUT_NO; + } else + gdb_connection->frontend_state = TARGET_RUNNING; return true; } - + LOG_ERROR("Unknown vCont packet"); return false; } @@ -3192,7 +3231,7 @@ static void gdb_restart_inferior(struct connection *connection, const char *pack static bool gdb_handle_vrun_packet(struct connection *connection, const char *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); const char *parse = packet; /* Skip "vRun" */ @@ -3238,7 +3277,7 @@ static int gdb_v_packet(struct connection *connection, struct gdb_connection *gdb_connection = connection->priv; int result; - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); if (strncmp(packet, "vCont", 5) == 0) { bool handled; @@ -3265,13 +3304,13 @@ static int gdb_v_packet(struct connection *connection, /* if flash programming disabled - send a empty reply */ - if (gdb_flash_program == 0) { + if (!gdb_flash_program) { gdb_put_packet(connection, "", 0); return ERROR_OK; } if (strncmp(packet, "vFlashErase:", 12) == 0) { - unsigned long addr; + target_addr_t addr; unsigned long length; char const *parse = packet + 12; @@ -3280,7 +3319,7 @@ static int gdb_v_packet(struct connection *connection, return ERROR_SERVER_REMOTE_CLOSED; } - addr = strtoul(parse, (char **)&parse, 16); + addr = strtoull(parse, (char **)&parse, 16); if (*(parse++) != ',' || *parse == '\0') { LOG_ERROR("incomplete vFlashErase packet received, dropping connection"); @@ -3328,7 +3367,7 @@ static int gdb_v_packet(struct connection *connection, if (strncmp(packet, "vFlashWrite:", 12) == 0) { int retval; - unsigned long addr; + target_addr_t addr; unsigned long length; char const *parse = packet + 12; @@ -3336,7 +3375,8 @@ static int gdb_v_packet(struct connection *connection, LOG_ERROR("incomplete vFlashErase packet received, dropping connection"); return ERROR_SERVER_REMOTE_CLOSED; } - addr = strtoul(parse, (char **)&parse, 16); + + addr = strtoull(parse, (char **)&parse, 16); if (*(parse++) != ':') { LOG_ERROR("incomplete vFlashErase packet received, dropping connection"); return ERROR_SERVER_REMOTE_CLOSED; @@ -3363,6 +3403,13 @@ static int gdb_v_packet(struct connection *connection, if (strncmp(packet, "vFlashDone", 10) == 0) { uint32_t written; + /* GDB command 'flash-erase' does not send a vFlashWrite, + * so nothing to write here. */ + if (!gdb_connection->vflash_image) { + gdb_put_packet(connection, "OK", 2); + return ERROR_OK; + } + /* process the flashing buffer. No need to erase as GDB * always issues a vFlashErase first. */ target_call_event_callbacks(target, @@ -3409,7 +3456,7 @@ static int gdb_detach(struct connection *connection) static int gdb_fileio_response_packet(struct connection *connection, char const *packet, int packet_size) { - struct target *target = get_target_from_connection(connection); + struct target *target = get_available_target_from_connection(connection); char *separator; char *parsing_point; int fileio_retcode = strtoul(packet + 1, &separator, 16); @@ -3439,9 +3486,9 @@ static int gdb_fileio_response_packet(struct connection *connection, /* After File-I/O ends, keep continue or step */ if (gdb_running_type == 'c') - retval = target_resume(target, 1, 0x0, 0, 0); + retval = target_resume(target, true, 0x0, false, false); else if (gdb_running_type == 's') - retval = target_step(target, 1, 0x0, 0); + retval = target_step(target, true, 0x0, false); else retval = ERROR_FAIL; @@ -3451,13 +3498,13 @@ static int gdb_fileio_response_packet(struct connection *connection, return ERROR_OK; } -static void gdb_log_callback(void *priv, const char *file, unsigned line, +static void gdb_log_callback(void *priv, const char *file, unsigned int line, const char *function, const char *string) { struct connection *connection = priv; struct gdb_connection *gdb_con = connection->priv; - if (gdb_con->output_flag == GDB_OUTPUT_NO) + if (gdb_con->output_flag != GDB_OUTPUT_ALL) /* No out allowed */ return; @@ -3542,10 +3589,14 @@ static int gdb_input_inner(struct connection *connection) retval = gdb_set_register_packet(connection, packet, packet_size); break; case 'm': + gdb_con->output_flag = GDB_OUTPUT_NOTIF; retval = gdb_read_memory_packet(connection, packet, packet_size); + gdb_con->output_flag = GDB_OUTPUT_NO; break; case 'M': + gdb_con->output_flag = GDB_OUTPUT_NOTIF; retval = gdb_write_memory_packet(connection, packet, packet_size); + gdb_con->output_flag = GDB_OUTPUT_NO; break; case 'z': case 'Z': @@ -3636,9 +3687,9 @@ static int gdb_input_inner(struct connection *connection) retval = gdb_detach(connection); break; case 'X': + gdb_con->output_flag = GDB_OUTPUT_NOTIF; retval = gdb_write_memory_binary_packet(connection, packet, packet_size); - if (retval != ERROR_OK) - return retval; + gdb_con->output_flag = GDB_OUTPUT_NO; break; case 'k': if (gdb_con->extended_protocol) { @@ -3698,10 +3749,11 @@ static int gdb_input_inner(struct connection *connection) } if (gdb_con->ctrl_c) { - if (target->state == TARGET_RUNNING) { - struct target *t = target; - if (target->rtos) - target->rtos->gdb_target_for_threadid(connection, target->rtos->current_threadid, &t); + struct target *available_target = get_available_target_from_connection(connection); + if (available_target->state == TARGET_RUNNING) { + struct target *t = available_target; + if (available_target->rtos) + available_target->rtos->gdb_target_for_threadid(connection, target->rtos->current_threadid, &t); retval = target_halt(t); if (retval == ERROR_OK) retval = target_poll(t); @@ -3709,7 +3761,8 @@ static int gdb_input_inner(struct connection *connection) target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); gdb_con->ctrl_c = false; } else { - LOG_INFO("The target is not running when halt was requested, stopping GDB."); + LOG_TARGET_INFO(target, "Not running when halt was requested, stopping GDB. (state=%d)", + target->state); target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); } } @@ -3734,19 +3787,51 @@ static int gdb_input(struct connection *connection) return ERROR_OK; } +/* + * Send custom notification packet as keep-alive during memory read/write. + * + * From gdb 7.0 (released 2009-10-06) an unknown notification received during + * memory read/write would be silently dropped. + * Before gdb 7.0 any character, with exclusion of "+-$", would be considered + * as junk and ignored. + * In both cases the reception will reset the timeout counter in gdb, thus + * working as a keep-alive. + * Check putpkt_binary() and getpkt_sane() in gdb commit + * 74531fed1f2d662debc2c209b8b3faddceb55960 + * + * Enable remote debug in gdb with 'set debug remote 1' to either dump the junk + * characters in gdb pre-7.0 and the notification from gdb 7.0. + */ +static void gdb_async_notif(struct connection *connection) +{ + static unsigned char count; + unsigned char checksum = 0; + char buf[22]; + + int len = sprintf(buf, "%%oocd_keepalive:%2.2x", count++); + for (int i = 1; i < len; i++) + checksum += buf[i]; + len += sprintf(buf + len, "#%2.2x", checksum); + +#ifdef _DEBUG_GDB_IO_ + LOG_DEBUG("sending packet '%s'", buf); +#endif + + gdb_write(connection, buf, len); +} + static void gdb_keep_client_alive(struct connection *connection) { struct gdb_connection *gdb_con = connection->priv; - if (gdb_con->busy) { - /* do not send packets, retry asap */ - return; - } - switch (gdb_con->output_flag) { case GDB_OUTPUT_NO: /* no need for keep-alive */ break; + case GDB_OUTPUT_NOTIF: + /* send asynchronous notification */ + gdb_async_notif(connection); + break; case GDB_OUTPUT_ALL: /* send an empty O packet */ gdb_output_con(connection, ""); @@ -3774,7 +3859,7 @@ static int gdb_target_start(struct target *target, const char *port) if (!gdb_service) return -ENOMEM; - LOG_INFO("starting gdb server for %s on %s", target_name(target), port); + LOG_TARGET_INFO(target, "starting gdb server on %s", port); gdb_service->target = target; gdb_service->core[0] = -1; @@ -3802,20 +3887,20 @@ static int gdb_target_add_one(struct target *target) /* skip targets that cannot handle a gdb connections (e.g. mem_ap) */ if (!target_supports_gdb_connection(target)) { - LOG_DEBUG("skip gdb server for target %s", target_name(target)); + LOG_TARGET_DEBUG(target, "skip gdb server"); return ERROR_OK; } if (target->gdb_port_override) { if (strcmp(target->gdb_port_override, "disabled") == 0) { - LOG_INFO("gdb port disabled"); + LOG_TARGET_INFO(target, "gdb port disabled"); return ERROR_OK; } return gdb_target_start(target, target->gdb_port_override); } - if (strcmp(gdb_port, "disabled") == 0) { - LOG_INFO("gdb port disabled"); + if (strcmp(gdb_port_next, "disabled") == 0) { + LOG_TARGET_INFO(target, "gdb port disabled"); return ERROR_OK; } @@ -3843,6 +3928,9 @@ static int gdb_target_add_one(struct target *target) gdb_port_next = strdup("0"); } } + } else if (strcmp(gdb_port_next, "pipe") == 0) { + free(gdb_port_next); + gdb_port_next = strdup("disabled"); } } return retval; @@ -3873,7 +3961,7 @@ COMMAND_HANDLER(handle_gdb_sync_command) if (!current_gdb_connection) { command_print(CMD, - "gdb_sync command can only be run from within gdb using \"monitor gdb_sync\""); + "gdb sync command can only be run from within gdb using \"monitor gdb sync\""); return ERROR_FAIL; } @@ -3882,7 +3970,6 @@ COMMAND_HANDLER(handle_gdb_sync_command) return ERROR_OK; } -/* daemon configuration command gdb_port */ COMMAND_HANDLER(handle_gdb_port_command) { int retval = CALL_COMMAND_HANDLER(server_pipe_command, &gdb_port); @@ -3929,7 +4016,6 @@ COMMAND_HANDLER(handle_gdb_report_register_access_error) return ERROR_OK; } -/* gdb_breakpoint_override */ COMMAND_HANDLER(handle_gdb_breakpoint_override_command) { if (CMD_ARGC == 0) { @@ -4006,9 +4092,9 @@ COMMAND_HANDLER(handle_gdb_save_tdesc_command) return retval; } -static const struct command_registration gdb_command_handlers[] = { +static const struct command_registration gdb_subcommand_handlers[] = { { - .name = "gdb_sync", + .name = "sync", .handler = handle_gdb_sync_command, .mode = COMMAND_ANY, .help = "next stepi will return immediately allowing " @@ -4017,7 +4103,7 @@ static const struct command_registration gdb_command_handlers[] = { .usage = "" }, { - .name = "gdb_port", + .name = "port", .handler = handle_gdb_port_command, .mode = COMMAND_CONFIG, .help = "Normally gdb listens to a TCP/IP port. Each subsequent GDB " @@ -4030,35 +4116,35 @@ static const struct command_registration gdb_command_handlers[] = { .usage = "[port_num]", }, { - .name = "gdb_memory_map", + .name = "memory_map", .handler = handle_gdb_memory_map_command, .mode = COMMAND_CONFIG, .help = "enable or disable memory map", .usage = "('enable'|'disable')" }, { - .name = "gdb_flash_program", + .name = "flash_program", .handler = handle_gdb_flash_program_command, .mode = COMMAND_CONFIG, .help = "enable or disable flash program", .usage = "('enable'|'disable')" }, { - .name = "gdb_report_data_abort", + .name = "report_data_abort", .handler = handle_gdb_report_data_abort_command, .mode = COMMAND_CONFIG, .help = "enable or disable reporting data aborts", .usage = "('enable'|'disable')" }, { - .name = "gdb_report_register_access_error", + .name = "report_register_access_error", .handler = handle_gdb_report_register_access_error, .mode = COMMAND_CONFIG, .help = "enable or disable reporting register access errors", .usage = "('enable'|'disable')" }, { - .name = "gdb_breakpoint_override", + .name = "breakpoint_override", .handler = handle_gdb_breakpoint_override_command, .mode = COMMAND_ANY, .help = "Display or specify type of breakpoint " @@ -4066,14 +4152,14 @@ static const struct command_registration gdb_command_handlers[] = { .usage = "('hard'|'soft'|'disable')" }, { - .name = "gdb_target_description", + .name = "target_description", .handler = handle_gdb_target_description_command, .mode = COMMAND_CONFIG, .help = "enable or disable target description", .usage = "('enable'|'disable')" }, { - .name = "gdb_save_tdesc", + .name = "save_tdesc", .handler = handle_gdb_save_tdesc_command, .mode = COMMAND_EXEC, .help = "Save the target description file", @@ -4082,6 +4168,17 @@ static const struct command_registration gdb_command_handlers[] = { COMMAND_REGISTRATION_DONE }; +static const struct command_registration gdb_command_handlers[] = { + { + .name = "gdb", + .mode = COMMAND_ANY, + .help = "GDB commands", + .chain = gdb_subcommand_handlers, + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; + int gdb_register_commands(struct command_context *cmd_ctx) { gdb_port = strdup("3333"); @@ -4094,3 +4191,8 @@ void gdb_service_free(void) free(gdb_port); free(gdb_port_next); } + +int gdb_get_actual_connections(void) +{ + return gdb_actual_connections; +} diff --git a/src/server/gdb_server.h b/src/server/gdb_server.h index e27aad7cfc..1a626ebd94 100644 --- a/src/server/gdb_server.h +++ b/src/server/gdb_server.h @@ -20,6 +20,7 @@ struct image; struct reg; #include <target/target.h> +#include <server/server.h> #define GDB_BUFFER_SIZE 16384 @@ -27,7 +28,9 @@ int gdb_target_add_all(struct target *target); int gdb_register_commands(struct command_context *command_context); void gdb_service_free(void); -int gdb_put_packet(struct connection *connection, char *buffer, int len); +int gdb_put_packet(struct connection *connection, const char *buffer, int len); + +int gdb_get_actual_connections(void); static inline struct target *get_target_from_connection(struct connection *connection) { diff --git a/src/server/ipdbg.c b/src/server/ipdbg.c index 3bbcf07146..859fdb035e 100644 --- a/src/server/ipdbg.c +++ b/src/server/ipdbg.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* Copyright (C) 2020 by Daniel Anselmi <danselmi@gmx.ch> */ #ifdef HAVE_CONFIG_H @@ -10,15 +10,20 @@ #include <jtag/jtag.h> #include <server/server.h> #include <target/target.h> +#include <pld/pld.h> #include "ipdbg.h" #define IPDBG_BUFFER_SIZE 16384 -#define IPDBG_MIN_NUM_OF_OPTIONS 4 -#define IPDBG_MAX_NUM_OF_OPTIONS 14 +#define IPDBG_MIN_NUM_OF_CREATE_OPTIONS 3 +#define IPDBG_MAX_NUM_OF_CREATE_OPTIONS 10 +#define IPDBG_NUM_OF_START_OPTIONS 4 +#define IPDBG_NUM_OF_STOP_OPTIONS 2 +#define IPDBG_NUM_OF_QUEUE_OPTIONS 2 #define IPDBG_MIN_DR_LENGTH 11 #define IPDBG_MAX_DR_LENGTH 13 #define IPDBG_TCP_PORT_STR_MAX_LENGTH 6 +#define IPDBG_SCRATCH_MEMORY_SIZE 1024 /* private connection data for IPDBG */ struct ipdbg_fifo { @@ -47,6 +52,13 @@ struct ipdbg_virtual_ir_info { uint32_t value; }; +struct ipdbg_hub_scratch_memory { + uint8_t *dr_out_vals; + uint8_t *dr_in_vals; + uint8_t *vir_out_val; + struct scan_field *fields; +}; + struct ipdbg_hub { uint32_t user_instruction; uint32_t max_tools; @@ -56,12 +68,16 @@ struct ipdbg_hub { uint32_t xoff_mask; uint32_t tool_mask; uint32_t last_dn_tool; + char *name; + size_t using_queue_size; struct ipdbg_hub *next; struct jtag_tap *tap; struct connection **connections; uint8_t data_register_length; uint8_t dn_xoff; + uint8_t flow_control_enabled; struct ipdbg_virtual_ir_info *virtual_ir; + struct ipdbg_hub_scratch_memory scratch_memory; }; static struct ipdbg_hub *ipdbg_first_hub; @@ -90,7 +106,7 @@ static void ipdbg_zero_rd_idx(struct ipdbg_fifo *fifo) return; size_t ri = fifo->rd_idx; - for (size_t idx = 0 ; idx < fifo->count ; ++idx) + for (size_t idx = 0; idx < fifo->count; ++idx) fifo->buffer[idx] = fifo->buffer[ri++]; fifo->rd_idx = 0; } @@ -149,7 +165,7 @@ static int ipdbg_max_tools_from_data_register_length(uint8_t data_register_lengt static struct ipdbg_service *ipdbg_find_service(struct ipdbg_hub *hub, uint8_t tool) { struct ipdbg_service *service; - for (service = ipdbg_first_service ; service ; service = service->next) { + for (service = ipdbg_first_service; service; service = service->next) { if (service->hub == hub && service->tool == tool) break; } @@ -160,7 +176,7 @@ static void ipdbg_add_service(struct ipdbg_service *service) { struct ipdbg_service *iservice; if (ipdbg_first_service) { - for (iservice = ipdbg_first_service ; iservice->next; iservice = iservice->next) + for (iservice = ipdbg_first_service; iservice->next; iservice = iservice->next) ; iservice->next = service; } else @@ -192,7 +208,7 @@ static int ipdbg_remove_service(struct ipdbg_service *service) return ERROR_OK; } - for (struct ipdbg_service *iservice = ipdbg_first_service ; iservice->next ; iservice = iservice->next) { + for (struct ipdbg_service *iservice = ipdbg_first_service; iservice->next; iservice = iservice->next) { if (service == iservice->next) { iservice->next = service->next; return ERROR_OK; @@ -205,7 +221,7 @@ static struct ipdbg_hub *ipdbg_find_hub(struct jtag_tap *tap, uint32_t user_instruction, struct ipdbg_virtual_ir_info *virtual_ir) { struct ipdbg_hub *hub = NULL; - for (hub = ipdbg_first_hub ; hub ; hub = hub->next) { + for (hub = ipdbg_first_hub; hub; hub = hub->next) { if (hub->tap == tap && hub->user_instruction == user_instruction) { if ((!virtual_ir && !hub->virtual_ir) || (virtual_ir && hub->virtual_ir && @@ -223,44 +239,31 @@ static void ipdbg_add_hub(struct ipdbg_hub *hub) { struct ipdbg_hub *ihub; if (ipdbg_first_hub) { - for (ihub = ipdbg_first_hub ; ihub->next; ihub = ihub->next) + for (ihub = ipdbg_first_hub; ihub->next; ihub = ihub->next) ; ihub->next = hub; - } else + } else { ipdbg_first_hub = hub; + } } -static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uint8_t data_register_length, - struct ipdbg_virtual_ir_info *virtual_ir, struct ipdbg_hub **hub) +static int ipdbg_remove_hub(struct ipdbg_hub *hub) { - *hub = NULL; - struct ipdbg_hub *new_hub = calloc(1, sizeof(struct ipdbg_hub)); - if (!new_hub) { - free(virtual_ir); - LOG_ERROR("Out of memory"); + if (!ipdbg_first_hub) return ERROR_FAIL; + if (hub == ipdbg_first_hub) { + ipdbg_first_hub = ipdbg_first_hub->next; + return ERROR_OK; } - new_hub->max_tools = ipdbg_max_tools_from_data_register_length(data_register_length); - new_hub->connections = calloc(new_hub->max_tools, sizeof(struct connection *)); - if (!new_hub->connections) { - free(virtual_ir); - free(new_hub); - LOG_ERROR("Out of memory"); - return ERROR_FAIL; + for (struct ipdbg_hub *ihub = ipdbg_first_hub; ihub->next; ihub = ihub->next) { + if (hub == ihub->next) { + ihub->next = hub->next; + return ERROR_OK; + } } - new_hub->tap = tap; - new_hub->user_instruction = user_instruction; - new_hub->data_register_length = data_register_length; - new_hub->valid_mask = BIT(data_register_length - 1); - new_hub->xoff_mask = BIT(data_register_length - 2); - new_hub->tool_mask = (new_hub->xoff_mask - 1) >> 8; - new_hub->last_dn_tool = new_hub->tool_mask; - new_hub->virtual_ir = virtual_ir; - - *hub = new_hub; - return ERROR_OK; + return ERROR_FAIL; } static void ipdbg_free_hub(struct ipdbg_hub *hub) @@ -269,26 +272,54 @@ static void ipdbg_free_hub(struct ipdbg_hub *hub) return; free(hub->connections); free(hub->virtual_ir); + free(hub->name); + free(hub->scratch_memory.dr_out_vals); + free(hub->scratch_memory.dr_in_vals); + free(hub->scratch_memory.fields); + free(hub->scratch_memory.vir_out_val); free(hub); } -static int ipdbg_remove_hub(struct ipdbg_hub *hub) +static struct ipdbg_hub *ipdbg_allocate_hub(uint8_t data_register_length, struct ipdbg_virtual_ir_info *virtual_ir, + const char *name) { - if (!ipdbg_first_hub) - return ERROR_FAIL; - if (hub == ipdbg_first_hub) { - ipdbg_first_hub = ipdbg_first_hub->next; - return ERROR_OK; + struct ipdbg_hub *new_hub = calloc(1, sizeof(struct ipdbg_hub)); + if (!new_hub) { + free(virtual_ir); + LOG_ERROR("Out of memory"); + return NULL; } - for (struct ipdbg_hub *ihub = ipdbg_first_hub ; ihub->next ; ihub = ihub->next) { - if (hub == ihub->next) { - ihub->next = hub->next; - return ERROR_OK; - } + new_hub->name = strdup(name); + if (!new_hub->name) { + free(new_hub); + free(virtual_ir); + LOG_ERROR("Out of memory"); + return NULL; } - return ERROR_FAIL; + const size_t dreg_buffer_size = DIV_ROUND_UP(data_register_length, 8); + uint32_t max_tools = ipdbg_max_tools_from_data_register_length(data_register_length); + + new_hub->scratch_memory.dr_out_vals = calloc(IPDBG_SCRATCH_MEMORY_SIZE, dreg_buffer_size); + new_hub->scratch_memory.dr_in_vals = calloc(IPDBG_SCRATCH_MEMORY_SIZE, dreg_buffer_size); + new_hub->scratch_memory.fields = calloc(IPDBG_SCRATCH_MEMORY_SIZE, sizeof(struct scan_field)); + new_hub->connections = calloc(max_tools, sizeof(struct connection *)); + + if (virtual_ir) { + new_hub->virtual_ir = virtual_ir; + new_hub->scratch_memory.vir_out_val = calloc(1, DIV_ROUND_UP(virtual_ir->length, 8)); + } + + if (!new_hub->scratch_memory.dr_out_vals || !new_hub->scratch_memory.dr_in_vals || + !new_hub->scratch_memory.fields || (virtual_ir && !new_hub->scratch_memory.vir_out_val) || + !new_hub->connections) { + ipdbg_free_hub(new_hub); + LOG_ERROR("Out of memory"); + return NULL; + } + + return new_hub; } static void ipdbg_init_scan_field(struct scan_field *fields, uint8_t *in_value, int num_bits, const uint8_t *out_value) @@ -315,6 +346,10 @@ static int ipdbg_shift_instr(struct ipdbg_hub *hub, uint32_t instr) } uint8_t *ir_out_val = calloc(DIV_ROUND_UP(tap->ir_length, 8), 1); + if (!ir_out_val) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } buf_set_u32(ir_out_val, 0, tap->ir_length, instr); struct scan_field fields; @@ -343,16 +378,11 @@ static int ipdbg_shift_vir(struct ipdbg_hub *hub) if (!tap) return ERROR_FAIL; - uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->virtual_ir->length, 8), 1); - buf_set_u32(dr_out_val, 0, hub->virtual_ir->length, hub->virtual_ir->value); - - struct scan_field fields; - ipdbg_init_scan_field(&fields, NULL, hub->virtual_ir->length, dr_out_val); - jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE); + ipdbg_init_scan_field(hub->scratch_memory.fields, NULL, + hub->virtual_ir->length, hub->scratch_memory.vir_out_val); + jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields, TAP_IDLE); retval = jtag_execute_queue(); - free(dr_out_val); - return retval; } @@ -365,20 +395,15 @@ static int ipdbg_shift_data(struct ipdbg_hub *hub, uint32_t dn_data, uint32_t *u if (!tap) return ERROR_FAIL; - uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1); - buf_set_u32(dr_out_val, 0, hub->data_register_length, dn_data); - uint8_t *dr_in_val = up_data ? calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1) : NULL; + buf_set_u32(hub->scratch_memory.dr_out_vals, 0, hub->data_register_length, dn_data); - struct scan_field fields; - ipdbg_init_scan_field(&fields, dr_in_val, hub->data_register_length, dr_out_val); - jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE); + ipdbg_init_scan_field(hub->scratch_memory.fields, hub->scratch_memory.dr_in_vals, + hub->data_register_length, hub->scratch_memory.dr_out_vals); + jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields, TAP_IDLE); int retval = jtag_execute_queue(); if (up_data && retval == ERROR_OK) - *up_data = buf_get_u32(dr_in_val, 0, hub->data_register_length); - - free(dr_out_val); - free(dr_in_val); + *up_data = buf_get_u32(hub->scratch_memory.dr_in_vals, 0, hub->data_register_length); return retval; } @@ -410,6 +435,60 @@ static int ipdbg_distribute_data_from_hub(struct ipdbg_hub *hub, uint32_t up) return ERROR_OK; } +static void ipdbg_check_for_xoff(struct ipdbg_hub *hub, size_t tool, + uint32_t rx_data) +{ + if ((rx_data & hub->xoff_mask) && hub->last_dn_tool != hub->max_tools) { + hub->dn_xoff |= BIT(hub->last_dn_tool); + LOG_INFO("tool %d sent xoff", hub->last_dn_tool); + } + + hub->last_dn_tool = tool; +} + +static int ipdbg_shift_empty_data(struct ipdbg_hub *hub) +{ + if (!hub) + return ERROR_FAIL; + + struct jtag_tap *tap = hub->tap; + if (!tap) + return ERROR_FAIL; + + const size_t dreg_buffer_size = DIV_ROUND_UP(hub->data_register_length, 8); + memset(hub->scratch_memory.dr_out_vals, 0, dreg_buffer_size); + for (size_t i = 0; i < hub->using_queue_size; ++i) { + ipdbg_init_scan_field(hub->scratch_memory.fields + i, + hub->scratch_memory.dr_in_vals + i * dreg_buffer_size, + hub->data_register_length, + hub->scratch_memory.dr_out_vals); + jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields + i, TAP_IDLE); + } + + int retval = jtag_execute_queue(); + + if (retval == ERROR_OK) { + uint32_t up_data; + for (size_t i = 0; i < hub->using_queue_size; ++i) { + up_data = buf_get_u32(hub->scratch_memory.dr_in_vals + + i * dreg_buffer_size, 0, + hub->data_register_length); + int rv = ipdbg_distribute_data_from_hub(hub, up_data); + if (rv != ERROR_OK) + retval = rv; + + if (i == 0) { + /* check if xoff sent is only needed on the first transfer which + may contain the xoff of the prev down transfer. + */ + ipdbg_check_for_xoff(hub, hub->max_tools, up_data); + } + } + } + + return retval; +} + static int ipdbg_jtag_transfer_byte(struct ipdbg_hub *hub, size_t tool, struct ipdbg_connection *connection) { uint32_t dn = hub->valid_mask | ((tool & hub->tool_mask) << 8) | @@ -423,14 +502,63 @@ static int ipdbg_jtag_transfer_byte(struct ipdbg_hub *hub, size_t tool, struct i if (ret != ERROR_OK) return ret; - if ((up & hub->xoff_mask) && (hub->last_dn_tool != hub->max_tools)) { - hub->dn_xoff |= BIT(hub->last_dn_tool); - LOG_INFO("tool %d sent xoff", hub->last_dn_tool); + ipdbg_check_for_xoff(hub, tool, up); + + return ERROR_OK; +} + +static int ipdbg_jtag_transfer_bytes(struct ipdbg_hub *hub, + size_t tool, struct ipdbg_connection *connection) +{ + if (!hub) + return ERROR_FAIL; + + struct jtag_tap *tap = hub->tap; + if (!tap) + return ERROR_FAIL; + + const size_t dreg_buffer_size = DIV_ROUND_UP(hub->data_register_length, 8); + size_t num_tx = (connection->dn_fifo.count < hub->using_queue_size) ? + connection->dn_fifo.count : hub->using_queue_size; + + for (size_t i = 0; i < num_tx; ++i) { + uint32_t dn_data = hub->valid_mask | ((tool & hub->tool_mask) << 8) | + (0x00fful & ipdbg_get_from_fifo(&connection->dn_fifo)); + buf_set_u32(hub->scratch_memory.dr_out_vals + i * dreg_buffer_size, 0, + hub->data_register_length, dn_data); + + ipdbg_init_scan_field(hub->scratch_memory.fields + i, + hub->scratch_memory.dr_in_vals + + i * dreg_buffer_size, + hub->data_register_length, + hub->scratch_memory.dr_out_vals + + i * dreg_buffer_size); + jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields + i, TAP_IDLE); } - hub->last_dn_tool = tool; + int retval = jtag_execute_queue(); - return ERROR_OK; + if (retval == ERROR_OK) { + uint32_t up_data; + for (size_t i = 0; i < num_tx; ++i) { + up_data = buf_get_u32(hub->scratch_memory.dr_in_vals + + i * dreg_buffer_size, + 0, hub->data_register_length); + int rv = ipdbg_distribute_data_from_hub(hub, up_data); + if (rv != ERROR_OK) + retval = rv; + if (i == 0) { + /* check if xoff sent is only needed on the first transfer which + may contain the xoff of the prev down transfer. + No checks for this channel because this function is only + called for channels without enabled flow control. + */ + ipdbg_check_for_xoff(hub, tool, up_data); + } + } + } + + return retval; } static int ipdbg_polling_callback(void *priv) @@ -446,36 +574,28 @@ static int ipdbg_polling_callback(void *priv) return ret; /* transfer dn buffers to jtag-hub */ - unsigned int num_transfers = 0; - for (size_t tool = 0 ; tool < hub->max_tools ; ++tool) { + for (size_t tool = 0; tool < hub->max_tools; ++tool) { struct connection *conn = hub->connections[tool]; if (conn && conn->priv) { struct ipdbg_connection *connection = conn->priv; while (((hub->dn_xoff & BIT(tool)) == 0) && !ipdbg_fifo_is_empty(&connection->dn_fifo)) { - ret = ipdbg_jtag_transfer_byte(hub, tool, connection); + if (hub->flow_control_enabled & BIT(tool)) + ret = ipdbg_jtag_transfer_byte(hub, tool, connection); + else + ret = ipdbg_jtag_transfer_bytes(hub, tool, connection); if (ret != ERROR_OK) return ret; - ++num_transfers; } } } /* some transfers to get data from jtag-hub in case there is no dn data */ - while (num_transfers++ < hub->max_tools) { - uint32_t dn = 0; - uint32_t up = 0; - - int retval = ipdbg_shift_data(hub, dn, &up); - if (retval != ERROR_OK) - return ret; - - retval = ipdbg_distribute_data_from_hub(hub, up); - if (retval != ERROR_OK) - return ret; - } + ret = ipdbg_shift_empty_data(hub); + if (ret != ERROR_OK) + return ret; /* write from up fifos to sockets */ - for (size_t tool = 0 ; tool < hub->max_tools ; ++tool) { + for (size_t tool = 0; tool < hub->max_tools; ++tool) { struct connection *conn = hub->connections[tool]; if (conn && conn->priv) { struct ipdbg_connection *connection = conn->priv; @@ -488,6 +608,33 @@ static int ipdbg_polling_callback(void *priv) return ERROR_OK; } +static int ipdbg_get_flow_control_info_from_hub(struct ipdbg_hub *hub) +{ + uint32_t up_data; + + /* on older implementations the flow_control_enable_word is not sent to us. + so we don't know -> assume it's enabled on all channels */ + hub->flow_control_enabled = 0x7f; + + int ret = ipdbg_shift_data(hub, 0UL, &up_data); + if (ret != ERROR_OK) + return ret; + + const bool valid_up_data = up_data & hub->valid_mask; + if (valid_up_data) { + const size_t tool = (up_data >> 8) & hub->tool_mask; + /* the first valid data from hub is flow_control_enable_word */ + if (tool == hub->tool_mask) + hub->flow_control_enabled = up_data & 0x007f; + else + ipdbg_distribute_data_from_hub(hub, up_data); + } + + LOG_INFO("Flow control enabled on IPDBG JTAG Hub: 0x%02x", hub->flow_control_enabled); + + return ERROR_OK; +} + static int ipdbg_start_polling(struct ipdbg_service *service, struct connection *connection) { struct ipdbg_hub *hub = service->hub; @@ -514,6 +661,10 @@ static int ipdbg_start_polling(struct ipdbg_service *service, struct connection if (ret != ERROR_OK) return ret; + ret = ipdbg_get_flow_control_info_from_hub(hub); + if (ret != ERROR_OK) + return ret; + LOG_INFO("IPDBG start_polling"); const int time_ms = 20; @@ -596,25 +747,62 @@ static const struct service_driver ipdbg_service_driver = { .keep_client_alive_handler = NULL, }; -static int ipdbg_start(uint16_t port, struct jtag_tap *tap, uint32_t user_instruction, - uint8_t data_register_length, struct ipdbg_virtual_ir_info *virtual_ir, uint8_t tool) +static struct ipdbg_hub *ipdbg_get_hub_by_name(const char *name) { - LOG_INFO("starting ipdbg service on port %d for tool %d", port, tool); + struct ipdbg_hub *hub = NULL; + for (hub = ipdbg_first_hub; hub; hub = hub->next) { + if (strcmp(hub->name, name) == 0) + break; + } + return hub; +}; - struct ipdbg_hub *hub = ipdbg_find_hub(tap, user_instruction, virtual_ir); - if (hub) { - free(virtual_ir); - if (hub->data_register_length != data_register_length) { - LOG_DEBUG("hub must have the same data_register_length for all tools"); - return ERROR_FAIL; - } - } else { - int retval = ipdbg_create_hub(tap, user_instruction, data_register_length, virtual_ir, &hub); - if (retval != ERROR_OK) { - free(virtual_ir); - return retval; +static int ipdbg_stop_service(struct ipdbg_service *service) +{ + int retval = ipdbg_remove_service(service); + if (retval != ERROR_OK) { + LOG_ERROR("BUG: ipdbg_remove_service failed"); + return retval; + } + + char port_str_buffer[IPDBG_TCP_PORT_STR_MAX_LENGTH]; + snprintf(port_str_buffer, IPDBG_TCP_PORT_STR_MAX_LENGTH, "%u", service->port); + retval = remove_service("ipdbg", port_str_buffer); + /* The ipdbg_service structure is freed by server.c:remove_service(). + There the "priv" pointer is freed.*/ + if (retval != ERROR_OK) { + LOG_ERROR("BUG: remove_service failed"); + return retval; + } + return ERROR_OK; +} + +int ipdbg_server_free(void) +{ + int retval = ERROR_OK; + for (struct ipdbg_hub *hub = ipdbg_first_hub; hub;) { + for (uint8_t tool = 0; tool < hub->max_tools; ++tool) { + struct ipdbg_service *service = ipdbg_find_service(hub, tool); + if (service) { + int new_retval = ipdbg_stop_service(service); + if (new_retval != ERROR_OK) + retval = new_retval; + hub->active_services--; + } } + struct ipdbg_hub *next_hub = hub->next; + int new_retval = ipdbg_remove_hub(hub); + if (new_retval != ERROR_OK) + retval = new_retval; + ipdbg_free_hub(hub); + hub = next_hub; } + return retval; +} + +static int ipdbg_start(struct ipdbg_hub *hub, uint16_t port, uint8_t tool) +{ + LOG_INFO("starting ipdbg service on port %d for tool %d", port, tool); struct ipdbg_service *service = NULL; int retval = ipdbg_create_service(hub, tool, &service, port); @@ -628,81 +816,228 @@ static int ipdbg_start(uint16_t port, struct jtag_tap *tap, uint32_t user_instru char port_str_buffer[IPDBG_TCP_PORT_STR_MAX_LENGTH]; snprintf(port_str_buffer, IPDBG_TCP_PORT_STR_MAX_LENGTH, "%u", port); retval = add_service(&ipdbg_service_driver, port_str_buffer, 1, service); - if (retval == ERROR_OK) { - ipdbg_add_service(service); - if (hub->active_services == 0 && hub->active_connections == 0) - ipdbg_add_hub(hub); - hub->active_services++; - } else { - if (hub->active_services == 0 && hub->active_connections == 0) - ipdbg_free_hub(hub); + if (retval != ERROR_OK) { free(service); + return retval; + } + ipdbg_add_service(service); + hub->active_services++; + return ERROR_OK; +} + +COMMAND_HANDLER(handle_ipdbg_start_command) +{ + struct ipdbg_hub *hub = CMD_DATA; + + uint16_t port = 4242; + uint8_t tool = 1; + + if (CMD_ARGC > IPDBG_NUM_OF_START_OPTIONS) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int i = 0; i < CMD_ARGC; ++i) { + if (strcmp(CMD_ARGV[i], "-port") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u16, i, port, "port number"); + } else if (strcmp(CMD_ARGV[i], "-tool") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u8, i, tool, "tool"); + } else { + command_print(CMD, "Unknown argument: %s", CMD_ARGV[i]); + return ERROR_FAIL; + } + } + + return ipdbg_start(hub, port, tool); +} + +static int ipdbg_stop(struct ipdbg_hub *hub, uint8_t tool) +{ + struct ipdbg_service *service = ipdbg_find_service(hub, tool); + if (!service) { + LOG_ERROR("No service for hub '%s'/tool %d found", hub->name, tool); + return ERROR_FAIL; } + int retval = ipdbg_stop_service(service); + hub->active_services--; + + LOG_INFO("stopped ipdbg service for tool %d", tool); return retval; } -static int ipdbg_stop(struct jtag_tap *tap, uint32_t user_instruction, - struct ipdbg_virtual_ir_info *virtual_ir, uint8_t tool) +COMMAND_HANDLER(handle_ipdbg_stop_command) +{ + struct ipdbg_hub *hub = CMD_DATA; + + uint8_t tool = 1; + + if (CMD_ARGC > IPDBG_NUM_OF_STOP_OPTIONS) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int i = 0; i < CMD_ARGC; ++i) { + if (strcmp(CMD_ARGV[i], "-tool") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u8, i, tool, "tool"); + } else { + command_print(CMD, "Unknown argument: %s", CMD_ARGV[i]); + return ERROR_FAIL; + } + } + + return ipdbg_stop(hub, tool); +} + +static const struct command_registration ipdbg_hostserver_subcommand_handlers[] = { + { + .name = "start", + .mode = COMMAND_EXEC, + .handler = handle_ipdbg_start_command, + .help = "Starts a IPDBG Host server.", + .usage = "-tool number -port port" + }, { + .name = "stop", + .mode = COMMAND_EXEC, + .handler = handle_ipdbg_stop_command, + .help = "Stops a IPDBG Host server.", + .usage = "-tool number" + }, + COMMAND_REGISTRATION_DONE +}; + +static COMMAND_HELPER(ipdbg_config_queuing, struct ipdbg_hub *hub, unsigned int size) { - struct ipdbg_hub *hub = ipdbg_find_hub(tap, user_instruction, virtual_ir); - free(virtual_ir); if (!hub) return ERROR_FAIL; - struct ipdbg_service *service = ipdbg_find_service(hub, tool); - if (!service) + if (hub->active_connections) { + command_print(CMD, "Configuration change not allowed when hub has active connections"); return ERROR_FAIL; - - int retval = ipdbg_remove_service(service); - if (retval != ERROR_OK) { - LOG_ERROR("BUG: ipdbg_remove_service failed"); - return retval; } - char port_str_buffer[IPDBG_TCP_PORT_STR_MAX_LENGTH]; - snprintf(port_str_buffer, IPDBG_TCP_PORT_STR_MAX_LENGTH, "%u", service->port); - retval = remove_service("ipdbg", port_str_buffer); - /* The ipdbg_service structure is freed by server.c:remove_service(). - There the "priv" pointer is freed.*/ - if (retval != ERROR_OK) { - LOG_ERROR("BUG: remove_service failed"); - return retval; + if (size == 0 || size > IPDBG_SCRATCH_MEMORY_SIZE) { + command_print(CMD, "queuing size out of range! Must be 0 < size <= %d", IPDBG_SCRATCH_MEMORY_SIZE); + return ERROR_COMMAND_ARGUMENT_INVALID; } - hub->active_services--; - if (hub->active_connections == 0 && hub->active_services == 0) { - retval = ipdbg_remove_hub(hub); - if (retval != ERROR_OK) { - LOG_ERROR("BUG: ipdbg_remove_hub failed"); - return retval; + + hub->using_queue_size = size; + return ERROR_OK; +} + +COMMAND_HANDLER(handle_ipdbg_cfg_queuing_command) +{ + struct ipdbg_hub *hub = CMD_DATA; + + unsigned int size; + + if (CMD_ARGC != IPDBG_NUM_OF_QUEUE_OPTIONS) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int i = 0; i < CMD_ARGC; ++i) { + if (strcmp(CMD_ARGV[i], "-size") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(uint, i, size, "size"); + } else { + command_print(CMD, "Unknown argument: %s", CMD_ARGV[i]); + return ERROR_FAIL; } - ipdbg_free_hub(hub); } + + return CALL_COMMAND_HANDLER(ipdbg_config_queuing, hub, size); +} + +static const struct command_registration ipdbg_hub_subcommand_handlers[] = { + { + .name = "ipdbg", + .mode = COMMAND_EXEC, + .help = "IPDBG Hub commands.", + .usage = "", + .chain = ipdbg_hostserver_subcommand_handlers + }, + { + .name = "queuing", + .handler = handle_ipdbg_cfg_queuing_command, + .mode = COMMAND_ANY, + .help = "configures queuing between IPDBG Host and Hub.", + .usage = "-size size", + }, + COMMAND_REGISTRATION_DONE +}; + +static int ipdbg_register_hub_command(struct ipdbg_hub *hub, struct command_invocation *cmd) +{ + Jim_Interp *interp = CMD_CTX->interp; + + /* does this command exist? */ + Jim_Cmd *jcmd = Jim_GetCommand(interp, Jim_NewStringObj(interp, hub->name, -1), JIM_NONE); + if (jcmd) { + LOG_ERROR("cannot create Hub because a command with name '%s' already exists", hub->name); + return ERROR_FAIL; + } + + const struct command_registration obj_commands[] = { + { + .name = hub->name, + .mode = COMMAND_EXEC, + .help = "IPDBG Hub command group.", + .usage = "", + .chain = ipdbg_hub_subcommand_handlers + }, + COMMAND_REGISTRATION_DONE + }; + + return register_commands_with_data(CMD_CTX, NULL, obj_commands, hub); +} + +static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uint8_t data_register_length, + struct ipdbg_virtual_ir_info *virtual_ir, const char *name, struct command_invocation *cmd) +{ + struct ipdbg_hub *new_hub = ipdbg_allocate_hub(data_register_length, virtual_ir, name); + if (!new_hub) + return ERROR_FAIL; + + if (virtual_ir) + buf_set_u32(new_hub->scratch_memory.vir_out_val, 0, virtual_ir->length, virtual_ir->value); + new_hub->tap = tap; + new_hub->user_instruction = user_instruction; + new_hub->data_register_length = data_register_length; + new_hub->valid_mask = BIT(data_register_length - 1); + new_hub->xoff_mask = BIT(data_register_length - 2); + new_hub->tool_mask = (new_hub->xoff_mask - 1) >> 8; + new_hub->last_dn_tool = new_hub->tool_mask; + new_hub->max_tools = ipdbg_max_tools_from_data_register_length(data_register_length); + new_hub->using_queue_size = IPDBG_SCRATCH_MEMORY_SIZE; + + int retval = ipdbg_register_hub_command(new_hub, cmd); + if (retval != ERROR_OK) { + LOG_ERROR("Creating hub failed"); + ipdbg_free_hub(new_hub); + return ERROR_FAIL; + } + + ipdbg_add_hub(new_hub); + return ERROR_OK; } -COMMAND_HANDLER(handle_ipdbg_command) +COMMAND_HANDLER(handle_ipdbg_create_hub_command) { struct jtag_tap *tap = NULL; - uint16_t port = 4242; - uint8_t tool = 1; uint32_t user_instruction = 0x00; uint8_t data_register_length = IPDBG_MAX_DR_LENGTH; - bool start = true; - bool hub_configured = false; bool has_virtual_ir = false; uint32_t virtual_ir_instruction = 0x00e; uint32_t virtual_ir_length = 5; uint32_t virtual_ir_value = 0x11; struct ipdbg_virtual_ir_info *virtual_ir = NULL; + int user_num = 1; + bool hub_configured = false; - if ((CMD_ARGC < IPDBG_MIN_NUM_OF_OPTIONS) || (CMD_ARGC > IPDBG_MAX_NUM_OF_OPTIONS)) + if (CMD_ARGC < IPDBG_MIN_NUM_OF_CREATE_OPTIONS || CMD_ARGC > IPDBG_MAX_NUM_OF_CREATE_OPTIONS) return ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned int i = 0; i < CMD_ARGC; ++i) { + const char *hub_name = CMD_ARGV[0]; + + for (unsigned int i = 1; i < CMD_ARGC; ++i) { if (strcmp(CMD_ARGV[i], "-tap") == 0) { if (i + 1 >= CMD_ARGC || CMD_ARGV[i + 1][0] == '-') { - command_print(CMD, "no TAP given"); + command_print(CMD, "no TAP name given"); return ERROR_FAIL; } tap = jtag_tap_by_string(CMD_ARGV[i + 1]); @@ -711,7 +1046,7 @@ COMMAND_HANDLER(handle_ipdbg_command) return ERROR_FAIL; } ++i; - } else if (strcmp(CMD_ARGV[i], "-hub") == 0) { + } else if (strcmp(CMD_ARGV[i], "-ir") == 0) { COMMAND_PARSE_ADDITIONAL_NUMBER(u32, i, user_instruction, "ir_value to select hub"); hub_configured = true; COMMAND_PARSE_OPTIONAL_NUMBER(u8, i, data_register_length); @@ -721,25 +1056,44 @@ COMMAND_HANDLER(handle_ipdbg_command) IPDBG_MIN_DR_LENGTH, IPDBG_MAX_DR_LENGTH); return ERROR_FAIL; } + } else if (strcmp(CMD_ARGV[i], "-pld") == 0) { + ++i; + if (i >= CMD_ARGC || CMD_ARGV[i][0] == '-') + return ERROR_COMMAND_SYNTAX_ERROR; + struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[i]); + if (!device || !device->driver) { + command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[i]); + return ERROR_FAIL; + } + COMMAND_PARSE_OPTIONAL_NUMBER(int, i, user_num); + struct pld_ipdbg_hub pld_hub; + struct pld_driver *driver = device->driver; + if (!driver->get_ipdbg_hub) { + command_print(CMD, "pld driver has no ipdbg support"); + return ERROR_FAIL; + } + if (driver->get_ipdbg_hub(user_num, device, &pld_hub) != ERROR_OK) { + command_print(CMD, "unable to retrieve hub from pld driver"); + return ERROR_FAIL; + } + if (!pld_hub.tap) { + command_print(CMD, "no tap received from pld driver"); + return ERROR_FAIL; + } + hub_configured = true; + user_instruction = pld_hub.user_ir_code; + tap = pld_hub.tap; + } else if (strcmp(CMD_ARGV[i], "-vir") == 0) { COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_value); COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_length); COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_instruction); has_virtual_ir = true; - } else if (strcmp(CMD_ARGV[i], "-port") == 0) { - COMMAND_PARSE_ADDITIONAL_NUMBER(u16, i, port, "port number"); - } else if (strcmp(CMD_ARGV[i], "-tool") == 0) { - COMMAND_PARSE_ADDITIONAL_NUMBER(u8, i, tool, "tool"); - } else if (strcmp(CMD_ARGV[i], "-stop") == 0) { - start = false; - } else if (strcmp(CMD_ARGV[i], "-start") == 0) { - start = true; } else { command_print(CMD, "Unknown argument: %s", CMD_ARGV[i]); return ERROR_FAIL; } } - if (!tap) { command_print(CMD, "no valid tap selected"); return ERROR_FAIL; @@ -750,8 +1104,8 @@ COMMAND_HANDLER(handle_ipdbg_command) return ERROR_FAIL; } - if (tool >= ipdbg_max_tools_from_data_register_length(data_register_length)) { - command_print(CMD, "Tool: %d is invalid", tool); + if (ipdbg_get_hub_by_name(hub_name)) { + LOG_ERROR("IPDBG hub with name '%s' already exists", hub_name); return ERROR_FAIL; } @@ -766,20 +1120,34 @@ COMMAND_HANDLER(handle_ipdbg_command) virtual_ir->value = virtual_ir_value; } - if (start) - return ipdbg_start(port, tap, user_instruction, data_register_length, virtual_ir, tool); - else - return ipdbg_stop(tap, user_instruction, virtual_ir, tool); + if (ipdbg_find_hub(tap, user_instruction, virtual_ir)) { + LOG_ERROR("IPDBG hub for given TAP and user-instruction already exists"); + free(virtual_ir); + return ERROR_FAIL; + } + + return ipdbg_create_hub(tap, user_instruction, data_register_length, virtual_ir, hub_name, cmd); } +static const struct command_registration ipdbg_config_command_handlers[] = { + { + .name = "create-hub", + .mode = COMMAND_ANY, + .handler = handle_ipdbg_create_hub_command, + .help = "create a IPDBG Hub", + .usage = "name.ipdbghub (-tap device.tap -ir ir_value [dr_length] |" + " -pld name.pld [user]) [-vir [vir_value [length [instr_code]]]]", + }, + COMMAND_REGISTRATION_DONE +}; + static const struct command_registration ipdbg_command_handlers[] = { { .name = "ipdbg", - .handler = handle_ipdbg_command, - .mode = COMMAND_EXEC, - .help = "Starts or stops an IPDBG JTAG-Host server.", - .usage = "[-start|-stop] -tap device.tap -hub ir_value [dr_length]" - " [-port number] [-tool number] [-vir [vir_value [length [instr_code]]]]", + .mode = COMMAND_ANY, + .help = "IPDBG Hub/Host commands.", + .usage = "", + .chain = ipdbg_config_command_handlers, }, COMMAND_REGISTRATION_DONE }; diff --git a/src/server/ipdbg.h b/src/server/ipdbg.h index 6b70545845..1f4156b7ac 100644 --- a/src/server/ipdbg.h +++ b/src/server/ipdbg.h @@ -7,5 +7,6 @@ #include <helper/command.h> int ipdbg_register_commands(struct command_context *cmd_ctx); +int ipdbg_server_free(void); #endif /* OPENOCD_IPDBG_IPDBG_H */ diff --git a/src/server/rtt_server.c b/src/server/rtt_server.c index 760e3d4940..b44101c3dc 100644 --- a/src/server/rtt_server.c +++ b/src/server/rtt_server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016-2017 by Marc Schink <dev@zapb.de> @@ -25,6 +25,13 @@ struct rtt_service { unsigned int channel; + char *hello_message; +}; + +struct rtt_connection_data { + unsigned char buffer[64]; + unsigned int length; + unsigned int offset; }; static int read_callback(unsigned int channel, const uint8_t *buffer, @@ -55,7 +62,16 @@ static int rtt_new_connection(struct connection *connection) { int ret; struct rtt_service *service; + struct rtt_connection_data *data; + + data = calloc(1, sizeof(struct rtt_connection_data)); + + if (!data) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + connection->priv = data; service = connection->service->priv; LOG_DEBUG("rtt: New connection for channel %u", service->channel); @@ -65,6 +81,9 @@ static int rtt_new_connection(struct connection *connection) if (ret != ERROR_OK) return ret; + if (service->hello_message) + connection_write(connection, service->hello_message, strlen(service->hello_message)); + return ERROR_OK; } @@ -75,31 +94,53 @@ static int rtt_connection_closed(struct connection *connection) service = (struct rtt_service *)connection->service->priv; rtt_unregister_sink(service->channel, &read_callback, connection); - LOG_DEBUG("rtt: Connection for channel %u closed", service->channel); + free(connection->priv); + LOG_DEBUG("rtt: Connection for channel %u closed", service->channel); return ERROR_OK; } static int rtt_input(struct connection *connection) { - int bytes_read; - unsigned char buffer[1024]; struct rtt_service *service; - size_t length; + struct rtt_connection_data *data; - service = (struct rtt_service *)connection->service->priv; - bytes_read = connection_read(connection, buffer, sizeof(buffer)); + data = connection->priv; + service = connection->service->priv; - if (!bytes_read) - return ERROR_SERVER_REMOTE_CLOSED; - else if (bytes_read < 0) { - LOG_ERROR("error during read: %s", strerror(errno)); - return ERROR_SERVER_REMOTE_CLOSED; - } + if (!connection->input_pending) { + int bytes_read; + + bytes_read = connection_read(connection, data->buffer, sizeof(data->buffer)); - length = bytes_read; - rtt_write_channel(service->channel, buffer, &length); + if (!bytes_read) { + return ERROR_SERVER_REMOTE_CLOSED; + } else if (bytes_read < 0) { + LOG_ERROR("error during read: %s", strerror(errno)); + return ERROR_SERVER_REMOTE_CLOSED; + } + data->length = bytes_read; + data->offset = 0; + } + if (data->length > 0) { + unsigned char *ptr; + size_t length, to_write; + + ptr = data->buffer + data->offset; + length = data->length - data->offset; + to_write = length; + rtt_write_channel(service->channel, ptr, &length); + + if (length < to_write) { + data->offset += length; + connection->input_pending = true; + } else { + data->offset = 0; + data->length = 0; + connection->input_pending = false; + } + } return ERROR_OK; } @@ -117,16 +158,32 @@ COMMAND_HANDLER(handle_rtt_start_command) int ret; struct rtt_service *service; - if (CMD_ARGC != 2) + if (CMD_ARGC < 2 || CMD_ARGC > 3) return ERROR_COMMAND_SYNTAX_ERROR; - service = malloc(sizeof(struct rtt_service)); + service = calloc(1, sizeof(struct rtt_service)); - if (!service) + if (!service) { + LOG_ERROR("Out of memory"); return ERROR_FAIL; + } COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], service->channel); + if (CMD_ARGC >= 3) { + const char *hello_message = CMD_ARGV[2]; + size_t hello_length = strlen(hello_message); + + service->hello_message = malloc(hello_length + 2); + if (!service->hello_message) { + LOG_ERROR("Out of memory"); + free(service); + return ERROR_FAIL; + } + strcpy(service->hello_message, hello_message); + service->hello_message[hello_length] = '\n'; + service->hello_message[hello_length + 1] = '\0'; + } ret = add_service(&rtt_service_driver, CMD_ARGV[0], CONNECTION_LIMIT_UNLIMITED, service); if (ret != ERROR_OK) { @@ -153,7 +210,7 @@ static const struct command_registration rtt_server_subcommand_handlers[] = { .handler = handle_rtt_start_command, .mode = COMMAND_ANY, .help = "Start a RTT server", - .usage = "<port> <channel>" + .usage = "<port> <channel> [message]" }, { .name = "stop", diff --git a/src/server/server.c b/src/server/server.c index eeaa3d750e..0649ec942b 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -23,6 +23,7 @@ #include "openocd.h" #include "tcl_server.h" #include "telnet_server.h" +#include "ipdbg.h" #include <signal.h> @@ -473,7 +474,7 @@ int server_loop(struct command_context *command_context) tv.tv_usec = 0; retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv); } else { - /* Every 100ms, can be changed with "poll_period" command */ + /* Timeout socket_select() when a target timer expires or every polling_period */ int timeout_ms = next_event - timeval_ms(); if (timeout_ms < 0) timeout_ms = 0; @@ -507,9 +508,12 @@ int server_loop(struct command_context *command_context) } if (retval == 0) { - /* We only execute these callbacks when there was nothing to do or we timed - *out */ - target_call_timer_callbacks_now(); + /* Execute callbacks of expired timers when + * - there was nothing to do if poll_ok was true + * - socket_select() timed out if poll_ok was false, now one or more + * timers expired or the polling period elapsed + */ + target_call_timer_callbacks(); next_event = target_timer_next_event(); process_jim_events(command_context); @@ -711,6 +715,7 @@ void server_free(void) tcl_service_free(); telnet_service_free(); jsp_service_free(); + ipdbg_server_free(); free(bindto_name); } @@ -744,6 +749,11 @@ int connection_read(struct connection *connection, void *data, int len) return read(connection->fd, data, len); } +bool openocd_is_shutdown_pending(void) +{ + return shutdown_openocd != CONTINUE_MAIN_LOOP; +} + /* tell the server we want to shut down */ COMMAND_HANDLER(handle_shutdown_command) { diff --git a/src/server/server.h b/src/server/server.h index f09988a8a0..ea1e94ec5f 100644 --- a/src/server/server.h +++ b/src/server/server.h @@ -104,6 +104,8 @@ int server_register_commands(struct command_context *context); int connection_write(struct connection *connection, const void *data, int len); int connection_read(struct connection *connection, void *data, int len); +bool openocd_is_shutdown_pending(void); + /** * Defines an extended command handler function declaration to enable * access to (and manipulation of) the server port number. @@ -116,5 +118,6 @@ COMMAND_HELPER(server_port_command, unsigned short *out); #define ERROR_SERVER_REMOTE_CLOSED (-400) #define ERROR_CONNECTION_REJECTED (-401) +#define ERROR_SERVER_INTERRUPTED (-402) #endif /* OPENOCD_SERVER_SERVER_H */ diff --git a/src/server/startup.tcl b/src/server/startup.tcl index 1d30b1dd37..cf3eca36e6 100644 --- a/src/server/startup.tcl +++ b/src/server/startup.tcl @@ -41,3 +41,81 @@ proc _telnet_autocomplete_helper pattern { return [lsort $cmds] } + +lappend _telnet_autocomplete_skip "gdb_sync" +proc "gdb_sync" {} { + echo "DEPRECATED! use 'gdb sync', not 'gdb_sync'" + eval gdb sync +} + +lappend _telnet_autocomplete_skip "gdb_port" +proc "gdb_port" {args} { + echo "DEPRECATED! use 'gdb port', not 'gdb_port'" + eval gdb port $args +} + +lappend _telnet_autocomplete_skip "gdb_memory_map" +proc "gdb_memory_map" {state} { + echo "DEPRECATED! use 'gdb memory_map', not 'gdb_memory_map'" + eval gdb memory_map $state +} + +lappend _telnet_autocomplete_skip "gdb_flash_program" +proc "gdb_flash_program" {state} { + echo "DEPRECATED! use 'gdb flash_program', not 'gdb_flash_program'" + eval gdb flash_program $state +} + +lappend _telnet_autocomplete_skip "gdb_report_data_abort" +proc "gdb_report_data_abort" {state} { + echo "DEPRECATED! use 'gdb report_data_abort', not 'gdb_report_data_abort'" + eval gdb report_data_abort $state +} + +lappend _telnet_autocomplete_skip "gdb_report_register_access_error" +proc "gdb_report_register_access_error" {state} { + echo "DEPRECATED! use 'gdb report_register_access_error', not 'gdb_report_register_access_error'" + eval gdb report_register_access_error $state +} + +lappend _telnet_autocomplete_skip "gdb_breakpoint_override" +proc "gdb_breakpoint_override" {override} { + echo "DEPRECATED! use 'gdb breakpoint_override', not 'gdb_breakpoint_override'" + eval gdb breakpoint_override $override +} + +lappend _telnet_autocomplete_skip "gdb_target_description" +proc "gdb_target_description" {state} { + echo "DEPRECATED! use 'gdb target_description', not 'gdb_target_description'" + eval gdb target_description $state +} + +lappend _telnet_autocomplete_skip "gdb_save_tdesc" +proc "gdb_save_tdesc" {} { + echo "DEPRECATED! use 'gdb save_tdesc', not 'gdb_save_tdesc'" + eval gdb save_tdesc +} + +lappend _telnet_autocomplete_skip "tcl_port" +proc "tcl_port" {args} { + echo "DEPRECATED! use 'tcl port' not 'tcl_port'" + eval tcl port $args +} + +lappend _telnet_autocomplete_skip "tcl_notifications" +proc "tcl_notifications" {state} { + echo "DEPRECATED! use 'tcl notifications' not 'tcl_notifications'" + eval tcl notifications $state +} + +lappend _telnet_autocomplete_skip "tcl_trace" +proc "tcl_trace" {state} { + echo "DEPRECATED! use 'tcl trace' not 'tcl_trace'" + eval tcl trace $state +} + +lappend _telnet_autocomplete_skip "telnet_port" +proc "telnet_port" {args} { + echo "DEPRECATED! use 'telnet port', not 'telnet_port'" + eval telnet port $args +} diff --git a/src/server/tcl_server.c b/src/server/tcl_server.c index 1793453a96..16cc55e29b 100644 --- a/src/server/tcl_server.c +++ b/src/server/tcl_server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 Øyvind Harboe * @@ -323,25 +323,25 @@ COMMAND_HANDLER(handle_tcl_trace_command) } } -static const struct command_registration tcl_command_handlers[] = { +static const struct command_registration tcl_subcommand_handlers[] = { { - .name = "tcl_port", + .name = "port", .handler = handle_tcl_port_command, .mode = COMMAND_CONFIG, .help = "Specify port on which to listen " "for incoming Tcl syntax. " - "Read help on 'gdb_port'.", + "Read help on 'gdb port'.", .usage = "[port_num]", }, { - .name = "tcl_notifications", + .name = "notifications", .handler = handle_tcl_notifications_command, .mode = COMMAND_EXEC, .help = "Target Notification output", .usage = "[on|off]", }, { - .name = "tcl_trace", + .name = "trace", .handler = handle_tcl_trace_command, .mode = COMMAND_EXEC, .help = "Target trace output", @@ -350,6 +350,17 @@ static const struct command_registration tcl_command_handlers[] = { COMMAND_REGISTRATION_DONE }; +static const struct command_registration tcl_command_handlers[] = { + { + .name = "tcl", + .mode = COMMAND_ANY, + .help = "tcl command group", + .usage = "", + .chain = tcl_subcommand_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + int tcl_register_commands(struct command_context *cmd_ctx) { tcl_port = strdup("6666"); diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c index d41cfb5316..3634a2a592 100644 --- a/src/server/telnet_server.c +++ b/src/server/telnet_server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -93,7 +93,7 @@ static int telnet_output(struct command_context *cmd_ctx, const char *line) return telnet_outputline(connection, line); } -static void telnet_log_callback(void *priv, const char *file, unsigned line, +static void telnet_log_callback(void *priv, const char *file, unsigned int line, const char *function, const char *string) { struct connection *connection = priv; @@ -570,7 +570,7 @@ static void telnet_auto_complete(struct connection *connection) struct list_head lh; }; - LIST_HEAD(matches); + OOCD_LIST_HEAD(matches); /* - user command sequence, either at line beginning * or we start over after these characters ';', '[', '{' @@ -671,7 +671,7 @@ static void telnet_auto_complete(struct connection *connection) } else if (jimcmd_is_oocd_command(jim_cmd)) { struct command *cmd = jimcmd_privdata(jim_cmd); - if (cmd && !cmd->handler && !cmd->jim_handler) { + if (cmd && !cmd->handler) { /* Initial part of a multi-word command. Ignore it! */ ignore_cmd = true; } else if (cmd && cmd->mode == COMMAND_CONFIG) { @@ -967,7 +967,6 @@ int telnet_init(char *banner) return ERROR_OK; } -/* daemon configuration command telnet_port */ COMMAND_HANDLER(handle_telnet_port_command) { return CALL_COMMAND_HANDLER(server_pipe_command, &telnet_port); @@ -978,22 +977,33 @@ COMMAND_HANDLER(handle_exit_command) return ERROR_COMMAND_CLOSE_CONNECTION; } +static const struct command_registration telnet_subcommand_handlers[] = { + { + .name = "port", + .handler = handle_telnet_port_command, + .mode = COMMAND_CONFIG, + .help = "Specify port on which to listen " + "for incoming telnet connections. " + "Read help on 'gdb port'.", + .usage = "[port_num]", + }, + COMMAND_REGISTRATION_DONE +}; + static const struct command_registration telnet_command_handlers[] = { { .name = "exit", .handler = handle_exit_command, - .mode = COMMAND_EXEC, + .mode = COMMAND_ANY, .usage = "", .help = "exit telnet session", }, { - .name = "telnet_port", - .handler = handle_telnet_port_command, + .name = "telnet", + .chain = telnet_subcommand_handlers, .mode = COMMAND_CONFIG, - .help = "Specify port on which to listen " - "for incoming telnet connections. " - "Read help on 'gdb_port'.", - .usage = "[port_num]", + .help = "telnet commands", + .usage = "", }, COMMAND_REGISTRATION_DONE }; diff --git a/src/svf/svf.c b/src/svf/svf.c index f1919a50f8..ce994686f1 100644 --- a/src/svf/svf.c +++ b/src/svf/svf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Simon Qian * @@ -22,6 +22,8 @@ #include "svf.h" #include "helper/system.h" #include <helper/time_support.h> +#include <helper/nvp.h> +#include <stdbool.h> /* SVF command */ enum svf_command { @@ -73,10 +75,10 @@ static const char *svf_trst_mode_name[4] = { }; struct svf_statemove { - tap_state_t from; - tap_state_t to; + enum tap_state from; + enum tap_state to; uint32_t num_of_moves; - tap_state_t paths[8]; + enum tap_state paths[8]; }; /* @@ -139,6 +141,9 @@ static const struct svf_statemove svf_statemoves[] = { #define XXR_TDO (1 << 1) #define XXR_MASK (1 << 2) #define XXR_SMASK (1 << 3) + +#define SVF_MAX_ADDCYCLES 255 + struct svf_xxr_para { int len; int data_mask; @@ -150,10 +155,10 @@ struct svf_xxr_para { struct svf_para { float frequency; - tap_state_t ir_end_state; - tap_state_t dr_end_state; - tap_state_t runtest_run_state; - tap_state_t runtest_end_state; + enum tap_state ir_end_state; + enum tap_state dr_end_state; + enum tap_state runtest_run_state; + enum tap_state runtest_end_state; enum trst_mode trst_mode; struct svf_xxr_para hir_para; @@ -220,6 +225,8 @@ static int svf_buffer_index, svf_buffer_size; static int svf_quiet; static int svf_nil; static int svf_ignore_error; +static bool svf_noreset; +static int svf_addcycles; /* Targeting particular tap */ static int svf_tap_is_specified; @@ -238,7 +245,7 @@ static int svf_last_printed_percentage = -1; #define SVF_BUF_LOG(_lvl, _buf, _nbits, _desc) \ svf_hexbuf_print(LOG_LVL_##_lvl, __FILE__, __LINE__, __func__, _buf, _nbits, _desc) -static void svf_hexbuf_print(int dbg_lvl, const char *file, unsigned line, +static void svf_hexbuf_print(int dbg_lvl, const char *file, unsigned int line, const char *function, const uint8_t *buf, int bit_len, const char *desc) { @@ -306,10 +313,10 @@ static void svf_free_xxd_para(struct svf_xxr_para *para) } } -int svf_add_statemove(tap_state_t state_to) +int svf_add_statemove(enum tap_state state_to) { - tap_state_t state_from = cmd_queue_cur_state; - unsigned index_var; + enum tap_state state_from = cmd_queue_cur_state; + unsigned int index_var; /* when resetting, be paranoid and ignore current state */ if (state_to == TAP_RESET) { @@ -340,19 +347,51 @@ int svf_add_statemove(tap_state_t state_to) return ERROR_FAIL; } +enum svf_cmd_param { + OPT_ADDCYCLES, + OPT_IGNORE_ERROR, + OPT_NIL, + OPT_NORESET, + OPT_PROGRESS, + OPT_QUIET, + OPT_TAP, + /* DEPRECATED */ + DEPRECATED_OPT_IGNORE_ERROR, + DEPRECATED_OPT_NIL, + DEPRECATED_OPT_PROGRESS, + DEPRECATED_OPT_QUIET, +}; + +static const struct nvp svf_cmd_opts[] = { + { .name = "-addcycles", .value = OPT_ADDCYCLES }, + { .name = "-ignore_error", .value = OPT_IGNORE_ERROR }, + { .name = "-nil", .value = OPT_NIL }, + { .name = "-noreset", .value = OPT_NORESET }, + { .name = "-progress", .value = OPT_PROGRESS }, + { .name = "-quiet", .value = OPT_QUIET }, + { .name = "-tap", .value = OPT_TAP }, + /* DEPRECATED */ + { .name = "ignore_error", .value = DEPRECATED_OPT_IGNORE_ERROR }, + { .name = "nil", .value = DEPRECATED_OPT_NIL }, + { .name = "progress", .value = DEPRECATED_OPT_PROGRESS }, + { .name = "quiet", .value = DEPRECATED_OPT_QUIET }, + { .name = NULL, .value = -1 } +}; + COMMAND_HANDLER(handle_svf_command) { #define SVF_MIN_NUM_OF_OPTIONS 1 -#define SVF_MAX_NUM_OF_OPTIONS 5 +#define SVF_MAX_NUM_OF_OPTIONS 8 int command_num = 0; int ret = ERROR_OK; int64_t time_measure_ms; int time_measure_s, time_measure_m; - /* use NULL to indicate a "plain" svf file which accounts for + /* + * use NULL to indicate a "plain" svf file which accounts for * any additional devices in the scan chain, otherwise the device * that should be affected - */ + */ struct jtag_tap *tap = NULL; if ((CMD_ARGC < SVF_MIN_NUM_OF_OPTIONS) || (CMD_ARGC > SVF_MAX_NUM_OF_OPTIONS)) @@ -363,34 +402,78 @@ COMMAND_HANDLER(handle_svf_command) svf_nil = 0; svf_progress_enabled = 0; svf_ignore_error = 0; + svf_noreset = false; + svf_addcycles = 0; + for (unsigned int i = 0; i < CMD_ARGC; i++) { - if (strcmp(CMD_ARGV[i], "-tap") == 0) { + const struct nvp *n = nvp_name2value(svf_cmd_opts, CMD_ARGV[i]); + switch (n->value) { + case OPT_ADDCYCLES: + svf_addcycles = atoi(CMD_ARGV[i + 1]); + if (svf_addcycles > SVF_MAX_ADDCYCLES) { + command_print(CMD, "addcycles: %s out of range", CMD_ARGV[i + 1]); + if (svf_fd) + fclose(svf_fd); + svf_fd = NULL; + return ERROR_COMMAND_ARGUMENT_INVALID; + } + i++; + break; + + case OPT_TAP: tap = jtag_tap_by_string(CMD_ARGV[i+1]); if (!tap) { command_print(CMD, "Tap: %s unknown", CMD_ARGV[i+1]); - return ERROR_FAIL; + if (svf_fd) + fclose(svf_fd); + svf_fd = NULL; + return ERROR_COMMAND_ARGUMENT_INVALID; } i++; - } else if ((strcmp(CMD_ARGV[i], - "quiet") == 0) || (strcmp(CMD_ARGV[i], "-quiet") == 0)) + break; + + case DEPRECATED_OPT_QUIET: + LOG_INFO("DEPRECATED flag '%s'; use '-%s'", CMD_ARGV[i], CMD_ARGV[i]); + /* fallthrough */ + case OPT_QUIET: svf_quiet = 1; - else if ((strcmp(CMD_ARGV[i], "nil") == 0) || (strcmp(CMD_ARGV[i], "-nil") == 0)) + break; + + case DEPRECATED_OPT_NIL: + LOG_INFO("DEPRECATED flag '%s'; use '-%s'", CMD_ARGV[i], CMD_ARGV[i]); + /* fallthrough */ + case OPT_NIL: svf_nil = 1; - else if ((strcmp(CMD_ARGV[i], - "progress") == 0) || (strcmp(CMD_ARGV[i], "-progress") == 0)) + break; + + case DEPRECATED_OPT_PROGRESS: + LOG_INFO("DEPRECATED flag '%s'; use '-%s'", CMD_ARGV[i], CMD_ARGV[i]); + /* fallthrough */ + case OPT_PROGRESS: svf_progress_enabled = 1; - else if ((strcmp(CMD_ARGV[i], - "ignore_error") == 0) || (strcmp(CMD_ARGV[i], "-ignore_error") == 0)) + break; + + case DEPRECATED_OPT_IGNORE_ERROR: + LOG_INFO("DEPRECATED flag '%s'; use '-%s'", CMD_ARGV[i], CMD_ARGV[i]); + /* fallthrough */ + case OPT_IGNORE_ERROR: svf_ignore_error = 1; - else { + break; + + case OPT_NORESET: + svf_noreset = true; + break; + + default: svf_fd = fopen(CMD_ARGV[i], "r"); if (!svf_fd) { int err = errno; command_print(CMD, "open(\"%s\"): %s", CMD_ARGV[i], strerror(err)); /* no need to free anything now */ return ERROR_COMMAND_SYNTAX_ERROR; - } else - LOG_USER("svf processing file: \"%s\"", CMD_ARGV[i]); + } + LOG_USER("svf processing file: \"%s\"", CMD_ARGV[i]); + break; } } @@ -424,7 +507,7 @@ COMMAND_HANDLER(handle_svf_command) memcpy(&svf_para, &svf_para_init, sizeof(svf_para)); - if (!svf_nil) { + if (!svf_nil && !svf_noreset) { /* TAP_RESET */ jtag_add_tlr(); } @@ -449,27 +532,31 @@ COMMAND_HANDLER(handle_svf_command) } /* HDR %d TDI (0) */ - if (svf_set_padding(&svf_para.hdr_para, header_dr_len, 0) != ERROR_OK) { - LOG_ERROR("failed to set data header"); - return ERROR_FAIL; + ret = svf_set_padding(&svf_para.hdr_para, header_dr_len, 0); + if (ret != ERROR_OK) { + command_print(CMD, "failed to set data header"); + goto free_all; } /* HIR %d TDI (0xFF) */ - if (svf_set_padding(&svf_para.hir_para, header_ir_len, 0xFF) != ERROR_OK) { - LOG_ERROR("failed to set instruction header"); - return ERROR_FAIL; + ret = svf_set_padding(&svf_para.hir_para, header_ir_len, 0xFF); + if (ret != ERROR_OK) { + command_print(CMD, "failed to set instruction header"); + goto free_all; } /* TDR %d TDI (0) */ - if (svf_set_padding(&svf_para.tdr_para, trailer_dr_len, 0) != ERROR_OK) { - LOG_ERROR("failed to set data trailer"); - return ERROR_FAIL; + ret = svf_set_padding(&svf_para.tdr_para, trailer_dr_len, 0); + if (ret != ERROR_OK) { + command_print(CMD, "failed to set data trailer"); + goto free_all; } /* TIR %d TDI (0xFF) */ - if (svf_set_padding(&svf_para.tir_para, trailer_ir_len, 0xFF) != ERROR_OK) { - LOG_ERROR("failed to set instruction trailer"); - return ERROR_FAIL; + ret = svf_set_padding(&svf_para.tir_para, trailer_ir_len, 0xFF); + if (ret != ERROR_OK) { + command_print(CMD, "failed to set instruction trailer"); + goto free_all; } } @@ -528,7 +615,7 @@ COMMAND_HANDLER(handle_svf_command) free_all: fclose(svf_fd); - svf_fd = 0; + svf_fd = NULL; /* free buffers */ free(svf_command_buffer); @@ -729,7 +816,7 @@ static int svf_parse_cmd_string(char *str, int len, char **argus, int *num_of_ar return ERROR_OK; } -bool svf_tap_state_is_stable(tap_state_t state) +bool svf_tap_state_is_stable(enum tap_state state) { return (state == TAP_RESET) || (state == TAP_IDLE) || (state == TAP_DRPAUSE) || (state == TAP_IRPAUSE); @@ -845,7 +932,7 @@ static int svf_check_tdo(void) index_var = svf_check_tdo_para[i].buffer_offset; len = svf_check_tdo_para[i].bit_len; if ((svf_check_tdo_para[i].enabled) - && buf_cmp_mask(&svf_tdi_buffer[index_var], &svf_tdo_buffer[index_var], + && !buf_eq_mask(&svf_tdi_buffer[index_var], &svf_tdo_buffer[index_var], &svf_mask_buffer[index_var], len)) { LOG_ERROR("tdo check error at line %d", svf_check_tdo_para[i].line_num); @@ -908,7 +995,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) uint8_t **pbuffer_tmp; struct scan_field field; /* for STATE */ - tap_state_t *path = NULL, state; + enum tap_state *path = NULL, state; /* flag padding commands skipped due to -tap command */ int padding_command_skipped = 0; @@ -1189,6 +1276,9 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) svf_para.dr_end_state); } + if (svf_addcycles) + jtag_add_clocks(svf_addcycles); + svf_buffer_index += (i + 7) >> 3; } else if (command == SIR) { /* check buffer size first, reallocate if necessary */ @@ -1408,7 +1498,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) } if (num_of_argu > 2) { /* STATE pathstate1 ... stable_state */ - path = malloc((num_of_argu - 1) * sizeof(tap_state_t)); + path = malloc((num_of_argu - 1) * sizeof(enum tap_state)); if (!path) { LOG_ERROR("not enough memory"); return ERROR_FAIL; @@ -1545,7 +1635,7 @@ static const struct command_registration svf_command_handlers[] = { .handler = handle_svf_command, .mode = COMMAND_EXEC, .help = "Runs a SVF file.", - .usage = "[-tap device.tap] <file> [quiet] [nil] [progress] [ignore_error]", + .usage = "[-tap device.tap] [-quiet] [-nil] [-progress] [-ignore_error] [-noreset] [-addcycles numcycles] file", }, COMMAND_REGISTRATION_DONE }; diff --git a/src/svf/svf.h b/src/svf/svf.h index 74f7d9ca9b..77a0e0dcf1 100644 --- a/src/svf/svf.h +++ b/src/svf/svf.h @@ -23,7 +23,7 @@ int svf_register_commands(struct command_context *cmd_ctx); * SVF specification for single-argument STATE commands (and also used * for various other state transitions). */ -int svf_add_statemove(tap_state_t goal_state); +int svf_add_statemove(enum tap_state goal_state); /** * svf_tap_state_is_stable() returns true for stable non-SHIFT states @@ -31,6 +31,6 @@ int svf_add_statemove(tap_state_t goal_state); * @param state The TAP state in question * @return true iff the state is stable and not a SHIFT state. */ -bool svf_tap_state_is_stable(tap_state_t state); +bool svf_tap_state_is_stable(enum tap_state state); #endif /* OPENOCD_SVF_SVF_H */ diff --git a/src/target/Makefile.am b/src/target/Makefile.am index 46870922af..1a76864180 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -19,7 +19,6 @@ noinst_LTLIBRARIES += %D%/libtarget.la $(ARM_MISC_SRC) \ $(AVR32_SRC) \ $(MIPS32_SRC) \ - $(NDS32_SRC) \ $(STM8_SRC) \ $(INTEL_IA32_SRC) \ $(ESIRISC_SRC) \ @@ -134,18 +133,6 @@ MIPS64_SRC = \ %D%/trace.c \ %D%/mips_ejtag.c -NDS32_SRC = \ - %D%/nds32.c \ - %D%/nds32_reg.c \ - %D%/nds32_cmd.c \ - %D%/nds32_disassembler.c \ - %D%/nds32_tlb.c \ - %D%/nds32_v2.c \ - %D%/nds32_v3_common.c \ - %D%/nds32_v3.c \ - %D%/nds32_v3m.c \ - %D%/nds32_aice.c - STM8_SRC = \ %D%/stm8.c @@ -217,6 +204,7 @@ ARC_SRC = \ %D%/image.h \ %D%/mips32.h \ %D%/mips64.h \ + %D%/mips_cpu.h \ %D%/mips_m4k.h \ %D%/mips_mips64.h \ %D%/mips_ejtag.h \ @@ -235,20 +223,7 @@ ARC_SRC = \ %D%/avr32_jtag.h \ %D%/avr32_mem.h \ %D%/avr32_regs.h \ - %D%/nds32.h \ - %D%/nds32_cmd.h \ - %D%/nds32_disassembler.h \ - %D%/nds32_edm.h \ - %D%/nds32_insn.h \ - %D%/nds32_reg.h \ - %D%/nds32_tlb.h \ - %D%/nds32_v2.h \ - %D%/nds32_v3_common.h \ - %D%/nds32_v3.h \ - %D%/nds32_v3m.h \ - %D%/nds32_aice.h \ %D%/semihosting_common.h \ - %D%/stm8.h \ %D%/lakemont.h \ %D%/x86_32_common.h \ %D%/arm_cti.h \ @@ -265,4 +240,4 @@ ARC_SRC = \ include %D%/openrisc/Makefile.am include %D%/riscv/Makefile.am include %D%/xtensa/Makefile.am -include %D%/espressif/Makefile.am \ No newline at end of file +include %D%/espressif/Makefile.am diff --git a/src/target/a64_disassembler.c b/src/target/a64_disassembler.c index 64c7c1d217..ca3d3ea7a9 100644 --- a/src/target/a64_disassembler.c +++ b/src/target/a64_disassembler.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2019 by Mete Balci * diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 20e212e2b3..101cb14408 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by David Ung * @@ -21,6 +21,7 @@ #include "arm_semihosting.h" #include "jtag/interface.h" #include "smp.h" +#include <helper/nvp.h> #include <helper/time_support.h> enum restart_mode { @@ -92,6 +93,7 @@ static int aarch64_restore_system_control_reg(struct target *target) case ARM_MODE_HYP: case ARM_MODE_UND: case ARM_MODE_SYS: + case ARM_MODE_MON: instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); break; @@ -104,7 +106,7 @@ static int aarch64_restore_system_control_reg(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg); + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg); if (retval != ERROR_OK) return retval; @@ -171,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable) case ARM_MODE_HYP: case ARM_MODE_UND: case ARM_MODE_SYS: + case ARM_MODE_MON: instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); break; @@ -181,7 +184,7 @@ static int aarch64_mmu_modify(struct target *target, int enable) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg_curr); if (target_mode != ARM_MODE_ANY) @@ -190,6 +193,20 @@ static int aarch64_mmu_modify(struct target *target, int enable) return retval; } +static int aarch64_read_prsr(struct target *target, uint32_t *prsr) +{ + struct armv8_common *armv8 = target_to_armv8(target); + int retval; + + retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_PRSR, prsr); + if (retval != ERROR_OK) + return retval; + + armv8->sticky_reset |= *prsr & PRSR_SR; + return ERROR_OK; +} + /* * Basic debug access, very low level assumes state is saved */ @@ -210,8 +227,7 @@ static int aarch64_init_debug_access(struct target *target) /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ - retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_PRSR, &dummy); + retval = aarch64_read_prsr(target, &dummy); if (retval != ERROR_OK) return retval; @@ -278,12 +294,10 @@ static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, static int aarch64_check_state_one(struct target *target, uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr) { - struct armv8_common *armv8 = target_to_armv8(target); uint32_t prsr; int retval; - retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_PRSR, &prsr); + retval = aarch64_read_prsr(target, &prsr); if (retval != ERROR_OK) return retval; @@ -503,16 +517,28 @@ static int update_halt_gdb(struct target *target, enum target_debug_reason debug static int aarch64_poll(struct target *target) { + struct armv8_common *armv8 = target_to_armv8(target); enum target_state prev_target_state; int retval = ERROR_OK; - int halted; + uint32_t prsr; - retval = aarch64_check_state_one(target, - PRSR_HALT, PRSR_HALT, &halted, NULL); + retval = aarch64_read_prsr(target, &prsr); if (retval != ERROR_OK) return retval; - if (halted) { + if (armv8->sticky_reset) { + armv8->sticky_reset = false; + if (target->state != TARGET_RESET) { + target->state = TARGET_RESET; + LOG_TARGET_INFO(target, "external reset detected"); + if (armv8->arm.core_cache) { + register_cache_invalidate(armv8->arm.core_cache); + register_cache_invalidate(armv8->arm.core_cache->next); + } + } + } + + if (prsr & PRSR_HALT) { prev_target_state = target->state; if (prev_target_state != TARGET_HALTED) { enum target_debug_reason debug_reason = target->debug_reason; @@ -543,8 +569,11 @@ static int aarch64_poll(struct target *target) break; } } - } else + } else if (prsr & PRSR_RESET) { + target->state = TARGET_RESET; + } else { target->state = TARGET_RUNNING; + } return retval; } @@ -560,8 +589,8 @@ static int aarch64_halt(struct target *target) return aarch64_halt_one(target, HALT_SYNC); } -static int aarch64_restore_one(struct target *target, int current, - uint64_t *address, int handle_breakpoints, int debug_execution) +static int aarch64_restore_one(struct target *target, bool current, + uint64_t *address, bool handle_breakpoints, bool debug_execution) { struct armv8_common *armv8 = target_to_armv8(target); struct arm *arm = &armv8->arm; @@ -573,7 +602,7 @@ static int aarch64_restore_one(struct target *target, int current, if (!debug_execution) target_free_all_working_areas(target); - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ resume_pc = buf_get_u64(arm->pc->value, 0, 64); if (!current) resume_pc = *address; @@ -588,7 +617,7 @@ static int aarch64_restore_one(struct target *target, int current, resume_pc &= 0xFFFFFFFC; break; case ARM_STATE_AARCH64: - resume_pc &= 0xFFFFFFFFFFFFFFFC; + resume_pc &= 0xFFFFFFFFFFFFFFFCULL; break; case ARM_STATE_THUMB: case ARM_STATE_THUMB_EE: @@ -660,8 +689,7 @@ static int aarch64_prepare_restart_one(struct target *target) if (retval == ERROR_OK) { /* clear sticky bits in PRSR, SDR is now 0 */ - retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_PRSR, &tmp); + retval = aarch64_read_prsr(target, &tmp); } return retval; @@ -725,7 +753,8 @@ static int aarch64_restart_one(struct target *target, enum restart_mode mode) /* * prepare all but the current target for restart */ -static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoints, struct target **p_first) +static int aarch64_prep_restart_smp(struct target *target, + bool handle_breakpoints, struct target **p_first) { int retval = ERROR_OK; struct target_list *head; @@ -744,7 +773,8 @@ static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoint continue; /* resume at current address, not in step mode */ - retval = aarch64_restore_one(curr, 1, &address, handle_breakpoints, 0); + retval = aarch64_restore_one(curr, true, &address, handle_breakpoints, + false); if (retval == ERROR_OK) retval = aarch64_prepare_restart_one(curr); if (retval != ERROR_OK) { @@ -771,7 +801,7 @@ static int aarch64_step_restart_smp(struct target *target) LOG_DEBUG("%s", target_name(target)); - retval = aarch64_prep_restart_smp(target, 0, &first); + retval = aarch64_prep_restart_smp(target, false, &first); if (retval != ERROR_OK) return retval; @@ -836,8 +866,8 @@ static int aarch64_step_restart_smp(struct target *target) return retval; } -static int aarch64_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int aarch64_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { int retval = 0; uint64_t addr = address; @@ -845,8 +875,10 @@ static int aarch64_resume(struct target *target, int current, struct armv8_common *armv8 = target_to_armv8(target); armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME; - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; + } /* * If this target is part of a SMP group, prepare the others @@ -1040,6 +1072,7 @@ static int aarch64_post_debug_entry(struct target *target) case ARM_MODE_HYP: case ARM_MODE_UND: case ARM_MODE_SYS: + case ARM_MODE_MON: instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0); break; @@ -1052,23 +1085,26 @@ static int aarch64_post_debug_entry(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg); + retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg); if (retval != ERROR_OK) return retval; if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY); - LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg); + LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg); aarch64->system_control_reg_curr = aarch64->system_control_reg; if (armv8->armv8_mmu.armv8_cache.info == -1) { armv8_identify_cache(armv8); armv8_read_mpidr(armv8); } - - armv8->armv8_mmu.mmu_enabled = + if (armv8->is_armv8r) { + armv8->armv8_mmu.mmu_enabled = 0; + } else { + armv8->armv8_mmu.mmu_enabled = (aarch64->system_control_reg & 0x1U) ? 1 : 0; + } armv8->armv8_mmu.armv8_cache.d_u_cache_enabled = (aarch64->system_control_reg & 0x4U) ? 1 : 0; armv8->armv8_mmu.armv8_cache.i_cache_enabled = @@ -1079,19 +1115,20 @@ static int aarch64_post_debug_entry(struct target *target) /* * single-step a target */ -static int aarch64_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int aarch64_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { struct armv8_common *armv8 = target_to_armv8(target); struct aarch64_common *aarch64 = target_to_aarch64(target); int saved_retval = ERROR_OK; + int poll_retval; int retval; uint32_t edecr; armv8->last_run_control_op = ARMV8_RUNCONTROL_STEP; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1112,7 +1149,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres if (retval != ERROR_OK) return retval; - if (target->smp && (current == 1)) { + if (target->smp && current) { /* * isolate current target so that it doesn't get resumed * together with the others @@ -1129,7 +1166,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres } /* all other targets running, restore and restart the current target */ - retval = aarch64_restore_one(target, current, &address, 0, 0); + retval = aarch64_restore_one(target, current, &address, false, false); if (retval == ERROR_OK) retval = aarch64_restart_one(target, RESTART_LAZY); @@ -1167,6 +1204,8 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres if (retval == ERROR_TARGET_TIMEOUT) saved_retval = aarch64_halt_one(target, HALT_SYNC); + poll_retval = aarch64_poll(target); + /* restore EDECR */ retval = mem_ap_write_atomic_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_EDECR, edecr); @@ -1183,6 +1222,9 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres if (saved_retval != ERROR_OK) return saved_retval; + if (poll_retval != ERROR_OK) + return poll_retval; + return ERROR_OK; } @@ -1245,7 +1287,7 @@ static int aarch64_set_breakpoint(struct target *target, | (byte_addr_select << 5) | (3 << 1) | 1; brp_list[brp_i].used = 1; - brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC; + brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL; brp_list[brp_i].control = control; bpt_value = brp_list[brp_i].value; @@ -1297,28 +1339,28 @@ static int aarch64_set_breakpoint(struct target *target, buf_set_u32(code, 0, 32, opcode); retval = target_read_memory(target, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; armv8_cache_d_inner_flush_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); retval = target_write_memory(target, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length, 1, code); if (retval != ERROR_OK) return retval; armv8_cache_d_inner_flush_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); armv8_cache_i_inner_inval_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); breakpoint->is_set = true; @@ -1450,7 +1492,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin | (iva_byte_addr_select << 5) | (3 << 1) | 1; brp_list[brp_2].used = 1; - brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC; + brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL; brp_list[brp_2].control = control_iva; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn, @@ -1574,29 +1616,29 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br /* restore original instruction (kept in target endianness) */ armv8_cache_d_inner_flush_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); if (breakpoint->length == 4) { retval = target_write_memory(target, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, 4, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; } else { retval = target_write_memory(target, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, 2, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; } armv8_cache_d_inner_flush_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); armv8_cache_i_inner_inval_virt(armv8, - breakpoint->address & 0xFFFFFFFFFFFFFFFE, + breakpoint->address & 0xFFFFFFFFFFFFFFFEULL, breakpoint->length); } breakpoint->is_set = false; @@ -1837,7 +1879,7 @@ static int aarch64_remove_watchpoint(struct target *target, * find out which watchpoint hits * get exception address and compare the address to watchpoints */ -int aarch64_hit_watchpoint(struct target *target, +static int aarch64_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) { if (target->debug_reason != DBG_REASON_WATCHPOINT) @@ -1968,7 +2010,7 @@ static int aarch64_assert_reset(struct target *target) } /* registers are now invalid */ - if (target_was_examined(target)) { + if (armv8->arm.core_cache) { register_cache_invalidate(armv8->arm.core_cache); register_cache_invalidate(armv8->arm.core_cache->next); } @@ -2035,6 +2077,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target, struct arm *arm = &armv8->arm; int retval; + if (size > 4 && arm->core_state != ARM_STATE_AARCH64) { + LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state"); + return ERROR_FAIL; + } + armv8_reg_current(arm, 1)->dirty = true; /* change DCC to normal mode if necessary */ @@ -2047,22 +2094,32 @@ static int aarch64_write_cpu_memory_slow(struct target *target, } while (count) { - uint32_t data, opcode; + uint32_t opcode; + uint64_t data; - /* write the data to store into DTRRX */ + /* write the data to store into DTRRX (and DTRTX for 64-bit) */ if (size == 1) data = *buffer; else if (size == 2) data = target_buffer_get_u16(target, buffer); - else + else if (size == 4) data = target_buffer_get_u32(target, buffer); + else + data = target_buffer_get_u64(target, buffer); + retval = mem_ap_write_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DTRRX, data); + armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data); + if (retval == ERROR_OK && size > 4) + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32)); if (retval != ERROR_OK) return retval; if (arm->core_state == ARM_STATE_AARCH64) - retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1)); + if (size <= 4) + retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1)); + else + retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1)); else retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0)); if (retval != ERROR_OK) @@ -2072,8 +2129,11 @@ static int aarch64_write_cpu_memory_slow(struct target *target, opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP); else if (size == 2) opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP); - else + else if (size == 4) opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP); + else + opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP); + retval = dpm->instr_execute(dpm, opcode); if (retval != ERROR_OK) return retval; @@ -2131,7 +2191,7 @@ static int aarch64_write_cpu_memory(struct target *target, uint32_t dscr; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2214,6 +2274,11 @@ static int aarch64_read_cpu_memory_slow(struct target *target, struct arm *arm = &armv8->arm; int retval; + if (size > 4 && arm->core_state != ARM_STATE_AARCH64) { + LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state"); + return ERROR_FAIL; + } + armv8_reg_current(arm, 1)->dirty = true; /* change DCC to normal mode (if necessary) */ @@ -2226,36 +2291,56 @@ static int aarch64_read_cpu_memory_slow(struct target *target, } while (count) { - uint32_t opcode, data; + uint32_t opcode; + uint32_t lower; + uint32_t higher; + uint64_t data; if (size == 1) opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP); else if (size == 2) opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP); - else + else if (size == 4) opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP); + else + opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP); + retval = dpm->instr_execute(dpm, opcode); if (retval != ERROR_OK) return retval; if (arm->core_state == ARM_STATE_AARCH64) - retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1)); + if (size <= 4) + retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1)); + else + retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1)); else retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0)); if (retval != ERROR_OK) return retval; retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DTRTX, &data); + armv8->debug_base + CPUV8_DBG_DTRTX, &lower); + if (retval == ERROR_OK) { + if (size > 4) + retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_DTRRX, &higher); + else + higher = 0; + } if (retval != ERROR_OK) return retval; + data = (uint64_t)lower | (uint64_t)higher << 32; + if (size == 1) *buffer = (uint8_t)data; else if (size == 2) target_buffer_set_u16(target, buffer, (uint16_t)data); + else if (size == 4) + target_buffer_set_u32(target, buffer, (uint32_t)data); else - target_buffer_set_u32(target, buffer, data); + target_buffer_set_u64(target, buffer, data); /* Advance */ buffer += size; @@ -2349,7 +2434,7 @@ static int aarch64_read_cpu_memory(struct target *target, address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2546,23 +2631,20 @@ static int aarch64_examine_first(struct target *target) if (!pc) return ERROR_FAIL; - if (armv8->debug_ap) { - dap_put_ap(armv8->debug_ap); - armv8->debug_ap = NULL; - } - - if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) { - /* Search for the APB-AB */ - retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap); - if (retval != ERROR_OK) { - LOG_ERROR("Could not find APB-AP for debug access"); - return retval; - } - } else { - armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num); - if (!armv8->debug_ap) { - LOG_ERROR("Cannot get AP"); - return ERROR_FAIL; + if (!armv8->debug_ap) { + if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) { + /* Search for the APB-AB */ + retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap); + if (retval != ERROR_OK) { + LOG_ERROR("Could not find APB-AP for debug access"); + return retval; + } + } else { + armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num); + if (!armv8->debug_ap) { + LOG_ERROR("Cannot get AP"); + return ERROR_FAIL; + } } } @@ -2692,6 +2774,9 @@ static int aarch64_examine(struct target *target) if (retval == ERROR_OK) retval = aarch64_init_debug_access(target); + if (retval == ERROR_OK) + retval = aarch64_poll(target); + return retval; } @@ -2729,7 +2814,26 @@ static int aarch64_init_arch_info(struct target *target, return ERROR_OK; } -static int aarch64_target_create(struct target *target, Jim_Interp *interp) +static int armv8r_target_create(struct target *target) +{ + struct aarch64_private_config *pc = target->private_config; + struct aarch64_common *aarch64; + + if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK) + return ERROR_FAIL; + + aarch64 = calloc(1, sizeof(struct aarch64_common)); + if (!aarch64) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + aarch64->armv8_common.is_armv8r = true; + + return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap); +} + +static int aarch64_target_create(struct target *target) { struct aarch64_private_config *pc = target->private_config; struct aarch64_common *aarch64; @@ -2743,6 +2847,8 @@ static int aarch64_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; } + aarch64->armv8_common.is_armv8r = false; + return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap); } @@ -2751,6 +2857,14 @@ static void aarch64_deinit_target(struct target *target) struct aarch64_common *aarch64 = target_to_aarch64(target); struct armv8_common *armv8 = &aarch64->armv8_common; struct arm_dpm *dpm = &armv8->dpm; + uint64_t address; + + if (target->state == TARGET_HALTED) { + // Restore the previous state of the target (gp registers, MMU, caches, etc) + int retval = aarch64_restore_one(target, true, &address, false, false); + if (retval != ERROR_OK) + LOG_TARGET_ERROR(target, "Failed to restore target state"); + } if (armv8->debug_ap) dap_put_ap(armv8->debug_ap); @@ -2765,12 +2879,16 @@ static void aarch64_deinit_target(struct target *target) static int aarch64_mmu(struct target *target, int *enabled) { + struct aarch64_common *aarch64 = target_to_aarch64(target); + struct armv8_common *armv8 = &aarch64->armv8_common; if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target %s not halted", __func__, target_name(target)); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } - - *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled; + if (armv8->is_armv8r) + *enabled = 0; + else + *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled; return ERROR_OK; } @@ -2800,9 +2918,9 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info * pc = (struct aarch64_private_config *)target->private_config; if (!pc) { - pc = calloc(1, sizeof(struct aarch64_private_config)); - pc->adiv5_config.ap_num = DP_APSEL_INVALID; - target->private_config = pc; + pc = calloc(1, sizeof(struct aarch64_private_config)); + pc->adiv5_config.ap_num = DP_APSEL_INVALID; + target->private_config = pc; } /* @@ -2811,13 +2929,8 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info * * options, JIM_OK if it correctly parsed the topmost option * and JIM_ERR if an error occurred during parameter evaluation. * For JIM_CONTINUE, we check our own params. - * - * adiv5_jim_configure() assumes 'private_config' to point to - * 'struct adiv5_private_config'. Override 'private_config'! */ - target->private_config = &pc->adiv5_config; - e = adiv5_jim_configure(target, goi); - target->private_config = pc; + e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY); if (e != JIM_CONTINUE) return e; @@ -2837,7 +2950,7 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info * switch (n->value) { case CFG_CTI: { - if (goi->isconfigure) { + if (goi->is_configure) { Jim_Obj *o_cti; struct arm_cti *cti; e = jim_getopt_obj(goi, &o_cti); @@ -2932,15 +3045,15 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command) struct target *target = get_current_target(CMD_CTX); struct aarch64_common *aarch64 = target_to_aarch64(target); - static const struct jim_nvp nvp_maskisr_modes[] = { + static const struct nvp nvp_maskisr_modes[] = { { .name = "off", .value = AARCH64_ISRMASK_OFF }, { .name = "on", .value = AARCH64_ISRMASK_ON }, { .name = NULL, .value = -1 }, }; - const struct jim_nvp *n; + const struct nvp *n; if (CMD_ARGC > 0) { - n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]); if (!n->name) { LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; @@ -2949,59 +3062,49 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command) aarch64->isrmasking_mode = n->value; } - n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode); + n = nvp_value2name(nvp_maskisr_modes, aarch64->isrmasking_mode); command_print(CMD, "aarch64 interrupt mask %s", n->name); return ERROR_OK; } -static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(aarch64_mcrmrc_command) { - struct command *c = jim_to_command(interp); - struct command_context *context; - struct target *target; - struct arm *arm; - int retval; bool is_mcr = false; - int arg_cnt = 0; + unsigned int arg_cnt = 5; - if (!strcmp(c->name, "mcr")) { + if (!strcmp(CMD_NAME, "mcr")) { is_mcr = true; - arg_cnt = 7; - } else { arg_cnt = 6; } - context = current_command_context(interp); - assert(context); + if (arg_cnt != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - LOG_ERROR("%s: no current target", __func__); - return JIM_ERR; + command_print(CMD, "no current target"); + return ERROR_FAIL; } if (!target_was_examined(target)) { - LOG_ERROR("%s: not yet examined", target_name(target)); - return JIM_ERR; + command_print(CMD, "%s: not yet examined", target_name(target)); + return ERROR_TARGET_NOT_EXAMINED; } - arm = target_to_arm(target); + struct arm *arm = target_to_arm(target); if (!is_arm(arm)) { - LOG_ERROR("%s: not an ARM", target_name(target)); - return JIM_ERR; + command_print(CMD, "%s: not an ARM", target_name(target)); + return ERROR_FAIL; } - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + command_print(CMD, "Error: [%s] not halted", target_name(target)); return ERROR_TARGET_NOT_HALTED; - - if (arm->core_state == ARM_STATE_AARCH64) { - LOG_ERROR("%s: not 32-bit arm target", target_name(target)); - return JIM_ERR; } - if (argc != arg_cnt) { - LOG_ERROR("%s: wrong number of arguments", __func__); - return JIM_ERR; + if (arm->core_state == ARM_STATE_AARCH64) { + command_print(CMD, "%s: not 32-bit arm target", target_name(target)); + return ERROR_FAIL; } int cpnum; @@ -3010,87 +3113,62 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) uint32_t crn; uint32_t crm; uint32_t value; - long l; /* NOTE: parameter sequence matches ARM instruction set usage: * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX * The "rX" is necessarily omitted; it uses Tcl mechanisms. */ - retval = Jim_GetLong(interp, argv[1], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "coprocessor", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum); + if (cpnum & ~0xf) { + command_print(CMD, "coprocessor %d out of range", cpnum); + return ERROR_COMMAND_ARGUMENT_INVALID; } - cpnum = l; - retval = Jim_GetLong(interp, argv[2], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0x7) { - LOG_ERROR("%s: %s %d out of range", __func__, - "op1", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1); + if (op1 & ~0x7) { + command_print(CMD, "op1 %d out of range", op1); + return ERROR_COMMAND_ARGUMENT_INVALID; } - op1 = l; - retval = Jim_GetLong(interp, argv[3], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "CRn", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn); + if (crn & ~0xf) { + command_print(CMD, "CRn %d out of range", crn); + return ERROR_COMMAND_ARGUMENT_INVALID; } - crn = l; - retval = Jim_GetLong(interp, argv[4], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "CRm", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm); + if (crm & ~0xf) { + command_print(CMD, "CRm %d out of range", crm); + return ERROR_COMMAND_ARGUMENT_INVALID; } - crm = l; - retval = Jim_GetLong(interp, argv[5], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0x7) { - LOG_ERROR("%s: %s %d out of range", __func__, - "op2", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2); + if (op2 & ~0x7) { + command_print(CMD, "op2 %d out of range", op2); + return ERROR_COMMAND_ARGUMENT_INVALID; } - op2 = l; - value = 0; - - if (is_mcr == true) { - retval = Jim_GetLong(interp, argv[6], &l); - if (retval != JIM_OK) - return retval; - value = l; + if (is_mcr) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value); /* NOTE: parameters reordered! */ /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */ - retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value); + int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value); if (retval != ERROR_OK) - return JIM_ERR; + return retval; } else { + value = 0; /* NOTE: parameters reordered! */ /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */ - retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value); + int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value); if (retval != ERROR_OK) - return JIM_ERR; + return retval; - Jim_SetResult(interp, Jim_NewIntObj(interp, value)); + command_print(CMD, "0x%" PRIx32, value); } - return JIM_OK; + return ERROR_OK; } static const struct command_registration aarch64_exec_command_handlers[] = { @@ -3125,14 +3203,14 @@ static const struct command_registration aarch64_exec_command_handlers[] = { { .name = "mcr", .mode = COMMAND_EXEC, - .jim_handler = jim_mcrmrc, + .handler = aarch64_mcrmrc_command, .help = "write coprocessor register", .usage = "cpnum op1 CRn CRm op2 value", }, { .name = "mrc", .mode = COMMAND_EXEC, - .jim_handler = jim_mcrmrc, + .handler = aarch64_mcrmrc_command, .help = "read coprocessor register", .usage = "cpnum op1 CRn CRm op2", }, @@ -3205,3 +3283,39 @@ struct target_type aarch64_target = { .mmu = aarch64_mmu, .virt2phys = aarch64_virt2phys, }; + +struct target_type armv8r_target = { + .name = "armv8r", + + .poll = aarch64_poll, + .arch_state = armv8_arch_state, + + .halt = aarch64_halt, + .resume = aarch64_resume, + .step = aarch64_step, + + .assert_reset = aarch64_assert_reset, + .deassert_reset = aarch64_deassert_reset, + + /* REVISIT allow exporting VFP3 registers ... */ + .get_gdb_arch = armv8_get_gdb_arch, + .get_gdb_reg_list = armv8_get_gdb_reg_list, + + .read_memory = aarch64_read_phys_memory, + .write_memory = aarch64_write_phys_memory, + + .add_breakpoint = aarch64_add_breakpoint, + .add_context_breakpoint = aarch64_add_context_breakpoint, + .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint, + .remove_breakpoint = aarch64_remove_breakpoint, + .add_watchpoint = aarch64_add_watchpoint, + .remove_watchpoint = aarch64_remove_watchpoint, + .hit_watchpoint = aarch64_hit_watchpoint, + + .commands = aarch64_command_handlers, + .target_create = armv8r_target_create, + .target_jim_configure = aarch64_jim_configure, + .init_target = aarch64_init_target, + .deinit_target = aarch64_deinit_target, + .examine = aarch64_examine, +}; diff --git a/src/target/aarch64.h b/src/target/aarch64.h index 902a508e4f..b265e82498 100644 --- a/src/target/aarch64.h +++ b/src/target/aarch64.h @@ -9,7 +9,7 @@ #include "armv8.h" -#define AARCH64_COMMON_MAGIC 0x411fc082 +#define AARCH64_COMMON_MAGIC 0x41413634U #define CPUDBG_CPUID 0xD00 #define CPUDBG_CTYPR 0xD04 @@ -38,11 +38,13 @@ struct aarch64_brp { }; struct aarch64_common { - int common_magic; + unsigned int common_magic; + + struct armv8_common armv8_common; /* Context information */ - uint32_t system_control_reg; - uint32_t system_control_reg_curr; + uint64_t system_control_reg; + uint64_t system_control_reg_curr; /* Breakpoint register pairs */ int brp_num_context; @@ -55,8 +57,6 @@ struct aarch64_common { int wp_num_available; struct aarch64_brp *wp_list; - struct armv8_common armv8_common; - enum aarch64_isrmasking_mode isrmasking_mode; }; diff --git a/src/target/adi_v5_dapdirect.c b/src/target/adi_v5_dapdirect.c index dadc8b1fce..07ea313d19 100644 --- a/src/target/adi_v5_dapdirect.c +++ b/src/target/adi_v5_dapdirect.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved @@ -58,8 +58,16 @@ static const struct command_registration dapdirect_jtag_subcommand_handlers[] = { .name = "newtap", .mode = COMMAND_CONFIG, - .jim_handler = jim_jtag_newtap, - .help = "declare a new TAP" + .handler = handle_jtag_newtap, + .help = "declare a new TAP", + .usage = "basename tap_type '-irlen' count " + "['-enable'|'-disable'] " + "['-expected_id' number] " + "['-ignore-version'] " + "['-ignore-bypass'] " + "['-ircapture' number] " + "['-ir-bypass' number] " + "['-mask' number]", }, { .name = "init", @@ -82,12 +90,18 @@ static const struct command_registration dapdirect_jtag_subcommand_handlers[] = { .name = "tapisenabled", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, + .help = "Returns a Tcl boolean (0/1) indicating whether " + "the TAP is enabled (1) or not (0).", + .usage = "tap_name", }, { .name = "tapenable", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_tap_enabler, + .handler = handle_jtag_tap_enabler, + .help = "Try to enable the specified TAP using the " + "'tap-enable' TAP event.", + .usage = "tap_name", }, { .name = "tapdisable", @@ -104,7 +118,8 @@ static const struct command_registration dapdirect_jtag_subcommand_handlers[] = { .name = "cget", .mode = COMMAND_EXEC, - .jim_handler = jim_jtag_configure, + .handler = handle_jtag_configure, + .usage = "", }, { .name = "names", @@ -135,8 +150,16 @@ static const struct command_registration dapdirect_swd_subcommand_handlers[] = { { .name = "newdap", .mode = COMMAND_CONFIG, - .jim_handler = jim_jtag_newtap, + .handler = handle_jtag_newtap, .help = "declare a new SWD DAP", + .usage = "basename dap_type ['-irlen' count] " + "['-enable'|'-disable'] " + "['-expected_id' number] " + "['-ignore-version'] " + "['-ignore-bypass'] " + "['-ircapture' number] " + "['-ir-bypass' number] " + "['-mask' number]", }, COMMAND_REGISTRATION_DONE }; @@ -184,13 +207,13 @@ static int dapdirect_init(struct command_context *ctx) } static struct transport dapdirect_jtag_transport = { - .name = "dapdirect_jtag", + .id = TRANSPORT_DAPDIRECT_JTAG, .select = dapdirect_jtag_select, .init = dapdirect_init, }; static struct transport dapdirect_swd_transport = { - .name = "dapdirect_swd", + .id = TRANSPORT_DAPDIRECT_SWD, .select = dapdirect_swd_select, .init = dapdirect_init, }; diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index a70fad3689..c9ed5b948b 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin @@ -350,20 +350,28 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap, { uint8_t out_value_buf[4]; int retval; - uint64_t sel = (reg_addr >> 4) & 0xf; + uint64_t sel = (reg_addr >> 4) & DP_SELECT_DPBANK; /* No need to change SELECT or RDBUFF as they are not banked */ - if (instr == JTAG_DP_DPACC && reg_addr != DP_SELECT && reg_addr != DP_RDBUFF && - sel != (dap->select & 0xf)) { - if (dap->select != DP_SELECT_INVALID) - sel |= dap->select & ~0xfull; - dap->select = sel; - LOG_DEBUG("DP BANKSEL: %x", (uint32_t)sel); + if (instr == JTAG_DP_DPACC && reg_addr != DP_SELECT && reg_addr != DP_RDBUFF + && (!dap->select_valid || sel != (dap->select & DP_SELECT_DPBANK))) { + /* Use the AP part of dap->select regardless of dap->select_valid: + * if !dap->select_valid + * dap->select contains a speculative value likely going to be used + * in the following swd_queue_ap_bankselect() */ + sel |= dap->select & SELECT_AP_MASK; + + LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, (uint32_t)sel); + buf_set_u32(out_value_buf, 0, 32, (uint32_t)sel); + retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_SELECT, DPAP_WRITE, out_value_buf, NULL, 0, NULL); if (retval != ERROR_OK) return retval; + + dap->select = sel; + dap->select_valid = true; } buf_set_u32(out_value_buf, 0, 32, outvalue); @@ -423,7 +431,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) struct dap_cmd *el, *tmp, *prev = NULL; int found_wait = 0; int64_t time_now; - LIST_HEAD(replay_list); + OOCD_LIST_HEAD(replay_list); /* make sure all queued transactions are complete */ retval = jtag_execute_queue(); @@ -520,7 +528,10 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) /* timeout happened */ if (tmp->ack == JTAG_ACK_WAIT) { LOG_ERROR("Timeout during WAIT recovery"); - dap->select = DP_SELECT_INVALID; + dap->select_valid = false; + dap->select1_valid = false; + /* Keep dap->select unchanged, the same AP and AP bank + * is likely going to be used further */ jtag_ap_q_abort(dap, NULL); /* clear the sticky overrun condition */ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC, @@ -566,15 +577,21 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) /* restore SELECT register first */ if (!list_empty(&replay_list)) { el = list_first_entry(&replay_list, struct dap_cmd, lh); + + uint8_t out_value_buf[4]; + buf_set_u32(out_value_buf, 0, 32, (uint32_t)(el->dp_select)); + tmp = dap_cmd_new(dap, JTAG_DP_DPACC, - DP_SELECT, DPAP_WRITE, (uint8_t *)&el->dp_select, NULL, 0); + DP_SELECT, DPAP_WRITE, out_value_buf, NULL, 0); if (!tmp) { retval = ERROR_JTAG_DEVICE_ERROR; goto done; } list_add(&tmp->lh, &replay_list); - dap->select = DP_SELECT_INVALID; + /* TODO: ADIv6 DP SELECT1 handling */ + + dap->select_valid = false; } list_for_each_entry_safe(el, tmp, &replay_list, lh) { @@ -609,7 +626,10 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) if (retval == ERROR_OK) { if (el->ack == JTAG_ACK_WAIT) { LOG_ERROR("Timeout during WAIT recovery"); - dap->select = DP_SELECT_INVALID; + dap->select_valid = false; + dap->select1_valid = false; + /* Keep dap->select unchanged, the same AP and AP bank + * is likely going to be used further */ jtag_ap_q_abort(dap, NULL); /* clear the sticky overrun condition */ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC, @@ -716,7 +736,7 @@ static int jtag_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq) return retval; } -static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg, +static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data) { int retval = jtag_limit_queue_size(dap); @@ -729,7 +749,7 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg, return retval; } -static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg, +static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data) { int retval = jtag_limit_queue_size(dap); @@ -742,44 +762,63 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg, return retval; } -/** Select the AP register bank matching bits 7:4 of reg. */ -static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg) +/** Select the AP register bank */ +static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned int reg) { int retval; struct adiv5_dap *dap = ap->dap; uint64_t sel; - if (is_adiv6(dap)) { + if (is_adiv6(dap)) sel = ap->ap_num | (reg & 0x00000FF0); - if (sel == (dap->select & ~0xfull)) - return ERROR_OK; + else + sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK); - if (dap->select != DP_SELECT_INVALID) - sel |= dap->select & 0xf; - dap->select = sel; - LOG_DEBUG("AP BANKSEL: %" PRIx64, sel); + uint64_t sel_diff = (sel ^ dap->select) & SELECT_AP_MASK; + + bool set_select = !dap->select_valid || (sel_diff & 0xffffffffull); + bool set_select1 = is_adiv6(dap) && dap->asize > 32 + && (!dap->select1_valid + || sel_diff & (0xffffffffull << 32)); + + if (set_select && set_select1) { + /* Prepare DP bank for DP_SELECT1 now to save one write */ + sel |= (DP_SELECT1 >> 4) & DP_SELECT_DPBANK; + } else { + /* Use the DP part of dap->select regardless of dap->select_valid: + * if !dap->select_valid + * dap->select contains a speculative value likely going to be used + * in the following swd_queue_dp_bankselect(). + * Moreover dap->select_valid should never be false here as a DP bank + * is always selected before selecting an AP bank */ + sel |= dap->select & DP_SELECT_DPBANK; + } + + if (set_select) { + LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel); retval = jtag_dp_q_write(dap, DP_SELECT, (uint32_t)sel); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + dap->select_valid = false; return retval; - - if (dap->asize > 32) - return jtag_dp_q_write(dap, DP_SELECT1, (uint32_t)(sel >> 32)); - return ERROR_OK; + } } - /* ADIv5 */ - sel = (ap->ap_num << 24) | (reg & 0x000000F0); + if (set_select1) { + LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32)); - if (sel == dap->select) - return ERROR_OK; + retval = jtag_dp_q_write(dap, DP_SELECT1, (uint32_t)(sel >> 32)); + if (retval != ERROR_OK) { + dap->select1_valid = false; + return retval; + } + } dap->select = sel; - - return jtag_dp_q_write(dap, DP_SELECT, (uint32_t)sel); + return ERROR_OK; } -static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg, +static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data) { int retval = jtag_limit_queue_size(ap->dap); @@ -801,7 +840,7 @@ static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg, return retval; } -static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg, +static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data) { int retval = jtag_limit_queue_size(ap->dap); diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index 801917e2ba..2d286136a5 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * @@ -13,7 +13,7 @@ * is a transport level interface, with "target/arm_adi_v5.[hc]" code * understanding operation semantics, shared with the JTAG transport. * - * Single-DAP support only. + * Single DAP and multidrop-SWD support. * * for details, see "ARM IHI 0031A" * ARM Debug Interface v5 Architecture Specification @@ -48,6 +48,8 @@ static bool do_sync; static struct adiv5_dap *swd_multidrop_selected_dap; +static bool swd_multidrop_in_swd_state; + static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg, uint32_t data); @@ -82,16 +84,8 @@ static void swd_clear_sticky_errors(struct adiv5_dap *dap) static int swd_run_inner(struct adiv5_dap *dap) { const struct swd_driver *swd = adiv5_dap_swd_driver(dap); - int retval; - - retval = swd->run(); - if (retval != ERROR_OK) { - /* fault response */ - dap->do_reconnect = true; - } - - return retval; + return swd->run(); } static inline int check_sync(struct adiv5_dap *dap) @@ -99,27 +93,30 @@ static inline int check_sync(struct adiv5_dap *dap) return do_sync ? swd_run_inner(dap) : ERROR_OK; } -/** Select the DP register bank matching bits 7:4 of reg. */ +/** Select the DP register bank */ static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg) { - /* Only register address 0 and 4 are banked. */ - if ((reg & 0xf) > 4) + /* Only register address 0 (ADIv6 only) and 4 are banked. */ + if (is_adiv6(dap) ? (reg & 0xf) > 4 : (reg & 0xf) != 4) return ERROR_OK; - uint64_t sel = (reg & 0x000000F0) >> 4; - if (dap->select != DP_SELECT_INVALID) - sel |= dap->select & ~0xfULL; + uint32_t sel = (reg >> 4) & DP_SELECT_DPBANK; - if (sel == dap->select) + /* ADIv6 ensures DPBANKSEL = 0 after line reset */ + if ((dap->select_valid || (is_adiv6(dap) && dap->select_dpbanksel_valid)) + && (sel == (dap->select & DP_SELECT_DPBANK))) return ERROR_OK; - dap->select = sel; + /* Use the AP part of dap->select regardless of dap->select_valid: + * if !dap->select_valid + * dap->select contains a speculative value likely going to be used + * in the following swd_queue_ap_bankselect() */ + sel |= (uint32_t)(dap->select & SELECT_AP_MASK); - int retval = swd_queue_dp_write_inner(dap, DP_SELECT, (uint32_t)sel); - if (retval != ERROR_OK) - dap->select = DP_SELECT_INVALID; + LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, sel); - return retval; + /* dap->select cache gets updated in the following call */ + return swd_queue_dp_write_inner(dap, DP_SELECT, sel); } static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg, @@ -140,31 +137,42 @@ static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg, static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg, uint32_t data) { - int retval; + int retval = ERROR_OK; const struct swd_driver *swd = adiv5_dap_swd_driver(dap); assert(swd); swd_finish_read(dap); if (reg == DP_SELECT) { - dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK); + dap->select = data | (dap->select & (0xffffffffull << 32)); swd->write_reg(swd_cmd(false, false, reg), data, 0); retval = check_sync(dap); - if (retval != ERROR_OK) - dap->select = DP_SELECT_INVALID; + dap->select_valid = (retval == ERROR_OK); + dap->select_dpbanksel_valid = dap->select_valid; return retval; } - retval = swd_queue_dp_bankselect(dap, reg); - if (retval != ERROR_OK) - return retval; + if (reg == DP_SELECT1) + dap->select = ((uint64_t)data << 32) | (dap->select & 0xffffffffull); - swd->write_reg(swd_cmd(false, false, reg), data, 0); + /* DP_ABORT write is not banked. + * Prevent writing DP_SELECT before as it would fail on locked up DP */ + if (reg != DP_ABORT) + retval = swd_queue_dp_bankselect(dap, reg); - return check_sync(dap); + if (retval == ERROR_OK) { + swd->write_reg(swd_cmd(false, false, reg), data, 0); + + retval = check_sync(dap); + } + + if (reg == DP_SELECT1) + dap->select1_valid = (retval == ERROR_OK); + + return retval; } @@ -176,7 +184,26 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr assert(dap_is_multidrop(dap)); - swd_send_sequence(dap, LINE_RESET); + /* Send JTAG_TO_DORMANT and DORMANT_TO_SWD just once + * and then use shorter LINE_RESET until communication fails */ + if (!swd_multidrop_in_swd_state) { + swd_send_sequence(dap, JTAG_TO_DORMANT); + swd_send_sequence(dap, DORMANT_TO_SWD); + } else { + swd_send_sequence(dap, LINE_RESET); + } + + /* + * Zero dap->select and set dap->select_dpbanksel_valid + * to skip the write to DP_SELECT before DPIDR read, avoiding + * the protocol error. + * Clear the other validity flags because the rest of the DP + * SELECT and SELECT1 registers is unknown after line reset. + */ + dap->select = 0; + dap->select_dpbanksel_valid = true; + dap->select_valid = false; + dap->select1_valid = false; retval = swd_queue_dp_write_inner(dap, DP_TARGETSEL, dap->multidrop_targetsel); if (retval != ERROR_OK) @@ -223,6 +250,7 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32, dap->multidrop_targetsel); swd_multidrop_selected_dap = dap; + swd_multidrop_in_swd_state = true; if (dpidr_ptr) *dpidr_ptr = dpidr; @@ -252,6 +280,7 @@ static int swd_multidrop_select(struct adiv5_dap *dap) swd_multidrop_selected_dap = NULL; if (retry > 3) { LOG_ERROR("Failed to select multidrop %s", adiv5_dap_name(dap)); + dap->do_reconnect = true; return retval; } @@ -259,6 +288,7 @@ static int swd_multidrop_select(struct adiv5_dap *dap) adiv5_dap_name(dap)); } + dap->do_reconnect = false; return retval; } @@ -270,8 +300,9 @@ static int swd_connect_multidrop(struct adiv5_dap *dap) int64_t timeout = timeval_ms() + 500; do { - swd_send_sequence(dap, JTAG_TO_DORMANT); - swd_send_sequence(dap, DORMANT_TO_SWD); + /* Do not make any assumptions about SWD state in case of reconnect */ + if (dap->do_reconnect) + swd_multidrop_in_swd_state = false; /* Clear link state, including the SELECT cache. */ dap->do_reconnect = false; @@ -282,6 +313,7 @@ static int swd_connect_multidrop(struct adiv5_dap *dap) if (retval == ERROR_OK) break; + swd_multidrop_in_swd_state = false; alive_sleep(1); } while (timeval_ms() < timeout); @@ -292,6 +324,7 @@ static int swd_connect_multidrop(struct adiv5_dap *dap) return retval; } + swd_multidrop_in_swd_state = true; LOG_INFO("SWD DPIDR 0x%08" PRIx32 ", DLPIDR 0x%08" PRIx32, dpidr, dlpidr); @@ -318,19 +351,20 @@ static int swd_connect_single(struct adiv5_dap *dap) /* The sequences to enter in SWD (JTAG_TO_SWD and DORMANT_TO_SWD) end * with a SWD line reset sequence (50 clk with SWDIO high). - * From ARM IHI 0074C ADIv6.0, chapter B4.3.3 "Connection and line reset - * sequence": - * - line reset sets DP_SELECT_DPBANK to zero; + * From ARM IHI 0031F ADIv5.2 and ARM IHI 0074C ADIv6.0, + * chapter B4.3.3 "Connection and line reset sequence": + * - DPv3 (ADIv6) only: line reset sets DP_SELECT_DPBANK to zero; * - read of DP_DPIDR takes the connection out of reset; * - write of DP_TARGETSEL keeps the connection in reset; * - other accesses return protocol error (SWDIO not driven by target). * - * Read DP_DPIDR to get out of reset. Initialize dap->select to zero to - * skip the write to DP_SELECT, avoiding the protocol error. Set again - * dap->select to DP_SELECT_INVALID because the rest of the register is - * unknown after line reset. + * dap_invalidate_cache() sets dap->select to zero and all validity + * flags to invalid. Set dap->select_dpbanksel_valid only + * to skip the write to DP_SELECT, avoiding the protocol error. + * Read DP_DPIDR to get out of reset. */ - dap->select = 0; + dap->select_dpbanksel_valid = true; + retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr); if (retval == ERROR_OK) { retval = swd_run_inner(dap); @@ -342,7 +376,6 @@ static int swd_connect_single(struct adiv5_dap *dap) dap->switch_through_dormant = !dap->switch_through_dormant; } while (timeval_ms() < timeout); - dap->select = DP_SELECT_INVALID; if (retval != ERROR_OK) { LOG_ERROR("Error connecting DP: cannot read IDR"); @@ -368,6 +401,13 @@ static int swd_connect_single(struct adiv5_dap *dap) return retval; } +static int swd_pre_connect(struct adiv5_dap *dap) +{ + swd_multidrop_in_swd_state = false; + + return ERROR_OK; +} + static int swd_connect(struct adiv5_dap *dap) { int status; @@ -445,7 +485,7 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) return check_sync(dap); } -static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, +static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data) { int retval = swd_check_reconnect(dap); @@ -459,12 +499,9 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, return swd_queue_dp_read_inner(dap, reg, data); } -static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, +static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data) { - const struct swd_driver *swd = adiv5_dap_swd_driver(dap); - assert(swd); - int retval = swd_check_reconnect(dap); if (retval != ERROR_OK) return retval; @@ -476,52 +513,58 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, return swd_queue_dp_write_inner(dap, reg, data); } -/** Select the AP register bank matching bits 7:4 of reg. */ -static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg) +/** Select the AP register bank */ +static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned int reg) { int retval; struct adiv5_dap *dap = ap->dap; uint64_t sel; - if (is_adiv6(dap)) { + if (is_adiv6(dap)) sel = ap->ap_num | (reg & 0x00000FF0); - if (sel == (dap->select & ~0xfULL)) - return ERROR_OK; - - if (dap->select != DP_SELECT_INVALID) - sel |= dap->select & 0xf; - dap->select = sel; - LOG_DEBUG("AP BANKSEL: %" PRIx64, sel); - - retval = swd_queue_dp_write(dap, DP_SELECT, (uint32_t)sel); + else + sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK); - if (retval == ERROR_OK && dap->asize > 32) - retval = swd_queue_dp_write(dap, DP_SELECT1, (uint32_t)(sel >> 32)); + uint64_t sel_diff = (sel ^ dap->select) & SELECT_AP_MASK; - if (retval != ERROR_OK) - dap->select = DP_SELECT_INVALID; + bool set_select = !dap->select_valid || (sel_diff & 0xffffffffull); + bool set_select1 = is_adiv6(dap) && dap->asize > 32 + && (!dap->select1_valid + || sel_diff & (0xffffffffull << 32)); - return retval; + if (set_select && set_select1) { + /* Prepare DP bank for DP_SELECT1 now to save one write */ + sel |= (DP_SELECT1 & 0x000000f0) >> 4; + } else { + /* Use the DP part of dap->select regardless of dap->select_valid: + * if !dap->select_valid + * dap->select contains a speculative value likely going to be used + * in the following swd_queue_dp_bankselect(). + * Moreover dap->select_valid should never be false here as a DP bank + * is always selected before selecting an AP bank */ + sel |= dap->select & DP_SELECT_DPBANK; } - /* ADIv5 */ - sel = (ap->ap_num << 24) | (reg & 0x000000F0); - if (dap->select != DP_SELECT_INVALID) - sel |= dap->select & DP_SELECT_DPBANK; + if (set_select) { + LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel); - if (sel == dap->select) - return ERROR_OK; + retval = swd_queue_dp_write(dap, DP_SELECT, (uint32_t)sel); + if (retval != ERROR_OK) + return retval; + } - dap->select = sel; + if (set_select1) { + LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32)); - retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel); - if (retval != ERROR_OK) - dap->select = DP_SELECT_INVALID; + retval = swd_queue_dp_write(dap, DP_SELECT1, (uint32_t)(sel >> 32)); + if (retval != ERROR_OK) + return retval; + } - return retval; + return ERROR_OK; } -static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, +static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data) { struct adiv5_dap *dap = ap->dap; @@ -546,7 +589,7 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, return check_sync(dap); } -static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg, +static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data) { struct adiv5_dap *dap = ap->dap; @@ -581,7 +624,13 @@ static int swd_run(struct adiv5_dap *dap) swd_finish_read(dap); - return swd_run_inner(dap); + retval = swd_run_inner(dap); + if (retval != ERROR_OK) { + /* fault response */ + dap->do_reconnect = true; + } + + return retval; } /** Put the SWJ-DP back to JTAG mode */ @@ -597,7 +646,12 @@ static void swd_quit(struct adiv5_dap *dap) done = true; if (dap_is_multidrop(dap)) { + /* Emit the switch seq to dormant state regardless the state mirrored + * in swd_multidrop_in_swd_state. Doing so ensures robust operation + * in the case the variable is out of sync. + * Sending SWD_TO_DORMANT makes no change if the DP is already dormant. */ swd->switch_seq(SWD_TO_DORMANT); + swd_multidrop_in_swd_state = false; /* Revisit! * Leaving DPs in dormant state was tested and offers some safety * against DPs mismatch in case of unintentional use of non-multidrop SWD. @@ -618,6 +672,7 @@ static void swd_quit(struct adiv5_dap *dap) } const struct dap_ops swd_dap_ops = { + .pre_connect_init = swd_pre_connect, .connect = swd_connect, .send_sequence = swd_send_sequence, .queue_dp_read = swd_queue_dp_read, @@ -639,9 +694,17 @@ static const struct command_registration swd_commands[] = { * REVISIT can we verify "just one SWD DAP" here/early? */ .name = "newdap", - .jim_handler = jim_jtag_newtap, + .handler = handle_jtag_newtap, .mode = COMMAND_CONFIG, - .help = "declare a new SWD DAP" + .help = "declare a new SWD DAP", + .usage = "basename dap_type ['-irlen' count] " + "['-enable'|'-disable'] " + "['-expected_id' number] " + "['-ignore-version'] " + "['-ignore-bypass'] " + "['-ircapture' number] " + "['-ir-bypass' number] " + "['-mask' number]", }, COMMAND_REGISTRATION_DONE }; @@ -693,7 +756,7 @@ static int swd_init(struct command_context *ctx) } static struct transport swd_transport = { - .name = "swd", + .id = TRANSPORT_SWD, .select = swd_select, .init = swd_init, }; diff --git a/src/target/algorithm.c b/src/target/algorithm.c index 4012413bc6..dee1f364b4 100644 --- a/src/target/algorithm.c +++ b/src/target/algorithm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -26,7 +26,8 @@ void destroy_mem_param(struct mem_param *param) param->value = NULL; } -void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction) +void init_reg_param(struct reg_param *param, const char *reg_name, + uint32_t size, enum param_direction direction) { param->reg_name = reg_name; param->size = size; diff --git a/src/target/algorithm.h b/src/target/algorithm.h index 25f1a66ab5..45b3fd97a5 100644 --- a/src/target/algorithm.h +++ b/src/target/algorithm.h @@ -35,8 +35,8 @@ void init_mem_param(struct mem_param *param, uint32_t address, uint32_t size, enum param_direction dir); void destroy_mem_param(struct mem_param *param); -void init_reg_param(struct reg_param *param, - char *reg_name, uint32_t size, enum param_direction dir); +void init_reg_param(struct reg_param *param, const char *reg_name, + uint32_t size, enum param_direction dir); void destroy_reg_param(struct reg_param *param); #endif /* OPENOCD_TARGET_ALGORITHM_H */ diff --git a/src/target/arc.c b/src/target/arc.c index 63de3f9301..f2482c25ef 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. * @@ -50,11 +50,18 @@ static int arc_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); +static int arc_enable_watchpoints(struct target *target); +static int arc_enable_breakpoints(struct target *target); +static int arc_unset_breakpoint(struct target *target, + struct breakpoint *breakpoint); +static int arc_set_breakpoint(struct target *target, + struct breakpoint *breakpoint); +static int arc_single_step_core(struct target *target); void arc_reg_data_type_add(struct target *target, struct arc_reg_data_type *data_type) { - LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id); + LOG_TARGET_DEBUG(target, "Adding %s reg_data_type", data_type->data_type.id); struct arc_common *arc = target_to_arc(target); assert(arc); @@ -93,11 +100,11 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first, * * @param target Target for which to reset caches states. */ -int arc_reset_caches_states(struct target *target) +static int arc_reset_caches_states(struct target *target) { struct arc_common *arc = target_to_arc(target); - LOG_DEBUG("Resetting internal variables of caches states"); + LOG_TARGET_DEBUG(target, "Resetting internal variables of caches states"); /* Reset caches states. */ arc->dcache_flushed = false; @@ -120,7 +127,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc, /* The only allowed ir_length is 4 for ARC jtag. */ if (tap->ir_length != 4) { - LOG_ERROR("ARC jtag instruction length should be equal to 4"); + LOG_TARGET_ERROR(target, "ARC jtag instruction length should be equal to 4"); return ERROR_FAIL; } @@ -139,7 +146,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc, sizeof(*std_types)); if (!std_types) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); return ERROR_FAIL; } @@ -198,7 +205,7 @@ int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg, } arc->num_regs += 1; - LOG_DEBUG( + LOG_TARGET_DEBUG(target, "added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}", arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id, arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "", @@ -220,7 +227,7 @@ static int arc_get_register(struct reg *reg) uint32_t value; if (reg->valid) { - LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32, reg->number, desc->name, target_buffer_get_u32(target, reg->value)); return ERROR_OK; } @@ -228,7 +235,7 @@ static int arc_get_register(struct reg *reg) if (desc->is_core) { /* Accessing to R61/R62 registers causes Jtag hang */ if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) { - LOG_ERROR("It is forbidden to read core registers 61 and 62."); + LOG_TARGET_ERROR(target, "It is forbidden to read core registers 61 and 62"); return ERROR_FAIL; } CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num, @@ -248,7 +255,7 @@ static int arc_get_register(struct reg *reg) reg->dirty = false; - LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32, reg->number, desc->name, value); @@ -269,12 +276,12 @@ static int arc_set_register(struct reg *reg, uint8_t *buf) /* Accessing to R61/R62 registers causes Jtag hang */ if (desc->is_core && (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62)) { - LOG_ERROR("It is forbidden to write core registers 61 and 62."); + LOG_TARGET_ERROR(target, "It is forbidden to write core registers 61 and 62"); return ERROR_FAIL; } target_buffer_set_u32(target, reg->value, value); - LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32, + LOG_TARGET_DEBUG(target, "Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32, reg->number, desc->name, value); reg->valid = true; @@ -283,7 +290,7 @@ static int arc_set_register(struct reg *reg, uint8_t *buf) return ERROR_OK; } -const struct reg_arch_type arc_reg_type = { +static const struct reg_arch_type arc_reg_type = { .get = arc_get_register, .set = arc_set_register, }; @@ -348,7 +355,7 @@ static int arc_build_reg_cache(struct target *target) struct reg *reg_list = calloc(num_regs, sizeof(*reg_list)); if (!cache || !reg_list) { - LOG_ERROR("Not enough memory"); + LOG_TARGET_ERROR(target, "Not enough memory"); goto fail; } @@ -361,14 +368,14 @@ static int arc_build_reg_cache(struct target *target) (*cache_p) = cache; if (list_empty(&arc->core_reg_descriptions)) { - LOG_ERROR("No core registers were defined"); + LOG_TARGET_ERROR(target, "No core registers were defined"); goto fail; } list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) { CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i)); - LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i, + LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i, reg_list[i].name, reg_list[i].group, reg_list[i].feature->name); @@ -376,27 +383,27 @@ static int arc_build_reg_cache(struct target *target) } if (list_empty(&arc->aux_reg_descriptions)) { - LOG_ERROR("No aux registers were defined"); + LOG_TARGET_ERROR(target, "No aux registers were defined"); goto fail; } list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) { - CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i)); + CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i)); - LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i, + LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i, reg_list[i].name, reg_list[i].group, reg_list[i].feature->name); /* PC and DEBUG are essential so we search for them. */ if (!strcmp("pc", reg_desc->name)) { if (arc->pc_index_in_cache != ULONG_MAX) { - LOG_ERROR("Double definition of PC in configuration"); + LOG_TARGET_ERROR(target, "Double definition of PC in configuration"); goto fail; } arc->pc_index_in_cache = i; } else if (!strcmp("debug", reg_desc->name)) { if (arc->debug_index_in_cache != ULONG_MAX) { - LOG_ERROR("Double definition of DEBUG in configuration"); + LOG_TARGET_ERROR(target, "Double definition of DEBUG in configuration"); goto fail; } arc->debug_index_in_cache = i; @@ -406,7 +413,7 @@ static int arc_build_reg_cache(struct target *target) if (arc->pc_index_in_cache == ULONG_MAX || arc->debug_index_in_cache == ULONG_MAX) { - LOG_ERROR("`pc' and `debug' registers must be present in target description."); + LOG_TARGET_ERROR(target, "`pc' and `debug' registers must be present in target description"); goto fail; } @@ -439,7 +446,7 @@ static int arc_build_bcr_reg_cache(struct target *target) unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs; if (!cache || !reg_list) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); goto fail; } @@ -452,17 +459,17 @@ static int arc_build_bcr_reg_cache(struct target *target) (*cache_p) = cache; if (list_empty(&arc->bcr_reg_descriptions)) { - LOG_ERROR("No BCR registers are defined"); + LOG_TARGET_ERROR(target, "No BCR registers are defined"); goto fail; } list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) { - CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, gdb_regnum)); + CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, gdb_regnum)); /* BCRs always semantically, they are just read-as-zero, if there is * not real register. */ reg_list[i].exist = true; - LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i, + LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i, reg_list[i].name, reg_list[i].group, reg_list[i].feature->name); i += 1; @@ -494,7 +501,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[], *reg_list = calloc(*reg_list_size, sizeof(struct reg *)); if (!*reg_list) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); return ERROR_FAIL; } @@ -509,18 +516,18 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[], unsigned long i = 0; struct reg_cache *reg_cache = target->reg_cache; while (reg_cache) { - for (unsigned j = 0; j < reg_cache->num_regs; j++, i++) + for (unsigned int j = 0; j < reg_cache->num_regs; j++, i++) (*reg_list)[i] = ®_cache->reg_list[j]; reg_cache = reg_cache->next; } assert(i == arc->num_regs); - LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size); + LOG_TARGET_DEBUG(target, "REG_CLASS_ALL: number of regs=%i", *reg_list_size); } else { unsigned long i = 0; unsigned long gdb_reg_number = 0; struct reg_cache *reg_cache = target->reg_cache; while (reg_cache) { - for (unsigned j = 0; + for (unsigned int j = 0; j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg; j++) { if (reg_cache->reg_list[j].exist) { @@ -532,7 +539,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[], reg_cache = reg_cache->next; } *reg_list_size = i; - LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size); + LOG_TARGET_DEBUG(target, "REG_CLASS_GENERAL: number of regs=%i", *reg_list_size); } return ERROR_OK; @@ -544,13 +551,13 @@ int arc_reg_get_field(struct target *target, const char *reg_name, { struct reg_data_type_struct_field *field; - LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name); + LOG_TARGET_DEBUG(target, "getting register field (reg_name=%s, field_name=%s)", reg_name, field_name); /* Get register */ struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true); if (!reg) { - LOG_ERROR("Requested register `%s' doesn't exist.", reg_name); + LOG_TARGET_ERROR(target, "Requested register `%s' doesn't exist", reg_name); return ERROR_ARC_REGISTER_NOT_FOUND; } @@ -590,7 +597,7 @@ int arc_reg_get_field(struct target *target, const char *reg_name, static int arc_get_register_value(struct target *target, const char *reg_name, uint32_t *value_ptr) { - LOG_DEBUG("reg_name=%s", reg_name); + LOG_TARGET_DEBUG(target, "reg_name=%s", reg_name); struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true); @@ -608,10 +615,10 @@ static int arc_get_register_value(struct target *target, const char *reg_name, static int arc_set_register_value(struct target *target, const char *reg_name, uint32_t value) { - LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value); + LOG_TARGET_DEBUG(target, "reg_name=%s value=0x%08" PRIx32, reg_name, value); if (!(target && reg_name)) { - LOG_ERROR("Arguments cannot be NULL."); + LOG_TARGET_ERROR(target, "Arguments cannot be NULL"); return ERROR_FAIL; } @@ -648,7 +655,7 @@ static int arc_configure_dccm(struct target *target) if (dccm_build_size0 == 0xF) dccm_size <<= dccm_build_size1; arc->dccm_end = arc->dccm_start + dccm_size; - LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32, arc->dccm_start, arc->dccm_end); } @@ -680,7 +687,7 @@ static int arc_configure_iccm(struct target *target) /* iccm0 start is located in highest 4 bits of aux_iccm */ arc->iccm0_start = aux_iccm & 0xF0000000; arc->iccm0_end = arc->iccm0_start + iccm0_size; - LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32, arc->iccm0_start, arc->iccm0_end); } @@ -700,7 +707,7 @@ static int arc_configure_iccm(struct target *target) iccm1_size <<= iccm_build_size11; arc->iccm1_start = aux_iccm & 0x0F000000; arc->iccm1_end = arc->iccm1_start + iccm1_size; - LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32, arc->iccm1_start, arc->iccm1_end); } return ERROR_OK; @@ -709,17 +716,17 @@ static int arc_configure_iccm(struct target *target) /* Configure some core features, depending on BCRs. */ static int arc_configure(struct target *target) { - LOG_DEBUG("Configuring ARC ICCM and DCCM"); + LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM"); /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */ - if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) && - arc_reg_get_by_name(target->reg_cache, "aux_dccm", true)) - CHECK_RETVAL(arc_configure_dccm(target)); + if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) + && arc_reg_get_by_name(target->reg_cache, "aux_dccm", true)) + CHECK_RETVAL(arc_configure_dccm(target)); /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */ - if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) && - arc_reg_get_by_name(target->reg_cache, "aux_iccm", true)) - CHECK_RETVAL(arc_configure_iccm(target)); + if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) + && arc_reg_get_by_name(target->reg_cache, "aux_iccm", true)) + CHECK_RETVAL(arc_configure_iccm(target)); return ERROR_OK; } @@ -748,24 +755,47 @@ static int arc_examine(struct target *target) return ERROR_OK; } +static int arc_exit_debug(struct target *target) +{ + uint32_t value; + struct arc_common *arc = target_to_arc(target); + + /* Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally. */ + CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value)); + value |= SET_CORE_FORCE_HALT; /* set the HALT bit */ + CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value)); + alive_sleep(1); + + target->state = TARGET_HALTED; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); + + if (debug_level >= LOG_LVL_DEBUG) { + LOG_TARGET_DEBUG(target, "core stopped (halted) debug-reg: 0x%08" PRIx32, value); + CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value)); + LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value); + } + + return ERROR_OK; +} + static int arc_halt(struct target *target) { uint32_t value, irq_state; struct arc_common *arc = target_to_arc(target); - LOG_DEBUG("target->state: %s", target_state_name(target)); + LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target)); if (target->state == TARGET_HALTED) { - LOG_DEBUG("target was already halted"); + LOG_TARGET_DEBUG(target, "target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - LOG_WARNING("target was in unknown state when halt was requested"); + LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested"); if (target->state == TARGET_RESET) { if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { - LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); + LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; } else { target->debug_reason = DBG_REASON_DBGRQ; @@ -795,9 +825,9 @@ static int arc_halt(struct target *target) /* some more debug information */ if (debug_level >= LOG_LVL_DEBUG) { - LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value); + LOG_TARGET_DEBUG(target, "core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value); CHECK_RETVAL(arc_get_register_value(target, "status32", &value)); - LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value); + LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value); } return ERROR_OK; @@ -816,7 +846,7 @@ static int arc_save_context(struct target *target) struct arc_common *arc = target_to_arc(target); struct reg *reg_list = arc->core_and_aux_cache->reg_list; - LOG_DEBUG("Saving aux and core registers values"); + LOG_TARGET_DEBUG(target, "Saving aux and core registers values"); assert(reg_list); /* It is assumed that there is at least one AUX register in the list, for @@ -835,7 +865,7 @@ static int arc_save_context(struct target *target) unsigned int aux_cnt = 0; if (!core_values || !core_addrs || !aux_values || !aux_addrs) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); retval = ERROR_FAIL; goto exit; } @@ -846,28 +876,24 @@ static int arc_save_context(struct target *target) memset(aux_addrs, 0xff, aux_regs_size); for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) { - struct reg *reg = &(reg_list[i]); + struct reg *reg = reg_list + i; struct arc_reg_desc *arc_reg = reg->arch_info; - if (!reg->valid && reg->exist) { - core_addrs[core_cnt] = arc_reg->arch_num; - core_cnt += 1; - } + if (!reg->valid && reg->exist) + core_addrs[core_cnt++] = arc_reg->arch_num; } for (i = arc->num_core_regs; i < regs_to_scan; i++) { - struct reg *reg = &(reg_list[i]); + struct reg *reg = reg_list + i; struct arc_reg_desc *arc_reg = reg->arch_info; - if (!reg->valid && reg->exist) { - aux_addrs[aux_cnt] = arc_reg->arch_num; - aux_cnt += 1; - } + if (!reg->valid && reg->exist) + aux_addrs[aux_cnt++] = arc_reg->arch_num; } /* Read data from target. */ if (core_cnt > 0) { retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values); if (retval != ERROR_OK) { - LOG_ERROR("Attempt to read core registers failed."); + LOG_TARGET_ERROR(target, "Attempt to read core registers failed"); retval = ERROR_FAIL; goto exit; } @@ -875,7 +901,7 @@ static int arc_save_context(struct target *target) if (aux_cnt > 0) { retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values); if (retval != ERROR_OK) { - LOG_ERROR("Attempt to read aux registers failed."); + LOG_TARGET_ERROR(target, "Attempt to read aux registers failed"); retval = ERROR_FAIL; goto exit; } @@ -884,30 +910,30 @@ static int arc_save_context(struct target *target) /* Parse core regs */ core_cnt = 0; for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) { - struct reg *reg = &(reg_list[i]); + struct reg *reg = reg_list + i; struct arc_reg_desc *arc_reg = reg->arch_info; if (!reg->valid && reg->exist) { target_buffer_set_u32(target, reg->value, core_values[core_cnt]); - core_cnt += 1; reg->valid = true; reg->dirty = false; - LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32, + LOG_TARGET_DEBUG(target, "Get core register regnum=%u, name=%s, value=0x%08" PRIx32, i, arc_reg->name, core_values[core_cnt]); + core_cnt++; } } /* Parse aux regs */ aux_cnt = 0; for (i = arc->num_core_regs; i < regs_to_scan; i++) { - struct reg *reg = &(reg_list[i]); + struct reg *reg = reg_list + i; struct arc_reg_desc *arc_reg = reg->arch_info; if (!reg->valid && reg->exist) { target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]); - aux_cnt += 1; reg->valid = true; reg->dirty = false; - LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32, + LOG_TARGET_DEBUG(target, "Get aux register regnum=%u, name=%s, value=0x%08" PRIx32, i, arc_reg->name, aux_values[aux_cnt]); + aux_cnt++; } } @@ -983,14 +1009,14 @@ static int arc_examine_debug_reason(struct target *target) if (actionpoint) { if (!actionpoint->used) - LOG_WARNING("Target halted by an unused actionpoint."); + LOG_TARGET_WARNING(target, "Target halted by an unused actionpoint"); if (actionpoint->type == ARC_AP_BREAKPOINT) target->debug_reason = DBG_REASON_BREAKPOINT; else if (actionpoint->type == ARC_AP_WATCHPOINT) target->debug_reason = DBG_REASON_WATCHPOINT; else - LOG_WARNING("Unknown type of actionpoint."); + LOG_TARGET_WARNING(target, "Unknown type of actionpoint"); } } @@ -1020,7 +1046,7 @@ static int arc_poll(struct target *target) /* check for processor halted */ if (status & ARC_JTAG_STAT_RU) { if (target->state != TARGET_RUNNING) { - LOG_WARNING("target is still running!"); + LOG_TARGET_WARNING(target, "target is still running"); target->state = TARGET_RUNNING; } return ERROR_OK; @@ -1031,21 +1057,19 @@ static int arc_poll(struct target *target) if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { CHECK_RETVAL(arc_get_register_value(target, "status32", &value)); if (value & AUX_STATUS32_REG_HALT_BIT) { - LOG_DEBUG("ARC core in halt or reset state."); + LOG_TARGET_DEBUG(target, "ARC core in halt or reset state"); /* Save context if target was not in reset state */ if (target->state == TARGET_RUNNING) CHECK_RETVAL(arc_debug_entry(target)); target->state = TARGET_HALTED; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); } else { - LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, " + LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, " "target is still running"); } - } else if (target->state == TARGET_DEBUG_RUNNING) { - target->state = TARGET_HALTED; - LOG_DEBUG("ARC core is in debug running mode"); + LOG_TARGET_DEBUG(target, "ARC core is in debug running mode"); CHECK_RETVAL(arc_debug_entry(target)); @@ -1061,7 +1085,7 @@ static int arc_assert_reset(struct target *target) enum reset_types jtag_reset_config = jtag_get_reset_config(); bool srst_asserted = false; - LOG_DEBUG("target->state: %s", target_state_name(target)); + LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target)); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { /* allow scripts to override the reset event */ @@ -1075,8 +1099,8 @@ static int arc_assert_reset(struct target *target) if (target->state == TARGET_HALTED && !target->reset_halt) { /* Resume the target and continue from the current * PC register value. */ - LOG_DEBUG("Starting CPU execution after reset"); - CHECK_RETVAL(target_resume(target, 1, 0, 0, 0)); + LOG_TARGET_DEBUG(target, "Starting CPU execution after reset"); + CHECK_RETVAL(target_resume(target, true, 0, false, false)); } target->state = TARGET_RESET; @@ -1112,7 +1136,7 @@ static int arc_assert_reset(struct target *target) static int arc_deassert_reset(struct target *target) { - LOG_DEBUG("target->state: %s", target_state_name(target)); + LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -1129,7 +1153,7 @@ static int arc_arch_state(struct target *target) CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value)); - LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32, + LOG_TARGET_DEBUG(target, "target state: %s; PC at: 0x%08" PRIx32, target_state_name(target), pc_value); @@ -1148,7 +1172,7 @@ static int arc_restore_context(struct target *target) struct arc_common *arc = target_to_arc(target); struct reg *reg_list = arc->core_and_aux_cache->reg_list; - LOG_DEBUG("Restoring registers values"); + LOG_TARGET_DEBUG(target, "Restoring registers values"); assert(reg_list); const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t); @@ -1161,7 +1185,7 @@ static int arc_restore_context(struct target *target) unsigned int aux_cnt = 0; if (!core_values || !core_addrs || !aux_values || !aux_addrs) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); retval = ERROR_FAIL; goto exit; } @@ -1175,7 +1199,7 @@ static int arc_restore_context(struct target *target) struct reg *reg = &(reg_list[i]); struct arc_reg_desc *arc_reg = reg->arch_info; if (reg->valid && reg->exist && reg->dirty) { - LOG_DEBUG("Will write regnum=%u", i); + LOG_TARGET_DEBUG(target, "Will write regnum=%u", i); core_addrs[core_cnt] = arc_reg->arch_num; core_values[core_cnt] = target_buffer_get_u32(target, reg->value); core_cnt += 1; @@ -1186,7 +1210,7 @@ static int arc_restore_context(struct target *target) struct reg *reg = &(reg_list[arc->num_core_regs + i]); struct arc_reg_desc *arc_reg = reg->arch_info; if (reg->valid && reg->exist && reg->dirty) { - LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i); + LOG_TARGET_DEBUG(target, "Will write regnum=%lu", arc->num_core_regs + i); aux_addrs[aux_cnt] = arc_reg->arch_num; aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value); aux_cnt += 1; @@ -1198,7 +1222,7 @@ static int arc_restore_context(struct target *target) if (core_cnt > 0) { retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values); if (retval != ERROR_OK) { - LOG_ERROR("Attempt to write to core registers failed."); + LOG_TARGET_ERROR(target, "Attempt to write to core registers failed"); retval = ERROR_FAIL; goto exit; } @@ -1207,7 +1231,7 @@ static int arc_restore_context(struct target *target) if (aux_cnt > 0) { retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values); if (retval != ERROR_OK) { - LOG_ERROR("Attempt to write to aux registers failed."); + LOG_TARGET_ERROR(target, "Attempt to write to aux registers failed"); retval = ERROR_FAIL; goto exit; } @@ -1222,7 +1246,7 @@ static int arc_restore_context(struct target *target) return retval; } -static int arc_enable_interrupts(struct target *target, int enable) +static int arc_enable_interrupts(struct target *target, bool enable) { uint32_t value; @@ -1234,26 +1258,26 @@ static int arc_enable_interrupts(struct target *target, int enable) /* enable interrupts */ value |= SET_CORE_ENABLE_INTERRUPTS; CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value)); - LOG_DEBUG("interrupts enabled"); + LOG_TARGET_DEBUG(target, "interrupts enabled"); } else { /* disable interrupts */ value &= ~SET_CORE_ENABLE_INTERRUPTS; CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value)); - LOG_DEBUG("interrupts disabled"); + LOG_TARGET_DEBUG(target, "interrupts disabled"); } return ERROR_OK; } -static int arc_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int arc_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution) { struct arc_common *arc = target_to_arc(target); uint32_t resume_pc = 0; uint32_t value; struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]; - LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i," + LOG_TARGET_DEBUG(target, "current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i," " debug_execution:%i", current, address, handle_breakpoints, debug_execution); /* We need to reset ARC cache variables so caches @@ -1262,16 +1286,23 @@ static int arc_resume(struct target *target, int current, target_addr_t address, CHECK_RETVAL(arc_reset_caches_states(target)); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current PC, otherwise continue at <address> */ + if (!debug_execution) { + /* (gdb) continue = execute until we hit break/watch-point */ + target_free_all_working_areas(target); + CHECK_RETVAL(arc_enable_breakpoints(target)); + CHECK_RETVAL(arc_enable_watchpoints(target)); + } + + /* current = true: continue on current PC, otherwise continue at <address> */ if (!current) { target_buffer_set_u32(target, pc->value, address); - pc->dirty = 1; - pc->valid = 1; - LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address); + pc->dirty = true; + pc->valid = true; + LOG_TARGET_DEBUG(target, "Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address); } if (!current) @@ -1281,16 +1312,29 @@ static int arc_resume(struct target *target, int current, target_addr_t address, CHECK_RETVAL(arc_restore_context(target)); - LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i", + LOG_TARGET_DEBUG(target, "Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i", resume_pc, pc->dirty, pc->valid); /* check if GDB tells to set our PC where to continue from */ - if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) { + if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) { value = target_buffer_get_u32(target, pc->value); - LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value); + LOG_TARGET_DEBUG(target, "resume Core (when start-core) with PC @:0x%08" PRIx32, value); CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value)); } + /* the front-end may request us not to handle breakpoints here */ + if (handle_breakpoints) { + /* Single step past breakpoint at current address */ + struct breakpoint *breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { + LOG_TARGET_DEBUG(target, "skipping past breakpoint at 0x%08" TARGET_PRIxADDR, + breakpoint->address); + CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint)); + CHECK_RETVAL(arc_single_step_core(target)); + CHECK_RETVAL(arc_set_breakpoint(target, breakpoint)); + } + } + /* Restore IRQ state if not in debug_execution*/ if (!debug_execution) CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state)); @@ -1304,7 +1348,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address, CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value)); value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value)); - LOG_DEBUG("Core started to run"); + LOG_TARGET_DEBUG(target, "Core started to run"); /* registers are now invalid */ register_cache_invalidate(arc->core_and_aux_cache); @@ -1312,11 +1356,11 @@ static int arc_resume(struct target *target, int current, target_addr_t address, if (!debug_execution) { target->state = TARGET_RUNNING; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc); + LOG_TARGET_DEBUG(target, "target resumed at 0x%08" PRIx32, resume_pc); } else { target->state = TARGET_DEBUG_RUNNING; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)); - LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc); + LOG_TARGET_DEBUG(target, "target debug resumed at 0x%08" PRIx32, resume_pc); } return ERROR_OK; @@ -1340,7 +1384,7 @@ static void arc_deinit_target(struct target *target) { struct arc_common *arc = target_to_arc(target); - LOG_DEBUG("deinitialization of target"); + LOG_TARGET_DEBUG(target, "deinitialization of target"); if (arc->core_aux_cache_built) arc_free_reg_cache(arc->core_and_aux_cache); if (arc->bcr_cache_built) @@ -1380,16 +1424,16 @@ static void arc_deinit_target(struct target *target) } -static int arc_target_create(struct target *target, Jim_Interp *interp) +static int arc_target_create(struct target *target) { struct arc_common *arc = calloc(1, sizeof(*arc)); if (!arc) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); return ERROR_FAIL; } - LOG_DEBUG("Entering"); + LOG_TARGET_DEBUG(target, "Entering"); CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap)); return ERROR_OK; @@ -1401,16 +1445,16 @@ static int arc_target_create(struct target *target, Jim_Interp *interp) * little endian, so different type of conversion should be done. * Middle endian: instruction "aabbccdd", stored as "bbaaddcc" */ -int arc_write_instruction_u32(struct target *target, uint32_t address, +static int arc_write_instruction_u32(struct target *target, uint32_t address, uint32_t instr) { uint8_t value_buf[4]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + LOG_TARGET_ERROR(target, "Target not examined yet"); return ERROR_FAIL; } - LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address, + LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address, instr); if (target->endianness == TARGET_LITTLE_ENDIAN) @@ -1428,13 +1472,13 @@ int arc_write_instruction_u32(struct target *target, uint32_t address, * case of little endian ARC instructions are in middle endian format, so * different type of conversion should be done. */ -int arc_read_instruction_u32(struct target *target, uint32_t address, +static int arc_read_instruction_u32(struct target *target, uint32_t address, uint32_t *value) { uint8_t value_buf[4]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + LOG_TARGET_ERROR(target, "Target not examined yet"); return ERROR_FAIL; } @@ -1446,7 +1490,7 @@ int arc_read_instruction_u32(struct target *target, uint32_t address, else *value = be_to_h_u32(value_buf); - LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address, + LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address, *value); return ERROR_OK; @@ -1467,7 +1511,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num, if (control_tt != AP_AC_TT_DISABLE) { if (arc->actionpoints_num_avail < 1) { - LOG_ERROR("No free actionpoints, maximum amount is %u", + LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u", arc->actionpoints_num); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1501,12 +1545,12 @@ static int arc_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { if (breakpoint->is_set) { - LOG_WARNING("breakpoint already set"); + LOG_TARGET_WARNING(target, "breakpoint already set"); return ERROR_OK; } if (breakpoint->type == BKPT_SOFT) { - LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); + LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id); if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; @@ -1520,7 +1564,7 @@ static int arc_set_breakpoint(struct target *target, CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify)); if (verify != ARC_SDBBP_32) { - LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR + LOG_TARGET_ERROR(target, "Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR " - check that memory is read/writable", breakpoint->address); return ERROR_FAIL; } @@ -1533,12 +1577,12 @@ static int arc_set_breakpoint(struct target *target, CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify)); if (verify != ARC_SDBBP_16) { - LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR + LOG_TARGET_ERROR(target, "Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR " - check that memory is read/writable", breakpoint->address); return ERROR_FAIL; } } else { - LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4"); + LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4"); return ERROR_COMMAND_ARGUMENT_INVALID; } @@ -1554,7 +1598,7 @@ static int arc_set_breakpoint(struct target *target, } if (bp_num >= arc->actionpoints_num) { - LOG_ERROR("No free actionpoints, maximum amount is %u", + LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u", arc->actionpoints_num); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1568,18 +1612,15 @@ static int arc_set_breakpoint(struct target *target, ap_list[bp_num].bp_value = breakpoint->address; ap_list[bp_num].type = ARC_AP_BREAKPOINT; - LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32, + LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32, breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value); } } else { - LOG_DEBUG("ERROR: setting unknown breakpoint type"); + LOG_TARGET_ERROR(target, "setting unknown breakpoint type"); return ERROR_FAIL; } - /* core instruction cache is now invalid. */ - CHECK_RETVAL(arc_cache_invalidate(target)); - return ERROR_OK; } @@ -1589,13 +1630,13 @@ static int arc_unset_breakpoint(struct target *target, int retval = ERROR_OK; if (!breakpoint->is_set) { - LOG_WARNING("breakpoint not set"); + LOG_TARGET_WARNING(target, "breakpoint not set"); return ERROR_OK; } if (breakpoint->type == BKPT_SOFT) { /* restore original instruction (kept in target endianness) */ - LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); + LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id); if (breakpoint->length == 4) { uint32_t current_instr; @@ -1608,7 +1649,7 @@ static int arc_unset_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; } else { - LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR + LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR " has been overwritten outside of debugger." "Expected: @0x%x, got: @0x%" PRIx32, breakpoint->address, ARC_SDBBP_32, current_instr); @@ -1624,24 +1665,24 @@ static int arc_unset_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; } else { - LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR + LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR " has been overwritten outside of debugger. " "Expected: 0x%04x, got: 0x%04" PRIx16, breakpoint->address, ARC_SDBBP_16, current_instr); } } else { - LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4"); + LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4"); return ERROR_COMMAND_ARGUMENT_INVALID; } breakpoint->is_set = false; - } else if (breakpoint->type == BKPT_HARD) { + } else if (breakpoint->type == BKPT_HARD) { struct arc_common *arc = target_to_arc(target); struct arc_actionpoint *ap_list = arc->actionpoints_list; unsigned int bp_num = breakpoint->number; if (bp_num >= arc->actionpoints_num) { - LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32, + LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in breakpoint: %" PRIu32, bp_num, breakpoint->unique_id); return ERROR_OK; } @@ -1654,20 +1695,30 @@ static int arc_unset_breakpoint(struct target *target, ap_list[bp_num].used = 0; ap_list[bp_num].bp_value = 0; - LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u", + LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 " - released actionpoint ID: %u", breakpoint->unique_id, bp_num); } } else { - LOG_DEBUG("ERROR: unsetting unknown breakpoint type"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "unsetting unknown breakpoint type"); + return ERROR_FAIL; } - /* core instruction cache is now invalid. */ - CHECK_RETVAL(arc_cache_invalidate(target)); - return retval; } +static int arc_enable_breakpoints(struct target *target) +{ + struct breakpoint *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) { + if (!breakpoint->is_set) + CHECK_RETVAL(arc_set_breakpoint(target, breakpoint)); + breakpoint = breakpoint->next; + } + + return ERROR_OK; +} static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { @@ -1675,7 +1726,7 @@ static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoi return arc_set_breakpoint(target, breakpoint); } else { - LOG_WARNING(" > core was not halted, please try again."); + LOG_TARGET_ERROR(target, "not halted (add breakpoint)"); return ERROR_TARGET_NOT_HALTED; } } @@ -1687,14 +1738,14 @@ static int arc_remove_breakpoint(struct target *target, if (breakpoint->is_set) CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint)); } else { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (remove breakpoint)"); return ERROR_TARGET_NOT_HALTED; } return ERROR_OK; } -void arc_reset_actionpoints(struct target *target) +static void arc_reset_actionpoints(struct target *target) { struct arc_common *arc = target_to_arc(target); struct arc_actionpoint *ap_list = arc->actionpoints_list; @@ -1722,7 +1773,7 @@ void arc_reset_actionpoints(struct target *target) int arc_set_actionpoints_num(struct target *target, uint32_t ap_num) { - LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num); + LOG_TARGET_DEBUG(target, "actionpoints=%" PRIu32, ap_num); struct arc_common *arc = target_to_arc(target); /* Make sure that there are no enabled actionpoints in target. */ @@ -1737,7 +1788,7 @@ int arc_set_actionpoints_num(struct target *target, uint32_t ap_num) arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint)); if (!arc->actionpoints_list) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); return ERROR_FAIL; } return ERROR_OK; @@ -1760,7 +1811,7 @@ int arc_add_auxreg_actionpoint(struct target *target, ap_num++; if (ap_num >= arc->actionpoints_num) { - LOG_ERROR("No actionpoint free, maximum amount is %u", + LOG_TARGET_ERROR(target, "No actionpoint free, maximum amount is %u", arc->actionpoints_num); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1805,7 +1856,7 @@ int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr) ap_list[ap_num].bp_value = 0; } } else { - LOG_ERROR("Register actionpoint not found"); + LOG_TARGET_ERROR(target, "Register actionpoint not found"); } return retval; } @@ -1819,7 +1870,7 @@ static int arc_set_watchpoint(struct target *target, struct arc_actionpoint *ap_list = arc->actionpoints_list; if (watchpoint->is_set) { - LOG_WARNING("watchpoint already set"); + LOG_TARGET_WARNING(target, "watchpoint already set"); return ERROR_OK; } @@ -1829,13 +1880,13 @@ static int arc_set_watchpoint(struct target *target, } if (wp_num >= arc->actionpoints_num) { - LOG_ERROR("No free actionpoints, maximum amount is %u", + LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u", arc->actionpoints_num); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if (watchpoint->length != 4) { - LOG_ERROR("Only watchpoints of length 4 are supported"); + LOG_TARGET_ERROR(target, "Only watchpoints of length 4 are supported"); return ERROR_TARGET_UNALIGNED_ACCESS; } @@ -1851,7 +1902,7 @@ static int arc_set_watchpoint(struct target *target, enable = AP_AC_TT_READWRITE; break; default: - LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); return ERROR_FAIL; } @@ -1864,7 +1915,7 @@ static int arc_set_watchpoint(struct target *target, ap_list[wp_num].bp_value = watchpoint->address; ap_list[wp_num].type = ARC_AP_WATCHPOINT; - LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32, + LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32, watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value); } @@ -1879,13 +1930,13 @@ static int arc_unset_watchpoint(struct target *target, struct arc_actionpoint *ap_list = arc->actionpoints_list; if (!watchpoint->is_set) { - LOG_WARNING("watchpoint not set"); + LOG_TARGET_WARNING(target, "watchpoint not set"); return ERROR_OK; } unsigned int wp_num = watchpoint->number; if (wp_num >= arc->actionpoints_num) { - LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32, + LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in watchpoint: %" PRIu32, wp_num, watchpoint->unique_id); return ERROR_OK; } @@ -1898,18 +1949,32 @@ static int arc_unset_watchpoint(struct target *target, ap_list[wp_num].used = 0; ap_list[wp_num].bp_value = 0; - LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u", + LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 " - releasing actionpoint ID: %u", watchpoint->unique_id, wp_num); } return retval; } +static int arc_enable_watchpoints(struct target *target) +{ + struct watchpoint *watchpoint = target->watchpoints; + + /* set any pending watchpoints */ + while (watchpoint) { + if (!watchpoint->is_set) + CHECK_RETVAL(arc_set_watchpoint(target, watchpoint)); + watchpoint = watchpoint->next; + } + + return ERROR_OK; +} + static int arc_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1922,7 +1987,7 @@ static int arc_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1942,18 +2007,18 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat if (actionpoint) { if (!actionpoint->used) - LOG_WARNING("Target halted by unused actionpoint."); + LOG_TARGET_WARNING(target, "Target halted by unused actionpoint"); /* If this check fails - that is some sort of an error in OpenOCD. */ if (actionpoint->type != ARC_AP_WATCHPOINT) - LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint."); + LOG_TARGET_WARNING(target, "Target halted by breakpoint, but is treated as a watchpoint"); for (struct watchpoint *watchpoint = target->watchpoints; watchpoint; watchpoint = watchpoint->next) { if (actionpoint->bp_value == watchpoint->address) { *hit_watchpoint = watchpoint; - LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u", + LOG_TARGET_DEBUG(target, "Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u", watchpoint->unique_id, watchpoint->number); return ERROR_OK; } @@ -1965,7 +2030,7 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat /* Helper function which switches core to single_step mode by * doing aux r/w operations. */ -int arc_config_step(struct target *target, int enable_step) +static int arc_config_step(struct target *target, bool enable_step) { uint32_t value; @@ -1978,7 +2043,7 @@ int arc_config_step(struct target *target, int enable_step) value &= ~SET_CORE_AE_BIT; /* clear the AE bit */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value)); - LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value); + LOG_TARGET_DEBUG(target, " [status32:0x%08" PRIx32 "]", value); /* Doing read-modify-write, because DEBUG might contain manually set * bits like UB or ED, which should be preserved. */ @@ -1987,7 +2052,7 @@ int arc_config_step(struct target *target, int enable_step) value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value)); - LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value); + LOG_TARGET_DEBUG(target, "core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value); } else { /* disable core debug step mode */ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, @@ -1995,14 +2060,30 @@ int arc_config_step(struct target *target, int enable_step) value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value)); - LOG_DEBUG("core debug step mode disabled"); + LOG_TARGET_DEBUG(target, "core debug step mode disabled"); } return ERROR_OK; } -int arc_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int arc_single_step_core(struct target *target) +{ + CHECK_RETVAL(arc_debug_entry(target)); + + /* disable interrupts while stepping */ + CHECK_RETVAL(arc_enable_interrupts(target, false)); + + /* configure single step mode */ + CHECK_RETVAL(arc_config_step(target, true)); + + /* exit debug mode */ + CHECK_RETVAL(arc_exit_debug(target)); + + return ERROR_OK; +} + +static int arc_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { /* get pointers to arch-specific information */ struct arc_common *arc = target_to_arc(target); @@ -2010,18 +2091,18 @@ int arc_step(struct target *target, int current, target_addr_t address, struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { buf_set_u32(pc->value, 0, 32, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } - LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32, + LOG_TARGET_DEBUG(target, "Target steps one instruction from PC=0x%" PRIx32, buf_get_u32(pc->value, 0, 32)); /* the front-end may request us not to handle breakpoints */ @@ -2039,10 +2120,10 @@ int arc_step(struct target *target, int current, target_addr_t address, CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); /* disable interrupts while stepping */ - CHECK_RETVAL(arc_enable_interrupts(target, 0)); + CHECK_RETVAL(arc_enable_interrupts(target, false)); /* do a single step */ - CHECK_RETVAL(arc_config_step(target, 1)); + CHECK_RETVAL(arc_config_step(target, true)); /* make sure we done our step */ alive_sleep(1); @@ -2053,7 +2134,7 @@ int arc_step(struct target *target, int current, target_addr_t address, if (breakpoint) CHECK_RETVAL(arc_set_breakpoint(target, breakpoint)); - LOG_DEBUG("target stepped "); + LOG_TARGET_DEBUG(target, "target stepped"); target->state = TARGET_HALTED; @@ -2076,7 +2157,7 @@ static int arc_icache_invalidate(struct target *target) if (!arc->has_icache || arc->icache_invalidated) return ERROR_OK; - LOG_DEBUG("Invalidating I$."); + LOG_TARGET_DEBUG(target, "Invalidating I$"); value = IC_IVIC_INVALIDATE; /* invalidate I$ */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value)); @@ -2096,7 +2177,7 @@ static int arc_dcache_invalidate(struct target *target) if (!arc->has_dcache || arc->dcache_invalidated) return ERROR_OK; - LOG_DEBUG("Invalidating D$."); + LOG_TARGET_DEBUG(target, "Invalidating D$"); CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value)); dc_ctrl_value = value; @@ -2125,7 +2206,7 @@ static int arc_l2cache_invalidate(struct target *target) if (!arc->has_l2cache || arc->l2cache_invalidated) return ERROR_OK; - LOG_DEBUG("Invalidating L2$."); + LOG_TARGET_DEBUG(target, "Invalidating L2$"); CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value)); slc_ctrl_value = value; @@ -2138,7 +2219,7 @@ static int arc_l2cache_invalidate(struct target *target) /* Wait until invalidate operation ends */ do { - LOG_DEBUG("Waiting for invalidation end."); + LOG_TARGET_DEBUG(target, "Waiting for invalidation end"); CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value)); } while (value & L2_CTRL_BS); @@ -2165,7 +2246,7 @@ int arc_cache_invalidate(struct target *target) * values directly from memory, bypassing cache, so if there are unflushed * lines debugger will read invalid values, which will cause a lot of troubles. * */ -int arc_dcache_flush(struct target *target) +static int arc_dcache_flush(struct target *target) { uint32_t value, dc_ctrl_value; bool has_to_set_dc_ctrl_im; @@ -2176,7 +2257,7 @@ int arc_dcache_flush(struct target *target) if (!arc->has_dcache || arc->dcache_flushed) return ERROR_OK; - LOG_DEBUG("Flushing D$."); + LOG_TARGET_DEBUG(target, "Flushing D$"); /* Store current value of DC_CTRL */ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value)); @@ -2212,14 +2293,14 @@ static int arc_l2cache_flush(struct target *target) if (!arc->has_l2cache || arc->l2cache_flushed) return ERROR_OK; - LOG_DEBUG("Flushing L2$."); + LOG_TARGET_DEBUG(target, "Flushing L2$"); /* Flush L2 cache */ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL)); /* Wait until flush operation ends */ do { - LOG_DEBUG("Waiting for flushing end."); + LOG_TARGET_DEBUG(target, "Waiting for flushing end"); CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value)); } while (value & L2_CTRL_BS); diff --git a/src/target/arc.h b/src/target/arc.h index 86d8d09d55..4255840d1f 100644 --- a/src/target/arc.h +++ b/src/target/arc.h @@ -22,12 +22,13 @@ #include "target_request.h" #include "target_type.h" #include "helper/bits.h" +#include "rtt/rtt.h" #include "arc_jtag.h" #include "arc_cmd.h" #include "arc_mem.h" -#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */ +#define ARC_COMMON_MAGIC 0xB32EB324U /* just a unique number */ #define AUX_DEBUG_REG 0x5 #define AUX_PC_REG 0x6 @@ -183,7 +184,7 @@ struct arc_actionpoint { }; struct arc_common { - uint32_t common_magic; + unsigned int common_magic; struct arc_jtag jtag_info; @@ -253,16 +254,6 @@ struct arc_common { } \ } while (0) -#define JIM_CHECK_RETVAL(action) \ - do { \ - int __retval = (action); \ - if (__retval != JIM_OK) { \ - LOG_DEBUG("error while calling \"%s\"", \ - # action); \ - return __retval; \ - } \ - } while (0) - static inline struct arc_common *target_to_arc(struct target *target) { return target->arch_info; diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c index 8c859f2d4d..bf8a8aa28b 100644 --- a/src/target/arc_cmd.c +++ b/src/target/arc_cmd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. * @@ -13,6 +13,7 @@ #endif #include "arc.h" +#include <helper/nvp.h> /* -------------------------------------------------------------------------- * @@ -22,14 +23,6 @@ * ------------------------------------------------------------------------- */ -static int arc_cmd_jim_get_uint32(struct jim_getopt_info *goi, uint32_t *value) -{ - jim_wide value_wide; - JIM_CHECK_RETVAL(jim_getopt_wide(goi, &value_wide)); - *value = (uint32_t)value_wide; - return JIM_OK; -} - enum add_reg_types { CFG_ADD_REG_TYPE_FLAG, CFG_ADD_REG_TYPE_STRUCT, @@ -40,7 +33,7 @@ enum add_reg_type_flags { CFG_ADD_REG_TYPE_FLAGS_FLAG, }; -static struct jim_nvp nvp_add_reg_type_flags_opts[] = { +static const struct nvp nvp_add_reg_type_flags_opts[] = { { .name = "-name", .value = CFG_ADD_REG_TYPE_FLAGS_NAME }, { .name = "-flag", .value = CFG_ADD_REG_TYPE_FLAGS_FLAG }, { .name = NULL, .value = -1 } @@ -62,113 +55,113 @@ static const char *validate_register(const struct arc_reg_desc * const reg, bool return NULL; } -/* Helper function to read the name of register type or register from - * configure files */ -static int jim_arc_read_reg_name_field(struct jim_getopt_info *goi, - const char **name, int *name_len) +static COMMAND_HELPER(arc_handle_add_reg_type_flags_ops, struct arc_reg_data_type *type) { - int e = JIM_OK; + struct reg_data_type_flags_field *fields = type->reg_type_flags_field; + struct arc_reg_bitfield *bitfields = type->bitfields; + struct reg_data_type_flags *flags = &type->data_type_flags; + unsigned int cur_field = 0; - if (!goi->argc) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-name <name> ..."); - return JIM_ERR; - } - e = jim_getopt_string(goi, name, name_len); - return e; -} + while (CMD_ARGC) { + const struct nvp *n = nvp_name2value(nvp_add_reg_type_flags_opts, CMD_ARGV[0]); + CMD_ARGC--; + CMD_ARGV++; + switch (n->value) { + case CFG_ADD_REG_TYPE_FLAGS_NAME: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; -/* Helper function to read bitfields/flags of register type. */ -static int jim_arc_read_reg_type_field(struct jim_getopt_info *goi, const char **field_name, int *field_name_len, - struct arc_reg_bitfield *bitfields, int cur_field, int type) -{ - jim_wide start_pos, end_pos; + const char *name = CMD_ARGV[0]; + CMD_ARGC--; + CMD_ARGV++; + + if (strlen(name) >= REG_TYPE_MAX_NAME_LENGTH) { + command_print(CMD, "Reg type name is too big."); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - int e = JIM_OK; - if ((type == CFG_ADD_REG_TYPE_STRUCT && goi->argc < 3) || - (type == CFG_ADD_REG_TYPE_FLAG && goi->argc < 2)) { - Jim_SetResultFormatted(goi->interp, "Not enough arguments after -flag/-bitfield"); - return JIM_ERR; + strcpy((void *)type->data_type.id, name); + break; + + case CFG_ADD_REG_TYPE_FLAGS_FLAG: + if (CMD_ARGC < 2) + return ERROR_COMMAND_ARGUMENT_INVALID; + + uint32_t val; + const char *field_name = CMD_ARGV[0]; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], val); + CMD_ARGC -= 2; + CMD_ARGV += 2; + bitfields[cur_field].bitfield.start = val; + bitfields[cur_field].bitfield.end = val; + + if (strlen(field_name) >= REG_TYPE_MAX_NAME_LENGTH) { + command_print(CMD, "Reg type field_name is too big."); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + fields[cur_field].name = bitfields[cur_field].name; + strcpy(bitfields[cur_field].name, field_name); + + fields[cur_field].bitfield = &bitfields[cur_field].bitfield; + if (cur_field > 0) + fields[cur_field - 1].next = &fields[cur_field]; + else + flags->fields = fields; + + cur_field += 1; + break; + + default: + nvp_unknown_command_print(CMD, nvp_add_reg_type_flags_opts, NULL, CMD_ARGV[-1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } + } - e = jim_getopt_string(goi, field_name, field_name_len); - if (e != JIM_OK) - return e; - - /* read start position of bitfield/flag */ - e = jim_getopt_wide(goi, &start_pos); - if (e != JIM_OK) - return e; - - end_pos = start_pos; - - /* Check if any arguments remain, - * set bitfields[cur_field].end if flag is multibit */ - if (goi->argc > 0) - /* Check current argv[0], if it is equal to "-flag", - * than bitfields[cur_field].end remains start */ - if ((strcmp(Jim_String(goi->argv[0]), "-flag") && type == CFG_ADD_REG_TYPE_FLAG) - || (type == CFG_ADD_REG_TYPE_STRUCT)) { - e = jim_getopt_wide(goi, &end_pos); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi->interp, "Error reading end position"); - return e; - } - } - - bitfields[cur_field].bitfield.start = start_pos; - bitfields[cur_field].bitfield.end = end_pos; - if ((end_pos != start_pos) || (type == CFG_ADD_REG_TYPE_STRUCT)) - bitfields[cur_field].bitfield.type = REG_TYPE_INT; - return e; + if (!type->data_type.id) { + command_print(CMD, "-name is a required option"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + return ERROR_OK; } -static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_add_reg_type_flags) { - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); + int retval; LOG_DEBUG("-"); - struct command_context *ctx; - struct target *target; - - ctx = current_command_context(interp); - assert(ctx); - target = get_current_target(ctx); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } - int e = JIM_OK; - /* Check if the amount of arguments is not zero */ - if (goi.argc <= 0) { - Jim_SetResultFormatted(goi.interp, "The command has no arguments"); - return JIM_ERR; - } + if (CMD_ARGC == 0) + return ERROR_COMMAND_SYNTAX_ERROR; /* Estimate number of registers as (argc - 2)/3 as each -flag option has 2 * arguments while -name is required. */ - unsigned int fields_sz = (goi.argc - 2) / 3; - unsigned int cur_field = 0; + unsigned int fields_sz = (CMD_ARGC - 2) / 3; /* The maximum amount of bitfields is 32 */ if (fields_sz > 32) { - Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32"); - return JIM_ERR; + command_print(CMD, "The amount of bitfields exceed 32"); + return ERROR_COMMAND_ARGUMENT_INVALID; } struct arc_reg_data_type *type = calloc(1, sizeof(*type)); - struct reg_data_type_flags *flags = &type->data_type_flags; struct reg_data_type_flags_field *fields = calloc(fields_sz, sizeof(*fields)); - type->reg_type_flags_field = fields; struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*bitfields)); - if (!(type && fields && bitfields)) { - Jim_SetResultFormatted(goi.interp, "Failed to allocate memory."); + if (!type || !fields || !bitfields) { + LOG_ERROR("Out of memory"); + retval = ERROR_FAIL; goto fail; } + struct reg_data_type_flags *flags = &type->data_type_flags; + type->reg_type_flags_field = fields; /* Initialize type */ type->bitfields = bitfields; @@ -178,92 +171,22 @@ static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc, type->data_type.reg_type_flags = flags; flags->size = 4; /* For now ARC has only 32-bit registers */ - while (goi.argc > 0 && e == JIM_OK) { - struct jim_nvp *n; - e = jim_getopt_nvp(&goi, nvp_add_reg_type_flags_opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, nvp_add_reg_type_flags_opts, 0); - continue; - } - - switch (n->value) { - case CFG_ADD_REG_TYPE_FLAGS_NAME: - { - const char *name = NULL; - int name_len = 0; - - e = jim_arc_read_reg_name_field(&goi, &name, &name_len); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to read reg name."); - goto fail; - } - - if (name_len > REG_TYPE_MAX_NAME_LENGTH) { - Jim_SetResultFormatted(goi.interp, "Reg type name is too big."); - goto fail; - } - - strncpy((void *)type->data_type.id, name, name_len); - if (!type->data_type.id) { - Jim_SetResultFormatted(goi.interp, "Unable to setup reg type name."); - goto fail; - } - - break; - } - - case CFG_ADD_REG_TYPE_FLAGS_FLAG: - { - const char *field_name = NULL; - int field_name_len = 0; - - e = jim_arc_read_reg_type_field(&goi, &field_name, &field_name_len, bitfields, - cur_field, CFG_ADD_REG_TYPE_FLAG); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to add reg_type_flag field."); - goto fail; - } - - if (field_name_len > REG_TYPE_MAX_NAME_LENGTH) { - Jim_SetResultFormatted(goi.interp, "Reg type field_name_len is too big."); - goto fail; - } - - fields[cur_field].name = bitfields[cur_field].name; - strncpy(bitfields[cur_field].name, field_name, field_name_len); - if (!fields[cur_field].name) { - Jim_SetResultFormatted(goi.interp, "Unable to setup field name. "); - goto fail; - } - - fields[cur_field].bitfield = &(bitfields[cur_field].bitfield); - if (cur_field > 0) - fields[cur_field - 1].next = &(fields[cur_field]); - else - flags->fields = fields; - - cur_field += 1; - break; - } - } - } - - if (!type->data_type.id) { - Jim_SetResultFormatted(goi.interp, "-name is a required option"); + retval = CALL_COMMAND_HANDLER(arc_handle_add_reg_type_flags_ops, type); + if (retval != ERROR_OK) goto fail; - } arc_reg_data_type_add(target, type); LOG_DEBUG("added flags type {name=%s}", type->data_type.id); - return JIM_OK; + return ERROR_OK; + fail: free(type); free(fields); free(bitfields); - return JIM_ERR; + return retval; } /* Add struct register data type */ @@ -272,43 +195,30 @@ enum add_reg_type_struct { CFG_ADD_REG_TYPE_STRUCT_BITFIELD, }; -static struct jim_nvp nvp_add_reg_type_struct_opts[] = { +static const struct nvp nvp_add_reg_type_struct_opts[] = { { .name = "-name", .value = CFG_ADD_REG_TYPE_STRUCT_NAME }, { .name = "-bitfield", .value = CFG_ADD_REG_TYPE_STRUCT_BITFIELD }, { .name = NULL, .value = -1 } }; -static int jim_arc_set_aux_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_set_aux_reg) { + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; - struct command_context *context; - struct target *target; - uint32_t regnum; - uint32_t value; - - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - if (goi.argc != 2) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <aux_reg_num> <aux_reg_value>", Jim_GetString(argv[0], NULL)); - return JIM_ERR; - } - - context = current_command_context(interp); - assert(context); - - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } /* Register number */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, ®num)); + uint32_t regnum; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], regnum); /* Register value */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &value)); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); struct arc_common *arc = target_to_arc(target); assert(arc); @@ -318,121 +228,87 @@ static int jim_arc_set_aux_reg(Jim_Interp *interp, int argc, Jim_Obj * const *ar return ERROR_OK; } -static int jim_arc_get_aux_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_get_aux_reg) { - struct command_context *context; - struct target *target; - uint32_t regnum; - uint32_t value; - - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - if (goi.argc != 1) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <aux_reg_num>", Jim_GetString(argv[0], NULL)); - return JIM_ERR; - } - - context = current_command_context(interp); - assert(context); + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } /* Register number */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, ®num)); + uint32_t regnum; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], regnum); struct arc_common *arc = target_to_arc(target); assert(arc); + uint32_t value; CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, regnum, &value)); - Jim_SetResultInt(interp, value); + + command_print(CMD, "0x%" PRIx32, value); return ERROR_OK; } -static int jim_arc_get_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_get_core_reg) { - struct command_context *context; - struct target *target; - uint32_t regnum; - uint32_t value; - - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - if (goi.argc != 1) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <core_reg_num>", Jim_GetString(argv[0], NULL)); - return JIM_ERR; - } - - context = current_command_context(interp); - assert(context); + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } /* Register number */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, ®num)); + uint32_t regnum; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], regnum); if (regnum > CORE_REG_MAX_NUMBER || regnum == ARC_R61 || regnum == ARC_R62) { - Jim_SetResultFormatted(goi.interp, "Core register number %i " + command_print(CMD, "Core register number %i " "is invalid. Must less then 64 and not 61 and 62.", regnum); - return JIM_ERR; + return ERROR_COMMAND_ARGUMENT_INVALID; } struct arc_common *arc = target_to_arc(target); assert(arc); /* Read value */ + uint32_t value; CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, regnum, &value)); - Jim_SetResultInt(interp, value); + + command_print(CMD, "0x%" PRIx32, value); return ERROR_OK; } -static int jim_arc_set_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_set_core_reg) { - struct command_context *context; - struct target *target; - uint32_t regnum; - uint32_t value; - - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - if (goi.argc != 2) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <core_reg_num> <core_reg_value>", Jim_GetString(argv[0], NULL)); - return JIM_ERR; - } - - context = current_command_context(interp); - assert(context); + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } /* Register number */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, ®num)); + uint32_t regnum; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], regnum); if (regnum > CORE_REG_MAX_NUMBER || regnum == ARC_R61 || regnum == ARC_R62) { - Jim_SetResultFormatted(goi.interp, "Core register number %i " + command_print(CMD, "Core register number %i " "is invalid. Must less then 64 and not 61 and 62.", regnum); - return JIM_ERR; + return ERROR_COMMAND_ARGUMENT_INVALID; } /* Register value */ - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &value)); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); struct arc_common *arc = target_to_arc(target); assert(arc); @@ -445,7 +321,7 @@ static int jim_arc_set_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *a static const struct command_registration arc_jtag_command_group[] = { { .name = "get-aux-reg", - .jim_handler = jim_arc_get_aux_reg, + .handler = arc_handle_get_aux_reg, .mode = COMMAND_EXEC, .help = "Get AUX register by number. This command does a " "raw JTAG request that bypasses OpenOCD register cache " @@ -455,7 +331,7 @@ static const struct command_registration arc_jtag_command_group[] = { }, { .name = "set-aux-reg", - .jim_handler = jim_arc_set_aux_reg, + .handler = arc_handle_set_aux_reg, .mode = COMMAND_EXEC, .help = "Set AUX register by number. This command does a " "raw JTAG request that bypasses OpenOCD register cache " @@ -465,7 +341,7 @@ static const struct command_registration arc_jtag_command_group[] = { }, { .name = "get-core-reg", - .jim_handler = jim_arc_get_core_reg, + .handler = arc_handle_get_core_reg, .mode = COMMAND_EXEC, .help = "Get/Set core register by number. This command does a " "raw JTAG request that bypasses OpenOCD register cache " @@ -475,7 +351,7 @@ static const struct command_registration arc_jtag_command_group[] = { }, { .name = "set-core-reg", - .jim_handler = jim_arc_set_core_reg, + .handler = arc_handle_set_core_reg, .mode = COMMAND_EXEC, .help = "Get/Set core register by number. This command does a " "raw JTAG request that bypasses OpenOCD register cache " @@ -488,53 +364,117 @@ static const struct command_registration arc_jtag_command_group[] = { /* This function supports only bitfields. */ -static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +static COMMAND_HELPER(arc_handle_add_reg_type_struct_opts, struct arc_reg_data_type *type) { - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); + struct reg_data_type_struct_field *fields = type->reg_type_struct_field; + struct arc_reg_bitfield *bitfields = type->bitfields; + struct reg_data_type_struct *struct_type = &type->data_type_struct; + unsigned int cur_field = 0; - LOG_DEBUG("-"); + while (CMD_ARGC) { + const struct nvp *n = nvp_name2value(nvp_add_reg_type_struct_opts, CMD_ARGV[0]); + CMD_ARGC--; + CMD_ARGV++; + switch (n->value) { + case CFG_ADD_REG_TYPE_STRUCT_NAME: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; - struct command_context *ctx; - struct target *target; + const char *name = CMD_ARGV[0]; + CMD_ARGC--; + CMD_ARGV++; - ctx = current_command_context(interp); - assert(ctx); - target = get_current_target(ctx); - if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + if (strlen(name) >= REG_TYPE_MAX_NAME_LENGTH) { + command_print(CMD, "Reg type name is too big."); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + strcpy((void *)type->data_type.id, name); + break; + + case CFG_ADD_REG_TYPE_STRUCT_BITFIELD: + if (CMD_ARGC < 3) + return ERROR_COMMAND_ARGUMENT_INVALID; + + uint32_t start_pos, end_pos; + const char *field_name = CMD_ARGV[0]; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], start_pos); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], end_pos); + CMD_ARGC -= 3; + CMD_ARGV += 3; + bitfields[cur_field].bitfield.start = start_pos; + bitfields[cur_field].bitfield.end = end_pos; + bitfields[cur_field].bitfield.type = REG_TYPE_INT; + + if (strlen(field_name) >= REG_TYPE_MAX_NAME_LENGTH) { + command_print(CMD, "Reg type field_name is too big."); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + fields[cur_field].name = bitfields[cur_field].name; + strcpy(bitfields[cur_field].name, field_name); + + fields[cur_field].bitfield = &bitfields[cur_field].bitfield; + fields[cur_field].use_bitfields = true; + if (cur_field > 0) + fields[cur_field - 1].next = &fields[cur_field]; + else + struct_type->fields = fields; + + cur_field += 1; + + break; + + default: + nvp_unknown_command_print(CMD, nvp_add_reg_type_struct_opts, NULL, CMD_ARGV[-1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } } - int e = JIM_OK; + if (!type->data_type.id) { + command_print(CMD, "-name is a required option"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - /* Check if the amount of arguments is not zero */ - if (goi.argc <= 0) { - Jim_SetResultFormatted(goi.interp, "The command has no arguments"); - return JIM_ERR; + return ERROR_OK; +} + +COMMAND_HANDLER(arc_handle_add_reg_type_struct) +{ + int retval; + + LOG_DEBUG("-"); + + struct target *target = get_current_target(CMD_CTX); + if (!target) { + command_print(CMD, "No current target"); + return ERROR_FAIL; } + /* Check if the amount of arguments is not zero */ + if (CMD_ARGC == 0) + return ERROR_COMMAND_SYNTAX_ERROR; + /* Estimate number of registers as (argc - 2)/4 as each -bitfield option has 3 * arguments while -name is required. */ - unsigned int fields_sz = (goi.argc - 2) / 4; - unsigned int cur_field = 0; + unsigned int fields_sz = (CMD_ARGC - 2) / 4; /* The maximum amount of bitfields is 32 */ if (fields_sz > 32) { - Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32"); - return JIM_ERR; + command_print(CMD, "The amount of bitfields exceed 32"); + return ERROR_COMMAND_ARGUMENT_INVALID; } struct arc_reg_data_type *type = calloc(1, sizeof(*type)); - struct reg_data_type_struct *struct_type = &type->data_type_struct; struct reg_data_type_struct_field *fields = calloc(fields_sz, sizeof(*fields)); - type->reg_type_struct_field = fields; struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*bitfields)); - if (!(type && fields && bitfields)) { - Jim_SetResultFormatted(goi.interp, "Failed to allocate memory."); + if (!type || !fields || !bitfields) { + LOG_ERROR("Out of memory"); + retval = ERROR_FAIL; goto fail; } + struct reg_data_type_struct *struct_type = &type->data_type_struct; + type->reg_type_struct_field = fields; /* Initialize type */ type->data_type.id = type->data_type_id; @@ -544,91 +484,22 @@ static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc, type->data_type.reg_type_struct = struct_type; struct_type->size = 4; /* For now ARC has only 32-bit registers */ - while (goi.argc > 0 && e == JIM_OK) { - struct jim_nvp *n; - e = jim_getopt_nvp(&goi, nvp_add_reg_type_struct_opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, nvp_add_reg_type_struct_opts, 0); - continue; - } - - switch (n->value) { - case CFG_ADD_REG_TYPE_STRUCT_NAME: - { - const char *name = NULL; - int name_len = 0; - - e = jim_arc_read_reg_name_field(&goi, &name, &name_len); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to read reg name."); - goto fail; - } - - if (name_len > REG_TYPE_MAX_NAME_LENGTH) { - Jim_SetResultFormatted(goi.interp, "Reg type name is too big."); - goto fail; - } - - strncpy((void *)type->data_type.id, name, name_len); - if (!type->data_type.id) { - Jim_SetResultFormatted(goi.interp, "Unable to setup reg type name."); - goto fail; - } - - break; - } - case CFG_ADD_REG_TYPE_STRUCT_BITFIELD: - { - const char *field_name = NULL; - int field_name_len = 0; - e = jim_arc_read_reg_type_field(&goi, &field_name, &field_name_len, bitfields, - cur_field, CFG_ADD_REG_TYPE_STRUCT); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to add reg_type_struct field."); - goto fail; - } - - if (field_name_len > REG_TYPE_MAX_NAME_LENGTH) { - Jim_SetResultFormatted(goi.interp, "Reg type field_name_len is too big."); - goto fail; - } - - fields[cur_field].name = bitfields[cur_field].name; - strncpy(bitfields[cur_field].name, field_name, field_name_len); - if (!fields[cur_field].name) { - Jim_SetResultFormatted(goi.interp, "Unable to setup field name. "); - goto fail; - } - - fields[cur_field].bitfield = &(bitfields[cur_field].bitfield); - fields[cur_field].use_bitfields = true; - if (cur_field > 0) - fields[cur_field - 1].next = &(fields[cur_field]); - else - struct_type->fields = fields; - - cur_field += 1; - - break; - } - } - } - - if (!type->data_type.id) { - Jim_SetResultFormatted(goi.interp, "-name is a required option"); + retval = CALL_COMMAND_HANDLER(arc_handle_add_reg_type_struct_opts, type); + if (retval != ERROR_OK) goto fail; - } arc_reg_data_type_add(target, type); + LOG_DEBUG("added struct type {name=%s}", type->data_type.id); - return JIM_OK; + + return ERROR_OK; fail: - free(type); - free(fields); - free(bitfields); + free(type); + free(fields); + free(bitfields); - return JIM_ERR; + return retval; } /* Add register */ @@ -642,7 +513,7 @@ enum opts_add_reg { CFG_ADD_REG_GENERAL, }; -static struct jim_nvp opts_nvp_add_reg[] = { +static const struct nvp opts_nvp_add_reg[] = { { .name = "-name", .value = CFG_ADD_REG_NAME }, { .name = "-num", .value = CFG_ADD_REG_ARCH_NUM }, { .name = "-core", .value = CFG_ADD_REG_IS_CORE }, @@ -660,155 +531,133 @@ void free_reg_desc(struct arc_reg_desc *r) free(r); } -static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +static COMMAND_HELPER(arc_handle_add_reg_do, struct arc_reg_desc *reg) { - struct jim_getopt_info goi; - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - struct arc_reg_desc *reg = calloc(1, sizeof(*reg)); - if (!reg) { - Jim_SetResultFormatted(goi.interp, "Failed to allocate memory."); - return JIM_ERR; - } - /* There is no architecture number that we could treat as invalid, so * separate variable required to ensure that arch num has been set. */ bool arch_num_set = false; const char *type_name = "int"; /* Default type */ - int type_name_len = strlen(type_name); - int e = ERROR_OK; /* At least we need to specify 4 parameters: name, number and gdb_feature, * which means there should be 6 arguments. Also there can be additional parameters * "-type <type>", "-g" and "-core" or "-bcr" which makes maximum 10 parameters. */ - if (goi.argc < 6 || goi.argc > 10) { - free_reg_desc(reg); - Jim_SetResultFormatted(goi.interp, - "Should be at least 6 arguments and not greater than 10: " - " -name <name> -num <num> -feature <gdb_feature> " - " [-type <type_name>] [-core|-bcr] [-g]."); - return JIM_ERR; - } + if (CMD_ARGC < 6 || CMD_ARGC > 10) + return ERROR_COMMAND_SYNTAX_ERROR; /* Parse options. */ - while (goi.argc > 0) { - struct jim_nvp *n; - e = jim_getopt_nvp(&goi, opts_nvp_add_reg, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, opts_nvp_add_reg, 0); - free_reg_desc(reg); - return e; - } - + while (CMD_ARGC) { + const struct nvp *n = nvp_name2value(opts_nvp_add_reg, CMD_ARGV[0]); + CMD_ARGC--; + CMD_ARGV++; switch (n->value) { - case CFG_ADD_REG_NAME: - { - const char *reg_name = NULL; - int reg_name_len = 0; - - e = jim_arc_read_reg_name_field(&goi, ®_name, ®_name_len); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to read register name."); - free_reg_desc(reg); - return e; - } - - reg->name = strndup(reg_name, reg_name_len); - break; - } - case CFG_ADD_REG_IS_CORE: - reg->is_core = true; - break; - case CFG_ADD_REG_IS_BCR: - reg->is_bcr = true; - break; - case CFG_ADD_REG_ARCH_NUM: - { - jim_wide archnum; - - if (!goi.argc) { - free_reg_desc(reg); - Jim_WrongNumArgs(interp, goi.argc, goi.argv, "-num <int> ..."); - return JIM_ERR; - } - - e = jim_getopt_wide(&goi, &archnum); - if (e != JIM_OK) { - free_reg_desc(reg); - return e; - } - - reg->arch_num = archnum; - arch_num_set = true; - break; + case CFG_ADD_REG_NAME: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + reg->name = strdup(CMD_ARGV[0]); + if (!reg->name) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } - case CFG_ADD_REG_GDB_FEATURE: - { - const char *feature = NULL; - int feature_len = 0; - - e = jim_arc_read_reg_name_field(&goi, &feature, &feature_len); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to read gdb_feature."); - free_reg_desc(reg); - return e; - } - - reg->gdb_xml_feature = strndup(feature, feature_len); - break; + + CMD_ARGC--; + CMD_ARGV++; + break; + + case CFG_ADD_REG_IS_CORE: + reg->is_core = true; + break; + + case CFG_ADD_REG_IS_BCR: + reg->is_bcr = true; + break; + + case CFG_ADD_REG_ARCH_NUM: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg->arch_num); + CMD_ARGC--; + CMD_ARGV++; + + arch_num_set = true; + break; + + case CFG_ADD_REG_GDB_FEATURE: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + reg->gdb_xml_feature = strdup(CMD_ARGV[0]); + if (!reg->gdb_xml_feature) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } - case CFG_ADD_REG_TYPE: - e = jim_arc_read_reg_name_field(&goi, &type_name, &type_name_len); - if (e != JIM_OK) { - Jim_SetResultFormatted(goi.interp, "Unable to read register type."); - free_reg_desc(reg); - return e; - } - - break; - case CFG_ADD_REG_GENERAL: - reg->is_general = true; - break; - default: - LOG_DEBUG("Error: Unknown parameter"); - free_reg_desc(reg); - return JIM_ERR; + + CMD_ARGC--; + CMD_ARGV++; + break; + + case CFG_ADD_REG_TYPE: + if (!CMD_ARGC) + return ERROR_COMMAND_ARGUMENT_INVALID; + + type_name = CMD_ARGV[0]; + CMD_ARGC--; + CMD_ARGV++; + break; + + case CFG_ADD_REG_GENERAL: + reg->is_general = true; + break; + + default: + nvp_unknown_command_print(CMD, opts_nvp_add_reg, NULL, CMD_ARGV[-1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } } /* Check that required fields are set */ const char * const errmsg = validate_register(reg, arch_num_set); if (errmsg) { - Jim_SetResultFormatted(goi.interp, errmsg); - free_reg_desc(reg); - return JIM_ERR; + command_print(CMD, "%s", errmsg); + return ERROR_COMMAND_ARGUMENT_INVALID; } /* Add new register */ - struct command_context *ctx; - struct target *target; - - ctx = current_command_context(interp); - assert(ctx); - target = get_current_target(ctx); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - free_reg_desc(reg); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } reg->target = target; - e = arc_reg_add(target, reg, type_name, type_name_len); - if (e == ERROR_ARC_REGTYPE_NOT_FOUND) { - Jim_SetResultFormatted(goi.interp, + int retval = arc_reg_add(target, reg, type_name, strlen(type_name)); + if (retval == ERROR_ARC_REGTYPE_NOT_FOUND) { + command_print(CMD, "Cannot find type `%s' for register `%s'.", type_name, reg->name); + return retval; + } + + return ERROR_OK; +} + +COMMAND_HANDLER(arc_handle_add_reg) +{ + struct arc_reg_desc *reg = calloc(1, sizeof(*reg)); + if (!reg) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + int retval = CALL_COMMAND_HANDLER(arc_handle_add_reg_do, reg); + if (retval != ERROR_OK) { free_reg_desc(reg); - return JIM_ERR; + return retval; } - return e; + return ERROR_OK; } /* arc set-reg-exists ($reg_name)+ @@ -818,7 +667,7 @@ COMMAND_HANDLER(arc_set_reg_exists) struct target * const target = get_current_target(CMD_CTX); if (!target) { command_print(CMD, "Unable to get current target."); - return JIM_ERR; + return ERROR_FAIL; } if (!CMD_ARGC) { @@ -838,64 +687,45 @@ COMMAND_HANDLER(arc_set_reg_exists) r->exist = true; } - return JIM_OK; + return ERROR_OK; } /* arc reg-field ($reg_name) ($reg_field) * Reads struct type register field */ -static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_get_reg_field) { - struct jim_getopt_info goi; - const char *reg_name, *field_name; - uint32_t value; - int retval; - - JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); - - LOG_DEBUG("Reading register field"); - if (goi.argc != 2) { - if (!goi.argc) - Jim_WrongNumArgs(interp, goi.argc, goi.argv, "<regname> <fieldname>"); - else if (goi.argc == 1) - Jim_WrongNumArgs(interp, goi.argc, goi.argv, "<fieldname>"); - else - Jim_WrongNumArgs(interp, goi.argc, goi.argv, "<regname> <fieldname>"); + if (CMD_ARGC != 2) return ERROR_COMMAND_SYNTAX_ERROR; - } - - JIM_CHECK_RETVAL(jim_getopt_string(&goi, ®_name, NULL)); - JIM_CHECK_RETVAL(jim_getopt_string(&goi, &field_name, NULL)); - assert(reg_name); - assert(field_name); - struct command_context * const ctx = current_command_context(interp); - assert(ctx); - struct target * const target = get_current_target(ctx); + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } - retval = arc_reg_get_field(target, reg_name, field_name, &value); + const char *reg_name = CMD_ARGV[0]; + const char *field_name = CMD_ARGV[1]; + uint32_t value; + int retval = arc_reg_get_field(target, reg_name, field_name, &value); switch (retval) { case ERROR_OK: break; case ERROR_ARC_REGISTER_NOT_FOUND: - Jim_SetResultFormatted(goi.interp, + command_print(CMD, "Register `%s' has not been found.", reg_name); return ERROR_COMMAND_ARGUMENT_INVALID; case ERROR_ARC_REGISTER_IS_NOT_STRUCT: - Jim_SetResultFormatted(goi.interp, + command_print(CMD, "Register `%s' must have 'struct' type.", reg_name); return ERROR_COMMAND_ARGUMENT_INVALID; case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: - Jim_SetResultFormatted(goi.interp, + command_print(CMD, "Field `%s' has not been found in register `%s'.", field_name, reg_name); return ERROR_COMMAND_ARGUMENT_INVALID; case ERROR_ARC_FIELD_IS_NOT_BITFIELD: - Jim_SetResultFormatted(goi.interp, + command_print(CMD, "Field `%s' is not a 'bitfield' field in a structure.", field_name); return ERROR_COMMAND_ARGUMENT_INVALID; @@ -904,9 +734,9 @@ static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const * return retval; } - Jim_SetResultInt(interp, value); + command_print(CMD, "0x%" PRIx32, value); - return JIM_OK; + return ERROR_OK; } COMMAND_HANDLER(arc_l1_cache_disable_auto_cmd) @@ -929,27 +759,17 @@ COMMAND_HANDLER(arc_l2_cache_disable_auto_cmd) &arc->has_l2cache, "target has l2 cache enabled"); } -static int jim_handle_actionpoints_num(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(arc_handle_actionpoints_num) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - LOG_DEBUG("-"); - if (goi.argc >= 2) { - Jim_WrongNumArgs(interp, goi.argc, goi.argv, "[<unsigned integer>]"); - return JIM_ERR; - } - - struct command_context *context = current_command_context(interp); - assert(context); - - struct target *target = get_current_target(context); + if (CMD_ARGC >= 2) + return ERROR_COMMAND_SYNTAX_ERROR; + struct target *target = get_current_target(CMD_CTX); if (!target) { - Jim_SetResultFormatted(goi.interp, "No current target"); - return JIM_ERR; + command_print(CMD, "No current target"); + return ERROR_FAIL; } struct arc_common *arc = target_to_arc(target); @@ -958,24 +778,24 @@ static int jim_handle_actionpoints_num(Jim_Interp *interp, int argc, * "actionpoint reset, initiated by arc_set_actionpoints_num. */ uint32_t ap_num = arc->actionpoints_num; - if (goi.argc == 1) { - JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &ap_num)); + if (CMD_ARGC == 1) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ap_num); int e = arc_set_actionpoints_num(target, ap_num); if (e != ERROR_OK) { - Jim_SetResultFormatted(goi.interp, + command_print(CMD, "Failed to set number of actionpoints"); - return JIM_ERR; + return e; } } - Jim_SetResultInt(interp, ap_num); + command_print(CMD, "%" PRIu32, ap_num); - return JIM_OK; + return ERROR_OK; } /* ----- Exported target commands ------------------------------------------ */ -const struct command_registration arc_l2_cache_group_handlers[] = { +static const struct command_registration arc_l2_cache_group_handlers[] = { { .name = "auto", .handler = arc_l2_cache_disable_auto_cmd, @@ -986,7 +806,7 @@ const struct command_registration arc_l2_cache_group_handlers[] = { COMMAND_REGISTRATION_DONE }; -const struct command_registration arc_cache_group_handlers[] = { +static const struct command_registration arc_cache_group_handlers[] = { { .name = "auto", .handler = arc_l1_cache_disable_auto_cmd, @@ -1008,7 +828,7 @@ const struct command_registration arc_cache_group_handlers[] = { static const struct command_registration arc_core_command_handlers[] = { { .name = "add-reg-type-flags", - .jim_handler = jim_arc_add_reg_type_flags, + .handler = arc_handle_add_reg_type_flags, .mode = COMMAND_CONFIG, .usage = "-name <string> -flag <name> <position> " "[-flag <name> <position>]...", @@ -1018,7 +838,7 @@ static const struct command_registration arc_core_command_handlers[] = { }, { .name = "add-reg-type-struct", - .jim_handler = jim_arc_add_reg_type_struct, + .handler = arc_handle_add_reg_type_struct, .mode = COMMAND_CONFIG, .usage = "-name <string> -bitfield <name> <start> <end> " "[-bitfield <name> <start> <end>]...", @@ -1030,7 +850,7 @@ static const struct command_registration arc_core_command_handlers[] = { }, { .name = "add-reg", - .jim_handler = jim_arc_add_reg, + .handler = arc_handle_add_reg, .mode = COMMAND_CONFIG, .usage = "-name <string> -num <int> -feature <string> [-gdbnum <int>] " "[-core|-bcr] [-type <type_name>] [-g]", @@ -1049,7 +869,7 @@ static const struct command_registration arc_core_command_handlers[] = { }, { .name = "get-reg-field", - .jim_handler = jim_arc_get_reg_field, + .handler = arc_handle_get_reg_field, .mode = COMMAND_ANY, .usage = "<regname> <field_name>", .help = "Returns value of field in a register with 'struct' type.", @@ -1070,7 +890,7 @@ static const struct command_registration arc_core_command_handlers[] = { }, { .name = "num-actionpoints", - .jim_handler = jim_handle_actionpoints_num, + .handler = arc_handle_actionpoints_num, .mode = COMMAND_ANY, .usage = "[<unsigned integer>]", .help = "Prints or sets amount of actionpoints in the processor.", @@ -1086,5 +906,8 @@ const struct command_registration arc_monitor_command_handlers[] = { .usage = "", .chain = arc_core_command_handlers, }, + { + .chain = rtt_target_command_handlers, + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/arc_jtag.c b/src/target/arc_jtag.c index d949aaad3e..c2bc5aa8fd 100644 --- a/src/target/arc_jtag.c +++ b/src/target/arc_jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013-2014,2019-2020 Synopsys, Inc. * @@ -66,7 +66,7 @@ static void arc_jtag_enque_write_ir(struct arc_jtag *jtag_info, uint32_t * @param end_state End state after reading. */ static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data, - tap_state_t end_state) + enum tap_state end_state) { assert(jtag_info); @@ -88,7 +88,7 @@ static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data, * @param end_state End state after writing. */ static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data, - tap_state_t end_state) + enum tap_state end_state) { uint8_t out_value[sizeof(uint32_t)] = {0}; @@ -116,7 +116,7 @@ static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data, * @param end_state End state after writing. */ static void arc_jtag_enque_set_transaction(struct arc_jtag *jtag_info, - uint32_t new_trans, tap_state_t end_state) + uint32_t new_trans, enum tap_state end_state) { uint8_t out_value[sizeof(uint32_t)] = {0}; @@ -298,7 +298,7 @@ static int arc_jtag_read_registers(struct arc_jtag *jtag_info, uint32_t type, ARC_JTAG_READ_FROM_CORE_REG : ARC_JTAG_READ_FROM_AUX_REG); arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE); - uint8_t *data_buf = calloc(sizeof(uint8_t), count * 4); + uint8_t *data_buf = calloc(count * 4, sizeof(uint8_t)); arc_jtag_enque_register_rw(jtag_info, addr, data_buf, NULL, count); @@ -498,7 +498,7 @@ int arc_jtag_read_memory(struct arc_jtag *jtag_info, uint32_t addr, if (!count) return ERROR_OK; - data_buf = calloc(sizeof(uint8_t), count * 4); + data_buf = calloc(count * 4, sizeof(uint8_t)); arc_jtag_enque_reset_transaction(jtag_info); /* We are reading from memory. */ diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c index 0dc3f6870e..5132aca3d9 100644 --- a/src/target/arc_mem.c +++ b/src/target/arc_mem.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013-2014,2019-2020 Synopsys, Inc. * @@ -35,7 +35,7 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr, { struct arc_common *arc = target_to_arc(target); - LOG_DEBUG("Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, + LOG_TARGET_DEBUG(target, "Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, addr, count); /* Check arguments */ @@ -66,7 +66,7 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr, uint8_t buffer_te[sizeof(uint32_t)]; uint8_t halfword_te[sizeof(uint16_t)]; - LOG_DEBUG("Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, + LOG_TARGET_DEBUG(target, "Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, addr, count); /* Check arguments */ @@ -124,7 +124,7 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr, uint8_t buffer_te[sizeof(uint32_t)]; - LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, + LOG_TARGET_DEBUG(target, "Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, addr, count); /* We will read data from memory, so we need to flush the cache. */ @@ -158,14 +158,9 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size, int retval = ERROR_OK; void *tunnel = NULL; - LOG_DEBUG("address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32, + LOG_TARGET_DEBUG(target, "address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32, address, size, count); - if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || !(count) || !(buffer)) return ERROR_COMMAND_SYNTAX_ERROR; @@ -182,7 +177,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size, tunnel = calloc(1, count * size * sizeof(uint8_t)); if (!tunnel) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); return ERROR_FAIL; } @@ -220,7 +215,7 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr, { struct arc_common *arc = target_to_arc(target); - LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32 + LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32 ", count=%" PRIu32, addr, size, count); assert(!(addr & 3)); assert(size == 4); @@ -243,14 +238,9 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size, uint32_t words_to_read, bytes_to_read; - LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32 + LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32 ", count=%" PRIu32, address, size, count); - if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - /* Sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || !(count) || !(buffer)) return ERROR_COMMAND_SYNTAX_ERROR; @@ -268,7 +258,7 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size, tunnel_te = calloc(1, bytes_to_read); if (!tunnel_he || !tunnel_te) { - LOG_ERROR("Unable to allocate memory"); + LOG_TARGET_ERROR(target, "Unable to allocate memory"); free(tunnel_he); free(tunnel_te); return ERROR_FAIL; diff --git a/src/target/arm.h b/src/target/arm.h index e264293f4e..79ec99d117 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -58,6 +58,14 @@ enum arm_arch { ARM_ARCH_V8M, }; +/** Known ARM implementer IDs */ +enum arm_implementer { + ARM_IMPLEMENTER_ARM = 0x41, + ARM_IMPLEMENTER_INFINEON = 0x49, + ARM_IMPLEMENTER_ARM_CHINA = 0x63, + ARM_IMPLEMENTER_REALTEK = 0x72, +}; + /** * Represent state of an ARM core. * @@ -135,8 +143,8 @@ enum { ARM_VFP_V3_FPSCR, }; -const char *arm_mode_name(unsigned psr_mode); -bool is_arm_mode(unsigned psr_mode); +const char *arm_mode_name(unsigned int psr_mode); +bool is_arm_mode(unsigned int psr_mode); /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */ enum arm_state { @@ -155,7 +163,7 @@ enum arm_vfp_version { ARM_VFP_V3, }; -#define ARM_COMMON_MAGIC 0x0A450A45 +#define ARM_COMMON_MAGIC 0x0A450A45U /** * Represents a generic ARM core, with standard application registers. @@ -165,7 +173,8 @@ enum arm_vfp_version { * registers as traditional ARM cores, and only support Thumb2 instructions. */ struct arm { - int common_magic; + unsigned int common_magic; + struct reg_cache *core_cache; /** Handle to the PC; valid in all core modes. */ @@ -223,12 +232,22 @@ struct arm { uint32_t crn, uint32_t crm, uint32_t *value); + /** Read coprocessor to two registers. */ + int (*mrrc)(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t *value); + /** Write coprocessor register. */ int (*mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value); + /** Write coprocessor from two registers. */ + int (*mcrr)(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t value); + void *arch_info; /** For targets conforming to ARM Debug Interface v5, @@ -239,7 +258,7 @@ struct arm { }; /** Convert target handle to generic ARM target state handle. */ -static inline struct arm *target_to_arm(struct target *target) +static inline struct arm *target_to_arm(const struct target *target) { assert(target); return target->arch_info; @@ -252,7 +271,7 @@ static inline bool is_arm(struct arm *arm) } struct arm_algorithm { - int common_magic; + unsigned int common_magic; enum arm_mode core_mode; enum arm_state core_state; @@ -272,13 +291,14 @@ void arm_free_reg_cache(struct arm *arm); struct reg_cache *armv8_build_reg_cache(struct target *target); extern const struct command_registration arm_command_handlers[]; +extern const struct command_registration arm_all_profiles_command_handlers[]; int arm_arch_state(struct target *target); -const char *arm_get_gdb_arch(struct target *target); +const char *arm_get_gdb_arch(const struct target *target); int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); -const char *armv8_get_gdb_arch(struct target *target); +const char *armv8_get_gdb_arch(const struct target *target); int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); @@ -290,14 +310,14 @@ int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info, + unsigned int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, - int timeout_ms, void *arch_info)); + unsigned int timeout_ms, void *arch_info)); int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum); @@ -305,10 +325,7 @@ int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); void arm_set_cpsr(struct arm *arm, uint32_t cpsr); -struct reg *arm_reg_current(struct arm *arm, unsigned regnum); -struct reg *armv8_reg_current(struct arm *arm, unsigned regnum); - -extern struct reg arm_gdb_dummy_fp_reg; -extern struct reg arm_gdb_dummy_fps_reg; +struct reg *arm_reg_current(struct arm *arm, unsigned int regnum); +struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum); #endif /* OPENOCD_TARGET_ARM_H */ diff --git a/src/target/arm11.c b/src/target/arm11.c index 2207a6dfa2..583830f948 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * @@ -30,8 +30,8 @@ #endif -static int arm11_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints); +static int arm11_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints); /** Check and if necessary take control of the system @@ -43,7 +43,7 @@ static int arm11_check_init(struct arm11_common *arm11) CHECK_RETVAL(arm11_read_dscr(arm11)); if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) { - LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); + LOG_DEBUG("DSCR %08" PRIx32, arm11->dscr); LOG_DEBUG("Bringing target into debug mode"); arm11->dscr |= DSCR_HALT_DBG_MODE; @@ -241,8 +241,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) registers hold data that was written by one side (CPU or JTAG) and not read out by the other side. */ - LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", - (unsigned) arm11->dscr); + LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", arm11->dscr); return ERROR_FAIL; } } @@ -402,7 +401,8 @@ static int arm11_halt(struct target *target) return ERROR_OK; } -static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) +static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current, + uint32_t address) { void *value = arm11->arm.pc->value; @@ -436,8 +436,8 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t a return address; } -static int arm11_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int arm11_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */ /* current, address, handle_breakpoints, debug_execution); */ @@ -449,7 +449,7 @@ static int arm11_resume(struct target *target, int current, if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -470,7 +470,7 @@ static int arm11_resume(struct target *target, int current, for (bp = target->breakpoints; bp; bp = bp->next) { if (bp->address == address) { LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address); - arm11_step(target, 1, 0, 0); + arm11_step(target, true, 0, false); break; } } @@ -479,7 +479,7 @@ static int arm11_resume(struct target *target, int current, /* activate all breakpoints */ if (true) { struct breakpoint *bp; - unsigned brp_num = 0; + unsigned int brp_num = 0; for (bp = target->breakpoints; bp; bp = bp->next) { struct arm11_sc7_action brp[2]; @@ -516,7 +516,7 @@ static int arm11_resume(struct target *target, int current, while (1) { CHECK_RETVAL(arm11_read_dscr(arm11)); - LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); + LOG_DEBUG("DSCR %08" PRIx32, arm11->dscr); if (arm11->dscr & DSCR_CORE_RESTARTED) break; @@ -544,14 +544,14 @@ static int arm11_resume(struct target *target, int current, return ERROR_OK; } -static int arm11_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int arm11_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { LOG_DEBUG("target->state: %s", target_state_name(target)); if (target->state != TARGET_HALTED) { - LOG_WARNING("target was not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -570,13 +570,13 @@ static int arm11_step(struct target *target, int current, /* skip over BKPT */ if ((next_instruction & 0xFFF00070) == 0xe1200070) { - address = arm11_nextpc(arm11, 0, address + 4); + address = arm11_nextpc(arm11, false, address + 4); LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address); } /* skip over Wait for interrupt / Standby * mcr 15, 0, r?, cr7, cr0, {4} */ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) { - address = arm11_nextpc(arm11, 0, address + 4); + address = arm11_nextpc(arm11, false, address + 4); LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address); } /* ignore B to self */ @@ -662,7 +662,7 @@ static int arm11_step(struct target *target, int current, | DSCR_CORE_HALTED; CHECK_RETVAL(arm11_read_dscr(arm11)); - LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); + LOG_DEBUG("DSCR %08" PRIx32 " e", arm11->dscr); if ((arm11->dscr & mask) == mask) break; @@ -798,7 +798,7 @@ static int arm11_read_memory_inner(struct target *target, int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target was not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -896,7 +896,7 @@ static int arm11_write_memory_inner(struct target *target, int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target was not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1012,10 +1012,8 @@ static int arm11_write_memory_inner(struct target *target, return retval; if (address + size * count != r0) { - LOG_ERROR("Data transfer failed. Expected end " - "address 0x%08x, got 0x%08x", - (unsigned) (address + size * count), - (unsigned) r0); + LOG_ERROR("Data transfer failed. Expected end address 0x%08" PRIx32 ", got 0x%08" PRIx32, + address + size * count, r0); if (burst) LOG_ERROR( @@ -1081,7 +1079,7 @@ static int arm11_remove_breakpoint(struct target *target, return ERROR_OK; } -static int arm11_target_create(struct target *target, Jim_Interp *interp) +static int arm11_target_create(struct target *target) { struct arm11_common *arm11; diff --git a/src/target/arm11.h b/src/target/arm11.h index 1f56f7bba4..40a3f9024d 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -39,7 +39,7 @@ struct arm11_common { /** Debug module state. */ struct arm_dpm dpm; struct arm11_sc7_action *bpwp_actions; - unsigned bpwp_n; + unsigned int bpwp_n; size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ size_t free_brps; /**< Number of breakpoints allocated */ diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 5035d9e053..4c7211365b 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * @@ -31,13 +31,13 @@ behavior of the FTDI driver IIRC was to go via RTI. Conversely there may be other places in this code where the ARM11 code relies on the driver to hit through RTI when coming from Update-?R. */ -static const tap_state_t arm11_move_pi_to_si_via_ci[] = { +static const enum tap_state arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; /* REVISIT no error handling here! */ static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields, - tap_state_t state) + enum tap_state state) { if (cmd_queue_cur_state == TAP_IRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), @@ -46,13 +46,13 @@ static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields jtag_add_ir_scan(tap, fields, state); } -static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { +static const enum tap_state arm11_move_pd_to_sd_via_cd[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; /* REVISIT no error handling here! */ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, - tap_state_t state) + enum tap_state state) { if (cmd_queue_cur_state == TAP_DRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), @@ -121,7 +121,7 @@ static const char *arm11_ir_to_string(uint8_t ir) * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state) +void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, enum tap_state state) { struct jtag_tap *tap = arm11->arm.target->tap; @@ -181,7 +181,7 @@ static void arm11_in_handler_scan_n(uint8_t *in_value) */ int arm11_add_debug_scan_n(struct arm11_common *arm11, - uint8_t chain, tap_state_t state) + uint8_t chain, enum tap_state state) { /* Don't needlessly switch the scan chain. * NOTE: the ITRSEL instruction fakes SCREG changing; @@ -240,9 +240,9 @@ int arm11_add_debug_scan_n(struct arm11_common *arm11, * to ensure that the rDTR is ready before that Run-Test/Idle state. */ static void arm11_add_debug_inst(struct arm11_common *arm11, - uint32_t inst, uint8_t *flag, tap_state_t state) + uint32_t inst, uint8_t *flag, enum tap_state state) { - JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst); + JTAG_DEBUG("INST <= 0x%08" PRIx32, inst); struct scan_field itr[2]; @@ -282,9 +282,7 @@ int arm11_read_dscr(struct arm11_common *arm11) CHECK_RETVAL(jtag_execute_queue()); if (arm11->dscr != dscr) - JTAG_DEBUG("DSCR = %08x (OLD %08x)", - (unsigned) dscr, - (unsigned) arm11->dscr); + JTAG_DEBUG("DSCR = %08" PRIx32 " (OLD %08" PRIx32 ")", dscr, arm11->dscr); arm11->dscr = dscr; @@ -317,9 +315,7 @@ int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr) CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DSCR <= %08x (OLD %08x)", - (unsigned) dscr, - (unsigned) arm11->dscr); + JTAG_DEBUG("DSCR <= %08" PRIx32 " (OLD %08" PRIx32 ")", dscr, arm11->dscr); arm11->dscr = dscr; @@ -509,8 +505,8 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR _data %08x ready %d n_retry %d", - (unsigned) _data, ready, n_retry); + JTAG_DEBUG("DTR _data %08" PRIx32 " ready %d n_retry %d", + _data, ready, n_retry); int64_t then = 0; @@ -546,7 +542,7 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -static const tap_state_t arm11_move_drpause_idle_drpause_with_delay[] = { +static const enum tap_state arm11_move_drpause_idle_drpause_with_delay[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -571,8 +567,8 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, chain5_fields[2].in_value = NULL; uint8_t *readies; - unsigned readies_num = count; - unsigned bytes = sizeof(*readies)*readies_num; + unsigned int readies_num = count; + unsigned int bytes = sizeof(*readies) * readies_num; readies = malloc(bytes); if (!readies) { @@ -596,7 +592,7 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, int retval = jtag_execute_queue(); if (retval == ERROR_OK) { - unsigned error_count = 0; + unsigned int error_count = 0; for (size_t i = 0; i < readies_num; i++) { if (readies[i] != 1) @@ -754,8 +750,8 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11, CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR _data %08x ready %d n_retry %d", - (unsigned) _data, ready, n_retry); + JTAG_DEBUG("DTR _data %08" PRIx32 " ready %d n_retry %d", + _data, ready, n_retry); int64_t then = 0; @@ -878,9 +874,8 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, /* Timeout here so we don't get stuck. */ int i_n = 0; while (1) { - JTAG_DEBUG("SC7 <= c%-3d Data %08x %s", - (unsigned) address_out, - (unsigned) data_out, + JTAG_DEBUG("SC7 <= c%-3" PRIu8 " Data %08" PRIx32 " %s", + address_out, data_out, n_rw ? "write" : "read"); arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields), @@ -908,7 +903,7 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, } if (!n_rw) - JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in); + JTAG_DEBUG("SC7 => Data %08" PRIx32, data_in); if (i > 0) { if (actions[i - 1].address != address_in) @@ -1047,7 +1042,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, * and watchpoint operations instead of running them right away. Since we * pre-allocated our vector, we don't need to worry about space. */ -static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, +static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, uint32_t addr, uint32_t control) { struct arm11_common *arm11 = dpm_to_arm11(dpm); @@ -1084,7 +1079,7 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, return ERROR_OK; } -static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) +static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) { struct arm11_common *arm11 = dpm_to_arm11(dpm); struct arm11_sc7_action *action; diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h index eeb174a8ba..74dda6e893 100644 --- a/src/target/arm11_dbgtap.h +++ b/src/target/arm11_dbgtap.h @@ -17,9 +17,9 @@ void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *in_data, void *out_data, struct scan_field *field); void arm11_add_ir(struct arm11_common *arm11, - uint8_t instr, tap_state_t state); + uint8_t instr, enum tap_state state); int arm11_add_debug_scan_n(struct arm11_common *arm11, - uint8_t chain, tap_state_t state); + uint8_t chain, enum tap_state state); int arm11_read_dscr(struct arm11_common *arm11); int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr); @@ -40,7 +40,7 @@ int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data); void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, - tap_state_t state); + enum tap_state state); /** * Used with arm11_sc7_run to make a list of read/write commands for diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 128a14f0c2..d1433dde72 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -241,8 +241,8 @@ static int arm720t_arch_state(struct target *target) static int arm720_mmu(struct target *target, int *enabled) { if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled; @@ -412,7 +412,7 @@ static int arm720t_init_arch_info(struct target *target, return ERROR_OK; } -static int arm720t_target_create(struct target *target, Jim_Interp *interp) +static int arm720t_target_create(struct target *target) { struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); diff --git a/src/target/arm720t.h b/src/target/arm720t.h index 81c6e1f6ad..65bd78ff08 100644 --- a/src/target/arm720t.h +++ b/src/target/arm720t.h @@ -11,11 +11,12 @@ #include "arm7tdmi.h" #include "armv4_5_mmu.h" -#define ARM720T_COMMON_MAGIC 0xa720a720 +#define ARM720T_COMMON_MAGIC 0xa720a720U struct arm720t_common { + unsigned int common_magic; + struct arm7_9_common arm7_9_common; - uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; uint32_t cp15_control_reg; uint32_t fsr_reg; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 9eed440826..5550fb1e24 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -184,7 +184,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break breakpoint->type); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -451,11 +451,12 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int rw_mask = 1; uint32_t mask; + const uint32_t wp_data_mask = watchpoint->mask; mask = watchpoint->length - 1; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -469,8 +470,8 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], - watchpoint->mask); - if (watchpoint->mask != 0xffffffffu) + wp_data_mask); + if (wp_data_mask != (uint32_t)WATCHPOINT_IGNORE_DATA_VALUE_MASK) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], @@ -488,8 +489,8 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], - watchpoint->mask); - if (watchpoint->mask != 0xffffffffu) + wp_data_mask); + if (wp_data_mask != (uint32_t)WATCHPOINT_IGNORE_DATA_VALUE_MASK) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], @@ -524,7 +525,7 @@ static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *wat struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1259,7 +1260,7 @@ static int arm7_9_debug_entry(struct target *target) return retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1390,7 +1391,7 @@ static int arm7_9_full_context(struct target *target) LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1506,7 +1507,7 @@ static int arm7_9_restore_context(struct target *target) LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1553,7 +1554,6 @@ static int arm7_9_restore_context(struct target *target) if (dirty) { uint32_t mask = 0x0; - int num_regs = 0; uint32_t regs[16]; if (mode_change) { @@ -1576,7 +1576,6 @@ static int arm7_9_restore_context(struct target *target) if (reg->dirty) { regs[j] = buf_get_u32(reg->value, 0, 32); mask |= 1 << j; - num_regs++; reg->dirty = false; reg->valid = true; LOG_DEBUG("writing register %i mode %s " @@ -1698,10 +1697,10 @@ static void arm7_9_enable_breakpoints(struct target *target) } int arm7_9_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, + bool debug_execution) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -1711,14 +1710,14 @@ int arm7_9_resume(struct target *target, LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } if (!debug_execution) target_free_all_working_areas(target); - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) buf_set_u32(arm->pc->value, 0, 32, address); @@ -1901,7 +1900,8 @@ void arm7_9_disable_eice_step(struct target *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]); } -int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) +int arm7_9_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -1909,11 +1909,11 @@ int arm7_9_step(struct target *target, int current, target_addr_t address, int h int err, retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) buf_set_u32(arm->pc->value, 0, 32, address); @@ -2120,7 +2120,7 @@ int arm7_9_read_memory(struct target *target, address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2293,7 +2293,7 @@ int arm7_9_write_memory(struct target *target, #endif if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2520,7 +2520,7 @@ static const uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, - int timeout_ms, + unsigned int timeout_ms, void *arch_info) { int retval = ERROR_OK; diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index 805fbc918e..c4a5b08d21 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -20,14 +20,15 @@ #include "arm.h" #include "arm_jtag.h" -#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */ +#define ARM7_9_COMMON_MAGIC 0x0a790a79U /**< */ /** * Structure for items that are common between both ARM7 and ARM9 targets. */ struct arm7_9_common { + unsigned int common_magic; + struct arm arm; - uint32_t common_magic; struct arm_jtag jtag_info; /**< JTAG information for target */ struct reg_cache *eice_cache; /**< Embedded ICE register cache */ @@ -144,10 +145,10 @@ int arm7_9_early_halt(struct target *target); int arm7_9_soft_reset_halt(struct target *target); int arm7_9_halt(struct target *target); -int arm7_9_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution); -int arm7_9_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints); +int arm7_9_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution); +int arm7_9_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints); int arm7_9_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); int arm7_9_write_memory(struct target *target, target_addr_t address, diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index b7094a3f77..2f59254afd 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -669,7 +669,7 @@ int arm7tdmi_init_arch_info(struct target *target, return ERROR_OK; } -static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) +static int arm7tdmi_target_create(struct target *target) { struct arm7_9_common *arm7_9; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 7b5fa81e67..95cfd7ceb2 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** @@ -533,8 +533,8 @@ int arm920t_arch_state(struct target *target) static int arm920_mmu(struct target *target, int *enabled) { if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled; @@ -833,7 +833,7 @@ static int arm920t_init_arch_info(struct target *target, return ERROR_OK; } -static int arm920t_target_create(struct target *target, Jim_Interp *interp) +static int arm920t_target_create(struct target *target) { struct arm920t_common *arm920t; @@ -1455,9 +1455,9 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for " + command_print(CMD, "Error: target must be stopped for " "\"%s\" command", CMD_NAME); - return ERROR_OK; + return ERROR_TARGET_NOT_HALTED; } /* one argument, read a register. diff --git a/src/target/arm920t.h b/src/target/arm920t.h index 49ec3c0001..eba768ffff 100644 --- a/src/target/arm920t.h +++ b/src/target/arm920t.h @@ -11,11 +11,12 @@ #include "arm9tdmi.h" #include "armv4_5_mmu.h" -#define ARM920T_COMMON_MAGIC 0xa920a920 +#define ARM920T_COMMON_MAGIC 0xa920a920U struct arm920t_common { + unsigned int common_magic; + struct arm7_9_common arm7_9_common; - uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; uint32_t cp15_control_reg; uint32_t d_fsr; diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 9739fc1f68..0531106562 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -702,7 +702,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm return ERROR_OK; } -static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) +static int arm926ejs_target_create(struct target *target) { struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); @@ -754,8 +754,8 @@ static int arm926ejs_mmu(struct target *target, int *enabled) struct arm926ejs_common *arm926ejs = target_to_arm926(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } *enabled = arm926ejs->armv4_5_mmu.mmu_enabled; return ERROR_OK; diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h index c652a3b092..479128e615 100644 --- a/src/target/arm926ejs.h +++ b/src/target/arm926ejs.h @@ -11,11 +11,12 @@ #include "arm9tdmi.h" #include "armv4_5_mmu.h" -#define ARM926EJS_COMMON_MAGIC 0xa926a926 +#define ARM926EJS_COMMON_MAGIC 0xa926a926U struct arm926ejs_common { + unsigned int common_magic; + struct arm7_9_common arm7_9_common; - uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value); diff --git a/src/target/arm946e.c b/src/target/arm946e.c index d2bccad228..828e70f4bc 100644 --- a/src/target/arm946e.c +++ b/src/target/arm946e.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -44,7 +44,7 @@ static int arm946e_post_debug_entry(struct target *target); static void arm946e_pre_restore_context(struct target *target); static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value); -int arm946e_init_arch_info(struct target *target, +static int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e, struct jtag_tap *tap) { @@ -79,7 +79,7 @@ int arm946e_init_arch_info(struct target *target, return ERROR_OK; } -static int arm946e_target_create(struct target *target, Jim_Interp *interp) +static int arm946e_target_create(struct target *target) { struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common)); @@ -173,7 +173,7 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu return ERROR_OK; } -int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) +static int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -574,7 +574,7 @@ COMMAND_HANDLER(arm946e_handle_cp15) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); return ERROR_TARGET_NOT_HALTED; } @@ -624,7 +624,7 @@ COMMAND_HANDLER(arm946e_handle_idcache) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); return ERROR_TARGET_NOT_HALTED; } @@ -720,7 +720,7 @@ static const struct command_registration arm946e_exec_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -const struct command_registration arm946e_command_handlers[] = { +static const struct command_registration arm946e_command_handlers[] = { { .chain = arm9tdmi_command_handlers, }, diff --git a/src/target/arm946e.h b/src/target/arm946e.h index b205534fd9..0196c2b378 100644 --- a/src/target/arm946e.h +++ b/src/target/arm946e.h @@ -16,11 +16,12 @@ #include "arm9tdmi.h" -#define ARM946E_COMMON_MAGIC 0x20f920f9 +#define ARM946E_COMMON_MAGIC 0x20f920f9U struct arm946e_common { + unsigned int common_magic; + struct arm7_9_common arm7_9_common; - int common_magic; uint32_t cp15_control_reg; uint32_t cp15_cache_info; }; @@ -31,10 +32,4 @@ static inline struct arm946e_common *target_to_arm946(struct target *target) arm7_9_common.arm); } -int arm946e_init_arch_info(struct target *target, - struct arm946e_common *arm946e, struct jtag_tap *tap); -int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value); - -extern const struct command_registration arm946e_command_handlers[]; - #endif /* OPENOCD_TARGET_ARM946E_H */ diff --git a/src/target/arm966e.c b/src/target/arm966e.c index c6eb832f82..b6bcc8ba97 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -38,7 +38,7 @@ int arm966e_init_arch_info(struct target *target, struct arm966e_common *arm966e return ERROR_OK; } -static int arm966e_target_create(struct target *target, Jim_Interp *interp) +static int arm966e_target_create(struct target *target) { struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); @@ -174,8 +174,8 @@ COMMAND_HANDLER(arm966e_handle_cp15_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } /* one or more argument, access a single register (write if second argument is given */ diff --git a/src/target/arm966e.h b/src/target/arm966e.h index e41b850376..be2b3391e8 100644 --- a/src/target/arm966e.h +++ b/src/target/arm966e.h @@ -13,11 +13,12 @@ #include "arm9tdmi.h" -#define ARM966E_COMMON_MAGIC 0x20f920f9 +#define ARM966E_COMMON_MAGIC 0x20f920f9U struct arm966e_common { + unsigned int common_magic; + struct arm7_9_common arm7_9_common; - int common_magic; uint32_t cp15_control_reg; }; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index f672899cd9..8ab12de320 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -57,7 +57,7 @@ static const struct arm9tdmi_vector { {"dabt", ARM9TDMI_DABT_VECTOR}, {"irq", ARM9TDMI_IRQ_VECTOR}, {"fiq", ARM9TDMI_FIQ_VECTOR}, - {0, 0}, + {NULL, 0}, }; int arm9tdmi_examine_debug_reason(struct target *target) @@ -765,7 +765,7 @@ int arm9tdmi_init_arch_info(struct target *target, return ERROR_OK; } -static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) +static int arm9tdmi_target_create(struct target *target) { struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common)); @@ -821,9 +821,9 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) else if (strcmp(CMD_ARGV[0], "none") == 0) { /* do nothing */ } else { - for (unsigned i = 0; i < CMD_ARGC; i++) { + for (unsigned int i = 0; i < CMD_ARGC; i++) { /* go through list of vectors */ - unsigned j; + unsigned int j; for (j = 0; arm9tdmi_vectors[j].name; j++) { if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) { vector_catch_value |= arm9tdmi_vectors[j].value; @@ -850,7 +850,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) } /* output current settings */ - for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) { + for (unsigned int i = 0; arm9tdmi_vectors[i].name; i++) { command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name, (vector_catch_value & arm9tdmi_vectors[i].value) ? "catch" : "don't catch"); diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index ff0d9b5495..67a3fcc577 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin * @@ -50,7 +50,16 @@ /* * Relevant specifications from ARM include: * - * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E + * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031G + * https://developer.arm.com/documentation/ihi0031/latest/ + * + * ARM(tm) Debug Interface v6 Architecture Specification ARM IHI 0074C + * https://developer.arm.com/documentation/ihi0074/latest/ + * + * Note that diagrams B4-1 to B4-7 in both ADI specifications show + * SWCLK signal mostly in wrong polarity. See detailed SWD timing + * https://developer.arm.com/documentation/dui0499/b/arm-dstream-target-interface-connections/swd-timing-requirements + * * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B * * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D @@ -113,7 +122,7 @@ static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar) int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL)); if (retval == ERROR_OK && is_64bit_ap(ap)) { /* See if bits 63:32 of tar is different from last setting */ - if ((ap->tar_value >> 32) != (tar >> 32)) + if (!ap->tar_valid || (ap->tar_value >> 32) != (tar >> 32)) retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32)); } if (retval != ERROR_OK) { @@ -164,6 +173,12 @@ static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap) return 2; case CSW_32BIT: return 4; + case CSW_64BIT: + return 8; + case CSW_128BIT: + return 16; + case CSW_256BIT: + return 32; default: return 0; } @@ -319,12 +334,145 @@ int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, return dap_run(ap->dap); } +/** + * Queue transactions setting up transfer parameters for the + * currently selected MEM-AP. If transfer size or packing + * has not been probed, run the queue, read back CSW and check if the requested + * transfer mode is supported. + * + * @param ap The MEM-AP. + * @param size Transfer width in bytes. Corresponding CSW.Size will be set. + * @param address Transfer address, MEM-AP TAR will be set to this value. + * @param addrinc TAR will be autoincremented. + * @param pack Try to setup packed transfer. + * @param this_size Points to a variable set to the size of single transfer + * or to 4 when transferring packed bytes or halfwords + * + * @return ERROR_OK if the transaction was properly queued, else a fault code. + */ +static int mem_ap_setup_transfer_verify_size_packing(struct adiv5_ap *ap, + unsigned int size, target_addr_t address, + bool addrinc, bool pack, unsigned int *this_size) +{ + int retval; + uint32_t csw_size; + + switch (size) { + case 1: + csw_size = CSW_8BIT; + break; + case 2: + csw_size = CSW_16BIT; + break; + case 4: + csw_size = CSW_32BIT; + break; + case 8: + csw_size = CSW_64BIT; + break; + case 16: + csw_size = CSW_128BIT; + break; + case 32: + csw_size = CSW_256BIT; + break; + default: + LOG_ERROR("Size %u not supported", size); + return ERROR_TARGET_SIZE_NOT_SUPPORTED; + } + + if (!addrinc || size >= 4 + || (ap->packed_transfers_probed && !ap->packed_transfers_supported) + || max_tar_block_size(ap->tar_autoincr_block, address) < 4) + pack = false; + + uint32_t csw_addrinc = pack ? CSW_ADDRINC_PACKED : + addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; + retval = mem_ap_setup_csw(ap, csw_size | csw_addrinc); + if (retval != ERROR_OK) + return retval; + + bool do_probe = !(ap->csw_size_probed_mask & size) + || (pack && !ap->packed_transfers_probed); + if (do_probe) { + uint32_t csw_readback; + retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(ap->dap), &csw_readback); + if (retval != ERROR_OK) + return retval; + + retval = dap_run(ap->dap); + if (retval != ERROR_OK) + return retval; + + bool size_supported = ((csw_readback & CSW_SIZE_MASK) == csw_size); + LOG_DEBUG("AP#0x%" PRIx64 " probed size %u: %s", ap->ap_num, size, + size_supported ? "supported" : "not supported"); + ap->csw_size_probed_mask |= size; + if (size_supported) { + ap->csw_size_supported_mask |= size; + if (pack && !ap->packed_transfers_probed) { + ap->packed_transfers_probed = true; + ap->packed_transfers_supported = + ((csw_readback & CSW_ADDRINC_MASK) == csw_addrinc); + LOG_DEBUG("probed packing: %s", + ap->packed_transfers_supported ? "supported" : "not supported"); + } + } + } + + if (!(ap->csw_size_supported_mask & size)) { + LOG_ERROR("Size %u not supported", size); + return ERROR_TARGET_SIZE_NOT_SUPPORTED; + } + + if (pack && !ap->packed_transfers_supported) + return ERROR_TARGET_PACKING_NOT_SUPPORTED; + + *this_size = pack ? 4 : size; + + return mem_ap_setup_tar(ap, address); +} + +/** + * Queue transactions setting up transfer parameters for the + * currently selected MEM-AP. If transfer size or packing + * has not been probed, run the queue, read back CSW and check if the requested + * transfer mode is supported. + * If packing is not supported fallback and prepare CSW for unpacked transfer. + * + * @param ap The MEM-AP. + * @param size Transfer width in bytes. Corresponding CSW.Size will be set. + * @param address Transfer address, MEM-AP TAR will be set to this value. + * @param addrinc TAR will be autoincremented. + * @param pack Try to setup packed transfer. + * @param this_size Points to a variable set to the size of single transfer + * or to 4 when transferring packed bytes or halfwords + * + * @return ERROR_OK if the transaction was properly queued, else a fault code. + */ +static int mem_ap_setup_transfer_verify_size_packing_fallback(struct adiv5_ap *ap, + unsigned int size, target_addr_t address, + bool addrinc, bool pack, unsigned int *this_size) +{ + int retval = mem_ap_setup_transfer_verify_size_packing(ap, + size, address, + addrinc, pack, this_size); + if (retval == ERROR_TARGET_PACKING_NOT_SUPPORTED) { + /* Retry without packing */ + retval = mem_ap_setup_transfer_verify_size_packing(ap, + size, address, + addrinc, false, this_size); + } + return retval; +} + /** * Synchronous write of a block of memory, using a specific access size. * * @param ap The MEM-AP to access. * @param buffer The data buffer to write. No particular alignment is assumed. - * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param size Which access size to use, in bytes. 1, 2, or 4. + * If large data extension is available also accepts sizes 8, 16, 32. * @param count The number of writes to do (in size units, not bytes). * @param address Address to be written; it must be writable by the currently selected MEM-AP. * @param addrinc Whether the target address should be increased for each write or not. This @@ -336,9 +484,6 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz { struct adiv5_dap *dap = ap->dap; size_t nbytes = size * count; - const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; - uint32_t csw_size; - target_addr_t addr_xor; int retval = ERROR_OK; /* TI BE-32 Quirks mode: @@ -353,83 +498,85 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz * To make writes of size < 4 work as expected, we xor a value with the address before * setting the TAP, and we set the TAP after every transfer rather then relying on * address increment. */ - - if (size == 4) { - csw_size = CSW_32BIT; - addr_xor = 0; - } else if (size == 2) { - csw_size = CSW_16BIT; - addr_xor = dap->ti_be_32_quirks ? 2 : 0; - } else if (size == 1) { - csw_size = CSW_8BIT; - addr_xor = dap->ti_be_32_quirks ? 3 : 0; - } else { - return ERROR_TARGET_UNALIGNED_ACCESS; + target_addr_t ti_be_addr_xor = 0; + target_addr_t ti_be_lane_xor = 0; + if (dap->ti_be_32_quirks) { + ti_be_lane_xor = 3; + switch (size) { + case 1: + ti_be_addr_xor = 3; + break; + case 2: + ti_be_addr_xor = 2; + break; + case 4: + break; + default: + LOG_ERROR("Write more than 32 bits not supported with ti_be_32_quirks"); + return ERROR_TARGET_SIZE_NOT_SUPPORTED; + } } if (ap->unaligned_access_bad && (address % size != 0)) return ERROR_TARGET_UNALIGNED_ACCESS; - while (nbytes > 0) { - uint32_t this_size = size; - - /* Select packed transfer if possible */ - if (addrinc && ap->packed_transfers && nbytes >= 4 - && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { - this_size = 4; - retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); - } else { - retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); - } - - if (retval != ERROR_OK) - break; + /* Nuvoton NPCX quirks prevent packed writes */ + bool pack = !dap->nu_npcx_quirks; - retval = mem_ap_setup_tar(ap, address ^ addr_xor); + while (nbytes > 0) { + unsigned int this_size; + retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap, + size, address ^ ti_be_addr_xor, + addrinc, pack && nbytes >= 4, &this_size); if (retval != ERROR_OK) return retval; /* How many source bytes each transfer will consume, and their location in the DRW, * depends on the type of transfer and alignment. See ARM document IHI0031C. */ - uint32_t outvalue = 0; uint32_t drw_byte_idx = address; - if (dap->ti_be_32_quirks) { - switch (this_size) { - case 4: - outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); - outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); - outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); - outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor); - break; - case 2: - outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor); - outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor); - break; - case 1: - outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor); - break; - } - } else { - switch (this_size) { - case 4: - outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); - outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); - /* fallthrough */ - case 2: - outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); - /* fallthrough */ - case 1: - outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3); + unsigned int drw_ops = DIV_ROUND_UP(this_size, 4); + + while (drw_ops--) { + uint32_t outvalue = 0; + if (dap->nu_npcx_quirks && this_size <= 2) { + switch (this_size) { + case 2: + { + /* Alternate low and high byte to all byte lanes */ + uint32_t low = *buffer++; + uint32_t high = *buffer++; + outvalue |= low << 8 * (drw_byte_idx++ & 3); + outvalue |= high << 8 * (drw_byte_idx++ & 3); + outvalue |= low << 8 * (drw_byte_idx++ & 3); + outvalue |= high << 8 * (drw_byte_idx & 3); + } + break; + case 1: + { + /* Mirror output byte to all byte lanes */ + uint32_t data = *buffer++; + outvalue |= data; + outvalue |= data << 8; + outvalue |= data << 16; + outvalue |= data << 24; + } + } + } else { + unsigned int drw_bytes = MIN(this_size, 4); + while (drw_bytes--) + outvalue |= (uint32_t)*buffer++ << + 8 * ((drw_byte_idx++ & 3) ^ ti_be_lane_xor); } - } - - nbytes -= this_size; - retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue); + retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue); + if (retval != ERROR_OK) + break; + } if (retval != ERROR_OK) break; mem_ap_update_tar_cache(ap); + nbytes -= this_size; if (addrinc) address += this_size; } @@ -454,7 +601,8 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz * * @param ap The MEM-AP to access. * @param buffer The data buffer to receive the data. No particular alignment is assumed. - * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param size Which access size to use, in bytes. 1, 2, or 4. + * If large data extension is available also accepts sizes 8, 16, 32. * @param count The number of reads to do (in size units, not bytes). * @param adr Address to be read; it must be readable by the currently selected MEM-AP. * @param addrinc Whether the target address should be increased after each read or not. This @@ -466,8 +614,6 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint { struct adiv5_dap *dap = ap->dap; size_t nbytes = size * count; - const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; - uint32_t csw_size; target_addr_t address = adr; int retval = ERROR_OK; @@ -476,16 +622,12 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint * They read from the physical address requested, but with DRW byte-reversed. * For example, a byte read from address 0 will place the result in the high bytes of DRW. * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes, - * so avoid them. */ + * so avoid them (ap->packed_transfers is forced to false in mem_ap_init). */ - if (size == 4) - csw_size = CSW_32BIT; - else if (size == 2) - csw_size = CSW_16BIT; - else if (size == 1) - csw_size = CSW_8BIT; - else - return ERROR_TARGET_UNALIGNED_ACCESS; + if (dap->ti_be_32_quirks && size > 4) { + LOG_ERROR("Read more than 32 bits not supported with ti_be_32_quirks"); + return ERROR_TARGET_SIZE_NOT_SUPPORTED; + } if (ap->unaligned_access_bad && (adr % size != 0)) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -493,7 +635,8 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant * over-allocation if packed transfers are going to be used, but determining the real need at * this point would be messy. */ - uint32_t *read_buf = calloc(count, sizeof(uint32_t)); + uint32_t *read_buf = calloc(count, MAX(sizeof(uint32_t), size)); + /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */ uint32_t *read_ptr = read_buf; if (!read_buf) { @@ -505,26 +648,20 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint * useful bytes it contains, and their location in the word, depends on the type of transfer * and alignment. */ while (nbytes > 0) { - uint32_t this_size = size; - - /* Select packed transfer if possible */ - if (addrinc && ap->packed_transfers && nbytes >= 4 - && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { - this_size = 4; - retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); - } else { - retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); - } + unsigned int this_size; + retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap, + size, address, + addrinc, nbytes >= 4, &this_size); if (retval != ERROR_OK) break; - retval = mem_ap_setup_tar(ap, address); - if (retval != ERROR_OK) - break; - retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++); - if (retval != ERROR_OK) - break; + unsigned int drw_ops = DIV_ROUND_UP(this_size, 4); + while (drw_ops--) { + retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++); + if (retval != ERROR_OK) + break; + } nbytes -= this_size; if (addrinc) @@ -543,7 +680,9 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint /* If something failed, read TAR to find out how much data was successfully read, so we can * at least give the caller what we have. */ - if (retval != ERROR_OK) { + if (retval == ERROR_TARGET_SIZE_NOT_SUPPORTED) { + nbytes = 0; + } else if (retval != ERROR_OK) { target_addr_t tar; if (mem_ap_read_tar(ap, &tar) == ERROR_OK) { /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */ @@ -556,39 +695,28 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint } } + target_addr_t ti_be_lane_xor = dap->ti_be_32_quirks ? 3 : 0; + /* Replay loop to populate caller's buffer from the correct word and byte lane */ while (nbytes > 0) { - uint32_t this_size = size; + /* Convert transfers longer than 32-bit on word-at-a-time basis */ + unsigned int this_size = MIN(size, 4); - if (addrinc && ap->packed_transfers && nbytes >= 4 + if (size < 4 && addrinc && ap->packed_transfers_supported && nbytes >= 4 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { - this_size = 4; + this_size = 4; /* Packed read of 4 bytes or 2 halfwords */ } - if (dap->ti_be_32_quirks) { - switch (this_size) { - case 4: - *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); - *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); - /* fallthrough */ - case 2: - *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); - /* fallthrough */ - case 1: - *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); - } - } else { - switch (this_size) { - case 4: - *buffer++ = *read_ptr >> 8 * (address++ & 3); - *buffer++ = *read_ptr >> 8 * (address++ & 3); - /* fallthrough */ - case 2: - *buffer++ = *read_ptr >> 8 * (address++ & 3); - /* fallthrough */ - case 1: - *buffer++ = *read_ptr >> 8 * (address++ & 3); - } + switch (this_size) { + case 4: + *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor); + *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor); + /* fallthrough */ + case 2: + *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor); + /* fallthrough */ + case 1: + *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor); } read_ptr++; @@ -635,7 +763,11 @@ int mem_ap_write_buf_noincr(struct adiv5_ap *ap, */ void dap_invalidate_cache(struct adiv5_dap *dap) { - dap->select = DP_SELECT_INVALID; + dap->select = 0; /* speculate the first AP access will select AP 0, bank 0 */ + dap->select_valid = false; + dap->select1_valid = false; + dap->select_dpbanksel_valid = false; + dap->last_read = NULL; int i; @@ -671,11 +803,12 @@ int dap_dp_init(struct adiv5_dap *dap) dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; /* - * This write operation clears the sticky error bit in jtag mode only and - * is ignored in swd mode. It also powers-up system and debug domains in - * both jtag and swd modes, if not done before. + * This write operation clears the sticky error and overrun bits in jtag + * mode only and is ignored in swd mode. It also powers-up system and + * debug domains in both jtag and swd modes, if not done before. */ - retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR); + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, + dap->dp_ctrl_stat | SSTICKYERR | SSTICKYORUN); if (retval != ERROR_OK) return retval; @@ -763,7 +896,7 @@ int dap_dp_init_or_reconnect(struct adiv5_dap *dap) int mem_ap_init(struct adiv5_ap *ap) { /* check that we support packed transfers */ - uint32_t csw, cfg; + uint32_t cfg; int retval; struct adiv5_dap *dap = ap->dap; @@ -780,30 +913,23 @@ int mem_ap_init(struct adiv5_ap *ap) ap->cfg_reg = cfg; ap->tar_valid = false; ap->csw_value = 0; /* force csw and tar write */ - retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), &csw); - if (retval != ERROR_OK) - return retval; + /* CSW 32-bit size must be supported (IHI 0031F and 0074D). */ + ap->csw_size_supported_mask = BIT(CSW_32BIT); + ap->csw_size_probed_mask = BIT(CSW_32BIT); - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; + /* Suppress probing sizes longer than 32 bit if AP has no large data extension */ + if (!(cfg & MEM_AP_REG_CFG_LD)) + ap->csw_size_probed_mask |= BIT(CSW_64BIT) | BIT(CSW_128BIT) | BIT(CSW_256BIT); - if (csw & CSW_ADDRINC_PACKED) - ap->packed_transfers = true; - else - ap->packed_transfers = false; - - /* Packed transfers on TI BE-32 processors do not work correctly in + /* Both IHI 0031F and 0074D state: Implementations that support transfers + * smaller than a word must support packed transfers. Unfortunately at least + * Cortex-M0 and Cortex-M0+ do not comply with this rule. + * Probe for packed transfers except we know they are broken. + * Packed transfers on TI BE-32 processors do not work correctly in * many cases. */ - if (dap->ti_be_32_quirks) - ap->packed_transfers = false; - - LOG_DEBUG("MEM_AP Packed Transfers: %s", - ap->packed_transfers ? "enabled" : "disabled"); + ap->packed_transfers_supported = false; + ap->packed_transfers_probed = dap->ti_be_32_quirks ? true : false; /* The ARM ADI spec leaves implementation-defined whether unaligned * memory accesses work, only work partially, or cause a sticky error. @@ -1336,11 +1462,13 @@ static const struct dap_part_nums { { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", }, { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", }, { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", }, + { ARM_ID, 0x4bd, "Cortex-R52+ ROM", "(ROM Table)", }, { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", }, { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", }, { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", }, { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", }, { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c9, "STAR ROM", "(ROM Table)", }, { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", }, { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", }, { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", }, @@ -1382,6 +1510,7 @@ static const struct dap_part_nums { { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", }, { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", }, { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", }, + { ARM_ID, 0x9bb, "Cortex-R52+ PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", }, { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", }, { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", }, { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", }, @@ -1411,11 +1540,16 @@ static const struct dap_part_nums { { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", }, { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", }, { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd05, "Cortex-A55 Debug", "(Debug Unit)", }, { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", }, { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", }, { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd16, "Cortex-R52+ Debug", "(Debug Unit)", }, + { ARM_ID, 0xd21, "STAR Debug", "(Debug Unit)", }, + { ARM_ID, 0xd22, "Cortex-M55 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd43, "Cortex-A65AE Debug", "(Debug Unit)", }, { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", }, { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */ { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */ @@ -1435,6 +1569,9 @@ static const struct dap_part_nums { { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", }, { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", }, + { 0x575, 0x132, "STAR SCS", "(System Control Space)", }, + { 0x575, 0x4d2, "Cortex-M52 ROM", "(ROM Table)", }, + { 0x575, 0xd24, "Cortex-M52 Debug", "(Debug Unit)", }, }; static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num) @@ -2230,7 +2367,7 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, switch (n->value) { case CFG_DAP: - if (goi->isconfigure) { + if (goi->is_configure) { Jim_Obj *o_t; struct adiv5_dap *dap; e = jim_getopt_obj(goi, &o_t); @@ -2238,7 +2375,9 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, return e; dap = dap_instance_by_jim_obj(goi->interp, o_t); if (!dap) { - Jim_SetResultString(goi->interp, "DAP name invalid!", -1); + const char *dap_name = Jim_GetString(o_t, NULL); + Jim_SetResultFormatted(goi->interp, "DAP '%s' not found", + dap_name); return JIM_ERR; } if (*dap_p && *dap_p != dap) { @@ -2259,7 +2398,7 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, break; case CFG_AP_NUM: - if (goi->isconfigure) { + if (goi->is_configure) { /* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */ jim_wide ap_num; e = jim_getopt_wide(goi, &ap_num); @@ -2286,7 +2425,7 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'"); /* fall through */ case CFG_BASEADDR: - if (goi->isconfigure) { + if (goi->is_configure) { jim_wide base; e = jim_getopt_wide(goi, &base); if (e != JIM_OK) @@ -2307,23 +2446,26 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, return JIM_ERR; } -int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi) +int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, + struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional) { - struct adiv5_private_config *pc; int e; - pc = (struct adiv5_private_config *)target->private_config; if (!pc) { - pc = calloc(1, sizeof(struct adiv5_private_config)); + pc = (struct adiv5_private_config *)target->private_config; if (!pc) { - LOG_ERROR("Out of memory"); - return JIM_ERR; + pc = calloc(1, sizeof(struct adiv5_private_config)); + if (!pc) { + LOG_ERROR("Out of memory"); + return JIM_ERR; + } + pc->ap_num = DP_APSEL_INVALID; + target->private_config = pc; } - pc->ap_num = DP_APSEL_INVALID; - target->private_config = pc; } - target->has_dap = true; + if (optional == ADI_CONFIGURE_DAP_COMPULSORY) + target->has_dap = true; e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL); if (e != JIM_OK) @@ -2338,11 +2480,17 @@ int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi) } target->tap = pc->dap->tap; target->dap_configured = true; + target->has_dap = true; } return JIM_OK; } +int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi) +{ + return adiv5_jim_configure_ext(target, goi, NULL, ADI_CONFIGURE_DAP_COMPULSORY); +} + int adiv5_verify_config(struct adiv5_private_config *pc) { if (!pc) @@ -2755,6 +2903,13 @@ COMMAND_HANDLER(dap_ti_be_32_quirks_command) "TI BE-32 quirks mode"); } +COMMAND_HANDLER(dap_nu_npcx_quirks_command) +{ + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->nu_npcx_quirks, + "Nuvoton NPCX quirks mode"); +} + const struct command_registration dap_instance_commands[] = { { .name = "info", @@ -2827,5 +2982,12 @@ const struct command_registration dap_instance_commands[] = { .help = "set/get quirks mode for TI TMS450/TMS570 processors", .usage = "[enable]", }, + { + .name = "nu_npcx_quirks", + .handler = dap_nu_npcx_quirks_command, + .mode = COMMAND_CONFIG, + .help = "set/get quirks mode for Nuvoton NPCX controllers", + .usage = "[enable]", + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 7ee6591497..ebd2752bd8 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -97,16 +97,20 @@ #define DP_DLPIDR_PROTVSN 1u -#define DP_SELECT_APSEL 0xFF000000 -#define DP_SELECT_APBANK 0x000000F0 -#define DP_SELECT_DPBANK 0x0000000F -#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */ +#define ADIV5_DP_SELECT_APSEL 0xFF000000 +#define ADIV5_DP_SELECT_APBANK 0x000000F0 +#define DP_SELECT_DPBANK 0x0000000F +/* + * Mask of AP ADDR in select cache, concatenating DP SELECT and DP_SELECT1. + * In case of ADIv5, the mask contains both APSEL and APBANKSEL fields. + */ +#define SELECT_AP_MASK (~(uint64_t)DP_SELECT_DPBANK) -#define DP_APSEL_MAX (255) /* for ADIv5 only */ -#define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */ +#define DP_APSEL_MAX (255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */ +#define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */ -#define DP_TARGETSEL_INVALID 0xFFFFFFFFU -#define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU +#define DP_TARGETSEL_INVALID 0xFFFFFFFFU +#define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U #define DP_TARGETSEL_INSTANCEID_SHIFT 28 @@ -161,6 +165,9 @@ #define CSW_8BIT 0 #define CSW_16BIT 1 #define CSW_32BIT 2 +#define CSW_64BIT 3 +#define CSW_128BIT 4 +#define CSW_256BIT 5 #define CSW_ADDRINC_MASK (3UL << 4) #define CSW_ADDRINC_OFF 0UL #define CSW_ADDRINC_SINGLE (1UL << 4) @@ -265,6 +272,26 @@ struct adiv5_ap { */ uint32_t csw_value; + /** + * Save the supported CSW.Size data types for the MEM-AP. + * Each bit corresponds to a data type. + * 0b1 = Supported data size. 0b0 = Not supported. + * Bit 0 = Byte (8-bits) + * Bit 1 = Halfword (16-bits) + * Bit 2 = Word (32-bits) - always supported by spec. + * Bit 3 = Doubleword (64-bits) + * Bit 4 = 128-bits + * Bit 5 = 256-bits + */ + uint32_t csw_size_supported_mask; + /** + * Probed CSW.Size data types for the MEM-AP. + * Each bit corresponds to a data type. + * 0b1 = Data size has been probed. 0b0 = Not yet probed. + * Bits assigned to sizes same way as above. + */ + uint32_t csw_size_probed_mask; + /** * Cache for (MEM-AP) AP_REG_TAR register value This is written to * configure the address being read or written @@ -282,7 +309,8 @@ struct adiv5_ap { uint32_t tar_autoincr_block; /* true if packed transfers are supported by the MEM-AP */ - bool packed_transfers; + bool packed_transfers_supported; + bool packed_transfers_probed; /* true if unaligned memory access is not supported by the MEM-AP */ bool unaligned_access_bad; @@ -338,11 +366,21 @@ struct adiv5_dap { /* The current manually selected AP by the "dap apsel" command */ uint64_t apsel; + /** Cache for DP SELECT and SELECT1 (ADIv6) register. */ + uint64_t select; + /** Validity of DP SELECT cache. false will force register rewrite */ + bool select_valid; + bool select1_valid; /* ADIv6 only */ /** - * Cache for DP_SELECT register. A value of DP_SELECT_INVALID - * indicates no cached value and forces rewrite of the register. + * Partial DPBANKSEL validity for SWD only. + * ADIv6 line reset sets DP SELECT DPBANKSEL to zero, + * ADIv5 does not. + * We can rely on it for the banked DP register 0 also on ADIv5 + * as ADIv5 has no mapping for DP reg 0 - it is always DPIDR. + * It is important to avoid setting DP SELECT in connection + * reset state before reading DPIDR. */ - uint64_t select; + bool select_dpbanksel_valid; /* information about current pending SWjDP-AHBAP transaction */ uint8_t ack; @@ -359,6 +397,10 @@ struct adiv5_dap { * swizzle appropriately. */ bool ti_be_32_quirks; + /* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios. + * The work around is to repeat the data in all 4 bytes of DRW */ + bool nu_npcx_quirks; + /** * STLINK adapter need to know if last AP operation was read or write, and * in case of write has to flush it with a dummy read from DP_RDBUFF @@ -402,6 +444,9 @@ struct adiv5_dap { * available until run(). */ struct dap_ops { + /** Optional; called once on the first enabled dap before connecting */ + int (*pre_connect_init)(struct adiv5_dap *dap); + /** connect operation for SWD */ int (*connect)(struct adiv5_dap *dap); @@ -409,17 +454,17 @@ struct dap_ops { int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq); /** DP register read. */ - int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg, + int (*queue_dp_read)(struct adiv5_dap *dap, unsigned int reg, uint32_t *data); /** DP register write. */ - int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg, + int (*queue_dp_write)(struct adiv5_dap *dap, unsigned int reg, uint32_t data); /** AP register read. */ - int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg, + int (*queue_ap_read)(struct adiv5_ap *ap, unsigned int reg, uint32_t *data); /** AP register write. */ - int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg, + int (*queue_ap_write)(struct adiv5_ap *ap, unsigned int reg, uint32_t data); /** AP operation abort. */ @@ -451,6 +496,9 @@ enum ap_type { AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8), /* AHB5 with enhanced HPROT Memory-AP */ }; +extern const struct dap_ops jtag_dp_ops; +extern const struct dap_ops swd_dap_ops; + /* Check the ap->cfg_reg Long Address field (bit 1) * * 0b0: The AP only supports physical addresses 32 bits or smaller @@ -505,7 +553,7 @@ static inline int dap_send_sequence(struct adiv5_dap *dap, * @return ERROR_OK for success, else a fault code. */ static inline int dap_queue_dp_read(struct adiv5_dap *dap, - unsigned reg, uint32_t *data) + unsigned int reg, uint32_t *data) { assert(dap->ops); return dap->ops->queue_dp_read(dap, reg, data); @@ -523,7 +571,7 @@ static inline int dap_queue_dp_read(struct adiv5_dap *dap, * @return ERROR_OK for success, else a fault code. */ static inline int dap_queue_dp_write(struct adiv5_dap *dap, - unsigned reg, uint32_t data) + unsigned int reg, uint32_t data) { assert(dap->ops); return dap->ops->queue_dp_write(dap, reg, data); @@ -540,7 +588,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, * @return ERROR_OK for success, else a fault code. */ static inline int dap_queue_ap_read(struct adiv5_ap *ap, - unsigned reg, uint32_t *data) + unsigned int reg, uint32_t *data) { assert(ap->dap->ops); if (ap->refcount == 0) { @@ -560,7 +608,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap, * @return ERROR_OK for success, else a fault code. */ static inline int dap_queue_ap_write(struct adiv5_ap *ap, - unsigned reg, uint32_t data) + unsigned int reg, uint32_t data) { assert(ap->dap->ops); if (ap->refcount == 0) { @@ -611,7 +659,7 @@ static inline int dap_sync(struct adiv5_dap *dap) return ERROR_OK; } -static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, +static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned int reg, uint32_t *value) { int retval; @@ -623,7 +671,7 @@ static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, return dap_run(dap); } -static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, +static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value, int timeout) { assert(timeout > 0); @@ -740,6 +788,15 @@ struct adiv5_private_config { }; extern int adiv5_verify_config(struct adiv5_private_config *pc); + +enum adiv5_configure_dap_optional { + ADI_CONFIGURE_DAP_COMPULSORY = false, + ADI_CONFIGURE_DAP_OPTIONAL = true +}; + +extern int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, + struct adiv5_private_config *pc, + enum adiv5_configure_dap_optional optional); extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi); struct adiv5_mem_ap_spot { diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c index 4ebdd234d1..032e5ac379 100644 --- a/src/target/arm_cti.c +++ b/src/target/arm_cti.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Matthias Welwarsky * @@ -25,7 +25,7 @@ struct arm_cti { struct adiv5_ap *ap; }; -static LIST_HEAD(all_cti); +static OOCD_LIST_HEAD(all_cti); const char *arm_cti_name(struct arm_cti *self) { @@ -157,48 +157,44 @@ int arm_cti_clear_channel(struct arm_cti *self, uint32_t channel) return arm_cti_write_reg(self, CTI_APPCLEAR, CTI_CHNL(channel)); } -static uint32_t cti_regs[28]; - static const struct { uint32_t offset; const char *label; - uint32_t *p_val; } cti_names[] = { - { CTI_CTR, "CTR", &cti_regs[0] }, - { CTI_GATE, "GATE", &cti_regs[1] }, - { CTI_INEN0, "INEN0", &cti_regs[2] }, - { CTI_INEN1, "INEN1", &cti_regs[3] }, - { CTI_INEN2, "INEN2", &cti_regs[4] }, - { CTI_INEN3, "INEN3", &cti_regs[5] }, - { CTI_INEN4, "INEN4", &cti_regs[6] }, - { CTI_INEN5, "INEN5", &cti_regs[7] }, - { CTI_INEN6, "INEN6", &cti_regs[8] }, - { CTI_INEN7, "INEN7", &cti_regs[9] }, - { CTI_INEN8, "INEN8", &cti_regs[10] }, - { CTI_OUTEN0, "OUTEN0", &cti_regs[11] }, - { CTI_OUTEN1, "OUTEN1", &cti_regs[12] }, - { CTI_OUTEN2, "OUTEN2", &cti_regs[13] }, - { CTI_OUTEN3, "OUTEN3", &cti_regs[14] }, - { CTI_OUTEN4, "OUTEN4", &cti_regs[15] }, - { CTI_OUTEN5, "OUTEN5", &cti_regs[16] }, - { CTI_OUTEN6, "OUTEN6", &cti_regs[17] }, - { CTI_OUTEN7, "OUTEN7", &cti_regs[18] }, - { CTI_OUTEN8, "OUTEN8", &cti_regs[19] }, - { CTI_TRIN_STATUS, "TRIN", &cti_regs[20] }, - { CTI_TROUT_STATUS, "TROUT", &cti_regs[21] }, - { CTI_CHIN_STATUS, "CHIN", &cti_regs[22] }, - { CTI_CHOU_STATUS, "CHOUT", &cti_regs[23] }, - { CTI_APPSET, "APPSET", &cti_regs[24] }, - { CTI_APPCLEAR, "APPCLR", &cti_regs[25] }, - { CTI_APPPULSE, "APPPULSE", &cti_regs[26] }, - { CTI_INACK, "INACK", &cti_regs[27] }, + { CTI_CTR, "CTR" }, + { CTI_GATE, "GATE" }, + { CTI_INEN0, "INEN0" }, + { CTI_INEN1, "INEN1" }, + { CTI_INEN2, "INEN2" }, + { CTI_INEN3, "INEN3" }, + { CTI_INEN4, "INEN4" }, + { CTI_INEN5, "INEN5" }, + { CTI_INEN6, "INEN6" }, + { CTI_INEN7, "INEN7" }, + { CTI_INEN8, "INEN8" }, + { CTI_OUTEN0, "OUTEN0" }, + { CTI_OUTEN1, "OUTEN1" }, + { CTI_OUTEN2, "OUTEN2" }, + { CTI_OUTEN3, "OUTEN3" }, + { CTI_OUTEN4, "OUTEN4" }, + { CTI_OUTEN5, "OUTEN5" }, + { CTI_OUTEN6, "OUTEN6" }, + { CTI_OUTEN7, "OUTEN7" }, + { CTI_OUTEN8, "OUTEN8" }, + { CTI_TRIN_STATUS, "TRIN" }, + { CTI_TROUT_STATUS, "TROUT" }, + { CTI_CHIN_STATUS, "CHIN" }, + { CTI_CHOU_STATUS, "CHOUT" }, + { CTI_APPSET, "APPSET" }, + { CTI_APPCLEAR, "APPCLR" }, + { CTI_APPPULSE, "APPPULSE" }, + { CTI_INACK, "INACK" }, + { CTI_DEVCTL, "DEVCTL" }, }; static int cti_find_reg_offset(const char *name) { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(cti_names); i++) { + for (size_t i = 0; i < ARRAY_SIZE(cti_names); i++) { if (!strcmp(name, cti_names[i].label)) return cti_names[i].offset; } @@ -226,22 +222,23 @@ COMMAND_HANDLER(handle_cti_dump) struct arm_cti *cti = CMD_DATA; struct adiv5_ap *ap = cti->ap; int retval = ERROR_OK; + uint32_t values[ARRAY_SIZE(cti_names)]; - for (int i = 0; (retval == ERROR_OK) && (i < (int)ARRAY_SIZE(cti_names)); i++) + for (size_t i = 0; (retval == ERROR_OK) && (i < ARRAY_SIZE(cti_names)); i++) retval = mem_ap_read_u32(ap, - cti->spot.base + cti_names[i].offset, cti_names[i].p_val); + cti->spot.base + cti_names[i].offset, &values[i]); if (retval == ERROR_OK) retval = dap_run(ap->dap); if (retval != ERROR_OK) - return JIM_ERR; + return retval; - for (int i = 0; i < (int)ARRAY_SIZE(cti_names); i++) + for (size_t i = 0; i < ARRAY_SIZE(cti_names); i++) command_print(CMD, "%8.8s (0x%04"PRIx32") 0x%08"PRIx32, - cti_names[i].label, cti_names[i].offset, *cti_names[i].p_val); + cti_names[i].label, cti_names[i].offset, values[i]); - return JIM_OK; + return ERROR_OK; } COMMAND_HANDLER(handle_cti_enable) @@ -323,7 +320,6 @@ COMMAND_HANDLER(handle_cti_ack) int retval = arm_cti_ack_events(cti, 1 << event); - if (retval != ERROR_OK) return retval; @@ -437,49 +433,48 @@ static int cti_configure(struct jim_getopt_info *goi, struct arm_cti *cti) return JIM_OK; } -static int cti_create(struct jim_getopt_info *goi) + +COMMAND_HANDLER(handle_cti_create) { - struct command_context *cmd_ctx; - static struct arm_cti *cti; - Jim_Obj *new_cmd; - Jim_Cmd *cmd; - const char *cp; - int e; - - cmd_ctx = current_command_context(goi->interp); - assert(cmd_ctx); - - if (goi->argc < 3) { - Jim_WrongNumArgs(goi->interp, 1, goi->argv, "?name? ..options..."); - return JIM_ERR; - } - /* COMMAND */ - jim_getopt_obj(goi, &new_cmd); - /* does this command exist? */ - cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE); - if (cmd) { - cp = Jim_GetString(new_cmd, NULL); - Jim_SetResultFormatted(goi->interp, "Command: %s Exists", cp); - return JIM_ERR; + if (CMD_ARGC < 3) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* check if the cti name clashes with an existing command name */ + Jim_Cmd *jimcmd = Jim_GetCommand(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], JIM_NONE); + if (jimcmd) { + command_print(CMD, "Command/cti: %s Exists", CMD_ARGV[0]); + return ERROR_FAIL; } /* Create it */ - cti = calloc(1, sizeof(*cti)); - if (!cti) - return JIM_ERR; + struct arm_cti *cti = calloc(1, sizeof(*cti)); + if (!cti) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } adiv5_mem_ap_spot_init(&cti->spot); /* Do the rest as "configure" options */ - goi->isconfigure = 1; - e = cti_configure(goi, cti); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, CMD_CTX->interp, CMD_ARGC - 1, CMD_JIMTCL_ARGV + 1); + goi.is_configure = 1; + int e = cti_configure(&goi, cti); if (e != JIM_OK) { + int reslen; + const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), &reslen); + if (reslen > 0) + command_print(CMD, "%s", result); free(cti); - return e; + return ERROR_COMMAND_ARGUMENT_INVALID; } - cp = Jim_GetString(new_cmd, NULL); - cti->name = strdup(cp); + cti->name = strdup(CMD_ARGV[0]); + if (!cti->name) { + LOG_ERROR("Out of memory"); + free(cti); + return ERROR_FAIL; + } /* now - create the new cti name command */ const struct command_registration cti_subcommands[] = { @@ -490,7 +485,7 @@ static int cti_create(struct jim_getopt_info *goi) }; const struct command_registration cti_commands[] = { { - .name = cp, + .name = CMD_ARGV[0], .mode = COMMAND_ANY, .help = "cti instance command group", .usage = "", @@ -498,62 +493,51 @@ static int cti_create(struct jim_getopt_info *goi) }, COMMAND_REGISTRATION_DONE }; - e = register_commands_with_data(cmd_ctx, NULL, cti_commands, cti); - if (e != ERROR_OK) - return JIM_ERR; + int retval = register_commands_with_data(CMD_CTX, NULL, cti_commands, cti); + if (retval != ERROR_OK) { + free(cti->name); + free(cti); + return retval; + } list_add_tail(&cti->lh, &all_cti); cti->ap = dap_get_ap(cti->spot.dap, cti->spot.ap_num); if (!cti->ap) { - Jim_SetResultString(goi->interp, "Cannot get AP", -1); - return JIM_ERR; + command_print(CMD, "Cannot get AP"); + free(cti->name); + free(cti); + return ERROR_FAIL; } - return JIM_OK; -} - -static int jim_cti_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 2) { - Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, - "<name> [<cti_options> ...]"); - return JIM_ERR; - } - return cti_create(&goi); + return ERROR_OK; } -static int jim_cti_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(cti_handle_names) { struct arm_cti *obj; - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); - list_for_each_entry(obj, &all_cti, lh) { - Jim_ListAppendElement(interp, Jim_GetResult(interp), - Jim_NewStringObj(interp, obj->name, -1)); - } - return JIM_OK; -} + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + list_for_each_entry(obj, &all_cti, lh) + command_print(CMD, "%s", obj->name); + return ERROR_OK; +} static const struct command_registration cti_subcommand_handlers[] = { { .name = "create", .mode = COMMAND_ANY, - .jim_handler = jim_cti_create, + .handler = handle_cti_create, .usage = "name '-chain-position' name [options ...]", .help = "Creates a new CTI object", }, { .name = "names", .mode = COMMAND_ANY, - .jim_handler = jim_cti_names, + .handler = cti_handle_names, .usage = "", .help = "Lists all registered CTI objects by name", }, diff --git a/src/target/arm_cti.h b/src/target/arm_cti.h index cfcde65608..1513f0254a 100644 --- a/src/target/arm_cti.h +++ b/src/target/arm_cti.h @@ -39,6 +39,7 @@ #define CTI_CHIN_STATUS 0x138 #define CTI_CHOU_STATUS 0x13C #define CTI_GATE 0x140 +#define CTI_DEVCTL 0x150 #define CTI_UNLOCK 0xFB0 #define CTI_CHNL(x) (1 << x) diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index ad23e66110..be5e63c7ca 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Matthias Welwarsky * @@ -18,10 +18,8 @@ #include "transport/transport.h" #include "jtag/interface.h" -static LIST_HEAD(all_dap); +static OOCD_LIST_HEAD(all_dap); -extern const struct dap_ops swd_dap_ops; -extern const struct dap_ops jtag_dp_ops; extern struct adapter_driver *adapter_driver; /* DAP command support */ @@ -93,6 +91,7 @@ static int dap_init_all(void) { struct arm_dap_object *obj; int retval; + bool pre_connect = true; LOG_DEBUG("Initializing all DAPs ..."); @@ -125,6 +124,14 @@ static int dap_init_all(void) is_adiv6(dap) ? "ADIv6" : "ADIv5"); } + if (pre_connect && dap->ops->pre_connect_init) { + retval = dap->ops->pre_connect_init(dap); + if (retval != ERROR_OK) + return retval; + + pre_connect = false; + } + retval = dap->ops->connect(dap); if (retval != ERROR_OK) return retval; @@ -326,61 +333,59 @@ static int dap_check_config(struct adiv5_dap *dap) return ERROR_OK; } -static int dap_create(struct jim_getopt_info *goi) +COMMAND_HANDLER(handle_dap_create) { - struct command_context *cmd_ctx; - static struct arm_dap_object *dap; - Jim_Obj *new_cmd; - Jim_Cmd *cmd; - const char *cp; - int e; + if (CMD_ARGC < 3) + return ERROR_COMMAND_SYNTAX_ERROR; - cmd_ctx = current_command_context(goi->interp); - assert(cmd_ctx); + int retval = ERROR_COMMAND_ARGUMENT_INVALID; - if (goi->argc < 3) { - Jim_WrongNumArgs(goi->interp, 1, goi->argv, "?name? ..options..."); - return JIM_ERR; - } - /* COMMAND */ - jim_getopt_obj(goi, &new_cmd); - /* does this command exist? */ - cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE); - if (cmd) { - cp = Jim_GetString(new_cmd, NULL); - Jim_SetResultFormatted(goi->interp, "Command: %s Exists", cp); - return JIM_ERR; + /* check if the dap name clashes with an existing command name */ + Jim_Cmd *jimcmd = Jim_GetCommand(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], JIM_NONE); + if (jimcmd) { + command_print(CMD, "Command/dap: %s Exists", CMD_ARGV[0]); + return ERROR_FAIL; } /* Create it */ - dap = calloc(1, sizeof(struct arm_dap_object)); - if (!dap) - return JIM_ERR; + struct arm_dap_object *dap = calloc(1, sizeof(struct arm_dap_object)); + if (!dap) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } dap_instance_init(&dap->dap); - cp = Jim_GetString(new_cmd, NULL); - dap->name = strdup(cp); + dap->name = strdup(CMD_ARGV[0]); + if (!dap->name) { + LOG_ERROR("Out of memory"); + free(dap); + return ERROR_FAIL; + } - e = dap_configure(goi, dap); - if (e != JIM_OK) + struct jim_getopt_info goi; + jim_getopt_setup(&goi, CMD_CTX->interp, CMD_ARGC - 1, CMD_JIMTCL_ARGV + 1); + int e = dap_configure(&goi, dap); + if (e != JIM_OK) { + int reslen; + const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), &reslen); + if (reslen > 0) + command_print(CMD, "%s", result); goto err; + } if (!dap->dap.tap) { - Jim_SetResultString(goi->interp, "-chain-position required when creating DAP", -1); - e = JIM_ERR; + command_print(CMD, "-chain-position required when creating DAP"); goto err; } - e = dap_check_config(&dap->dap); - if (e != ERROR_OK) { - e = JIM_ERR; + retval = dap_check_config(&dap->dap); + if (retval != ERROR_OK) goto err; - } struct command_registration dap_create_commands[] = { { - .name = cp, + .name = CMD_ARGV[0], .mode = COMMAND_ANY, .help = "dap instance command group", .usage = "", @@ -393,48 +398,30 @@ static int dap_create(struct jim_getopt_info *goi) if (transport_is_hla()) dap_create_commands[0].chain = NULL; - e = register_commands_with_data(cmd_ctx, NULL, dap_create_commands, dap); - if (e != ERROR_OK) { - e = JIM_ERR; + retval = register_commands_with_data(CMD_CTX, NULL, dap_create_commands, dap); + if (retval != ERROR_OK) goto err; - } list_add_tail(&dap->lh, &all_dap); - return JIM_OK; + return ERROR_OK; err: free(dap->name); free(dap); - return e; + return retval; } -static int jim_dap_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_dap_names) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 2) { - Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, - "<name> [<dap_options> ...]"); - return JIM_ERR; - } - return dap_create(&goi); -} + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; -static int jim_dap_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ struct arm_dap_object *obj; + list_for_each_entry(obj, &all_dap, lh) + command_print(CMD, "%s", obj->name); - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); - list_for_each_entry(obj, &all_dap, lh) { - Jim_ListAppendElement(interp, Jim_GetResult(interp), - Jim_NewStringObj(interp, obj->name, -1)); - } - return JIM_OK; + return ERROR_OK; } COMMAND_HANDLER(handle_dap_init) @@ -493,14 +480,14 @@ static const struct command_registration dap_subcommand_handlers[] = { { .name = "create", .mode = COMMAND_ANY, - .jim_handler = jim_dap_create, + .handler = handle_dap_create, .usage = "name '-chain-position' name", .help = "Creates a new DAP instance", }, { .name = "names", .mode = COMMAND_ANY, - .jim_handler = jim_dap_names, + .handler = handle_dap_names, .usage = "", .help = "Lists all registered DAP instances by name", }, diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 821be48999..8619f8f82e 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * @@ -114,7 +114,7 @@ static int evaluate_pld(uint32_t opcode, if ((opcode & 0x0d30f000) == 0x0510f000) { uint8_t rn; uint8_t u; - unsigned offset; + unsigned int offset; instruction->type = ARM_PLD; rn = (opcode & 0xf0000) >> 16; @@ -266,18 +266,18 @@ static int evaluate_srs(uint32_t opcode, case 0x08400000: snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSRS%s\tSP%s, #%d", + "\tSRS%s\tSP%s, #%" PRIu32, address, opcode, mode, wback, - (unsigned)(opcode & 0x1f)); + opcode & 0x1f); break; case 0x08100000: snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tRFE%s\tr%d%s", + "\tRFE%s\tr%" PRIu32 "%s", address, opcode, mode, - (unsigned)((opcode >> 16) & 0xf), wback); + (opcode >> 16) & 0xf, wback); break; default: return evaluate_unknown(opcode, address, instruction); @@ -701,9 +701,9 @@ static int evaluate_load_store(uint32_t opcode, static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp) { - unsigned rm = (opcode >> 0) & 0xf; - unsigned rd = (opcode >> 12) & 0xf; - unsigned rn = (opcode >> 16) & 0xf; + unsigned int rm = (opcode >> 0) & 0xf; + unsigned int rd = (opcode >> 12) & 0xf; + unsigned int rn = (opcode >> 16) & 0xf; char *type, *rot; switch ((opcode >> 24) & 0x3) { @@ -842,7 +842,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address, /* halfword pack */ if ((opcode & 0x01f00020) == 0x00800000) { char *type, *shift; - unsigned imm = (unsigned) (opcode >> 7) & 0x1f; + unsigned int imm = (opcode >> 7) & 0x1f; if (opcode & (1 << 6)) { type = "TB"; @@ -865,7 +865,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address, /* word saturate */ if ((opcode & 0x01a00020) == 0x00a00000) { char *shift; - unsigned imm = (unsigned) (opcode >> 7) & 0x1f; + unsigned int imm = (opcode >> 7) & 0x1f; if (opcode & (1 << 6)) { shift = "ASR"; @@ -892,7 +892,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address, /* multiplies */ if ((opcode & 0x01f00080) == 0x01000000) { - unsigned rn = (opcode >> 12) & 0xf; + unsigned int rn = (opcode >> 12) & 0xf; if (rn != 0xf) sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d", @@ -925,7 +925,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address, return ERROR_OK; } if ((opcode & 0x01f00000) == 0x01500000) { - unsigned rn = (opcode >> 12) & 0xf; + unsigned int rn = (opcode >> 12) & 0xf; switch (opcode & 0xc0) { case 3: @@ -1001,8 +1001,8 @@ static int evaluate_media(uint32_t opcode, uint32_t address, return ERROR_OK; } if (mnemonic) { - unsigned rm = (opcode >> 0) & 0xf; - unsigned rd = (opcode >> 12) & 0xf; + unsigned int rm = (opcode >> 0) & 0xf; + unsigned int rd = (opcode >> 12) & 0xf; sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd); return ERROR_OK; @@ -2046,8 +2046,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, return evaluate_cdp_mcr_mrc(opcode, address, instruction); } - LOG_ERROR("ARM: should never reach this point (opcode=%08x)", - (unsigned) opcode); + LOG_ERROR("ARM: should never reach this point (opcode=%08" PRIx32 ")", opcode); return -1; } @@ -2748,7 +2747,7 @@ static int evaluate_cond_branch_thumb(uint16_t opcode, static int evaluate_cb_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { - unsigned offset; + unsigned int offset; /* added in Thumb2 */ offset = (opcode >> 3) & 0x1f; @@ -2859,7 +2858,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address, static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { - unsigned cond = (opcode >> 4) & 0x0f; + unsigned int cond = (opcode >> 4) & 0x0f; char *x = "", *y = "", *z = ""; if (opcode & 0x01) diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index 1be567475c..8317da997b 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -171,7 +171,7 @@ struct arm_instruction { uint32_t opcode; /* return value ... Thumb-2 sizes vary */ - unsigned instruction_size; + unsigned int instruction_size; union { struct arm_b_bl_bx_blx_instr b_bl_bx_blx; diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index b5ce4ee5c9..8ab464d0ab 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009 by David Brownell @@ -50,16 +50,38 @@ static int dpm_mrc(struct target *target, int cpnum, if (retval != ERROR_OK) return retval; - LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, - (int) op1, (int) crn, - (int) crm, (int) op2); + LOG_TARGET_DEBUG(target, "MRC p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32, + cpnum, op1, crn, crm, op2); /* read coprocessor register into R0; return via DCC */ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2), value); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); + return retval; +} + +static int dpm_mrrc(struct target *target, int cpnum, + uint32_t op, uint32_t crm, uint64_t *value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + return retval; + + LOG_TARGET_DEBUG(target, "MRRC p%d, %" PRId32 ", r0, r1, c%" PRId32, + cpnum, op, crm); + + /* read coprocessor register into R0, R1; return via DCC */ + retval = dpm->instr_read_data_r0_r1(dpm, + ARMV5_T_MRRC(cpnum, op, 0, 1, crm), + value); + + dpm->finish(dpm); return retval; } @@ -75,16 +97,38 @@ static int dpm_mcr(struct target *target, int cpnum, if (retval != ERROR_OK) return retval; - LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, - (int) op1, (int) crn, - (int) crm, (int) op2); + LOG_TARGET_DEBUG(target, "MCR p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32, + cpnum, op1, crn, crm, op2); /* read DCC into r0; then write coprocessor register from R0 */ retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2), value); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); + return retval; +} + +static int dpm_mcrr(struct target *target, int cpnum, + uint32_t op, uint32_t crm, uint64_t value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + return retval; + + LOG_TARGET_DEBUG(target, "MCRR p%d, %" PRId32 ", r0, r1, c%" PRId32, + cpnum, op, crm); + + /* read DCC into r0, r1; then write coprocessor register from R0, R1 */ + retval = dpm->instr_write_data_r0_r1(dpm, + ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value); + + dpm->finish(dpm); + return retval; } @@ -121,7 +165,7 @@ int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) } /* Read 64bit VFP registers */ -static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { int retval = ERROR_FAIL; uint32_t value_r0, value_r1; @@ -152,15 +196,15 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum) buf_set_u32(r->value + 4, 0, 32, value_r1); r->valid = true; r->dirty = false; - LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name, - (unsigned) value_r0, (unsigned) value_r1); + LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32 ", %8.8" PRIx32, + r->name, value_r0, value_r1); } return retval; } /* just read the register -- rely on the core mode being right */ -int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { uint32_t value; int retval; @@ -192,10 +236,10 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) break; case ARM_STATE_JAZELLE: /* core-specific ... ? */ - LOG_WARNING("Jazelle PC adjustment unknown"); + LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown"); break; default: - LOG_WARNING("unknown core state"); + LOG_TARGET_WARNING(dpm->arm->target, "unknown core state"); break; } break; @@ -220,14 +264,15 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) buf_set_u32(r->value, 0, 32, value); r->valid = true; r->dirty = false; - LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value); + LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32, r->name, + value); } return retval; } /* Write 64bit VFP registers */ -static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { int retval = ERROR_FAIL; uint32_t value_r0 = buf_get_u32(r->value, 0, 32); @@ -256,15 +301,15 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum if (retval == ERROR_OK) { r->dirty = false; - LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name, - (unsigned) value_r0, (unsigned) value_r1); + LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32, + r->name, value_r0, value_r1); } return retval; } /* just write the register -- rely on the core mode being right */ -static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { int retval; uint32_t value = buf_get_u32(r->value, 0, 32); @@ -305,7 +350,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) if (retval == ERROR_OK) { r->dirty = false; - LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value); + LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32, r->name, + value); } return retval; @@ -342,7 +388,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm) return retval; /* read R0 and R1 first (it's used for scratch), then CPSR */ - for (unsigned i = 0; i < 2; i++) { + for (unsigned int i = 0; i < 2; i++) { r = arm->core_cache->reg_list + i; if (!r->valid) { retval = arm_dpm_read_reg(dpm, r, i); @@ -360,7 +406,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm) arm_set_cpsr(arm, cpsr); /* REVISIT we can probably avoid reading R1..R14, saving time... */ - for (unsigned i = 2; i < 16; i++) { + for (unsigned int i = 2; i < 16; i++) { r = arm_reg_current(arm, i); if (r->valid) continue; @@ -378,7 +424,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm) */ fail: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -419,9 +465,8 @@ static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, xp->address, xp->control); if (retval != ERROR_OK) - LOG_ERROR("%s: can't %s HW %spoint %d", + LOG_TARGET_ERROR(dpm->arm->target, "can't %s HW %spoint %d", disable ? "disable" : "enable", - target_name(dpm->arm->target), (xp->number < 16) ? "break" : "watch", xp->number & 0xf); done: @@ -457,7 +502,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) * cope with the hand-crafted breakpoint code. */ if (arm->target->type->add_breakpoint == dpm_add_breakpoint) { - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { struct dpm_bp *dbp = dpm->dbp + i; struct breakpoint *bp = dbp->bp; @@ -469,7 +514,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) } /* enable/disable watchpoints */ - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { struct dpm_wp *dwp = dpm->dwp + i; struct watchpoint *wp = dwp->wp; @@ -494,9 +539,9 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) did_write = false; /* check everything except our scratch registers R0 and R1 */ - for (unsigned i = 2; i < cache->num_regs; i++) { + for (unsigned int i = 2; i < cache->num_regs; i++) { struct arm_reg *r; - unsigned regnum; + unsigned int regnum; /* also skip PC, CPSR, and non-dirty */ if (i == 15) @@ -581,14 +626,14 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) arm->pc->dirty = false; /* flush R0 and R1 (our scratch registers) */ - for (unsigned i = 0; i < 2; i++) { + for (unsigned int i = 0; i < 2; i++) { retval = dpm_write_reg(dpm, &cache->reg_list[i], i); if (retval != ERROR_OK) goto done; cache->reg_list[i].dirty = false; } - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); done: return retval; } @@ -599,7 +644,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) * or MODE_ANY. */ static enum arm_mode dpm_mapmode(struct arm *arm, - unsigned num, enum arm_mode mode) + unsigned int num, enum arm_mode mode) { enum arm_mode amode = arm->core_mode; @@ -626,7 +671,7 @@ static enum arm_mode dpm_mapmode(struct arm *arm, case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR: return mode; default: - LOG_WARNING("invalid register #%u", num); + LOG_TARGET_WARNING(arm->target, "invalid register #%u", num); break; } return ARM_MODE_ANY; @@ -675,10 +720,10 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r, /* always clean up, regardless of error */ if (mode != ARM_MODE_ANY) - /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY); + arm_dpm_modeswitch(dpm, ARM_MODE_ANY); fail: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -717,10 +762,10 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r, /* always clean up, regardless of error */ if (mode != ARM_MODE_ANY) - /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY); + arm_dpm_modeswitch(dpm, ARM_MODE_ANY); fail: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -749,7 +794,7 @@ static int arm_dpm_full_context(struct target *target) * Pick some mode with unread registers and read them all. * Repeat until done. */ - for (unsigned i = 0; i < cache->num_regs; i++) { + for (unsigned int i = 0; i < cache->num_regs; i++) { struct arm_reg *r; if (!cache->reg_list[i].exist || cache->reg_list[i].valid) @@ -787,7 +832,7 @@ static int arm_dpm_full_context(struct target *target) } while (did_read); retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); done: return retval; } @@ -841,7 +886,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, } /* FALL THROUGH */ default: - LOG_ERROR("unsupported {break,watch}point length/alignment"); + LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -855,7 +900,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, xp->control = control; xp->dirty = true; - LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d", + LOG_TARGET_DEBUG(dpm->arm->target, "BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d", xp->address, control, xp->number); /* hardware is updated in write_dirty_registers() */ @@ -875,9 +920,9 @@ static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp) /* FIXME we need a generic solution for software breakpoints. */ if (bp->type == BKPT_SOFT) - LOG_DEBUG("using HW bkpt, not SW..."); + LOG_TARGET_DEBUG(dpm->arm->target, "using HW breakpoint instead of SW"); - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { if (!dpm->dbp[i].bp) { retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp, bp->address, bp->length); @@ -896,7 +941,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp) struct arm_dpm *dpm = arm->dpm; int retval = ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { if (dpm->dbp[i].bp == bp) { dpm->dbp[i].bp = NULL; dpm->dbp[i].bpwp.dirty = true; @@ -910,7 +955,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp) return retval; } -static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, +static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t, struct watchpoint *wp) { int retval; @@ -918,8 +963,8 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, uint32_t control; /* this hardware doesn't support data value matching or masking */ - if (wp->value || wp->mask != ~(uint32_t)0) { - LOG_DEBUG("watchpoint values and masking not supported"); + if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) { + LOG_TARGET_ERROR(dpm->arm->target, "watchpoint values and masking not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -953,7 +998,7 @@ static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp) int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; if (dpm->bpwp_enable) { - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { if (!dpm->dwp[i].wp) { retval = dpm_watchpoint_setup(dpm, i, wp); break; @@ -970,7 +1015,7 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp) struct arm_dpm *dpm = arm->dpm; int retval = ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { if (dpm->dwp[i].wp == wp) { dpm->dwp[i].wp = NULL; dpm->dwp[i].bpwp.dirty = true; @@ -1050,7 +1095,7 @@ int arm_dpm_setup(struct arm_dpm *dpm) { struct arm *arm = dpm->arm; struct target *target = arm->target; - struct reg_cache *cache = 0; + struct reg_cache *cache = NULL; arm->dpm = dpm; @@ -1070,6 +1115,8 @@ int arm_dpm_setup(struct arm_dpm *dpm) /* coprocessor access setup */ arm->mrc = dpm_mrc; arm->mcr = dpm_mcr; + arm->mrrc = dpm_mrrc; + arm->mcrr = dpm_mcrr; /* breakpoint setup -- optional until it works everywhere */ if (!target->type->add_breakpoint) { @@ -1097,8 +1144,8 @@ int arm_dpm_setup(struct arm_dpm *dpm) return ERROR_FAIL; } - LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", - target_name(target), dpm->nbp, dpm->nwp); + LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints", + dpm->nbp, dpm->nwp); /* REVISIT ... and some of those breakpoints could match * execution context IDs... @@ -1115,7 +1162,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm) { /* Disable all breakpoints and watchpoints at startup. */ if (dpm->bpwp_disable) { - unsigned i; + unsigned int i; for (i = 0; i < dpm->nbp; i++) { dpm->dbp[i].bpwp.number = i; @@ -1126,8 +1173,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm) (void) dpm->bpwp_disable(dpm, 16 + i); } } else - LOG_WARNING("%s: can't disable breakpoints and watchpoints", - target_name(dpm->arm->target)); + LOG_TARGET_WARNING(dpm->arm->target, "can't disable breakpoints and watchpoints"); return ERROR_OK; } diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index d35e9f68d6..16c801ea53 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -19,7 +19,7 @@ */ struct dpm_bpwp { - unsigned number; + unsigned int number; uint32_t address; uint32_t control; /* true if hardware state needs flushing */ @@ -72,6 +72,12 @@ struct arm_dpm { int (*instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data); + /** + * Runs two instructions, writing data to R0 and R1 before execution. + */ + int (*instr_write_data_r0_r1)(struct arm_dpm *dpm, + uint32_t opcode, uint64_t data); + /** Runs one instruction, writing data to R0 before execution. */ int (*instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data); @@ -92,11 +98,18 @@ struct arm_dpm { int (*instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data); + /** + * Runs two instructions, reading data from r0 and r1 after + * execution. + */ + int (*instr_read_data_r0_r1)(struct arm_dpm *dpm, + uint32_t opcode, uint64_t *data); + int (*instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data); struct reg *(*arm_reg_current)(struct arm *arm, - unsigned regnum); + unsigned int regnum); /* BREAKPOINT/WATCHPOINT SUPPORT */ @@ -106,7 +119,7 @@ struct arm_dpm { * must currently be disabled. Indices 0..15 are used for * breakpoints; indices 16..31 are for watchpoints. */ - int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, + int (*bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value, uint32_t addr, uint32_t control); /** @@ -114,15 +127,15 @@ struct arm_dpm { * hardware control registers. Indices are the same ones * accepted by bpwp_enable(). */ - int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value); + int (*bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value); /* The breakpoint and watchpoint arrays are private to the * DPM infrastructure. There are nbp indices in the dbp * array. There are nwp indices in the dwp array. */ - unsigned nbp; - unsigned nwp; + unsigned int nbp; + unsigned int nwp; struct dpm_bp *dbp; struct dpm_wp *dwp; @@ -145,7 +158,7 @@ struct arm_dpm { int arm_dpm_setup(struct arm_dpm *dpm); int arm_dpm_initialize(struct arm_dpm *dpm); -int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum); +int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum); int arm_dpm_read_current_registers(struct arm_dpm *dpm); int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode); diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c index 160846283f..e553ec8b87 100644 --- a/src/target/arm_jtag.c +++ b/src/target/arm_jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -19,7 +19,7 @@ #endif int arm_jtag_set_instr_inner(struct jtag_tap *tap, - uint32_t new_instr, void *no_verify_capture, tap_state_t end_state) + uint32_t new_instr, void *no_verify_capture, enum tap_state end_state) { struct scan_field field; uint8_t t[4] = { 0 }; @@ -41,7 +41,7 @@ int arm_jtag_set_instr_inner(struct jtag_tap *tap, return ERROR_OK; } -int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state) +int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, enum tap_state end_state) { int retval = ERROR_OK; diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h index 11b7c3efd7..5356bcf277 100644 --- a/src/target/arm_jtag.h +++ b/src/target/arm_jtag.h @@ -26,10 +26,10 @@ struct arm_jtag { int arm_jtag_set_instr_inner(struct jtag_tap *tap, uint32_t new_instr, void *no_verify_capture, - tap_state_t end_state); + enum tap_state end_state); static inline int arm_jtag_set_instr(struct jtag_tap *tap, - uint32_t new_instr, void *no_verify_capture, tap_state_t end_state) + uint32_t new_instr, void *no_verify_capture, enum tap_state end_state) { /* inline most common code path */ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (new_instr & (BIT(tap->ir_length) - 1))) @@ -39,8 +39,8 @@ static inline int arm_jtag_set_instr(struct jtag_tap *tap, } -int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state); -static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state) +int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, enum tap_state end_state); +static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, enum tap_state end_state) { /* inline most common code path */ int retval = ERROR_OK; diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index c182f41c4e..c8ce51f299 100644 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -187,6 +187,17 @@ (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \ | ((rd) << 12) | ((crn) << 16) | ((op1) << 21)) +/* Move to two ARM registers from coprocessor + * cp: Coprocessor number + * op: Coprocessor opcode + * rt: destination register 1 + * rt2: destination register 2 + * crm: coprocessor source register + */ +#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \ + (0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \ + | ((rt) << 12) | ((rt2) << 16)) + /* Move to coprocessor from ARM register * cp: Coprocessor number * op1: Coprocessor opcode @@ -199,6 +210,17 @@ (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \ | ((rd) << 12) | ((crn) << 16) | ((op1) << 21)) +/* Move to coprocessor from two ARM registers + * cp: Coprocessor number + * op: Coprocessor opcode + * rt: destination register 1 + * rt2: destination register 2 + * crm: coprocessor source register + */ +#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \ + (0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \ + | ((rt) << 12) | ((rt2) << 16)) + /* Breakpoint instruction (ARMv5) * im: 16-bit immediate */ diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index 853e20fa3f..a7c47bf417 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Marvell Technology Group Ltd. * @@ -50,7 +50,7 @@ static int arm_semihosting_resume(struct target *target, int *retval) if (is_armv8(target_to_armv8(target))) { struct armv8_common *armv8 = target_to_armv8(target); if (armv8->last_run_control_op == ARMV8_RUNCONTROL_RESUME) { - *retval = target_resume(target, 1, 0, 0, 0); + *retval = target_resume(target, true, 0, false, false); if (*retval != ERROR_OK) { LOG_ERROR("Failed to resume target"); return 0; @@ -58,7 +58,7 @@ static int arm_semihosting_resume(struct target *target, int *retval) } else if (armv8->last_run_control_op == ARMV8_RUNCONTROL_STEP) target->debug_reason = DBG_REASON_SINGLESTEP; } else { - *retval = target_resume(target, 1, 0, 0, 0); + *retval = target_resume(target, true, 0, false, false); if (*retval != ERROR_OK) { LOG_ERROR("Failed to resume target"); return 0; diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 64240c029e..058e3d38b8 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c index a9f558e124..afdd8ce919 100644 --- a/src/target/arm_tpiu_swo.c +++ b/src/target/arm_tpiu_swo.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /** * @file @@ -40,7 +40,6 @@ /* START_DEPRECATED_TPIU */ #include <target/cortex_m.h> -#include <target/target_type.h> #define MSG "DEPRECATED \'tpiu config\' command: " /* END_DEPRECATED_TPIU */ @@ -127,7 +126,7 @@ struct arm_tpiu_swo_priv_connection { struct arm_tpiu_swo_object *obj; }; -static LIST_HEAD(all_tpiu_swo); +static OOCD_LIST_HEAD(all_tpiu_swo); #define ARM_TPIU_SWO_TRACE_BUF_SIZE 4096 @@ -153,7 +152,7 @@ static int arm_tpiu_swo_poll_trace(void *priv) } } - if (obj->out_filename && obj->out_filename[0] == ':') + if (obj->out_filename[0] == ':') list_for_each_entry(c, &obj->connections, lh) if (connection_write(c->connection, buf, size) != (int)size) LOG_ERROR("Error writing to connection"); /* FIXME: which connection? */ @@ -161,7 +160,7 @@ static int arm_tpiu_swo_poll_trace(void *priv) return ERROR_OK; } -static void arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_tpiu_swo_event event) +static int arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_tpiu_swo_event event) { for (struct arm_tpiu_swo_event_action *ea = obj->event_action; ea; ea = ea->next) { if (ea->event != event) @@ -182,7 +181,7 @@ static void arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_ if (retval == JIM_RETURN) retval = ea->interp->returnCode; if (retval == JIM_OK || retval == ERROR_COMMAND_CLOSE_CONNECTION) - return; + return ERROR_OK; Jim_MakeErrorMessage(ea->interp); LOG_USER("Error executing event %s on TPIU/SWO %s:\n%s", @@ -191,8 +190,10 @@ static void arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_ Jim_GetString(Jim_GetResult(ea->interp), NULL)); /* clean both error code and stacktrace before return */ Jim_Eval(ea->interp, "error \"\" \"\""); - return; + return ERROR_FAIL; } + + return ERROR_OK; } static void arm_tpiu_swo_close_output(struct arm_tpiu_swo_object *obj) @@ -201,7 +202,7 @@ static void arm_tpiu_swo_close_output(struct arm_tpiu_swo_object *obj) fclose(obj->file); obj->file = NULL; } - if (obj->out_filename && obj->out_filename[0] == ':') + if (obj->out_filename[0] == ':') remove_service(TCP_SERVICE_NAME, &obj->out_filename[1]); } @@ -357,7 +358,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s { assert(obj); - if (goi->isconfigure && obj->enabled) { + if (goi->is_configure && obj->enabled) { Jim_SetResultFormatted(goi->interp, "Cannot configure TPIU/SWO; %s is enabled!", obj->name); return JIM_ERR; } @@ -381,7 +382,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s switch (n->value) { case CFG_PORT_WIDTH: - if (goi->isconfigure) { + if (goi->is_configure) { jim_wide port_width; e = jim_getopt_wide(goi, &port_width); if (e != JIM_OK) @@ -398,7 +399,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_PROTOCOL: - if (goi->isconfigure) { + if (goi->is_configure) { struct jim_nvp *p; e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_protocol_opts, &p); if (e != JIM_OK) @@ -417,7 +418,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_FORMATTER: - if (goi->isconfigure) { + if (goi->is_configure) { struct jim_nvp *p; e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_bool_opts, &p); if (e != JIM_OK) @@ -436,7 +437,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_TRACECLKIN: - if (goi->isconfigure) { + if (goi->is_configure) { jim_wide clk; e = jim_getopt_wide(goi, &clk); if (e != JIM_OK) @@ -449,7 +450,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_BITRATE: - if (goi->isconfigure) { + if (goi->is_configure) { jim_wide clk; e = jim_getopt_wide(goi, &clk); if (e != JIM_OK) @@ -462,7 +463,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_OUTFILE: - if (goi->isconfigure) { + if (goi->is_configure) { const char *s; e = jim_getopt_string(goi, &s, NULL); if (e != JIM_OK) @@ -475,12 +476,13 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s return JIM_ERR; } } - free(obj->out_filename); - obj->out_filename = strdup(s); - if (!obj->out_filename) { + char *out_filename = strdup(s); + if (!out_filename) { LOG_ERROR("Out of memory"); return JIM_ERR; } + free(obj->out_filename); + obj->out_filename = out_filename; } else { if (goi->argc) goto err_no_params; @@ -489,7 +491,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s } break; case CFG_EVENT: - if (goi->isconfigure) { + if (goi->is_configure) { if (goi->argc < 2) { Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event ?event-name? ?EVENT-BODY?"); return JIM_ERR; @@ -519,7 +521,7 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s ea = ea->next; } - if (goi->isconfigure) { + if (goi->is_configure) { if (!ea) { ea = calloc(1, sizeof(*ea)); if (!ea) { @@ -552,20 +554,28 @@ static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_s return JIM_ERR; } -static int jim_arm_tpiu_swo_configure(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_arm_tpiu_swo_configure) { - struct command *c = jim_to_command(interp); + struct arm_tpiu_swo_object *obj = CMD_DATA; + + if (!CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + struct jim_getopt_info goi; + jim_getopt_setup(&goi, CMD_CTX->interp, CMD_ARGC, CMD_JIMTCL_ARGV); + goi.is_configure = !strcmp(CMD_NAME, "configure"); - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - goi.isconfigure = !strcmp(c->name, "configure"); - if (goi.argc < 1) { - Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, - "missing: -option ..."); - return JIM_ERR; - } - struct arm_tpiu_swo_object *obj = c->jim_handler_data; - return arm_tpiu_swo_configure(&goi, obj); + int e = arm_tpiu_swo_configure(&goi, obj); + + int reslen; + const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), &reslen); + if (reslen > 0) + command_print(CMD, "%s", result); + + if (e != JIM_OK) + return ERROR_FAIL; + + return ERROR_OK; } static int wrap_write_u32(struct target *target, struct adiv5_ap *tpiu_ap, @@ -595,54 +605,61 @@ static const struct service_driver arm_tpiu_swo_service_driver = { .keep_client_alive_handler = NULL, }; -static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_arm_tpiu_swo_enable) { - struct command *c = jim_to_command(interp); - struct arm_tpiu_swo_object *obj = c->jim_handler_data; - struct command_context *cmd_ctx = current_command_context(interp); + struct arm_tpiu_swo_object *obj = CMD_DATA; uint32_t value; int retval; - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - if (cmd_ctx->mode == COMMAND_CONFIG) { + if (CMD_CTX->mode == COMMAND_CONFIG) { LOG_DEBUG("%s: enable deferred", obj->name); obj->deferred_enable = true; - return JIM_OK; + return ERROR_OK; } if (obj->enabled) - return JIM_OK; + return ERROR_OK; if (transport_is_hla() && obj->spot.ap_num != 0) { - LOG_ERROR("Invalid access port 0x%" PRIx64 ". Only AP#0 allowed with hla transport", obj->spot.ap_num); - return JIM_ERR; + command_print(CMD, + "Invalid access port 0x%" PRIx64 ". Only AP#0 allowed with hla transport", + obj->spot.ap_num); + return ERROR_FAIL; } if (!obj->traceclkin_freq) { - LOG_ERROR("Trace clock-in frequency not set"); - return JIM_ERR; + command_print(CMD, "Trace clock-in frequency not set"); + return ERROR_FAIL; } - if (obj->pin_protocol == TPIU_SPPR_PROTOCOL_MANCHESTER || obj->pin_protocol == TPIU_SPPR_PROTOCOL_UART) - if (!obj->swo_pin_freq) + const bool output_external = !strcmp(obj->out_filename, "external"); + + if (obj->pin_protocol == TPIU_SPPR_PROTOCOL_MANCHESTER || obj->pin_protocol == TPIU_SPPR_PROTOCOL_UART) { + if (!obj->swo_pin_freq) { + if (output_external) { + command_print(CMD, "SWO pin frequency required when using external capturing"); + return ERROR_FAIL; + } + LOG_DEBUG("SWO pin frequency not set, will be autodetected by the adapter"); + } + } - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); /* START_DEPRECATED_TPIU */ if (obj->recheck_ap_cur_target) { - if (strcmp(target->type->name, "cortex_m") && - strcmp(target->type->name, "hla_target")) { + if (strcmp(target_type_name(target), "cortex_m") && + strcmp(target_type_name(target), "hla_target")) { LOG_ERROR(MSG "Current target is not a Cortex-M nor a HLA"); - return JIM_ERR; + return ERROR_FAIL; } if (!target_was_examined(target)) { LOG_ERROR(MSG "Current target not examined yet"); - return JIM_ERR; + return ERROR_FAIL; } struct cortex_m_common *cm = target_to_cm(target); obj->recheck_ap_cur_target = false; @@ -660,18 +677,20 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const if (!obj->ap) { obj->ap = dap_get_ap(obj->spot.dap, obj->spot.ap_num); if (!obj->ap) { - LOG_ERROR("Cannot get AP"); - return JIM_ERR; + command_print(CMD, "Cannot get AP"); + return ERROR_FAIL; } } /* trigger the event before any attempt to R/W in the TPIU/SWO */ - arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_PRE_ENABLE); + retval = arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_PRE_ENABLE); + if (retval != ERROR_OK) + return retval; retval = wrap_read_u32(target, obj->ap, obj->spot.base + TPIU_DEVID_OFFSET, &value); if (retval != ERROR_OK) { - LOG_ERROR("Unable to read %s", obj->name); - return JIM_ERR; + command_print(CMD, "Unable to read %s", obj->name); + return retval; } switch (obj->pin_protocol) { case TPIU_SPPR_PROTOCOL_SYNC: @@ -687,67 +706,67 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const value = 0; } if (!value) { - struct jim_nvp *p; - jim_nvp_value2name(interp, nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol, &p); - LOG_ERROR("%s does not support protocol %s", obj->name, p->name); - return JIM_ERR; + struct jim_nvp *p = jim_nvp_value2name_simple(nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol); + command_print(CMD, "%s does not support protocol %s", obj->name, p->name); + return ERROR_FAIL; } if (obj->pin_protocol == TPIU_SPPR_PROTOCOL_SYNC) { retval = wrap_read_u32(target, obj->ap, obj->spot.base + TPIU_SSPSR_OFFSET, &value); if (retval != ERROR_OK) { - LOG_ERROR("Cannot read TPIU register SSPSR"); - return JIM_ERR; + command_print(CMD, "Cannot read TPIU register SSPSR"); + return retval; } if (!(value & BIT(obj->port_width - 1))) { - LOG_ERROR("TPIU does not support port-width of %d bits", obj->port_width); - return JIM_ERR; + command_print(CMD, "TPIU does not support port-width of %d bits", obj->port_width); + return ERROR_FAIL; } } uint16_t prescaler = 1; /* dummy value */ unsigned int swo_pin_freq = obj->swo_pin_freq; /* could be replaced */ - if (obj->out_filename && strcmp(obj->out_filename, "external") && obj->out_filename[0]) { + if (!output_external) { if (obj->out_filename[0] == ':') { struct arm_tpiu_swo_priv_connection *priv = malloc(sizeof(*priv)); if (!priv) { LOG_ERROR("Out of memory"); - return JIM_ERR; + return ERROR_FAIL; } priv->obj = obj; LOG_INFO("starting trace server for %s on %s", obj->name, &obj->out_filename[1]); retval = add_service(&arm_tpiu_swo_service_driver, &obj->out_filename[1], CONNECTION_LIMIT_UNLIMITED, priv); if (retval != ERROR_OK) { - LOG_ERROR("Can't configure trace TCP port %s", &obj->out_filename[1]); - return JIM_ERR; + command_print(CMD, "Can't configure trace TCP port %s", &obj->out_filename[1]); + return retval; } } else if (strcmp(obj->out_filename, "-")) { obj->file = fopen(obj->out_filename, "ab"); if (!obj->file) { - LOG_ERROR("Can't open trace destination file \"%s\"", obj->out_filename); - return JIM_ERR; + command_print(CMD, "Can't open trace destination file \"%s\"", obj->out_filename); + return ERROR_FAIL; } } retval = adapter_config_trace(true, obj->pin_protocol, obj->port_width, &swo_pin_freq, obj->traceclkin_freq, &prescaler); if (retval != ERROR_OK) { - LOG_ERROR("Failed to start adapter's trace"); + command_print(CMD, "Failed to start adapter's trace"); arm_tpiu_swo_close_output(obj); - return JIM_ERR; + return retval; } if (obj->pin_protocol == TPIU_SPPR_PROTOCOL_MANCHESTER || obj->pin_protocol == TPIU_SPPR_PROTOCOL_UART) if (!swo_pin_freq) { if (obj->swo_pin_freq) - LOG_ERROR("Adapter rejected SWO pin frequency %d Hz", obj->swo_pin_freq); + command_print(CMD, "Adapter rejected SWO pin frequency %d Hz", obj->swo_pin_freq); else - LOG_ERROR("Adapter does not support auto-detection of SWO pin frequency nor a default value"); + command_print(CMD, + "Adapter does not support auto-detection of SWO pin frequency nor a default value"); arm_tpiu_swo_close_output(obj); - return JIM_ERR; + return ERROR_FAIL; } if (obj->swo_pin_freq != swo_pin_freq) @@ -792,17 +811,19 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const if (retval != ERROR_OK) goto error_exit; - arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_POST_ENABLE); + retval = arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_POST_ENABLE); + if (retval != ERROR_OK) + goto error_exit; /* START_DEPRECATED_TPIU */ target_handle_event(target, TARGET_EVENT_TRACE_CONFIG); /* END_DEPRECATED_TPIU */ obj->enabled = true; - return JIM_OK; + return ERROR_OK; error_exit: - LOG_ERROR("Error!"); + command_print(CMD, "Error!"); if (obj->en_capture) { obj->en_capture = false; @@ -811,27 +832,22 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const target_unregister_timer_callback(arm_tpiu_swo_poll_trace, obj); - retval = adapter_config_trace(false, 0, 0, NULL, 0, NULL); - if (retval != ERROR_OK) { - LOG_ERROR("Failed to stop adapter's trace"); - return JIM_ERR; - } + int retval1 = adapter_config_trace(false, 0, 0, NULL, 0, NULL); + if (retval1 != ERROR_OK) + command_print(CMD, "Failed to stop adapter's trace"); } - return JIM_ERR; + return retval; } -static int jim_arm_tpiu_swo_disable(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_arm_tpiu_swo_disable) { - struct command *c = jim_to_command(interp); - struct arm_tpiu_swo_object *obj = c->jim_handler_data; + struct arm_tpiu_swo_object *obj = CMD_DATA; - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; if (!obj->enabled) - return JIM_OK; + return ERROR_OK; obj->enabled = false; arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_PRE_DISABLE); @@ -845,34 +861,33 @@ static int jim_arm_tpiu_swo_disable(Jim_Interp *interp, int argc, Jim_Obj *const int retval = adapter_config_trace(false, 0, 0, NULL, 0, NULL); if (retval != ERROR_OK) { - LOG_ERROR("Failed to stop adapter's trace"); - return JIM_ERR; + command_print(CMD, "Failed to stop adapter's trace"); + return retval; } } arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_POST_DISABLE); /* START_DEPRECATED_TPIU */ - struct command_context *cmd_ctx = current_command_context(interp); - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); target_handle_event(target, TARGET_EVENT_TRACE_CONFIG); /* END_DEPRECATED_TPIU */ - return JIM_OK; + return ERROR_OK; } static const struct command_registration arm_tpiu_swo_instance_command_handlers[] = { { .name = "configure", .mode = COMMAND_ANY, - .jim_handler = jim_arm_tpiu_swo_configure, + .handler = handle_arm_tpiu_swo_configure, .help = "configure a new TPIU/SWO for use", .usage = "[attribute value ...]", }, { .name = "cget", .mode = COMMAND_ANY, - .jim_handler = jim_arm_tpiu_swo_configure, + .handler = handle_arm_tpiu_swo_configure, .help = "returns the specified TPIU/SWO attribute", .usage = "attribute", }, @@ -886,142 +901,129 @@ static const struct command_registration arm_tpiu_swo_instance_command_handlers[ { .name = "enable", .mode = COMMAND_ANY, - .jim_handler = jim_arm_tpiu_swo_enable, + .handler = handle_arm_tpiu_swo_enable, .usage = "", .help = "Enables the TPIU/SWO output", }, { .name = "disable", .mode = COMMAND_EXEC, - .jim_handler = jim_arm_tpiu_swo_disable, + .handler = handle_arm_tpiu_swo_disable, .usage = "", .help = "Disables the TPIU/SWO output", }, COMMAND_REGISTRATION_DONE }; -static int arm_tpiu_swo_create(Jim_Interp *interp, struct arm_tpiu_swo_object *obj) +COMMAND_HANDLER(handle_arm_tpiu_swo_create) { - struct command_context *cmd_ctx; - Jim_Cmd *cmd; - int e; + int retval = ERROR_FAIL; - cmd_ctx = current_command_context(interp); - assert(cmd_ctx); + if (!CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; /* does this command exist? */ - cmd = Jim_GetCommand(interp, Jim_NewStringObj(interp, obj->name, -1), JIM_NONE); - if (cmd) { - Jim_SetResultFormatted(interp, "cannot create TPIU object because a command with name '%s' already exists", - obj->name); - return JIM_ERR; - } - - /* now - create the new tpiu/swo name command */ - const struct command_registration obj_commands[] = { - { - .name = obj->name, - .mode = COMMAND_ANY, - .help = "tpiu/swo instance command group", - .usage = "", - .chain = arm_tpiu_swo_instance_command_handlers, - }, - COMMAND_REGISTRATION_DONE - }; - e = register_commands_with_data(cmd_ctx, NULL, obj_commands, obj); - if (e != ERROR_OK) - return JIM_ERR; - - list_add_tail(&obj->lh, &all_tpiu_swo); - - return JIM_OK; -} - -static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 1) { - Jim_WrongNumArgs(interp, 1, argv, "name ?option option ...?"); - return JIM_ERR; + Jim_Cmd *jimcmd = Jim_GetCommand(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], JIM_NONE); + if (jimcmd) { + command_print(CMD, "cannot create TPIU object because a command with name '%s' already exists", + CMD_ARGV[0]); + return ERROR_FAIL; } struct arm_tpiu_swo_object *obj = calloc(1, sizeof(struct arm_tpiu_swo_object)); if (!obj) { LOG_ERROR("Out of memory"); - return JIM_ERR; + return ERROR_FAIL; } INIT_LIST_HEAD(&obj->connections); adiv5_mem_ap_spot_init(&obj->spot); obj->spot.base = TPIU_SWO_DEFAULT_BASE; obj->port_width = 1; + obj->out_filename = strdup("external"); + if (!obj->out_filename) { + LOG_ERROR("Out of memory"); + goto err_exit; + } - Jim_Obj *n; - jim_getopt_obj(&goi, &n); - obj->name = strdup(Jim_GetString(n, NULL)); + obj->name = strdup(CMD_ARGV[0]); if (!obj->name) { LOG_ERROR("Out of memory"); - free(obj); - return JIM_ERR; + goto err_exit; } /* Do the rest as "configure" options */ - goi.isconfigure = 1; + struct jim_getopt_info goi; + jim_getopt_setup(&goi, CMD_CTX->interp, CMD_ARGC - 1, CMD_JIMTCL_ARGV + 1); + goi.is_configure = 1; int e = arm_tpiu_swo_configure(&goi, obj); + + int reslen; + const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), &reslen); + if (reslen > 0) + command_print(CMD, "%s", result); + if (e != JIM_OK) goto err_exit; if (!obj->spot.dap || obj->spot.ap_num == DP_APSEL_INVALID) { - Jim_SetResultString(goi.interp, "-dap and -ap-num required when creating TPIU", -1); + command_print(CMD, "-dap and -ap-num required when creating TPIU"); goto err_exit; } - e = arm_tpiu_swo_create(goi.interp, obj); - if (e != JIM_OK) + /* now - create the new tpiu/swo name command */ + const struct command_registration obj_commands[] = { + { + .name = obj->name, + .mode = COMMAND_ANY, + .help = "tpiu/swo instance command group", + .usage = "", + .chain = arm_tpiu_swo_instance_command_handlers, + }, + COMMAND_REGISTRATION_DONE + }; + retval = register_commands_with_data(CMD_CTX, NULL, obj_commands, obj); + if (retval != ERROR_OK) goto err_exit; - return JIM_OK; + list_add_tail(&obj->lh, &all_tpiu_swo); + + return ERROR_OK; err_exit: free(obj->name); free(obj->out_filename); free(obj); - return JIM_ERR; + return retval; } -static int jim_arm_tpiu_swo_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_arm_tpiu_swo_names) { struct arm_tpiu_swo_object *obj; - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); - list_for_each_entry(obj, &all_tpiu_swo, lh) { - Jim_ListAppendElement(interp, Jim_GetResult(interp), - Jim_NewStringObj(interp, obj->name, -1)); - } - return JIM_OK; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + list_for_each_entry(obj, &all_tpiu_swo, lh) + command_print(CMD, "%s", obj->name); + + return ERROR_OK; } -static int jim_arm_tpiu_swo_init(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_arm_tpiu_swo_init) { - struct command_context *cmd_ctx = current_command_context(interp); struct arm_tpiu_swo_object *obj; - int retval = JIM_OK; + int retval = ERROR_OK; + + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } list_for_each_entry(obj, &all_tpiu_swo, lh) { if (!obj->deferred_enable) continue; LOG_DEBUG("%s: running enable during init", obj->name); - int retval2 = command_run_linef(cmd_ctx, "%s enable", obj->name); + int retval2 = command_run_linef(CMD_CTX, "%s enable", obj->name); if (retval2 != ERROR_OK) - retval = JIM_ERR; + retval = retval2; } return retval; } @@ -1034,8 +1036,8 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command) struct arm_tpiu_swo_object *obj = NULL; int retval; - if (strcmp(target->type->name, "cortex_m") && - strcmp(target->type->name, "hla_target")) { + if (strcmp(target_type_name(target), "cortex_m") && + strcmp(target_type_name(target), "hla_target")) { LOG_ERROR(MSG "Current target is not a Cortex-M nor a HLA"); return ERROR_FAIL; } @@ -1186,21 +1188,21 @@ static const struct command_registration arm_tpiu_swo_subcommand_handlers[] = { { .name = "create", .mode = COMMAND_ANY, - .jim_handler = jim_arm_tpiu_swo_create, + .handler = handle_arm_tpiu_swo_create, .usage = "name [-dap dap] [-ap-num num] [-baseaddr baseaddr]", .help = "Creates a new TPIU or SWO object", }, { .name = "names", .mode = COMMAND_ANY, - .jim_handler = jim_arm_tpiu_swo_names, + .handler = handle_arm_tpiu_swo_names, .usage = "", .help = "Lists all registered TPIU and SWO objects by name", }, { .name = "init", .mode = COMMAND_EXEC, - .jim_handler = jim_arm_tpiu_swo_init, + .handler = handle_arm_tpiu_swo_init, .usage = "", .help = "Initialize TPIU and SWO", }, diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 2b347924fe..d907615691 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -168,9 +168,9 @@ static const struct { }; /** Map PSR mode bits to the name of an ARM processor operating mode. */ -const char *arm_mode_name(unsigned psr_mode) +const char *arm_mode_name(unsigned int psr_mode) { - for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { if (arm_mode_data[i].psr == psr_mode) return arm_mode_data[i].name; } @@ -179,9 +179,9 @@ const char *arm_mode_name(unsigned psr_mode) } /** Return true iff the parameter denotes a valid ARM processor mode. */ -bool is_arm_mode(unsigned psr_mode) +bool is_arm_mode(unsigned int psr_mode) { - for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { if (arm_mode_data[i].psr == psr_mode) return true; } @@ -248,7 +248,11 @@ enum arm_mode armv4_5_number_to_mode(int number) } static const char *arm_state_strings[] = { - "ARM", "Thumb", "Jazelle", "ThumbEE", + [ARM_STATE_ARM] = "ARM", + [ARM_STATE_THUMB] = "Thumb", + [ARM_STATE_JAZELLE] = "Jazelle", + [ARM_STATE_THUMB_EE] = "ThumbEE", + [ARM_STATE_AARCH64] = "AArch64", }; /* Templates for ARM core registers. @@ -272,8 +276,8 @@ static const struct { * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY. * (Exception modes have both CPSR and SPSR registers ...) */ - unsigned cookie; - unsigned gdb_index; + unsigned int cookie; + unsigned int gdb_index; enum arm_mode mode; } arm_core_regs[] = { /* IMPORTANT: we guarantee that the first eight cached registers @@ -430,6 +434,16 @@ const int armv4_5_core_reg_map[9][17] = { } }; +static const char *arm_core_state_string(struct arm *arm) +{ + if (arm->core_state > ARRAY_SIZE(arm_state_strings)) { + LOG_TARGET_ERROR(arm->target, "core_state exceeds table size"); + return "Unknown"; + } + + return arm_state_strings[arm->core_state]; +} + /** * Configures host-side ARM records to reflect the specified CPSR. * Later, code can use arm_reg_current() to map register numbers @@ -469,22 +483,22 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) if (cpsr & (1 << 5)) { /* T */ if (cpsr & (1 << 24)) { /* J */ - LOG_WARNING("ThumbEE -- incomplete support"); + LOG_TARGET_WARNING(arm->target, "ThumbEE -- incomplete support"); state = ARM_STATE_THUMB_EE; } else state = ARM_STATE_THUMB; } else { if (cpsr & (1 << 24)) { /* J */ - LOG_ERROR("Jazelle state handling is BROKEN!"); + LOG_TARGET_ERROR(arm->target, "Jazelle state handling is broken"); state = ARM_STATE_JAZELLE; } else state = ARM_STATE_ARM; } arm->core_state = state; - LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, + LOG_TARGET_DEBUG(arm->target, "set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr, arm_mode_name(mode), - arm_state_strings[arm->core_state]); + arm_core_state_string(arm)); } /** @@ -499,7 +513,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) * However, R8..R14, and SPSR (arm->spsr) *must* be mapped. * CPSR (arm->cpsr) is also not mapped. */ -struct reg *arm_reg_current(struct arm *arm, unsigned regnum) +struct reg *arm_reg_current(struct arm *arm, unsigned int regnum) { struct reg *r; @@ -507,7 +521,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum) return NULL; if (!arm->map) { - LOG_ERROR("Register map is not available yet, the target is not fully initialised"); + LOG_TARGET_ERROR(arm->target, "Register map is not available yet, the target is not fully initialised"); r = arm->core_cache->reg_list + regnum; } else r = arm->core_cache->reg_list + arm->map[regnum]; @@ -516,7 +530,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum) * that doesn't support it... */ if (!r) { - LOG_ERROR("Invalid CPSR mode"); + LOG_TARGET_ERROR(arm->target, "Invalid CPSR mode"); r = arm->core_cache->reg_list + regnum; } @@ -535,7 +549,7 @@ static struct reg_feature arm_gdb_dummy_fp_features = { * Modern ARM cores use Vector Floating Point (VFP), if they * have any floating point support. VFP is not FPA-compatible. */ -struct reg arm_gdb_dummy_fp_reg = { +static struct reg arm_gdb_dummy_fp_reg = { .name = "GDB dummy FPA register", .value = (uint8_t *) arm_gdb_dummy_fp_value, .valid = true, @@ -552,7 +566,7 @@ static const uint8_t arm_gdb_dummy_fps_value[4]; * Dummy FPA status registers are required to support GDB on ARM. * Register packets require an obsolete FPA status register. */ -struct reg arm_gdb_dummy_fps_reg = { +static struct reg arm_gdb_dummy_fps_reg = { .name = "GDB dummy FPA status register", .value = (uint8_t *) arm_gdb_dummy_fps_value, .valid = true, @@ -578,7 +592,7 @@ static int armv4_5_get_core_reg(struct reg *reg) struct target *target = reg_arch_info->target; if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -600,7 +614,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -617,7 +631,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) */ if (armv4_5_target->core_mode != (enum arm_mode)(value & 0x1f)) { - LOG_DEBUG("changing ARM core mode to '%s'", + LOG_TARGET_DEBUG(target, "changing ARM core mode to '%s'", arm_mode_name(value & 0x1f)); value &= ~((1 << 24) | (1 << 5)); uint8_t t[4]; @@ -784,7 +798,7 @@ int arm_arch_state(struct target *target) struct arm *arm = target_to_arm(target); if (arm->common_magic != ARM_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARM target"); + LOG_TARGET_ERROR(target, "BUG: called for a non-ARM target"); return ERROR_FAIL; } @@ -792,9 +806,9 @@ int arm_arch_state(struct target *target) if (target->semihosting && target->semihosting->hit_fileio) return ERROR_OK; - LOG_USER("target halted in %s state due to %s, current mode: %s\n" + LOG_TARGET_USER(target, "target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s", - arm_state_strings[arm->core_state], + arm_core_state_string(arm), debug_reason_name(target), arm_mode_name(arm->core_mode), buf_get_u32(arm->cpsr->value, 0, 32), @@ -817,8 +831,8 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) } if (target->state != TARGET_HALTED) { - command_print(CMD, "error: target must be halted for register accesses"); - return ERROR_FAIL; + command_print(CMD, "Error: target must be halted for register accesses"); + return ERROR_TARGET_NOT_HALTED; } if (arm->core_type != ARM_CORE_TYPE_STD) { @@ -828,19 +842,19 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) } if (!is_arm_mode(arm->core_mode)) { - LOG_ERROR("not a valid arm core mode - communication failure?"); + command_print(CMD, "not a valid arm core mode - communication failure?"); return ERROR_FAIL; } if (!arm->full_context) { - command_print(CMD, "error: target doesn't support %s", + command_print(CMD, "Error: target doesn't support %s", CMD_NAME); return ERROR_FAIL; } regs = arm->core_cache->reg_list; - for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { + for (unsigned int mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { const char *name; char *sep = "\n"; char *shadow = ""; @@ -875,11 +889,11 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) sep, name, shadow); /* display N rows of up to 4 registers each */ - for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) { + for (unsigned int i = 0; i < arm_mode_data[mode].n_indices; ) { char output[80]; int output_len = 0; - for (unsigned j = 0; j < 4; j++, i++) { + for (unsigned int j = 0; j < 4; j++, i++) { uint32_t value; struct reg *reg = regs; @@ -905,32 +919,33 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) return ERROR_OK; } -COMMAND_HANDLER(handle_armv4_5_core_state_command) +COMMAND_HANDLER(handle_arm_core_state_command) { struct target *target = get_current_target(CMD_CTX); struct arm *arm = target_to_arm(target); + int ret = ERROR_OK; if (!is_arm(arm)) { command_print(CMD, "current target isn't an ARM"); return ERROR_FAIL; } - if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) { - /* armv7m not supported */ - command_print(CMD, "Unsupported Command"); - return ERROR_OK; - } - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "arm") == 0) - arm->core_state = ARM_STATE_ARM; + if (strcmp(CMD_ARGV[0], "arm") == 0) { + if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) { + command_print(CMD, "arm mode not supported on Cortex-M"); + ret = ERROR_FAIL; + } else { + arm->core_state = ARM_STATE_ARM; + } + } if (strcmp(CMD_ARGV[0], "thumb") == 0) arm->core_state = ARM_STATE_THUMB; } - command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]); + command_print(CMD, "core state: %s", arm_core_state_string(arm)); - return ERROR_OK; + return ret; } COMMAND_HANDLER(handle_arm_disassemble_command) @@ -939,7 +954,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command) struct target *target = get_current_target(CMD_CTX); if (!target) { - LOG_ERROR("No target selected"); + command_print(CMD, "No target selected"); return ERROR_FAIL; } @@ -988,35 +1003,38 @@ COMMAND_HANDLER(handle_arm_disassemble_command) #endif } -static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_armv4_5_mcrmrc) { - struct command_context *context; - struct target *target; - struct arm *arm; - int retval; + bool is_mcr = false; + unsigned int arg_cnt = 5; + + if (!strcmp(CMD_NAME, "mcr")) { + is_mcr = true; + arg_cnt = 6; + } - context = current_command_context(interp); - assert(context); + if (arg_cnt != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; - target = get_current_target(context); + struct target *target = get_current_target(CMD_CTX); if (!target) { - LOG_ERROR("%s: no current target", __func__); - return JIM_ERR; + command_print(CMD, "no current target"); + return ERROR_FAIL; } if (!target_was_examined(target)) { - LOG_ERROR("%s: not yet examined", target_name(target)); - return JIM_ERR; + command_print(CMD, "%s: not yet examined", target_name(target)); + return ERROR_TARGET_NOT_EXAMINED; } - arm = target_to_arm(target); + + struct arm *arm = target_to_arm(target); if (!is_arm(arm)) { - LOG_ERROR("%s: not an ARM", target_name(target)); - return JIM_ERR; + command_print(CMD, "%s: not an ARM", target_name(target)); + return ERROR_FAIL; } - if ((argc < 6) || (argc > 7)) { - /* FIXME use the command name to verify # params... */ - LOG_ERROR("%s: wrong number of arguments", __func__); - return JIM_ERR; + if (target->state != TARGET_HALTED) { + command_print(CMD, "Error: [%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; } int cpnum; @@ -1025,95 +1043,156 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) uint32_t crn; uint32_t crm; uint32_t value; - long l; /* NOTE: parameter sequence matches ARM instruction set usage: * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX * The "rX" is necessarily omitted; it uses Tcl mechanisms. */ - retval = Jim_GetLong(interp, argv[1], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "coprocessor", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum); + if (cpnum & ~0xf) { + command_print(CMD, "coprocessor %d out of range", cpnum); + return ERROR_COMMAND_ARGUMENT_INVALID; } - cpnum = l; - retval = Jim_GetLong(interp, argv[2], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0x7) { - LOG_ERROR("%s: %s %d out of range", __func__, - "op1", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1); + if (op1 & ~0x7) { + command_print(CMD, "op1 %d out of range", op1); + return ERROR_COMMAND_ARGUMENT_INVALID; } - op1 = l; - retval = Jim_GetLong(interp, argv[3], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "CRn", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn); + if (crn & ~0xf) { + command_print(CMD, "CRn %d out of range", crn); + return ERROR_COMMAND_ARGUMENT_INVALID; } - crn = l; - retval = Jim_GetLong(interp, argv[4], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0xf) { - LOG_ERROR("%s: %s %d out of range", __func__, - "CRm", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm); + if (crm & ~0xf) { + command_print(CMD, "CRm %d out of range", crm); + return ERROR_COMMAND_ARGUMENT_INVALID; } - crm = l; - retval = Jim_GetLong(interp, argv[5], &l); - if (retval != JIM_OK) - return retval; - if (l & ~0x7) { - LOG_ERROR("%s: %s %d out of range", __func__, - "op2", (int) l); - return JIM_ERR; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2); + if (op2 & ~0x7) { + command_print(CMD, "op2 %d out of range", op2); + return ERROR_COMMAND_ARGUMENT_INVALID; } - op2 = l; - value = 0; - - /* FIXME don't assume "mrc" vs "mcr" from the number of params; - * that could easily be a typo! Check both... - * + /* * FIXME change the call syntax here ... simplest to just pass * the MRC() or MCR() instruction to be executed. That will also * let us support the "mrc2" and "mcr2" opcodes (toggling one bit) * if that's ever needed. */ - if (argc == 7) { - retval = Jim_GetLong(interp, argv[6], &l); - if (retval != JIM_OK) - return retval; - value = l; + if (is_mcr) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value); /* NOTE: parameters reordered! */ /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */ - retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value); + int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value); if (retval != ERROR_OK) - return JIM_ERR; + return retval; } else { + value = 0; /* NOTE: parameters reordered! */ /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */ - retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value); + int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value); + if (retval != ERROR_OK) + return retval; + + command_print(CMD, "0x%" PRIx32, value); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(handle_armv4_5_mcrrmrrc) +{ + bool is_mcrr = false; + unsigned int arg_cnt = 3; + + if (!strcmp(CMD_NAME, "mcrr")) { + is_mcrr = true; + arg_cnt = 4; + } + + if (arg_cnt != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + if (!target) { + command_print(CMD, "no current target"); + return ERROR_FAIL; + } + if (!target_was_examined(target)) { + command_print(CMD, "%s: not yet examined", target_name(target)); + return ERROR_TARGET_NOT_EXAMINED; + } + + struct arm *arm = target_to_arm(target); + if (!is_arm(arm)) { + command_print(CMD, "%s: not an ARM", target_name(target)); + return ERROR_FAIL; + } + + if (target->state != TARGET_HALTED) + return ERROR_TARGET_NOT_HALTED; + + int cpnum; + uint32_t op1; + uint32_t crm; + uint64_t value; + + /* NOTE: parameter sequence matches ARM instruction set usage: + * MCRR pNUM, op1, rX1, rX2, CRm ; write CP from rX1 and rX2 + * MREC pNUM, op1, rX1, rX2, CRm ; read CP into rX1 and rX2 + * The "rXn" are necessarily omitted; they use Tcl mechanisms. + */ + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum); + if (cpnum & ~0xf) { + command_print(CMD, "coprocessor %d out of range", cpnum); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1); + if (op1 & ~0xf) { + command_print(CMD, "op1 %d out of range", op1); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crm); + if (crm & ~0xf) { + command_print(CMD, "CRm %d out of range", crm); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + /* + * FIXME change the call syntax here ... simplest to just pass + * the MRC() or MCR() instruction to be executed. That will also + * let us support the "mrrc2" and "mcrr2" opcodes (toggling one bit) + * if that's ever needed. + */ + if (is_mcrr) { + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], value); + + /* NOTE: parameters reordered! */ + /* ARMV5_T_MCRR(cpnum, op1, crm) */ + int retval = arm->mcrr(target, cpnum, op1, crm, value); + if (retval != ERROR_OK) + return retval; + } else { + value = 0; + /* NOTE: parameters reordered! */ + /* ARMV5_T_MRRC(cpnum, op1, crm) */ + int retval = arm->mrrc(target, cpnum, op1, crm, &value); if (retval != ERROR_OK) - return JIM_ERR; + return retval; - Jim_SetResult(interp, Jim_NewIntObj(interp, value)); + command_print(CMD, "0x%" PRIx64, value); } - return JIM_OK; + return ERROR_OK; } static const struct command_registration arm_exec_command_handlers[] = { @@ -1124,9 +1203,44 @@ static const struct command_registration arm_exec_command_handlers[] = { .help = "display ARM core registers", .usage = "", }, + { + .name = "mcr", + .mode = COMMAND_EXEC, + .handler = handle_armv4_5_mcrmrc, + .help = "write coprocessor register", + .usage = "cpnum op1 CRn CRm op2 value", + }, + { + .name = "mrc", + .mode = COMMAND_EXEC, + .handler = handle_armv4_5_mcrmrc, + .help = "read coprocessor register", + .usage = "cpnum op1 CRn CRm op2", + }, + { + .name = "mcrr", + .mode = COMMAND_EXEC, + .handler = handle_armv4_5_mcrrmrrc, + .help = "write coprocessor 64-bit register", + .usage = "cpnum op1 CRm value", + }, + { + .name = "mrrc", + .mode = COMMAND_EXEC, + .handler = handle_armv4_5_mcrrmrrc, + .help = "read coprocessor 64-bit register", + .usage = "cpnum op1 CRm", + }, + { + .chain = arm_all_profiles_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +const struct command_registration arm_all_profiles_command_handlers[] = { { .name = "core_state", - .handler = handle_armv4_5_core_state_command, + .handler = handle_arm_core_state_command, .mode = COMMAND_EXEC, .usage = "['arm'|'thumb']", .help = "display/change ARM core state", @@ -1138,25 +1252,12 @@ static const struct command_registration arm_exec_command_handlers[] = { .usage = "address [count ['thumb']]", .help = "disassemble instructions", }, - { - .name = "mcr", - .mode = COMMAND_EXEC, - .jim_handler = &jim_mcrmrc, - .help = "write coprocessor register", - .usage = "cpnum op1 CRn CRm op2 value", - }, - { - .name = "mrc", - .mode = COMMAND_EXEC, - .jim_handler = &jim_mcrmrc, - .help = "read coprocessor register", - .usage = "cpnum op1 CRn CRm op2", - }, { .chain = semihosting_common_handlers, }, COMMAND_REGISTRATION_DONE }; + const struct command_registration arm_command_handlers[] = { { .name = "arm", @@ -1177,7 +1278,7 @@ const struct command_registration arm_command_handlers[] = { * same way as a gdb for arm. This can be changed later on. User can still * set the specific architecture variant with the gdb command. */ -const char *arm_get_gdb_arch(struct target *target) +const char *arm_get_gdb_arch(const struct target *target) { return "arm"; } @@ -1190,7 +1291,7 @@ int arm_get_gdb_reg_list(struct target *target, unsigned int i; if (!is_arm_mode(arm->core_mode)) { - LOG_ERROR("not a valid arm core mode - communication failure?"); + LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -1200,11 +1301,11 @@ int arm_get_gdb_reg_list(struct target *target, *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < 16; i++) - (*reg_list)[i] = arm_reg_current(arm, i); + (*reg_list)[i] = arm_reg_current(arm, i); /* For GDB compatibility, take FPA registers size into account and zero-fill it*/ for (i = 16; i < 24; i++) - (*reg_list)[i] = &arm_gdb_dummy_fp_reg; + (*reg_list)[i] = &arm_gdb_dummy_fp_reg; (*reg_list)[24] = &arm_gdb_dummy_fps_reg; (*reg_list)[25] = arm->cpsr; @@ -1229,25 +1330,25 @@ int arm_get_gdb_reg_list(struct target *target, *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < 16; i++) - (*reg_list)[i] = arm_reg_current(arm, i); + (*reg_list)[i] = arm_reg_current(arm, i); for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) { - int reg_index = arm->core_cache->reg_list[i].number; + int reg_index = arm->core_cache->reg_list[i].number; - if (arm_core_regs[i].mode == ARM_MODE_MON + if (arm_core_regs[i].mode == ARM_MODE_MON && arm->core_type != ARM_CORE_TYPE_SEC_EXT && arm->core_type != ARM_CORE_TYPE_VIRT_EXT) - continue; - if (arm_core_regs[i].mode == ARM_MODE_HYP + continue; + if (arm_core_regs[i].mode == ARM_MODE_HYP && arm->core_type != ARM_CORE_TYPE_VIRT_EXT) - continue; - (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]); + continue; + (*reg_list)[reg_index] = &arm->core_cache->reg_list[i]; } /* When we supply the target description, there is no need for fake FPA */ for (i = 16; i < 24; i++) { - (*reg_list)[i] = &arm_gdb_dummy_fp_reg; - (*reg_list)[i]->size = 0; + (*reg_list)[i] = &arm_gdb_dummy_fp_reg; + (*reg_list)[i]->size = 0; } (*reg_list)[24] = &arm_gdb_dummy_fps_reg; (*reg_list)[24]->size = 0; @@ -1261,7 +1362,7 @@ int arm_get_gdb_reg_list(struct target *target, return ERROR_OK; default: - LOG_ERROR("not a valid register class type in query."); + LOG_TARGET_ERROR(target, "not a valid register class type in query"); return ERROR_FAIL; } } @@ -1269,7 +1370,7 @@ int arm_get_gdb_reg_list(struct target *target, /* wait for execution to complete and check exit point */ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, - int timeout_ms, + unsigned int timeout_ms, void *arch_info) { int retval; @@ -1290,8 +1391,7 @@ static int armv4_5_run_algorithm_completion(struct target *target, /* fast exit: ARMv5+ code can use BKPT */ if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) { - LOG_WARNING( - "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", + LOG_TARGET_ERROR(target, "reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32, buf_get_u32(arm->pc->value, 0, 32)); return ERROR_TARGET_TIMEOUT; } @@ -1303,9 +1403,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info, + unsigned int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, - int timeout_ms, void *arch_info)) + unsigned int timeout_ms, void *arch_info)) { struct arm *arm = target_to_arm(target); struct arm_algorithm *arm_algorithm_info = arch_info; @@ -1316,26 +1416,26 @@ int armv4_5_run_algorithm_inner(struct target *target, int i; int retval = ERROR_OK; - LOG_DEBUG("Running algorithm"); + LOG_TARGET_DEBUG(target, "Running algorithm"); if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) { - LOG_ERROR("current target isn't an ARMV4/5 target"); + LOG_TARGET_ERROR(target, "current target isn't an ARMV4/5 target"); return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (run target algo)"); return ERROR_TARGET_NOT_HALTED; } if (!is_arm_mode(arm->core_mode)) { - LOG_ERROR("not a valid arm core mode - communication failure?"); + LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?"); return ERROR_FAIL; } /* armv5 and later can terminate with BKPT instruction; less overhead */ if (!exit_point && arm->arch == ARM_ARCH_V4) { - LOG_ERROR("ARMv4 target needs HW breakpoint location"); + LOG_TARGET_ERROR(target, "ARMv4 target needs HW breakpoint location"); return ERROR_FAIL; } @@ -1369,12 +1469,12 @@ int armv4_5_run_algorithm_inner(struct target *target, struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false); if (!reg) { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } if (reg->size != reg_params[i].size) { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1390,12 +1490,12 @@ int armv4_5_run_algorithm_inner(struct target *target, else if (arm->core_state == ARM_STATE_THUMB) exit_breakpoint_size = 2; else { - LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); + LOG_TARGET_ERROR(target, "BUG: can't execute algorithms when not in ARM or Thumb state"); return ERROR_COMMAND_SYNTAX_ERROR; } if (arm_algorithm_info->core_mode != ARM_MODE_ANY) { - LOG_DEBUG("setting core_mode: 0x%2.2x", + LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x", arm_algorithm_info->core_mode); buf_set_u32(arm->cpsr->value, 0, 5, arm_algorithm_info->core_mode); @@ -1408,12 +1508,12 @@ int armv4_5_run_algorithm_inner(struct target *target, retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD); if (retval != ERROR_OK) { - LOG_ERROR("can't add HW breakpoint to terminate algorithm"); + LOG_TARGET_ERROR(target, "can't add HW breakpoint to terminate algorithm"); return ERROR_TARGET_FAILURE; } } - retval = target_resume(target, 0, entry_point, 1, 1); + retval = target_resume(target, false, entry_point, true, true); if (retval != ERROR_OK) return retval; retval = run_it(target, exit_point, timeout_ms, arch_info); @@ -1441,13 +1541,13 @@ int armv4_5_run_algorithm_inner(struct target *target, reg_params[i].reg_name, false); if (!reg) { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name); retval = ERROR_COMMAND_SYNTAX_ERROR; continue; } if (reg->size != reg_params[i].size) { - LOG_ERROR( + LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); retval = ERROR_COMMAND_SYNTAX_ERROR; @@ -1491,7 +1591,7 @@ int armv4_5_run_algorithm(struct target *target, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, + unsigned int timeout_ms, void *arch_info) { return armv4_5_run_algorithm_inner(target, @@ -1552,7 +1652,7 @@ int arm_checksum_memory(struct target *target, buf_set_u32(reg_params[1].value, 0, 32, count); /* 20 second timeout/megabyte */ - int timeout = 20000 * (1 + (count / (1024 * 1024))); + unsigned int timeout = 20000 * (1 + (count / (1024 * 1024))); /* armv4 must exit using a hardware breakpoint */ if (arm->arch == ARM_ARCH_V4) @@ -1566,7 +1666,7 @@ int arm_checksum_memory(struct target *target, if (retval == ERROR_OK) *checksum = buf_get_u32(reg_params[0].value, 0, 32); else - LOG_ERROR("error executing ARM crc algorithm"); + LOG_TARGET_ERROR(target, "error executing ARM CRC algorithm"); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -1601,7 +1701,7 @@ int arm_blank_check_memory(struct target *target, assert(sizeof(check_code_le) % 4 == 0); if (erased_value != 0xff) { - LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets", + LOG_TARGET_ERROR(target, "Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets", erased_value); return ERROR_FAIL; } @@ -1663,7 +1763,7 @@ int arm_blank_check_memory(struct target *target, static int arm_full_context(struct target *target) { struct arm *arm = target_to_arm(target); - unsigned num_regs = arm->core_cache->num_regs; + unsigned int num_regs = arm->core_cache->num_regs; struct reg *reg = arm->core_cache->reg_list; int retval = ERROR_OK; @@ -1680,7 +1780,15 @@ static int arm_default_mrc(struct target *target, int cpnum, uint32_t crn, uint32_t crm, uint32_t *value) { - LOG_ERROR("%s doesn't implement MRC", target_type_name(target)); + LOG_TARGET_ERROR(target, "%s doesn't implement MRC", target_type_name(target)); + return ERROR_FAIL; +} + +static int arm_default_mrrc(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t *value) +{ + LOG_TARGET_ERROR(target, "%s doesn't implement MRRC", target_type_name(target)); return ERROR_FAIL; } @@ -1689,7 +1797,15 @@ static int arm_default_mcr(struct target *target, int cpnum, uint32_t crn, uint32_t crm, uint32_t value) { - LOG_ERROR("%s doesn't implement MCR", target_type_name(target)); + LOG_TARGET_ERROR(target, "%s doesn't implement MCR", target_type_name(target)); + return ERROR_FAIL; +} + +static int arm_default_mcrr(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t value) +{ + LOG_TARGET_ERROR(target, "%s doesn't implement MCRR", target_type_name(target)); return ERROR_FAIL; } @@ -1712,8 +1828,12 @@ int arm_init_arch_info(struct target *target, struct arm *arm) if (!arm->mrc) arm->mrc = arm_default_mrc; + if (!arm->mrrc) + arm->mrrc = arm_default_mrrc; if (!arm->mcr) arm->mcr = arm_default_mcr; + if (!arm->mcrr) + arm->mcrr = arm_default_mcrr; return ERROR_OK; } diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c index c271c7cf37..e12c43d336 100644 --- a/src/target/armv4_5_cache.c +++ b/src/target/armv4_5_cache.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index b9bc21a8e6..0c09cb4ca7 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -107,8 +107,10 @@ int armv4_5_mmu_read_physical(struct target *target, { int retval; - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; + } /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); @@ -135,8 +137,10 @@ int armv4_5_mmu_write_physical(struct target *target, { int retval; - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; + } /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 9511ed98a0..2bbafd420f 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by David Brownell * @@ -68,13 +68,13 @@ static void armv7a_show_fault_registers(struct target *target) if (retval != ERROR_OK) goto done; - LOG_USER("Data fault registers DFSR: %8.8" PRIx32 + LOG_TARGET_USER(target, "Data fault registers DFSR: %8.8" PRIx32 ", DFAR: %8.8" PRIx32, dfsr, dfar); - LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 + LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32 ", IFAR: %8.8" PRIx32, ifsr, ifar); done: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); } @@ -101,14 +101,14 @@ static int armv7a_read_midr(struct target *target) armv7a->arch = (midr >> 16) & 0xf; armv7a->variant = (midr >> 20) & 0xf; armv7a->implementor = (midr >> 24) & 0xff; - LOG_DEBUG("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32 - ", variant %" PRIx32 ", implementor %" PRIx32, - target->cmd_name, - armv7a->rev, - armv7a->partnum, - armv7a->arch, - armv7a->variant, - armv7a->implementor); + LOG_TARGET_DEBUG(target, + "rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32 + ", variant %" PRIx32 ", implementor %" PRIx32, + armv7a->rev, + armv7a->partnum, + armv7a->arch, + armv7a->variant, + armv7a->implementor); done: dpm->finish(dpm); @@ -134,7 +134,7 @@ int armv7a_read_ttbcr(struct target *target) if (retval != ERROR_OK) goto done; - LOG_DEBUG("ttbcr %" PRIx32, ttbcr); + LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr); ttbcr_n = ttbcr & 0x7; armv7a->armv7a_mmu.ttbcr = ttbcr; @@ -169,7 +169,7 @@ int armv7a_read_ttbcr(struct target *target) armv7a->armv7a_mmu.ttbr_mask[0] = 7 << (32 - ttbcr_n); } - LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32, + LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32, (ttbcr_n != 0) ? "used" : "not used", armv7a->armv7a_mmu.ttbr_mask[0], armv7a->armv7a_mmu.ttbr_mask[1]); @@ -179,59 +179,10 @@ int armv7a_read_ttbcr(struct target *target) return retval; } -/* FIXME: remove it */ -static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way) -{ - struct armv7a_l2x_cache *l2x_cache; - struct target_list *head; - - struct armv7a_common *armv7a = target_to_armv7a(target); - l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache)); - l2x_cache->base = base; - l2x_cache->way = way; - /*LOG_INFO("cache l2 initialized base %x way %d", - l2x_cache->base,l2x_cache->way);*/ - if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) - LOG_INFO("outer cache already initialized\n"); - armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache; - /* initialize all target in this cluster (smp target) - * l2 cache must be configured after smp declaration */ - foreach_smp_target(head, target->smp_targets) { - struct target *curr = head->target; - if (curr != target) { - armv7a = target_to_armv7a(curr); - if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) - LOG_ERROR("smp target : outer cache already initialized\n"); - armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache; - } - } - return JIM_OK; -} - -/* FIXME: remove it */ -COMMAND_HANDLER(handle_cache_l2x) -{ - struct target *target = get_current_target(CMD_CTX); - uint32_t base, way; - - if (CMD_ARGC != 2) - return ERROR_COMMAND_SYNTAX_ERROR; - - /* command_print(CMD, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */ - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way); - - /* AP address is in bits 31:24 of DP_SELECT */ - armv7a_l2x_cache_init(target, base, way); - - return ERROR_OK; -} - int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache) { - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a_cache->outer_cache); + struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache; int cl; @@ -297,14 +248,13 @@ static int armv7a_read_mpidr(struct target *target) /* Is register in Multiprocessing Extensions register format? */ if (mpidr & MPIDR_MP_EXT) { - LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr); + LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr); armv7a->multi_processor_system = (mpidr >> 30) & 1; armv7a->multi_threading_processor = (mpidr >> 24) & 1; armv7a->level2_id = (mpidr >> 16) & 0xf; armv7a->cluster_id = (mpidr >> 8) & 0xf; armv7a->cpu_id = mpidr & 0xf; - LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s", - target_name(target), + LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s", armv7a->level2_id, armv7a->cluster_id, armv7a->cpu_id, @@ -312,7 +262,7 @@ static int armv7a_read_mpidr(struct target *target) armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT"); } else - LOG_ERROR("MPIDR not in multiprocessor format"); + LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format"); done: dpm->finish(dpm); @@ -387,7 +337,7 @@ int armv7a_identify_cache(struct target *target) cache->iminline = 4UL << (ctr & 0xf); cache->dminline = 4UL << ((ctr & 0xf0000) >> 16); - LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32, + LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32, ctr, cache->iminline, cache->dminline); /* retrieve CLIDR @@ -399,7 +349,7 @@ int armv7a_identify_cache(struct target *target) goto done; cache->loc = (clidr & 0x7000000) >> 24; - LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc); + LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc); /* retrieve selected cache for later restore * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */ @@ -427,13 +377,13 @@ int armv7a_identify_cache(struct target *target) goto done; cache->arch[cl].d_u_size = decode_cache_reg(cache_reg); - LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, + LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, cache->arch[cl].d_u_size.index, cache->arch[cl].d_u_size.index_shift, cache->arch[cl].d_u_size.way, cache->arch[cl].d_u_size.way_shift); - LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", + LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", cache->arch[cl].d_u_size.linelen, cache->arch[cl].d_u_size.cachesize, cache->arch[cl].d_u_size.associativity); @@ -447,13 +397,13 @@ int armv7a_identify_cache(struct target *target) goto done; cache->arch[cl].i_size = decode_cache_reg(cache_reg); - LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, + LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, cache->arch[cl].i_size.index, cache->arch[cl].i_size.index_shift, cache->arch[cl].i_size.way, cache->arch[cl].i_size.way_shift); - LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", + LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", cache->arch[cl].i_size.linelen, cache->arch[cl].i_size.cachesize, cache->arch[cl].i_size.associativity); @@ -473,7 +423,7 @@ int armv7a_identify_cache(struct target *target) /* if no l2 cache initialize l1 data cache flush function function */ if (!armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) { armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = - armv7a_cache_auto_flush_all_data; + armv7a_cache_flush_all_data; } armv7a->armv7a_mmu.armv7a_cache.info = 1; @@ -494,7 +444,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable) armv7a->debug_base + CPUDBG_VCR, &vcr); if (ret < 0) { - LOG_ERROR("Failed to read VCR register\n"); + LOG_TARGET_ERROR(target, "Failed to read VCR register"); return ret; } @@ -507,7 +457,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable) armv7a->debug_base + CPUDBG_VCR, vcr); if (ret < 0) - LOG_ERROR("Failed to write VCR register\n"); + LOG_TARGET_ERROR(target, "Failed to write VCR register"); return ret; } @@ -525,7 +475,6 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a) armv7a->armv7a_mmu.armv7a_cache.info = -1; armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL; - armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1; return ERROR_OK; } @@ -539,18 +488,18 @@ int armv7a_arch_state(struct target *target) struct arm *arm = &armv7a->arm; if (armv7a->common_magic != ARMV7_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARMv7A target"); + LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target"); return ERROR_COMMAND_SYNTAX_ERROR; } arm_arch_state(target); if (armv7a->is_armv7r) { - LOG_USER("D-Cache: %s, I-Cache: %s", + LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s", state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); } else { - LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", + LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s", state[armv7a->armv7a_mmu.mmu_enabled], state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); @@ -562,33 +511,7 @@ int armv7a_arch_state(struct target *target) return ERROR_OK; } -static const struct command_registration l2_cache_commands[] = { - { - .name = "l2x", - .handler = handle_cache_l2x, - .mode = COMMAND_EXEC, - .help = "configure l2x cache", - .usage = "[base_addr] [number_of_way]", - }, - COMMAND_REGISTRATION_DONE - -}; - -static const struct command_registration l2x_cache_command_handlers[] = { - { - .name = "cache_config", - .mode = COMMAND_EXEC, - .help = "cache configuration for a target", - .usage = "", - .chain = l2_cache_commands, - }, - COMMAND_REGISTRATION_DONE -}; - const struct command_registration armv7a_command_handlers[] = { - { - .chain = l2x_cache_command_handlers, - }, { .chain = arm7a_cache_command_handlers, }, diff --git a/src/target/armv7a.h b/src/target/armv7a.h index ebd38f0f68..2706c4629b 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -19,7 +19,7 @@ enum { ARM_CPSR = 16 }; -#define ARMV7_COMMON_MAGIC 0x0A450999 +#define ARMV7_COMMON_MAGIC 0x0A450999U /* VA to PA translation operations opc2 values*/ #define V2PCWPR 0 @@ -65,10 +65,8 @@ struct armv7a_cache_common { struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */ int i_cache_enabled; int d_u_cache_enabled; - int auto_cache_enabled; /* openocd automatic - * cache handling */ /* outer unified cache if some */ - void *outer_cache; + struct armv7a_l2x_cache *outer_cache; int (*flush_all_data_cache)(struct target *target); }; @@ -87,8 +85,9 @@ struct armv7a_mmu_common { }; struct armv7a_common { + unsigned int common_magic; + struct arm arm; - int common_magic; struct reg_cache *core_cache; /* Core Debug Unit */ diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index 460e334549..f2f1097c5a 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Oleksij Rempel * @@ -22,7 +22,7 @@ static int armv7a_l1_d_cache_sanity_check(struct target *target) struct armv7a_common *armv7a = target_to_armv7a(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -40,7 +40,7 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target) struct armv7a_common *armv7a = target_to_armv7a(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -118,20 +118,19 @@ static int armv7a_l1_d_cache_clean_inval_all(struct target *target) return retval; } -int armv7a_cache_auto_flush_all_data(struct target *target) +int armv7a_cache_flush_all_data(struct target *target) { int retval = ERROR_FAIL; - struct armv7a_common *armv7a = target_to_armv7a(target); - - if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) - return ERROR_OK; if (target->smp) { struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - if (curr->state == TARGET_HALTED) - retval = armv7a_l1_d_cache_clean_inval_all(curr); + if (curr->state == TARGET_HALTED) { + int retval1 = armv7a_l1_d_cache_clean_inval_all(curr); + if (retval1 != ERROR_OK) + retval = retval1; + } } } else retval = armv7a_l1_d_cache_clean_inval_all(target); @@ -391,27 +390,6 @@ int armv7a_cache_flush_virt(struct target *target, uint32_t virt, return ERROR_OK; } -/* - * We assume that target core was chosen correctly. It means if same data - * was handled by two cores, other core will loose the changes. Since it - * is impossible to know (FIXME) which core has correct data, keep in mind - * that some kind of data lost or corruption is possible. - * Possible scenario: - * - core1 loaded and changed data on 0x12345678 - * - we halted target and modified same data on core0 - * - data on core1 will be lost. - */ -int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, - uint32_t size) -{ - struct armv7a_common *armv7a = target_to_armv7a(target); - - if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) - return ERROR_OK; - - return armv7a_cache_flush_virt(target, virt, size); -} - COMMAND_HANDLER(arm7a_l1_cache_info_cmd) { struct target *target = get_current_target(CMD_CTX); @@ -493,28 +471,6 @@ COMMAND_HANDLER(arm7a_l1_i_cache_inval_virt_cmd) return armv7a_l1_i_cache_inval_virt(target, virt, size); } -COMMAND_HANDLER(arm7a_cache_disable_auto_cmd) -{ - struct target *target = get_current_target(CMD_CTX); - struct armv7a_common *armv7a = target_to_armv7a(target); - - if (CMD_ARGC == 0) { - command_print(CMD, "auto cache is %s", - armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled ? "enabled" : "disabled"); - return ERROR_OK; - } - - if (CMD_ARGC == 1) { - uint32_t set; - - COMMAND_PARSE_ENABLE(CMD_ARGV[0], set); - armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = !!set; - return ERROR_OK; - } - - return ERROR_COMMAND_SYNTAX_ERROR; -} - static const struct command_registration arm7a_l1_d_cache_commands[] = { { .name = "flush_all", @@ -584,13 +540,6 @@ static const struct command_registration arm7a_l1_di_cache_group_handlers[] = { }; static const struct command_registration arm7a_cache_group_handlers[] = { - { - .name = "auto", - .handler = arm7a_cache_disable_auto_cmd, - .mode = COMMAND_ANY, - .help = "disable or enable automatic cache handling.", - .usage = "(1|0)", - }, { .name = "l1", .mode = COMMAND_ANY, diff --git a/src/target/armv7a_cache.h b/src/target/armv7a_cache.h index 17ec5e6de1..c4637c5d30 100644 --- a/src/target/armv7a_cache.h +++ b/src/target/armv7a_cache.h @@ -20,9 +20,7 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt, int armv7a_l1_i_cache_inval_all(struct target *target); int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size); -int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, - uint32_t size); -int armv7a_cache_auto_flush_all_data(struct target *target); +int armv7a_cache_flush_all_data(struct target *target); int armv7a_cache_flush_virt(struct target *target, uint32_t virt, uint32_t size); extern const struct command_registration arm7a_cache_command_handlers[]; diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c index 4c5dbeee69..bc60e6d193 100644 --- a/src/target/armv7a_cache_l2x.c +++ b/src/target/armv7a_cache_l2x.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by Oleksij Rempel * @@ -21,8 +21,8 @@ static int arm7a_l2x_sanity_check(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a->armv7a_mmu.armv7a_cache.outer_cache); + struct armv7a_l2x_cache *l2x_cache = + armv7a->armv7a_mmu.armv7a_cache.outer_cache; if (target->state != TARGET_HALTED) { LOG_ERROR("%s: target not halted", __func__); @@ -42,8 +42,8 @@ static int arm7a_l2x_sanity_check(struct target *target) int arm7a_l2x_flush_all_data(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a->armv7a_mmu.armv7a_cache.outer_cache); + struct armv7a_l2x_cache *l2x_cache = + armv7a->armv7a_mmu.armv7a_cache.outer_cache; uint32_t l2_way_val; int retval; @@ -62,8 +62,8 @@ int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt, uint32_t size) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a->armv7a_mmu.armv7a_cache.outer_cache); + struct armv7a_l2x_cache *l2x_cache = + armv7a->armv7a_mmu.armv7a_cache.outer_cache; /* FIXME: different controllers have different linelen? */ uint32_t i, linelen = 32; int retval; @@ -97,8 +97,8 @@ static int armv7a_l2x_cache_inval_virt(struct target *target, target_addr_t virt uint32_t size) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a->armv7a_mmu.armv7a_cache.outer_cache); + struct armv7a_l2x_cache *l2x_cache = + armv7a->armv7a_mmu.armv7a_cache.outer_cache; /* FIXME: different controllers have different linelen */ uint32_t i, linelen = 32; int retval; @@ -132,8 +132,8 @@ static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt unsigned int size) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a->armv7a_mmu.armv7a_cache.outer_cache); + struct armv7a_l2x_cache *l2x_cache = + armv7a->armv7a_mmu.armv7a_cache.outer_cache; /* FIXME: different controllers have different linelen */ uint32_t i, linelen = 32; int retval; @@ -166,8 +166,7 @@ static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache) { - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) - (armv7a_cache->outer_cache); + struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache; if (armv7a_cache->info == -1) { command_print(cmd, "cache not yet identified"); diff --git a/src/target/armv7a_cache_l2x.h b/src/target/armv7a_cache_l2x.h index d5f1a6f0e5..ea726ec58e 100644 --- a/src/target/armv7a_cache_l2x.h +++ b/src/target/armv7a_cache_l2x.h @@ -122,16 +122,16 @@ struct outer_cache_fns { void (*resume)(void); /* This is an ARM L2C thing */ - void (*write_sec)(unsigned long, unsigned); + void (*write_sec)(unsigned long, unsigned int); void (*configure)(const struct l2x0_regs *); }; struct l2c_init_data { const char *type; - unsigned way_size_0; - unsigned num_lock; + unsigned int way_size_0; + unsigned int num_lock; - void (*enable)(uint32_t, uint32_t, unsigned); + void (*enable)(uint32_t, uint32_t, unsigned int); void (*fixup)(uint32_t, uint32_t, struct outer_cache_fns *); void (*save)(uint32_t); void (*configure)(uint32_t); diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c index 3f89e14c88..43b5dae8ef 100644 --- a/src/target/armv7a_mmu.c +++ b/src/target/armv7a_mmu.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Matthias Welwarsky * @@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table) /* skip empty entries in the first level table */ if ((first_lvl_descriptor & 3) == 0) { pt_idx++; - } else - if ((first_lvl_descriptor & 0x40002) == 2) { + } else if ((first_lvl_descriptor & 0x40002) == 2) { /* section descriptor */ uint32_t va_range = 1024*1024-1; /* 1MB range */ uint32_t va_start = pt_idx << 20; @@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table) LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s", va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe)); pt_idx++; - } else - if ((first_lvl_descriptor & 0x40002) == 0x40002) { + } else if ((first_lvl_descriptor & 0x40002) == 0x40002) { /* supersection descriptor */ uint32_t va_range = 16*1024*1024-1; /* 16MB range */ uint32_t va_start = pt_idx << 20; @@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table) if ((second_lvl_descriptor & 3) == 0) { /* skip entry */ pt2_idx++; - } else - if ((second_lvl_descriptor & 3) == 1) { + } else if ((second_lvl_descriptor & 3) == 1) { /* large page */ uint32_t va_range = 64*1024-1; /* 64KB range */ uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12); diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 4c46240f89..dc2d84fe15 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -53,7 +53,7 @@ const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = { ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC, - ARMV7M_xPSR, + ARMV7M_XPSR, }; /* MSP is used in handler and some thread modes */ @@ -62,7 +62,29 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = { ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC, - ARMV7M_xPSR, + ARMV7M_XPSR, +}; + +static struct reg_data_type_bitfield armv8m_vpr_bits[] = { + { 0, 15, REG_TYPE_UINT }, + { 16, 19, REG_TYPE_UINT }, + { 20, 23, REG_TYPE_UINT }, +}; + +static struct reg_data_type_flags_field armv8m_vpr_fields[] = { + { "P0", armv8m_vpr_bits + 0, armv8m_vpr_fields + 1, }, + { "MASK01", armv8m_vpr_bits + 1, armv8m_vpr_fields + 2, }, + { "MASK23", armv8m_vpr_bits + 2, NULL }, +}; + +static struct reg_data_type_flags armv8m_vpr_flags[] = { + { 4, armv8m_vpr_fields }, +}; + +static struct reg_data_type armv8m_flags_vpr[] = { + { REG_TYPE_ARCH_DEFINED, "vpr_reg", REG_TYPE_CLASS_FLAGS, + { .reg_type_flags = armv8m_vpr_flags }, + }, }; /* @@ -74,36 +96,37 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = { * doesn't include basepri or faultmask registers. */ static const struct { - unsigned id; + unsigned int id; const char *name; - unsigned bits; + unsigned int bits; enum reg_type type; const char *group; const char *feature; + struct reg_data_type *data_type; } armv7m_regs[] = { - { ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" }, - { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" }, - - { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + { ARMV7M_XPSR, "xpsr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, }, + + { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system", NULL, }, + { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system", NULL, }, /* A working register for packing/unpacking special regs, hidden from gdb */ - { ARMV7M_PMSK_BPRI_FLTMSK_CTRL, "pmsk_bpri_fltmsk_ctrl", 32, REG_TYPE_INT, NULL, NULL }, + { ARMV7M_PMSK_BPRI_FLTMSK_CTRL, "pmsk_bpri_fltmsk_ctrl", 32, REG_TYPE_INT, NULL, NULL, NULL }, /* WARNING: If you use armv7m_write_core_reg() on one of 4 following * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL @@ -111,52 +134,54 @@ static const struct { * To trigger write to CPU HW register, add * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,); */ - { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - - /* ARMv8-M specific registers */ - { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, - - { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL }, - { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - - { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL }, - { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, - { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, }, + { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, }, + { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, }, + { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, }, + + /* ARMv8-M security extension (TrustZone) specific registers */ + { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, }, + + { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL, NULL, }, + { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + + { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL, NULL, }, + { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, + { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, }, /* FPU registers */ - { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - { ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, - - { ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" }, + { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + { ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, }, + + { ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp", NULL, }, + + { ARMV8M_VPR, "vpr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.m-profile-mve", armv8m_flags_vpr, }, }; #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) @@ -171,7 +196,7 @@ int armv7m_restore_context(struct target *target) struct armv7m_common *armv7m = target_to_armv7m(target); struct reg_cache *cache = armv7m->arm.core_cache; - LOG_DEBUG(" "); + LOG_TARGET_DEBUG(target, " "); if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); @@ -182,8 +207,11 @@ int armv7m_restore_context(struct target *target) for (i = cache->num_regs - 1; i >= 0; i--) { struct reg *r = &cache->reg_list[i]; - if (r->exist && r->dirty) - armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value); + if (r->exist && r->dirty) { + int retval = armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value); + if (retval != ERROR_OK) + return retval; + } } return ERROR_OK; @@ -245,7 +273,7 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id) switch (arm_reg_id) { case ARMV7M_R0 ... ARMV7M_R14: case ARMV7M_PC: - case ARMV7M_xPSR: + case ARMV7M_XPSR: case ARMV7M_MSP: case ARMV7M_PSP: /* NOTE: we "know" here that the register identifiers @@ -269,6 +297,9 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id) case ARMV7M_FPSCR: return ARMV7M_REGSEL_FPSCR; + case ARMV8M_VPR: + return ARMV8M_REGSEL_VPR; + case ARMV7M_D0 ... ARMV7M_D15: return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0); @@ -363,9 +394,9 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r, buf_set_u32(r->value + 4, 0, 32, reg_value); uint64_t q = buf_get_u64(r->value, 0, 64); - LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q); + LOG_TARGET_DEBUG(target, "read %s value 0x%016" PRIx64, r->name, q); } else { - LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value); + LOG_TARGET_DEBUG(target, "read %s value 0x%08" PRIx32, r->name, reg_value); } } @@ -433,9 +464,9 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r, goto out_error; uint64_t q = buf_get_u64(value, 0, 64); - LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q); + LOG_TARGET_DEBUG(target, "write %s value 0x%016" PRIx64, r->name, q); } else { - LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t); + LOG_TARGET_DEBUG(target, "write %s value 0x%08" PRIx32, r->name, t); } } @@ -446,7 +477,7 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r, out_error: r->dirty = true; - LOG_ERROR("Error setting register %s", r->name); + LOG_TARGET_ERROR(target, "Error setting register %s", r->name); return retval; } @@ -481,7 +512,7 @@ int armv7m_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info) + unsigned int timeout_ms, void *arch_info) { int retval; @@ -517,22 +548,28 @@ int armv7m_start_algorithm(struct target *target, * at the exit point */ if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { - LOG_ERROR("current target isn't an ARMV7M target"); + LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target"); return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (start target algo)"); return ERROR_TARGET_NOT_HALTED; } /* Store all non-debug execution registers to armv7m_algorithm_info context */ - for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) { + for (unsigned int i = 0; i < armv7m->arm.core_cache->num_regs; i++) { + struct reg *reg = &armv7m->arm.core_cache->reg_list[i]; + if (!reg->exist) + continue; + + if (!reg->valid) + armv7m_get_core_reg(reg); + + if (!reg->valid) + LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name); - armv7m_algorithm_info->context[i] = buf_get_u32( - armv7m->arm.core_cache->reg_list[i].value, - 0, - 32); + armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32); } for (int i = 0; i < num_mem_params; i++) { @@ -554,12 +591,12 @@ int armv7m_start_algorithm(struct target *target, /* uint32_t regvalue; */ if (!reg) { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } if (reg->size != reg_params[i].size) { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -579,7 +616,7 @@ int armv7m_start_algorithm(struct target *target, * Because xPSR.T is populated on reset from the vector table, * it might be 0 if the vector table has "bad" data in it. */ - struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR]; + struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR]; buf_set_u32(reg->value, 0, 32, 0x01000000); reg->valid = true; reg->dirty = true; @@ -591,10 +628,11 @@ int armv7m_start_algorithm(struct target *target, /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */ if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) { armv7m_algorithm_info->core_mode = ARM_MODE_THREAD; - LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead"); + LOG_TARGET_INFO(target, "ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead"); } - LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); + LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x", + armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; @@ -604,7 +642,7 @@ int armv7m_start_algorithm(struct target *target, /* save previous core mode */ armv7m_algorithm_info->core_mode = core_mode; - retval = target_resume(target, 0, entry_point, 1, 1); + retval = target_resume(target, false, entry_point, true, true); return retval; } @@ -613,7 +651,7 @@ int armv7m_start_algorithm(struct target *target, int armv7m_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - target_addr_t exit_point, int timeout_ms, + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { struct armv7m_common *armv7m = target_to_armv7m(target); @@ -624,7 +662,7 @@ int armv7m_wait_algorithm(struct target *target, * at the exit point */ if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { - LOG_ERROR("current target isn't an ARMV7M target"); + LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target"); return ERROR_TARGET_INVALID; } @@ -644,7 +682,7 @@ int armv7m_wait_algorithm(struct target *target, /* PC value has been cached in cortex_m_debug_entry() */ uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32); if (pc != exit_point) { - LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR, + LOG_TARGET_DEBUG(target, "failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR, pc, exit_point); return ERROR_TARGET_ALGO_EXIT; } @@ -669,12 +707,13 @@ int armv7m_wait_algorithm(struct target *target, false); if (!reg) { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_TARGET_ERROR(target, "BUG: register '%s' not found", + reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } if (reg->size != reg_params[i].size) { - LOG_ERROR( + LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; @@ -685,22 +724,25 @@ int armv7m_wait_algorithm(struct target *target, } for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) { + struct reg *reg = &armv7m->arm.core_cache->reg_list[i]; + if (!reg->exist) + continue; + uint32_t regvalue; - regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32); + regvalue = buf_get_u32(reg->value, 0, 32); if (regvalue != armv7m_algorithm_info->context[i]) { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, - armv7m->arm.core_cache->reg_list[i].name, - armv7m_algorithm_info->context[i]); - buf_set_u32(armv7m->arm.core_cache->reg_list[i].value, + LOG_TARGET_DEBUG(target, "restoring register %s with value 0x%8.8" PRIx32, + reg->name, armv7m_algorithm_info->context[i]); + buf_set_u32(reg->value, 0, 32, armv7m_algorithm_info->context[i]); - armv7m->arm.core_cache->reg_list[i].valid = true; - armv7m->arm.core_cache->reg_list[i].dirty = true; + reg->valid = true; + reg->dirty = true; } } /* restore previous core mode */ if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) { - LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); + LOG_TARGET_DEBUG(target, "restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; @@ -726,7 +768,7 @@ int armv7m_arch_state(struct target *target) ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32); - LOG_USER("target halted due to %s, current mode: %s %s\n" + LOG_TARGET_USER(target, "halted due to %s, current mode: %s %s\n" "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s", debug_reason_name(target), arm_mode_name(arm->core_mode), @@ -794,16 +836,20 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) feature->name = armv7m_regs[i].feature; reg_list[i].feature = feature; } else - LOG_ERROR("unable to allocate feature list"); + LOG_TARGET_ERROR(target, "unable to allocate feature list"); reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type)); - if (reg_list[i].reg_data_type) - reg_list[i].reg_data_type->type = armv7m_regs[i].type; - else - LOG_ERROR("unable to allocate reg type list"); + if (reg_list[i].reg_data_type) { + if (armv7m_regs[i].data_type) + *reg_list[i].reg_data_type = *armv7m_regs[i].data_type; + else + reg_list[i].reg_data_type->type = armv7m_regs[i].type; + } else { + LOG_TARGET_ERROR(target, "unable to allocate reg type list"); + } } - arm->cpsr = reg_list + ARMV7M_xPSR; + arm->cpsr = reg_list + ARMV7M_XPSR; arm->pc = reg_list + ARMV7M_PC; arm->core_cache = cache; @@ -854,6 +900,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) /* Enable stimulus port #0 by default */ armv7m->trace_config.itm_ter[0] = 1; + arm->core_state = ARM_STATE_THUMB; arm->core_type = ARM_CORE_TYPE_M_PROFILE; arm->arch_info = armv7m; arm->setup_semihosting = armv7m_setup_semihosting; @@ -895,7 +942,7 @@ int armv7m_checksum_memory(struct target *target, buf_set_u32(reg_params[0].value, 0, 32, address); buf_set_u32(reg_params[1].value, 0, 32, count); - int timeout = 20000 * (1 + (count / (1024 * 1024))); + unsigned int timeout = 20000 * (1 + (count / (1024 * 1024))); retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6), @@ -904,7 +951,7 @@ int armv7m_checksum_memory(struct target *target, if (retval == ERROR_OK) *checksum = buf_get_u32(reg_params[0].value, 0, 32); else - LOG_ERROR("error executing cortex_m crc algorithm"); + LOG_TARGET_ERROR(target, "error executing cortex_m crc algorithm"); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -989,7 +1036,7 @@ int armv7m_blank_check_memory(struct target *target, uint32_t erased_word = erased_value | (erased_value << 8) | (erased_value << 16) | (erased_value << 24); - LOG_DEBUG("Starting erase check of %d blocks, parameters@" + LOG_TARGET_DEBUG(target, "Starting erase check of %d blocks, parameters@" TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address); armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; @@ -1002,7 +1049,7 @@ int armv7m_blank_check_memory(struct target *target, buf_set_u32(reg_params[1].value, 0, 32, erased_word); /* assume CPU clk at least 1 MHz */ - int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000; + unsigned int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000; retval = target_run_algorithm(target, 0, NULL, @@ -1030,7 +1077,8 @@ int armv7m_blank_check_memory(struct target *target, blocks[i].result = result; } if (i && timed_out) - LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i); + LOG_TARGET_INFO(target, "Slow CPU clock: %d blocks checked, %d remain. Continuing...", + i, num_blocks - i); retval = i; /* return number of blocks really checked */ @@ -1071,7 +1119,7 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) r->dirty = true; r->valid = true; result = true; - LOG_DEBUG("Skipping over BKPT instruction"); + LOG_TARGET_DEBUG(target, "Skipping over BKPT instruction"); } } } @@ -1084,7 +1132,11 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) const struct command_registration armv7m_command_handlers[] = { { - .chain = arm_command_handlers, + .name = "arm", + .mode = COMMAND_ANY, + .help = "ARM command group", + .usage = "", + .chain = arm_all_profiles_command_handlers, }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 6d97e4ac51..86c45f7f26 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -46,7 +46,7 @@ enum { ARMV7M_REGSEL_R14, ARMV7M_REGSEL_PC = 15, - ARMV7M_REGSEL_xPSR = 16, + ARMV7M_REGSEL_XPSR = 16, ARMV7M_REGSEL_MSP, ARMV7M_REGSEL_PSP, @@ -62,6 +62,7 @@ enum { ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14, ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22, ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23, + ARMV8M_REGSEL_VPR = 0x24, ARMV7M_REGSEL_FPSCR = 0x21, /* 32bit Floating-point registers */ @@ -124,7 +125,7 @@ enum { ARMV7M_R14 = ARMV7M_REGSEL_R14, ARMV7M_PC = ARMV7M_REGSEL_PC, - ARMV7M_xPSR = ARMV7M_REGSEL_xPSR, + ARMV7M_XPSR = ARMV7M_REGSEL_XPSR, ARMV7M_MSP = ARMV7M_REGSEL_MSP, ARMV7M_PSP = ARMV7M_REGSEL_PSP, @@ -196,12 +197,15 @@ enum { /* Floating-point status register */ ARMV7M_FPSCR, + /* Vector Predication Status and Control Register */ + ARMV8M_VPR, + /* for convenience add registers' block delimiters */ ARMV7M_LAST_REG, ARMV7M_CORE_FIRST_REG = ARMV7M_R0, - ARMV7M_CORE_LAST_REG = ARMV7M_xPSR, + ARMV7M_CORE_LAST_REG = ARMV7M_XPSR, ARMV7M_FPU_FIRST_REG = ARMV7M_D0, - ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR, + ARMV7M_FPU_LAST_REG = ARMV8M_VPR, ARMV8M_FIRST_REG = ARMV8M_MSP_NS, ARMV8M_LAST_REG = ARMV8M_CONTROL_NS, }; @@ -211,16 +215,19 @@ enum { FPV4_SP, FPV5_SP, FPV5_DP, + FPV5_MVE_I, + FPV5_MVE_F, }; #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1) -#define ARMV7M_COMMON_MAGIC 0x2A452A45 +#define ARMV7M_COMMON_MAGIC 0x2A452A45U struct armv7m_common { + unsigned int common_magic; + struct arm arm; - int common_magic; int exception_number; /* AP this processor is connected to in the DAP */ @@ -289,7 +296,7 @@ target_to_armv7m_safe(struct target *target) } struct armv7m_algorithm { - int common_magic; + unsigned int common_magic; enum arm_mode core_mode; @@ -313,7 +320,7 @@ int armv7m_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); int armv7m_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, @@ -324,7 +331,7 @@ int armv7m_start_algorithm(struct target *target, int armv7m_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - target_addr_t exit_point, int timeout_ms, + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info); int armv7m_invalidate_core_regs(struct target *target); diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c index b4fd6fd3a2..556568d71a 100644 --- a/src/target/armv7m_trace.c +++ b/src/target/armv7m_trace.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 Paul Fertser <fercerpav@gmail.com> * @@ -92,11 +92,14 @@ COMMAND_HANDLER(handle_itm_port_command) else armv7m->trace_config.itm_ter[reg_idx] &= ~(1 << port); - if (CMD_CTX->mode == COMMAND_EXEC) - return armv7m_trace_itm_config(target); + /* + * In config mode ITM is not accessible yet. + * Keep the value and it will be programmed at target init. + */ + if (CMD_CTX->mode == COMMAND_CONFIG) + return ERROR_OK; - armv7m->trace_config.itm_deferred_config = true; - return ERROR_OK; + return armv7m_trace_itm_config(target); } COMMAND_HANDLER(handle_itm_ports_command) @@ -112,11 +115,14 @@ COMMAND_HANDLER(handle_itm_ports_command) memset(armv7m->trace_config.itm_ter, enable ? 0xff : 0, sizeof(armv7m->trace_config.itm_ter)); - if (CMD_CTX->mode == COMMAND_EXEC) - return armv7m_trace_itm_config(target); + /* + * In config mode ITM is not accessible yet. + * Keep the value and it will be programmed at target init. + */ + if (CMD_CTX->mode == COMMAND_CONFIG) + return ERROR_OK; - armv7m->trace_config.itm_deferred_config = true; - return ERROR_OK; + return armv7m_trace_itm_config(target); } static const struct command_registration itm_command_handlers[] = { diff --git a/src/target/armv7m_trace.h b/src/target/armv7m_trace.h index 5abb0b9406..02eca932df 100644 --- a/src/target/armv7m_trace.h +++ b/src/target/armv7m_trace.h @@ -35,8 +35,6 @@ struct armv7m_trace_config { bool itm_async_timestamps; /** Enable synchronisation packet transmission (for sync port only) */ bool itm_synchro_packets; - /** Config ITM after target examine */ - bool itm_deferred_config; }; extern const struct command_registration armv7m_trace_command_handlers[]; diff --git a/src/target/armv8.c b/src/target/armv8.c index f4ae1f55cf..ece49c2a26 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2015 by David Ung * @@ -19,6 +19,7 @@ #include "register.h" #include <helper/binarybuffer.h> #include <helper/command.h> +#include <helper/nvp.h> #include <stdlib.h> #include <string.h> @@ -35,7 +36,7 @@ static const char * const armv8_state_strings[] = { static const struct { const char *name; - unsigned psr; + unsigned int psr; } armv8_mode_data[] = { { .name = "USR", @@ -104,9 +105,9 @@ static const struct { }; /** Map PSR mode bits to the name of an ARM processor operating mode. */ -const char *armv8_mode_name(unsigned psr_mode) +const char *armv8_mode_name(unsigned int psr_mode) { - for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) { if (armv8_mode_data[i].psr == psr_mode) return armv8_mode_data[i].name; } @@ -114,13 +115,177 @@ const char *armv8_mode_name(unsigned psr_mode) return "UNRECOGNIZED"; } +static uint8_t armv8_pa_size(uint32_t ps) +{ + uint8_t ret = 0; + switch (ps) { + case 0: + ret = 32; + break; + case 1: + ret = 36; + break; + case 2: + ret = 40; + break; + case 3: + ret = 42; + break; + case 4: + ret = 44; + break; + case 5: + ret = 48; + break; + default: + LOG_INFO("Unknown physical address size"); + break; + } + return ret; +} + +static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target) +{ + struct armv8_common *armv8 = target_to_armv8(target); + struct arm_dpm *dpm = armv8->arm.dpm; + uint32_t ttbcr, ttbcr_n; + int retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 2, 0, 2), + &ttbcr); + if (retval != ERROR_OK) + goto done; + + LOG_DEBUG("ttbcr %" PRIx32, ttbcr); + + ttbcr_n = ttbcr & 0x7; + armv8->armv8_mmu.ttbcr = ttbcr; + + /* + * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition), + * document # ARM DDI 0406C + */ + armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n; + armv8->armv8_mmu.ttbr_range[1] = 0xffffffff; + armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n); + armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14; + + LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32, + (ttbcr_n != 0) ? "used" : "not used", + armv8->armv8_mmu.ttbr_mask[0], + armv8->armv8_mmu.ttbr_mask[1]); + +done: + dpm->finish(dpm); + return retval; +} + +static int armv8_read_ttbcr(struct target *target) +{ + struct armv8_common *armv8 = target_to_armv8(target); + struct arm_dpm *dpm = armv8->arm.dpm; + struct arm *arm = &armv8->arm; + uint32_t ttbcr; + uint64_t ttbcr_64; + + int retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + + /* clear ttrr1_used and ttbr0_mask */ + memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used)); + memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask)); + + switch (armv8_curel_from_core_mode(arm->core_mode)) { + case SYSTEM_CUREL_EL3: + retval = dpm->instr_read_data_r0(dpm, + ARMV8_MRS(SYSTEM_TCR_EL3, 0), + &ttbcr); + retval += dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_TTBR0_EL3, 0), + &armv8->ttbr_base); + if (retval != ERROR_OK) + goto done; + armv8->va_size = 64 - (ttbcr & 0x3F); + armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7); + armv8->page_size = (ttbcr >> 14) & 3; + break; + case SYSTEM_CUREL_EL2: + retval = dpm->instr_read_data_r0(dpm, + ARMV8_MRS(SYSTEM_TCR_EL2, 0), + &ttbcr); + retval += dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_TTBR0_EL2, 0), + &armv8->ttbr_base); + if (retval != ERROR_OK) + goto done; + armv8->va_size = 64 - (ttbcr & 0x3F); + armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7); + armv8->page_size = (ttbcr >> 14) & 3; + break; + case SYSTEM_CUREL_EL0: + armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H); + /* fall through */ + case SYSTEM_CUREL_EL1: + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_TCR_EL1, 0), + &ttbcr_64); + armv8->va_size = 64 - (ttbcr_64 & 0x3F); + armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7); + armv8->page_size = (ttbcr_64 >> 14) & 3; + armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0; + armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFFULL; + retval += dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0), + &armv8->ttbr_base); + if (retval != ERROR_OK) + goto done; + break; + default: + LOG_ERROR("unknown core state"); + retval = ERROR_FAIL; + break; + } + if (retval != ERROR_OK) + goto done; + + if (armv8->armv8_mmu.ttbr1_used == 1) + LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask)); + +done: + armv8_dpm_modeswitch(dpm, ARM_MODE_ANY); + dpm->finish(dpm); + return retval; +} + +static int armv8_get_pauth_mask(struct armv8_common *armv8, uint64_t *mask) +{ + struct arm *arm = &armv8->arm; + int retval = ERROR_OK; + if (armv8->va_size == 0) + retval = armv8_read_ttbcr(arm->target); + if (retval != ERROR_OK) + return retval; + + *mask = ~(((uint64_t)1 << armv8->va_size) - 1); + + return retval; +} + static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval) { struct arm_dpm *dpm = &armv8->dpm; + unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode); int retval; uint32_t value; uint64_t value_64; + if (!regval) + return ERROR_FAIL; + switch (regnum) { case 0 ... 30: retval = dpm->instr_read_data_dcc_64(dpm, @@ -134,7 +299,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS_DLR(0), &value_64); break; - case ARMV8_xPSR: + case ARMV8_XPSR: retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS_DSPSR(0), &value); value_64 = value; @@ -150,56 +315,97 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv value_64 = value; break; case ARMV8_ELR_EL1: + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64); break; case ARMV8_ELR_EL2: + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64); break; case ARMV8_ELR_EL3: + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64); break; case ARMV8_ESR_EL1: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value_64); break; case ARMV8_ESR_EL2: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value_64); break; case ARMV8_ESR_EL3: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64); break; case ARMV8_SPSR_EL1: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value_64); break; case ARMV8_SPSR_EL2: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value_64); break; case ARMV8_SPSR_EL3: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value); - value_64 = value; + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_read_data_r0_64(dpm, + ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value_64); + break; + case ARMV8_PAUTH_CMASK: + case ARMV8_PAUTH_DMASK: + retval = armv8_get_pauth_mask(armv8, &value_64); break; default: retval = ERROR_FAIL; break; } - if (retval == ERROR_OK && regval) + if (retval == ERROR_OK) *regval = value_64; - else - retval = ERROR_FAIL; return retval; } @@ -230,6 +436,7 @@ static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64) { struct arm_dpm *dpm = &armv8->dpm; + unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode); int retval; uint32_t value; @@ -249,7 +456,7 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu ARMV8_MSR_DLR(0), value_64); break; - case ARMV8_xPSR: + case ARMV8_XPSR: value = value_64; retval = dpm->instr_write_data_r0(dpm, ARMV8_MSR_DSPSR(0), @@ -269,46 +476,85 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu break; /* registers clobbered by taking exception in debug state */ case ARMV8_ELR_EL1: + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_write_data_r0_64(dpm, ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64); break; case ARMV8_ELR_EL2: + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_write_data_r0_64(dpm, ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64); break; case ARMV8_ELR_EL3: + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_write_data_r0_64(dpm, ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64); break; case ARMV8_ESR_EL1: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value); + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value_64); break; case ARMV8_ESR_EL2: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value); + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value_64); break; case ARMV8_ESR_EL3: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value); + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64); break; case ARMV8_SPSR_EL1: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value); + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value_64); break; case ARMV8_SPSR_EL2: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value); + if (curel < SYSTEM_CUREL_EL2) { + LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value_64); break; case ARMV8_SPSR_EL3: - value = value_64; - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value); + if (curel < SYSTEM_CUREL_EL3) { + LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } + retval = dpm->instr_write_data_r0_64(dpm, + ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value_64); break; default: retval = ERROR_FAIL; @@ -347,6 +593,9 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re uint32_t value = 0; int retval; + if (!regval) + return ERROR_FAIL; + switch (regnum) { case ARMV8_R0 ... ARMV8_R14: /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ @@ -364,7 +613,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re ARMV8_MRC_DLR(0), &value); break; - case ARMV8_xPSR: + case ARMV8_XPSR: retval = dpm->instr_read_data_r0(dpm, ARMV8_MRC_DSPSR(0), &value); @@ -394,22 +643,22 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re ARMV4_5_MRC(15, 4, 0, 5, 2, 0), &value); break; - case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */ + case ARMV8_ESR_EL3: /* no equivalent in aarch32 */ retval = ERROR_FAIL; break; case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */ retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS_xPSR_T1(1, 0), + ARMV8_MRS_XPSR_T1(1, 0), &value); break; case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */ retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS_xPSR_T1(1, 0), + ARMV8_MRS_XPSR_T1(1, 0), &value); break; case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */ retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS_xPSR_T1(1, 0), + ARMV8_MRS_XPSR_T1(1, 0), &value); break; case ARMV8_FPSR: @@ -422,7 +671,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re break; } - if (retval == ERROR_OK && regval) + if (retval == ERROR_OK) *regval = value; return retval; @@ -434,7 +683,7 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, struct arm_dpm *dpm = &armv8->dpm; struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1; uint32_t value_r0 = 0, value_r1 = 0; - unsigned num = (regnum - ARMV8_V0) << 1; + unsigned int num = (regnum - ARMV8_V0) << 1; switch (regnum) { case ARMV8_V0 ... ARMV8_V15: @@ -500,7 +749,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va retval = dpm->instr_write_data_r0(dpm, ARMV8_MCR_DLR(0), value); break; - case ARMV8_xPSR: /* CPSR */ + case ARMV8_XPSR: /* CPSR */ /* read r0 from DCC, then "MCR r0, DSPSR" */ retval = dpm->instr_write_data_r0(dpm, ARMV8_MCR_DSPSR(0), value); @@ -530,22 +779,22 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va ARMV4_5_MCR(15, 4, 0, 5, 2, 0), value); break; - case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */ + case ARMV8_ESR_EL3: /* no equivalent in aarch32 */ retval = ERROR_FAIL; break; case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */ retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP_xPSR_T1(1, 0, 15), + ARMV8_MSR_GP_XPSR_T1(1, 0, 15), value); break; case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */ retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP_xPSR_T1(1, 0, 15), + ARMV8_MSR_GP_XPSR_T1(1, 0, 15), value); break; case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */ retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP_xPSR_T1(1, 0, 15), + ARMV8_MSR_GP_XPSR_T1(1, 0, 15), value); break; case ARMV8_FPSR: @@ -568,7 +817,7 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum struct arm_dpm *dpm = &armv8->dpm; struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1; uint32_t value_r0 = 0, value_r1 = 0; - unsigned num = (regnum - ARMV8_V0) << 1; + unsigned int num = (regnum - ARMV8_V0) << 1; switch (regnum) { case ARMV8_V0 ... ARMV8_V15: @@ -634,12 +883,27 @@ int armv8_read_mpidr(struct armv8_common *armv8) int retval = ERROR_FAIL; struct arm *arm = &armv8->arm; struct arm_dpm *dpm = armv8->arm.dpm; - uint32_t mpidr; + uint64_t mpidr; + uint8_t multi_processor_system; + uint8_t aff3; + uint8_t aff2; + uint8_t aff1; + uint8_t aff0; + uint8_t mt; retval = dpm->prepare(dpm); if (retval != ERROR_OK) goto done; + /* + * TODO: BUG - routine armv8_dpm_modeswitch() doesn't re-evaluate 'arm->dpm->core_state'. + * If the core is halted in EL0 AArch32 while EL1 is in AArch64, the modeswitch moves the core + * to EL1, but there is no re-evaluation of dpm->arm->core_state. As a result, while the core + * is in AArch64, the code considers the system still in AArch32. The read of MPIDR would + * select the instruction based on the old core_state. The call to 'armv8_dpm_get_core_state()' + * below could also potentially return the incorrect execution state for the current EL. + */ + /* check if we're in an unprivileged mode */ if (armv8_curel_from_core_mode(arm->core_mode) < SYSTEM_CUREL_EL1) { retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H); @@ -647,17 +911,39 @@ int armv8_read_mpidr(struct armv8_common *armv8) return retval; } - retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr); + retval = dpm->instr_read_data_r0_64(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr); if (retval != ERROR_OK) goto done; if (mpidr & 1U<<31) { - armv8->multi_processor_system = (mpidr >> 30) & 1; - armv8->cluster_id = (mpidr >> 8) & 0xf; - armv8->cpu_id = mpidr & 0x3; - LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target), - armv8->cluster_id, - armv8->cpu_id, - armv8->multi_processor_system == 0 ? "multi core" : "single core"); + multi_processor_system = (mpidr >> 30) & 1; + aff3 = (mpidr >> 32) & 0xff; + aff2 = (mpidr >> 16) & 0xff; + aff1 = (mpidr >> 8) & 0xff; + aff0 = mpidr & 0xff; + mt = (mpidr >> 24) & 0x1; + if (armv8_dpm_get_core_state(&armv8->dpm) == ARM_STATE_AARCH64) { + if (mt) + LOG_INFO("%s socket %" PRIu32 " cluster %" PRIu32 " core %" PRIu32 " thread %" PRIu32 " %s", + target_name(armv8->arm.target), + aff3, aff2, aff1, aff0, + multi_processor_system == 0 ? "multi core" : "single core"); + else + LOG_INFO("%s socket %" PRIu32 " cluster %" PRIu32 " core %" PRIu32 " %s", + target_name(armv8->arm.target), + aff3, aff1, aff0, + multi_processor_system == 0 ? "multi core" : "single core"); + } else { + if (mt) + LOG_INFO("%s cluster %" PRIu32 " core %" PRIu32 " thread %" PRIu32 " %s", + target_name(armv8->arm.target), + aff2, aff1, aff0, + multi_processor_system == 0 ? "multi core" : "single core"); + else + LOG_INFO("%s cluster %" PRIu32 " core %" PRIu32 " %s", + target_name(armv8->arm.target), + aff1, aff0, + multi_processor_system == 0 ? "multi core" : "single core"); + } } else LOG_ERROR("mpidr not in multiprocessor format"); @@ -712,7 +998,7 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr) arm->core_state = state; arm->core_mode = mode; - LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, + LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr, armv8_mode_name(arm->core_mode), armv8_state_strings[arm->core_state]); } @@ -761,7 +1047,7 @@ static void armv8_show_fault_registers32(struct armv8_common *armv8) ", IFAR: %8.8" PRIx32, ifsr, ifar); done: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); } static __attribute__((unused)) void armv8_show_fault_registers(struct target *target) @@ -772,156 +1058,79 @@ static __attribute__((unused)) void armv8_show_fault_registers(struct target *ta armv8_show_fault_registers32(armv8); } -static uint8_t armv8_pa_size(uint32_t ps) +static void armv8_decode_cacheability(int attr) { - uint8_t ret = 0; - switch (ps) { + if (attr == 0) { + LOG_USER_N("UNPREDICTABLE"); + return; + } + if (attr == 4) { + LOG_USER_N("Non-cacheable"); + return; + } + switch (attr & 0xC) { case 0: - ret = 32; + LOG_USER_N("Write-Through Transient"); break; - case 1: - ret = 36; + case 0x4: + LOG_USER_N("Write-Back Transient"); break; - case 2: - ret = 40; + case 0x8: + LOG_USER_N("Write-Through Non-transient"); break; - case 3: - ret = 42; - break; - case 4: - ret = 44; - break; - case 5: - ret = 48; - break; - default: - LOG_INFO("Unknown physical address size"); + case 0xC: + LOG_USER_N("Write-Back Non-transient"); break; } - return ret; -} - -static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target) -{ - struct armv8_common *armv8 = target_to_armv8(target); - struct arm_dpm *dpm = armv8->arm.dpm; - uint32_t ttbcr, ttbcr_n; - int retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - goto done; - /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/ - retval = dpm->instr_read_data_r0(dpm, - ARMV4_5_MRC(15, 0, 0, 2, 0, 2), - &ttbcr); - if (retval != ERROR_OK) - goto done; - - LOG_DEBUG("ttbcr %" PRIx32, ttbcr); - - ttbcr_n = ttbcr & 0x7; - armv8->armv8_mmu.ttbcr = ttbcr; - - /* - * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition), - * document # ARM DDI 0406C - */ - armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n; - armv8->armv8_mmu.ttbr_range[1] = 0xffffffff; - armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n); - armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14; - - LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32, - (ttbcr_n != 0) ? "used" : "not used", - armv8->armv8_mmu.ttbr_mask[0], - armv8->armv8_mmu.ttbr_mask[1]); - -done: - dpm->finish(dpm); - return retval; + if (attr & 2) + LOG_USER_N(" Read-Allocate"); + else + LOG_USER_N(" No-Read Allocate"); + if (attr & 1) + LOG_USER_N(" Write-Allocate"); + else + LOG_USER_N(" No-Write Allocate"); } -static __attribute__((unused)) int armv8_read_ttbcr(struct target *target) +static void armv8_decode_memory_attr(int attr) { - struct armv8_common *armv8 = target_to_armv8(target); - struct arm_dpm *dpm = armv8->arm.dpm; - struct arm *arm = &armv8->arm; - uint32_t ttbcr; - uint64_t ttbcr_64; - - int retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - goto done; - - /* clear ttrr1_used and ttbr0_mask */ - memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used)); - memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask)); - - switch (armv8_curel_from_core_mode(arm->core_mode)) { - case SYSTEM_CUREL_EL3: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_TCR_EL3, 0), - &ttbcr); - retval += dpm->instr_read_data_r0_64(dpm, - ARMV8_MRS(SYSTEM_TTBR0_EL3, 0), - &armv8->ttbr_base); - if (retval != ERROR_OK) - goto done; - armv8->va_size = 64 - (ttbcr & 0x3F); - armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7); - armv8->page_size = (ttbcr >> 14) & 3; - break; - case SYSTEM_CUREL_EL2: - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(SYSTEM_TCR_EL2, 0), - &ttbcr); - retval += dpm->instr_read_data_r0_64(dpm, - ARMV8_MRS(SYSTEM_TTBR0_EL2, 0), - &armv8->ttbr_base); - if (retval != ERROR_OK) - goto done; - armv8->va_size = 64 - (ttbcr & 0x3F); - armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7); - armv8->page_size = (ttbcr >> 14) & 3; - break; - case SYSTEM_CUREL_EL0: - armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H); - /* fall through */ - case SYSTEM_CUREL_EL1: - retval = dpm->instr_read_data_r0_64(dpm, - ARMV8_MRS(SYSTEM_TCR_EL1, 0), - &ttbcr_64); - armv8->va_size = 64 - (ttbcr_64 & 0x3F); - armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7); - armv8->page_size = (ttbcr_64 >> 14) & 3; - armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0; - armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF; - retval += dpm->instr_read_data_r0_64(dpm, - ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0), - &armv8->ttbr_base); - if (retval != ERROR_OK) - goto done; - break; - default: - LOG_ERROR("unknown core state"); - retval = ERROR_FAIL; - break; + if (attr == 0x40) { + LOG_USER("Normal Memory, Inner Non-cacheable, " + "Outer Non-cacheable, XS=0"); + } else if (attr == 0xA0) { + LOG_USER("Normal Memory, Inner Write-through Cacheable, " + "Outer Write-through Cacheable, Read-Allocate, " + "No-Write Allocate, Non-transient, XS=0"); + } else if (attr == 0xF0) { + LOG_USER("Tagged Normal Memory, Inner Write-Back, " + "Outer Write-Back, Read-Allocate, Write-Allocate, " + "Non-transient"); + } else if ((attr & 0xF0) == 0) { + switch (attr & 0xC) { + case 0: + LOG_USER_N("Device-nGnRnE Memory"); + break; + case 0x4: + LOG_USER_N("Device-nGnRE Memory"); + break; + case 0x8: + LOG_USER_N("Device-nGRE Memory"); + break; + case 0xC: + LOG_USER_N("Device-GRE Memory"); + break; + } + if (attr & 1) + LOG_USER(", XS=0"); + else + LOG_USER_N("\n"); + } else { + LOG_USER_N("Normal Memory, Inner "); + armv8_decode_cacheability(attr & 0xF); + LOG_USER_N(", Outer "); + armv8_decode_cacheability(attr >> 4); + LOG_USER_N("\n"); } - if (retval != ERROR_OK) - goto done; - - if (armv8->armv8_mmu.ttbr1_used == 1) - LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask)); - -done: - armv8_dpm_modeswitch(dpm, ARM_MODE_ANY); - dpm->finish(dpm); - return retval; -} - -/* method adapted to cortex A : reused arm v4 v5 method*/ -int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val) -{ - return ERROR_OK; } /* V8 method VA TO PA */ @@ -945,7 +1154,7 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, }; if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s not halted", target_name(target)); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1006,11 +1215,9 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, int NS = (par >> 9) & 1; int ATTR = (par >> 56) & 0xFF; - char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory"; - LOG_USER("%sshareable, %s", shared_name[SH], secure_name[NS]); - LOG_USER("%s", memtype); + armv8_decode_memory_attr(ATTR); } } @@ -1025,7 +1232,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) unsigned int argp = 0; int retval; - static const struct jim_nvp nvp_ecatch_modes[] = { + static const struct nvp nvp_ecatch_modes[] = { { .name = "off", .value = 0 }, { .name = "nsec_el1", .value = (1 << 5) }, { .name = "nsec_el2", .value = (2 << 5) }, @@ -1035,7 +1242,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) { .name = "sec_el13", .value = (5 << 1) }, { .name = NULL, .value = -1 }, }; - const struct jim_nvp *n; + const struct nvp *n; if (CMD_ARGC == 0) { const char *sec = NULL, *nsec = NULL; @@ -1045,11 +1252,11 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) if (retval != ERROR_OK) return retval; - n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f); + n = nvp_value2name(nvp_ecatch_modes, edeccr & 0x0f); if (n->name) sec = n->name; - n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0); + n = nvp_value2name(nvp_ecatch_modes, edeccr & 0xf0); if (n->name) nsec = n->name; @@ -1063,7 +1270,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) } while (argp < CMD_ARGC) { - n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); + n = nvp_name2value(nvp_ecatch_modes, CMD_ARGV[argp]); if (!n->name) { LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]); return ERROR_FAIL; @@ -1083,6 +1290,15 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) return ERROR_OK; } +COMMAND_HANDLER(armv8_pauth_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct armv8_common *armv8 = target_to_armv8(target); + return CALL_COMMAND_HANDLER(handle_command_parse_bool, + &armv8->enable_pauth, + "pauth feature"); +} + int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache) { @@ -1321,9 +1537,9 @@ static struct reg_data_type aarch64_flags_cpsr[] = { }; static const struct { - unsigned id; + unsigned int id; const char *name; - unsigned bits; + unsigned int bits; enum arm_mode mode; enum reg_type type; const char *group; @@ -1364,7 +1580,7 @@ static const struct { { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL}, { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL}, - { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, + { ARMV8_XPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr}, { ARMV8_V0, "v0", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v}, { ARMV8_V1, "v1", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v}, @@ -1403,31 +1619,33 @@ static const struct { { ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_ESR_EL1, "ESR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_SPSR_EL1, "SPSR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_ESR_EL2, "ESR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_ESR_EL2, "ESR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_SPSR_EL2, "SPSR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, { ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_ESR_EL3, "ESR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, - { ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", + { ARMV8_SPSR_EL3, "SPSR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", NULL}, + { ARMV8_PAUTH_DMASK, "pauth_dmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL}, + { ARMV8_PAUTH_CMASK, "pauth_cmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL}, }; static const struct { - unsigned id; - unsigned mapping; + unsigned int id; + unsigned int mapping; const char *name; - unsigned bits; + unsigned int bits; enum arm_mode mode; enum reg_type type; const char *group; @@ -1449,7 +1667,7 @@ static const struct { { ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" }, { ARMV8_R14, 0, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" }, { ARMV8_PC, 0, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" }, - { ARMV8_xPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" }, + { ARMV8_XPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" }, { ARMV8_V0, 0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"}, { ARMV8_V0, 8, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"}, { ARMV8_V1, 0, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"}, @@ -1505,12 +1723,12 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf) struct arm_reg *armv8_reg = reg->arch_info; struct target *target = armv8_reg->target; struct arm *arm = target_to_arm(target); - uint64_t value = buf_get_u64(buf, 0, reg->size); if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; if (reg->size <= 64) { + uint64_t value = buf_get_u64(buf, 0, reg->size); if (reg == arm->cpsr) armv8_set_cpsr(arm, (uint32_t)value); else { @@ -1518,6 +1736,7 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf) reg->valid = true; } } else if (reg->size <= 128) { + uint64_t value = buf_get_u64(buf, 0, 64); uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64); buf_set_u64(reg->value, 0, 64, value); @@ -1650,9 +1869,12 @@ struct reg_cache *armv8_build_reg_cache(struct target *target) *reg_list[i].reg_data_type = *armv8_regs[i].data_type; } else LOG_ERROR("unable to allocate reg type list"); + + if (i == ARMV8_PAUTH_CMASK || i == ARMV8_PAUTH_DMASK) + reg_list[i].exist = armv8->enable_pauth; } - arm->cpsr = reg_list + ARMV8_xPSR; + arm->cpsr = reg_list + ARMV8_XPSR; arm->pc = reg_list + ARMV8_PC; arm->core_cache = cache; @@ -1691,7 +1913,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target) return cache; } -struct reg *armv8_reg_current(struct arm *arm, unsigned regnum) +struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum) { struct reg *r; @@ -1745,10 +1967,21 @@ const struct command_registration armv8_command_handlers[] = { .help = "configure exception catch", .usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]", }, + { + .name = "pauth", + .handler = armv8_pauth_command, + .mode = COMMAND_CONFIG, + .help = "enable or disable providing GDB with an 8-bytes mask to " + "remove signature bits added by pointer authentication." + "Pointer authentication feature is broken until gdb 12.1, going to be fixed. " + "Consider using a newer version of gdb if you want enable " + "pauth feature.", + .usage = "[on|off]", + }, COMMAND_REGISTRATION_DONE }; -const char *armv8_get_gdb_arch(struct target *target) +const char *armv8_get_gdb_arch(const struct target *target) { struct arm *arm = target_to_arm(target); return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm"; @@ -1771,7 +2004,7 @@ int armv8_get_gdb_reg_list(struct target *target, *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < *reg_list_size; i++) - (*reg_list)[i] = armv8_reg_current(arm, i); + (*reg_list)[i] = armv8_reg_current(arm, i); return ERROR_OK; case REG_CLASS_ALL: @@ -1779,7 +2012,7 @@ int armv8_get_gdb_reg_list(struct target *target, *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < *reg_list_size; i++) - (*reg_list)[i] = armv8_reg_current(arm, i); + (*reg_list)[i] = armv8_reg_current(arm, i); return ERROR_OK; diff --git a/src/target/armv8.h b/src/target/armv8.h index 912da675cd..64ca5ec9d4 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -49,7 +49,7 @@ enum { ARMV8_SP = 31, ARMV8_PC = 32, - ARMV8_xPSR = 33, + ARMV8_XPSR = 33, ARMV8_V0 = 34, ARMV8_V1, @@ -98,6 +98,10 @@ enum { ARMV8_ESR_EL3 = 75, ARMV8_SPSR_EL3 = 76, + /* Pseudo registers defined by GDB to remove the pauth signature. */ + ARMV8_PAUTH_DMASK = 77, + ARMV8_PAUTH_CMASK = 78, + ARMV8_LAST_REG, }; @@ -108,7 +112,7 @@ enum run_control_op { ARMV8_RUNCONTROL_STEP = 3, }; -#define ARMV8_COMMON_MAGIC 0x0A450AAA +#define ARMV8_COMMON_MAGIC 0x0A450AAAU /* VA to PA translation operations opc2 values*/ #define V2PCWPR 0 @@ -158,6 +162,7 @@ struct armv8_cache_common { /* l2 external unified cache if some */ void *l2_cache; int (*flush_all_data_cache)(struct target *target); + int (*invalidate_all_instruction_cache)(struct target *target); int (*display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache); }; @@ -178,8 +183,9 @@ struct armv8_mmu_common { }; struct armv8_common { + unsigned int common_magic; + struct arm arm; - int common_magic; struct reg_cache *core_cache; /* Core Debug Unit */ @@ -189,21 +195,22 @@ struct armv8_common { const uint32_t *opcodes; - /* mdir */ - uint8_t multi_processor_system; - uint8_t cluster_id; - uint8_t cpu_id; - /* armv8 aarch64 need below information for page translation */ uint8_t va_size; uint8_t pa_size; uint32_t page_size; uint64_t ttbr_base; + bool is_armv8r; struct armv8_mmu_common armv8_mmu; struct arm_cti *cti; + /* True if OpenOCD provides pointer auth related info to GDB */ + bool enable_pauth; + + bool sticky_reset; + /* last run-control command issued to this target (resume, halt, step) */ enum run_control_op last_run_control_op; @@ -287,7 +294,6 @@ int armv8_identify_cache(struct armv8_common *armv8); int armv8_init_arch_info(struct target *target, struct armv8_common *armv8); int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo); -int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val); int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache); @@ -318,7 +324,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode) } } -const char *armv8_mode_name(unsigned psr_mode); +const char *armv8_mode_name(unsigned int psr_mode); void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64); int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value); diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c index b24ef62bdb..1c251beb99 100644 --- a/src/target/armv8_cache.c +++ b/src/target/armv8_cache.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2016 by Matthias Welwarsky * @@ -61,6 +61,7 @@ static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct ar goto done; c_way -= 1; } while (c_way >= 0); + keep_alive(); c_index -= 1; } while (c_index >= 0); @@ -140,6 +141,36 @@ int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, return retval; } +static int armv8_cache_i_inner_clean_inval_all(struct armv8_common *armv8) +{ + struct arm_dpm *dpm = armv8->arm.dpm; + int retval; + + retval = armv8_i_cache_sanity_check(armv8); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("flushing cache"); + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + + retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_ICIALLU)); + if (retval != ERROR_OK) + goto done; + + dpm->finish(dpm); + LOG_DEBUG("flushing cache done"); + return retval; + +done: + LOG_ERROR("i-cache invalidate failed"); + dpm->finish(dpm); + + return retval; +} + int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size) { struct arm_dpm *dpm = armv8->arm.dpm; @@ -243,7 +274,7 @@ static int armv8_flush_all_data(struct target *target) foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; if (curr->state == TARGET_HALTED) { - LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid); + LOG_TARGET_INFO(curr, "Wait flushing data l1."); retval = _armv8_flush_all_data(curr); } } @@ -252,6 +283,32 @@ static int armv8_flush_all_data(struct target *target) return retval; } +static int armv8_flush_all_instruction(struct target *target) +{ + int retval = ERROR_FAIL; + /* check that armv8_cache is correctly identify */ + struct armv8_common *armv8 = target_to_armv8(target); + if (armv8->armv8_mmu.armv8_cache.info == -1) { + LOG_ERROR("trying to flush un-identified cache"); + return retval; + } + + if (target->smp) { + /* look if all the other target have been flushed in order to flush icache */ + struct target_list *head; + foreach_smp_target(head, target->smp_targets) { + struct target *curr = head->target; + if (curr->state == TARGET_HALTED) { + LOG_TARGET_INFO(curr, "Wait flushing instruction l1."); + retval = armv8_cache_i_inner_clean_inval_all(target_to_armv8(curr)); + } + } + } else { + retval = armv8_cache_i_inner_clean_inval_all(armv8); + } + return retval; +} + static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg) { struct armv8_common *armv8 = dpm->arm->arch_info; @@ -286,8 +343,9 @@ static struct armv8_cachesize decode_cache_reg(uint32_t cache_reg) size.index = (cache_reg >> 13) & 0x7fff; size.way = ((cache_reg >> 3) & 0x3ff); - while (((size.way << i) & 0x80000000) == 0) - i++; + if (size.way != 0) + while (((size.way << i) & 0x80000000) == 0) + i++; size.way_shift = i; return size; @@ -410,6 +468,12 @@ int armv8_identify_cache(struct armv8_common *armv8) armv8->armv8_mmu.armv8_cache.flush_all_data_cache = armv8_flush_all_data; } + if (!armv8->armv8_mmu.armv8_cache.invalidate_all_instruction_cache) { + armv8->armv8_mmu.armv8_cache.display_cache_info = + armv8_handle_inner_cache_info_command; + armv8->armv8_mmu.armv8_cache.invalidate_all_instruction_cache = + armv8_flush_all_instruction; + } done: armv8_dpm_modeswitch(dpm, ARM_MODE_ANY); diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index 017c175fcd..3384e82ea5 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009 by David Brownell @@ -46,7 +46,7 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm) dpm->last_el = el; /* In Debug state, each bit gives the current Execution state of each EL */ - if ((rw >> el) & 0b1) + if ((rw >> el) & 1) return ARM_STATE_AARCH64; return ARM_STATE_ARM; @@ -274,7 +274,7 @@ static int dpmv8_instr_write_data_dcc(struct arm_dpm *dpm, if (retval != ERROR_OK) return retval; - return dpmv8_exec_opcode(dpm, opcode, 0); + return dpmv8_exec_opcode(dpm, opcode, NULL); } static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm, @@ -287,7 +287,7 @@ static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm, if (retval != ERROR_OK) return retval; - return dpmv8_exec_opcode(dpm, opcode, 0); + return dpmv8_exec_opcode(dpm, opcode, NULL); } static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm, @@ -417,7 +417,7 @@ static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm, } #if 0 -static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, +static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, target_addr_t addr, uint32_t control) { struct armv8_common *armv8 = dpm->arm->arch_info; @@ -441,8 +441,7 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, vr += 16 * index_t; cr += 16 * index_t; - LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", - (unsigned) vr, (unsigned) cr); + LOG_DEBUG("A8: bpwp enable, vr %08" PRIx32 " cr %08" PRIx32, vr, cr); retval = mem_ap_write_atomic_u32(armv8->debug_ap, vr, addr); if (retval != ERROR_OK) @@ -451,7 +450,7 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, } #endif -static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) +static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) { struct armv8_common *armv8 = dpm->arm->arch_info; uint32_t cr; @@ -469,7 +468,7 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) } cr += 16 * index_t; - LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr); + LOG_DEBUG("A: bpwp disable, cr %08" PRIx32, cr); /* clear control register */ return mem_ap_write_atomic_u32(armv8->debug_ap, cr, 0); @@ -501,7 +500,7 @@ static int dpmv8_mrc(struct target *target, int cpnum, ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2), value); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -526,7 +525,7 @@ static int dpmv8_mcr(struct target *target, int cpnum, ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2), value); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -543,6 +542,8 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) unsigned int target_el; enum arm_state core_state; uint32_t cpsr; + uint32_t rw = (dpm->dscr >> 10) & 0xF; + uint32_t ns = (dpm->dscr >> 18) & 0x1; /* restore previous mode */ if (mode == ARM_MODE_ANY) { @@ -565,7 +566,11 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) case ARM_MODE_IRQ: case ARM_MODE_FIQ: case ARM_MODE_SYS: - target_el = 1; + /* For Secure, EL1 if EL3 is aarch64, EL3 if EL3 is aarch32 */ + if (ns || (rw & (1 << 3))) + target_el = 1; + else + target_el = 3; break; /* * TODO: handle ARM_MODE_HYP @@ -587,6 +592,9 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) } LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el); + if (dpm->last_el == target_el) + return ERROR_OK; /* nothing to do */ + if (target_el > dpm->last_el) { retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el); @@ -596,12 +604,12 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) } else { core_state = armv8_dpm_get_core_state(dpm); if (core_state != ARM_STATE_AARCH64) { - /* cannot do DRPS/ERET when already in EL0 */ - if (dpm->last_el != 0) { + /* cannot do DRPS/ERET when in EL0 or in SYS mode */ + if (dpm->last_el != 0 && dpm->arm->core_mode != ARM_MODE_SYS) { /* load SPSR with the desired mode and execute DRPS */ LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr); retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr); + ARMV8_MSR_GP_XPSR_T1(1, 0, 15), cpsr); if (retval == ERROR_OK) retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS)); } @@ -639,7 +647,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) /* * Common register read, relies on armv8_select_reg_access() having been called. */ -static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { struct armv8_common *armv8 = dpm->arm->arch_info; int retval = ERROR_FAIL; @@ -674,7 +682,7 @@ static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) } if (retval != ERROR_OK) - LOG_ERROR("Failed to read %s register", r->name); + LOG_DEBUG("Failed to read %s register", r->name); return retval; } @@ -682,7 +690,7 @@ static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) /* * Common register write, relies on armv8_select_reg_access() having been called. */ -static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) +static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) { struct armv8_common *armv8 = dpm->arm->arch_info; int retval = ERROR_FAIL; @@ -716,13 +724,14 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) } if (retval != ERROR_OK) - LOG_ERROR("Failed to write %s register", r->name); + LOG_DEBUG("Failed to write %s register", r->name); return retval; } /** - * Read basic registers of the current context: R0 to R15, and CPSR; + * Read basic registers of the current context: R0 to R15, and CPSR in AArch32 + * state or R0 to R31, PC and CPSR in AArch64 state; * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). * In normal operation this is called on entry to halting debug state, * possibly after some other operations supporting restore of debug state @@ -769,9 +778,15 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm) /* update core mode and state */ armv8_set_cpsr(arm, cpsr); - for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) { + /* read the remaining registers that would be required by GDB 'g' packet */ + for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) { struct arm_reg *arm_reg; + /* in AArch32 skip AArch64 registers */ + /* TODO: this should be detected below through arm_reg->mode */ + if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC) + continue; + r = armv8_reg_current(arm, i); if (!r->exist || r->valid) continue; @@ -878,7 +893,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) * cope with the hand-crafted breakpoint code. */ if (arm->target->type->add_breakpoint == dpmv8_add_breakpoint) { - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { struct dpm_bp *dbp = dpm->dbp + i; struct breakpoint *bp = dbp->bp; @@ -890,7 +905,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) } /* enable/disable watchpoints */ - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { struct dpm_wp *dwp = dpm->dwp + i; struct watchpoint *wp = dwp->wp; @@ -910,14 +925,14 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) goto done; /* check everything except our scratch register R0 */ - for (unsigned i = 1; i < cache->num_regs; i++) { + for (unsigned int i = 1; i < cache->num_regs; i++) { struct arm_reg *r; /* skip non-existent */ if (!cache->reg_list[i].exist) continue; /* skip PC and CPSR */ - if (i == ARMV8_PC || i == ARMV8_xPSR) + if (i == ARMV8_PC || i == ARMV8_XPSR) continue; /* skip invalid */ if (!cache->reg_list[i].valid) @@ -939,7 +954,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) /* flush CPSR and PC */ if (retval == ERROR_OK) - retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR); + retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR); if (retval == ERROR_OK) retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC); /* flush R0 -- it's *very* dirty by now */ @@ -982,7 +997,7 @@ static int armv8_dpm_read_core_reg(struct target *target, struct reg *r, goto fail; fail: - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); return retval; } @@ -1038,7 +1053,7 @@ static int armv8_dpm_full_context(struct target *target) * Pick some mode with unread registers and read them all. * Repeat until done. */ - for (unsigned i = 0; i < cache->num_regs; i++) { + for (unsigned int i = 0; i < cache->num_regs; i++) { struct arm_reg *r; if (!cache->reg_list[i].exist || cache->reg_list[i].valid) @@ -1076,7 +1091,7 @@ static int armv8_dpm_full_context(struct target *target) } while (did_read); retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY); - /* (void) */ dpm->finish(dpm); + dpm->finish(dpm); done: return retval; } @@ -1166,7 +1181,7 @@ static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp) if (bp->type == BKPT_SOFT) LOG_DEBUG("using HW bkpt, not SW..."); - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { if (!dpm->dbp[i].bp) { retval = dpmv8_bpwp_setup(dpm, &dpm->dbp[i].bpwp, bp->address, bp->length); @@ -1185,7 +1200,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp) struct arm_dpm *dpm = arm->dpm; int retval = ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned i = 0; i < dpm->nbp; i++) { + for (unsigned int i = 0; i < dpm->nbp; i++) { if (dpm->dbp[i].bp == bp) { dpm->dbp[i].bp = NULL; dpm->dbp[i].bpwp.dirty = true; @@ -1199,7 +1214,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp) return retval; } -static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, +static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t, struct watchpoint *wp) { int retval; @@ -1207,7 +1222,7 @@ static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, uint32_t control; /* this hardware doesn't support data value matching or masking */ - if (wp->value || wp->mask != ~(uint32_t)0) { + if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) { LOG_DEBUG("watchpoint values and masking not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1242,7 +1257,7 @@ static int dpmv8_add_watchpoint(struct target *target, struct watchpoint *wp) int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; if (dpm->bpwp_enable) { - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { if (!dpm->dwp[i].wp) { retval = dpmv8_watchpoint_setup(dpm, i, wp); break; @@ -1259,7 +1274,7 @@ static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp) struct arm_dpm *dpm = arm->dpm; int retval = ERROR_COMMAND_SYNTAX_ERROR; - for (unsigned i = 0; i < dpm->nwp; i++) { + for (unsigned int i = 0; i < dpm->nwp; i++) { if (dpm->dwp[i].wp == wp) { dpm->dwp[i].wp = NULL; dpm->dwp[i].bpwp.dirty = true; @@ -1293,9 +1308,9 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore) unsigned int el; static const int clobbered_regs_by_el[3][5] = { - { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 }, - { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 }, - { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 }, + { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 }, + { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 }, + { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 }, }; el = (dpm->dscr >> 8) & 3; @@ -1310,7 +1325,7 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore) mem_ap_write_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); - armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr); + armv8->read_reg_u64(armv8, ARMV8_XPSR, &dlr); dspsr = dlr; armv8->read_reg_u64(armv8, ARMV8_PC, &dlr); @@ -1475,7 +1490,7 @@ int armv8_dpm_initialize(struct arm_dpm *dpm) { /* Disable all breakpoints and watchpoints at startup. */ if (dpm->bpwp_disable) { - unsigned i; + unsigned int i; for (i = 0; i < dpm->nbp; i++) { dpm->dbp[i].bpwp.number = i; diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c index b62b8a2027..0f6c8108e8 100644 --- a/src/target/armv8_opcodes.c +++ b/src/target/armv8_opcodes.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com> @@ -36,9 +36,12 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = { [ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0), [ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0), [ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP(1, 0), + [ARMV8_OPC_LDRD_IP] = ARMV8_LDRD_IP(1, 0), [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP(1, 0), [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0), [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0), + [ARMV8_OPC_STRD_IP] = ARMV8_STRD_IP(1, 0), + [ARMV8_OPC_ICIALLU] = ARMV8_SYS(SYSTEM_ICIALLU, 0x1F), }; static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = { @@ -66,6 +69,7 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = { [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP_T3(1, 0), [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP_T3(1, 0), [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP_T3(1, 0), + [ARMV8_OPC_ICIALLU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 0), }; void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64) diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h index c4ecd667c0..9f18e94d29 100644 --- a/src/target/armv8_opcodes.h +++ b/src/target/armv8_opcodes.h @@ -26,80 +26,82 @@ #define SYSTEM_AAR64_MODE_EL3T 0xC #define SYSTEM_AAR64_MODE_EL3H 0xd -#define SYSTEM_DAIF 0b1101101000010001 +#define SYSTEM_DAIF 0xDA11 #define SYSTEM_DAIF_MASK 0x3C0 #define SYSTEM_DAIF_SHIFT 6 -#define SYSTEM_ELR_EL1 0b1100001000000001 -#define SYSTEM_ELR_EL2 0b1110001000000001 -#define SYSTEM_ELR_EL3 0b1111001000000001 - -#define SYSTEM_SCTLR_EL1 0b1100000010000000 -#define SYSTEM_SCTLR_EL2 0b1110000010000000 -#define SYSTEM_SCTLR_EL3 0b1111000010000000 - -#define SYSTEM_FPCR 0b1101101000100000 -#define SYSTEM_FPSR 0b1101101000100001 -#define SYSTEM_DAIF 0b1101101000010001 -#define SYSTEM_NZCV 0b1101101000010000 -#define SYSTEM_SP_EL0 0b1100001000001000 -#define SYSTEM_SP_EL1 0b1110001000001000 -#define SYSTEM_SP_EL2 0b1111001000001000 -#define SYSTEM_SP_SEL 0b1100001000010000 -#define SYSTEM_SPSR_ABT 0b1110001000011001 -#define SYSTEM_SPSR_FIQ 0b1110001000011011 -#define SYSTEM_SPSR_IRQ 0b1110001000011000 -#define SYSTEM_SPSR_UND 0b1110001000011010 - -#define SYSTEM_SPSR_EL1 0b1100001000000000 -#define SYSTEM_SPSR_EL2 0b1110001000000000 -#define SYSTEM_SPSR_EL3 0b1111001000000000 - -#define SYSTEM_ISR_EL1 0b1100011000001000 - -#define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000 -#define SYSTEM_DBG_DLR_EL0 0b1101101000101001 -#define SYSTEM_DBG_DTRRX_EL0 0b1001100000101000 -#define SYSTEM_DBG_DTRTX_EL0 0b1001100000101000 -#define SYSTEM_DBG_DBGDTR_EL0 0b1001100000100000 - -#define SYSTEM_CCSIDR 0b1100100000000000 -#define SYSTEM_CLIDR 0b1100100000000001 -#define SYSTEM_CSSELR 0b1101000000000000 -#define SYSTEM_CTYPE 0b1101100000000001 -#define SYSTEM_CTR 0b1101100000000001 - -#define SYSTEM_DCCISW 0b0100001111110010 -#define SYSTEM_DCCSW 0b0100001111010010 -#define SYSTEM_ICIVAU 0b0101101110101001 -#define SYSTEM_DCCVAU 0b0101101111011001 -#define SYSTEM_DCCIVAC 0b0101101111110001 - -#define SYSTEM_MPIDR 0b1100000000000101 - -#define SYSTEM_TCR_EL1 0b1100000100000010 -#define SYSTEM_TCR_EL2 0b1110000100000010 -#define SYSTEM_TCR_EL3 0b1111000100000010 - -#define SYSTEM_TTBR0_EL1 0b1100000100000000 -#define SYSTEM_TTBR0_EL2 0b1110000100000000 -#define SYSTEM_TTBR0_EL3 0b1111000100000000 -#define SYSTEM_TTBR1_EL1 0b1100000100000001 +#define SYSTEM_ELR_EL1 0xC201 +#define SYSTEM_ELR_EL2 0xE201 +#define SYSTEM_ELR_EL3 0xF201 + +#define SYSTEM_SCTLR_EL1 0xC080 +#define SYSTEM_SCTLR_EL2 0xE080 +#define SYSTEM_SCTLR_EL3 0xF080 + +#define SYSTEM_FPCR 0xDA20 +#define SYSTEM_FPSR 0xDA21 +#define SYSTEM_DAIF 0xDA11 +#define SYSTEM_NZCV 0xDA10 +#define SYSTEM_SP_EL0 0xC208 +#define SYSTEM_SP_EL1 0xE208 +#define SYSTEM_SP_EL2 0xF208 +#define SYSTEM_SP_SEL 0xC210 +#define SYSTEM_SPSR_ABT 0xE219 +#define SYSTEM_SPSR_FIQ 0xE21B +#define SYSTEM_SPSR_IRQ 0xE218 +#define SYSTEM_SPSR_UND 0xE21A + +#define SYSTEM_SPSR_EL1 0xC200 +#define SYSTEM_SPSR_EL2 0xE200 +#define SYSTEM_SPSR_EL3 0xF200 + +#define SYSTEM_ISR_EL1 0xC608 + +#define SYSTEM_DBG_DSPSR_EL0 0xDA28 +#define SYSTEM_DBG_DLR_EL0 0xDA29 +#define SYSTEM_DBG_DTRRX_EL0 0x9828 +#define SYSTEM_DBG_DTRTX_EL0 0x9828 +#define SYSTEM_DBG_DBGDTR_EL0 0x9820 + +#define SYSTEM_CCSIDR 0xC800 +#define SYSTEM_CLIDR 0xC801 +#define SYSTEM_CSSELR 0xD000 +#define SYSTEM_CTYPE 0xD801 +#define SYSTEM_CTR 0xD801 + +#define SYSTEM_DCCISW 0x43F2 +#define SYSTEM_DCCSW 0x43D2 +#define SYSTEM_ICIVAU 0x5BA9 +/* Attention, SYSTEM_ICIALLU requires rt=0x1f */ +#define SYSTEM_ICIALLU 0x03A8 +#define SYSTEM_DCCVAU 0x5BD9 +#define SYSTEM_DCCIVAC 0x5BF1 + +#define SYSTEM_MPIDR 0xC005 + +#define SYSTEM_TCR_EL1 0xC102 +#define SYSTEM_TCR_EL2 0xE102 +#define SYSTEM_TCR_EL3 0xF102 + +#define SYSTEM_TTBR0_EL1 0xC100 +#define SYSTEM_TTBR0_EL2 0xE100 +#define SYSTEM_TTBR0_EL3 0xF100 +#define SYSTEM_TTBR1_EL1 0xC101 /* ARMv8 address translation */ -#define SYSTEM_PAR_EL1 0b1100001110100000 -#define SYSTEM_ATS12E0R 0b0110001111000110 -#define SYSTEM_ATS12E1R 0b0110001111000100 -#define SYSTEM_ATS1E2R 0b0110001111000000 -#define SYSTEM_ATS1E3R 0b0111001111000000 +#define SYSTEM_PAR_EL1 0xC3A0 +#define SYSTEM_ATS12E0R 0x63C6 +#define SYSTEM_ATS12E1R 0x63C4 +#define SYSTEM_ATS1E2R 0x63C0 +#define SYSTEM_ATS1E3R 0x73C0 /* fault status and fault address */ -#define SYSTEM_FAR_EL1 0b1100001100000000 -#define SYSTEM_FAR_EL2 0b1110001100000000 -#define SYSTEM_FAR_EL3 0b1111001100000000 -#define SYSTEM_ESR_EL1 0b1100001010010000 -#define SYSTEM_ESR_EL2 0b1110001010010000 -#define SYSTEM_ESR_EL3 0b1111001010010000 +#define SYSTEM_FAR_EL1 0xC300 +#define SYSTEM_FAR_EL2 0xE300 +#define SYSTEM_FAR_EL3 0xF300 +#define SYSTEM_ESR_EL1 0xC290 +#define SYSTEM_ESR_EL2 0xE290 +#define SYSTEM_ESR_EL3 0xF290 #define ARMV8_MRS_DSPSR(rt) (0xd53b4500 | (rt)) #define ARMV8_MSR_DSPSR(rt) (0xd51b4500 | (rt)) @@ -138,9 +140,9 @@ (0xd500401f | ((op1) << 16) | ((crm) << 8) | ((op2) << 5)) #define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4)) -#define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8)) +#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8)) #define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4)) -#define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8)) +#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8)) #define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5)) #define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5)) @@ -155,6 +157,7 @@ #define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd) #define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd) #define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd) +#define ARMV8_LDRD_IP(rd, rn) (0xf8408400 | (rn << 5) | rd) #define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12)) #define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12)) @@ -163,6 +166,7 @@ #define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd) #define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd) #define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd) +#define ARMV8_STRD_IP(rd, rn) (0xf8008400 | (rn << 5) | rd) #define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12)) #define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12)) @@ -200,9 +204,12 @@ enum armv8_opcode { ARMV8_OPC_STRB_IP, ARMV8_OPC_STRH_IP, ARMV8_OPC_STRW_IP, + ARMV8_OPC_STRD_IP, ARMV8_OPC_LDRB_IP, ARMV8_OPC_LDRH_IP, ARMV8_OPC_LDRW_IP, + ARMV8_OPC_LDRD_IP, + ARMV8_OPC_ICIALLU, ARMV8_OPC_NUM, }; diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index 14c4d08151..94962c2055 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> * @@ -300,8 +300,8 @@ static int avr32_ap7k_deassert_reset(struct target *target) return ERROR_OK; } -static int avr32_ap7k_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int avr32_ap7k_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { struct avr32_ap7k_common *ap7k = target_to_ap7k(target); struct breakpoint *breakpoint = NULL; @@ -309,7 +309,7 @@ static int avr32_ap7k_resume(struct target *target, int current, int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -321,7 +321,7 @@ static int avr32_ap7k_resume(struct target *target, int current, */ } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { #if 0 if (retval != ERROR_OK) @@ -382,8 +382,8 @@ static int avr32_ap7k_resume(struct target *target, int current, return ERROR_OK; } -static int avr32_ap7k_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int avr32_ap7k_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { LOG_ERROR("%s: implement me", __func__); @@ -431,7 +431,7 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -471,7 +471,7 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -510,7 +510,7 @@ static int avr32_ap7k_init_target(struct command_context *cmd_ctx, return ERROR_OK; } -static int avr32_ap7k_target_create(struct target *target, Jim_Interp *interp) +static int avr32_ap7k_target_create(struct target *target) { struct avr32_ap7k_common *ap7k = calloc(1, sizeof(struct avr32_ap7k_common)); diff --git a/src/target/avr32_ap7k.h b/src/target/avr32_ap7k.h index 6984b61013..ac35754f47 100644 --- a/src/target/avr32_ap7k.h +++ b/src/target/avr32_ap7k.h @@ -9,9 +9,11 @@ struct target; -#define AP7K_COMMON_MAGIC 0x4150374b +#define AP7K_COMMON_MAGIC 0x4150374bU + struct avr32_ap7k_common { - int common_magic; + unsigned int common_magic; + struct avr32_jtag jtag; struct reg_cache *core_cache; uint32_t core_regs[AVR32NUMCOREREGS]; diff --git a/src/target/avr32_jtag.c b/src/target/avr32_jtag.c index 6f46b00454..a9c4f8dd64 100644 --- a/src/target/avr32_jtag.c +++ b/src/target/avr32_jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> * diff --git a/src/target/avr32_mem.c b/src/target/avr32_mem.c index 045cf87f1b..835a501f03 100644 --- a/src/target/avr32_mem.c +++ b/src/target/avr32_mem.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> * diff --git a/src/target/avr32_regs.c b/src/target/avr32_regs.c index be307892eb..d6fd0e0020 100644 --- a/src/target/avr32_regs.c +++ b/src/target/avr32_regs.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> * diff --git a/src/target/avrt.c b/src/target/avrt.c index 335686546d..e25718bcc2 100644 --- a/src/target/avrt.c +++ b/src/target/avrt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Simon Qian * @@ -16,25 +16,25 @@ #define AVR_JTAG_INS_LEN 4 /* forward declarations */ -static int avr_target_create(struct target *target, Jim_Interp *interp); +static int avr_target_create(struct target *target); static int avr_init_target(struct command_context *cmd_ctx, struct target *target); static int avr_arch_state(struct target *target); static int avr_poll(struct target *target); static int avr_halt(struct target *target); -static int avr_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution); -static int avr_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints); +static int avr_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution); +static int avr_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints); static int avr_assert_reset(struct target *target); static int avr_deassert_reset(struct target *target); /* IR and DR functions */ -static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, int rti); -static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len, int rti); -static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti); -static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *ir_in, uint32_t ir_out, int dr_len, int rti); +static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len); +static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len); +static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len); +static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *ir_in, uint32_t ir_out, int dr_len); struct target_type avr_target = { .name = "avr", @@ -68,7 +68,7 @@ struct target_type avr_target = { .init_target = avr_init_target, }; -static int avr_target_create(struct target *target, Jim_Interp *interp) +static int avr_target_create(struct target *target) { struct avr_common *avr = calloc(1, sizeof(struct avr_common)); @@ -105,14 +105,15 @@ static int avr_halt(struct target *target) return ERROR_OK; } -static int avr_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int avr_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution) { LOG_DEBUG("%s", __func__); return ERROR_OK; } -static int avr_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) +static int avr_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { LOG_DEBUG("%s", __func__); return ERROR_OK; @@ -137,23 +138,23 @@ static int avr_deassert_reset(struct target *target) int avr_jtag_senddat(struct jtag_tap *tap, uint32_t *dr_in, uint32_t dr_out, int len) { - return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1); + return mcu_write_dr_u32(tap, dr_in, dr_out, len); } int avr_jtag_sendinstr(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out) { - return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN, 1); + return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN); } /* IR and DR functions */ static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, - int ir_len, int rti) + int ir_len) { if (!tap) { LOG_ERROR("invalid tap"); return ERROR_FAIL; } - if (ir_len != tap->ir_length) { + if ((unsigned int)ir_len != tap->ir_length) { LOG_ERROR("invalid ir_len"); return ERROR_FAIL; } @@ -166,7 +167,7 @@ static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, } static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, - int dr_len, int rti) + int dr_len) { if (!tap) { LOG_ERROR("invalid tap"); @@ -181,27 +182,27 @@ static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, } static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, - uint8_t ir_out, int ir_len, int rti) + uint8_t ir_out, int ir_len) { if (ir_len > 8) { LOG_ERROR("ir_len overflow, maximum is 8"); return ERROR_FAIL; } - mcu_write_ir(tap, ir_in, &ir_out, ir_len, rti); + mcu_write_ir(tap, ir_in, &ir_out, ir_len); return ERROR_OK; } static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *dr_in, - uint32_t dr_out, int dr_len, int rti) + uint32_t dr_out, int dr_len) { if (dr_len > 32) { LOG_ERROR("dr_len overflow, maximum is 32"); return ERROR_FAIL; } - mcu_write_dr(tap, (uint8_t *)dr_in, (uint8_t *)&dr_out, dr_len, rti); + mcu_write_dr(tap, (uint8_t *)dr_in, (uint8_t *)&dr_out, dr_len); return ERROR_OK; } diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index b031367863..a080416291 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -17,6 +17,11 @@ #include "breakpoints.h" #include "smp.h" +enum breakpoint_watchpoint { + BREAKPOINT, + WATCHPOINT, +}; + static const char * const breakpoint_type_strings[] = { "hardware", "software" @@ -33,7 +38,7 @@ static int bpwp_unique_id; static int breakpoint_add_internal(struct target *target, target_addr_t address, - uint32_t length, + unsigned int length, enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; @@ -47,7 +52,7 @@ static int breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_ERROR("Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", + LOG_TARGET_ERROR(target, "Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", address, breakpoint->unique_id); return ERROR_TARGET_DUPLICATE_BREAKPOINT; } @@ -78,16 +83,15 @@ static int breakpoint_add_internal(struct target *target, default: reason = "unknown reason"; fail: - LOG_ERROR("can't add breakpoint: %s", reason); + LOG_TARGET_ERROR(target, "can't add breakpoint: %s", reason); free((*breakpoint_p)->orig_instr); free(*breakpoint_p); *breakpoint_p = NULL; return retval; } - LOG_DEBUG("[%d] added %s breakpoint at " TARGET_ADDR_FMT + LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT " of length 0x%8.8x, (BPID: %" PRIu32 ")", - target->coreid, breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->address, (*breakpoint_p)->length, (*breakpoint_p)->unique_id); @@ -97,7 +101,7 @@ static int breakpoint_add_internal(struct target *target, static int context_breakpoint_add_internal(struct target *target, uint32_t asid, - uint32_t length, + unsigned int length, enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; @@ -110,7 +114,7 @@ static int context_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_ERROR("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", + LOG_TARGET_ERROR(target, "Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); return ERROR_TARGET_DUPLICATE_BREAKPOINT; } @@ -129,14 +133,14 @@ static int context_breakpoint_add_internal(struct target *target, (*breakpoint_p)->unique_id = bpwp_unique_id++; retval = target_add_context_breakpoint(target, *breakpoint_p); if (retval != ERROR_OK) { - LOG_ERROR("could not add breakpoint"); + LOG_TARGET_ERROR(target, "could not add breakpoint"); free((*breakpoint_p)->orig_instr); free(*breakpoint_p); *breakpoint_p = NULL; return retval; } - LOG_DEBUG("added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")", + LOG_TARGET_DEBUG(target, "added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")", breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->asid, (*breakpoint_p)->length, (*breakpoint_p)->unique_id); @@ -147,7 +151,7 @@ static int context_breakpoint_add_internal(struct target *target, static int hybrid_breakpoint_add_internal(struct target *target, target_addr_t address, uint32_t asid, - uint32_t length, + unsigned int length, enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; @@ -160,11 +164,11 @@ static int hybrid_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_ERROR("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", + LOG_TARGET_ERROR(target, "Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); return ERROR_TARGET_DUPLICATE_BREAKPOINT; } else if ((breakpoint->address == address) && (breakpoint->asid == 0)) { - LOG_ERROR("Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", + LOG_TARGET_ERROR(target, "Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", address, breakpoint->unique_id); return ERROR_TARGET_DUPLICATE_BREAKPOINT; @@ -185,13 +189,13 @@ static int hybrid_breakpoint_add_internal(struct target *target, retval = target_add_hybrid_breakpoint(target, *breakpoint_p); if (retval != ERROR_OK) { - LOG_ERROR("could not add breakpoint"); + LOG_TARGET_ERROR(target, "could not add breakpoint"); free((*breakpoint_p)->orig_instr); free(*breakpoint_p); *breakpoint_p = NULL; return retval; } - LOG_DEBUG( + LOG_TARGET_DEBUG(target, "added %s Hybrid breakpoint at address " TARGET_ADDR_FMT " of length 0x%8.8x, (BPID: %" PRIu32 ")", breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->address, @@ -203,7 +207,7 @@ static int hybrid_breakpoint_add_internal(struct target *target, int breakpoint_add(struct target *target, target_addr_t address, - uint32_t length, + unsigned int length, enum breakpoint_type type) { if (target->smp) { @@ -229,7 +233,7 @@ int breakpoint_add(struct target *target, int context_breakpoint_add(struct target *target, uint32_t asid, - uint32_t length, + unsigned int length, enum breakpoint_type type) { if (target->smp) { @@ -251,7 +255,7 @@ int context_breakpoint_add(struct target *target, int hybrid_breakpoint_add(struct target *target, target_addr_t address, uint32_t asid, - uint32_t length, + unsigned int length, enum breakpoint_type type) { if (target->smp) { @@ -270,7 +274,7 @@ int hybrid_breakpoint_add(struct target *target, } /* free up a breakpoint */ -static void breakpoint_free(struct target *target, struct breakpoint *breakpoint_to_remove) +static int breakpoint_free(struct target *target, struct breakpoint *breakpoint_to_remove) { struct breakpoint *breakpoint = target->breakpoints; struct breakpoint **breakpoint_p = &target->breakpoints; @@ -284,14 +288,21 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint } if (!breakpoint) - return; + return ERROR_OK; retval = target_remove_breakpoint(target, breakpoint); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "could not remove breakpoint #%d on this target", + breakpoint->number); + return retval; + } - LOG_DEBUG("free BPID: %" PRIu32 " --> %d", breakpoint->unique_id, retval); + LOG_TARGET_DEBUG(target, "free BPID: %" PRIu32 " --> %d", breakpoint->unique_id, retval); (*breakpoint_p) = breakpoint->next; free(breakpoint->orig_instr); free(breakpoint); + + return ERROR_OK; } static int breakpoint_remove_internal(struct target *target, target_addr_t address) @@ -306,77 +317,173 @@ static int breakpoint_remove_internal(struct target *target, target_addr_t addre } if (breakpoint) { - breakpoint_free(target, breakpoint); - return 1; + return breakpoint_free(target, breakpoint); } else { - if (!target->smp) - LOG_ERROR("no breakpoint at address " TARGET_ADDR_FMT " found", address); - return 0; + return ERROR_BREAKPOINT_NOT_FOUND; } } -static void breakpoint_remove_all_internal(struct target *target) +static int breakpoint_remove_all_internal(struct target *target) { + LOG_TARGET_DEBUG(target, "Delete all breakpoints"); + struct breakpoint *breakpoint = target->breakpoints; + int retval = ERROR_OK; while (breakpoint) { struct breakpoint *tmp = breakpoint; breakpoint = breakpoint->next; - breakpoint_free(target, tmp); + int status = breakpoint_free(target, tmp); + if (status != ERROR_OK) + retval = status; } + + return retval; } -void breakpoint_remove(struct target *target, target_addr_t address) +int breakpoint_remove(struct target *target, target_addr_t address) { + int retval = ERROR_OK; + unsigned int num_found_breakpoints = 0; if (target->smp) { - unsigned int num_breakpoints = 0; struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - num_breakpoints += breakpoint_remove_internal(curr, address); + int status = breakpoint_remove_internal(curr, address); + + if (status != ERROR_BREAKPOINT_NOT_FOUND) { + num_found_breakpoints++; + + if (status != ERROR_OK) { + LOG_TARGET_ERROR(curr, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address); + retval = status; + } + } } - if (!num_breakpoints) - LOG_ERROR("no breakpoint at address " TARGET_ADDR_FMT " found", address); + } else { - breakpoint_remove_internal(target, address); + retval = breakpoint_remove_internal(target, address); + + if (retval != ERROR_BREAKPOINT_NOT_FOUND) { + num_found_breakpoints++; + + if (retval != ERROR_OK) + LOG_TARGET_ERROR(target, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address); + } + } + + if (num_found_breakpoints == 0) { + LOG_TARGET_ERROR(target, "no breakpoint at address " TARGET_ADDR_FMT " found", address); + return ERROR_BREAKPOINT_NOT_FOUND; + } + + return retval; +} + +static int watchpoint_free(struct target *target, struct watchpoint *watchpoint_to_remove) +{ + struct watchpoint *watchpoint = target->watchpoints; + struct watchpoint **watchpoint_p = &target->watchpoints; + int retval; + + while (watchpoint) { + if (watchpoint == watchpoint_to_remove) + break; + watchpoint_p = &watchpoint->next; + watchpoint = watchpoint->next; + } + + if (!watchpoint) + return ERROR_OK; + retval = target_remove_watchpoint(target, watchpoint); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "could not remove watchpoint #%d on this target", + watchpoint->number); + return retval; + } + + LOG_TARGET_DEBUG(target, "free WPID: %d --> %d", watchpoint->unique_id, retval); + (*watchpoint_p) = watchpoint->next; + free(watchpoint); + + return ERROR_OK; +} + +static int watchpoint_remove_all_internal(struct target *target) +{ + struct watchpoint *watchpoint = target->watchpoints; + int retval = ERROR_OK; + + while (watchpoint) { + struct watchpoint *tmp = watchpoint; + watchpoint = watchpoint->next; + int status = watchpoint_free(target, tmp); + if (status != ERROR_OK) + retval = status; } + + return retval; } -void breakpoint_remove_all(struct target *target) +static int breakpoint_watchpoint_remove_all(struct target *target, enum breakpoint_watchpoint bp_wp) { + assert(bp_wp == BREAKPOINT || bp_wp == WATCHPOINT); + int retval = ERROR_OK; if (target->smp) { struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - breakpoint_remove_all_internal(curr); + + int status = ERROR_OK; + if (bp_wp == BREAKPOINT) + status = breakpoint_remove_all_internal(curr); + else + status = watchpoint_remove_all_internal(curr); + + if (status != ERROR_OK) + retval = status; } } else { - breakpoint_remove_all_internal(target); + if (bp_wp == BREAKPOINT) + retval = breakpoint_remove_all_internal(target); + else + retval = watchpoint_remove_all_internal(target); } + + return retval; +} + +int breakpoint_remove_all(struct target *target) +{ + return breakpoint_watchpoint_remove_all(target, BREAKPOINT); } -static void breakpoint_clear_target_internal(struct target *target) +int watchpoint_remove_all(struct target *target) { - LOG_DEBUG("Delete all breakpoints for target: %s", - target_name(target)); - while (target->breakpoints) - breakpoint_free(target, target->breakpoints); + return breakpoint_watchpoint_remove_all(target, WATCHPOINT); } -void breakpoint_clear_target(struct target *target) +int breakpoint_clear_target(struct target *target) { + int retval = ERROR_OK; + if (target->smp) { struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - breakpoint_clear_target_internal(curr); + int status = breakpoint_remove_all_internal(curr); + + if (status != ERROR_OK) + retval = status; } } else { - breakpoint_clear_target_internal(target); + retval = breakpoint_remove_all_internal(target); } + + return retval; } struct breakpoint *breakpoint_find(struct target *target, target_addr_t address) @@ -392,8 +499,8 @@ struct breakpoint *breakpoint_find(struct target *target, target_addr_t address) return NULL; } -int watchpoint_add_internal(struct target *target, target_addr_t address, - uint32_t length, enum watchpoint_rw rw, uint32_t value, uint32_t mask) +static int watchpoint_add_internal(struct target *target, target_addr_t address, + unsigned int length, enum watchpoint_rw rw, uint64_t value, uint64_t mask) { struct watchpoint *watchpoint = target->watchpoints; struct watchpoint **watchpoint_p = &target->watchpoints; @@ -406,7 +513,7 @@ int watchpoint_add_internal(struct target *target, target_addr_t address, || watchpoint->value != value || watchpoint->mask != mask || watchpoint->rw != rw) { - LOG_ERROR("address " TARGET_ADDR_FMT + LOG_TARGET_ERROR(target, "address " TARGET_ADDR_FMT " already has watchpoint %d", address, watchpoint->unique_id); return ERROR_FAIL; @@ -440,7 +547,7 @@ int watchpoint_add_internal(struct target *target, target_addr_t address, default: reason = "unrecognized error"; bye: - LOG_ERROR("can't add %s watchpoint at " TARGET_ADDR_FMT ", %s", + LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s", watchpoint_rw_strings[(*watchpoint_p)->rw], address, reason); free(*watchpoint_p); @@ -448,9 +555,8 @@ int watchpoint_add_internal(struct target *target, target_addr_t address, return retval; } - LOG_DEBUG("[%d] added %s watchpoint at " TARGET_ADDR_FMT - " of length 0x%8.8" PRIx32 " (WPID: %d)", - target->coreid, + LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT + " of length 0x%8.8x (WPID: %d)", watchpoint_rw_strings[(*watchpoint_p)->rw], (*watchpoint_p)->address, (*watchpoint_p)->length, @@ -460,7 +566,7 @@ int watchpoint_add_internal(struct target *target, target_addr_t address, } int watchpoint_add(struct target *target, target_addr_t address, - uint32_t length, enum watchpoint_rw rw, uint32_t value, uint32_t mask) + unsigned int length, enum watchpoint_rw rw, uint64_t value, uint64_t mask) { if (target->smp) { struct target_list *head; @@ -479,28 +585,7 @@ int watchpoint_add(struct target *target, target_addr_t address, } } -static void watchpoint_free(struct target *target, struct watchpoint *watchpoint_to_remove) -{ - struct watchpoint *watchpoint = target->watchpoints; - struct watchpoint **watchpoint_p = &target->watchpoints; - int retval; - - while (watchpoint) { - if (watchpoint == watchpoint_to_remove) - break; - watchpoint_p = &watchpoint->next; - watchpoint = watchpoint->next; - } - - if (!watchpoint) - return; - retval = target_remove_watchpoint(target, watchpoint); - LOG_DEBUG("free WPID: %d --> %d", watchpoint->unique_id, retval); - (*watchpoint_p) = watchpoint->next; - free(watchpoint); -} - -int watchpoint_remove_internal(struct target *target, target_addr_t address) +static int watchpoint_remove_internal(struct target *target, target_addr_t address) { struct watchpoint *watchpoint = target->watchpoints; @@ -511,38 +596,66 @@ int watchpoint_remove_internal(struct target *target, target_addr_t address) } if (watchpoint) { - watchpoint_free(target, watchpoint); - return 1; + return watchpoint_free(target, watchpoint); } else { - if (!target->smp) - LOG_ERROR("no watchpoint at address " TARGET_ADDR_FMT " found", address); - return 0; + return ERROR_WATCHPOINT_NOT_FOUND; } } -void watchpoint_remove(struct target *target, target_addr_t address) +int watchpoint_remove(struct target *target, target_addr_t address) { + int retval = ERROR_OK; + unsigned int num_found_watchpoints = 0; if (target->smp) { - unsigned int num_watchpoints = 0; struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; - num_watchpoints += watchpoint_remove_internal(curr, address); + int status = watchpoint_remove_internal(curr, address); + + if (status != ERROR_WATCHPOINT_NOT_FOUND) { + num_found_watchpoints++; + + if (status != ERROR_OK) { + LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address); + retval = status; + } + } } - if (num_watchpoints == 0) - LOG_ERROR("no watchpoint at address " TARGET_ADDR_FMT " num_watchpoints", address); } else { - watchpoint_remove_internal(target, address); + retval = watchpoint_remove_internal(target, address); + + if (retval != ERROR_WATCHPOINT_NOT_FOUND) { + num_found_watchpoints++; + + if (retval != ERROR_OK) + LOG_TARGET_ERROR(target, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address); + } } + + if (num_found_watchpoints == 0) { + LOG_TARGET_ERROR(target, "no watchpoint at address " TARGET_ADDR_FMT " found", address); + return ERROR_WATCHPOINT_NOT_FOUND; + } + + return retval; } -void watchpoint_clear_target(struct target *target) +int watchpoint_clear_target(struct target *target) { - LOG_DEBUG("Delete all watchpoints for target: %s", - target_name(target)); - while (target->watchpoints) - watchpoint_free(target, target->watchpoints); + LOG_TARGET_DEBUG(target, "Delete all watchpoints"); + + struct watchpoint *watchpoint = target->watchpoints; + int retval = ERROR_OK; + + while (watchpoint) { + struct watchpoint *tmp = watchpoint; + watchpoint = watchpoint->next; + int status = watchpoint_free(target, tmp); + if (status != ERROR_OK) + retval = status; + } + return retval; } int watchpoint_hit(struct target *target, enum watchpoint_rw *rw, @@ -558,7 +671,7 @@ int watchpoint_hit(struct target *target, enum watchpoint_rw *rw, *rw = hit_watchpoint->rw; *address = hit_watchpoint->address; - LOG_DEBUG("Found hit watchpoint at " TARGET_ADDR_FMT " (WPID: %d)", + LOG_TARGET_DEBUG(target, "Found hit watchpoint at " TARGET_ADDR_FMT " (WPID: %d)", hit_watchpoint->address, hit_watchpoint->unique_id); diff --git a/src/target/breakpoints.h b/src/target/breakpoints.h index a9ae484357..0789267c7d 100644 --- a/src/target/breakpoints.h +++ b/src/target/breakpoints.h @@ -26,7 +26,7 @@ enum watchpoint_rw { struct breakpoint { target_addr_t address; uint32_t asid; - int length; + unsigned int length; enum breakpoint_type type; bool is_set; unsigned int number; @@ -36,11 +36,13 @@ struct breakpoint { int linked_brp; }; +#define WATCHPOINT_IGNORE_DATA_VALUE_MASK (~(uint64_t)0) + struct watchpoint { target_addr_t address; - uint32_t length; - uint32_t mask; - uint32_t value; + unsigned int length; + uint64_t mask; + uint64_t value; enum watchpoint_rw rw; bool is_set; unsigned int number; @@ -48,15 +50,16 @@ struct watchpoint { int unique_id; }; -void breakpoint_clear_target(struct target *target); +int breakpoint_clear_target(struct target *target); int breakpoint_add(struct target *target, - target_addr_t address, uint32_t length, enum breakpoint_type type); + target_addr_t address, unsigned int length, enum breakpoint_type type); int context_breakpoint_add(struct target *target, - uint32_t asid, uint32_t length, enum breakpoint_type type); + uint32_t asid, unsigned int length, enum breakpoint_type type); int hybrid_breakpoint_add(struct target *target, - target_addr_t address, uint32_t asid, uint32_t length, enum breakpoint_type type); -void breakpoint_remove(struct target *target, target_addr_t address); -void breakpoint_remove_all(struct target *target); + target_addr_t address, uint32_t asid, unsigned int length, + enum breakpoint_type type); +int breakpoint_remove(struct target *target, target_addr_t address); +int breakpoint_remove_all(struct target *target); struct breakpoint *breakpoint_find(struct target *target, target_addr_t address); @@ -66,11 +69,12 @@ static inline void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int breakpoint->number = hw_number; } -void watchpoint_clear_target(struct target *target); +int watchpoint_clear_target(struct target *target); int watchpoint_add(struct target *target, - target_addr_t address, uint32_t length, - enum watchpoint_rw rw, uint32_t value, uint32_t mask); -void watchpoint_remove(struct target *target, target_addr_t address); + target_addr_t address, unsigned int length, + enum watchpoint_rw rw, uint64_t value, uint64_t mask); +int watchpoint_remove(struct target *target, target_addr_t address); +int watchpoint_remove_all(struct target *target); /* report type and address of just hit watchpoint */ int watchpoint_hit(struct target *target, enum watchpoint_rw *rw, @@ -82,4 +86,7 @@ static inline void watchpoint_set(struct watchpoint *watchpoint, unsigned int nu watchpoint->number = number; } +#define ERROR_BREAKPOINT_NOT_FOUND (-1600) +#define ERROR_WATCHPOINT_NOT_FOUND (-1601) + #endif /* OPENOCD_TARGET_BREAKPOINTS_H */ diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index c5cb8d47ab..2ebbf65774 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -52,6 +52,7 @@ #include "transport/transport.h" #include "smp.h" #include <helper/bits.h> +#include <helper/nvp.h> #include <helper/time_support.h> static int cortex_a_poll(struct target *target); @@ -313,19 +314,6 @@ static int cortex_a_exec_opcode(struct target *target, return retval; } -/* Write to memory mapped registers directly with no cache or mmu handling */ -static int cortex_a_dap_write_memap_register_u32(struct target *target, - uint32_t address, - uint32_t value) -{ - int retval; - struct armv7a_common *armv7a = target_to_armv7a(target); - - retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value); - - return retval; -} - /* * Cortex-A implementation of Debug Programmer's Model * @@ -470,6 +458,28 @@ static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm, return retval; } +static int cortex_a_instr_write_data_r0_r1(struct arm_dpm *dpm, + uint32_t opcode, uint64_t data) +{ + struct cortex_a_common *a = dpm_to_a(dpm); + uint32_t dscr = DSCR_INSTR_COMP; + int retval; + + retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data & 0xffffffffULL); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a_instr_write_data_rt_dcc(dpm, 1, data >> 32); + if (retval != ERROR_OK) + return retval; + + /* then the opcode, taking data from R0, R1 */ + retval = cortex_a_exec_opcode(a->armv7a_common.arm.target, + opcode, + &dscr); + return retval; +} + static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm) { struct target *target = dpm->arm->target; @@ -538,7 +548,30 @@ static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm, return cortex_a_instr_read_data_rt_dcc(dpm, 0, data); } -static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, +static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm, + uint32_t opcode, uint64_t *data) +{ + uint32_t lo, hi; + int retval; + + /* the opcode, writing data to RO, R1 */ + retval = cortex_a_instr_read_data_r0(dpm, opcode, &lo); + if (retval != ERROR_OK) + return retval; + + *data = lo; + + /* write R1 to DCC */ + retval = cortex_a_instr_read_data_rt_dcc(dpm, 1, &hi); + if (retval != ERROR_OK) + return retval; + + *data |= (uint64_t)hi << 32; + + return retval; +} + +static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, uint32_t addr, uint32_t control) { struct cortex_a_common *a = dpm_to_a(dpm); @@ -562,19 +595,18 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, vr += 4 * index_t; cr += 4 * index_t; - LOG_DEBUG("A: bpwp enable, vr %08x cr %08x", - (unsigned) vr, (unsigned) cr); + LOG_DEBUG("A: bpwp enable, vr %08" PRIx32 " cr %08" PRIx32, vr, cr); - retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target, + retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, vr, addr); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target, + retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, cr, control); return retval; } -static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) +static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) { struct cortex_a_common *a = dpm_to_a(dpm); uint32_t cr; @@ -592,10 +624,10 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) } cr += 4 * index_t; - LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr); + LOG_DEBUG("A: bpwp disable, cr %08" PRIx32, cr); /* clear control register */ - return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0); + return mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, cr, 0); } static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr) @@ -611,10 +643,12 @@ static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr) dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc; dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0; + dpm->instr_write_data_r0_r1 = cortex_a_instr_write_data_r0_r1; dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync; dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc; dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0; + dpm->instr_read_data_r0_r1 = cortex_a_instr_read_data_r0_r1; dpm->bpwp_enable = cortex_a_bpwp_enable; dpm->bpwp_disable = cortex_a_bpwp_disable; @@ -783,8 +817,8 @@ static int cortex_a_halt(struct target *target) return ERROR_OK; } -static int cortex_a_internal_restore(struct target *target, int current, - target_addr_t *address, int handle_breakpoints, int debug_execution) +static int cortex_a_internal_restore(struct target *target, bool current, + target_addr_t *address, bool handle_breakpoints, bool debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; @@ -807,15 +841,15 @@ static int cortex_a_internal_restore(struct target *target, int current, armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true; /* Make sure we are in Thumb mode */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0, 32, + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0, 32) | (1 << 24)); - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true; - armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true; + armv7m->core_cache->reg_list[ARMV7M_XPSR].dirty = true; + armv7m->core_cache->reg_list[ARMV7M_XPSR].valid = true; } #endif - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ resume_pc = buf_get_u32(arm->pc->value, 0, 32); if (!current) resume_pc = *address; @@ -931,7 +965,7 @@ static int cortex_a_internal_restart(struct target *target) return ERROR_OK; } -static int cortex_a_restore_smp(struct target *target, int handle_breakpoints) +static int cortex_a_restore_smp(struct target *target, bool handle_breakpoints) { int retval = 0; struct target_list *head; @@ -942,16 +976,16 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints) if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) { /* resume current address , not in step mode */ - retval += cortex_a_internal_restore(curr, 1, &address, - handle_breakpoints, 0); + retval += cortex_a_internal_restore(curr, true, &address, + handle_breakpoints, false); retval += cortex_a_internal_restart(curr); } } return retval; } -static int cortex_a_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int cortex_a_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { int retval = 0; /* dummy resume for smp toggle in order to reduce gdb impact */ @@ -963,7 +997,8 @@ static int cortex_a_resume(struct target *target, int current, target_call_event_callbacks(target, TARGET_EVENT_RESUMED); return 0; } - cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution); + cortex_a_internal_restore(target, current, &address, handle_breakpoints, + debug_execution); if (target->smp) { target->gdb_service->core[0] = -1; retval = cortex_a_restore_smp(target, handle_breakpoints); @@ -1134,8 +1169,31 @@ static int cortex_a_set_dscr_bits(struct target *target, return retval; } -static int cortex_a_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +/* + * Single-step on ARMv7a/r is implemented through a HW breakpoint that hits + * every instruction at any address except the address of the current + * instruction. + * Such HW breakpoint is never hit in case of a single instruction that jumps + * on itself (infinite loop), or a WFI or a WFE. In this case, halt the CPU + * after a timeout. + * The jump on itself would be executed several times before the timeout forces + * the halt, but this is not an issue. In ARMv7a/r there are few "pathological" + * instructions, listed below, that jumps on itself and that can have side + * effects if executed more than once; but they are not considered as real use + * cases generated by a compiler. + * Some example: + * - 'pop {pc}' or multi register 'pop' including PC, when the new PC value is + * the same value of current PC. The single step will not stop at the first + * 'pop' and will continue taking values from the stack, modifying SP at each + * iteration. + * - 'rfeda', 'rfedb', 'rfeia', 'rfeib', when the new PC value is the same + * value of current PC. The register provided to the instruction (usually SP) + * will be incremented or decremented at each iteration. + * + * TODO: fix exit in case of error, cleaning HW breakpoints. + */ +static int cortex_a_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { struct cortex_a_common *cortex_a = target_to_cortex_a(target); struct armv7a_common *armv7a = target_to_armv7a(target); @@ -1146,11 +1204,11 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ r = arm->pc; if (!current) buf_set_u32(r->value, 0, 32, address); @@ -1161,7 +1219,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre * But since Cortex-A uses breakpoint for single step, * we MUST handle breakpoints. */ - handle_breakpoints = 1; + handle_breakpoints = true; if (handle_breakpoints) { breakpoint = breakpoint_find(target, address); if (breakpoint) @@ -1188,19 +1246,38 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre target->debug_reason = DBG_REASON_SINGLESTEP; - retval = cortex_a_resume(target, 1, address, 0, 0); + retval = cortex_a_resume(target, true, address, false, false); if (retval != ERROR_OK) return retval; - int64_t then = timeval_ms(); + // poll at least once before starting the timeout + retval = cortex_a_poll(target); + if (retval != ERROR_OK) + return retval; + + int64_t then = timeval_ms() + 100; while (target->state != TARGET_HALTED) { + if (timeval_ms() > then) + break; + retval = cortex_a_poll(target); if (retval != ERROR_OK) return retval; - if (target->state == TARGET_HALTED) - break; - if (timeval_ms() > then + 1000) { - LOG_ERROR("timeout waiting for target halt"); + } + + if (target->state != TARGET_HALTED) { + LOG_TARGET_DEBUG(target, "timeout waiting for target halt, try halt"); + + retval = cortex_a_halt(target); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a_poll(target); + if (retval != ERROR_OK) + return retval; + + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "timeout waiting for target halt"); return ERROR_FAIL; } } @@ -1220,9 +1297,6 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre if (breakpoint) cortex_a_set_breakpoint(target, breakpoint, 0); - if (target->state != TARGET_HALTED) - LOG_DEBUG("target stepped"); - return ERROR_OK; } @@ -1275,13 +1349,13 @@ static int cortex_a_set_breakpoint(struct target *target, brp_list[brp_i].used = true; brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].control = control; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; @@ -1290,21 +1364,34 @@ static int cortex_a_set_breakpoint(struct target *target, brp_list[brp_i].value); } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; - /* length == 2: Thumb breakpoint */ - if (breakpoint->length == 2) + if (breakpoint->length == 2) { + /* length == 2: Thumb breakpoint */ buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); - else - /* length == 3: Thumb-2 breakpoint, actual encoding is - * a regular Thumb BKPT instruction but we replace a - * 32bit Thumb-2 instruction, so fix-up the breakpoint - * length - */ - if (breakpoint->length == 3) { + } else if (breakpoint->length == 3) { + /* length == 3: Thumb-2 breakpoint, actual encoding is + * a regular Thumb BKPT instruction but we replace a + * 32bit Thumb-2 instruction, so fix-up the breakpoint + * length + */ buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); breakpoint->length = 4; - } else + } else { /* length == 4, normal ARM breakpoint */ buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11)); + } + + /* + * ARMv7-A/R fetches instructions in little-endian on both LE and BE CPUs. + * But Cortex-R4 and Cortex-R5 big-endian require BE instructions. + * https://developer.arm.com/documentation/den0042/a/Coding-for-Cortex-R-Processors/Endianness + * https://developer.arm.com/documentation/den0013/d/Porting/Endianness + */ + if ((((cortex_a->cpuid & CPUDBG_CPUID_MASK) == CPUDBG_CPUID_CORTEX_R4) || + ((cortex_a->cpuid & CPUDBG_CPUID_MASK) == CPUDBG_CPUID_CORTEX_R5)) && + target->endianness == TARGET_BIG_ENDIAN) { + // In place swapping is allowed + buf_bswap32(code, code, 4); + } retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, @@ -1314,10 +1401,7 @@ static int cortex_a_set_breakpoint(struct target *target, return retval; /* make sure data cache is cleaned & invalidated down to PoC */ - if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) { - armv7a_cache_flush_virt(target, breakpoint->address, - breakpoint->length); - } + armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length); retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, @@ -1326,10 +1410,8 @@ static int cortex_a_set_breakpoint(struct target *target, return retval; /* update i-cache at breakpoint location */ - armv7a_l1_d_cache_inval_virt(target, breakpoint->address, - breakpoint->length); - armv7a_l1_i_cache_inval_virt(target, breakpoint->address, - breakpoint->length); + armv7a_l1_d_cache_inval_virt(target, breakpoint->address, breakpoint->length); + armv7a_l1_i_cache_inval_virt(target, breakpoint->address, breakpoint->length); breakpoint->is_set = true; } @@ -1369,13 +1451,13 @@ static int cortex_a_set_context_breakpoint(struct target *target, brp_list[brp_i].used = true; brp_list[brp_i].value = (breakpoint->asid); brp_list[brp_i].control = control; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; @@ -1435,13 +1517,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi brp_list[brp_1].used = true; brp_list[brp_1].value = (breakpoint->asid); brp_list[brp_1].control = control_ctx; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn, brp_list[brp_1].value); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn, brp_list[brp_1].control); if (retval != ERROR_OK) return retval; @@ -1453,13 +1535,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi brp_list[brp_2].used = true; brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_2].control = control_iva; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn, brp_list[brp_2].value); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn, brp_list[brp_2].control); if (retval != ERROR_OK) return retval; @@ -1492,13 +1574,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b brp_list[brp_i].used = false; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; @@ -1511,13 +1593,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b brp_list[brp_j].used = false; brp_list[brp_j].value = 0; brp_list[brp_j].control = 0; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn, brp_list[brp_j].control); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn, brp_list[brp_j].value); if (retval != ERROR_OK) return retval; @@ -1536,13 +1618,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b brp_list[brp_i].used = false; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; @@ -1552,10 +1634,8 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b } else { /* make sure data cache is cleaned & invalidated down to PoC */ - if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) { - armv7a_cache_flush_virt(target, breakpoint->address, + armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length); - } /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { @@ -1739,14 +1819,14 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat wrp_list[wrp_i].value = address; wrp_list[wrp_i].control = control; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, wrp_list[wrp_i].value); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, wrp_list[wrp_i].control); if (retval != ERROR_OK) return retval; @@ -1788,13 +1868,13 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w wrp_list[wrp_i].used = false; wrp_list[wrp_i].value = 0; wrp_list[wrp_i].control = 0; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, wrp_list[wrp_i].control); if (retval != ERROR_OK) return retval; - retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, + retval = mem_ap_write_atomic_u32(armv7a->debug_ap, + armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, wrp_list[wrp_i].value); if (retval != ERROR_OK) return retval; @@ -1884,7 +1964,7 @@ static int cortex_a_assert_reset(struct target *target) } /* registers are now invalid */ - if (target_was_examined(target)) + if (armv7a->arm.core_cache) register_cache_invalidate(armv7a->arm.core_cache); target->state = TARGET_RESET; @@ -2224,7 +2304,7 @@ static int cortex_a_write_cpu_memory(struct target *target, LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32, address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2246,7 +2326,7 @@ static int cortex_a_write_cpu_memory(struct target *target, /* Switch to non-blocking mode if not already in that mode. */ retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr); if (retval != ERROR_OK) - goto out; + return retval; /* Mark R0 as dirty. */ arm_reg_current(arm, 0)->dirty = true; @@ -2254,16 +2334,16 @@ static int cortex_a_write_cpu_memory(struct target *target, /* Read DFAR and DFSR, as they will be modified in the event of a fault. */ retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr); if (retval != ERROR_OK) - goto out; + return retval; /* Get the memory address into R0. */ retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRRX, address); if (retval != ERROR_OK) - goto out; + return retval; retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) - goto out; + return retval; if (size == 4 && (address % 4) == 0) { /* We are doing a word-aligned transfer, so use fast mode. */ @@ -2288,7 +2368,6 @@ static int cortex_a_write_cpu_memory(struct target *target, retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr); } -out: final_retval = retval; /* Switch to non-blocking mode if not already in that mode. */ @@ -2542,7 +2621,7 @@ static int cortex_a_read_cpu_memory(struct target *target, LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32, address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2564,7 +2643,7 @@ static int cortex_a_read_cpu_memory(struct target *target, /* Switch to non-blocking mode if not already in that mode. */ retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr); if (retval != ERROR_OK) - goto out; + return retval; /* Mark R0 as dirty. */ arm_reg_current(arm, 0)->dirty = true; @@ -2572,16 +2651,16 @@ static int cortex_a_read_cpu_memory(struct target *target, /* Read DFAR and DFSR, as they will be modified in the event of a fault. */ retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr); if (retval != ERROR_OK) - goto out; + return retval; /* Get the memory address into R0. */ retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRRX, address); if (retval != ERROR_OK) - goto out; + return retval; retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) - goto out; + return retval; if (size == 4 && (address % 4) == 0) { /* We are doing a word-aligned transfer, so use fast mode. */ @@ -2607,7 +2686,6 @@ static int cortex_a_read_cpu_memory(struct target *target, retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr); } -out: final_retval = retval; /* Switch to non-blocking mode if not already in that mode. */ @@ -2745,9 +2823,6 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address, LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32, address, size, count); - /* memory writes bypass the caches, must flush before writing */ - armv7a_cache_auto_flush_on_write(target, address, size * count); - cortex_a_prep_memaccess(target, 0); retval = cortex_a_write_cpu_memory(target, address, size, count, buffer); cortex_a_post_memaccess(target, 0); @@ -2874,23 +2949,20 @@ static int cortex_a_examine_first(struct target *target) int retval = ERROR_OK; uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1; - if (armv7a->debug_ap) { - dap_put_ap(armv7a->debug_ap); - armv7a->debug_ap = NULL; - } - - if (pc->ap_num == DP_APSEL_INVALID) { - /* Search for the APB-AP - it is needed for access to debug registers */ - retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap); - if (retval != ERROR_OK) { - LOG_ERROR("Could not find APB-AP for debug access"); - return retval; - } - } else { - armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num); - if (!armv7a->debug_ap) { - LOG_ERROR("Cannot get AP"); - return ERROR_FAIL; + if (!armv7a->debug_ap) { + if (pc->ap_num == DP_APSEL_INVALID) { + /* Search for the APB-AP - it is needed for access to debug registers */ + retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap); + if (retval != ERROR_OK) { + LOG_ERROR("Could not find APB-AP for debug access"); + return retval; + } + } else { + armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num); + if (!armv7a->debug_ap) { + LOG_ERROR("Cannot get AP"); + return ERROR_FAIL; + } } } @@ -2903,14 +2975,12 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_ap->memaccess_tck = 80; if (!target->dbgbase_set) { - LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table", - target->cmd_name); + LOG_TARGET_DEBUG(target, "dbgbase is not set, trying to detect using the ROM table"); /* Lookup Processor DAP */ retval = dap_lookup_cs_component(armv7a->debug_ap, ARM_CS_C9_DEVTYPE_CORE_DEBUG, &armv7a->debug_base, target->coreid); if (retval != ERROR_OK) { - LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.", - target->cmd_name); + LOG_TARGET_ERROR(target, "Can't detect dbgbase from the ROM table; you need to specify it explicitly"); return retval; } LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT, @@ -2919,8 +2989,9 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_base = target->dbgbase; if ((armv7a->debug_base & (1UL<<31)) == 0) - LOG_WARNING("Debug base address for target %s has bit 31 set to 0. Access to debug registers will likely fail!\n" - "Please fix the target configuration.", target_name(target)); + LOG_TARGET_WARNING(target, + "Debug base address has bit 31 set to 0. Access to debug registers will likely fail!\n" + "Please fix the target configuration"); retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DIDR, &didr); @@ -2946,29 +3017,29 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGPRSR 0x%" PRIx32, dbg_osreg); if ((dbg_osreg & PRSR_POWERUP_STATUS) == 0) { - LOG_ERROR("target->coreid %" PRId32 " powered down!", target->coreid); + LOG_TARGET_ERROR(target, "powered down!"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } if (dbg_osreg & PRSR_STICKY_RESET_STATUS) - LOG_DEBUG("target->coreid %" PRId32 " was reset!", target->coreid); + LOG_TARGET_DEBUG(target, "was reset!"); /* Read DBGOSLSR and check if OSLK is implemented */ retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGOSLSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGOSLSR 0x%" PRIx32, dbg_osreg); /* check if OS Lock is implemented */ if ((dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM0 || (dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM1) { /* check if OS Lock is set */ if (dbg_osreg & OSLSR_OSLK) { - LOG_DEBUG("target->coreid %" PRId32 " OSLock set! Trying to unlock", target->coreid); + LOG_TARGET_DEBUG(target, "OSLock set! Trying to unlock"); retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLAR, @@ -2979,8 +3050,7 @@ static int cortex_a_examine_first(struct target *target) /* if we fail to access the register or cannot reset the OSLK bit, bail out */ if (retval != ERROR_OK || (dbg_osreg & OSLSR_OSLK) != 0) { - LOG_ERROR("target->coreid %" PRId32 " OSLock sticky, core not powered?", - target->coreid); + LOG_TARGET_ERROR(target, "OSLock sticky, core not powered?"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } @@ -2993,13 +3063,11 @@ static int cortex_a_examine_first(struct target *target) return retval; if (dbg_idpfr1 & 0x000000f0) { - LOG_DEBUG("target->coreid %" PRId32 " has security extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has security extensions"); armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT; } if (dbg_idpfr1 & 0x0000f000) { - LOG_DEBUG("target->coreid %" PRId32 " has virtualization extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has virtualization extensions"); /* * overwrite and simplify the checks. * virtualization extensions require implementation of security extension @@ -3110,7 +3178,7 @@ static int cortex_a_init_arch_info(struct target *target, return ERROR_OK; } -static int cortex_a_target_create(struct target *target, Jim_Interp *interp) +static int cortex_a_target_create(struct target *target) { struct cortex_a_common *cortex_a; struct adiv5_private_config *pc; @@ -3132,7 +3200,7 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp) return cortex_a_init_arch_info(target, cortex_a, pc->dap); } -static int cortex_r4_target_create(struct target *target, Jim_Interp *interp) +static int cortex_r4_target_create(struct target *target) { struct cortex_a_common *cortex_a; struct adiv5_private_config *pc; @@ -3187,8 +3255,8 @@ static int cortex_a_mmu(struct target *target, int *enabled) struct armv7a_common *armv7a = target_to_armv7a(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } if (armv7a->is_armv7r) @@ -3251,15 +3319,15 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) struct target *target = get_current_target(CMD_CTX); struct cortex_a_common *cortex_a = target_to_cortex_a(target); - static const struct jim_nvp nvp_maskisr_modes[] = { + static const struct nvp nvp_maskisr_modes[] = { { .name = "off", .value = CORTEX_A_ISRMASK_OFF }, { .name = "on", .value = CORTEX_A_ISRMASK_ON }, { .name = NULL, .value = -1 }, }; - const struct jim_nvp *n; + const struct nvp *n; if (CMD_ARGC > 0) { - n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]); if (!n->name) { LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; @@ -3268,7 +3336,7 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) cortex_a->isrmasking_mode = n->value; } - n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode); + n = nvp_value2name(nvp_maskisr_modes, cortex_a->isrmasking_mode); command_print(CMD, "cortex_a interrupt mask %s", n->name); return ERROR_OK; @@ -3279,22 +3347,22 @@ COMMAND_HANDLER(handle_cortex_a_dacrfixup_command) struct target *target = get_current_target(CMD_CTX); struct cortex_a_common *cortex_a = target_to_cortex_a(target); - static const struct jim_nvp nvp_dacrfixup_modes[] = { + static const struct nvp nvp_dacrfixup_modes[] = { { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF }, { .name = "on", .value = CORTEX_A_DACRFIXUP_ON }, { .name = NULL, .value = -1 }, }; - const struct jim_nvp *n; + const struct nvp *n; if (CMD_ARGC > 0) { - n = jim_nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]); + n = nvp_name2value(nvp_dacrfixup_modes, CMD_ARGV[0]); if (!n->name) return ERROR_COMMAND_SYNTAX_ERROR; cortex_a->dacrfixup_mode = n->value; } - n = jim_nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode); + n = nvp_value2name(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode); command_print(CMD, "cortex_a domain access control fixup %s", n->name); return ERROR_OK; diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index abf358d0d4..8e438fd958 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -19,8 +19,7 @@ #include "armv7a.h" -#define CORTEX_A_COMMON_MAGIC 0x411fc082 -#define CORTEX_A15_COMMON_MAGIC 0x413fc0f1 +#define CORTEX_A_COMMON_MAGIC 0x411fc082U #define CORTEX_A5_PARTNUM 0xc05 #define CORTEX_A7_PARTNUM 0xc07 @@ -31,6 +30,9 @@ #define CORTEX_A_MIDR_PARTNUM_SHIFT 4 #define CPUDBG_CPUID 0xD00 +#define CPUDBG_CPUID_MASK 0xff00fff0 +#define CPUDBG_CPUID_CORTEX_R4 0x4100c140 +#define CPUDBG_CPUID_CORTEX_R5 0x4100c150 #define CPUDBG_CTYPR 0xD04 #define CPUDBG_TTYPR 0xD0C #define CPUDBG_LOCKACCESS 0xFB0 @@ -68,7 +70,9 @@ struct cortex_a_wrp { }; struct cortex_a_common { - int common_magic; + unsigned int common_magic; + + struct armv7a_common armv7a_common; /* Context information */ uint32_t cpudbg_dscr; @@ -97,9 +101,6 @@ struct cortex_a_common { enum cortex_a_isrmasking_mode isrmasking_mode; enum cortex_a_dacrfixup_mode dacrfixup_mode; - - struct armv7a_common armv7a_common; - }; static inline struct cortex_a_common * diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 1682f5dec9..0501a5b2f5 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -28,6 +28,8 @@ #include "register.h" #include "arm_opcodes.h" #include "arm_semihosting.h" +#include "smp.h" +#include <helper/nvp.h> #include <helper/time_support.h> #include <rtt/rtt.h> @@ -48,61 +50,95 @@ /* Supported Cortex-M Cores */ static const struct cortex_m_part_info cortex_m_parts[] = { { - .partno = CORTEX_M0_PARTNO, + .impl_part = CORTEX_M0_PARTNO, .name = "Cortex-M0", .arch = ARM_ARCH_V6M, }, { - .partno = CORTEX_M0P_PARTNO, + .impl_part = CORTEX_M0P_PARTNO, .name = "Cortex-M0+", .arch = ARM_ARCH_V6M, }, { - .partno = CORTEX_M1_PARTNO, + .impl_part = CORTEX_M1_PARTNO, .name = "Cortex-M1", .arch = ARM_ARCH_V6M, }, { - .partno = CORTEX_M3_PARTNO, + .impl_part = CORTEX_M3_PARTNO, .name = "Cortex-M3", .arch = ARM_ARCH_V7M, .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K, }, { - .partno = CORTEX_M4_PARTNO, + .impl_part = CORTEX_M4_PARTNO, .name = "Cortex-M4", .arch = ARM_ARCH_V7M, .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K, }, { - .partno = CORTEX_M7_PARTNO, + .impl_part = CORTEX_M7_PARTNO, .name = "Cortex-M7", .arch = ARM_ARCH_V7M, .flags = CORTEX_M_F_HAS_FPV5, }, { - .partno = CORTEX_M23_PARTNO, + .impl_part = CORTEX_M23_PARTNO, .name = "Cortex-M23", .arch = ARM_ARCH_V8M, }, { - .partno = CORTEX_M33_PARTNO, + .impl_part = CORTEX_M33_PARTNO, .name = "Cortex-M33", .arch = ARM_ARCH_V8M, .flags = CORTEX_M_F_HAS_FPV5, }, { - .partno = CORTEX_M35P_PARTNO, + .impl_part = CORTEX_M35P_PARTNO, .name = "Cortex-M35P", .arch = ARM_ARCH_V8M, .flags = CORTEX_M_F_HAS_FPV5, }, { - .partno = CORTEX_M55_PARTNO, + .impl_part = CORTEX_M52_PARTNO, + .name = "Cortex-M52", + .arch = ARM_ARCH_V8M, + .flags = CORTEX_M_F_HAS_FPV5, + }, + { + .impl_part = CORTEX_M55_PARTNO, .name = "Cortex-M55", .arch = ARM_ARCH_V8M, .flags = CORTEX_M_F_HAS_FPV5, }, + { + .impl_part = CORTEX_M85_PARTNO, + .name = "Cortex-M85", + .arch = ARM_ARCH_V8M, + .flags = CORTEX_M_F_HAS_FPV5, + }, + { + .impl_part = STAR_MC1_PARTNO, + .name = "STAR-MC1", + .arch = ARM_ARCH_V8M, + .flags = CORTEX_M_F_HAS_FPV5, + }, + { + .impl_part = INFINEON_SLX2_PARTNO, + .name = "Infineon-SLx2", + .arch = ARM_ARCH_V8M, + }, + { + .impl_part = REALTEK_M200_PARTNO, + .name = "Real-M200 (KM0)", + .arch = ARM_ARCH_V8M, + }, + { + .impl_part = REALTEK_M300_PARTNO, + .name = "Real-M300 (KM4)", + .arch = ARM_ARCH_V8M, + .flags = CORTEX_M_F_HAS_FPV5, + }, }; /* forward declarations */ @@ -243,7 +279,8 @@ static int cortex_m_fast_read_all_regs(struct target *target) /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ - if (target->dbg_msg_enabled) { + bool dbg_msg_enabled = target->dbg_msg_enabled; + if (dbg_msg_enabled) { retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr); if (retval != ERROR_OK) return retval; @@ -296,7 +333,7 @@ static int cortex_m_fast_read_all_regs(struct target *target) if (retval != ERROR_OK) return retval; - if (target->dbg_msg_enabled) { + if (dbg_msg_enabled) { /* restore DCB_DCRDR - this needs to be in a separate * transaction otherwise the emulated DCC channel breaks */ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr); @@ -652,6 +689,11 @@ static int cortex_m_endreset_event(struct target *target) register_cache_invalidate(armv7m->arm.core_cache); + /* TODO: invalidate also working areas (needed in the case of detected reset). + * Doing so will require flash drivers to test if working area + * is still valid in all target algo calling loops. + */ + /* make sure we have latest dhcsr flags */ retval = cortex_m_read_dhcsr_atomic_sticky(target); if (retval != ERROR_OK) @@ -762,9 +804,45 @@ static int cortex_m_examine_exception_reason(struct target *target) return retval; } +/* Errata 3092511 workaround + * Cortex-M7 can halt in an incorrect address when breakpoint + * and exception occurs simultaneously */ +static int cortex_m_erratum_check_breakpoint(struct target *target) +{ + struct cortex_m_common *cortex_m = target_to_cm(target); + struct armv7m_common *armv7m = &cortex_m->armv7m; + struct arm *arm = &armv7m->arm; + + uint32_t pc = buf_get_u32(arm->pc->value, 0, 32); + + /* To reduce the workaround processing cost we assume FPB is in sync + * with OpenOCD breakpoints. If the target app writes to FPB + * OpenOCD will resume after the break set by app */ + struct breakpoint *bkpt = breakpoint_find(target, pc); + if (bkpt) { + LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint confirmed"); + return ERROR_OK; + } + if (pc >= 0xe0000000u) + /* not executable area, do not read instruction @ pc */ + return ERROR_OK; + + uint16_t insn; + int retval = target_read_u16(target, pc, &insn); + if (retval != ERROR_OK) + return ERROR_OK; /* do not propagate the error, just avoid workaround */ + + if ((insn & 0xff00) == (ARMV5_T_BKPT(0) & 0xff00)) { + LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint embedded in code confirmed"); + return ERROR_OK; + } + LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint not found, proceed with resume"); + return ERROR_TARGET_HALTED_DO_RESUME; +} + static int cortex_m_debug_entry(struct target *target) { - uint32_t xPSR; + uint32_t xpsr; int retval; struct cortex_m_common *cortex_m = target_to_cm(target); struct armv7m_common *armv7m = &cortex_m->armv7m; @@ -788,15 +866,11 @@ static int cortex_m_debug_entry(struct target *target) return retval; /* examine PE security state */ - bool secure_state = false; + uint32_t dscsr = 0; if (armv7m->arm.arch == ARM_ARCH_V8M) { - uint32_t dscsr; - retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr); if (retval != ERROR_OK) return retval; - - secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS; } /* Load all registers to arm.core_cache */ @@ -815,16 +889,16 @@ static int cortex_m_debug_entry(struct target *target) return retval; r = arm->cpsr; - xPSR = buf_get_u32(r->value, 0, 32); + xpsr = buf_get_u32(r->value, 0, 32); /* Are we in an exception handler */ - if (xPSR & 0x1FF) { - armv7m->exception_number = (xPSR & 0x1FF); + if (xpsr & 0x1FF) { + armv7m->exception_number = (xpsr & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { - unsigned control = buf_get_u32(arm->core_cache + unsigned int control = buf_get_u32(arm->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 3); /* is this thread privileged? */ @@ -844,6 +918,7 @@ static int cortex_m_debug_entry(struct target *target) if (armv7m->exception_number) cortex_m_examine_exception_reason(target); + bool secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS; LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s", arm_mode_name(arm->core_mode), @@ -851,6 +926,17 @@ static int cortex_m_debug_entry(struct target *target) secure_state ? "Secure" : "Non-Secure", target_state_name(target)); + /* Errata 3092511 workaround + * Cortex-M7 can halt in an incorrect address when breakpoint + * and exception occurs simultaneously */ + if (cortex_m->incorrect_halt_erratum + && armv7m->exception_number + && cortex_m->nvic_dfsr == (DFSR_BKPT | DFSR_HALTED)) { + retval = cortex_m_erratum_check_breakpoint(target); + if (retval != ERROR_OK) + return retval; + } + if (armv7m->post_debug_entry) { retval = armv7m->post_debug_entry(target); if (retval != ERROR_OK) @@ -860,7 +946,7 @@ static int cortex_m_debug_entry(struct target *target) return ERROR_OK; } -static int cortex_m_poll(struct target *target) +static int cortex_m_poll_one(struct target *target) { int detected_failure = ERROR_OK; int retval = ERROR_OK; @@ -899,8 +985,24 @@ static int cortex_m_poll(struct target *target) if (target->state != TARGET_RESET) { target->state = TARGET_RESET; LOG_TARGET_INFO(target, "external reset detected"); + /* In case of an unexpected S_RESET_ST set TARGET_RESET state + * and keep it until the next poll to allow its detection */ + return ERROR_OK; } - return ERROR_OK; + + /* refresh status bits */ + retval = cortex_m_read_dhcsr_atomic_sticky(target); + if (retval != ERROR_OK) + return retval; + + /* If still under reset, quit and re-check at next poll */ + if (cortex_m->dcb_dhcsr_cumulated_sticky & S_RESET_ST) { + cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST; + return ERROR_OK; + } + + /* S_RESET_ST was expected (in a reset command). Continue processing + * to quickly get out of TARGET_RESET state */ } if (target->state == TARGET_RESET) { @@ -923,21 +1025,48 @@ static int cortex_m_poll(struct target *target) if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) { retval = cortex_m_debug_entry(target); - if (retval != ERROR_OK) - return retval; - if (arm_semihosting(target, &retval) != 0) + /* Errata 3092511 workaround + * Cortex-M7 can halt in an incorrect address when breakpoint + * and exception occurs simultaneously */ + if (retval == ERROR_TARGET_HALTED_DO_RESUME) { + struct arm *arm = &armv7m->arm; + LOG_TARGET_INFO(target, "Resuming after incorrect halt @ PC 0x%08" PRIx32 + ", ARM Cortex-M7 erratum 3092511", + buf_get_u32(arm->pc->value, 0, 32)); + /* We don't need to restore registers, just restart the core */ + cortex_m_set_maskints_for_run(target); + retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT); + if (retval != ERROR_OK) + return retval; + + target->debug_reason = DBG_REASON_NOTHALTED; + /* registers are now invalid */ + register_cache_invalidate(armv7m->arm.core_cache); + + target->state = TARGET_RUNNING; + return ERROR_OK; + } + + /* arm_semihosting needs to know registers, don't run if debug entry returned error */ + if (retval == ERROR_OK && arm_semihosting(target, &retval) != 0) return retval; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (target->smp) { + LOG_TARGET_DEBUG(target, "postpone target event 'halted'"); + target->smp_halt_event_postponed = true; + } else { + /* regardless of errors returned in previous code update state */ + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } } if (prev_target_state == TARGET_DEBUG_RUNNING) { retval = cortex_m_debug_entry(target); - if (retval != ERROR_OK) - return retval; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } + if (retval != ERROR_OK) + return retval; } if (target->state == TARGET_UNKNOWN) { @@ -970,10 +1099,113 @@ static int cortex_m_poll(struct target *target) return retval; } -static int cortex_m_halt(struct target *target) +static int cortex_m_halt_one(struct target *target); + +static int cortex_m_smp_halt_all(struct list_head *smp_targets) { + int retval = ERROR_OK; + struct target_list *head; + + foreach_smp_target(head, smp_targets) { + struct target *curr = head->target; + if (!target_was_examined(curr)) + continue; + if (curr->state == TARGET_HALTED) + continue; + + int ret2 = cortex_m_halt_one(curr); + if (retval == ERROR_OK) + retval = ret2; /* store the first error code ignore others */ + } + return retval; +} + +static int cortex_m_smp_post_halt_poll(struct list_head *smp_targets) +{ + int retval = ERROR_OK; + struct target_list *head; + + foreach_smp_target(head, smp_targets) { + struct target *curr = head->target; + if (!target_was_examined(curr)) + continue; + /* skip targets that were already halted */ + if (curr->state == TARGET_HALTED) + continue; + + int ret2 = cortex_m_poll_one(curr); + if (retval == ERROR_OK) + retval = ret2; /* store the first error code ignore others */ + } + return retval; +} + +static int cortex_m_poll_smp(struct list_head *smp_targets) +{ + int retval = ERROR_OK; + struct target_list *head; + bool halted = false; + + foreach_smp_target(head, smp_targets) { + struct target *curr = head->target; + if (curr->smp_halt_event_postponed) { + halted = true; + break; + } + } + + if (halted) { + retval = cortex_m_smp_halt_all(smp_targets); + + int ret2 = cortex_m_smp_post_halt_poll(smp_targets); + if (retval == ERROR_OK) + retval = ret2; /* store the first error code ignore others */ + + foreach_smp_target(head, smp_targets) { + struct target *curr = head->target; + if (!curr->smp_halt_event_postponed) + continue; + + curr->smp_halt_event_postponed = false; + if (curr->state == TARGET_HALTED) { + LOG_TARGET_DEBUG(curr, "sending postponed target event 'halted'"); + target_call_event_callbacks(curr, TARGET_EVENT_HALTED); + } + } + /* There is no need to set gdb_service->target + * as hwthread_update_threads() selects an interesting thread + * by its own + */ + } + return retval; +} + +static int cortex_m_poll(struct target *target) +{ + int retval = cortex_m_poll_one(target); + + if (target->smp) { + struct target_list *last; + last = list_last_entry(target->smp_targets, struct target_list, lh); + if (target == last->target) + /* After the last target in SMP group has been polled + * check for postponed halted events and eventually halt and re-poll + * other targets */ + cortex_m_poll_smp(target->smp_targets); + } + return retval; +} + +static int cortex_m_halt_one(struct target *target) +{ + int retval; LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target)); + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "target non examined yet"); + return ERROR_TARGET_NOT_EXAMINED; + } + if (target->state == TARGET_HALTED) { LOG_TARGET_DEBUG(target, "target was already halted"); return ERROR_OK; @@ -982,22 +1214,8 @@ static int cortex_m_halt(struct target *target) if (target->state == TARGET_UNKNOWN) LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested"); - if (target->state == TARGET_RESET) { - if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { - LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST"); - return ERROR_TARGET_FAILURE; - } else { - /* we came here in a reset_halt or reset_init sequence - * debug entry was already prepared in cortex_m3_assert_reset() - */ - target->debug_reason = DBG_REASON_DBGRQ; - - return ERROR_OK; - } - } - /* Write to Debug Halting Control and Status Register */ - cortex_m_write_debug_halt_mask(target, C_HALT, 0); + retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0); /* Do this really early to minimize the window where the MASKINTS erratum * can pile up pending interrupts. */ @@ -1005,7 +1223,15 @@ static int cortex_m_halt(struct target *target) target->debug_reason = DBG_REASON_DBGRQ; - return ERROR_OK; + return retval; +} + +static int cortex_m_halt(struct target *target) +{ + if (target->smp) + return cortex_m_smp_halt_all(target->smp_targets); + else + return cortex_m_halt_one(target); } static int cortex_m_soft_reset_halt(struct target *target) @@ -1085,8 +1311,8 @@ void cortex_m_enable_breakpoints(struct target *target) } } -static int cortex_m_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int cortex_m_restore_one(struct target *target, bool current, + target_addr_t *address, bool handle_breakpoints, bool debug_execution) { struct armv7m_common *armv7m = target_to_armv7m(target); struct breakpoint *breakpoint = NULL; @@ -1094,7 +1320,7 @@ static int cortex_m_resume(struct target *target, int current, struct reg *r; if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1133,10 +1359,10 @@ static int cortex_m_resume(struct target *target, int current, r->valid = true; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ r = armv7m->arm.pc; if (!current) { - buf_set_u32(r->value, 0, 32, address); + buf_set_u32(r->value, 0, 32, *address); r->dirty = true; r->valid = true; } @@ -1150,8 +1376,12 @@ static int cortex_m_resume(struct target *target, int current, armv7m_maybe_skip_bkpt_inst(target, NULL); resume_pc = buf_get_u32(r->value, 0, 32); + if (current) + *address = resume_pc; - armv7m_restore_context(target); + int retval = armv7m_restore_context(target); + if (retval != ERROR_OK) + return retval; /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { @@ -1161,37 +1391,103 @@ static int cortex_m_resume(struct target *target, int current, LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")", breakpoint->address, breakpoint->unique_id); - cortex_m_unset_breakpoint(target, breakpoint); - cortex_m_single_step_core(target); - cortex_m_set_breakpoint(target, breakpoint); + retval = cortex_m_unset_breakpoint(target, breakpoint); + if (retval == ERROR_OK) + retval = cortex_m_single_step_core(target); + int ret2 = cortex_m_set_breakpoint(target, breakpoint); + if (retval != ERROR_OK) + return retval; + if (ret2 != ERROR_OK) + return ret2; } } + return ERROR_OK; +} + +static int cortex_m_restart_one(struct target *target, bool debug_execution) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + /* Restart core */ cortex_m_set_maskints_for_run(target); cortex_m_write_debug_halt_mask(target, 0, C_HALT); target->debug_reason = DBG_REASON_NOTHALTED; - /* registers are now invalid */ register_cache_invalidate(armv7m->arm.core_cache); if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_TARGET_DEBUG(target, "target resumed at 0x%" PRIx32 "", resume_pc); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_TARGET_DEBUG(target, "target debug resumed at 0x%" PRIx32 "", resume_pc); } return ERROR_OK; } +static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints) +{ + struct target_list *head; + target_addr_t address; + foreach_smp_target(head, target->smp_targets) { + struct target *curr = head->target; + /* skip calling target */ + if (curr == target) + continue; + if (!target_was_examined(curr)) + continue; + /* skip running targets */ + if (curr->state == TARGET_RUNNING) + continue; + + int retval = cortex_m_restore_one(curr, true, &address, + handle_breakpoints, false); + if (retval != ERROR_OK) + return retval; + + retval = cortex_m_restart_one(curr, false); + if (retval != ERROR_OK) + return retval; + + LOG_TARGET_DEBUG(curr, "SMP resumed at " TARGET_ADDR_FMT, address); + } + return ERROR_OK; +} + +static int cortex_m_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) +{ + int retval = cortex_m_restore_one(target, current, &address, + handle_breakpoints, debug_execution); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "context restore failed, aborting resume"); + return retval; + } + + if (target->smp && !debug_execution) { + retval = cortex_m_restore_smp(target, handle_breakpoints); + if (retval != ERROR_OK) + LOG_TARGET_WARNING(target, "resume of a SMP target failed, trying to resume current one"); + } + + cortex_m_restart_one(target, debug_execution); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "resume failed"); + return retval; + } + + LOG_TARGET_DEBUG(target, "%sresumed at " TARGET_ADDR_FMT, + debug_execution ? "debug " : "", address); + + return ERROR_OK; +} + /* int irqstepcount = 0; */ -static int cortex_m_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int cortex_m_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { struct cortex_m_common *cortex_m = target_to_cm(target); struct armv7m_common *armv7m = &cortex_m->armv7m; @@ -1202,11 +1498,16 @@ static int cortex_m_step(struct target *target, int current, bool isr_timed_out = false; if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* Just one of SMP cores will step. Set the gdb control + * target to current one or gdb miss gdb-end event */ + if (target->smp && target->gdb_service) + target->gdb_service->target = target; + + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { buf_set_u32(pc->value, 0, 32, address); pc->dirty = true; @@ -1233,7 +1534,7 @@ static int cortex_m_step(struct target *target, int current, /* if no bkpt instruction is found at pc then we can perform * a normal step, otherwise we have to manually step over the bkpt * instruction - as such simulate a step */ - if (bkpt_inst_found == false) { + if (!bkpt_inst_found) { if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) { /* Automatic ISR masking mode off: Just step over the next * instruction, with interrupts on or off as appropriate. */ @@ -1370,7 +1671,7 @@ static int cortex_m_step(struct target *target, int current, cortex_m->dcb_dhcsr, cortex_m->nvic_icsr); retval = cortex_m_debug_entry(target); - if (retval != ERROR_OK) + if (retval != ERROR_OK && retval != ERROR_TARGET_HALTED_DO_RESUME) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1387,8 +1688,9 @@ static int cortex_m_assert_reset(struct target *target) struct armv7m_common *armv7m = &cortex_m->armv7m; enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config; - LOG_TARGET_DEBUG(target, "target->state: %s", - target_state_name(target)); + LOG_TARGET_DEBUG(target, "target->state: %s,%s examined", + target_state_name(target), + target_was_examined(target) ? "" : " not"); enum reset_types jtag_reset_config = jtag_get_reset_config(); @@ -1403,28 +1705,45 @@ static int cortex_m_assert_reset(struct target *target) } /* some cores support connecting while srst is asserted - * use that mode is it has been configured */ + * use that mode if it has been configured */ bool srst_asserted = false; - if (!target_was_examined(target)) { - if (jtag_reset_config & RESET_HAS_SRST) { - adapter_assert_reset(); + if ((jtag_reset_config & RESET_HAS_SRST) && + ((jtag_reset_config & RESET_SRST_NO_GATING) + || (!armv7m->debug_ap && !target->defer_examine))) { + /* If we have no debug_ap, asserting SRST is the only thing + * we can do now */ + adapter_assert_reset(); + srst_asserted = true; + } + + /* TODO: replace the hack calling target_examine_one() + * as soon as a better reset framework is available */ + if (!target_was_examined(target) && !target->defer_examine + && srst_asserted && (jtag_reset_config & RESET_SRST_NO_GATING)) { + LOG_TARGET_DEBUG(target, "Trying to re-examine under reset"); + target_examine_one(target); + } + + /* We need at least debug_ap to go further. + * Inform user and bail out if we don't have one. */ + if (!armv7m->debug_ap) { + if (srst_asserted) { if (target->reset_halt) - LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!"); + LOG_TARGET_ERROR(target, "Debug AP not available, will not halt after reset!"); + + /* Do not propagate error: reset was asserted, proceed to deassert! */ + target->state = TARGET_RESET; + register_cache_invalidate(cortex_m->armv7m.arm.core_cache); return ERROR_OK; + } else { - LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!"); + LOG_TARGET_ERROR(target, "Debug AP not available, reset NOT asserted!"); return ERROR_FAIL; } } - if ((jtag_reset_config & RESET_HAS_SRST) && - (jtag_reset_config & RESET_SRST_NO_GATING)) { - adapter_assert_reset(); - srst_asserted = true; - } - /* Enable debug requests */ int retval = cortex_m_read_dhcsr_atomic_sticky(target); @@ -1460,6 +1779,7 @@ static int cortex_m_assert_reset(struct target *target) int retval2; retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + target->debug_reason = DBG_REASON_DBGRQ; if (retval != ERROR_OK || retval2 != ERROR_OK) LOG_TARGET_INFO(target, "AP write error, reset will not halt"); } @@ -1472,9 +1792,8 @@ static int cortex_m_assert_reset(struct target *target) /* srst is asserted, ignore AP access errors */ retval = ERROR_OK; } else { - /* Use a standard Cortex-M3 software reset mechanism. - * We default to using VECTRESET as it is supported on all current cores - * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!) + /* Use a standard Cortex-M software reset mechanism. + * We default to using VECTRESET. * This has the disadvantage of not resetting the peripherals, so a * reset-init event handler is needed to perform any peripheral resets. */ @@ -1521,34 +1840,27 @@ static int cortex_m_assert_reset(struct target *target) register_cache_invalidate(cortex_m->armv7m.arm.core_cache); - /* now return stored error code if any */ - if (retval != ERROR_OK) - return retval; - - if (target->reset_halt) { - retval = target_halt(target); - if (retval != ERROR_OK) - return retval; - } - - return ERROR_OK; + return retval; } static int cortex_m_deassert_reset(struct target *target) { struct armv7m_common *armv7m = &target_to_cm(target)->armv7m; - LOG_TARGET_DEBUG(target, "target->state: %s", - target_state_name(target)); + LOG_TARGET_DEBUG(target, "target->state: %s,%s examined", + target_state_name(target), + target_was_examined(target) ? "" : " not"); + + enum reset_types jtag_reset_config = jtag_get_reset_config(); /* deassert reset lines */ - adapter_deassert_reset(); + if (jtag_reset_config & RESET_HAS_SRST) + adapter_deassert_reset(); - enum reset_types jtag_reset_config = jtag_get_reset_config(); if ((jtag_reset_config & RESET_HAS_SRST) && - !(jtag_reset_config & RESET_SRST_NO_GATING) && - target_was_examined(target)) { + !(jtag_reset_config & RESET_SRST_NO_GATING) && + armv7m->debug_ap) { int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap); if (retval != ERROR_OK) { @@ -1736,7 +2048,8 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat target_write_u32(target, comparator->dwt_comparator_address + 0, comparator->comp); - if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) { + if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M_V2_0 + && (cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M_V2_1) { uint32_t mask = 0, temp; /* watchpoint params were validated earlier */ @@ -1784,11 +2097,9 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat target_write_u32(target, comparator->dwt_comparator_address + 8, comparator->function); - LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", + LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08" PRIx32 " 0x%" PRIx32 " 0x%05" PRIx32, watchpoint->unique_id, dwt_num, - (unsigned) comparator->comp, - (unsigned) comparator->mask, - (unsigned) comparator->function); + comparator->comp, comparator->mask, comparator->function); return ERROR_OK; } @@ -1805,9 +2116,9 @@ static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *w unsigned int dwt_num = watchpoint->number; - LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: 0x%08x clear", + LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: " TARGET_ADDR_FMT " clear", watchpoint->unique_id, dwt_num, - (unsigned) watchpoint->address); + watchpoint->address); if (dwt_num >= cortex_m->dwt_num_comp) { LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint"); @@ -1834,14 +2145,20 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - /* hardware doesn't support data value masking */ - if (watchpoint->mask != ~(uint32_t)0) { + /* REVISIT This DWT may well be able to watch for specific data + * values. Requires comparator #1 to set DATAVMATCH and match + * the data, and another comparator (DATAVADDR0) matching addr. + * + * NOTE: hardware doesn't support data value masking, so we'll need + * to check that mask is zero + */ + if (watchpoint->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) { LOG_TARGET_DEBUG(target, "watchpoint value masks not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* hardware allows address masks of up to 32K */ - unsigned mask; + unsigned int mask; for (mask = 0; mask < 16; mask++) { if ((1u << mask) == watchpoint->length) @@ -1856,18 +2173,6 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - /* Caller doesn't seem to be able to describe watching for data - * values of zero; that flags "no value". - * - * REVISIT This DWT may well be able to watch for specific data - * values. Requires comparator #1 to set DATAVMATCH and match - * the data, and another comparator (DATAVADDR0) matching addr. - */ - if (watchpoint->value) { - LOG_TARGET_DEBUG(target, "data value watchpoint not YET supported"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - cortex_m->dwt_comp_available--; LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available); @@ -1880,7 +2185,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1893,7 +2198,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo return ERROR_OK; } -int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) +static int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) { if (target->debug_reason != DBG_REASON_WATCHPOINT) return ERROR_FAIL; @@ -2013,7 +2318,7 @@ int cortex_m_profiling(struct target *target, uint32_t *samples, /* Make sure the target is running */ target_poll(target); if (target->state == TARGET_HALTED) - retval = target_resume(target, 1, 0, 0, 0); + retval = target_resume(target, true, 0, false, false); if (retval != ERROR_OK) { LOG_TARGET_ERROR(target, "Error while resuming target"); @@ -2089,7 +2394,7 @@ static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf) struct dwt_reg { uint32_t addr; const char *name; - unsigned size; + unsigned int size; }; static const struct dwt_reg dwt_base_regs[] = { @@ -2145,6 +2450,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dw r->value = state->value; r->arch_info = state; r->type = &dwt_reg_type; + r->exist = true; } static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target) @@ -2241,16 +2547,139 @@ static void cortex_m_dwt_free(struct target *target) cm->dwt_cache = NULL; } -#define MVFR0 0xe000ef40 -#define MVFR1 0xe000ef44 +static bool cortex_m_has_tz(struct target *target) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + uint32_t dauthstatus; + + if (armv7m->arm.arch != ARM_ARCH_V8M) + return false; -#define MVFR0_DEFAULT_M4 0x10110021 -#define MVFR1_DEFAULT_M4 0x11000011 + int retval = target_read_u32(target, DAUTHSTATUS, &dauthstatus); + if (retval != ERROR_OK) { + LOG_TARGET_WARNING(target, "Error reading DAUTHSTATUS register"); + return false; + } + return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0; +} -#define MVFR0_DEFAULT_M7_SP 0x10110021 -#define MVFR0_DEFAULT_M7_DP 0x10110221 -#define MVFR1_DEFAULT_M7_SP 0x11000011 -#define MVFR1_DEFAULT_M7_DP 0x12000011 +int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec) +{ + if (ssec) { + ssec->dscsr_dirty = false; + ssec->sau_ctrl_dirty = false; + ssec->mpu_ctrl_dirty = false; + } + + if (!cortex_m_has_tz(target)) + return ERROR_OK; + + uint32_t dscsr; + int retval = target_read_u32(target, DCB_DSCSR, &dscsr); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR read failed"); + return retval; + } + if (!(dscsr & DSCSR_CDS)) { + if (ssec) { + ssec->dscsr_dirty = true; + ssec->dscsr = dscsr; + } + LOG_TARGET_DEBUG(target, "Setting Current Domain Secure in DSCSR"); + retval = target_write_u32(target, DCB_DSCSR, DSCSR_CDS); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR write failed"); + return retval; + } + } + + uint32_t sau_ctrl; + retval = target_read_u32(target, SAU_CTRL, &sau_ctrl); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: SAU_CTRL read failed"); + return retval; + } + if (sau_ctrl & SAU_CTRL_ENABLE) { + if (ssec) { + ssec->sau_ctrl_dirty = true; + ssec->sau_ctrl = sau_ctrl; + } + retval = target_write_u32(target, SAU_CTRL, sau_ctrl & ~SAU_CTRL_ENABLE); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: SAU_CTRL write failed"); + return retval; + } + } + + uint32_t mpu_ctrl; + retval = target_read_u32(target, MPU_CTRL, &mpu_ctrl); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: MPU_CTRL read failed"); + return retval; + } + if (mpu_ctrl & MPU_CTRL_ENABLE) { + if (ssec) { + ssec->mpu_ctrl_dirty = true; + ssec->mpu_ctrl = mpu_ctrl; + } + retval = target_write_u32(target, MPU_CTRL, mpu_ctrl & ~MPU_CTRL_ENABLE); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: MPU_CTRL write failed"); + return retval; + } + } + return ERROR_OK; +} + +int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec) +{ + int retval; + if (!cortex_m_has_tz(target)) + return ERROR_OK; + + if (!ssec) + return ERROR_OK; + + if (ssec->mpu_ctrl_dirty) { + retval = target_write_u32(target, MPU_CTRL, ssec->mpu_ctrl); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M security restore: MPU_CTRL write failed"); + return retval; + } + ssec->mpu_ctrl_dirty = false; + } + + if (ssec->sau_ctrl_dirty) { + retval = target_write_u32(target, SAU_CTRL, ssec->sau_ctrl); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M security restore: SAU_CTRL write failed"); + return retval; + } + ssec->sau_ctrl_dirty = false; + } + + if (ssec->dscsr_dirty) { + LOG_TARGET_DEBUG(target, "Restoring Current Domain Security in DSCSR"); + retval = target_write_u32(target, DCB_DSCSR, ssec->dscsr & ~DSCSR_CDSKEY); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR write failed"); + return retval; + } + ssec->dscsr_dirty = false; + } + return ERROR_OK; +} + +#define MVFR0 0xE000EF40 +#define MVFR0_SP_MASK 0x000000F0 +#define MVFR0_SP 0x00000020 +#define MVFR0_DP_MASK 0x00000F00 +#define MVFR0_DP 0x00000200 + +#define MVFR1 0xE000EF44 +#define MVFR1_MVE_MASK 0x00000F00 +#define MVFR1_MVE_I 0x00000100 +#define MVFR1_MVE_F 0x00000200 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp, struct adiv5_ap **debug_ap) @@ -2264,7 +2693,7 @@ static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp, int cortex_m_examine(struct target *target) { int retval; - uint32_t cpuid, fpcr, mvfr0, mvfr1; + uint32_t cpuid, fpcr; struct cortex_m_common *cortex_m = target_to_cm(target); struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap; struct armv7m_common *armv7m = target_to_armv7m(target); @@ -2272,23 +2701,20 @@ int cortex_m_examine(struct target *target) /* hla_target shares the examine handler but does not support * all its calls */ if (!armv7m->is_hla_target) { - if (armv7m->debug_ap) { - dap_put_ap(armv7m->debug_ap); - armv7m->debug_ap = NULL; - } - - if (cortex_m->apsel == DP_APSEL_INVALID) { - /* Search for the MEM-AP */ - retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap); - if (retval != ERROR_OK) { - LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core"); - return retval; - } - } else { - armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel); - if (!armv7m->debug_ap) { - LOG_ERROR("Cannot get AP"); - return ERROR_FAIL; + if (!armv7m->debug_ap) { + if (cortex_m->apsel == DP_APSEL_INVALID) { + /* Search for the MEM-AP */ + retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap); + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core"); + return retval; + } + } else { + armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel); + if (!armv7m->debug_ap) { + LOG_TARGET_ERROR(target, "Cannot get AP"); + return ERROR_FAIL; + } } } @@ -2307,18 +2733,18 @@ int cortex_m_examine(struct target *target) if (retval != ERROR_OK) return retval; - /* Get ARCH and CPU types */ - const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS; + /* Inspect implementer/part to look for recognized cores */ + unsigned int impl_part = cpuid & (ARM_CPUID_IMPLEMENTER_MASK | ARM_CPUID_PARTNO_MASK); for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) { - if (core_partno == cortex_m_parts[n].partno) { + if (impl_part == cortex_m_parts[n].impl_part) { cortex_m->core_info = &cortex_m_parts[n]; break; } } if (!cortex_m->core_info) { - LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is unrecognized", core_partno); + LOG_TARGET_ERROR(target, "Cortex-M CPUID: 0x%x is unrecognized", cpuid); return ERROR_FAIL; } @@ -2330,37 +2756,57 @@ int cortex_m_examine(struct target *target) (uint8_t)((cpuid >> 0) & 0xf)); cortex_m->maskints_erratum = false; - if (core_partno == CORTEX_M7_PARTNO) { + cortex_m->incorrect_halt_erratum = false; + if (impl_part == CORTEX_M7_PARTNO) { uint8_t rev, patch; rev = (cpuid >> 20) & 0xf; patch = (cpuid >> 0) & 0xf; if ((rev == 0) && (patch < 2)) { - LOG_TARGET_WARNING(target, "Silicon bug: single stepping may enter pending exception handler!"); + LOG_TARGET_WARNING(target, "Erratum 702596: single stepping may enter pending exception handler!"); cortex_m->maskints_erratum = true; } + /* TODO: add revision check when a Cortex-M7 revision with fixed 3092511 is out */ + LOG_TARGET_WARNING(target, "Erratum 3092511: Cortex-M7 can halt in an incorrect address when breakpoint and exception occurs simultaneously"); + cortex_m->incorrect_halt_erratum = true; + if (armv7m->is_hla_target) + LOG_TARGET_WARNING(target, "No erratum 3092511 workaround on hla adapter"); + else + LOG_TARGET_INFO(target, "The erratum 3092511 workaround will resume after an incorrect halt"); } LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid); if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) { + uint32_t mvfr0; target_read_u32(target, MVFR0, &mvfr0); - target_read_u32(target, MVFR1, &mvfr1); - /* test for floating point feature on Cortex-M4 */ - if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { - LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", cortex_m->core_info->name); + if ((mvfr0 & MVFR0_SP_MASK) == MVFR0_SP) { + LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", + cortex_m->core_info->name); armv7m->fp_feature = FPV4_SP; } } else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) { + uint32_t mvfr0, mvfr1; target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); - /* test for floating point features on Cortex-M7 */ - if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) { - LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", cortex_m->core_info->name); + if ((mvfr0 & MVFR0_DP_MASK) == MVFR0_DP) { + if ((mvfr1 & MVFR1_MVE_MASK) == MVFR1_MVE_F) { + LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP + MVE-F found", + cortex_m->core_info->name); + armv7m->fp_feature = FPV5_MVE_F; + } else { + LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", + cortex_m->core_info->name); + armv7m->fp_feature = FPV5_DP; + } + } else if ((mvfr0 & MVFR0_SP_MASK) == MVFR0_SP) { + LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", + cortex_m->core_info->name); armv7m->fp_feature = FPV5_SP; - } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) { - LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", cortex_m->core_info->name); - armv7m->fp_feature = FPV5_DP; + } else if ((mvfr1 & MVFR1_MVE_MASK) == MVFR1_MVE_I) { + LOG_TARGET_DEBUG(target, "%s floating point feature MVE-I found", + cortex_m->core_info->name); + armv7m->fp_feature = FPV5_MVE_I; } } @@ -2372,7 +2818,11 @@ int cortex_m_examine(struct target *target) for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++) armv7m->arm.core_cache->reg_list[idx].exist = false; - if (armv7m->arm.arch != ARM_ARCH_V8M) + /* TODO: MVE can be present without floating points. Revisit this test */ + if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != FPV5_MVE_I) + armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = false; + + if (!cortex_m_has_tz(target)) for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++) armv7m->arm.core_cache->reg_list[idx].exist = false; @@ -2386,6 +2836,20 @@ int cortex_m_examine(struct target *target) retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; + + /* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR + * as S_RESET_ST may indicate a reset that happened long time ago + * (most probably the power-on reset before OpenOCD was started). + * As we are just initializing the debug system we do not need + * to call cortex_m_endreset_event() in the following poll. + */ + if (!cortex_m->dcb_dhcsr_sticky_is_recent) { + cortex_m->dcb_dhcsr_sticky_is_recent = true; + if (cortex_m->dcb_dhcsr & S_RESET_ST) { + LOG_TARGET_DEBUG(target, "reset happened some time ago, ignore"); + cortex_m->dcb_dhcsr &= ~S_RESET_ST; + } + } cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr); if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) { @@ -2403,8 +2867,8 @@ int cortex_m_examine(struct target *target) if (retval != ERROR_OK) return retval; - if (armv7m->trace_config.itm_deferred_config) - armv7m_trace_itm_config(target); + /* Configure ITM */ + armv7m_trace_itm_config(target); /* NOTE: FPB and DWT are both optional. */ @@ -2538,7 +3002,7 @@ static int cortex_m_init_arch_info(struct target *target, armv7m_init_arch_info(target, armv7m); /* default reset mode is to use srst if fitted - * if not it will use CORTEX_M3_RESET_VECTRESET */ + * if not it will use CORTEX_M_RESET_VECTRESET */ cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET; armv7m->arm.dap = dap; @@ -2559,7 +3023,7 @@ static int cortex_m_init_arch_info(struct target *target, return ERROR_OK; } -static int cortex_m_target_create(struct target *target, Jim_Interp *interp) +static int cortex_m_target_create(struct target *target) { struct adiv5_private_config *pc; @@ -2595,8 +3059,7 @@ static int cortex_m_verify_pointer(struct command_invocation *cmd, /* * Only stuff below this line should need to verify that its target - * is a Cortex-M3. Everything else should have indirected through the - * cortexm3_target structure, which is only used with CM3 targets. + * is a Cortex-M with available DAP access (not a HLA adapter). */ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) @@ -2609,7 +3072,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) static const struct { char name[10]; - unsigned mask; + unsigned int mask; } vec_ids[] = { { "hard_err", VC_HARDERR, }, { "int_err", VC_INTERR, }, @@ -2635,7 +3098,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) return retval; if (CMD_ARGC > 0) { - unsigned catch = 0; + unsigned int catch = 0; if (CMD_ARGC == 1) { if (strcmp(CMD_ARGV[0], "all") == 0) { @@ -2647,7 +3110,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) goto write; } while (CMD_ARGC-- > 0) { - unsigned i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0) continue; @@ -2655,7 +3118,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) break; } if (i == ARRAY_SIZE(vec_ids)) { - LOG_TARGET_ERROR(target, "No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]); + LOG_TARGET_ERROR(target, "No Cortex-M vector '%s'", CMD_ARGV[CMD_ARGC]); return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -2680,7 +3143,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) */ } - for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(vec_ids); i++) { command_print(CMD, "%9s: %s", vec_ids[i].name, (demcr & vec_ids[i].mask) ? "catch" : "ignore"); } @@ -2694,14 +3157,14 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command) struct cortex_m_common *cortex_m = target_to_cm(target); int retval; - static const struct jim_nvp nvp_maskisr_modes[] = { + static const struct nvp nvp_maskisr_modes[] = { { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO }, { .name = "off", .value = CORTEX_M_ISRMASK_OFF }, { .name = "on", .value = CORTEX_M_ISRMASK_ON }, { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY }, { .name = NULL, .value = -1 }, }; - const struct jim_nvp *n; + const struct nvp *n; retval = cortex_m_verify_pointer(CMD, cortex_m); @@ -2709,19 +3172,19 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } if (CMD_ARGC > 0) { - n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]); if (!n->name) return ERROR_COMMAND_SYNTAX_ERROR; cortex_m->isrmasking_mode = n->value; cortex_m_set_maskints_for_halt(target); } - n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode); + n = nvp_value2name(nvp_maskisr_modes, cortex_m->isrmasking_mode); command_print(CMD, "cortex_m interrupt mask %s", n->name); return ERROR_OK; @@ -2794,6 +3257,9 @@ static const struct command_registration cortex_m_exec_command_handlers[] = { .help = "configure software reset handling", .usage = "['sysresetreq'|'vectreset']", }, + { + .chain = smp_command_handlers, + }, COMMAND_REGISTRATION_DONE }; static const struct command_registration cortex_m_command_handlers[] = { diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 3f0d55c1c2..82b2c1ecde 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -17,7 +17,7 @@ #include "armv7m.h" #include "helper/bits.h" -#define CORTEX_M_COMMON_MAGIC 0x1A451A45 +#define CORTEX_M_COMMON_MAGIC 0x1A451A45U #define SYSTEM_CONTROL_BASE 0x400FE000 @@ -31,21 +31,36 @@ #define CPUID 0xE000ED00 -#define ARM_CPUID_PARTNO_POS 4 -#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS) +#define ARM_CPUID_IMPLEMENTER_POS 24 +#define ARM_CPUID_IMPLEMENTER_MASK (0xFF << ARM_CPUID_IMPLEMENTER_POS) +#define ARM_CPUID_PARTNO_POS 4 +#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS) -enum cortex_m_partno { +#define ARM_MAKE_CPUID(impl, partno) ((((impl) << ARM_CPUID_IMPLEMENTER_POS) & ARM_CPUID_IMPLEMENTER_MASK) | \ + (((partno) << ARM_CPUID_PARTNO_POS) & ARM_CPUID_PARTNO_MASK)) + +/** Known Arm Cortex masked CPU Ids + * This includes the implementer and part number, but _not_ the revision or + * patch fields. + */ +enum cortex_m_impl_part { CORTEX_M_PARTNO_INVALID, - CORTEX_M0_PARTNO = 0xC20, - CORTEX_M1_PARTNO = 0xC21, - CORTEX_M3_PARTNO = 0xC23, - CORTEX_M4_PARTNO = 0xC24, - CORTEX_M7_PARTNO = 0xC27, - CORTEX_M0P_PARTNO = 0xC60, - CORTEX_M23_PARTNO = 0xD20, - CORTEX_M33_PARTNO = 0xD21, - CORTEX_M35P_PARTNO = 0xD31, - CORTEX_M55_PARTNO = 0xD22, + STAR_MC1_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM_CHINA, 0x132), + CORTEX_M0_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC20), + CORTEX_M1_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC21), + CORTEX_M3_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC23), + CORTEX_M4_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC24), + CORTEX_M7_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC27), + CORTEX_M0P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC60), + CORTEX_M23_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD20), + CORTEX_M33_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD21), + CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD31), + CORTEX_M52_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM_CHINA, 0xD24), + CORTEX_M55_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD22), + CORTEX_M85_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD23), + INFINEON_SLX2_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_INFINEON, 0xDB0), + REALTEK_M200_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_REALTEK, 0xd20), + REALTEK_M300_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_REALTEK, 0xd22), }; /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */ @@ -54,7 +69,7 @@ enum cortex_m_partno { #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2) struct cortex_m_part_info { - enum cortex_m_partno partno; + enum cortex_m_impl_part impl_part; const char *name; enum arm_arch arch; uint32_t flags; @@ -67,6 +82,9 @@ struct cortex_m_part_info { #define DCB_DEMCR 0xE000EDFC #define DCB_DSCSR 0xE000EE08 +#define DAUTHSTATUS 0xE000EFB8 +#define DAUTHSTATUS_SID_MASK 0x00000030 + #define DCRSR_WNR BIT(16) #define DWT_CTRL 0xE0001000 @@ -77,7 +95,8 @@ struct cortex_m_part_info { #define DWT_FUNCTION0 0xE0001028 #define DWT_DEVARCH 0xE0001FBC -#define DWT_DEVARCH_ARMV8M 0x101A02 +#define DWT_DEVARCH_ARMV8M_V2_0 0x101A02 +#define DWT_DEVARCH_ARMV8M_V2_1 0x111A02 #define FP_CTRL 0xE0002000 #define FP_REMAP 0xE0002004 @@ -131,6 +150,7 @@ struct cortex_m_part_info { #define VC_CORERESET BIT(0) /* DCB_DSCSR bit and field definitions */ +#define DSCSR_CDSKEY BIT(17) #define DSCSR_CDS BIT(16) /* NVIC registers */ @@ -147,6 +167,8 @@ struct cortex_m_part_info { #define NVIC_DFSR 0xE000ED30 #define NVIC_MMFAR 0xE000ED34 #define NVIC_BFAR 0xE000ED38 +#define MPU_CTRL 0xE000ED94 +#define SAU_CTRL 0xE000EDD0 #define NVIC_SFSR 0xE000EDE4 #define NVIC_SFAR 0xE000EDE8 @@ -164,6 +186,9 @@ struct cortex_m_part_info { #define DFSR_VCATCH 8 #define DFSR_EXTERNAL 16 +#define MPU_CTRL_ENABLE BIT(0) +#define SAU_CTRL_ENABLE BIT(0) + #define FPCR_CODE 0 #define FPCR_LITERAL 1 #define FPCR_REPLACE_REMAP (0ul << 30) @@ -199,11 +224,15 @@ enum cortex_m_isrmasking_mode { }; struct cortex_m_common { - int common_magic; + unsigned int common_magic; + + struct armv7m_common armv7m; /* Context information */ uint32_t dcb_dhcsr; uint32_t dcb_dhcsr_cumulated_sticky; + /* DCB DHCSR has been at least once read, so the sticky bits have been reset */ + bool dcb_dhcsr_sticky_is_recent; uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ @@ -226,7 +255,6 @@ struct cortex_m_common { enum cortex_m_isrmasking_mode isrmasking_mode; const struct cortex_m_part_info *core_info; - struct armv7m_common armv7m; bool slow_register_read; /* A register has not been ready, poll S_REGRDY */ @@ -235,6 +263,19 @@ struct cortex_m_common { /* Whether this target has the erratum that makes C_MASKINTS not apply to * already pending interrupts */ bool maskints_erratum; + + /* Errata 3092511 Cortex-M7 can halt in an incorrect address when breakpoint + * and exception occurs simultaneously */ + bool incorrect_halt_erratum; +}; + +struct cortex_m_saved_security { + bool dscsr_dirty; + uint32_t dscsr; + bool sau_ctrl_dirty; + uint32_t sau_ctrl; + bool mpu_ctrl_dirty; + uint32_t mpu_ctrl; }; static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m) @@ -285,11 +326,11 @@ target_to_cortex_m_safe(struct target *target) } /** - * @returns cached value of Cortex-M part number + * @returns cached value of the cpuid, masked for implementation and part. * or CORTEX_M_PARTNO_INVALID if the magic number does not match * or core_info is not initialised. */ -static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target) +static inline enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target) { struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target); if (!cortex_m) @@ -298,7 +339,7 @@ static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *targe if (!cortex_m->core_info) return CORTEX_M_PARTNO_INVALID; - return cortex_m->core_info->partno; + return cortex_m->core_info->impl_part; } int cortex_m_examine(struct target *target); @@ -314,4 +355,17 @@ void cortex_m_deinit_target(struct target *target); int cortex_m_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); +/** + * Forces Cortex-M core to the basic secure context with SAU and MPU off + * @param ssec pointer to save previous security state or NULL + * @returns error code or ERROR_OK if secure mode was set or is not applicable + * (not ARMv8M with security extension) + */ +int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec); + +/** + * Restores saved security context to MPU_CTRL, SAU_CTRL and DSCSR + */ +int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec); + #endif /* OPENOCD_TARGET_CORTEX_M_H */ diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index b572ce56b6..dc85a21800 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009-2011 by Mathias Kuester * @@ -220,9 +220,9 @@ enum dsp563xx_reg_idx { }; static const struct { - unsigned id; + unsigned int id; const char *name; - unsigned bits; + unsigned int bits; /* effective addressing mode encoding */ uint8_t eame; uint32_t instr_mask; @@ -880,7 +880,7 @@ static void dsp563xx_invalidate_x_context(struct target *target, } } -static int dsp563xx_target_create(struct target *target, Jim_Interp *interp) +static int dsp563xx_target_create(struct target *target) { struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common)); @@ -912,7 +912,7 @@ static int dsp563xx_examine(struct target *target) { uint32_t chip; - if (target->tap->hasidcode == false) { + if (!target->tap->has_idcode) { LOG_ERROR("no IDCODE present on device"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1115,10 +1115,10 @@ static int dsp563xx_halt(struct target *target) } static int dsp563xx_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, + bool debug_execution) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); @@ -1132,10 +1132,10 @@ static int dsp563xx_resume(struct target *target, if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) { dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC); address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; - current = 0; + current = false; } - LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address); + LOG_DEBUG("%s %08X %08" TARGET_PRIXADDR, __func__, current, address); err = dsp563xx_restore_context(target); if (err != ERROR_OK) @@ -1172,9 +1172,9 @@ static int dsp563xx_resume(struct target *target, } static int dsp563xx_step_ex(struct target *target, - int current, + bool current, uint32_t address, - int handle_breakpoints, + bool handle_breakpoints, int steps) { int err; @@ -1196,10 +1196,10 @@ static int dsp563xx_step_ex(struct target *target, if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) { dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC); address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; - current = 0; + current = false; } - LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address); + LOG_DEBUG("%s %08X %08" PRIX32, __func__, current, address); err = dsp563xx_jtag_debug_request(target); if (err != ERROR_OK) @@ -1260,15 +1260,15 @@ static int dsp563xx_step_ex(struct target *target, err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in); if (err != ERROR_OK) return err; - LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff); + LOG_DEBUG("fetch: %08" PRIX32, dr_in & 0x00ffffff); err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in); if (err != ERROR_OK) return err; - LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff); + LOG_DEBUG("decode: %08" PRIX32, dr_in & 0x00ffffff); err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in); if (err != ERROR_OK) return err; - LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff); + LOG_DEBUG("execute: %08" PRIX32, dr_in & 0x00ffffff); /* reset trace mode */ err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000); @@ -1288,15 +1288,15 @@ static int dsp563xx_step_ex(struct target *target, } static int dsp563xx_step(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints) + bool handle_breakpoints) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1359,7 +1359,7 @@ static int dsp563xx_deassert_reset(struct target *target) * reset vector and need 2 cycles to fill * the cache (fetch,decode,execute) */ - err = dsp563xx_step_ex(target, 1, 0, 1, 1); + err = dsp563xx_step_ex(target, true, 0, true, 1); if (err != ERROR_OK) return err; } @@ -1374,14 +1374,14 @@ static int dsp563xx_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info) + unsigned int timeout_ms, void *arch_info) { int i; int retval = ERROR_OK; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (run target algo)"); return ERROR_TARGET_NOT_HALTED; } @@ -1419,7 +1419,7 @@ static int dsp563xx_run_algorithm(struct target *target, } /* exec */ - retval = target_resume(target, 0, entry_point, 1, 1); + retval = target_resume(target, false, entry_point, true, true); if (retval != ERROR_OK) return retval; @@ -1705,7 +1705,7 @@ static int dsp563xx_write_memory_core(struct target *target, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1972,7 +1972,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres if (err == ERROR_OK && was_running) { /* Resume from current PC */ - err = dsp563xx_resume(target, 1, 0x0, 0, 0); + err = dsp563xx_resume(target, true, 0x0, false, false); } return err; @@ -2140,7 +2140,7 @@ COMMAND_HANDLER(dsp563xx_mem_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count); } - buffer = calloc(count, sizeof(uint32_t)); + buffer = calloc(count, 4); if (read_mem == 1) { err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t), diff --git a/src/target/dsp563xx_once.c b/src/target/dsp563xx_once.c index b1955827d8..bb41ae8c7c 100644 --- a/src/target/dsp563xx_once.c +++ b/src/target/dsp563xx_once.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Mathias Kuester * @@ -34,6 +34,8 @@ #define JTAG_INSTR_DEBUG_REQUEST 0x07 #define JTAG_INSTR_BYPASS 0x0F +static int dsp563xx_once_reg_read_ex(struct jtag_tap *tap, int flush, uint8_t reg, uint8_t len, uint32_t *data); + /** */ static inline int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len, int rti) { @@ -60,7 +62,7 @@ static inline int dsp563xx_once_ir_exec(struct jtag_tap *tap, int flush, uint8_t { int err; - err = dsp563xx_write_dr_u8(tap, 0, instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0); + err = dsp563xx_write_dr_u8(tap, NULL, instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0); if (err != ERROR_OK) return err; if (flush) @@ -185,7 +187,7 @@ int dsp563xx_once_read_register(struct jtag_tap *tap, int flush, struct once_reg } /** once read register with register len */ -int dsp563xx_once_reg_read_ex(struct jtag_tap *tap, int flush, uint8_t reg, uint8_t len, uint32_t *data) +static int dsp563xx_once_reg_read_ex(struct jtag_tap *tap, int flush, uint8_t reg, uint8_t len, uint32_t *data) { int err; @@ -226,7 +228,7 @@ int dsp563xx_once_reg_write(struct jtag_tap *tap, int flush, uint8_t reg, uint32 err = dsp563xx_once_ir_exec(tap, flush, reg, 0, 0, 0); if (err != ERROR_OK) return err; - err = dsp563xx_write_dr_u32(tap, 0x00, data, 24, 0); + err = dsp563xx_write_dr_u32(tap, NULL, data, 24, 0); if (err != ERROR_OK) return err; if (flush) @@ -242,7 +244,7 @@ int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, int flush, uint32_t opcode err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0); if (err != ERROR_OK) return err; - err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + err = dsp563xx_write_dr_u32(tap, NULL, opcode, 24, 0); if (err != ERROR_OK) return err; if (flush) @@ -258,7 +260,7 @@ int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, int flush, uint32_t opcode err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 0, 0); if (err != ERROR_OK) return err; - err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + err = dsp563xx_write_dr_u32(tap, NULL, opcode, 24, 0); if (err != ERROR_OK) return err; if (flush) { @@ -270,7 +272,7 @@ int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, int flush, uint32_t opcode err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0); if (err != ERROR_OK) return err; - err = dsp563xx_write_dr_u32(tap, 0, operand, 24, 0); + err = dsp563xx_write_dr_u32(tap, NULL, operand, 24, 0); if (err != ERROR_OK) return err; if (flush) { diff --git a/src/target/dsp563xx_once.h b/src/target/dsp563xx_once.h index 8715488374..4f27e1db78 100644 --- a/src/target/dsp563xx_once.h +++ b/src/target/dsp563xx_once.h @@ -65,8 +65,6 @@ int dsp563xx_once_target_status(struct jtag_tap *tap); /** once read registers */ int dsp563xx_once_read_register(struct jtag_tap *tap, int flush, struct once_reg *regs, int len); /** once read register */ -int dsp563xx_once_reg_read_ex(struct jtag_tap *tap, int flush, uint8_t reg, uint8_t len, uint32_t *data); -/** once read register */ int dsp563xx_once_reg_read(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t *data); /** once write register */ int dsp563xx_once_reg_write(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t data); diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c index 621caaf37a..65efbae324 100644 --- a/src/target/dsp5680xx.c +++ b/src/target/dsp5680xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Rodrigo L. Rosa * @@ -16,7 +16,7 @@ #include "target_type.h" #include "dsp5680xx.h" -struct dsp5680xx_common dsp5680xx_context; +static struct dsp5680xx_common dsp5680xx_context; #define _E "DSP5680XX_ERROR:%d\nAt:%s:%d:%s" #define err_check(r, c, m) if (r != ERROR_OK) {LOG_ERROR(_E, c, __func__, __LINE__, m); return r; } @@ -44,7 +44,7 @@ static int reset_jtag(void) { int retval; - tap_state_t states[2]; + enum tap_state states[2]; const char *cp = "RESET"; @@ -855,7 +855,7 @@ static int eonce_pc_store(struct target *target) return ERROR_OK; } -static int dsp5680xx_target_create(struct target *target, Jim_Interp *interp) +static int dsp5680xx_target_create(struct target *target) { struct dsp5680xx_common *dsp5680xx = calloc(1, sizeof(struct dsp5680xx_common)); @@ -993,8 +993,8 @@ static int dsp5680xx_poll(struct target *target) return ERROR_OK; } -static int dsp5680xx_resume(struct target *target, int current, - target_addr_t address, int hb, int d) +static int dsp5680xx_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { if (target->state == TARGET_RUNNING) { LOG_USER("Target already running."); @@ -1172,7 +1172,7 @@ static int dsp5680xx_read(struct target *t, target_addr_t a, uint32_t size, dsp5680xx_context.flush = 0; int counter = FLUSH_COUNT_READ_WRITE; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { if (--counter == 0) { dsp5680xx_context.flush = 1; counter = FLUSH_COUNT_READ_WRITE; @@ -2048,7 +2048,7 @@ int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t coun retval = core_tx_upper_data(target, tmp, &drscan_data); err_check_propagate(retval); - retval = dsp5680xx_resume(target, 0, ram_addr, 0, 0); + retval = dsp5680xx_resume(target, false, ram_addr, false, false); err_check_propagate(retval); int counter = FLUSH_COUNT_FLASH; @@ -2200,8 +2200,8 @@ int dsp5680xx_f_lock(struct target *target) struct jtag_tap *tap_chp; struct jtag_tap *tap_cpu; - uint16_t lock_word[] = { HFM_LOCK_FLASH }; - retval = dsp5680xx_f_wr(target, (uint8_t *) (lock_word), HFM_LOCK_ADDR_L, 2, 1); + uint16_t lock_word = HFM_LOCK_FLASH; + retval = dsp5680xx_f_wr(target, (uint8_t *)&lock_word, HFM_LOCK_ADDR_L, 2, 1); err_check_propagate(retval); jtag_add_reset(0, 1); @@ -2234,8 +2234,8 @@ int dsp5680xx_f_lock(struct target *target) return retval; } -static int dsp5680xx_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int dsp5680xx_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP, "Not implemented yet."); diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h index 3c03ac2695..152f446977 100644 --- a/src/target/dsp5680xx.h +++ b/src/target/dsp5680xx.h @@ -278,8 +278,6 @@ struct dsp5680xx_common { bool debug_mode_enabled; }; -extern struct dsp5680xx_common dsp5680xx_context; - static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target) { diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 9bfee81941..7aef153b58 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * diff --git a/src/target/esirisc.c b/src/target/esirisc.c index 6121648db8..fac5dc72ee 100644 --- a/src/target/esirisc.c +++ b/src/target/esirisc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Square, Inc. * @@ -160,11 +160,11 @@ static int esirisc_disable_interrupts(struct target *target) uint32_t etc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC"); return retval; } @@ -172,7 +172,7 @@ static int esirisc_disable_interrupts(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC"); return retval; } @@ -187,11 +187,11 @@ static int esirisc_enable_interrupts(struct target *target) uint32_t etc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC"); return retval; } @@ -199,7 +199,7 @@ static int esirisc_enable_interrupts(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC"); return retval; } @@ -212,12 +212,12 @@ static int esirisc_save_interrupts(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &esirisc->etc_save); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC"); return retval; } @@ -229,12 +229,12 @@ static int esirisc_restore_interrupts(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, esirisc->etc_save); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC"); return retval; } @@ -247,12 +247,12 @@ static int esirisc_save_hwdc(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC, &esirisc->hwdc_save); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Thread CSR: HWDC"); return retval; } @@ -265,12 +265,12 @@ static int esirisc_restore_hwdc(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC, esirisc->hwdc_save); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: HWDC"); return retval; } @@ -281,9 +281,9 @@ static int esirisc_save_context(struct target *target) { struct esirisc_common *esirisc = target_to_esirisc(target); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); - for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) { + for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) { struct reg *reg = esirisc->reg_cache->reg_list + i; struct esirisc_reg *reg_info = reg->arch_info; @@ -298,9 +298,9 @@ static int esirisc_restore_context(struct target *target) { struct esirisc_common *esirisc = target_to_esirisc(target); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); - for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) { + for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) { struct reg *reg = esirisc->reg_cache->reg_list + i; struct esirisc_reg *reg_info = reg->arch_info; @@ -316,14 +316,16 @@ static int esirisc_flush_caches(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; + } int retval = esirisc_jtag_flush_caches(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to flush caches", target_name(target)); + LOG_TARGET_ERROR(target, "failed to flush caches"); return retval; } @@ -335,7 +337,7 @@ static int esirisc_wait_debug_active(struct esirisc_common *esirisc, int ms) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int64_t t; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(esirisc->target, "-"); t = timeval_ms(); for (;;) { @@ -357,7 +359,7 @@ static int esirisc_read_memory(struct target *target, target_addr_t address, struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int num_bits = 8 * size; for (uint32_t i = 0; i < count; ++i) { @@ -381,12 +383,12 @@ static int esirisc_read_memory(struct target *target, target_addr_t address, break; default: - LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size); + LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); return ERROR_FAIL; } if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target), + LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR, address); return retval; } @@ -406,7 +408,7 @@ static int esirisc_write_memory(struct target *target, target_addr_t address, struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int num_bits = 8 * size; for (uint32_t i = 0; i < count; ++i) { @@ -429,12 +431,12 @@ static int esirisc_write_memory(struct target *target, target_addr_t address, break; default: - LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size); + LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); return ERROR_FAIL; } if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR, target_name(target), + LOG_TARGET_ERROR(target, "failed to write address: 0x%" TARGET_PRIxADDR, address); return retval; } @@ -458,7 +460,7 @@ static int esirisc_next_breakpoint(struct target *target) struct breakpoint **breakpoints_p = esirisc->breakpoints_p; struct breakpoint **breakpoints_e = breakpoints_p + esirisc->num_breakpoints; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); for (int bp_index = 0; breakpoints_p < breakpoints_e; ++breakpoints_p, ++bp_index) if (!*breakpoints_p) @@ -475,13 +477,13 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea uint32_t ibc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* * The default linker scripts provided by the eSi-RISC toolchain do * not specify attributes on memory regions, which results in * incorrect application of software breakpoints by GDB. Targets - * must be configured with `gdb_breakpoint_override hard` as + * must be configured with `gdb breakpoint_override hard` as * software breakpoints are not supported. */ if (breakpoint->type != BKPT_HARD) @@ -489,7 +491,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea bp_index = esirisc_next_breakpoint(target); if (bp_index < 0) { - LOG_ERROR("%s: out of hardware breakpoints", target_name(target)); + LOG_TARGET_ERROR(target, "out of hardware breakpoints"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -500,14 +502,14 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBA_N + bp_index, breakpoint->address); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBA"); return retval; } /* enable instruction breakpoint */ retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC"); return retval; } @@ -515,7 +517,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC"); return retval; } @@ -526,7 +528,7 @@ static int esirisc_add_breakpoints(struct target *target) { struct breakpoint *breakpoint = target->breakpoints; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); while (breakpoint) { if (!breakpoint->is_set) @@ -546,12 +548,12 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b uint32_t ibc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* disable instruction breakpoint */ retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC"); return retval; } @@ -559,7 +561,7 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC"); return retval; } @@ -574,12 +576,12 @@ static int esirisc_remove_breakpoints(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* clear instruction breakpoints */ int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, 0); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC"); return retval; } @@ -594,7 +596,7 @@ static int esirisc_next_watchpoint(struct target *target) struct watchpoint **watchpoints_p = esirisc->watchpoints_p; struct watchpoint **watchpoints_e = watchpoints_p + esirisc->num_watchpoints; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); for (int wp_index = 0; watchpoints_p < watchpoints_e; ++watchpoints_p, ++wp_index) if (!*watchpoints_p) @@ -611,11 +613,11 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc uint32_t dbs, dbc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); wp_index = esirisc_next_watchpoint(target); if (wp_index < 0) { - LOG_ERROR("%s: out of hardware watchpoints", target_name(target)); + LOG_TARGET_ERROR(target, "out of hardware watchpoints"); return ERROR_FAIL; } @@ -626,14 +628,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBA_N + wp_index, watchpoint->address); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBA"); return retval; } /* specify data breakpoint size */ retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, &dbs); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBS"); return retval; } @@ -655,7 +657,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc break; default: - LOG_ERROR("%s: unsupported length: %" PRIu32, target_name(target), + LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32, watchpoint->length); return ERROR_FAIL; } @@ -664,14 +666,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, dbs); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBS"); return retval; } /* enable data breakpoint */ retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC"); return retval; } @@ -690,8 +692,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc break; default: - LOG_ERROR("%s: unsupported rw: %" PRId32, target_name(target), - watchpoint->rw); + LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw); return ERROR_FAIL; } @@ -699,7 +700,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC"); return retval; } @@ -710,7 +711,7 @@ static int esirisc_add_watchpoints(struct target *target) { struct watchpoint *watchpoint = target->watchpoints; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); while (watchpoint) { if (!watchpoint->is_set) @@ -730,12 +731,12 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w uint32_t dbc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* disable data breakpoint */ retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC"); return retval; } @@ -743,7 +744,7 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC"); return retval; } @@ -758,12 +759,12 @@ static int esirisc_remove_watchpoints(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* clear data breakpoints */ int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, 0); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC"); return retval; } @@ -777,14 +778,14 @@ static int esirisc_halt(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (target->state == TARGET_HALTED) return ERROR_OK; int retval = esirisc_jtag_break(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to halt target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to halt target"); return retval; } @@ -800,11 +801,11 @@ static int esirisc_disable_step(struct target *target) uint32_t dc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC"); return retval; } @@ -812,7 +813,7 @@ static int esirisc_disable_step(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC"); return retval; } @@ -826,11 +827,11 @@ static int esirisc_enable_step(struct target *target) uint32_t dc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC"); return retval; } @@ -838,25 +839,28 @@ static int esirisc_enable_step(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC"); return retval; } return ERROR_OK; } -static int esirisc_resume_or_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution, bool step) +static int esirisc_resume_or_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution, + bool step) { struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; struct breakpoint *breakpoint = NULL; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); - if (target->state != TARGET_HALTED) + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; + } if (!debug_execution) { target_free_all_working_areas(target); @@ -897,7 +901,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add retval = esirisc_jtag_continue(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to resume target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to resume target"); return retval; } @@ -914,22 +918,22 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add return ERROR_OK; } -static int esirisc_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int esirisc_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); return esirisc_resume_or_step(target, current, address, handle_breakpoints, debug_execution, false); } -static int esirisc_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int esirisc_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); return esirisc_resume_or_step(target, current, address, - handle_breakpoints, 0, true); + handle_breakpoints, false, true); } static int esirisc_debug_step(struct target *target) @@ -938,20 +942,20 @@ static int esirisc_debug_step(struct target *target) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); esirisc_disable_interrupts(target); esirisc_enable_step(target); retval = esirisc_jtag_continue(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to resume target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to resume target"); return retval; } retval = esirisc_wait_debug_active(esirisc, STEP_TIMEOUT); if (retval != ERROR_OK) { - LOG_ERROR("%s: step timed out", target_name(target)); + LOG_TARGET_ERROR(target, "step timed out"); return retval; } @@ -967,23 +971,23 @@ static int esirisc_debug_reset(struct target *target) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_assert_reset(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to assert reset", target_name(target)); + LOG_TARGET_ERROR(target, "failed to assert reset"); return retval; } retval = esirisc_jtag_deassert_reset(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to deassert reset", target_name(target)); + LOG_TARGET_ERROR(target, "failed to deassert reset"); return retval; } retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT); if (retval != ERROR_OK) { - LOG_ERROR("%s: reset timed out", target_name(target)); + LOG_TARGET_ERROR(target, "reset timed out"); return retval; } @@ -996,11 +1000,11 @@ static int esirisc_debug_enable(struct target *target) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_enable_debug(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to enable debug mode", target_name(target)); + LOG_TARGET_ERROR(target, "failed to enable debug mode"); return retval; } @@ -1011,13 +1015,13 @@ static int esirisc_debug_enable(struct target *target) * targets, which will respond with all ones and appear active. */ if (esirisc_jtag_is_stopped(jtag_info)) { - LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target)); + LOG_TARGET_INFO(target, "debug clock inactive; attempting debug reset"); retval = esirisc_debug_reset(target); if (retval != ERROR_OK) return retval; if (esirisc_jtag_is_stopped(jtag_info)) { - LOG_ERROR("%s: target unresponsive; giving up", target_name(target)); + LOG_TARGET_ERROR(target, "target unresponsive; giving up"); return ERROR_FAIL; } } @@ -1030,7 +1034,7 @@ static int esirisc_debug_entry(struct target *target) struct esirisc_common *esirisc = target_to_esirisc(target); struct breakpoint *breakpoint; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); esirisc_save_context(target); @@ -1083,12 +1087,12 @@ static int esirisc_poll(struct target *target) retval = esirisc_jtag_enable_debug(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to poll target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to poll target"); return retval; } if (esirisc_jtag_is_stopped(jtag_info)) { - LOG_ERROR("%s: target has stopped; reset required", target_name(target)); + LOG_TARGET_ERROR(target, "target has stopped; reset required"); target->state = TARGET_UNKNOWN; return ERROR_TARGET_FAILURE; } @@ -1118,7 +1122,7 @@ static int esirisc_assert_reset(struct target *target) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (jtag_get_reset_config() & RESET_HAS_SRST) { jtag_add_reset(1, 1); @@ -1130,7 +1134,7 @@ static int esirisc_assert_reset(struct target *target) retval = esirisc_jtag_assert_reset(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to assert reset", target_name(target)); + LOG_TARGET_ERROR(target, "failed to assert reset"); return retval; } } @@ -1149,19 +1153,19 @@ static int esirisc_reset_entry(struct target *target) uint32_t eta, epc; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* read exception table address */ retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETA, &eta); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETA"); return retval; } /* read reset entry point */ retval = esirisc_jtag_read_word(jtag_info, eta + ENTRY_RESET, &epc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target), + LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR, (target_addr_t)epc); return retval; } @@ -1169,7 +1173,7 @@ static int esirisc_reset_entry(struct target *target) /* write reset entry point */ retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_EPC, epc); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Thread CSR: EPC"); return retval; } @@ -1182,7 +1186,7 @@ static int esirisc_deassert_reset(struct target *target) struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (jtag_get_reset_config() & RESET_HAS_SRST) { jtag_add_reset(0, 0); @@ -1198,14 +1202,14 @@ static int esirisc_deassert_reset(struct target *target) } else { retval = esirisc_jtag_deassert_reset(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to deassert reset", target_name(target)); + LOG_TARGET_ERROR(target, "failed to deassert reset"); return retval; } } retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT); if (retval != ERROR_OK) { - LOG_ERROR("%s: reset timed out", target_name(target)); + LOG_TARGET_ERROR(target, "reset timed out"); return retval; } @@ -1221,7 +1225,7 @@ static int esirisc_deassert_reset(struct target *target) if (!target->reset_halt) { retval = esirisc_jtag_continue(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to resume target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to resume target"); return retval; } } @@ -1237,18 +1241,18 @@ static int esirisc_arch_state(struct target *target) uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size); uint32_t ed = buf_get_u32(esirisc->ed->value, 0, esirisc->ed->size); - LOG_USER("target halted due to %s, exception: %s\n" + LOG_TARGET_USER(target, "target halted due to %s, exception: %s\n" "EPC: 0x%" PRIx32 ", ECAS: 0x%" PRIx32 ", EID: 0x%" PRIx32 ", ED: 0x%" PRIx32, debug_reason_name(target), esirisc_exception_strings[eid], epc, ecas, eid, ed); return ERROR_OK; } -static const char *esirisc_get_gdb_arch(struct target *target) +static const char *esirisc_get_gdb_arch(const struct target *target) { struct esirisc_common *esirisc = target_to_esirisc(target); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); /* * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a @@ -1268,7 +1272,7 @@ static int esirisc_get_gdb_reg_list(struct target *target, struct reg **reg_list { struct esirisc_common *esirisc = target_to_esirisc(target); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); *reg_list_size = ESIRISC_NUM_REGS; @@ -1298,11 +1302,11 @@ static int esirisc_read_reg(struct reg *reg) struct target *target = esirisc->target; uint32_t data; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_read_reg(jtag_info, reg->number, &data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read register: %s", target_name(target), reg->name); + LOG_TARGET_ERROR(target, "failed to read register: %s", reg->name); return retval; } @@ -1321,11 +1325,11 @@ static int esirisc_write_reg(struct reg *reg) struct target *target = esirisc->target; uint32_t data = buf_get_u32(reg->value, 0, reg->size); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_write_reg(jtag_info, reg->number, data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write register: %s", target_name(target), reg->name); + LOG_TARGET_ERROR(target, "failed to write register: %s", reg->name); return retval; } @@ -1343,11 +1347,11 @@ static int esirisc_read_csr(struct reg *reg) struct target *target = esirisc->target; uint32_t data; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_read_csr(jtag_info, reg_info->bank, reg_info->csr, &data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read CSR: %s", target_name(target), reg->name); + LOG_TARGET_ERROR(target, "failed to read CSR: %s", reg->name); return retval; } @@ -1366,11 +1370,11 @@ static int esirisc_write_csr(struct reg *reg) struct target *target = esirisc->target; uint32_t data = buf_get_u32(reg->value, 0, reg->size); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); int retval = esirisc_jtag_write_csr(jtag_info, reg_info->bank, reg_info->csr, data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write CSR: %s", target_name(target), reg->name); + LOG_TARGET_ERROR(target, "failed to write CSR: %s", reg->name); return retval; } @@ -1386,7 +1390,7 @@ static int esirisc_get_reg(struct reg *reg) struct esirisc_common *esirisc = reg_info->esirisc; struct target *target = esirisc->target; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; @@ -1401,7 +1405,7 @@ static int esirisc_set_reg(struct reg *reg, uint8_t *buf) struct target *target = esirisc->target; uint32_t value = buf_get_u32(buf, 0, reg->size); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; @@ -1425,7 +1429,7 @@ static struct reg_cache *esirisc_build_reg_cache(struct target *target) struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = calloc(ESIRISC_NUM_REGS, sizeof(struct reg)); - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); cache->name = "eSi-RISC registers"; cache->next = NULL; @@ -1482,6 +1486,32 @@ static struct reg_cache *esirisc_build_reg_cache(struct target *target) return cache; } +static void esirisc_free_reg_cache(struct target *target) +{ + struct esirisc_common *esirisc = target_to_esirisc(target); + struct reg_cache *cache = esirisc->reg_cache; + struct reg *reg_list = cache->reg_list; + + for (int i = 0; i < esirisc->num_regs; ++i) { + struct reg *reg = reg_list + esirisc_regs[i].number; + + free(reg->arch_info); + free(reg->value); + free(reg->reg_data_type); + } + + for (size_t i = 0; i < ARRAY_SIZE(esirisc_csrs); ++i) { + struct reg *reg = reg_list + esirisc_csrs[i].number; + + free(reg->arch_info); + free(reg->value); + free(reg->reg_data_type); + } + + free(reg_list); + free(cache); +} + static int esirisc_identify(struct target *target) { struct esirisc_common *esirisc = target_to_esirisc(target); @@ -1489,11 +1519,11 @@ static int esirisc_identify(struct target *target) uint32_t csr; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_ARCH0, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: ARCH0"); return retval; } @@ -1502,7 +1532,7 @@ static int esirisc_identify(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_MEM, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: MEM"); return retval; } @@ -1511,7 +1541,7 @@ static int esirisc_identify(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_IC, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: IC"); return retval; } @@ -1519,7 +1549,7 @@ static int esirisc_identify(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DC, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DC"); return retval; } @@ -1527,7 +1557,7 @@ static int esirisc_identify(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DBG, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DBG"); return retval; } @@ -1536,7 +1566,7 @@ static int esirisc_identify(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_TRACE, &csr); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Configuration CSR: TRACE"); return retval; } @@ -1545,7 +1575,7 @@ static int esirisc_identify(struct target *target) return ERROR_OK; } -static int esirisc_target_create(struct target *target, Jim_Interp *interp) +static int esirisc_target_create(struct target *target) { struct jtag_tap *tap = target->tap; struct esirisc_common *esirisc; @@ -1554,8 +1584,7 @@ static int esirisc_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; if (tap->ir_length != INSTR_LENGTH) { - LOG_ERROR("%s: invalid IR length; expected %d", target_name(target), - INSTR_LENGTH); + LOG_TARGET_ERROR(target, "invalid IR length; expected %d", INSTR_LENGTH); return ERROR_FAIL; } @@ -1580,13 +1609,26 @@ static int esirisc_init_target(struct command_context *cmd_ctx, struct target *t return ERROR_OK; } +static void esirisc_deinit_target(struct target *target) +{ + struct esirisc_common *esirisc = target_to_esirisc(target); + + if (!target_was_examined(target)) + return; + + esirisc_free_reg_cache(target); + + free(esirisc->gdb_arch); + free(esirisc); +} + static int esirisc_examine(struct target *target) { struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_jtag *jtag_info = &esirisc->jtag_info; int retval; - LOG_DEBUG("-"); + LOG_TARGET_DEBUG(target, "-"); if (!target_was_examined(target)) { retval = esirisc_debug_enable(target); @@ -1606,7 +1648,7 @@ static int esirisc_examine(struct target *target) } else { retval = esirisc_jtag_break(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to halt target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to halt target"); return retval; } @@ -1615,7 +1657,7 @@ static int esirisc_examine(struct target *target) retval = esirisc_identify(target); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to identify target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to identify target"); return retval; } @@ -1632,20 +1674,20 @@ static int esirisc_examine(struct target *target) else { retval = esirisc_jtag_continue(jtag_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to resume target", target_name(target)); + LOG_TARGET_ERROR(target, "failed to resume target"); return retval; } } target_set_examined(target); - LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target), + LOG_TARGET_INFO(target, "%d bit, %d registers, %s%s%s", esirisc->num_bits, esirisc->num_regs, target_endianness(target), esirisc->has_icache ? ", icache" : "", esirisc->has_dcache ? ", dcache" : ""); - LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target), + LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints%s", esirisc->num_breakpoints, esirisc->num_watchpoints, esirisc->has_trace ? ", trace" : ""); } @@ -1664,7 +1706,7 @@ COMMAND_HANDLER(handle_esirisc_cache_arch_command) else if (strcmp(*CMD_ARGV, "von_neumann") == 0) esirisc->cache_arch = ESIRISC_CACHE_VON_NEUMANN; else { - LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV); + LOG_TARGET_ERROR(target, "invalid cache_arch: %s", *CMD_ARGV); return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -1681,7 +1723,7 @@ COMMAND_HANDLER(handle_esirisc_flush_caches_command) int retval; if (!esirisc_has_cache(esirisc)) { - LOG_ERROR("target does not support caching"); + LOG_TARGET_ERROR(target, "target does not support caching"); return ERROR_FAIL; } @@ -1727,7 +1769,7 @@ COMMAND_HANDLER(handle_esirisc_hwdc_command) while (CMD_ARGC-- > 0) { int mask = esirisc_find_hwdc_mask(CMD_ARGV[CMD_ARGC]); if (mask < 0) { - LOG_ERROR("invalid mask: %s", CMD_ARGV[CMD_ARGC]); + LOG_TARGET_ERROR(target, "invalid mask: %s", CMD_ARGV[CMD_ARGC]); return ERROR_COMMAND_SYNTAX_ERROR; } esirisc->hwdc_save |= mask; @@ -1818,5 +1860,6 @@ struct target_type esirisc_target = { .target_create = esirisc_target_create, .init_target = esirisc_init_target, + .deinit_target = esirisc_deinit_target, .examine = esirisc_examine, }; diff --git a/src/target/esirisc.h b/src/target/esirisc.h index 7496b1eda7..6f8cd14722 100644 --- a/src/target/esirisc.h +++ b/src/target/esirisc.h @@ -106,7 +106,7 @@ struct esirisc_reg { int (*write)(struct reg *reg); }; -static inline struct esirisc_common *target_to_esirisc(struct target *target) +static inline struct esirisc_common *target_to_esirisc(const struct target *target) { return (struct esirisc_common *)target->arch_info; } diff --git a/src/target/esirisc_jtag.c b/src/target/esirisc_jtag.c index 4c54c245a8..ad2bef543e 100644 --- a/src/target/esirisc_jtag.c +++ b/src/target/esirisc_jtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Square, Inc. * @@ -19,6 +19,8 @@ #include "esirisc_jtag.h" +static uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info); + static void esirisc_jtag_set_instr(struct esirisc_jtag *jtag_info, uint32_t new_instr) { struct jtag_tap *tap = jtag_info->tap; @@ -58,11 +60,12 @@ static int esirisc_jtag_get_padding(void) return padding; } -static int esirisc_jtag_count_bits(int num_fields, struct scan_field *fields) +static int esirisc_jtag_count_bits(unsigned int num_fields, + struct scan_field *fields) { int bit_count = 0; - for (int i = 0; i < num_fields; ++i) + for (unsigned int i = 0; i < num_fields; ++i) bit_count += fields[i].num_bits; return bit_count; @@ -130,7 +133,9 @@ static int esirisc_jtag_recv(struct esirisc_jtag *jtag_info, int num_in_bytes = DIV_ROUND_UP(num_in_bits, 8); struct scan_field fields[3]; - uint8_t r[num_in_bytes * 2]; + /* prevent zero-size variable length array */ + int r_size = num_in_bytes ? num_in_bytes * 2 : 1; + uint8_t r[r_size]; esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG); @@ -218,7 +223,7 @@ bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info) return !!(jtag_info->status & 1<<6); /* S */ } -uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info) +static uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info) { return jtag_info->status & 0x3f; /* EID */ } @@ -487,7 +492,7 @@ int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info) return esirisc_jtag_send_ctrl(jtag_info, DEBUG_ENABLE_DEBUG); } -int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info) +static __attribute__((unused)) int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info) { return esirisc_jtag_send_ctrl(jtag_info, DEBUG_DISABLE_DEBUG); } diff --git a/src/target/esirisc_jtag.h b/src/target/esirisc_jtag.h index 98ec8af8d6..d59b75fbee 100644 --- a/src/target/esirisc_jtag.h +++ b/src/target/esirisc_jtag.h @@ -54,7 +54,6 @@ struct esirisc_jtag { bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info); bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info); -uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info); int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info, uint32_t address, uint8_t *data); @@ -81,7 +80,6 @@ int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t csr, uint32_t data); int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info); -int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info); int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info); int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info); diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c index 2f183cfd64..a1d92d1ca9 100644 --- a/src/target/esirisc_trace.c +++ b/src/target/esirisc_trace.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Square, Inc. * @@ -85,7 +85,7 @@ static int esirisc_trace_clear_status(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, ~0); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Status", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Status"); return retval; } @@ -102,7 +102,7 @@ static int esirisc_trace_get_status(struct target *target, uint32_t *status) int retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, status); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Trace CSR: Status", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Trace CSR: Status"); return retval; } @@ -121,7 +121,7 @@ static int esirisc_trace_start(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control"); return retval; } @@ -129,7 +129,7 @@ static int esirisc_trace_start(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control"); return retval; } @@ -148,7 +148,7 @@ static int esirisc_trace_stop(struct target *target) retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control"); return retval; } @@ -156,7 +156,7 @@ static int esirisc_trace_stop(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control"); return retval; } @@ -195,7 +195,7 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control"); return retval; } @@ -203,14 +203,14 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_START, trace_info->buffer_start); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: BufferStart", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferStart"); return retval; } retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_END, trace_info->buffer_end); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: BufferEnd", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferEnd"); return retval; } @@ -221,7 +221,7 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR, trace_info->buffer_start); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: BufferCurrent", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferCurrent"); return retval; } @@ -241,7 +241,7 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_TRIGGER, trigger); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Trigger", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Trigger"); return retval; } @@ -249,14 +249,14 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_DATA, trace_info->start_data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: StartData", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartData"); return retval; } retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_MASK, trace_info->start_mask); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: StartMask", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartMask"); return retval; } @@ -264,14 +264,14 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_DATA, trace_info->stop_data); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: StopData", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopData"); return retval; } retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_MASK, trace_info->stop_mask); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: StopMask", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopMask"); return retval; } @@ -279,7 +279,7 @@ static int esirisc_trace_init(struct target *target) retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_DELAY, trace_info->delay_cycles); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to write Trace CSR: Delay", target_name(target)); + LOG_TARGET_ERROR(target, "failed to write Trace CSR: Delay"); return retval; } @@ -287,9 +287,9 @@ static int esirisc_trace_init(struct target *target) } static int esirisc_trace_buf_get_u32(uint8_t *buffer, uint32_t size, - unsigned *pos, unsigned count, uint32_t *value) + unsigned int *pos, unsigned int count, uint32_t *value) { - const unsigned num_bits = size * 8; + const unsigned int num_bits = size * 8; if (*pos+count > num_bits) return ERROR_FAIL; @@ -301,7 +301,7 @@ static int esirisc_trace_buf_get_u32(uint8_t *buffer, uint32_t size, } static int esirisc_trace_buf_get_pc(struct target *target, uint8_t *buffer, uint32_t size, - unsigned *pos, uint32_t *value) + unsigned int *pos, uint32_t *value) { struct esirisc_common *esirisc = target_to_esirisc(target); struct esirisc_trace *trace_info = &esirisc->trace_info; @@ -326,7 +326,7 @@ static int esirisc_trace_read_memory(struct target *target, target_addr_t addres retval = target_read_memory(target, address, 1, size, buffer); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read trace data", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read trace data"); return retval; } @@ -346,7 +346,7 @@ static int esirisc_trace_read_buffer(struct target *target, uint8_t *buffer) retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR, &buffer_cur); if (retval != ERROR_OK) { - LOG_ERROR("%s: failed to read Trace CSR: BufferCurrent", target_name(target)); + LOG_TARGET_ERROR(target, "failed to read Trace CSR: BufferCurrent"); return retval; } @@ -380,7 +380,7 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b const uint32_t num_bits = size * 8; int retval; - unsigned pos = 0; + unsigned int pos = 0; while (pos < num_bits) { uint32_t id; @@ -484,7 +484,7 @@ static int esirisc_trace_analyze_simple(struct command_invocation *cmd, uint8_t const uint32_t num_bits = size * 8; int retval; - unsigned pos = 0; + unsigned int pos = 0; while (pos < num_bits) { uint32_t pc; diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am index df002b33bc..cf82ee995e 100644 --- a/src/target/espressif/Makefile.am +++ b/src/target/espressif/Makefile.am @@ -2,13 +2,27 @@ noinst_LTLIBRARIES += %D%/libespressif.la %C%_libespressif_la_SOURCES = \ - %D%/esp_xtensa.c \ - %D%/esp_xtensa.h \ - %D%/esp_xtensa_smp.c \ - %D%/esp_xtensa_smp.h \ - %D%/esp32.c \ - %D%/esp32.h \ - %D%/esp32s2.c \ - %D%/esp32s2.h \ - %D%/esp32s3.c \ - %D%/esp32s3.h + %D%/esp_xtensa.c \ + %D%/esp_xtensa.h \ + %D%/esp_xtensa_smp.c \ + %D%/esp_xtensa_smp.h \ + %D%/esp_xtensa_semihosting.c \ + %D%/esp_xtensa_semihosting.h \ + %D%/esp_xtensa_apptrace.c \ + %D%/esp_xtensa_apptrace.h \ + %D%/esp_xtensa_algorithm.c \ + %D%/esp_xtensa_algorithm.h \ + %D%/esp32_apptrace.c \ + %D%/esp32_apptrace.h \ + %D%/esp32.c \ + %D%/esp32s2.c \ + %D%/esp32s3.c \ + %D%/esp.c \ + %D%/esp.h \ + %D%/esp32_sysview.c \ + %D%/esp32_sysview.h \ + %D%/segger_sysview.h \ + %D%/esp_semihosting.c \ + %D%/esp_semihosting.h \ + %D%/esp_algorithm.c \ + %D%/esp_algorithm.h diff --git a/src/target/espressif/esp.c b/src/target/espressif/esp.c new file mode 100644 index 0000000000..600f6d7e99 --- /dev/null +++ b/src/target/espressif/esp.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Espressif chips common target API for OpenOCD * + * Copyright (C) 2021 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/log.h> +#include <helper/binarybuffer.h> +#include "target/target.h" +#include "esp.h" + +int esp_common_init(struct esp_common *esp, const struct esp_algorithm_hw *algo_hw) +{ + if (!esp) + return ERROR_FAIL; + + esp->algo_hw = algo_hw; + + return ERROR_OK; +} + +int esp_dbgstubs_table_read(struct target *target, struct esp_dbg_stubs *dbg_stubs) +{ + uint32_t table_size, table_start_id, desc_entry_id, gcov_entry_id; + uint32_t entries[ESP_DBG_STUB_ENTRY_MAX] = {0}; + uint8_t entry_buff[sizeof(entries)] = {0}; /* to avoid endiannes issues */ + + LOG_TARGET_DEBUG(target, "Read debug stubs info %" PRIx32 " / %d", dbg_stubs->base, dbg_stubs->entries_count); + + /* First of, read 2 entries to get magic num and table size */ + int res = target_read_buffer(target, dbg_stubs->base, sizeof(uint32_t) * 2, entry_buff); + if (res != ERROR_OK) { + LOG_ERROR("%s: Failed to read first debug stub entry!", target_name(target)); + return res; + } + entries[0] = target_buffer_get_u32(target, entry_buff); + entries[1] = target_buffer_get_u32(target, entry_buff + sizeof(uint32_t)); + + if (entries[0] != ESP_DBG_STUB_MAGIC_NUM_VAL) { + /* idf with the old table entry structure */ + table_size = 2; + table_start_id = 0; + desc_entry_id = 0; + gcov_entry_id = 1; + } else { + table_size = entries[1]; + table_start_id = ESP_DBG_STUB_TABLE_START; + desc_entry_id = ESP_DBG_STUB_TABLE_START; + gcov_entry_id = ESP_DBG_STUB_ENTRY_FIRST; + + /* discard unsupported entries */ + if (table_size > ESP_DBG_STUB_ENTRY_MAX) + table_size = ESP_DBG_STUB_ENTRY_MAX; + + /* now read the remaining entries */ + res = target_read_buffer(target, dbg_stubs->base + 2 * sizeof(uint32_t), sizeof(uint32_t) * table_size - 2, + entry_buff + sizeof(uint32_t) * 2); + if (res != ERROR_OK) { + LOG_TARGET_ERROR(target, "Failed to read debug stubs info!"); + return res; + } + for (unsigned int i = 2; i < table_size; ++i) + entries[i] = target_buffer_get_u32(target, entry_buff + sizeof(uint32_t) * i); + + dbg_stubs->entries[ESP_DBG_STUB_CAPABILITIES] = entries[ESP_DBG_STUB_CAPABILITIES]; + } + + dbg_stubs->entries[ESP_DBG_STUB_DESC] = entries[desc_entry_id]; + dbg_stubs->entries[ESP_DBG_STUB_ENTRY_GCOV] = entries[gcov_entry_id]; + + for (enum esp_dbg_stub_id i = ESP_DBG_STUB_DESC; i < ESP_DBG_STUB_ENTRY_MAX; i++) { + LOG_DEBUG("Check dbg stub %d - %x", i, dbg_stubs->entries[i]); + if (dbg_stubs->entries[i]) { + LOG_DEBUG("New dbg stub %d at %x", dbg_stubs->entries_count, dbg_stubs->entries[i]); + dbg_stubs->entries_count++; + } + } + if (dbg_stubs->entries_count < table_size - table_start_id) + LOG_WARNING("Not full dbg stub table %d of %d", dbg_stubs->entries_count, table_size - table_start_id); + + return ERROR_OK; +} diff --git a/src/target/espressif/esp.h b/src/target/espressif/esp.h new file mode 100644 index 0000000000..6e0a2d2d35 --- /dev/null +++ b/src/target/espressif/esp.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Espressif chips common target API for OpenOCD * + * Copyright (C) 2021 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_H +#define OPENOCD_TARGET_ESP_H + +#include <stdint.h> +#include <helper/bits.h> + +/* must be in sync with ESP-IDF version */ +/** Size of the pre-compiled target buffer for stub trampoline. + * @note Must be in sync with ESP-IDF version */ +#define ESP_DBG_STUBS_CODE_BUF_SIZE 32 /* TODO: move this info to esp_dbg_stubs_desc */ +/** Size of the pre-compiled target buffer for stack. + * @note Must be in sync with ESP-IDF version */ +#define ESP_DBG_STUBS_STACK_MIN_SIZE 2048/* TODO: move this info to esp_dbg_stubs_desc */ + +/** + * Debug stubs table entries IDs + * + * @note Must be in sync with ESP-IDF version + */ +enum esp_dbg_stub_id { + ESP_DBG_STUB_ENTRY_MAGIC_NUM, + ESP_DBG_STUB_TABLE_SIZE, + ESP_DBG_STUB_TABLE_START, + ESP_DBG_STUB_DESC = ESP_DBG_STUB_TABLE_START, /*< Stubs descriptor ID */ + ESP_DBG_STUB_ENTRY_FIRST, + ESP_DBG_STUB_ENTRY_GCOV = ESP_DBG_STUB_ENTRY_FIRST, /*< GCOV stub ID */ + ESP_DBG_STUB_CAPABILITIES, + /* add new stub entries here */ + ESP_DBG_STUB_ENTRY_MAX, +}; + +#define ESP_DBG_STUB_MAGIC_NUM_VAL 0xFEEDBEEF +#define ESP_DBG_STUB_CAP_GCOV_THREAD BIT(0) + +/** + * Debug stubs descriptor. ID: ESP_DBG_STUB_DESC + * + * @note Must be in sync with ESP-IDF version + */ +struct esp_dbg_stubs_desc { + /** Address of pre-compiled target buffer for stub trampoline. + * Size of the buffer is ESP_DBG_STUBS_CODE_BUF_SIZE + */ + uint32_t tramp_addr; + /** Pre-compiled target buffer's addr for stack. The size of the buffer is ESP_DBG_STUBS_STACK_MIN_SIZE. + * Target has the buffer which is used for the stack of onboard algorithms. + * If stack size required by algorithm exceeds ESP_DBG_STUBS_STACK_MIN_SIZE, + * it should be allocated using onboard function pointed by 'data_alloc' and + * freed by 'data_free'. They fit to the minimal stack. See below. + */ + uint32_t min_stack_addr; + /** Address of malloc-like function to allocate buffer on target. */ + uint32_t data_alloc; + /** Address of free-like function to free buffer allocated with data_alloc. */ + uint32_t data_free; +}; + +/** + * Debug stubs info. + */ +struct esp_dbg_stubs { + /** Address. */ + uint32_t base; + /** Table contents. */ + uint32_t entries[ESP_DBG_STUB_ENTRY_MAX]; + /** Number of table entries. */ + uint32_t entries_count; + /** Debug stubs decsriptor. */ + struct esp_dbg_stubs_desc desc; +}; + +struct esp_common { + const struct esp_algorithm_hw *algo_hw; + struct esp_dbg_stubs dbg_stubs; +}; + +int esp_common_init(struct esp_common *esp, const struct esp_algorithm_hw *algo_hw); +int esp_dbgstubs_table_read(struct target *target, struct esp_dbg_stubs *dbg_stubs); + +#endif /* OPENOCD_TARGET_ESP_H */ diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c index 29d94a272b..5e2490a229 100644 --- a/src/target/espressif/esp32.c +++ b/src/target/espressif/esp32.c @@ -1,10 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * ESP32 target API for OpenOCD * * Copyright (C) 2016-2019 Espressif Systems Ltd. * - * Author: Dmitry Yakovlev <dmitry@espressif.com> * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -15,8 +13,8 @@ #include <target/target.h> #include <target/target_type.h> #include <target/smp.h> +#include <target/semihosting_common.h> #include "assert.h" -#include "esp32.h" #include "esp_xtensa_smp.h" /* @@ -26,20 +24,8 @@ implementation. */ /* ESP32 memory map */ -#define ESP32_DRAM_LOW 0x3ffae000 -#define ESP32_DRAM_HIGH 0x40000000 -#define ESP32_IROM_MASK_LOW 0x40000000 -#define ESP32_IROM_MASK_HIGH 0x40064f00 -#define ESP32_IRAM_LOW 0x40070000 -#define ESP32_IRAM_HIGH 0x400a0000 -#define ESP32_RTC_IRAM_LOW 0x400c0000 -#define ESP32_RTC_IRAM_HIGH 0x400c2000 -#define ESP32_RTC_DRAM_LOW 0x3ff80000 -#define ESP32_RTC_DRAM_HIGH 0x3ff82000 #define ESP32_RTC_DATA_LOW 0x50000000 #define ESP32_RTC_DATA_HIGH 0x50002000 -#define ESP32_EXTRAM_DATA_LOW 0x3f800000 -#define ESP32_EXTRAM_DATA_HIGH 0x3fc00000 #define ESP32_DR_REG_LOW 0x3ff00000 #define ESP32_DR_REG_HIGH 0x3ff71000 #define ESP32_SYS_RAM_LOW 0x60000000UL @@ -72,204 +58,6 @@ implementation. #define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac) #define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0 - -/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in - *xtensa-overlay */ -static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = { - XT_REG_IDX_PC, - XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3, - XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7, - XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11, - XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15, - XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19, - XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23, - XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27, - XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31, - XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35, - XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39, - XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43, - XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47, - XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51, - XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55, - XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59, - XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63, - XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR, - XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1, - XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1, - XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI, - XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3, - ESP32_REG_IDX_EXPSTATE, - ESP32_REG_IDX_F64R_LO, - ESP32_REG_IDX_F64R_HI, - ESP32_REG_IDX_F64S, - XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3, - XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7, - XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11, - XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15, - XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, - XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR, - XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1, - XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1, - XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4, - XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC, - XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5, - XT_REG_IDX_EPS6, XT_REG_IDX_EPS7, - XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4, - XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE, - XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE, - XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT, - XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR, - XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2, - XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3, - XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3, - XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7, - XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11, - XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15, - XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT, - XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR, - XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS, - XT_REG_IDX_FAULT_INFO, - XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT, - XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER, - XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART, - XT_REG_IDX_TRAX_MEMEND, - XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1, - XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1, - XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR, -}; - -static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = { - { "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type }, - { "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type }, - { "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type }, - { "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type }, -}; - -static const struct xtensa_config esp32_xtensa_cfg = { - .density = true, - .aregs_num = XT_AREGS_NUM_MAX, - .windowed = true, - .coproc = true, - .fp_coproc = true, - .loop = true, - .miscregs_num = 4, - .threadptr = true, - .boolean = true, - .reloc_vec = true, - .proc_id = true, - .cond_store = true, - .mac16 = true, - .user_regs_num = ARRAY_SIZE(esp32_user_regs), - .user_regs = esp32_user_regs, - .fetch_user_regs = xtensa_fetch_user_regs_u32, - .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32, - .gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND, - .gdb_regs_mapping = esp32_gdb_regs_mapping, - .irom = { - .count = 2, - .regions = { - { - .base = ESP32_IROM_LOW, - .size = ESP32_IROM_HIGH - ESP32_IROM_LOW, - .access = XT_MEM_ACCESS_READ, - }, - { - .base = ESP32_IROM_MASK_LOW, - .size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW, - .access = XT_MEM_ACCESS_READ, - }, - } - }, - .iram = { - .count = 2, - .regions = { - { - .base = ESP32_IRAM_LOW, - .size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_RTC_IRAM_LOW, - .size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .drom = { - .count = 1, - .regions = { - { - .base = ESP32_DROM_LOW, - .size = ESP32_DROM_HIGH - ESP32_DROM_LOW, - .access = XT_MEM_ACCESS_READ, - }, - } - }, - .dram = { - .count = 6, - .regions = { - { - .base = ESP32_DRAM_LOW, - .size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_RTC_DRAM_LOW, - .size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_RTC_DATA_LOW, - .size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_EXTRAM_DATA_LOW, - .size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_DR_REG_LOW, - .size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_SYS_RAM_LOW, - .size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .exc = { - .enabled = true, - }, - .irq = { - .enabled = true, - .irq_num = 32, - }, - .high_irq = { - .enabled = true, - .excm_level = 3, - .nmi_num = 1, - }, - .tim_irq = { - .enabled = true, - .comp_num = 3, - }, - .debug = { - .enabled = true, - .irq_level = 6, - .ibreaks_num = 2, - .dbreaks_num = 2, - .icount_sz = 32, - }, - .trace = { - .enabled = true, - .mem_sz = ESP32_TRACEMEM_BLOCK_SZ, - .reversed_mem_access = true, - }, -}; - /* 0 - don't care, 1 - TMS low, 2 - TMS high */ enum esp32_flash_bootstrap { FBS_DONTCARE = 0, @@ -301,7 +89,7 @@ static inline struct esp32_common *target_to_esp32(struct target *target) * 6. restore initial PC and the contents of ESP32_SMP_RTC_DATA_LOW * TODO: some state of RTC_CNTL is not reset during SW_SYS_RST. Need to reset that manually. */ -const uint8_t esp32_reset_stub_code[] = { +static const uint8_t esp32_reset_stub_code[] = { #include "../../../contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc" }; @@ -387,7 +175,8 @@ static int esp32_soc_reset(struct target *target) LOG_DEBUG("Resuming the target"); xtensa = target_to_xtensa(target); xtensa->suppress_dsr_errors = true; - res = xtensa_resume(target, 0, ESP32_RTC_SLOW_MEM_BASE + 4, 0, 0); + res = xtensa_resume(target, false, ESP32_RTC_SLOW_MEM_BASE + 4, false, + false); xtensa->suppress_dsr_errors = false; if (res != ERROR_OK) { LOG_ERROR("Failed to run stub (%d)!", res); @@ -403,7 +192,8 @@ static int esp32_soc_reset(struct target *target) alive_sleep(10); xtensa_poll(target); if (timeval_ms() >= timeout) { - LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state); + LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s", + target_state_name(target)); get_timeout = true; break; } @@ -465,7 +255,10 @@ static int esp32_disable_wdts(struct target *target) static int esp32_on_halt(struct target *target) { - return esp32_disable_wdts(target); + int ret = esp32_disable_wdts(target); + if (ret == ERROR_OK) + ret = esp_xtensa_smp_on_halt(target); + return ret; } static int esp32_arch_state(struct target *target) @@ -483,7 +276,6 @@ static int esp32_virt2phys(struct target *target, return ERROR_FAIL; } - /* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin * can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the * esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to @@ -530,7 +322,11 @@ static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = { .on_halt = esp32_on_halt }; -static int esp32_target_create(struct target *target, Jim_Interp *interp) +static const struct esp_semihost_ops esp32_semihost_ops = { + .prepare = esp32_disable_wdts +}; + +static int esp32_target_create(struct target *target) { struct xtensa_debug_module_config esp32_dm_cfg = { .dbg_ops = &esp32_dbg_ops, @@ -546,8 +342,8 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; } - int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg, - &esp32_dm_cfg, &esp32_chip_ops); + int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, + &esp32_dm_cfg, &esp32_chip_ops, &esp32_semihost_ops); if (ret != ERROR_OK) { LOG_ERROR("Failed to init arch info!"); free(esp32); @@ -561,7 +357,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp) return ERROR_OK; } -COMMAND_HELPER(esp32_cmd_flashbootstrap_do, struct esp32_common *esp32) +static COMMAND_HELPER(esp32_cmd_flashbootstrap_do, struct esp32_common *esp32) { int state = -1; @@ -636,6 +432,11 @@ static const struct command_registration esp32_command_handlers[] = { { .chain = esp_xtensa_smp_command_handlers, }, + { + .name = "esp", + .usage = "", + .chain = esp32_apptrace_command_handlers, + }, { .name = "esp32", .usage = "", @@ -646,6 +447,13 @@ static const struct command_registration esp32_command_handlers[] = { .usage = "", .chain = esp32_any_command_handlers, }, + { + .name = "arm", + .mode = COMMAND_ANY, + .help = "ARM Command Group", + .usage = "", + .chain = semihosting_common_handlers + }, COMMAND_REGISTRATION_DONE }; @@ -677,6 +485,10 @@ struct target_type esp32_target = { .get_gdb_arch = xtensa_get_gdb_arch, .get_gdb_reg_list = xtensa_get_gdb_reg_list, + .run_algorithm = xtensa_run_algorithm, + .start_algorithm = xtensa_start_algorithm, + .wait_algorithm = xtensa_wait_algorithm, + .add_breakpoint = esp_xtensa_breakpoint_add, .remove_breakpoint = esp_xtensa_breakpoint_remove, diff --git a/src/target/espressif/esp32.h b/src/target/espressif/esp32.h deleted file mode 100644 index f07c08d41c..0000000000 --- a/src/target/espressif/esp32.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * ESP32 target for OpenOCD * - * Copyright (C) 2017 Espressif Systems Ltd. * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_ESP32_H -#define OPENOCD_TARGET_ESP32_H - -#include <target/xtensa/xtensa_regs.h> - -#define ESP32_DROM_LOW 0x3F400000 -#define ESP32_DROM_HIGH 0x3F800000 -#define ESP32_IROM_LOW 0x400D0000 -#define ESP32_IROM_HIGH 0x40400000 - -/* Number of registers returned directly by the G command - * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */ -#define ESP32_NUM_REGS_G_COMMAND 105 - -enum esp32_reg_id { - /* chip specific registers that extend ISA go after ISA-defined ones */ - ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START, - ESP32_REG_IDX_F64R_LO, - ESP32_REG_IDX_F64R_HI, - ESP32_REG_IDX_F64S, - ESP32_NUM_REGS, -}; - -#endif /* OPENOCD_TARGET_ESP32_H */ diff --git a/src/target/espressif/esp32_apptrace.c b/src/target/espressif/esp32_apptrace.c new file mode 100644 index 0000000000..307096019a --- /dev/null +++ b/src/target/espressif/esp32_apptrace.c @@ -0,0 +1,1635 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * ESP32xx application tracing module for OpenOCD * + * Copyright (C) 2017 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_ARPA_INET_H +#include <arpa/inet.h> +#endif + +#ifdef HAVE_NETDB_H +#include <netdb.h> +#endif + +#ifndef _WIN32 +#include <netinet/tcp.h> +#include <sys/ioctl.h> +#endif + +#include <helper/list.h> +#include <helper/time_support.h> +#include <target/target.h> +#include <target/target_type.h> +#include <target/smp.h> +#include <server/server.h> +#include "esp_xtensa.h" +#include "esp_xtensa_smp.h" +#include "esp_xtensa_apptrace.h" +#include "esp32_apptrace.h" +#include "esp32_sysview.h" +#include "segger_sysview.h" + +#define ESP32_APPTRACE_USER_BLOCK_CORE(_v_) ((_v_) >> 15) +#define ESP32_APPTRACE_USER_BLOCK_LEN(_v_) ((_v_) & ~BIT(15)) + +#define ESP32_APPTRACE_USER_BLOCK_HDR_SZ 4 + +#define ESP_APPTRACE_CMD_MODE_GEN 0 +#define ESP_APPTRACE_CMD_MODE_SYSVIEW 1 +#define ESP_APPTRACE_CMD_MODE_SYSVIEW_MCORE 2 +#define ESP_APPTRACE_CMD_MODE_SYNC 3 + +#define ESP32_APPTRACE_TGT_STATE_TMO 5000 +#define ESP_APPTRACE_BLOCKS_POOL_SZ 10 + +struct esp32_apptrace_dest_file_data { + int fout; +}; + +struct esp32_apptrace_dest_tcp_data { + int sockfd; +}; + +struct esp32_apptrace_target_state { + int running; + uint32_t block_id; + uint32_t data_len; +}; + +struct esp_apptrace_target2host_hdr { + uint16_t block_sz; + uint16_t wr_sz; +}; +#define APPTRACE_BLOCK_SIZE_OFFSET 0 +#define APPTRACE_WR_SIZE_OFFSET 2 + +struct esp32_apptrace_block { + struct list_head node; + uint8_t *data; + uint32_t data_len; +}; + +static int esp32_apptrace_data_processor(void *priv); +static int esp32_apptrace_get_data_info(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_target_state *target_state, + uint32_t *fired_target_num); +static int esp32_apptrace_safe_halt_targets(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_target_state *targets); +static struct esp32_apptrace_block *esp32_apptrace_free_block_get(struct esp32_apptrace_cmd_ctx *ctx); +static int esp32_apptrace_handle_trace_block(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_block *block); +static int esp32_sysview_start(struct esp32_apptrace_cmd_ctx *ctx); +static int esp32_sysview_stop(struct esp32_apptrace_cmd_ctx *ctx); + +static const bool s_time_stats_enable = true; + +/********************************************************************* +* Trace destination API +**********************************************************************/ + +static int esp32_apptrace_file_dest_write(void *priv, uint8_t *data, int size) +{ + struct esp32_apptrace_dest_file_data *dest_data = (struct esp32_apptrace_dest_file_data *)priv; + + int wr_sz = write(dest_data->fout, data, size); + if (wr_sz != size) { + LOG_ERROR("Failed to write %d bytes to out file (%d)! Written %d.", size, errno, wr_sz); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int esp32_apptrace_file_dest_cleanup(void *priv) +{ + struct esp32_apptrace_dest_file_data *dest_data = (struct esp32_apptrace_dest_file_data *)priv; + + if (dest_data->fout > 0) + close(dest_data->fout); + free(dest_data); + return ERROR_OK; +} + +static int esp32_apptrace_file_dest_init(struct esp32_apptrace_dest *dest, const char *dest_name) +{ + struct esp32_apptrace_dest_file_data *dest_data = calloc(1, sizeof(*dest_data)); + if (!dest_data) { + LOG_ERROR("Failed to alloc mem for file dest!"); + return ERROR_FAIL; + } + + LOG_INFO("Open file %s", dest_name); + dest_data->fout = open(dest_name, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, 0666); + if (dest_data->fout <= 0) { + LOG_ERROR("Failed to open file %s", dest_name); + free(dest_data); + return ERROR_FAIL; + } + + dest->priv = dest_data; + dest->write = esp32_apptrace_file_dest_write; + dest->clean = esp32_apptrace_file_dest_cleanup; + dest->log_progress = true; + + return ERROR_OK; +} + +static int esp32_apptrace_console_dest_write(void *priv, uint8_t *data, int size) +{ + LOG_USER_N("%.*s", size, data); + return ERROR_OK; +} + +static int esp32_apptrace_console_dest_cleanup(void *priv) +{ + return ERROR_OK; +} + +static int esp32_apptrace_console_dest_init(struct esp32_apptrace_dest *dest, const char *dest_name) +{ + dest->priv = NULL; + dest->write = esp32_apptrace_console_dest_write; + dest->clean = esp32_apptrace_console_dest_cleanup; + dest->log_progress = false; + + return ERROR_OK; +} + +static int esp32_apptrace_tcp_dest_write(void *priv, uint8_t *data, int size) +{ + struct esp32_apptrace_dest_tcp_data *dest_data = (struct esp32_apptrace_dest_tcp_data *)priv; + int wr_sz = write_socket(dest_data->sockfd, data, size); + if (wr_sz != size) { + LOG_ERROR("Failed to write %u bytes to out socket (%d)! Written %d.", size, errno, wr_sz); + return ERROR_FAIL; + } + return ERROR_OK; +} + +static int esp32_apptrace_tcp_dest_cleanup(void *priv) +{ + struct esp32_apptrace_dest_tcp_data *dest_data = (struct esp32_apptrace_dest_tcp_data *)priv; + + if (dest_data->sockfd > 0) + close_socket(dest_data->sockfd); + free(dest_data); + return ERROR_OK; +} + +static int esp32_apptrace_tcp_dest_init(struct esp32_apptrace_dest *dest, const char *dest_name) +{ + const char *port_sep = strchr(dest_name, ':'); + /* separator not found, or was the first or the last character */ + if (!port_sep || port_sep == dest_name || port_sep == dest_name + strlen(dest_name) - 1) { + LOG_ERROR("apptrace: Invalid connection URI, format should be tcp://host:port"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + size_t hostname_len = port_sep - dest_name; + + char hostname[64] = { 0 }; + if (hostname_len >= sizeof(hostname)) { + LOG_ERROR("apptrace: Hostname too long"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + memcpy(hostname, dest_name, hostname_len); + + const char *port_str = port_sep + 1; + struct addrinfo *ai; + int flags = 0; +#ifdef AI_NUMERICSERV + flags |= AI_NUMERICSERV; +#endif /* AI_NUMERICSERV */ + struct addrinfo hint = { + .ai_family = AF_UNSPEC, + .ai_socktype = SOCK_STREAM, + .ai_protocol = 0, + .ai_flags = flags + }; + int res = getaddrinfo(hostname, port_str, &hint, &ai); + if (res != 0) { + LOG_ERROR("apptrace: Failed to resolve host name: %s", hostname); + return ERROR_FAIL; + } + int sockfd = -1; + for (struct addrinfo *ai_it = ai; ai_it; ai_it = ai_it->ai_next) { + sockfd = socket(ai_it->ai_family, ai_it->ai_socktype, ai_it->ai_protocol); + if (sockfd < 0) { + LOG_DEBUG("apptrace: Failed to create socket (%d, %d, %d) (%s)", + ai_it->ai_family, + ai_it->ai_socktype, + ai_it->ai_protocol, + strerror(errno)); + continue; + } + + char cur_hostname[NI_MAXHOST]; + char cur_portname[NI_MAXSERV]; + res = + getnameinfo(ai_it->ai_addr, ai_it->ai_addrlen, cur_hostname, + sizeof(cur_hostname), + cur_portname, sizeof(cur_portname), + NI_NUMERICHOST | NI_NUMERICSERV); + if (res != 0) + continue; + + LOG_INFO("apptrace: Trying to connect to %s:%s", cur_hostname, cur_portname); + if (connect(sockfd, ai_it->ai_addr, ai_it->ai_addrlen) < 0) { + close_socket(sockfd); + sockfd = -1; + LOG_WARNING("apptrace: Connection failed (%s)", strerror(errno)); + continue; + } + break; + } + freeaddrinfo(ai); + if (sockfd < 0) { + LOG_ERROR("apptrace: Could not connect to %s:%s", hostname, port_str); + return ERROR_FAIL; + } + LOG_INFO("apptrace: Connected!"); + + struct esp32_apptrace_dest_tcp_data *dest_data = calloc(1, sizeof(struct esp32_apptrace_dest_tcp_data)); + if (!dest_data) { + LOG_ERROR("apptrace: Failed to alloc mem for tcp dest!"); + close_socket(sockfd); + return ERROR_FAIL; + } + + dest_data->sockfd = sockfd; + dest->priv = dest_data; + dest->write = esp32_apptrace_tcp_dest_write; + dest->clean = esp32_apptrace_tcp_dest_cleanup; + dest->log_progress = true; + + return ERROR_OK; +} + +int esp32_apptrace_dest_init(struct esp32_apptrace_dest dest[], const char *dest_paths[], unsigned int max_dests) +{ + int res; + unsigned int i; + + for (i = 0; i < max_dests; i++) { + if (strncmp(dest_paths[i], "file://", 7) == 0) + res = esp32_apptrace_file_dest_init(&dest[i], &dest_paths[i][7]); + else if (strncmp(dest_paths[i], "con:", 4) == 0) + res = esp32_apptrace_console_dest_init(&dest[i], NULL); + else if (strncmp(dest_paths[i], "tcp://", 6) == 0) + res = esp32_apptrace_tcp_dest_init(&dest[i], &dest_paths[i][6]); + else + break; + + if (res != ERROR_OK) { + LOG_ERROR("apptrace: Failed to init trace data destination '%s'!", dest_paths[i]); + return 0; + } + } + + return i; +} + +int esp32_apptrace_dest_cleanup(struct esp32_apptrace_dest dest[], unsigned int max_dests) +{ + for (unsigned int i = 0; i < max_dests; i++) { + if (dest[i].clean && dest[i].priv) { + int res = dest[i].clean(dest[i].priv); + dest[i].priv = NULL; + return res; + } + } + return ERROR_OK; +} + +/********************************************************************* +* Trace data blocks management API +**********************************************************************/ +static void esp32_apptrace_blocks_pool_cleanup(struct esp32_apptrace_cmd_ctx *ctx) +{ + struct esp32_apptrace_block *cur; + struct list_head *head = &ctx->free_trace_blocks; + struct list_head *tmp, *pos; + + list_for_each_safe(pos, tmp, head) { + cur = list_entry(pos, struct esp32_apptrace_block, node); + if (cur) { + list_del(&cur->node); + free(cur->data); + free(cur); + } + } + + head = &ctx->ready_trace_blocks; + + list_for_each_safe(pos, tmp, head) { + cur = list_entry(pos, struct esp32_apptrace_block, node); + if (cur) { + list_del(&cur->node); + free(cur->data); + free(cur); + } + } +} + +struct esp32_apptrace_block *esp32_apptrace_free_block_get(struct esp32_apptrace_cmd_ctx *ctx) +{ + struct esp32_apptrace_block *block = NULL; + + if (!list_empty(&ctx->free_trace_blocks)) { + /*get first */ + block = list_first_entry(&ctx->free_trace_blocks, struct esp32_apptrace_block, node); + list_del(&block->node); + } + + return block; +} + +static int esp32_apptrace_ready_block_put(struct esp32_apptrace_cmd_ctx *ctx, struct esp32_apptrace_block *block) +{ + LOG_DEBUG("esp32_apptrace_ready_block_put"); + /* add to ready blocks list */ + INIT_LIST_HEAD(&block->node); + list_add(&block->node, &ctx->ready_trace_blocks); + + return ERROR_OK; +} + +static struct esp32_apptrace_block *esp32_apptrace_ready_block_get(struct esp32_apptrace_cmd_ctx *ctx) +{ + if (list_empty(&ctx->ready_trace_blocks)) + return NULL; + + struct esp32_apptrace_block *block = + list_last_entry(&ctx->ready_trace_blocks, struct esp32_apptrace_block, node); + + /* remove it from ready list */ + list_del(&block->node); + + return block; +} + +static int esp32_apptrace_block_free(struct esp32_apptrace_cmd_ctx *ctx, struct esp32_apptrace_block *block) +{ + /* add to free blocks list */ + INIT_LIST_HEAD(&block->node); + list_add(&block->node, &ctx->free_trace_blocks); + + return ERROR_OK; +} + +static int esp32_apptrace_wait_tracing_finished(struct esp32_apptrace_cmd_ctx *ctx) +{ + int64_t timeout = timeval_ms() + (LOG_LEVEL_IS(LOG_LVL_DEBUG) ? 70000 : 5000); + while (!list_empty(&ctx->ready_trace_blocks)) { + alive_sleep(100); + if (timeval_ms() >= timeout) { + LOG_ERROR("Failed to wait for pended trace blocks!"); + return ERROR_FAIL; + } + } + /* signal timer callback to stop */ + ctx->running = 0; + target_unregister_timer_callback(esp32_apptrace_data_processor, ctx); + return ERROR_OK; +} + +/********************************************************************* +* Trace commands +**********************************************************************/ + +int esp32_apptrace_cmd_ctx_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, struct command_invocation *cmd, int mode) +{ + struct target *target = get_current_target(CMD_CTX); + + memset(cmd_ctx, 0, sizeof(struct esp32_apptrace_cmd_ctx)); + cmd_ctx->target = target; + cmd_ctx->mode = mode; + cmd_ctx->target_state = target->state; + cmd_ctx->cmd = cmd; + + if (target->smp) { + struct target_list *head; + struct target *curr; + unsigned int i = 0; + cmd_ctx->cores_num = 0; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + if (i == ESP32_APPTRACE_MAX_CORES_NUM) { + command_print(cmd, "Too many cores configured! Max %d cores are supported.", + ESP32_APPTRACE_MAX_CORES_NUM); + return ERROR_FAIL; + } + if (!target_was_examined(curr)) + continue; + cmd_ctx->cores_num++; + cmd_ctx->cpus[i++] = curr; + } + } else { + cmd_ctx->cores_num = 1; + cmd_ctx->cpus[0] = target; + } + /* some relies on ESP32_APPTRACE_MAX_CORES_NUM + * TODO: remove that dependency */ + assert(cmd_ctx->cores_num <= ESP32_APPTRACE_MAX_CORES_NUM && "Too many cores number!"); + + struct xtensa *xtensa = target->arch_info; + if (xtensa->common_magic == XTENSA_COMMON_MAGIC) { + cmd_ctx->hw = target_to_esp_xtensa(target)->apptrace.hw; + } else { /* TODO: riscv is not supported yet */ + command_print(cmd, "Unsupported target arch 0x%X", xtensa->common_magic); + return ERROR_FAIL; + } + + cmd_ctx->max_trace_block_sz = cmd_ctx->hw->max_block_size_get(cmd_ctx->cpus[0]); + if (cmd_ctx->max_trace_block_sz == 0) { + command_print(cmd, "Failed to get max trace block size!"); + return ERROR_FAIL; + } + LOG_INFO("Total trace memory: %" PRIu32 " bytes", cmd_ctx->max_trace_block_sz); + + INIT_LIST_HEAD(&cmd_ctx->ready_trace_blocks); + INIT_LIST_HEAD(&cmd_ctx->free_trace_blocks); + for (unsigned int i = 0; i < ESP_APPTRACE_BLOCKS_POOL_SZ; i++) { + struct esp32_apptrace_block *block = calloc(1, sizeof(struct esp32_apptrace_block)); + if (!block) { + command_print(cmd, "Failed to alloc trace buffer entry!"); + esp32_apptrace_blocks_pool_cleanup(cmd_ctx); + return ERROR_FAIL; + } + block->data = malloc(cmd_ctx->max_trace_block_sz); + if (!block->data) { + free(block); + command_print(cmd, "Failed to alloc trace buffer %" PRIu32 " bytes!", cmd_ctx->max_trace_block_sz); + esp32_apptrace_blocks_pool_cleanup(cmd_ctx); + return ERROR_FAIL; + } + INIT_LIST_HEAD(&block->node); + list_add(&block->node, &cmd_ctx->free_trace_blocks); + } + + cmd_ctx->running = 1; + if (cmd_ctx->mode != ESP_APPTRACE_CMD_MODE_SYNC) { + int res = target_register_timer_callback(esp32_apptrace_data_processor, + 0, + TARGET_TIMER_TYPE_PERIODIC, + cmd_ctx); + if (res != ERROR_OK) { + command_print(cmd, "Failed to start trace data timer callback (%d)!", res); + esp32_apptrace_blocks_pool_cleanup(cmd_ctx); + return ERROR_FAIL; + } + } + + if (s_time_stats_enable) { + cmd_ctx->stats.min_blk_read_time = 1000000.0; + cmd_ctx->stats.min_blk_proc_time = 1000000.0; + } + if (duration_start(&cmd_ctx->idle_time) != 0) { + command_print(cmd, "Failed to start idle time measurement!"); + esp32_apptrace_cmd_ctx_cleanup(cmd_ctx); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +int esp32_apptrace_cmd_ctx_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx) +{ + esp32_apptrace_blocks_pool_cleanup(cmd_ctx); + return ERROR_OK; +} + +#define ESP32_APPTRACE_CMD_NUM_ARG_CHECK(_cmd_, _arg_, _start_, _end_) \ + do { \ + if ((_arg_) == 0 && (_start_) == (_end_)) { \ + command_print(_cmd_, "Invalid '" # _arg_ "' arg!"); \ + return; \ + } \ + } while (0) + +void esp32_apptrace_cmd_args_parse(struct esp32_apptrace_cmd_ctx *cmd_ctx, + struct esp32_apptrace_cmd_data *cmd_data, + const char **argv, + int argc) +{ + char *end; + + cmd_data->poll_period = strtoul(argv[0], &end, 10); + ESP32_APPTRACE_CMD_NUM_ARG_CHECK(cmd_ctx->cmd, cmd_data->poll_period, argv[0], end); + if (argc > 1) { + cmd_data->max_len = strtoul(argv[1], &end, 10); + ESP32_APPTRACE_CMD_NUM_ARG_CHECK(cmd_ctx->cmd, cmd_data->max_len, argv[1], end); + if (argc > 2) { + int32_t tmo = strtol(argv[2], &end, 10); + ESP32_APPTRACE_CMD_NUM_ARG_CHECK(cmd_ctx->cmd, tmo, argv[2], end); + cmd_ctx->stop_tmo = 1.0 * tmo; + if (argc > 3) { + cmd_data->wait4halt = strtoul(argv[3], &end, 10); + ESP32_APPTRACE_CMD_NUM_ARG_CHECK(cmd_ctx->cmd, cmd_data->wait4halt, argv[3], end); + if (argc > 4) { + cmd_data->skip_len = strtoul(argv[4], &end, 10); + ESP32_APPTRACE_CMD_NUM_ARG_CHECK(cmd_ctx->cmd, cmd_data->skip_len, argv[4], end); + } + } + } + } +} + +static int esp32_apptrace_core_id_get(struct target *target, uint8_t *hdr_buf) +{ + return ESP32_APPTRACE_USER_BLOCK_CORE(target_buffer_get_u16(target, hdr_buf + APPTRACE_BLOCK_SIZE_OFFSET)); +} + +static uint32_t esp32_apptrace_usr_block_len_get(struct target *target, uint8_t *hdr_buf, uint32_t *wr_len) +{ + *wr_len = ESP32_APPTRACE_USER_BLOCK_LEN(target_buffer_get_u16(target, hdr_buf + APPTRACE_WR_SIZE_OFFSET)); + return ESP32_APPTRACE_USER_BLOCK_LEN(target_buffer_get_u16(target, hdr_buf + APPTRACE_BLOCK_SIZE_OFFSET)); +} + +static int esp32_apptrace_cmd_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, + struct command_invocation *cmd, + int mode, + const char **argv, + int argc) +{ + struct esp32_apptrace_cmd_data *cmd_data; + + if (argc < 1) { + command_print(cmd, "Not enough args! Need trace data destination!"); + return ERROR_FAIL; + } + + int res = esp32_apptrace_cmd_ctx_init(cmd_ctx, cmd, mode); + if (res != ERROR_OK) + return res; + + cmd_data = calloc(1, sizeof(*cmd_data)); + assert(cmd_data && "No memory for command data!"); + cmd_ctx->cmd_priv = cmd_data; + + /*outfile1 [poll_period [trace_size [stop_tmo [wait4halt [skip_size]]]]] */ + res = esp32_apptrace_dest_init(&cmd_data->data_dest, argv, 1); + if (res != 1) { /* only one destination needs to be initialized */ + command_print(cmd, "Wrong args! Needs a trace data destination!"); + free(cmd_data); + goto on_error; + } + cmd_ctx->stop_tmo = -1.0; /* infinite */ + cmd_data->max_len = UINT32_MAX; + cmd_data->poll_period = 0 /*ms*/; + if (argc > 1) + /* parse remaining args */ + esp32_apptrace_cmd_args_parse(cmd_ctx, cmd_data, &argv[1], argc - 1); + + LOG_USER("App trace params: from %d cores, size %" PRId32 " bytes, stop_tmo %g s, poll period %" PRId32 + " ms, wait_rst %d, skip %" PRId32 " bytes", cmd_ctx->cores_num, + cmd_data->max_len, + cmd_ctx->stop_tmo, + cmd_data->poll_period, + cmd_data->wait4halt, + cmd_data->skip_len); + + cmd_ctx->trace_format.hdr_sz = ESP32_APPTRACE_USER_BLOCK_HDR_SZ; + cmd_ctx->trace_format.core_id_get = esp32_apptrace_core_id_get; + cmd_ctx->trace_format.usr_block_len_get = esp32_apptrace_usr_block_len_get; + return ERROR_OK; +on_error: + command_print(cmd, "Not enough args! Need %d trace data destinations!", cmd_ctx->cores_num); + cmd_ctx->running = 0; + esp32_apptrace_cmd_ctx_cleanup(cmd_ctx); + return res; +} + +static int esp32_apptrace_cmd_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx) +{ + struct esp32_apptrace_cmd_data *cmd_data = cmd_ctx->cmd_priv; + + esp32_apptrace_dest_cleanup(&cmd_data->data_dest, 1); + free(cmd_data); + cmd_ctx->cmd_priv = NULL; + esp32_apptrace_cmd_ctx_cleanup(cmd_ctx); + return ERROR_OK; +} + +static void esp32_apptrace_print_stats(struct esp32_apptrace_cmd_ctx *ctx) +{ + struct esp32_apptrace_cmd_data *cmd_data = ctx->cmd_priv; + uint32_t trace_sz = 0; + + if (cmd_data) + trace_sz = ctx->tot_len > cmd_data->skip_len ? ctx->tot_len - cmd_data->skip_len : 0; + LOG_USER("Tracing is %s. Size is %" PRId32 " of %" PRId32 " @ %f (%f) KiB/s", + !ctx->running ? "STOPPED" : "RUNNING", + trace_sz, + cmd_data ? cmd_data->max_len : 0, + duration_kbps(&ctx->read_time, ctx->tot_len), + duration_kbps(&ctx->read_time, ctx->raw_tot_len)); + LOG_USER("Data: blocks incomplete %" PRId32 ", lost bytes: %" PRId32, + ctx->stats.incompl_blocks, + ctx->stats.lost_bytes); + if (s_time_stats_enable) { + LOG_USER("Block read time [%f..%f] ms", + 1000 * ctx->stats.min_blk_read_time, + 1000 * ctx->stats.max_blk_read_time); + LOG_USER("Block proc time [%f..%f] ms", + 1000 * ctx->stats.min_blk_proc_time, + 1000 * ctx->stats.max_blk_proc_time); + } +} + +static int esp32_apptrace_wait4halt(struct esp32_apptrace_cmd_ctx *ctx, struct target *target) +{ + LOG_USER("Wait for halt..."); + while (!openocd_is_shutdown_pending()) { + int res = target_poll(target); + if (res != ERROR_OK) + return res; + if (target->state == TARGET_HALTED) { + LOG_TARGET_USER(target, "HALTED"); + break; + } + alive_sleep(500); + } + return ERROR_OK; +} + +int esp32_apptrace_safe_halt_targets(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_target_state *targets) +{ + int res = ERROR_OK; + + memset(targets, 0, ctx->cores_num * sizeof(struct esp32_apptrace_target_state)); + /* halt all CPUs */ + LOG_DEBUG("Halt all targets!"); + for (unsigned int k = 0; k < ctx->cores_num; k++) { + if (!target_was_examined(ctx->cpus[k])) + continue; + if (ctx->cpus[k]->state == TARGET_HALTED) + continue; + res = target_halt(ctx->cpus[k]); + if (res != ERROR_OK) { + LOG_ERROR("Failed to halt target (%d)!", res); + return res; + } + res = target_wait_state(ctx->cpus[k], TARGET_HALTED, ESP32_APPTRACE_TGT_STATE_TMO); + if (res != ERROR_OK) { + LOG_ERROR("Failed to wait halt target %s / %d (%d)!", + target_name(ctx->cpus[k]), + ctx->cpus[k]->state, + res); + return res; + } + } + /* read current block statuses from CPUs */ + LOG_DEBUG("Read current block statuses"); + for (unsigned int k = 0; k < ctx->cores_num; k++) { + uint32_t stat; + res = ctx->hw->status_reg_read(ctx->cpus[k], &stat); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read trace status (%d)!", res); + return res; + } + /* check if some CPU stopped inside tracing regs update critical section */ + if (stat) { + if (ctx->hw->leave_trace_crit_section_start) { + res = ctx->hw->leave_trace_crit_section_start(ctx->cpus[k]); + if (res != ERROR_OK) + return res; + } + uint32_t bp_addr = stat; + res = breakpoint_add(ctx->cpus[k], bp_addr, 1, BKPT_HARD); + if (res != ERROR_OK) { + LOG_ERROR("Failed to set breakpoint (%d)!", res); + return res; + } + while (stat) { + /* allow this CPU to leave ERI write critical section */ + res = target_resume(ctx->cpus[k], true, 0, true, false); + if (res != ERROR_OK) { + LOG_ERROR("Failed to resume target (%d)!", res); + breakpoint_remove(ctx->cpus[k], bp_addr); + return res; + } + /* wait for CPU to be halted on BP */ + enum target_debug_reason debug_reason = DBG_REASON_UNDEFINED; + while (debug_reason != DBG_REASON_BREAKPOINT) { + res = target_wait_state(ctx->cpus[k], TARGET_HALTED, + ESP32_APPTRACE_TGT_STATE_TMO); + if (res != ERROR_OK) { + LOG_ERROR("Failed to wait halt on bp (%d)!", res); + breakpoint_remove(ctx->cpus[k], bp_addr); + return res; + } + debug_reason = ctx->cpus[k]->debug_reason; + } + res = ctx->hw->status_reg_read(ctx->cpus[k], &stat); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read trace status (%d)!", res); + breakpoint_remove(ctx->cpus[k], bp_addr); + return res; + } + } + breakpoint_remove(ctx->cpus[k], bp_addr); + if (ctx->hw->leave_trace_crit_section_stop) { + res = ctx->hw->leave_trace_crit_section_stop(ctx->cpus[k]); + if (res != ERROR_OK) + return res; + } + } + res = ctx->hw->data_len_read(ctx->cpus[k], &targets[k].block_id, &targets[k].data_len); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read trace status (%d)!", res); + return res; + } + } + + return ERROR_OK; +} + +static int esp32_apptrace_connect_targets(struct esp32_apptrace_cmd_ctx *ctx, + bool conn, + bool resume_target) +{ + struct esp32_apptrace_target_state target_to_connect[ESP32_APPTRACE_MAX_CORES_NUM]; + + if (conn) + LOG_USER("Connect targets..."); + else + LOG_USER("Disconnect targets..."); + + int res = esp32_apptrace_safe_halt_targets(ctx, target_to_connect); + if (res != ERROR_OK) { + command_print(ctx->cmd, "Failed to halt targets (%d)!", res); + return res; + } + if (ctx->cores_num > 1) { + /* set block ids to the highest value */ + uint32_t max_id = 0; + for (unsigned int k = 0; k < ctx->cores_num; k++) { + if (target_to_connect[k].block_id > max_id) + max_id = target_to_connect[k].block_id; + } + for (unsigned int k = 0; k < ctx->cores_num; k++) + target_to_connect[k].block_id = max_id; + } + for (unsigned int k = 0; k < ctx->cores_num; k++) { + /* update host connected status */ + res = ctx->hw->ctrl_reg_write(ctx->cpus[k], + target_to_connect[k].block_id, + 0 /*ack target data*/, + conn, + false /*no host data*/); + if (res != ERROR_OK) { + command_print(ctx->cmd, "Failed to read trace status (%d)!", res); + return res; + } + } + if (resume_target) { + LOG_DEBUG("Resume targets"); + bool smp_resumed = false; + for (unsigned int k = 0; k < ctx->cores_num; k++) { + if (smp_resumed && ctx->cpus[k]->smp) { + /* in SMP mode we need to call target_resume for one core only */ + continue; + } + res = target_resume(ctx->cpus[k], true, 0, true, false); + if (res != ERROR_OK) { + command_print(ctx->cmd, "Failed to resume target (%d)!", res); + return res; + } + if (ctx->cpus[k]->smp) + smp_resumed = true; + } + } + if (conn) + LOG_INFO("Targets connected."); + else + LOG_INFO("Targets disconnected."); + return ERROR_OK; +} + +int esp_apptrace_usr_block_write(const struct esp32_apptrace_hw *hw, struct target *target, + uint32_t block_id, + const uint8_t *data, + uint32_t size) +{ + struct esp_apptrace_host2target_hdr hdr = { .block_sz = size }; + uint32_t buf_sz[2] = { sizeof(hdr), size }; + const uint8_t *bufs[2] = { (const uint8_t *)&hdr, data }; + + if (size > hw->usr_block_max_size_get(target)) { + LOG_ERROR("Too large user block %" PRId32, size); + return ERROR_FAIL; + } + + return hw->buffs_write(target, + ARRAY_SIZE(buf_sz), + buf_sz, + bufs, + block_id, + true /*ack target data*/, + true /*host data*/); +} + +static uint32_t esp32_apptrace_usr_block_check(struct esp32_apptrace_cmd_ctx *ctx, uint8_t *hdr_buf) +{ + uint32_t wr_len = 0; + uint32_t usr_len = ctx->trace_format.usr_block_len_get(ctx->target, hdr_buf, &wr_len); + if (usr_len != wr_len) { + LOG_ERROR("Incomplete block sz %" PRId32 ", wr %" PRId32, usr_len, wr_len); + ctx->stats.incompl_blocks++; + ctx->stats.lost_bytes += usr_len - wr_len; + } + return usr_len; +} + +int esp32_apptrace_get_data_info(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_target_state *target_state, + uint32_t *fired_target_num) +{ + if (fired_target_num) + *fired_target_num = UINT32_MAX; + + for (unsigned int i = 0; i < ctx->cores_num; i++) { + int res = ctx->hw->data_len_read(ctx->cpus[i], &target_state[i].block_id, &target_state[i].data_len); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read data len on (%s)!", target_name(ctx->cpus[i])); + return res; + } + if (target_state[i].data_len) { + LOG_TARGET_DEBUG(ctx->cpus[i], "Block %" PRId32 ", len %" PRId32 " bytes on fired", + target_state[i].block_id, target_state[i].data_len); + if (fired_target_num) + *fired_target_num = i; + break; + } + } + return ERROR_OK; +} + +static int esp32_apptrace_process_data(struct esp32_apptrace_cmd_ctx *ctx, + unsigned int core_id, + uint8_t *data, + uint32_t data_len) +{ + struct esp32_apptrace_cmd_data *cmd_data = ctx->cmd_priv; + + LOG_DEBUG("Got block %" PRId32 " bytes [%x %x...%x %x]", data_len, data[12], data[13], + data[data_len - 2], data[data_len - 1]); + if (ctx->tot_len + data_len > cmd_data->skip_len) { + uint32_t wr_idx = 0, wr_chunk_len = data_len; + if (ctx->tot_len < cmd_data->skip_len) { + wr_chunk_len = (ctx->tot_len + wr_chunk_len) - cmd_data->skip_len; + wr_idx = cmd_data->skip_len - ctx->tot_len; + } + if (ctx->tot_len + wr_chunk_len > cmd_data->max_len) + wr_chunk_len -= (ctx->tot_len + wr_chunk_len - cmd_data->skip_len) - cmd_data->max_len; + if (wr_chunk_len > 0) { + int res = cmd_data->data_dest.write(cmd_data->data_dest.priv, data + wr_idx, wr_chunk_len); + if (res != ERROR_OK) { + LOG_ERROR("Failed to write %" PRId32 " bytes to dest 0!", data_len); + return res; + } + } + ctx->tot_len += wr_chunk_len; + } else { + ctx->tot_len += data_len; + } + + if (cmd_data->data_dest.log_progress) + LOG_USER("%" PRId32 " ", ctx->tot_len); + /* check for stop condition */ + if (ctx->tot_len > cmd_data->skip_len && (ctx->tot_len - cmd_data->skip_len >= cmd_data->max_len)) { + ctx->running = 0; + if (duration_measure(&ctx->read_time) != 0) { + LOG_ERROR("Failed to stop trace read time measure!"); + return ERROR_FAIL; + } + } + return ERROR_OK; +} + +static int esp32_apptrace_handle_trace_block(struct esp32_apptrace_cmd_ctx *ctx, + struct esp32_apptrace_block *block) +{ + uint32_t processed = 0; + uint32_t hdr_sz = ctx->trace_format.hdr_sz; + + LOG_DEBUG("Got block %" PRId32 " bytes", block->data_len); + /* process user blocks one by one */ + while (processed < block->data_len) { + LOG_DEBUG("Process usr block %" PRId32 "/%" PRId32, processed, block->data_len); + /* process user block */ + uint32_t usr_len = esp32_apptrace_usr_block_check(ctx, block->data + processed); + int core_id = ctx->trace_format.core_id_get(ctx->target, block->data + processed); + /* process user data */ + int res = ctx->process_data(ctx, core_id, block->data + processed + hdr_sz, usr_len); + if (res != ERROR_OK) { + LOG_ERROR("Failed to process %" PRId32 " bytes!", usr_len); + return res; + } + processed += usr_len + hdr_sz; + } + return ERROR_OK; +} + +static int esp32_apptrace_data_processor(void *priv) +{ + struct esp32_apptrace_cmd_ctx *ctx = (struct esp32_apptrace_cmd_ctx *)priv; + + if (!ctx->running) + return ERROR_OK; + + struct esp32_apptrace_block *block = esp32_apptrace_ready_block_get(ctx); + if (!block) + return ERROR_OK; + + int res = esp32_apptrace_handle_trace_block(ctx, block); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_ERROR("Failed to process trace block %" PRId32 " bytes!", block->data_len); + return res; + } + res = esp32_apptrace_block_free(ctx, block); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_ERROR("Failed to free ready block!"); + return res; + } + + return ERROR_OK; +} + +static int esp32_apptrace_check_connection(struct esp32_apptrace_cmd_ctx *ctx) +{ + if (!ctx) + return ERROR_FAIL; + + unsigned int busy_target_num = 0; + + for (unsigned int i = 0; i < ctx->cores_num; i++) { + bool conn = true; + int res = ctx->hw->ctrl_reg_read(ctx->cpus[i], NULL, NULL, &conn); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read apptrace control reg for cpu(%d) res(%d)!", i, res); + return res; + } + if (!conn) { + uint32_t stat = 0; + LOG_TARGET_WARNING(ctx->cpus[i], "apptrace connection is lost. Re-connect."); + res = ctx->hw->status_reg_read(ctx->cpus[i], &stat); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read trace status (%d)!", res); + return res; + } + if (stat) { + LOG_TARGET_WARNING(ctx->cpus[i], "in critical state. Retry in next poll"); + if (++busy_target_num == ctx->cores_num) { + LOG_WARNING("No available core"); + return ERROR_WAIT; + } + continue; + } + res = ctx->hw->ctrl_reg_write(ctx->cpus[i], + 0, + 0, + true /*host connected*/, + false /*no host data*/); + if (res != ERROR_OK) { + LOG_ERROR("Failed to write apptrace control reg for cpu(%d) res(%d)!", i, res); + return res; + } + if (ctx->stop_tmo != -1.0) { + /* re-start idle time measurement */ + if (duration_start(&ctx->idle_time) != 0) { + LOG_ERROR("Failed to re-start idle time measure!"); + return ERROR_FAIL; + } + } + } + } + + return ERROR_OK; +} + +static int esp32_apptrace_poll(void *priv) +{ + struct esp32_apptrace_cmd_ctx *ctx = (struct esp32_apptrace_cmd_ctx *)priv; + int res; + uint32_t fired_target_num = 0; + struct esp32_apptrace_target_state target_state[ESP32_APPTRACE_MAX_CORES_NUM]; + struct duration blk_proc_time; + + if (!ctx->running) { + if (ctx->auto_clean) + ctx->auto_clean(ctx); + return ERROR_FAIL; + } + + /* Check for connection is alive.For some reason target and therefore host_connected flag + * might have been reset */ + res = esp32_apptrace_check_connection(ctx); + if (res != ERROR_OK) { + if (res != ERROR_WAIT) + ctx->running = 0; + return res; + } + + /* check for data from target */ + res = esp32_apptrace_get_data_info(ctx, target_state, &fired_target_num); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_ERROR("Failed to read data len!"); + return res; + } + /* LOG_DEBUG("Block %d (%d bytes) on target (%s)!", target_state[0].block_id, + * target_state[0].data_len, target_name(ctx->cpus[0])); */ + if (fired_target_num == UINT32_MAX) { + /* no data has been received, but block could be switched due to the data transferred + * from host to target */ + if (ctx->cores_num > 1) { + uint32_t max_block_id = 0, min_block_id = ctx->hw->max_block_id; + /* find maximum block ID and set the same ID in control reg for both cores + * */ + for (unsigned int i = 0; i < ctx->cores_num; i++) { + if (max_block_id < target_state[i].block_id) + max_block_id = target_state[i].block_id; + if (min_block_id > target_state[i].block_id) + min_block_id = target_state[i].block_id; + } + /* handle block ID overflow */ + if (max_block_id == ctx->hw->max_block_id && min_block_id == 0) + max_block_id = 0; + for (unsigned int i = 0; i < ctx->cores_num; i++) { + if (max_block_id != target_state[i].block_id) { + LOG_TARGET_DEBUG(ctx->cpus[i], "Ack empty block %" PRId32 "!", max_block_id); + res = ctx->hw->ctrl_reg_write(ctx->cpus[i], + max_block_id, + 0 /*all read*/, + true /*host connected*/, + false /*no host data*/); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_TARGET_ERROR(ctx->cpus[i], "Failed to ack empty data block!"); + return res; + } + } + } + ctx->last_blk_id = max_block_id; + } + if (ctx->stop_tmo != -1.0) { + if (duration_measure(&ctx->idle_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to measure idle time!"); + return ERROR_FAIL; + } + if (duration_elapsed(&ctx->idle_time) >= ctx->stop_tmo) { + ctx->running = 0; + LOG_ERROR("Data timeout!"); + return ERROR_FAIL; + } + } + return ERROR_OK;/* no data */ + } + /* sanity check */ + if (target_state[fired_target_num].data_len > ctx->max_trace_block_sz) { + ctx->running = 0; + LOG_ERROR("Too large block size %" PRId32 "!", target_state[fired_target_num].data_len); + return ERROR_FAIL; + } + if (ctx->tot_len == 0) { + if (duration_start(&ctx->read_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to start trace read time measurement!"); + return ERROR_FAIL; + } + } + struct esp32_apptrace_block *block = esp32_apptrace_free_block_get(ctx); + if (!block) { + ctx->running = 0; + LOG_TARGET_ERROR(ctx->cpus[fired_target_num], "Failed to get free block for data!"); + return ERROR_FAIL; + } + if (s_time_stats_enable) { + /* read block */ + if (duration_start(&blk_proc_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to start block read time measurement!"); + return ERROR_FAIL; + } + } + res = ctx->hw->data_read(ctx->cpus[fired_target_num], target_state[fired_target_num].data_len, block->data, + target_state[fired_target_num].block_id, + /* do not ack target data in sync mode, + esp32_apptrace_handle_trace_block() can write response data and will do ack thereafter */ + ctx->mode != ESP_APPTRACE_CMD_MODE_SYNC); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_TARGET_ERROR(ctx->cpus[fired_target_num], "Failed to read data!"); + return res; + } + ctx->last_blk_id = target_state[fired_target_num].block_id; + block->data_len = target_state[fired_target_num].data_len; + ctx->raw_tot_len += block->data_len; + if (s_time_stats_enable) { + if (duration_measure(&blk_proc_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to measure block read time!"); + return ERROR_FAIL; + } + /* update stats */ + float brt = duration_elapsed(&blk_proc_time); + if (brt > ctx->stats.max_blk_read_time) + ctx->stats.max_blk_read_time = brt; + if (brt < ctx->stats.min_blk_read_time) + ctx->stats.min_blk_read_time = brt; + + if (duration_start(&blk_proc_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to start block proc time measurement!"); + return ERROR_FAIL; + } + } + /* in sync mode do not ack target data on other cores, esp32_apptrace_handle_trace_block() can write response + * data and will do ack thereafter */ + if (ctx->mode != ESP_APPTRACE_CMD_MODE_SYNC) { + for (unsigned int i = 0; i < ctx->cores_num; i++) { + if (i == fired_target_num) + continue; + res = ctx->hw->ctrl_reg_write(ctx->cpus[i], + ctx->last_blk_id, + 0 /*all read*/, + true /*host connected*/, + false /*no host data*/); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_TARGET_ERROR(ctx->cpus[i], "Failed to ack data!"); + return res; + } + LOG_TARGET_DEBUG(ctx->cpus[i], "Ack block %" PRId32, ctx->last_blk_id); + } + res = esp32_apptrace_ready_block_put(ctx, block); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_TARGET_ERROR(ctx->cpus[fired_target_num], "Failed to put ready block of data!"); + return res; + } + } else { + res = esp32_apptrace_handle_trace_block(ctx, block); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_ERROR("Failed to process trace block %" PRId32 " bytes!", block->data_len); + return res; + } + res = esp32_apptrace_block_free(ctx, block); + if (res != ERROR_OK) { + ctx->running = 0; + LOG_ERROR("Failed to free ready block!"); + return res; + } + } + if (ctx->stop_tmo != -1.0) { + /* start idle time measurement */ + if (duration_start(&ctx->idle_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to start idle time measure!"); + return ERROR_FAIL; + } + } + if (s_time_stats_enable) { + if (duration_measure(&blk_proc_time) != 0) { + ctx->running = 0; + LOG_ERROR("Failed to stop block proc time measure!"); + return ERROR_FAIL; + } + /* update stats */ + float bt = duration_elapsed(&blk_proc_time); + if (bt > ctx->stats.max_blk_proc_time) + ctx->stats.max_blk_proc_time = bt; + if (bt < ctx->stats.min_blk_proc_time) + ctx->stats.min_blk_proc_time = bt; + } + return ERROR_OK; +} + +static inline bool is_sysview_mode(int mode) +{ + return mode == ESP_APPTRACE_CMD_MODE_SYSVIEW || mode == ESP_APPTRACE_CMD_MODE_SYSVIEW_MCORE; +} + +static void esp32_apptrace_cmd_stop(struct esp32_apptrace_cmd_ctx *ctx) +{ + if (duration_measure(&ctx->read_time) != 0) + LOG_ERROR("Failed to stop trace read time measurement!"); + int res = target_unregister_timer_callback(esp32_apptrace_poll, ctx); + if (res != ERROR_OK) + LOG_ERROR("Failed to unregister target timer handler (%d)!", res); + if (is_sysview_mode(ctx->mode)) { + /* stop tracing */ + res = esp32_sysview_stop(ctx); + if (res != ERROR_OK) + LOG_ERROR("sysview: Failed to stop tracing!"); + } + /* data processor is alive, so wait for all received blocks to be processed */ + res = esp32_apptrace_wait_tracing_finished(ctx); + if (res != ERROR_OK) + LOG_ERROR("Failed to wait for pended blocks (%d)!", res); + res = esp32_apptrace_connect_targets(ctx, false, ctx->target_state == TARGET_RUNNING); + if (res != ERROR_OK) + LOG_ERROR("Failed to disconnect targets (%d)!", res); + esp32_apptrace_print_stats(ctx); + res = esp32_apptrace_cmd_cleanup(ctx); + if (res != ERROR_OK) + LOG_ERROR("Failed to cleanup cmd ctx (%d)!", res); +} + +/* this function must be called after connecting to targets */ +static int esp32_sysview_start(struct esp32_apptrace_cmd_ctx *ctx) +{ + uint8_t cmds[] = { SEGGER_SYSVIEW_COMMAND_ID_START }; + uint32_t fired_target_num = 0; + struct esp32_apptrace_target_state target_state[ESP32_APPTRACE_MAX_CORES_NUM] = {{0}}; + struct esp32_sysview_cmd_data *cmd_data = ctx->cmd_priv; + + /* get current block id */ + int res = esp32_apptrace_get_data_info(ctx, target_state, &fired_target_num); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to read target data info!"); + return res; + } + if (fired_target_num == UINT32_MAX) { + /* it can happen that there is no pending target data, but block was switched + * in this case block_ids on both CPUs are equal, so select the first one */ + fired_target_num = 0; + } + /* start tracing */ + res = esp_apptrace_usr_block_write(ctx->hw, ctx->cpus[fired_target_num], target_state[fired_target_num].block_id, + cmds, sizeof(cmds)); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to start tracing!"); + return res; + } + cmd_data->sv_trace_running = 1; + return res; +} + +static int esp32_sysview_stop(struct esp32_apptrace_cmd_ctx *ctx) +{ + uint32_t old_block_id, fired_target_num = 0, empty_target_num = 0; + struct esp32_apptrace_target_state target_state[ESP32_APPTRACE_MAX_CORES_NUM]; + struct esp32_sysview_cmd_data *cmd_data = ctx->cmd_priv; + uint8_t cmds[] = { SEGGER_SYSVIEW_COMMAND_ID_STOP }; + struct duration wait_time; + + struct esp32_apptrace_block *block = esp32_apptrace_free_block_get(ctx); + if (!block) { + LOG_ERROR("Failed to get free block for data on (%s)!", target_name(ctx->cpus[fired_target_num])); + return ERROR_FAIL; + } + + /* halt all CPUs (not only one), otherwise it can happen that there is no target data and + * while we are queueing commands another CPU switches tracing block */ + int res = esp32_apptrace_safe_halt_targets(ctx, target_state); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to halt targets (%d)!", res); + return res; + } + /* it can happen that there is no pending target data + * in this case block_ids on both CPUs are equal, so the first one will be selected */ + for (unsigned int k = 0; k < ctx->cores_num; k++) { + if (target_state[k].data_len) { + fired_target_num = k; + break; + } + } + if (target_state[fired_target_num].data_len) { + /* read pending data without ack, they will be acked when stop command is queued */ + res = ctx->hw->data_read(ctx->cpus[fired_target_num], target_state[fired_target_num].data_len, block->data, + target_state[fired_target_num].block_id, + false /*no ack target data*/); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to read data on (%s)!", target_name(ctx->cpus[fired_target_num])); + return res; + } + /* process data */ + block->data_len = target_state[fired_target_num].data_len; + res = esp32_apptrace_handle_trace_block(ctx, block); + if (res != ERROR_OK) { + LOG_ERROR("Failed to process trace block %" PRId32 " bytes!", block->data_len); + return res; + } + } + /* stop tracing and ack target data */ + res = esp_apptrace_usr_block_write(ctx->hw, ctx->cpus[fired_target_num], target_state[fired_target_num].block_id, + cmds, + sizeof(cmds)); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to stop tracing!"); + return res; + } + if (ctx->cores_num > 1) { + empty_target_num = fired_target_num ? 0 : 1; + /* ack target data on another CPU */ + res = ctx->hw->ctrl_reg_write(ctx->cpus[empty_target_num], target_state[fired_target_num].block_id, + 0 /*target data ack*/, + true /*host connected*/, + false /*no host data*/); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to ack data on target '%s' (%d)!", + target_name(ctx->cpus[empty_target_num]), res); + return res; + } + } + /* resume targets to allow command processing */ + LOG_INFO("Resume targets"); + bool smp_resumed = false; + for (unsigned int k = 0; k < ctx->cores_num; k++) { + if (smp_resumed && ctx->cpus[k]->smp) { + /* in SMP mode we need to call target_resume for one core only */ + continue; + } + res = target_resume(ctx->cpus[k], true, 0, true, false); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to resume target '%s' (%d)!", target_name(ctx->cpus[k]), res); + return res; + } + if (ctx->cpus[k]->smp) + smp_resumed = true; + } + /* wait for block switch (command sent), so we can disconnect from targets */ + old_block_id = target_state[fired_target_num].block_id; + if (duration_start(&wait_time) != 0) { + LOG_ERROR("Failed to start trace stop timeout measurement!"); + return ERROR_FAIL; + } + /* we are waiting for the last data from tracing block and also there can be data in the pended + * data buffer */ + /* so we are expecting two TRX block switches at most or stopping due to timeout */ + while (cmd_data->sv_trace_running) { + res = esp32_apptrace_get_data_info(ctx, target_state, &fired_target_num); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to read targets data info!"); + return res; + } + if (fired_target_num == UINT32_MAX) { + /* it can happen that there is no pending (last) target data, but block was + * switched */ + /* in this case block_ids on both CPUs are equal, so select the first one */ + fired_target_num = 0; + } + if (target_state[fired_target_num].block_id != old_block_id) { + if (target_state[fired_target_num].data_len) { + /* read last data and ack them */ + res = ctx->hw->data_read(ctx->cpus[fired_target_num], + target_state[fired_target_num].data_len, + block->data, + target_state[fired_target_num].block_id, + true /*ack target data*/); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to read last data on (%s)!", target_name(ctx->cpus[fired_target_num])); + } else { + if (ctx->cores_num > 1) { + /* ack target data on another CPU */ + empty_target_num = fired_target_num ? 0 : 1; + res = ctx->hw->ctrl_reg_write(ctx->cpus[empty_target_num], + target_state[fired_target_num].block_id, + 0 /*all read*/, + true /*host connected*/, + false /*no host data*/); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to ack data on target '%s' (%d)!", + target_name(ctx->cpus[empty_target_num]), res); + return res; + } + } + /* process data */ + block->data_len = target_state[fired_target_num].data_len; + res = esp32_apptrace_handle_trace_block(ctx, block); + if (res != ERROR_OK) { + LOG_ERROR("Failed to process trace block %" PRId32 " bytes!", + block->data_len); + return res; + } + } + old_block_id = target_state[fired_target_num].block_id; + } + } + if (duration_measure(&wait_time) != 0) { + LOG_ERROR("Failed to start trace stop timeout measurement!"); + return ERROR_FAIL; + } + const float stop_tmo = LOG_LEVEL_IS(LOG_LVL_DEBUG) ? 30.0 : 0.5; + if (duration_elapsed(&wait_time) >= stop_tmo) { + LOG_INFO("Stop waiting for the last data due to timeout."); + break; + } + } + return res; +} + +static int esp32_cmd_apptrace_generic(struct command_invocation *cmd, int mode, const char **argv, int argc) +{ + static struct esp32_apptrace_cmd_ctx s_at_cmd_ctx; + struct esp32_apptrace_cmd_data *cmd_data; + int res = ERROR_FAIL; + enum target_state old_state; + struct target *target = get_current_target(CMD_CTX); + + if (argc < 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* command can be invoked on unexamined core, if so find examined one */ + if (target->smp && !target_was_examined(target)) { + struct target_list *head; + struct target *curr; + LOG_WARNING("Current target '%s' was not examined!", target_name(target)); + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + if (target_was_examined(curr)) { + target = curr; + LOG_WARNING("Run command on target '%s'", target_name(target)); + break; + } + } + } + old_state = target->state; + + if (strcmp(argv[0], "start") == 0) { + if (is_sysview_mode(mode)) { + /* init cmd context */ + res = esp32_sysview_cmd_init(&s_at_cmd_ctx, + cmd, + mode, + mode == ESP_APPTRACE_CMD_MODE_SYSVIEW_MCORE, + &argv[1], + argc - 1); + if (res != ERROR_OK) { + command_print(cmd, "Failed to init cmd ctx (%d)!", res); + return res; + } + cmd_data = s_at_cmd_ctx.cmd_priv; + if (cmd_data->skip_len != 0) { + s_at_cmd_ctx.running = 0; + esp32_sysview_cmd_cleanup(&s_at_cmd_ctx); + command_print(cmd, "Data skipping not supported!"); + return ERROR_FAIL; + } + s_at_cmd_ctx.process_data = esp32_sysview_process_data; + } else { + res = esp32_apptrace_cmd_init(&s_at_cmd_ctx, + cmd, + mode, + &argv[1], + argc - 1); + if (res != ERROR_OK) { + command_print(cmd, "Failed to init cmd ctx (%d)!", res); + return res; + } + cmd_data = s_at_cmd_ctx.cmd_priv; + s_at_cmd_ctx.process_data = esp32_apptrace_process_data; + } + s_at_cmd_ctx.auto_clean = esp32_apptrace_cmd_stop; + if (cmd_data->wait4halt) { + res = esp32_apptrace_wait4halt(&s_at_cmd_ctx, target); + if (res != ERROR_OK) { + command_print(cmd, "Failed to wait for halt target (%d)!", res); + goto _on_start_error; + } + } + res = esp32_apptrace_connect_targets(&s_at_cmd_ctx, true, old_state == TARGET_RUNNING); + if (res != ERROR_OK) { + command_print(cmd, "Failed to connect to targets (%d)!", res); + goto _on_start_error; + } + if (is_sysview_mode(mode)) { + /* start tracing */ + res = esp32_sysview_start(&s_at_cmd_ctx); + if (res != ERROR_OK) { + esp32_apptrace_connect_targets(&s_at_cmd_ctx, false, old_state == TARGET_RUNNING); + s_at_cmd_ctx.running = 0; + esp32_apptrace_cmd_cleanup(&s_at_cmd_ctx); + command_print(cmd, "sysview: Failed to start tracing!"); + return res; + } + } + res = target_register_timer_callback(esp32_apptrace_poll, + cmd_data->poll_period, + TARGET_TIMER_TYPE_PERIODIC, + &s_at_cmd_ctx); + if (res != ERROR_OK) { + command_print(cmd, "Failed to register target timer handler (%d)!", res); + goto _on_start_error; + } + } else if (strcmp(argv[0], "stop") == 0) { + if (!s_at_cmd_ctx.running) { + command_print(cmd, "Tracing is not running!"); + return ERROR_FAIL; + } + esp32_apptrace_cmd_stop(&s_at_cmd_ctx); + return ERROR_OK; + } else if (strcmp(argv[0], "status") == 0) { + if (s_at_cmd_ctx.running && duration_measure(&s_at_cmd_ctx.read_time) != 0) + LOG_ERROR("Failed to measure trace read time!"); + esp32_apptrace_print_stats(&s_at_cmd_ctx); + return ERROR_OK; + } else if (strcmp(argv[0], "dump") == 0) { + if (is_sysview_mode(mode)) { + command_print(cmd, "Not supported!"); + return ERROR_FAIL; + } + /* [dump outfile] - post-mortem dump without connection to targets */ + res = esp32_apptrace_cmd_init(&s_at_cmd_ctx, + cmd, + mode, + &argv[1], + argc - 1); + if (res != ERROR_OK) { + command_print(cmd, "Failed to init cmd ctx (%d)!", res); + return res; + } + s_at_cmd_ctx.stop_tmo = 0.01; /* use small stop tmo */ + s_at_cmd_ctx.process_data = esp32_apptrace_process_data; + /* check for exit signal and command completion */ + while (!openocd_is_shutdown_pending() && s_at_cmd_ctx.running) { + res = esp32_apptrace_poll(&s_at_cmd_ctx); + if (res != ERROR_OK) { + LOG_ERROR("Failed to poll target for trace data (%d)!", res); + break; + } + /* let registered timer callbacks to run */ + target_call_timer_callbacks(); + } + if (s_at_cmd_ctx.running) { + /* data processor is alive, so wait for all received blocks to be processed */ + res = esp32_apptrace_wait_tracing_finished(&s_at_cmd_ctx); + if (res != ERROR_OK) + LOG_ERROR("Failed to wait for pended blocks (%d)!", res); + } + esp32_apptrace_print_stats(&s_at_cmd_ctx); + res = esp32_apptrace_cmd_cleanup(&s_at_cmd_ctx); + if (res != ERROR_OK) + command_print(cmd, "Failed to cleanup cmd ctx (%d)!", res); + } else { + command_print(cmd, "Invalid action '%s'!", argv[0]); + } + + return res; + +_on_start_error: + s_at_cmd_ctx.running = 0; + if (is_sysview_mode(mode)) + esp32_sysview_cmd_cleanup(&s_at_cmd_ctx); + else + esp32_apptrace_cmd_cleanup(&s_at_cmd_ctx); + return res; +} + +COMMAND_HANDLER(esp32_cmd_apptrace) +{ + return esp32_cmd_apptrace_generic(CMD, ESP_APPTRACE_CMD_MODE_GEN, CMD_ARGV, CMD_ARGC); +} + +COMMAND_HANDLER(esp32_cmd_sysview) +{ + return esp32_cmd_apptrace_generic(CMD, ESP_APPTRACE_CMD_MODE_SYSVIEW, CMD_ARGV, CMD_ARGC); +} + +COMMAND_HANDLER(esp32_cmd_sysview_mcore) +{ + return esp32_cmd_apptrace_generic(CMD, ESP_APPTRACE_CMD_MODE_SYSVIEW_MCORE, CMD_ARGV, CMD_ARGC); +} + +const struct command_registration esp32_apptrace_command_handlers[] = { + { + .name = "apptrace", + .handler = esp32_cmd_apptrace, + .mode = COMMAND_EXEC, + .help = + "App Tracing: application level trace control. Starts, stops or queries tracing process status.", + .usage = + "(start <destination> [poll_period [trace_size [stop_tmo [wait4halt [skip_size]]]]) | (stop) | (status) | (dump <destination>)", + }, + { + .name = "sysview", + .handler = esp32_cmd_sysview, + .mode = COMMAND_EXEC, + .help = + "App Tracing: SEGGER SystemView compatible trace control. Starts, stops or queries tracing process status.", + .usage = + "(start file://<outfile1> [file://<outfile2>] [poll_period [trace_size [stop_tmo [wait4halt [skip_size]]]]) | (stop) | (status)", + }, + { + .name = "sysview_mcore", + .handler = esp32_cmd_sysview_mcore, + .mode = COMMAND_EXEC, + .help = + "App Tracing: Espressif multi-core SystemView trace control. Starts, stops or queries tracing process status.", + .usage = + "(start file://<outfile> [poll_period [trace_size [stop_tmo [wait4halt [skip_size]]]]) | (stop) | (status)", + }, + COMMAND_REGISTRATION_DONE +}; diff --git a/src/target/espressif/esp32_apptrace.h b/src/target/espressif/esp32_apptrace.h new file mode 100644 index 0000000000..3873342226 --- /dev/null +++ b/src/target/espressif/esp32_apptrace.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * ESP32 application trace module * + * Copyright (C) 2017-2019 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP32_APPTRACE_H +#define OPENOCD_TARGET_ESP32_APPTRACE_H + +#include <helper/command.h> +#include <helper/time_support.h> +#include <target/target.h> + +#define ESP32_APPTRACE_MAX_CORES_NUM 2 + +struct esp32_apptrace_hw { + uint32_t max_block_id; + uint32_t (*max_block_size_get)(struct target *target); + int (*status_reg_read)(struct target *target, uint32_t *stat); + int (*ctrl_reg_write)(struct target *target, + uint32_t block_id, + uint32_t len, + bool conn, + bool data); + int (*ctrl_reg_read)(struct target *target, + uint32_t *block_id, + uint32_t *len, + bool *conn); + int (*data_len_read)(struct target *target, + uint32_t *block_id, + uint32_t *len); + int (*data_read)(struct target *target, + uint32_t size, + uint8_t *buffer, + uint32_t block_id, + bool ack); + uint32_t (*usr_block_max_size_get)(struct target *target); + int (*buffs_write)(struct target *target, + uint32_t bufs_num, + uint32_t buf_sz[], + const uint8_t *bufs[], + uint32_t block_id, + bool ack, + bool data); + int (*leave_trace_crit_section_start)(struct target *target); + int (*leave_trace_crit_section_stop)(struct target *target); +}; + +struct esp_apptrace_host2target_hdr { + uint16_t block_sz; +}; + +struct esp32_apptrace_dest { + void *priv; + int (*write)(void *priv, uint8_t *data, int size); + int (*clean)(void *priv); + bool log_progress; +}; + +struct esp32_apptrace_format { + uint32_t hdr_sz; + int (*core_id_get)(struct target *target, uint8_t *hdr_buf); + uint32_t (*usr_block_len_get)(struct target *target, uint8_t *hdr_buf, uint32_t *wr_len); +}; + +struct esp32_apptrace_cmd_stats { + uint32_t incompl_blocks; + uint32_t lost_bytes; + float min_blk_read_time; + float max_blk_read_time; + float min_blk_proc_time; + float max_blk_proc_time; +}; + +struct esp32_apptrace_cmd_ctx { + volatile int running; + int mode; + /* TODO: use subtargets from target arch info */ + struct target *cpus[ESP32_APPTRACE_MAX_CORES_NUM]; + /* TODO: use cores num from target */ + unsigned int cores_num; + const struct esp32_apptrace_hw *hw; + enum target_state target_state; + uint32_t last_blk_id; + struct list_head free_trace_blocks; + struct list_head ready_trace_blocks; + uint32_t max_trace_block_sz; + struct esp32_apptrace_format trace_format; + int (*process_data)(struct esp32_apptrace_cmd_ctx *ctx, unsigned int core_id, uint8_t *data, uint32_t data_len); + void (*auto_clean)(struct esp32_apptrace_cmd_ctx *ctx); + uint32_t tot_len; + uint32_t raw_tot_len; + float stop_tmo; + struct esp32_apptrace_cmd_stats stats; + struct duration read_time; + struct duration idle_time; + void *cmd_priv; + struct target *target; + struct command_invocation *cmd; +}; + +struct esp32_apptrace_cmd_data { + struct esp32_apptrace_dest data_dest; + uint32_t poll_period; + uint32_t max_len; + uint32_t skip_len; + bool wait4halt; +}; + +int esp32_apptrace_cmd_ctx_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, struct command_invocation *cmd, int mode); +int esp32_apptrace_cmd_ctx_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx); +void esp32_apptrace_cmd_args_parse(struct esp32_apptrace_cmd_ctx *cmd_ctx, + struct esp32_apptrace_cmd_data *cmd_data, + const char **argv, + int argc); +int esp32_apptrace_dest_init(struct esp32_apptrace_dest dest[], const char *dest_paths[], unsigned int max_dests); +int esp32_apptrace_dest_cleanup(struct esp32_apptrace_dest dest[], unsigned int max_dests); +int esp_apptrace_usr_block_write(const struct esp32_apptrace_hw *hw, struct target *target, + uint32_t block_id, + const uint8_t *data, + uint32_t size); + +extern const struct command_registration esp32_apptrace_command_handlers[]; + +#endif /* OPENOCD_TARGET_ESP32_APPTRACE_H */ diff --git a/src/target/espressif/esp32_sysview.c b/src/target/espressif/esp32_sysview.c new file mode 100644 index 0000000000..2fe2157780 --- /dev/null +++ b/src/target/espressif/esp32_sysview.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * ESP32 sysview tracing module * + * Copyright (C) 2020 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/log.h> +#include "esp32_apptrace.h" +#include "esp32_sysview.h" +#include "segger_sysview.h" + +/* in SystemView mode core ID is passed in event ID field */ +#define ESP32_SYSVIEW_USER_BLOCK_CORE(_v_) (0) /* not used */ +#define ESP32_SYSVIEW_USER_BLOCK_LEN(_v_) (_v_) +#define ESP32_SYSVIEW_USER_BLOCK_HDR_SZ 2 + +struct esp_sysview_target2host_hdr { + uint8_t block_sz; + uint8_t wr_sz; +}; +#define SYSVIEW_BLOCK_SIZE_OFFSET 0 +#define SYSVIEW_WR_SIZE_OFFSET 1 + +static int esp_sysview_trace_header_write(struct esp32_apptrace_cmd_ctx *ctx, bool mcore_format); +static int esp32_sysview_core_id_get(struct target *target, uint8_t *hdr_buf); +static uint32_t esp32_sysview_usr_block_len_get(struct target *target, uint8_t *hdr_buf, uint32_t *wr_len); + +int esp32_sysview_cmd_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, + struct command_invocation *cmd, + int mode, + bool mcore_format, + const char **argv, + int argc) +{ + struct esp32_sysview_cmd_data *cmd_data; + + if (argc < 1) { + command_print(cmd, "Not enough args! Need trace data destination!"); + return ERROR_FAIL; + } + + int res = esp32_apptrace_cmd_ctx_init(cmd_ctx, cmd, mode); + if (res != ERROR_OK) + return res; + + int core_num = cmd_ctx->cores_num; + + if (!mcore_format && argc < core_num) { + command_print(cmd, "Not enough args! Need %d trace data destinations!", core_num); + res = ERROR_FAIL; + goto on_error; + } + + cmd_data = calloc(1, sizeof(*cmd_data)); + if (!cmd_data) { + command_print(cmd, "No memory for command data!"); + res = ERROR_FAIL; + goto on_error; + } + cmd_ctx->cmd_priv = cmd_data; + cmd_data->mcore_format = mcore_format; + + /*outfile1 [outfile2] [poll_period [trace_size [stop_tmo [wait4halt [skip_size]]]]] */ + int dests_num = esp32_apptrace_dest_init(cmd_data->data_dests, argv, !mcore_format ? core_num : 1); + if (!mcore_format && dests_num < core_num) { + command_print(cmd, "Not enough args! Need %d trace data destinations!", core_num); + free(cmd_data); + res = ERROR_FAIL; + goto on_error; + } + cmd_data->apptrace.max_len = UINT32_MAX; + cmd_data->apptrace.poll_period = 0 /*ms*/; + cmd_ctx->stop_tmo = -1.0; /* infinite */ + if (argc > dests_num) { + /* parse remaining args */ + esp32_apptrace_cmd_args_parse(cmd_ctx, + &cmd_data->apptrace, + &argv[dests_num], + argc - dests_num); + } + LOG_USER("App trace params: from %d cores, size %u bytes, stop_tmo %g s, " + "poll period %u ms, wait_rst %d, skip %u bytes", + cmd_ctx->cores_num, + cmd_data->apptrace.max_len, + cmd_ctx->stop_tmo, + cmd_data->apptrace.poll_period, + cmd_data->apptrace.wait4halt, + cmd_data->apptrace.skip_len); + + cmd_ctx->trace_format.hdr_sz = ESP32_SYSVIEW_USER_BLOCK_HDR_SZ; + cmd_ctx->trace_format.core_id_get = esp32_sysview_core_id_get; + cmd_ctx->trace_format.usr_block_len_get = esp32_sysview_usr_block_len_get; + + res = esp_sysview_trace_header_write(cmd_ctx, mcore_format); + if (res != ERROR_OK) { + command_print(cmd, "Failed to write trace header (%d)!", res); + esp32_apptrace_dest_cleanup(cmd_data->data_dests, core_num); + free(cmd_data); + return res; + } + return ERROR_OK; +on_error: + cmd_ctx->running = 0; + esp32_apptrace_cmd_ctx_cleanup(cmd_ctx); + return res; +} + +int esp32_sysview_cmd_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx) +{ + struct esp32_sysview_cmd_data *cmd_data = cmd_ctx->cmd_priv; + + esp32_apptrace_dest_cleanup(cmd_data->data_dests, cmd_ctx->cores_num); + free(cmd_data); + cmd_ctx->cmd_priv = NULL; + esp32_apptrace_cmd_ctx_cleanup(cmd_ctx); + return ERROR_OK; +} + +static int esp32_sysview_core_id_get(struct target *target, uint8_t *hdr_buf) +{ + /* for sysview compressed apptrace header is used, so core id is encoded in sysview packet */ + return 0; +} + +static uint32_t esp32_sysview_usr_block_len_get(struct target *target, uint8_t *hdr_buf, uint32_t *wr_len) +{ + *wr_len = ESP32_SYSVIEW_USER_BLOCK_LEN(hdr_buf[SYSVIEW_WR_SIZE_OFFSET]); + return ESP32_SYSVIEW_USER_BLOCK_LEN(hdr_buf[SYSVIEW_BLOCK_SIZE_OFFSET]); +} + +static int esp_sysview_trace_header_write(struct esp32_apptrace_cmd_ctx *ctx, bool mcore_format) +{ + struct esp32_sysview_cmd_data *cmd_data = ctx->cmd_priv; + char *hdr_str; + int dests_num; + + if (!mcore_format) { + hdr_str = ";\n" + "; Version " SYSVIEW_MIN_VER_STRING "\n" + "; Author Espressif Inc\n" + ";\n"; + dests_num = ctx->cores_num; + } else { + hdr_str = ";\n" + "; Version " SYSVIEW_MIN_VER_STRING "\n" + "; Author Espressif Inc\n" + "; ESP_Extension\n" + ";\n"; + dests_num = 1; + } + + int hdr_len = strlen(hdr_str); + for (int i = 0; i < dests_num; i++) { + int res = cmd_data->data_dests[i].write(cmd_data->data_dests[i].priv, + (uint8_t *)hdr_str, + hdr_len); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u bytes to dest %d!", hdr_len, i); + return ERROR_FAIL; + } + } + return ERROR_OK; +} + +static void sysview_encode_u32(uint8_t **dest, uint32_t val) +{ + uint8_t *sv_ptr = *dest; + while (val > 0x7F) { + *sv_ptr++ = (uint8_t)(val | 0x80); + val >>= 7; + } + *sv_ptr++ = (uint8_t)val; + *dest = sv_ptr; +} + +static uint32_t esp_sysview_decode_u32(uint8_t **ptr) +{ + uint32_t val = 0; + for (int k = 0;; k++, (*ptr)++) { + if (**ptr & 0x80) { + val |= (uint32_t)(**ptr & ~0x80) << 7 * k; + } else { + val |= (uint32_t)**ptr << 7 * k; + (*ptr)++; + break; + } + } + return val; +} + +static uint16_t esp_sysview_decode_plen(uint8_t **ptr) +{ + uint16_t payload_len = 0; + uint8_t *p = *ptr; + /* here pkt points to encoded payload length */ + if (*p & 0x80) { + payload_len = *(p + 1); /* higher part */ + payload_len = (payload_len << 7) | (*p & ~0x80);/* lower 7 bits */ + p += 2; /* payload len (2 bytes) */ + } else { + payload_len = *p; + p++; /* payload len (1 byte) */ + } + *ptr = p; + + return payload_len; +} + +static uint16_t esp_sysview_get_predef_payload_len(uint16_t id, uint8_t *pkt) +{ + uint16_t len; + uint8_t *ptr = pkt; + + switch (id) { + case SYSVIEW_EVTID_OVERFLOW: + case SYSVIEW_EVTID_ISR_ENTER: + case SYSVIEW_EVTID_TASK_START_EXEC: + case SYSVIEW_EVTID_TASK_START_READY: + case SYSVIEW_EVTID_TASK_CREATE: + case SYSVIEW_EVTID_SYSTIME_CYCLES: + case SYSVIEW_EVTID_USER_START: + case SYSVIEW_EVTID_USER_STOP: + case SYSVIEW_EVTID_TIMER_ENTER: + /*ENCODE_U32 */ + esp_sysview_decode_u32(&ptr); + len = ptr - pkt; + break; + case SYSVIEW_EVTID_TASK_STOP_READY: + case SYSVIEW_EVTID_SYSTIME_US: + /*2*ENCODE_U32 */ + esp_sysview_decode_u32(&ptr); + esp_sysview_decode_u32(&ptr); + len = ptr - pkt; + break; + case SYSVIEW_EVTID_SYSDESC: + /*str(128 + 1) */ + len = *ptr + 1; + break; + case SYSVIEW_EVTID_TASK_INFO: + case SYSVIEW_EVTID_MODULEDESC: + /*2*ENCODE_U32 + str */ + esp_sysview_decode_u32(&ptr); + esp_sysview_decode_u32(&ptr); + /* TODO: add support for strings longer then 255 bytes */ + len = ptr - pkt + *ptr + 1; + break; + case SYSVIEW_EVTID_STACK_INFO: + /*4*ENCODE_U32 */ + esp_sysview_decode_u32(&ptr); + esp_sysview_decode_u32(&ptr); + esp_sysview_decode_u32(&ptr); + esp_sysview_decode_u32(&ptr); + len = ptr - pkt; + break; + case SYSVIEW_EVTID_ISR_EXIT: + case SYSVIEW_EVTID_TASK_STOP_EXEC: + case SYSVIEW_EVTID_TRACE_START: + case SYSVIEW_EVTID_TRACE_STOP: + case SYSVIEW_EVTID_IDLE: + case SYSVIEW_EVTID_ISR_TO_SCHEDULER: + case SYSVIEW_EVTID_TIMER_EXIT: + len = 0; + break; + + /*case SYSVIEW_EVTID_NOP: */ + default: + LOG_ERROR("sysview: Unsupported predef event %d!", id); + len = 0; + } + return len; +} + +static uint16_t esp_sysview_parse_packet(uint8_t *pkt_buf, + uint32_t *pkt_len, + unsigned int *pkt_core_id, + uint32_t *delta, + uint32_t *delta_len, + bool clear_core_bit) +{ + uint8_t *pkt = pkt_buf; + uint16_t event_id = 0, payload_len = 0; + + *pkt_core_id = 0; + *pkt_len = 0; + /* 1-2 byte of message type, 0-2 byte of payload length, payload, 1-5 bytes of timestamp. */ + if (*pkt & 0x80) { + if (*(pkt + 1) & (1 << 6)) { + if (clear_core_bit) + *(pkt + 1) &= ~(1 << 6); /* clear core_id bit */ + *pkt_core_id = 1; + } + event_id = *(pkt + 1) & ~(1 << 6); /* higher part */ + event_id = (event_id << 7) | (*pkt & ~0x80); /* lower 7 bits */ + pkt += 2; /* event_id (2 bytes) */ + /* here pkt points to encoded payload length */ + payload_len = esp_sysview_decode_plen(&pkt); + } else { + if (*pkt & (1 << 6)) { + if (clear_core_bit) + *pkt &= ~(1 << 6); /* clear core_id bit */ + *pkt_core_id = 1; + } + /* event_id (1 byte) */ + event_id = *pkt & ~(1 << 6); + pkt++; + if (event_id < 24) + payload_len = esp_sysview_get_predef_payload_len(event_id, pkt); + else + payload_len = esp_sysview_decode_plen(&pkt); + } + pkt += payload_len; + uint8_t *delta_start = pkt; + *delta = esp_sysview_decode_u32(&pkt); + *delta_len = pkt - delta_start; + *pkt_len = pkt - pkt_buf; + LOG_DEBUG("sysview: evt %d len %d plen %d dlen %d", + event_id, + *pkt_len, + payload_len, + *delta_len); + return event_id; +} + +static int esp32_sysview_write_packet(struct esp32_sysview_cmd_data *cmd_data, + int pkt_core_id, uint32_t pkt_len, uint8_t *pkt_buf, uint32_t delta_len, uint8_t *delta_buf) +{ + if (!cmd_data->data_dests[pkt_core_id].write) + return ERROR_FAIL; + + int res = cmd_data->data_dests[pkt_core_id].write(cmd_data->data_dests[pkt_core_id].priv, pkt_buf, pkt_len); + + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u bytes to dest %d!", pkt_len, pkt_core_id); + return res; + } + if (delta_len) { + /* write packet with modified delta */ + res = cmd_data->data_dests[pkt_core_id].write(cmd_data->data_dests[pkt_core_id].priv, delta_buf, delta_len); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u bytes of delta to dest %d!", delta_len, pkt_core_id); + return res; + } + } + return ERROR_OK; +} + +static int esp32_sysview_process_packet(struct esp32_apptrace_cmd_ctx *ctx, + unsigned int pkt_core_id, uint16_t event_id, uint32_t delta, uint32_t delta_len, + uint32_t pkt_len, uint8_t *pkt_buf) +{ + struct esp32_sysview_cmd_data *cmd_data = ctx->cmd_priv; + int pkt_core_changed = 0; + uint32_t new_delta_len = 0; + uint8_t new_delta_buf[10]; + uint32_t wr_len = pkt_len; + + if (ctx->cores_num > 1) { + if (cmd_data->sv_last_core_id == pkt_core_id) { + /* if this packet is for the same core as the prev one acc delta and write packet unmodified */ + cmd_data->sv_acc_time_delta += delta; + } else { + /* if this packet is for another core then prev one set acc delta to the packet's delta */ + uint8_t *delta_ptr = new_delta_buf; + sysview_encode_u32(&delta_ptr, delta + cmd_data->sv_acc_time_delta); + cmd_data->sv_acc_time_delta = delta; + wr_len -= delta_len; + new_delta_len = delta_ptr - new_delta_buf; + pkt_core_changed = 1; + } + cmd_data->sv_last_core_id = pkt_core_id; + } + if (pkt_core_id >= ctx->cores_num) { + LOG_WARNING("sysview: invalid core ID in packet %d, must be less then %d! Event id %d", + pkt_core_id, + ctx->cores_num, + event_id); + return ERROR_FAIL; + } + int res = esp32_sysview_write_packet(cmd_data, + pkt_core_id, + wr_len, + pkt_buf, + new_delta_len, + new_delta_buf); + if (res != ERROR_OK) + return res; + for (unsigned int i = 0; i < ctx->cores_num; i++) { + if (pkt_core_id == i) + continue; + switch (event_id) { + /* messages below should be sent to trace destinations for all cores */ + case SYSVIEW_EVTID_TRACE_START: + case SYSVIEW_EVTID_TRACE_STOP: + case SYSVIEW_EVTID_SYSTIME_CYCLES: + case SYSVIEW_EVTID_SYSTIME_US: + case SYSVIEW_EVTID_SYSDESC: + case SYSVIEW_EVTID_TASK_INFO: + case SYSVIEW_EVTID_STACK_INFO: + case SYSVIEW_EVTID_MODULEDESC: + case SYSVIEW_EVTID_INIT: + case SYSVIEW_EVTID_NUMMODULES: + case SYSVIEW_EVTID_OVERFLOW: + case SYSVIEW_EVTID_TASK_START_READY: + /* if packet's source core has changed */ + wr_len = pkt_len; + if (pkt_core_changed) { + /* clone packet with unmodified delta */ + new_delta_len = 0; + } else { + /* clone packet with modified delta */ + uint8_t *delta_ptr = new_delta_buf; + sysview_encode_u32(&delta_ptr, cmd_data->sv_acc_time_delta /*delta has been accumulated above*/); + wr_len -= delta_len; + new_delta_len = delta_ptr - new_delta_buf; + } + LOG_DEBUG("sysview: Redirect %d bytes of event %d to dest %d", wr_len, event_id, i); + res = esp32_sysview_write_packet(cmd_data, + i, + wr_len, + pkt_buf, + new_delta_len, + new_delta_buf); + if (res != ERROR_OK) + return res; + /* messages above are cloned to trace files for both cores, + * so reset acc time delta, both files have actual delta + * info */ + cmd_data->sv_acc_time_delta = 0; + break; + default: + break; + } + } + return ERROR_OK; +} + +int esp32_sysview_process_data(struct esp32_apptrace_cmd_ctx *ctx, + unsigned int core_id, + uint8_t *data, + uint32_t data_len) +{ + struct esp32_sysview_cmd_data *cmd_data = ctx->cmd_priv; + + LOG_DEBUG("sysview: Read from target %d bytes [%x %x %x %x]", + data_len, + data[0], + data[1], + data[2], + data[3]); + int res; + uint32_t processed = 0; + if (core_id >= ctx->cores_num) { + LOG_ERROR("sysview: Invalid core id %d in user block!", core_id); + return ERROR_FAIL; + } + if (cmd_data->mcore_format) + core_id = 0; + if (ctx->tot_len == 0) { + /* handle sync seq */ + if (data_len < SYSVIEW_SYNC_LEN) { + LOG_ERROR("sysview: Invalid init seq len %d!", data_len); + return ERROR_FAIL; + } + LOG_DEBUG("sysview: Process %d sync bytes", SYSVIEW_SYNC_LEN); + uint8_t sync_seq[SYSVIEW_SYNC_LEN] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + if (memcmp(data, sync_seq, SYSVIEW_SYNC_LEN) != 0) { + LOG_ERROR("sysview: Invalid init seq [%x %x %x %x %x %x %x %x %x %x]", + data[0], data[1], data[2], data[3], data[4], data[5], data[6], + data[7], data[8], data[9]); + return ERROR_FAIL; + } + res = cmd_data->data_dests[core_id].write(cmd_data->data_dests[core_id].priv, + data, + SYSVIEW_SYNC_LEN); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u sync bytes to dest %d!", + SYSVIEW_SYNC_LEN, + core_id); + return res; + } + if (!cmd_data->mcore_format) { + for (unsigned int i = 0; i < ctx->cores_num; i++) { + if (core_id == i) + continue; + res = + cmd_data->data_dests[i].write(cmd_data->data_dests[i].priv, + data, + SYSVIEW_SYNC_LEN); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u sync bytes to dest %d!", SYSVIEW_SYNC_LEN, core_id ? 0 : 1); + return res; + } + } + } + ctx->tot_len += SYSVIEW_SYNC_LEN; + processed += SYSVIEW_SYNC_LEN; + } + while (processed < data_len) { + unsigned int pkt_core_id; + uint32_t delta_len = 0; + uint32_t pkt_len = 0, delta = 0; + uint16_t event_id = esp_sysview_parse_packet(data + processed, + &pkt_len, + &pkt_core_id, + &delta, + &delta_len, + !cmd_data->mcore_format); + LOG_DEBUG("sysview: Process packet: core %d, %d id, %d bytes [%x %x %x %x]", + pkt_core_id, + event_id, + pkt_len, + data[processed + 0], + data[processed + 1], + data[processed + 2], + data[processed + 3]); + if (!cmd_data->mcore_format) { + res = esp32_sysview_process_packet(ctx, + pkt_core_id, + event_id, + delta, + delta_len, + pkt_len, + data + processed); + if (res != ERROR_OK) + return res; + } else { + res = cmd_data->data_dests[0].write(cmd_data->data_dests[0].priv, data + processed, pkt_len); + if (res != ERROR_OK) { + LOG_ERROR("sysview: Failed to write %u bytes to dest %d!", pkt_len, 0); + return res; + } + } + if (event_id == SYSVIEW_EVTID_TRACE_STOP) + cmd_data->sv_trace_running = 0; + ctx->tot_len += pkt_len; + processed += pkt_len; + } + LOG_USER("%u ", ctx->tot_len); + /* check for stop condition */ + if (ctx->tot_len > cmd_data->apptrace.skip_len && + (ctx->tot_len - cmd_data->apptrace.skip_len >= cmd_data->apptrace.max_len)) { + ctx->running = 0; + if (duration_measure(&ctx->read_time) != 0) { + LOG_ERROR("Failed to stop trace read time measure!"); + return ERROR_FAIL; + } + } + return ERROR_OK; +} diff --git a/src/target/espressif/esp32_sysview.h b/src/target/espressif/esp32_sysview.h new file mode 100644 index 0000000000..230ce46329 --- /dev/null +++ b/src/target/espressif/esp32_sysview.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * ESP32 sysview tracing module * + * Copyright (C) 2020 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP32_SYSVIEW_H +#define OPENOCD_TARGET_ESP32_SYSVIEW_H + +#include <stdint.h> +#include "esp32_apptrace.h" + +struct esp32_sysview_cmd_data { + /* Should be the first field. Generic apptrace command handling code accesses it */ + struct esp32_apptrace_cmd_data apptrace; + struct esp32_apptrace_dest data_dests[ESP32_APPTRACE_MAX_CORES_NUM]; + bool mcore_format; + uint32_t sv_acc_time_delta; + unsigned int sv_last_core_id; + int sv_trace_running; +}; + +struct esp32_apptrace_cmd_ctx; + +int esp32_sysview_cmd_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, + struct command_invocation *cmd, + int mode, + bool mcore_format, + const char **argv, + int argc); +int esp32_sysview_cmd_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx); +int esp32_sysview_process_data(struct esp32_apptrace_cmd_ctx *ctx, + unsigned int core_id, + uint8_t *data, + uint32_t data_len); + +#endif /* OPENOCD_TARGET_ESP32_SYSVIEW_H */ diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c index 4251e84c98..e32893a6b2 100644 --- a/src/target/espressif/esp32s2.c +++ b/src/target/espressif/esp32s2.c @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * ESP32-S2 target for OpenOCD * * Copyright (C) 2019 Espressif Systems Ltd. * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -14,36 +13,16 @@ #include "assert.h" #include <target/target.h> #include <target/target_type.h> +#include <target/semihosting_common.h> #include "esp_xtensa.h" -#include "esp32s2.h" - -/* Overall memory map - * TODO: read memory configuration from target registers */ -#define ESP32_S2_IROM_MASK_LOW 0x40000000 -#define ESP32_S2_IROM_MASK_HIGH 0x40020000 -#define ESP32_S2_IRAM_LOW 0x40020000 -#define ESP32_S2_IRAM_HIGH 0x40070000 -#define ESP32_S2_DRAM_LOW 0x3ffb0000 -#define ESP32_S2_DRAM_HIGH 0x40000000 -#define ESP32_S2_RTC_IRAM_LOW 0x40070000 -#define ESP32_S2_RTC_IRAM_HIGH 0x40072000 -#define ESP32_S2_RTC_DRAM_LOW 0x3ff9e000 -#define ESP32_S2_RTC_DRAM_HIGH 0x3ffa0000 +#include "esp_xtensa_semihosting.h" + #define ESP32_S2_RTC_DATA_LOW 0x50000000 #define ESP32_S2_RTC_DATA_HIGH 0x50002000 -#define ESP32_S2_EXTRAM_DATA_LOW 0x3f500000 -#define ESP32_S2_EXTRAM_DATA_HIGH 0x3ff80000 #define ESP32_S2_DR_REG_LOW 0x3f400000 #define ESP32_S2_DR_REG_HIGH 0x3f4d3FFC #define ESP32_S2_SYS_RAM_LOW 0x60000000UL #define ESP32_S2_SYS_RAM_HIGH (ESP32_S2_SYS_RAM_LOW + 0x20000000UL) -/* ESP32-S2 DROM mapping is not contiguous. */ -/* IDF declares this as 0x3F000000..0x3FF80000, but there are peripheral registers mapped to - * 0x3f400000..0x3f4d3FFC. */ -#define ESP32_S2_DROM0_LOW ESP32_S2_DROM_LOW -#define ESP32_S2_DROM0_HIGH ESP32_S2_DR_REG_LOW -#define ESP32_S2_DROM1_LOW ESP32_S2_DR_REG_HIGH -#define ESP32_S2_DROM1_HIGH ESP32_S2_DROM_HIGH /* ESP32 WDT */ #define ESP32_S2_WDT_WKEY_VALUE 0x50d83aa1 @@ -90,190 +69,6 @@ #define ESP32_S2_DR_REG_UART_BASE 0x3f400000 #define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000) #define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74) - -/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in - * xtensa-overlay */ -static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = { - XT_REG_IDX_PC, - XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3, - XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7, - XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11, - XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15, - XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19, - XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23, - XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27, - XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31, - XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35, - XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39, - XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43, - XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47, - XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51, - XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55, - XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59, - XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63, - XT_REG_IDX_SAR, - XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1, - XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, - ESP32_S2_REG_IDX_GPIOOUT, - XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR, - XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1, - XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1, - XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4, - XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC, - XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5, - XT_REG_IDX_EPS6, XT_REG_IDX_EPS7, - XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4, - XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE, - XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE, - XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT, - XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR, - XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2, - XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3, - XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3, - XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7, - XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11, - XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15, - XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT, - XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR, - XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS, - XT_REG_IDX_FAULT_INFO, - XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT, - XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER, - XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART, - XT_REG_IDX_TRAX_MEMEND, - XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1, - XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1, - XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR, -}; - -static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = { - { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type }, -}; - -static const struct xtensa_config esp32s2_xtensa_cfg = { - .density = true, - .aregs_num = XT_AREGS_NUM_MAX, - .windowed = true, - .coproc = true, - .miscregs_num = 4, - .reloc_vec = true, - .proc_id = true, - .threadptr = true, - .user_regs_num = ARRAY_SIZE(esp32s2_user_regs), - .user_regs = esp32s2_user_regs, - .fetch_user_regs = xtensa_fetch_user_regs_u32, - .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32, - .gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND, - .gdb_regs_mapping = esp32s2_gdb_regs_mapping, - .irom = { - .count = 2, - .regions = { - { - .base = ESP32_S2_IROM_LOW, - .size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW, - .access = XT_MEM_ACCESS_READ, - }, - { - .base = ESP32_S2_IROM_MASK_LOW, - .size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW, - .access = XT_MEM_ACCESS_READ, - }, - } - }, - .iram = { - .count = 2, - .regions = { - { - .base = ESP32_S2_IRAM_LOW, - .size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_RTC_IRAM_LOW, - .size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .drom = { - .count = 2, - .regions = { - { - .base = ESP32_S2_DROM0_LOW, - .size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW, - .access = XT_MEM_ACCESS_READ, - }, - { - .base = ESP32_S2_DROM1_LOW, - .size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW, - .access = XT_MEM_ACCESS_READ, - }, - } - }, - .dram = { - .count = 6, - .regions = { - { - .base = ESP32_S2_DRAM_LOW, - .size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_RTC_DRAM_LOW, - .size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_RTC_DATA_LOW, - .size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_EXTRAM_DATA_LOW, - .size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_DR_REG_LOW, - .size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S2_SYS_RAM_LOW, - .size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .exc = { - .enabled = true, - }, - .irq = { - .enabled = true, - .irq_num = 32, - }, - .high_irq = { - .enabled = true, - .excm_level = 3, - .nmi_num = 1, - }, - .tim_irq = { - .enabled = true, - .comp_num = 3, - }, - .debug = { - .enabled = true, - .irq_level = 6, - .ibreaks_num = 2, - .dbreaks_num = 2, - .icount_sz = 32, - }, - .trace = { - .enabled = true, - .mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ, - }, -}; - struct esp32s2_common { struct esp_xtensa_common esp_xtensa; }; @@ -306,7 +101,7 @@ static int esp32s2_deassert_reset(struct target *target) return ERROR_OK; } -int esp32s2_soft_reset_halt(struct target *target) +static int esp32s2_soft_reset_halt(struct target *target) { LOG_TARGET_DEBUG(target, "begin"); @@ -314,7 +109,7 @@ int esp32s2_soft_reset_halt(struct target *target) int res = esp32s2_soc_reset(target); if (res != ERROR_OK) return res; - return xtensa_assert_reset(target); + return xtensa_soft_reset_halt(target); } static int esp32s2_set_peri_reg_mask(struct target *target, @@ -477,7 +272,8 @@ static int esp32s2_soc_reset(struct target *target) alive_sleep(10); xtensa_poll(target); if (timeval_ms() >= timeout) { - LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state); + LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s", + target_state_name(target)); return ERROR_TARGET_TIMEOUT; } } @@ -568,10 +364,14 @@ static int esp32s2_arch_state(struct target *target) static int esp32s2_on_halt(struct target *target) { - return esp32s2_disable_wdts(target); + int ret = esp32s2_disable_wdts(target); + if (ret == ERROR_OK) + ret = esp_xtensa_on_halt(target); + return ret; } -static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) +static int esp32s2_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { int ret = xtensa_step(target, current, address, handle_breakpoints); if (ret == ERROR_OK) { @@ -585,12 +385,27 @@ static int esp32s2_poll(struct target *target) { enum target_state old_state = target->state; int ret = esp_xtensa_poll(target); + if (ret != ERROR_OK) + return ret; if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) { /* Call any event callbacks that are applicable */ if (old_state == TARGET_DEBUG_RUNNING) { target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } else { + if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) { + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + if (ret == ERROR_OK && esp_xtensa->semihost.need_resume) { + esp_xtensa->semihost.need_resume = false; + /* Resume xtensa_resume will handle BREAK instruction. */ + ret = target_resume(target, true, 0, true, false); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to resume target"); + return ret; + } + } + return ret; + } esp32s2_on_halt(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); } @@ -608,7 +423,11 @@ static int esp32s2_virt2phys(struct target *target, static int esp32s2_target_init(struct command_context *cmd_ctx, struct target *target) { - return esp_xtensa_target_init(cmd_ctx, target); + int ret = esp_xtensa_target_init(cmd_ctx, target); + if (ret != ERROR_OK) + return ret; + + return esp_xtensa_semihosting_init(target); } static const struct xtensa_debug_ops esp32s2_dbg_ops = { @@ -622,7 +441,11 @@ static const struct xtensa_power_ops esp32s2_pwr_ops = { .queue_reg_write = xtensa_dm_queue_pwr_reg_write }; -static int esp32s2_target_create(struct target *target, Jim_Interp *interp) +static const struct esp_semihost_ops esp32s2_semihost_ops = { + .prepare = esp32s2_disable_wdts +}; + +static int esp32s2_target_create(struct target *target) { struct xtensa_debug_module_config esp32s2_dm_cfg = { .dbg_ops = &esp32s2_dbg_ops, @@ -639,7 +462,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; } - int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg); + int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg, &esp32s2_semihost_ops); if (ret != ERROR_OK) { LOG_ERROR("Failed to init arch info!"); free(esp32); @@ -654,11 +477,19 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp) static const struct command_registration esp32s2_command_handlers[] = { { - .name = "xtensa", + .chain = xtensa_command_handlers, + }, + { + .name = "esp", + .usage = "", + .chain = esp32_apptrace_command_handlers, + }, + { + .name = "arm", .mode = COMMAND_ANY, - .help = "Xtensa commands group", + .help = "ARM Command Group", .usage = "", - .chain = xtensa_command_handlers, + .chain = semihosting_common_handlers }, COMMAND_REGISTRATION_DONE }; @@ -691,6 +522,10 @@ struct target_type esp32s2_target = { .get_gdb_arch = xtensa_get_gdb_arch, .get_gdb_reg_list = xtensa_get_gdb_reg_list, + .run_algorithm = xtensa_run_algorithm, + .start_algorithm = xtensa_start_algorithm, + .wait_algorithm = xtensa_wait_algorithm, + .add_breakpoint = esp_xtensa_breakpoint_add, .remove_breakpoint = esp_xtensa_breakpoint_remove, diff --git a/src/target/espressif/esp32s2.h b/src/target/espressif/esp32s2.h deleted file mode 100644 index adaabbf852..0000000000 --- a/src/target/espressif/esp32s2.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * ESP32-S2 target for OpenOCD * - * Copyright (C) 2019 Espressif Systems Ltd. * - * Author: Alexey Gerenkov <alexey@espressif.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_ESP32S2_H -#define OPENOCD_TARGET_ESP32S2_H - -#include <target/xtensa/xtensa_regs.h> - -#define ESP32_S2_DROM_LOW 0x3f000000 -#define ESP32_S2_DROM_HIGH 0x3ff80000 -#define ESP32_S2_IROM_LOW 0x40080000 -#define ESP32_S2_IROM_HIGH 0x40800000 - -/* Number of registers returned directly by the G command - * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */ -#define ESP32_S2_NUM_REGS_G_COMMAND 72 - -enum esp32s2_reg_id { - /* chip specific registers that extend ISA go after ISA-defined ones */ - ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START, - ESP32_S2_NUM_REGS, -}; - -#endif /* OPENOCD_TARGET_ESP32S2_H */ diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c index b5487407f3..14f7a7bb64 100644 --- a/src/target/espressif/esp32s3.c +++ b/src/target/espressif/esp32s3.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * ESP32-S3 target API for OpenOCD * @@ -13,8 +13,8 @@ #include <target/target.h> #include <target/target_type.h> #include <target/smp.h> +#include <target/semihosting_common.h> #include "assert.h" -#include "esp32s3.h" #include "esp_xtensa_smp.h" /* @@ -24,16 +24,6 @@ implementation. */ /* ESP32_S3 memory map */ -#define ESP32_S3_IRAM_LOW 0x40370000 -#define ESP32_S3_IRAM_HIGH 0x403E0000 -#define ESP32_S3_IROM_MASK_LOW 0x40000000 -#define ESP32_S3_IROM_MASK_HIGH 0x40060000 -#define ESP32_S3_DRAM_LOW 0x3FC88000 -#define ESP32_S3_DRAM_HIGH 0x3FD00000 -#define ESP32_S3_RTC_IRAM_LOW 0x600FE000 -#define ESP32_S3_RTC_IRAM_HIGH 0x60100000 -#define ESP32_S3_RTC_DRAM_LOW 0x600FE000 -#define ESP32_S3_RTC_DRAM_HIGH 0x60100000 #define ESP32_S3_RTC_DATA_LOW 0x50000000 #define ESP32_S3_RTC_DATA_HIGH 0x50002000 #define ESP32_S3_EXTRAM_DATA_LOW 0x3D000000 @@ -75,246 +65,10 @@ implementation. #define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC) #define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0 -/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in - *xtensa-overlay */ -static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = { - XT_REG_IDX_PC, - XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3, - XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7, - XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11, - XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15, - XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19, - XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23, - XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27, - XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31, - XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35, - XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39, - XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43, - XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47, - XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51, - XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55, - XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59, - XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63, - XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR, - XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1, - XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1, - XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI, - XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3, - ESP32_S3_REG_IDX_GPIOOUT, - XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3, - XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7, - XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11, - XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15, - XT_REG_IDX_FCR, XT_REG_IDX_FSR, - ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1, - ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2, - ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4, - ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2, - ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4, - ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH, - ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2, - ESP32_S3_REG_IDX_UA_STATE_3, - ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3, - ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7, - - XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, - XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR, - XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1, - XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1, - XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4, - XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC, - XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5, - XT_REG_IDX_EPS6, XT_REG_IDX_EPS7, - XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4, - XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE, - XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE, - XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT, - XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR, - XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2, - XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3, - - XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT, - XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR, - XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS, - XT_REG_IDX_FAULT_INFO, - XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT, - XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER, - XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART, - XT_REG_IDX_TRAX_MEMEND, - XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1, - XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1, - XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR, - XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3, - XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7, - XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11, - XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15, -}; - -/* actually this table contains user + TIE registers - * TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/ -static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = { - { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type }, - { "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type }, - { "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type }, - { "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type }, - { "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type }, - { "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type }, - { "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type }, - { "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type }, - { "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type }, - { "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type }, - { "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type }, - { "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type }, - { "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type }, - { "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type }, - { "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type }, - { "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type }, - { "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type }, - { "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type }, -}; - struct esp32s3_common { struct esp_xtensa_smp_common esp_xtensa_smp; }; -static int esp32s3_fetch_user_regs(struct target *target); -static int esp32s3_queue_write_dirty_user_regs(struct target *target); - -static const struct xtensa_config esp32s3_xtensa_cfg = { - .density = true, - .aregs_num = XT_AREGS_NUM_MAX, - .windowed = true, - .coproc = true, - .fp_coproc = true, - .loop = true, - .miscregs_num = 4, - .threadptr = true, - .boolean = true, - .reloc_vec = true, - .proc_id = true, - .cond_store = true, - .mac16 = true, - .user_regs_num = ARRAY_SIZE(esp32s3_user_regs), - .user_regs = esp32s3_user_regs, - .fetch_user_regs = esp32s3_fetch_user_regs, - .queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs, - .gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND, - .gdb_regs_mapping = esp32s3_gdb_regs_mapping, - .irom = { - .count = 2, - .regions = { - { - .base = ESP32_S3_IROM_LOW, - .size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW, - .access = XT_MEM_ACCESS_READ, - }, - { - .base = ESP32_S3_IROM_MASK_LOW, - .size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW, - .access = XT_MEM_ACCESS_READ, - } - } - }, - .iram = { - .count = 2, - .regions = { - { - .base = ESP32_S3_IRAM_LOW, - .size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S3_RTC_IRAM_LOW, - .size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .drom = { - .count = 1, - .regions = { - { - .base = ESP32_S3_DROM_LOW, - .size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW, - .access = XT_MEM_ACCESS_READ, - }, - } - }, - .dram = { - .count = 4, - .regions = { - { - .base = ESP32_S3_DRAM_LOW, - .size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S3_RTC_DRAM_LOW, - .size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S3_RTC_DATA_LOW, - .size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - { - .base = ESP32_S3_SYS_RAM_LOW, - .size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW, - .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE, - }, - } - }, - .exc = { - .enabled = true, - }, - .irq = { - .enabled = true, - .irq_num = 32, - }, - .high_irq = { - .enabled = true, - .excm_level = 3, - .nmi_num = 1, - }, - .tim_irq = { - .enabled = true, - .comp_num = 3, - }, - .debug = { - .enabled = true, - .irq_level = 6, - .ibreaks_num = 2, - .dbreaks_num = 2, - .icount_sz = 32, - }, - .trace = { - .enabled = true, - .mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ, - }, -}; - -static int esp32s3_fetch_user_regs(struct target *target) -{ - LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target)); - return ERROR_OK; -} - -static int esp32s3_queue_write_dirty_user_regs(struct target *target) -{ - LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target)); - return ERROR_OK; -} - /* Reset ESP32-S3's peripherals. * 1. OpenOCD makes sure the target is halted; if not, tries to halt it. * If that fails, tries to reset it (via OCD) and then halt. @@ -332,7 +86,7 @@ static int esp32s3_queue_write_dirty_user_regs(struct target *target) * PRO CPU is halted, APP CPU is in reset. */ -const uint8_t esp32s3_reset_stub_code[] = { +static const uint8_t esp32s3_reset_stub_code[] = { #include "../../../contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc" }; @@ -421,7 +175,8 @@ static int esp32s3_soc_reset(struct target *target) LOG_DEBUG("Resuming the target"); xtensa = target_to_xtensa(target); xtensa->suppress_dsr_errors = true; - res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0); + res = xtensa_resume(target, false, ESP32_S3_RTC_SLOW_MEM_BASE + 4, false, + false); xtensa->suppress_dsr_errors = false; if (res != ERROR_OK) { LOG_ERROR("Failed to run stub (%d)!", res); @@ -438,8 +193,8 @@ static int esp32s3_soc_reset(struct target *target) xtensa_poll(target); if (timeval_ms() >= timeout) { LOG_TARGET_ERROR(target, - "Timed out waiting for CPU to be reset, target state=%d", - target->state); + "Timed out waiting for CPU to be reset, target state %s", + target_state_name(target)); get_timeout = true; break; } @@ -519,7 +274,10 @@ static int esp32s3_disable_wdts(struct target *target) static int esp32s3_on_halt(struct target *target) { - return esp32s3_disable_wdts(target); + int ret = esp32s3_disable_wdts(target); + if (ret == ERROR_OK) + ret = esp_xtensa_smp_on_halt(target); + return ret; } static int esp32s3_arch_state(struct target *target) @@ -537,10 +295,9 @@ static int esp32s3_virt2phys(struct target *target, return ERROR_FAIL; } - static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target) { - return esp_xtensa_target_init(cmd_ctx, target); + return esp_xtensa_smp_target_init(cmd_ctx, target); } static const struct xtensa_debug_ops esp32s3_dbg_ops = { @@ -559,7 +316,11 @@ static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = { .on_halt = esp32s3_on_halt }; -static int esp32s3_target_create(struct target *target, Jim_Interp *interp) +static const struct esp_semihost_ops esp32s3_semihost_ops = { + .prepare = esp32s3_disable_wdts +}; + +static int esp32s3_target_create(struct target *target) { struct xtensa_debug_module_config esp32s3_dm_cfg = { .dbg_ops = &esp32s3_dbg_ops, @@ -577,9 +338,9 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp) int ret = esp_xtensa_smp_init_arch_info(target, &esp32s3->esp_xtensa_smp, - &esp32s3_xtensa_cfg, &esp32s3_dm_cfg, - &esp32s3_chip_ops); + &esp32s3_chip_ops, + &esp32s3_semihost_ops); if (ret != ERROR_OK) { LOG_ERROR("Failed to init arch info!"); free(esp32s3); @@ -597,11 +358,23 @@ static const struct command_registration esp32s3_command_handlers[] = { .usage = "", .chain = esp_xtensa_smp_command_handlers, }, + { + .name = "esp", + .usage = "", + .chain = esp32_apptrace_command_handlers, + }, { .name = "esp32", .usage = "", .chain = smp_command_handlers, }, + { + .name = "arm", + .mode = COMMAND_ANY, + .help = "ARM Command Group", + .usage = "", + .chain = semihosting_common_handlers + }, COMMAND_REGISTRATION_DONE }; @@ -633,6 +406,10 @@ struct target_type esp32s3_target = { .get_gdb_arch = xtensa_get_gdb_arch, .get_gdb_reg_list = xtensa_get_gdb_reg_list, + .run_algorithm = xtensa_run_algorithm, + .start_algorithm = xtensa_start_algorithm, + .wait_algorithm = xtensa_wait_algorithm, + .add_breakpoint = esp_xtensa_breakpoint_add, .remove_breakpoint = esp_xtensa_breakpoint_remove, @@ -645,4 +422,5 @@ struct target_type esp32s3_target = { .deinit_target = esp_xtensa_target_deinit, .commands = esp32s3_command_handlers, + .profiling = esp_xtensa_profiling, }; diff --git a/src/target/espressif/esp32s3.h b/src/target/espressif/esp32s3.h deleted file mode 100644 index a7d57ec024..0000000000 --- a/src/target/espressif/esp32s3.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * ESP32-S3 target for OpenOCD * - * Copyright (C) 2020 Espressif Systems Ltd. * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_ESP32S3_H -#define OPENOCD_TARGET_ESP32S3_H - -#include <target/xtensa/xtensa_regs.h> - -#define ESP32_S3_DROM_LOW 0x3C000000 -#define ESP32_S3_DROM_HIGH 0x3D000000 -#define ESP32_S3_IROM_LOW 0x42000000 -#define ESP32_S3_IROM_HIGH 0x44000000 - -/*Number of registers returned directly by the G command - *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */ -#define ESP32_S3_NUM_REGS_G_COMMAND 128 - -enum esp32s3_reg_id { - /* chip specific registers that extend ISA go after ISA-defined ones */ - ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS, - ESP32_S3_REG_IDX_ACCX_0, - ESP32_S3_REG_IDX_ACCX_1, - ESP32_S3_REG_IDX_QACC_H_0, - ESP32_S3_REG_IDX_QACC_H_1, - ESP32_S3_REG_IDX_QACC_H_2, - ESP32_S3_REG_IDX_QACC_H_3, - ESP32_S3_REG_IDX_QACC_H_4, - ESP32_S3_REG_IDX_QACC_L_0, - ESP32_S3_REG_IDX_QACC_L_1, - ESP32_S3_REG_IDX_QACC_L_2, - ESP32_S3_REG_IDX_QACC_L_3, - ESP32_S3_REG_IDX_QACC_L_4, - ESP32_S3_REG_IDX_SAR_BYTE, - ESP32_S3_REG_IDX_FFT_BIT_WIDTH, - ESP32_S3_REG_IDX_UA_STATE_0, - ESP32_S3_REG_IDX_UA_STATE_1, - ESP32_S3_REG_IDX_UA_STATE_2, - ESP32_S3_REG_IDX_UA_STATE_3, - ESP32_S3_REG_IDX_Q0, - ESP32_S3_REG_IDX_Q1, - ESP32_S3_REG_IDX_Q2, - ESP32_S3_REG_IDX_Q3, - ESP32_S3_REG_IDX_Q4, - ESP32_S3_REG_IDX_Q5, - ESP32_S3_REG_IDX_Q6, - ESP32_S3_REG_IDX_Q7, - ESP32_S3_NUM_REGS, -}; - -#endif /* OPENOCD_TARGET_ESP32S3_H */ diff --git a/src/target/espressif/esp_algorithm.c b/src/target/espressif/esp_algorithm.c new file mode 100644 index 0000000000..79f610b922 --- /dev/null +++ b/src/target/espressif/esp_algorithm.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Espressif chips common algorithm API for OpenOCD * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/align.h> +#include <target/algorithm.h> +#include <target/target.h> +#include "esp_algorithm.h" + +#define DEFAULT_ALGORITHM_TIMEOUT_MS 40000 /* ms */ + +static int esp_algorithm_read_stub_logs(struct target *target, struct esp_algorithm_stub *stub) +{ + if (!stub || stub->log_buff_addr == 0 || stub->log_buff_size == 0) + return ERROR_FAIL; + + uint32_t len = 0; + int retval = target_read_u32(target, stub->log_buff_addr, &len); + if (retval != ERROR_OK) + return retval; + + /* sanity check. log_buff_size = sizeof(len) + sizeof(log_buff) */ + if (len == 0 || len > stub->log_buff_size - 4) + return ERROR_FAIL; + + uint8_t *log_buff = calloc(1, len); + if (!log_buff) { + LOG_ERROR("Failed to allocate memory for the stub log!"); + return ERROR_FAIL; + } + retval = target_read_memory(target, stub->log_buff_addr + 4, 1, len, log_buff); + if (retval == ERROR_OK) + LOG_OUTPUT("%*.*s", len, len, log_buff); + free(log_buff); + return retval; +} + +static int esp_algorithm_run_image(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap) +{ + struct working_area **mem_handles = NULL; + + if (!run || !run->hw) + return ERROR_FAIL; + + int retval = run->hw->algo_init(target, run, num_args, ap); + if (retval != ERROR_OK) + return retval; + + /* allocate memory arguments and fill respective reg params */ + if (run->mem_args.count > 0) { + mem_handles = calloc(run->mem_args.count, sizeof(*mem_handles)); + if (!mem_handles) { + LOG_ERROR("Failed to alloc target mem handles!"); + retval = ERROR_FAIL; + goto _cleanup; + } + /* alloc memory args target buffers */ + for (uint32_t i = 0; i < run->mem_args.count; i++) { + /* small hack: if we need to update some reg param this field holds + * appropriate user argument number, */ + /* otherwise should hold UINT_MAX */ + uint32_t usr_param_num = run->mem_args.params[i].address; + static struct working_area *area; + retval = target_alloc_working_area(target, run->mem_args.params[i].size, &area); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to alloc target buffer!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _cleanup; + } + mem_handles[i] = area; + run->mem_args.params[i].address = area->address; + if (usr_param_num != UINT_MAX) /* if we need update some register param with mem param value */ + esp_algorithm_user_arg_set_uint(run, usr_param_num, run->mem_args.params[i].address); + } + } + + if (run->usr_func_init) { + retval = run->usr_func_init(target, run, run->usr_func_arg); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to prepare algorithm host side args stub (%d)!", retval); + goto _cleanup; + } + } + + LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT, + run->stub.tramp_mapped_addr, run->stack_size, run->stub.stack_addr); + retval = target_start_algorithm(target, + run->mem_args.count, run->mem_args.params, + run->reg_args.count, run->reg_args.params, + run->stub.tramp_mapped_addr, 0, + run->stub.ainfo); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to start algorithm (%d)!", retval); + goto _cleanup; + } + + if (run->usr_func) { + /* give target algorithm stub time to init itself, then user func can communicate to it safely */ + alive_sleep(100); + retval = run->usr_func(target, run->usr_func_arg); + if (retval != ERROR_OK) + LOG_ERROR("Failed to exec algorithm user func (%d)!", retval); + } + uint32_t timeout_ms = 0; /* do not wait if 'usr_func' returned error */ + if (retval == ERROR_OK) + timeout_ms = run->timeout_ms ? run->timeout_ms : DEFAULT_ALGORITHM_TIMEOUT_MS; + LOG_DEBUG("Wait algorithm completion"); + retval = target_wait_algorithm(target, + run->mem_args.count, run->mem_args.params, + run->reg_args.count, run->reg_args.params, + 0, timeout_ms, + run->stub.ainfo); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to wait algorithm (%d)!", retval); + /* target has been forced to stop in target_wait_algorithm() */ + } + esp_algorithm_read_stub_logs(target, &run->stub); + + if (run->usr_func_done) + run->usr_func_done(target, run, run->usr_func_arg); + + if (retval != ERROR_OK) { + LOG_ERROR("Algorithm run failed (%d)!", retval); + } else { + run->ret_code = esp_algorithm_user_arg_get_uint(run, 0); + LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code); + } + +_cleanup: + /* free memory arguments */ + if (mem_handles) { + for (uint32_t i = 0; i < run->mem_args.count; i++) { + if (mem_handles[i]) + target_free_working_area(target, mem_handles[i]); + } + free(mem_handles); + } + run->hw->algo_cleanup(target, run); + + return retval; +} + +static int esp_algorithm_run_debug_stub(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap) +{ + if (!run || !run->hw) + return ERROR_FAIL; + + int retval = run->hw->algo_init(target, run, num_args, ap); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT, + run->stub.tramp_mapped_addr, run->stack_size, run->stub.stack_addr); + retval = target_start_algorithm(target, + run->mem_args.count, run->mem_args.params, + run->reg_args.count, run->reg_args.params, + run->stub.tramp_mapped_addr, 0, + run->stub.ainfo); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to start algorithm (%d)!", retval); + goto _cleanup; + } + + uint32_t timeout_ms = 0; /* do not wait if 'usr_func' returned error */ + if (retval == ERROR_OK) + timeout_ms = run->timeout_ms ? run->timeout_ms : DEFAULT_ALGORITHM_TIMEOUT_MS; + LOG_DEBUG("Wait algorithm completion"); + retval = target_wait_algorithm(target, + run->mem_args.count, run->mem_args.params, + run->reg_args.count, run->reg_args.params, + 0, timeout_ms, + run->stub.ainfo); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to wait algorithm (%d)!", retval); + /* target has been forced to stop in target_wait_algorithm() */ + } + + if (retval != ERROR_OK) { + LOG_ERROR("Algorithm run failed (%d)!", retval); + } else { + run->ret_code = esp_algorithm_user_arg_get_uint(run, 0); + LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code); + } + +_cleanup: + run->hw->algo_cleanup(target, run); + + return retval; +} + +static void reverse_binary(const uint8_t *src, uint8_t *dest, size_t length) +{ + size_t remaining = length % 4; + size_t offset = 0; + size_t aligned_len = ALIGN_UP(length, 4); + + if (remaining > 0) { + /* Put extra bytes to the beginning with padding */ + memset(dest + remaining, 0xFF, 4 - remaining); + for (size_t i = 0; i < remaining; i++) + dest[i] = src[length - remaining + i]; + length -= remaining; /* reverse the others */ + offset = 4; + } + + for (size_t i = offset; i < aligned_len; i += 4) { + dest[i + 0] = src[length - i + offset - 4]; + dest[i + 1] = src[length - i + offset - 3]; + dest[i + 2] = src[length - i + offset - 2]; + dest[i + 3] = src[length - i + offset - 1]; + } +} + +static int load_section_from_image(struct target *target, + struct esp_algorithm_run_data *run, + int section_num, + bool reverse) +{ + if (!run) + return ERROR_FAIL; + + struct imagesection *section = &run->image.image.sections[section_num]; + uint32_t sec_wr = 0; + uint8_t buf[1024]; + + assert(sizeof(buf) % 4 == 0); + + while (sec_wr < section->size) { + uint32_t nb = section->size - sec_wr > sizeof(buf) ? sizeof(buf) : section->size - sec_wr; + size_t size_read = 0; + int retval = image_read_section(&run->image.image, section_num, sec_wr, nb, buf, &size_read); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read stub section (%d)!", retval); + return retval; + } + + if (reverse) { + size_t aligned_len = ALIGN_UP(size_read, 4); + uint8_t reversed_buf[aligned_len]; + + /* Send original size to allow padding */ + reverse_binary(buf, reversed_buf, size_read); + + /* + The address range accessed via the instruction bus is in reverse order (word-wise) compared to access + via the data bus. That is to say, address + 0x3FFE_0000 and 0x400B_FFFC access the same word + 0x3FFE_0004 and 0x400B_FFF8 access the same word + 0x3FFE_0008 and 0x400B_FFF4 access the same word + ... + The data bus and instruction bus of the CPU are still both little-endian, + so the byte order of individual words is not reversed between address spaces. + For example, address + 0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC. + 0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC. + 0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC. + For more details, please refer to ESP32 TRM, Internal SRAM1 section. + */ + retval = target_write_buffer(target, run->image.dram_org - sec_wr - aligned_len, aligned_len, reversed_buf); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to write stub section!"); + return retval; + } + } else { + retval = target_write_buffer(target, section->base_address + sec_wr, size_read, buf); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to write stub section!"); + return retval; + } + } + + sec_wr += size_read; + } + + return ERROR_OK; +} + +/* + * Configuration: + * ---------------------------- + * The linker scripts defines the memory layout for the stub code. + * The OpenOCD script specifies the workarea address and it's size + * Sections defined in the linker are organized to share the same addresses with the workarea. + * code and data sections are located in Internal SRAM1 and OpenOCD fills these sections using the data bus. + */ +int esp_algorithm_load_func_image(struct target *target, struct esp_algorithm_run_data *run) +{ + int retval; + size_t tramp_sz = 0; + const uint8_t *tramp = NULL; + struct duration algo_time; + bool alloc_code_working_area = true; + + if (!run || !run->hw) + return ERROR_FAIL; + + if (duration_start(&algo_time) != 0) { + LOG_ERROR("Failed to start algo time measurement!"); + return ERROR_FAIL; + } + + if (run->hw->stub_tramp_get) { + tramp = run->hw->stub_tramp_get(target, &tramp_sz); + if (!tramp) + return ERROR_FAIL; + } + + LOG_DEBUG("stub: base 0x%x, start 0x%" PRIx32 ", %d sections", + run->image.image.base_address_set ? (unsigned int)run->image.image.base_address : 0, + run->image.image.start_address, + run->image.image.num_sections); + run->stub.entry = run->image.image.start_address; + + /* [code + trampoline] + <padding> + [data] */ + + /* ESP32 has reversed memory region. It will use the last part of DRAM, the others will use the first part. + * To avoid complexity for the backup/restore process, we will allocate a workarea for all IRAM region from + * the beginning. In that case no need to have a padding area. + */ + if (run->image.reverse) { + if (target_alloc_working_area(target, run->image.iram_len, &run->stub.code) != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc space for stub code!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + alloc_code_working_area = false; + } + + uint32_t code_size = 0; + + /* Load code section */ + for (unsigned int i = 0; i < run->image.image.num_sections; i++) { + struct imagesection *section = &run->image.image.sections[i]; + + if (section->size == 0) + continue; + + if (section->flags & ESP_IMAGE_ELF_PHF_EXEC) { + LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64, + section->base_address, section->size, section->flags); + + if (alloc_code_working_area) { + retval = target_alloc_working_area(target, section->size, &run->stub.code); + if (retval != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc space for stub code!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + } + + if (section->base_address == 0) { + section->base_address = run->stub.code->address; + /* sanity check, stub is compiled to be run from working area */ + } else if (run->stub.code->address != section->base_address) { + LOG_ERROR("working area " TARGET_ADDR_FMT " and stub code section " TARGET_ADDR_FMT + " address mismatch!", + section->base_address, + run->stub.code->address); + retval = ERROR_FAIL; + goto _on_error; + } + + retval = load_section_from_image(target, run, i, run->image.reverse); + if (retval != ERROR_OK) + goto _on_error; + + code_size += ALIGN_UP(section->size, 4); + break; /* Stub has one executable text section */ + } + } + + /* If exists, load trampoline to the code area */ + if (tramp) { + if (run->stub.tramp_addr == 0) { + if (alloc_code_working_area) { + /* alloc trampoline in code working area */ + if (target_alloc_working_area(target, tramp_sz, &run->stub.tramp) != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc space for stub jumper!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + run->stub.tramp_addr = run->stub.tramp->address; + } + } + + size_t al_tramp_size = ALIGN_UP(tramp_sz, 4); + + if (run->image.reverse) { + target_addr_t reversed_tramp_addr = run->image.dram_org - code_size; + uint8_t reversed_tramp[al_tramp_size]; + + /* Send original size to allow padding */ + reverse_binary(tramp, reversed_tramp, tramp_sz); + run->stub.tramp_addr = reversed_tramp_addr - al_tramp_size; + LOG_DEBUG("Write reversed tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, al_tramp_size); + retval = target_write_buffer(target, run->stub.tramp_addr, al_tramp_size, reversed_tramp); + } else { + LOG_DEBUG("Write tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, tramp_sz); + retval = target_write_buffer(target, run->stub.tramp_addr, tramp_sz, tramp); + } + + if (retval != ERROR_OK) { + LOG_ERROR("Failed to write stub jumper!"); + goto _on_error; + } + + run->stub.tramp_mapped_addr = run->image.iram_org + code_size; + code_size += al_tramp_size; + LOG_DEBUG("Tramp mapped to addr " TARGET_ADDR_FMT, run->stub.tramp_mapped_addr); + } + + /* allocate dummy space until the data address */ + if (alloc_code_working_area) { + /* we dont need to restore padding area. */ + uint32_t backup_working_area_prev = target->backup_working_area; + target->backup_working_area = 0; + if (target_alloc_working_area(target, run->image.iram_len - code_size, &run->stub.padding) != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc space for stub code!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + target->backup_working_area = backup_working_area_prev; + } + + /* Load the data section */ + for (unsigned int i = 0; i < run->image.image.num_sections; i++) { + struct imagesection *section = &run->image.image.sections[i]; + + if (section->size == 0) + continue; + + if (!(section->flags & ESP_IMAGE_ELF_PHF_EXEC)) { + LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64, section->base_address, section->size, + section->flags); + /* target_alloc_working_area() aligns the whole working area size to 4-byte boundary. + We alloc one area for both DATA and BSS, so align each of them ourselves. */ + uint32_t data_sec_sz = ALIGN_UP(section->size, 4); + LOG_DEBUG("DATA sec size %" PRIu32 " -> %" PRIu32, section->size, data_sec_sz); + uint32_t bss_sec_sz = ALIGN_UP(run->image.bss_size, 4); + LOG_DEBUG("BSS sec size %" PRIu32 " -> %" PRIu32, run->image.bss_size, bss_sec_sz); + if (target_alloc_working_area(target, data_sec_sz + bss_sec_sz, &run->stub.data) != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc space for stub data!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + if (section->base_address == 0) { + section->base_address = run->stub.data->address; + /* sanity check, stub is compiled to be run from working area */ + } else if (run->stub.data->address != section->base_address) { + LOG_ERROR("working area " TARGET_ADDR_FMT + " and stub data section " TARGET_ADDR_FMT + " address mismatch!", + section->base_address, + run->stub.data->address); + retval = ERROR_FAIL; + goto _on_error; + } + + retval = load_section_from_image(target, run, i, false); + if (retval != ERROR_OK) + goto _on_error; + } + } + + /* stack */ + if (run->stub.stack_addr == 0 && run->stack_size > 0) { + /* allocate stack in data working area */ + if (target_alloc_working_area(target, run->stack_size, &run->stub.stack) != ERROR_OK) { + LOG_ERROR("no working area available, can't alloc stub stack!"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto _on_error; + } + run->stub.stack_addr = run->stub.stack->address + run->stack_size; + } + + if (duration_measure(&algo_time) != 0) { + LOG_ERROR("Failed to stop algo run measurement!"); + retval = ERROR_FAIL; + goto _on_error; + } + LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000); + return ERROR_OK; + +_on_error: + esp_algorithm_unload_func_image(target, run); + return retval; +} + +int esp_algorithm_unload_func_image(struct target *target, struct esp_algorithm_run_data *run) +{ + if (!run) + return ERROR_FAIL; + + target_free_all_working_areas(target); + + run->stub.tramp = NULL; + run->stub.stack = NULL; + run->stub.code = NULL; + run->stub.data = NULL; + run->stub.padding = NULL; + + return ERROR_OK; +} + +int esp_algorithm_exec_func_image_va(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap) +{ + if (!run || !run->image.image.start_address_set || run->image.image.start_address == 0) + return ERROR_FAIL; + + return esp_algorithm_run_image(target, run, num_args, ap); +} + +int esp_algorithm_load_onboard_func(struct target *target, target_addr_t func_addr, struct esp_algorithm_run_data *run) +{ + int res; + const uint8_t *tramp = NULL; + size_t tramp_sz = 0; + struct duration algo_time; + + if (!run || !run->hw) + return ERROR_FAIL; + + if (duration_start(&algo_time) != 0) { + LOG_ERROR("Failed to start algo time measurement!"); + return ERROR_FAIL; + } + + if (run->hw->stub_tramp_get) { + tramp = run->hw->stub_tramp_get(target, &tramp_sz); + if (!tramp) + return ERROR_FAIL; + } + + if (tramp_sz > run->on_board.code_buf_size) { + LOG_ERROR("Stub tramp size %zu bytes exceeds target buf size %d bytes!", + tramp_sz, run->on_board.code_buf_size); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (run->stack_size > run->on_board.min_stack_size) { + LOG_ERROR("Algorithm stack size not fit into the allocated target stack!"); + return ERROR_FAIL; + } + + run->stub.stack_addr = run->on_board.min_stack_addr + run->stack_size; + run->stub.tramp_addr = run->on_board.code_buf_addr; + run->stub.tramp_mapped_addr = run->stub.tramp_addr; + run->stub.entry = func_addr; + + if (tramp) { + res = target_write_buffer(target, run->stub.tramp_addr, tramp_sz, tramp); + if (res != ERROR_OK) { + LOG_ERROR("Failed to write stub jumper!"); + esp_algorithm_unload_onboard_func(target, run); + return res; + } + } + + if (duration_measure(&algo_time) != 0) { + LOG_ERROR("Failed to stop algo run measurement!"); + return ERROR_FAIL; + } + LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000); + + return ERROR_OK; +} + +int esp_algorithm_unload_onboard_func(struct target *target, struct esp_algorithm_run_data *run) +{ + return ERROR_OK; +} + +int esp_algorithm_exec_onboard_func_va(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap) +{ + return esp_algorithm_run_debug_stub(target, run, num_args, ap); +} diff --git a/src/target/espressif/esp_algorithm.h b/src/target/espressif/esp_algorithm.h new file mode 100644 index 0000000000..185234f971 --- /dev/null +++ b/src/target/espressif/esp_algorithm.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Espressif chips common algorithm API for OpenOCD * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_ALGORITHM_H +#define OPENOCD_TARGET_ESP_ALGORITHM_H + +#include "helper/log.h" +#include "helper/binarybuffer.h" +#include <helper/time_support.h> +#include <target/algorithm.h> +#include <target/image.h> + +/** + * API defined below allows executing pieces of code on target without breaking the execution of the running program. + * This functionality can be useful for various debugging and maintenance procedures. + * @note ESP flashing code to load flasher stub on target and write/read/erase flash. + * Also ESP GCOV command uses some of these functions to run onboard routines to dump coverage info. + * Stub entry function can take up to 5 arguments and should be of the following form: + * + * int stub_entry([uint32_t a1 [, uint32_t a2 [, uint32_t a3 [, uint32_t a4 [, uint32_t a5]]]]]); + * + * The general scheme of stub code execution is shown below. + * + * ------- ----------- (initial frame) ---- + * | | -------(registers, stub entry, stub args)------> |trampoline | ---(stub args)---> | | + * | | | | | | + * |OpenOCD| <----------(stub-specific communications)---------------------------------------> |stub| + * | | | | | | + * | | <---------(target halted event, ret code)------- |tramp break| <---(ret code)---- | | + * ------- ----------- ---- + * + * Procedure of executing stub on target includes: + * 1) User prepares struct esp_algorithm_run_data and calls one of algorithm_run_xxx() functions. + * 2) Routine allocates all necessary stub code and data sections. + * 3) If a user specifies an initializer func esp_algorithm_run_data::usr_func_init + * it is called just before the stub starts. + * 4) If user specifies stub communication func esp_algorithm_run_data::usr_func + * (@see esp_flash_write/read in ESP flash driver) + * it is called just after the stub starts. When communication with stub is finished this function must return. + * 5) OpenOCD waits for the stub to finish (hit exit breakpoint). + * 6) If the user specified arguments cleanup func esp_algorithm_run_data::usr_func_done, + * it is called just after the stub finishes. + * + * There are two options to run code on target under OpenOCD control: + * - Run externally compiled stub code. + * - Run onboard pre-compiled code. @note For ESP chips debug stubs must be enabled in target code @see ESP IDF docs. + * The main difference between the execution of external stub code and target built-in functions is that + * in the latter case working areas can not be used to allocate target memory for code and data because they can overlap + * with code and data involved in onboard function execution. For example, if memory allocated in the working area + * for the stub stack will overlap with some on-board data used by the stub the stack will get overwritten. + * The same stands for allocations in target code space. + * + * External Code Execution + * ----------------------- + * To run external code on the target user should use esp_algorithm_run_func_image(). + * In this case all necessary memory (code/data) is allocated in working areas that have fixed configuration + * defined in target TCL file. Stub code is actually a standalone program, so all its segments must have known + * addresses due to position-dependent code nature. So stub must be linked in such a way that its code segment + * starts at the beginning of the working area for code space defined in TCL. The same restriction must be applied + * to stub's data segment and base addresses of working area for data space. @see ESP stub flasher LD scripts. + * Also in order to simplify memory allocation BSS section must follow the DATA section in the stub image. + * The size of the BSS section must be specified in the bss_size field of struct algorithm_image. + * Sample stub memory map is shown below. + * ___________________________________________ + * | data space working area start | + * | | + * | <stub .data segment> | + * |___________________________________________| + * | stub .bss start | + * | | + * | <stub .bss segment of size 'bss_size'> | + * |___________________________________________| + * | stub stack base | + * | | + * | <stub stack> | + * |___________________________________________| + * | | + * | <stub mem arg1> | + * |___________________________________________| + * | | + * | <stub mem arg2> | + * |___________________________________________| + * ___________________________________________ + * | code space working area start | + * | | + * | <stub .text segment> | + * |___________________________________________| + * | | + * | <stub trampoline with exit breakpoint> | + * |___________________________________________| + * + * For example on how to execute external code with memory arguments @see esp_algo_flash_blank_check in + * ESP flash driver. + * + * On-Board Code Execution + * ----------------------- + * To run on-board code on the target user should use esp_algorithm_run_onboard_func(). + * On-board code execution process does not need to allocate target memory for stub code and data, + * Because the stub is pre-compiled to the code running on the target. + * But it still needs memory for stub trampoline, stack, and memory arguments. + * Working areas can not be used due to possible memory layout conflicts with on-board stub code and data. + * Debug stubs functionality provided by ESP IDF allows OpenOCD to overcome the above problem. + * It provides a special descriptor which provides info necessary to safely allocate memory on target. + * @see struct esp_dbg_stubs_desc. + * That info is also used to locate memory for stub trampoline code. + * User can execute target function at any address, but @see ESP IDF debug stubs also provide a way to pass to the host + * an entry address of pre-defined registered stub functions. + * For example of an on-board code execution @see esp32_cmd_gcov() in ESP32 apptrace module. +*/ + +/** + * Algorithm image data. + * Helper struct to work with algorithms consisting of code and data segments. + */ +struct esp_algorithm_image { + /** Image. */ + struct image image; + /** BSS section size. */ + uint32_t bss_size; + /** IRAM start address in the linker script */ + uint32_t iram_org; + /** Total reserved IRAM size */ + uint32_t iram_len; + /** DRAM start address in the linker script */ + uint32_t dram_org; + /** Total reserved DRAM size */ + uint32_t dram_len; + /** IRAM DRAM address range reversed or not */ + bool reverse; +}; + +#define ESP_IMAGE_ELF_PHF_EXEC 0x1 + +/** + * Algorithm stub data. + */ +struct esp_algorithm_stub { + /** Entry addr. */ + target_addr_t entry; + /** Working area for code segment. */ + struct working_area *code; + /** Working area for data segment. */ + struct working_area *data; + /** Working area for trampoline. */ + struct working_area *tramp; + /** Working area for padding between code and data area. */ + struct working_area *padding; + /** Address of the target buffer for stub trampoline. If zero tramp->address will be used. */ + target_addr_t tramp_addr; + /** Tramp code area will be filled from dbus. + * We need to map it to the ibus to be able to initialize PC register to start algorithm execution from. + */ + target_addr_t tramp_mapped_addr; + /** Working area for stack. */ + struct working_area *stack; + /** Address of the target buffer for stack. If zero tramp->address will be used. */ + target_addr_t stack_addr; + /** Address of the log buffer */ + target_addr_t log_buff_addr; + /** Size of the log buffer */ + uint32_t log_buff_size; + /** Algorithm's arch-specific info. */ + void *ainfo; +}; + +/** + * Algorithm stub in-memory arguments. + */ +struct esp_algorithm_mem_args { + /** Memory params. */ + struct mem_param *params; + /** Number of memory params. */ + uint32_t count; +}; + +/** + * Algorithm stub register arguments. + */ +struct esp_algorithm_reg_args { + /** Algorithm register params. User args start from user_first_reg_param */ + struct reg_param *params; + /** Number of register params. */ + uint32_t count; + /** The first several reg_params can be used by stub itself (e.g. for trampoline). + * This is the index of the first reg_param available for user to pass args to algorithm stub. */ + uint32_t first_user_param; +}; + +struct esp_algorithm_run_data; + +struct esp_algorithm_hw { + int (*algo_init)(struct target *target, struct esp_algorithm_run_data *run, uint32_t num_args, va_list ap); + int (*algo_cleanup)(struct target *target, struct esp_algorithm_run_data *run); + const uint8_t *(*stub_tramp_get)(struct target *target, size_t *size); +}; + +/** + * Algorithm run data. + */ +struct esp_algorithm_run_data { + /** Algorithm completion timeout in ms. If 0, default value will be used */ + uint32_t timeout_ms; + /** Algorithm stack size. */ + uint32_t stack_size; + /** Algorithm register arguments. */ + struct esp_algorithm_reg_args reg_args; + /** Algorithm memory arguments. */ + struct esp_algorithm_mem_args mem_args; + /** Algorithm arch-specific info. For Xtensa this should point to struct xtensa_algorithm. */ + void *arch_info; + /** Algorithm return code. */ + int32_t ret_code; + /** Stub. */ + struct esp_algorithm_stub stub; + union { + struct { + /** Size of the pre-alocated on-board buffer for stub's code. */ + uint32_t code_buf_size; + /** Address of pre-compiled target buffer for stub trampoline. */ + target_addr_t code_buf_addr; + /** Size of the pre-alocated on-board buffer for stub's stack. */ + uint32_t min_stack_size; + /** Pre-compiled target buffer's addr for stack. */ + target_addr_t min_stack_addr; + } on_board; + struct esp_algorithm_image image; + }; + /** Host side algorithm function argument. */ + void *usr_func_arg; + + /** + * @brief Host part of algorithm. + * This function will be called while stub is running on target. + * It can be used for communication with stub. + * + * @param target Pointer to target. + * @param usr_arg Function specific argument. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. + */ + int (*usr_func)(struct target *target, void *usr_arg); + + /** + * @brief Algorithm's arguments setup function. + * This function will be called just before stub start. + * It must return when all operations with running stub are completed. + * It can be used to prepare stub memory parameters. + * + * @param target Pointer to target. + * @param run Pointer to algo run data. + * @param usr_arg Function specific argument. The same as for usr_func. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. + */ + int (*usr_func_init)(struct target *target, + struct esp_algorithm_run_data *run, + void *usr_arg); + + /** + * @brief Algorithm's arguments cleanup function. + * This function will be called just after stub exit. + * It can be used to cleanup stub memory parameters. + * + * @param target Pointer to target. + * @param run Pointer to algo run data. + * @param usr_arg Function specific argument. The same as for usr_func. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. + */ + void (*usr_func_done)(struct target *target, + struct esp_algorithm_run_data *run, + void *usr_arg); + + /** + * @brief Algorithm run function. + * + * @param target Pointer to target. + * @param run Pointer to algo run data. + * @param arg Function specific argument. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. + */ + int (*algo_func)(struct target *target, struct esp_algorithm_run_data *run, void *arg); + + /** HW specific API */ + const struct esp_algorithm_hw *hw; +}; + +int esp_algorithm_load_func_image(struct target *target, struct esp_algorithm_run_data *run); +int esp_algorithm_unload_func_image(struct target *target, struct esp_algorithm_run_data *run); + +int esp_algorithm_exec_func_image_va(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap); + +/** + * @brief Loads and runs stub from specified image. + * This function should be used to run external stub code on target. + * + * @param target Pointer to target. + * @param run Pointer to algo run data. + * @param num_args Number of stub arguments that follow. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. Stub return code is in run->ret_code. + */ +static inline int esp_algorithm_run_func_image_va(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap) +{ + int ret = esp_algorithm_load_func_image(target, run); + if (ret != ERROR_OK) + return ret; + ret = esp_algorithm_exec_func_image_va(target, run, num_args, ap); + int rc = esp_algorithm_unload_func_image(target, run); + return ret != ERROR_OK ? ret : rc; +} + +static inline int esp_algorithm_run_func_image(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + ...) +{ + va_list ap; + va_start(ap, num_args); + int retval = esp_algorithm_run_func_image_va(target, run, num_args, ap); + va_end(ap); + return retval; +} + +int esp_algorithm_load_onboard_func(struct target *target, + target_addr_t func_addr, + struct esp_algorithm_run_data *run); +int esp_algorithm_unload_onboard_func(struct target *target, struct esp_algorithm_run_data *run); +int esp_algorithm_exec_onboard_func_va(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t num_args, + va_list ap); + +/** + * @brief Runs pre-compiled on-board function. + * This function should be used to run on-board stub code. + * + * @param target Pointer to target. + * @param run Pointer to algo run data. + * @param func_entry Address of the function to run. + * @param num_args Number of function arguments that follow. + * + * @return ERROR_OK on success, otherwise ERROR_XXX. Stub return code is in run->ret_code. + */ +static inline int esp_algorithm_run_onboard_func_va(struct target *target, + struct esp_algorithm_run_data *run, + target_addr_t func_addr, + uint32_t num_args, + va_list ap) +{ + int ret = esp_algorithm_load_onboard_func(target, func_addr, run); + if (ret != ERROR_OK) + return ret; + ret = esp_algorithm_exec_onboard_func_va(target, run, num_args, ap); + if (ret != ERROR_OK) + return ret; + return esp_algorithm_unload_onboard_func(target, run); +} + +static inline int esp_algorithm_run_onboard_func(struct target *target, + struct esp_algorithm_run_data *run, + target_addr_t func_addr, + uint32_t num_args, + ...) +{ + va_list ap; + va_start(ap, num_args); + int retval = esp_algorithm_run_onboard_func_va(target, run, func_addr, num_args, ap); + va_end(ap); + return retval; +} + +/** + * @brief Set the value of an argument passed via registers to the stub main function. + */ +static inline void esp_algorithm_user_arg_set_uint(struct esp_algorithm_run_data *run, + int arg_num, + uint64_t val) +{ + struct reg_param *param = &run->reg_args.params[run->reg_args.first_user_param + arg_num]; + + assert(param->size <= 64); + + if (param->size <= 32) + buf_set_u32(param->value, 0, param->size, val); + else + buf_set_u64(param->value, 0, param->size, val); +} + +/** + * @brief Get the value of an argument passed via registers from the stub main function. + */ +static inline uint64_t esp_algorithm_user_arg_get_uint(struct esp_algorithm_run_data *run, int arg_num) +{ + struct reg_param *param = &run->reg_args.params[run->reg_args.first_user_param + arg_num]; + + assert(param->size <= 64); + + if (param->size <= 32) + return buf_get_u32(param->value, 0, param->size); + return buf_get_u64(param->value, 0, param->size); +} + +#endif /* OPENOCD_TARGET_ESP_ALGORITHM_H */ diff --git a/src/target/espressif/esp_semihosting.c b/src/target/espressif/esp_semihosting.c new file mode 100644 index 0000000000..51d499866d --- /dev/null +++ b/src/target/espressif/esp_semihosting.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Semihosting API for Espressif chips * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/log.h> +#include <target/target.h> +#include <target/semihosting_common.h> +#include "esp_semihosting.h" +#include "esp_xtensa.h" + +static struct esp_semihost_data __attribute__((unused)) *target_to_esp_semihost_data(struct target *target) +{ + struct xtensa *xtensa = target->arch_info; + if (xtensa->common_magic == XTENSA_COMMON_MAGIC) + return &target_to_esp_xtensa(target)->semihost; + /* TODO: add riscv */ + LOG_ERROR("Unknown target arch!"); + return NULL; +} + +static int esp_semihosting_sys_seek(struct target *target, uint64_t fd, uint32_t pos, size_t whence) +{ + struct semihosting *semihosting = target->semihosting; + + semihosting->result = lseek(fd, pos, whence); + semihosting->sys_errno = errno; + LOG_TARGET_DEBUG(target, "lseek(%" PRIx64 ", %" PRIu32 " %" PRId64 ")=%d", fd, pos, semihosting->result, errno); + return ERROR_OK; +} + +int esp_semihosting_common(struct target *target) +{ + struct semihosting *semihosting = target->semihosting; + if (!semihosting) + /* Silently ignore if the semihosting field was not set. */ + return ERROR_OK; + + int retval = ERROR_NOT_IMPLEMENTED; + + /* Enough space to hold 4 long words. */ + uint8_t fields[4 * 8]; + + /* + * By default return an error. + * The actual result must be set by each function + */ + semihosting->result = -1; + semihosting->sys_errno = EIO; + + LOG_TARGET_DEBUG(target, "op=0x%x, param=0x%" PRIx64, semihosting->op, semihosting->param); + + switch (semihosting->op) { + case ESP_SEMIHOSTING_SYS_DRV_INFO: + /* Return success to make esp-idf application happy */ + retval = ERROR_OK; + semihosting->result = 0; + semihosting->sys_errno = 0; + break; + + case ESP_SEMIHOSTING_SYS_SEEK: + retval = semihosting_read_fields(target, 3, fields); + if (retval == ERROR_OK) { + uint64_t fd = semihosting_get_field(target, 0, fields); + uint32_t pos = semihosting_get_field(target, 1, fields); + size_t whence = semihosting_get_field(target, 2, fields); + retval = esp_semihosting_sys_seek(target, fd, pos, whence); + } + break; + + case ESP_SEMIHOSTING_SYS_APPTRACE_INIT: + case ESP_SEMIHOSTING_SYS_DEBUG_STUBS_INIT: + case ESP_SEMIHOSTING_SYS_BREAKPOINT_SET: + case ESP_SEMIHOSTING_SYS_WATCHPOINT_SET: + /* For the time being only riscv chips support these commands + * TODO: invoke riscv custom command handler */ + break; + } + + return retval; +} + +int esp_semihosting_basedir_command(struct command_invocation *cmd) +{ + struct target *target = get_current_target(CMD_CTX); + + if (!target) { + LOG_ERROR("No target selected"); + return ERROR_FAIL; + } + + struct semihosting *semihosting = target->semihosting; + if (!semihosting) { + command_print(CMD, "semihosting not supported for current target"); + return ERROR_FAIL; + } + + if (!semihosting->is_active) { + if (semihosting->setup(target, true) != ERROR_OK) { + LOG_ERROR("Failed to Configure semihosting"); + return ERROR_FAIL; + } + semihosting->is_active = true; + } + + if (CMD_ARGC > 0) { + free(semihosting->basedir); + semihosting->basedir = strdup(CMD_ARGV[0]); + if (!semihosting->basedir) { + command_print(CMD, "semihosting failed to allocate memory for basedir!"); + return ERROR_FAIL; + } + } + + command_print(CMD, "DEPRECATED! semihosting base dir: %s", + semihosting->basedir ? semihosting->basedir : ""); + + return ERROR_OK; +} diff --git a/src/target/espressif/esp_semihosting.h b/src/target/espressif/esp_semihosting.h new file mode 100644 index 0000000000..bd2c0799ed --- /dev/null +++ b/src/target/espressif/esp_semihosting.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Semihosting API for Espressif chips * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_SEMIHOSTING_H +#define OPENOCD_TARGET_ESP_SEMIHOSTING_H + +/* Legacy syscalls */ +#define ESP_SYS_DRV_INFO_LEGACY 0xE0 + +/* syscalls compatible to ARM standard */ +#define ESP_SEMIHOSTING_SYS_DRV_INFO 0x100 +#define ESP_SEMIHOSTING_SYS_APPTRACE_INIT 0x101 +#define ESP_SEMIHOSTING_SYS_DEBUG_STUBS_INIT 0x102 +#define ESP_SEMIHOSTING_SYS_BREAKPOINT_SET 0x103 +#define ESP_SEMIHOSTING_SYS_WATCHPOINT_SET 0x104 +#define ESP_SEMIHOSTING_SYS_SEEK 0x105 /* custom lseek with whence */ +/* not implemented yet */ +#define ESP_SEMIHOSTING_SYS_MKDIR 0x106 +#define ESP_SEMIHOSTING_SYS_OPENDIR 0x107 +#define ESP_SEMIHOSTING_SYS_READDIR 0x108 +#define ESP_SEMIHOSTING_SYS_READDIR_R 0x109 +#define ESP_SEMIHOSTING_SYS_SEEKDIR 0x10A +#define ESP_SEMIHOSTING_SYS_TELLDIR 0x10B +#define ESP_SEMIHOSTING_SYS_CLOSEDIR 0x10C +#define ESP_SEMIHOSTING_SYS_RMDIR 0x10D +#define ESP_SEMIHOSTING_SYS_ACCESS 0x10E +#define ESP_SEMIHOSTING_SYS_TRUNCATE 0x10F +#define ESP_SEMIHOSTING_SYS_UTIME 0x110 +#define ESP_SEMIHOSTING_SYS_FSTAT 0x111 +#define ESP_SEMIHOSTING_SYS_STAT 0x112 +#define ESP_SEMIHOSTING_SYS_FSYNC 0x113 +#define ESP_SEMIHOSTING_SYS_LINK 0x114 +#define ESP_SEMIHOSTING_SYS_UNLINK 0x115 + +/** + * Semihost calls handling operations. + */ +struct esp_semihost_ops { + /** Callback called before handling semihost call */ + int (*prepare)(struct target *target); +}; + +struct esp_semihost_data { + bool need_resume; + struct esp_semihost_ops *ops; +}; + +int esp_semihosting_common(struct target *target); +int esp_semihosting_basedir_command(struct command_invocation *cmd); + +#endif /* OPENOCD_TARGET_ESP_SEMIHOSTING_H */ diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c index cc2888b0de..4cadcb3301 100644 --- a/src/target/espressif/esp_xtensa.c +++ b/src/target/espressif/esp_xtensa.c @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Espressif Xtensa target API for OpenOCD * * Copyright (C) 2019 Espressif Systems Ltd. * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -13,15 +12,71 @@ #include <stdbool.h> #include <stdint.h> #include <target/smp.h> -#include "esp_xtensa.h" #include <target/register.h> +#include "esp.h" +#include "esp_xtensa.h" +#include "esp_xtensa_apptrace.h" +#include "esp_semihosting.h" +#include "esp_xtensa_algorithm.h" + +#define ESP_XTENSA_DBGSTUBS_UPDATE_DATA_ENTRY(_e_) \ + do { \ + uint32_t __internal_val = (_e_); \ + if (!xtensa_data_addr_valid(target, __internal_val)) { \ + LOG_ERROR("No valid stub data entry found (0x%" PRIx32 ")!", __internal_val); \ + return; \ + } \ + } while (0) + +#define ESP_XTENSA_DBGSTUBS_UPDATE_CODE_ENTRY(_e_) \ + do { \ + uint32_t __internal_val = (_e_); \ + if (__internal_val == 0) { \ + LOG_ERROR("No valid stub code entry found (0x%" PRIx32 ")!", __internal_val); \ + return; \ + } \ + } while (0) + +static void esp_xtensa_dbgstubs_info_update(struct target *target); +static void esp_xtensa_dbgstubs_addr_check(struct target *target); + +static int esp_xtensa_dbgstubs_restore(struct target *target) +{ + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + + if (esp_xtensa->esp.dbg_stubs.base == 0) + return ERROR_OK; + + LOG_TARGET_INFO(target, "Restore debug stubs address %" PRIx32, esp_xtensa->esp.dbg_stubs.base); + int res = esp_xtensa_apptrace_status_reg_write(target, esp_xtensa->esp.dbg_stubs.base); + if (res != ERROR_OK) { + LOG_ERROR("Failed to write trace status (%d)!", res); + return res; + } + return ERROR_OK; +} +int esp_xtensa_on_halt(struct target *target) +{ + /* debug stubs can be used in HALTED state only, so it is OK to get info about them here */ + esp_xtensa_dbgstubs_info_update(target); + return ERROR_OK; +} int esp_xtensa_init_arch_info(struct target *target, struct esp_xtensa_common *esp_xtensa, - const struct xtensa_config *xtensa_cfg, - struct xtensa_debug_module_config *dm_cfg) + struct xtensa_debug_module_config *dm_cfg, + const struct esp_semihost_ops *semihost_ops) { - return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg); + int ret = xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg); + if (ret != ERROR_OK) + return ret; + ret = esp_common_init(&esp_xtensa->esp, &xtensa_algo_hw); + if (ret != ERROR_OK) + return ret; + + esp_xtensa->semihost.ops = (struct esp_semihost_ops *)semihost_ops; + esp_xtensa->apptrace.hw = &esp_xtensa_apptrace_hw; + return ERROR_OK; } int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target) @@ -33,6 +88,11 @@ void esp_xtensa_target_deinit(struct target *target) { LOG_DEBUG("start"); + if (target_was_examined(target)) { + int ret = esp_xtensa_dbgstubs_restore(target); + if (ret != ERROR_OK) + return; + } xtensa_target_deinit(target); free(target_to_esp_xtensa(target)); /* same as free(xtensa) */ } @@ -44,7 +104,68 @@ int esp_xtensa_arch_state(struct target *target) int esp_xtensa_poll(struct target *target) { - return xtensa_poll(target); + struct xtensa *xtensa = target_to_xtensa(target); + struct esp_xtensa_common *esp_xtensa_common = target_to_esp_xtensa(target); + + int ret = xtensa_poll(target); + + if (xtensa_dm_power_status_get(&xtensa->dbg_mod) & PWRSTAT_COREWASRESET(xtensa)) { + LOG_TARGET_DEBUG(target, "Clear debug stubs info"); + memset(&esp_xtensa_common->esp.dbg_stubs, 0, sizeof(esp_xtensa_common->esp.dbg_stubs)); + } + if (target->state != TARGET_DEBUG_RUNNING) + esp_xtensa_dbgstubs_addr_check(target); + return ret; +} + +static void esp_xtensa_dbgstubs_addr_check(struct target *target) +{ + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + uint32_t vec_addr = 0; + + if (esp_xtensa->esp.dbg_stubs.base != 0) + return; + + int res = esp_xtensa_apptrace_status_reg_read(target, &vec_addr); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read debug stubs address location (%d)!", res); + return; + } + if (xtensa_data_addr_valid(target, vec_addr)) { + LOG_TARGET_INFO(target, "Detected debug stubs @ %" PRIx32, vec_addr); + res = esp_xtensa_apptrace_status_reg_write(target, 0); + if (res != ERROR_OK) + LOG_ERROR("Failed to clear debug stubs address location (%d)!", res); + esp_xtensa->esp.dbg_stubs.base = vec_addr; + } +} + +static void esp_xtensa_dbgstubs_info_update(struct target *target) +{ + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + + if (esp_xtensa->esp.dbg_stubs.base == 0 || esp_xtensa->esp.dbg_stubs.entries_count != 0) + return; + + int res = esp_dbgstubs_table_read(target, &esp_xtensa->esp.dbg_stubs); + if (res != ERROR_OK) + return; + if (esp_xtensa->esp.dbg_stubs.entries_count == 0) + return; + + /* read debug stubs descriptor */ + ESP_XTENSA_DBGSTUBS_UPDATE_DATA_ENTRY(esp_xtensa->esp.dbg_stubs.entries[ESP_DBG_STUB_DESC]); + res = target_read_buffer(target, esp_xtensa->esp.dbg_stubs.entries[ESP_DBG_STUB_DESC], + sizeof(struct esp_dbg_stubs_desc), + (uint8_t *)&esp_xtensa->esp.dbg_stubs.desc); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read debug stubs descriptor (%d)!", res); + return; + } + ESP_XTENSA_DBGSTUBS_UPDATE_CODE_ENTRY(esp_xtensa->esp.dbg_stubs.desc.tramp_addr); + ESP_XTENSA_DBGSTUBS_UPDATE_DATA_ENTRY(esp_xtensa->esp.dbg_stubs.desc.min_stack_addr); + ESP_XTENSA_DBGSTUBS_UPDATE_CODE_ENTRY(esp_xtensa->esp.dbg_stubs.desc.data_alloc); + ESP_XTENSA_DBGSTUBS_UPDATE_CODE_ENTRY(esp_xtensa->esp.dbg_stubs.desc.data_free); } int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint) @@ -58,3 +179,75 @@ int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *break return xtensa_breakpoint_remove(target, breakpoint); /* flash breakpoints will be handled in another patch */ } + +int esp_xtensa_profiling(struct target *target, uint32_t *samples, + uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds) +{ + struct timeval timeout, now; + struct xtensa *xtensa = target_to_xtensa(target); + int retval = ERROR_OK; + int res; + + /* Vary samples per pass to avoid sampling a periodic function periodically */ + #define MIN_PASS 200 + #define MAX_PASS 1000 + + gettimeofday(&timeout, NULL); + timeval_add_time(&timeout, seconds, 0); + + uint8_t buf[sizeof(uint32_t) * MAX_PASS]; + + /* Capture one sample to verify the register is present and working */ + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DEBUGPC, buf); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_TARGET_INFO(target, "Failed to read DEBUGPC, fallback to stop-and-go"); + return target_profiling_default(target, samples, max_num_samples, num_samples, seconds); + } else if (buf[0] == 0 && buf[1] == 0 && buf[2] == 0 && buf[3] == 0) { + LOG_TARGET_INFO(target, "NULL DEBUGPC, fallback to stop-and-go"); + return target_profiling_default(target, samples, max_num_samples, num_samples, seconds); + } + + LOG_TARGET_INFO(target, "Starting XTENSA DEBUGPC profiling. Sampling as fast as we can..."); + + /* Make sure the target is running */ + target_poll(target); + if (target->state == TARGET_HALTED) + retval = target_resume(target, true, 0, false, false); + + if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "Error while resuming target"); + return retval; + } + + uint32_t sample_count = 0; + + for (;;) { + uint32_t remaining = max_num_samples - sample_count; + uint32_t this_pass = rand() % (MAX_PASS - MIN_PASS) + MIN_PASS; + this_pass = this_pass > remaining ? remaining : this_pass; + for (uint32_t i = 0; i < this_pass; ++i) + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DEBUGPC, buf + i * sizeof(uint32_t)); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_TARGET_ERROR(target, "Failed to read DEBUGPC!"); + return res; + } + + for (uint32_t i = 0; i < this_pass; ++i) { + uint32_t sample32 = buf_get_u32(buf + i * sizeof(uint32_t), 0, 32); + samples[sample_count++] = sample32; + } + gettimeofday(&now, NULL); + if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) { + LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count); + break; + } + } + + *num_samples = sample_count; + return retval; + + #undef MIN_PASS + #undef MAX_PASS +} diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h index e3507e31e0..56c903f607 100644 --- a/src/target/espressif/esp_xtensa.h +++ b/src/target/espressif/esp_xtensa.h @@ -3,18 +3,22 @@ /*************************************************************************** * Generic ESP xtensa target implementation for OpenOCD * * Copyright (C) 2019 Espressif Systems Ltd. * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifndef OPENOCD_TARGET_ESP_XTENSA_H #define OPENOCD_TARGET_ESP_XTENSA_H -#include <helper/command.h> #include <target/target.h> #include <target/xtensa/xtensa.h> +#include "esp_semihosting.h" +#include "esp.h" +#include "esp_xtensa_apptrace.h" struct esp_xtensa_common { struct xtensa xtensa; /* must be the first element */ + struct esp_common esp; + struct esp_semihost_data semihost; + struct esp_xtensa_apptrace_info apptrace; }; static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *target) @@ -24,8 +28,8 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ int esp_xtensa_init_arch_info(struct target *target, struct esp_xtensa_common *esp_xtensa, - const struct xtensa_config *xtensa_cfg, - struct xtensa_debug_module_config *dm_cfg); + struct xtensa_debug_module_config *dm_cfg, + const struct esp_semihost_ops *semihost_ops); int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target); void esp_xtensa_target_deinit(struct target *target); int esp_xtensa_arch_state(struct target *target); @@ -33,5 +37,9 @@ void esp_xtensa_queue_tdi_idle(struct target *target); int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint); int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint); int esp_xtensa_poll(struct target *target); +int esp_xtensa_profiling(struct target *target, uint32_t *samples, + uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); + +int esp_xtensa_on_halt(struct target *target); #endif /* OPENOCD_TARGET_ESP_XTENSA_H */ diff --git a/src/target/espressif/esp_xtensa_algorithm.c b/src/target/espressif/esp_xtensa_algorithm.c new file mode 100644 index 0000000000..68005cbf2c --- /dev/null +++ b/src/target/espressif/esp_xtensa_algorithm.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Module to run arbitrary code on Xtensa using OpenOCD * + * Copyright (C) 2019 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include <config.h> +#endif + +#include <target/xtensa/xtensa.h> +#include "esp_xtensa_algorithm.h" + +static int esp_xtensa_algo_init(struct target *target, struct esp_algorithm_run_data *run, + uint32_t num_args, va_list ap); +static int esp_xtensa_algo_cleanup(struct target *target, struct esp_algorithm_run_data *run); +static const uint8_t *esp_xtensa_stub_tramp_get(struct target *target, size_t *size); + +const struct esp_algorithm_hw xtensa_algo_hw = { + .algo_init = esp_xtensa_algo_init, + .algo_cleanup = esp_xtensa_algo_cleanup, + .stub_tramp_get = esp_xtensa_stub_tramp_get, +}; + +/* Generated from contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.S */ +static const uint8_t esp_xtensa_stub_tramp_win[] = { +#include "../../../contrib/loaders/trampoline/espressif/xtensa/esp_xtensa_stub_tramp_win.inc" +}; + +static const uint8_t *esp_xtensa_stub_tramp_get(struct target *target, size_t *size) +{ + struct xtensa *xtensa = target_to_xtensa(target); + + if (!xtensa->core_config->windowed) { + LOG_ERROR("Running stubs is not supported for cores without windowed registers option!"); + return NULL; + } + *size = sizeof(esp_xtensa_stub_tramp_win); + return esp_xtensa_stub_tramp_win; +} + +static int esp_xtensa_algo_regs_init_start(struct target *target, struct esp_algorithm_run_data *run) +{ + uint32_t stack_addr = run->stub.stack_addr; + + LOG_TARGET_DEBUG(target, "Check stack addr 0x%x", stack_addr); + if (stack_addr & 0xFUL) { + stack_addr &= ~0xFUL; + LOG_TARGET_DEBUG(target, "Adjust stack addr to 0x%x", stack_addr); + } + stack_addr -= 16; + struct reg_param *params = run->reg_args.params; + init_reg_param(¶ms[0], "a0", 32, PARAM_OUT); /*TODO: move to tramp */ + init_reg_param(¶ms[1], "a1", 32, PARAM_OUT); + init_reg_param(¶ms[2], "a8", 32, PARAM_OUT); + init_reg_param(¶ms[3], "windowbase", 32, PARAM_OUT); /*TODO: move to tramp */ + init_reg_param(¶ms[4], "windowstart", 32, PARAM_OUT); /*TODO: move to tramp */ + init_reg_param(¶ms[5], "ps", 32, PARAM_OUT); + buf_set_u32(params[0].value, 0, 32, 0); /* a0 TODO: move to tramp */ + buf_set_u32(params[1].value, 0, 32, stack_addr); /* a1 */ + buf_set_u32(params[2].value, 0, 32, run->stub.entry); /* a8 */ + buf_set_u32(params[3].value, 0, 32, 0x0); /* initial window base TODO: move to tramp */ + buf_set_u32(params[4].value, 0, 32, 0x1); /* initial window start TODO: move to tramp */ + buf_set_u32(params[5].value, 0, 32, 0x60025); /* enable WOE, UM and debug interrupts level (6) */ + return ERROR_OK; +} + +static int esp_xtensa_algo_init(struct target *target, struct esp_algorithm_run_data *run, + uint32_t num_args, va_list ap) +{ + enum xtensa_mode core_mode = XT_MODE_ANY; + static const char *const arg_regs[] = { "a2", "a3", "a4", "a5", "a6" }; + + if (!run) + return ERROR_FAIL; + + if (num_args > ARRAY_SIZE(arg_regs)) { + LOG_ERROR("Too many algo user args %u! Max %zu args are supported.", num_args, ARRAY_SIZE(arg_regs)); + return ERROR_FAIL; + } + + struct xtensa_algorithm *ainfo = calloc(1, sizeof(struct xtensa_algorithm)); + if (!ainfo) { + LOG_ERROR("Unable to allocate memory"); + return ERROR_FAIL; + } + + if (run->arch_info) { + struct xtensa_algorithm *xtensa_algo = run->arch_info; + core_mode = xtensa_algo->core_mode; + } + + run->reg_args.first_user_param = ESP_XTENSA_STUB_ARGS_FUNC_START; + run->reg_args.count = run->reg_args.first_user_param + num_args; + if (num_args == 0) + run->reg_args.count++; /* a2 reg is used as the 1st arg and return code */ + LOG_DEBUG("reg params count %d (%d/%d).", + run->reg_args.count, + run->reg_args.first_user_param, + num_args); + run->reg_args.params = calloc(run->reg_args.count, sizeof(struct reg_param)); + if (!run->reg_args.params) { + free(ainfo); + LOG_ERROR("Unable to allocate memory"); + return ERROR_FAIL; + } + + esp_xtensa_algo_regs_init_start(target, run); + + init_reg_param(&run->reg_args.params[run->reg_args.first_user_param + 0], "a2", 32, PARAM_IN_OUT); + + if (num_args > 0) { + uint32_t arg = va_arg(ap, uint32_t); + esp_algorithm_user_arg_set_uint(run, 0, arg); + LOG_DEBUG("Set arg[0] = %d (%s)", arg, run->reg_args.params[run->reg_args.first_user_param + 0].reg_name); + } else { + esp_algorithm_user_arg_set_uint(run, 0, 0); + } + + for (unsigned int i = 1; i < num_args; i++) { + uint32_t arg = va_arg(ap, uint32_t); + init_reg_param(&run->reg_args.params[run->reg_args.first_user_param + i], (char *)arg_regs[i], 32, PARAM_OUT); + esp_algorithm_user_arg_set_uint(run, i, arg); + LOG_DEBUG("Set arg[%d] = %d (%s)", i, arg, run->reg_args.params[run->reg_args.first_user_param + i].reg_name); + } + + ainfo->core_mode = core_mode; + run->stub.ainfo = ainfo; + return ERROR_OK; +} + +static int esp_xtensa_algo_cleanup(struct target *target, struct esp_algorithm_run_data *run) +{ + free(run->stub.ainfo); + for (uint32_t i = 0; i < run->reg_args.count; i++) + destroy_reg_param(&run->reg_args.params[i]); + free(run->reg_args.params); + return ERROR_OK; +} diff --git a/src/target/espressif/esp_xtensa_algorithm.h b/src/target/espressif/esp_xtensa_algorithm.h new file mode 100644 index 0000000000..36fa1a331b --- /dev/null +++ b/src/target/espressif/esp_xtensa_algorithm.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Module to run arbitrary code on Xtensa using OpenOCD * + * Copyright (C) 2019 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_XTENSA_ALGO_H +#define OPENOCD_TARGET_ESP_XTENSA_ALGO_H + +#include <target/xtensa/xtensa.h> +#include <target/espressif/esp_algorithm.h> + +/** Index of the first user-defined algo arg. @see algorithm_stub */ +#define ESP_XTENSA_STUB_ARGS_FUNC_START 6 + +extern const struct esp_algorithm_hw xtensa_algo_hw; + +#endif /* OPENOCD_TARGET_XTENSA_ALGO_H */ diff --git a/src/target/espressif/esp_xtensa_apptrace.c b/src/target/espressif/esp_xtensa_apptrace.c new file mode 100644 index 0000000000..313f6ce778 --- /dev/null +++ b/src/target/espressif/esp_xtensa_apptrace.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Xtensa application tracing module for OpenOCD * + * Copyright (C) 2017 Espressif Systems Ltd. * + ***************************************************************************/ + +/* + How it works? + https://github.com/espressif/esp-idf/blob/master/components/app_trace/port/xtensa/port.c#L8 +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/align.h> +#include <target/xtensa/xtensa.h> +#include <target/xtensa/xtensa_debug_module.h> +#include "esp_xtensa_apptrace.h" + +/* TRAX is disabled, so we use its registers for our own purposes + * | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 | + */ +#define XTENSA_APPTRACE_CTRL_REG XDMREG_DELAYCNT +#define XTENSA_APPTRACE_BLOCK_ID_MSK 0x7FUL +#define XTENSA_APPTRACE_BLOCK_ID_MAX XTENSA_APPTRACE_BLOCK_ID_MSK +/* if non-zero then apptrace code entered the critical section and the value is an address of the + * critical section's exit point */ +#define XTENSA_APPTRACE_STAT_REG XDMREG_TRIGGERPC + +#define XTENSA_APPTRACE_BLOCK_LEN_MSK 0x7FFFUL +#define XTENSA_APPTRACE_BLOCK_LEN(_l_) ((_l_) & XTENSA_APPTRACE_BLOCK_LEN_MSK) +#define XTENSA_APPTRACE_BLOCK_LEN_GET(_v_) ((_v_) & XTENSA_APPTRACE_BLOCK_LEN_MSK) +#define XTENSA_APPTRACE_BLOCK_ID(_id_) (((_id_) & XTENSA_APPTRACE_BLOCK_ID_MSK) << 15) +#define XTENSA_APPTRACE_BLOCK_ID_GET(_v_) (((_v_) >> 15) & XTENSA_APPTRACE_BLOCK_ID_MSK) +#define XTENSA_APPTRACE_HOST_DATA BIT(22) +#define XTENSA_APPTRACE_HOST_CONNECT BIT(23) + +static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target); +static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target); +static int esp_xtensa_apptrace_buffs_write(struct target *target, + uint32_t bufs_num, + uint32_t buf_sz[], + const uint8_t *bufs[], + uint32_t block_id, + bool ack, + bool data); + +struct esp32_apptrace_hw esp_xtensa_apptrace_hw = { + .max_block_id = XTENSA_APPTRACE_BLOCK_ID_MAX, + .max_block_size_get = esp_xtensa_apptrace_block_max_size_get, + .status_reg_read = esp_xtensa_apptrace_status_reg_read, + .ctrl_reg_write = esp_xtensa_apptrace_ctrl_reg_write, + .ctrl_reg_read = esp_xtensa_apptrace_ctrl_reg_read, + .data_len_read = esp_xtensa_apptrace_data_len_read, + .data_read = esp_xtensa_apptrace_data_read, + .usr_block_max_size_get = esp_xtensa_apptrace_usr_block_max_size_get, + .buffs_write = esp_xtensa_apptrace_buffs_write, + .leave_trace_crit_section_start = esp_xtensa_apptrace_leave_crit_section_start, + .leave_trace_crit_section_stop = esp_xtensa_apptrace_leave_crit_section_stop, +}; + +uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + struct xtensa_trace_status trace_status; + struct xtensa_trace_config trace_config; + uint32_t max_trace_block_sz; + + int res = xtensa_dm_trace_status_read(&xtensa->dbg_mod, &trace_status); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read TRAX status (%d)!", res); + return 0; + } + + max_trace_block_sz = BIT(((trace_status.stat >> 8) & 0x1f) - 2) * 4; + res = xtensa_dm_trace_config_read(&xtensa->dbg_mod, &trace_config); + if (res != ERROR_OK) { + LOG_ERROR("Failed to read TRAX config (%d)!", res); + return 0; + } + LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32, + trace_config.ctrl, + trace_config.memaddr_start, + trace_config.memaddr_end, + trace_config.addr); + + return max_trace_block_sz; +} + +uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target) +{ + return esp_xtensa_apptrace_block_max_size_get(target) - sizeof(struct esp_apptrace_host2target_hdr); +} + +int esp_xtensa_apptrace_data_len_read(struct target *target, + uint32_t *block_id, + uint32_t *len) +{ + return esp_xtensa_apptrace_ctrl_reg_read(target, block_id, len, NULL); +} + +int esp_xtensa_apptrace_usr_block_write(struct target *target, + uint32_t block_id, + const uint8_t *data, + uint32_t size) +{ + return esp_apptrace_usr_block_write(&esp_xtensa_apptrace_hw, target, block_id, data, size); +} + +static int esp_xtensa_apptrace_data_reverse_read(struct xtensa *xtensa, + uint32_t size, + uint8_t *buffer, + uint8_t *unal_bytes) +{ + int res = 0; + uint32_t rd_sz = ALIGN_UP(size, 4); + + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - rd_sz) / 4); + if (res != ERROR_OK) + return res; + if (!IS_ALIGNED(size, 4)) { + res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes); + if (res != ERROR_OK) + return res; + } + for (unsigned int i = size / 4; i != 0; i--) { + res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[(i - 1) * 4]); + if (res != ERROR_OK) + return res; + } + return ERROR_OK; +} + +static int esp_xtensa_apptrace_data_normal_read(struct xtensa *xtensa, + uint32_t size, + uint8_t *buffer, + uint8_t *unal_bytes) +{ + int res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0); + if (res != ERROR_OK) + return res; + for (unsigned int i = 0; i < size / 4; i++) { + res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[i * 4]); + if (res != ERROR_OK) + return res; + } + if (!IS_ALIGNED(size, 4)) { + res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes); + if (res != ERROR_OK) + return res; + } + return ERROR_OK; +} + +int esp_xtensa_apptrace_data_read(struct target *target, + uint32_t size, + uint8_t *buffer, + uint32_t block_id, + bool ack) +{ + struct xtensa *xtensa = target_to_xtensa(target); + int res; + uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT | XTENSA_APPTRACE_BLOCK_ID(block_id) | + XTENSA_APPTRACE_BLOCK_LEN(0); + uint8_t unal_bytes[4]; + + LOG_DEBUG("Read data on target (%s)", target_name(target)); + if (xtensa->core_config->trace.reversed_mem_access) + res = esp_xtensa_apptrace_data_reverse_read(xtensa, size, buffer, unal_bytes); + else + res = esp_xtensa_apptrace_data_normal_read(xtensa, size, buffer, unal_bytes); + if (res != ERROR_OK) + return res; + if (ack) { + LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target)); + res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp); + if (res != ERROR_OK) + return res; + } + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_ERROR("Failed to exec JTAG queue!"); + return res; + } + if (!IS_ALIGNED(size, 4)) { + /* copy the last unaligned bytes */ + memcpy(buffer + ALIGN_DOWN(size, 4), unal_bytes, size & 0x3UL); + } + return ERROR_OK; +} + +int esp_xtensa_apptrace_ctrl_reg_write(struct target *target, + uint32_t block_id, + uint32_t len, + bool conn, + bool data) +{ + struct xtensa *xtensa = target_to_xtensa(target); + uint32_t tmp = (conn ? XTENSA_APPTRACE_HOST_CONNECT : 0) | + (data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) | + XTENSA_APPTRACE_BLOCK_LEN(len); + + xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp); + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_ERROR("Failed to exec JTAG queue!"); + return res; + } + + return ERROR_OK; +} + +int esp_xtensa_apptrace_ctrl_reg_read(struct target *target, + uint32_t *block_id, + uint32_t *len, + bool *conn) +{ + struct xtensa *xtensa = target_to_xtensa(target); + uint8_t tmp[4]; + + xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp); + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) + return res; + uint32_t val = target_buffer_get_u32(target, tmp); + if (block_id) + *block_id = XTENSA_APPTRACE_BLOCK_ID_GET(val); + if (len) + *len = XTENSA_APPTRACE_BLOCK_LEN_GET(val); + if (conn) + *conn = val & XTENSA_APPTRACE_HOST_CONNECT; + return ERROR_OK; +} + +int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat) +{ + struct xtensa *xtensa = target_to_xtensa(target); + uint8_t tmp[4]; + + int res = xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_STAT_REG, tmp); + if (res != ERROR_OK) + return res; + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_ERROR("Failed to exec JTAG queue!"); + return res; + } + *stat = buf_get_u32(tmp, 0, 32); + return ERROR_OK; +} + +int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat) +{ + struct xtensa *xtensa = target_to_xtensa(target); + + xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_STAT_REG, stat); + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_ERROR("Failed to exec JTAG queue!"); + return res; + } + return ERROR_OK; +} + +static int esp_xtensa_swdbg_activate(struct target *target, int enab) +{ + struct xtensa *xtensa = target_to_xtensa(target); + + xtensa_queue_dbg_reg_write(xtensa, enab ? XDMREG_DCRSET : XDMREG_DCRCLR, OCDDCR_DEBUGSWACTIVE); + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_TARGET_ERROR(target, "writing DCR failed"); + return res; + } + + return ERROR_OK; +} + +static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target) +{ + /* TODO: not sure that we need this, but it seems that we fail to leave tracing critical + *section w/o this */ + int res = esp_xtensa_swdbg_activate(target, 1 /*enable*/); + if (res != ERROR_OK) { + LOG_ERROR("Failed to activate SW debug (%d)!", res); + return res; + } + return ERROR_OK; +} + +static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target) +{ + int res = esp_xtensa_swdbg_activate(target, 0 /*disable*/); + if (res != ERROR_OK) { + LOG_ERROR("Failed to activate SW debug (%d)!", res); + return res; + } + return ERROR_OK; +} + +static int esp_xtensa_apptrace_queue_reverse_write(struct target *target, uint32_t bufs_num, + uint32_t buf_sz[], const uint8_t *bufs[]) +{ + int res = ERROR_OK; + uint32_t cached_bytes = 0, total_sz = 0; + uint8_t cached_data8[sizeof(uint32_t)] = { 0 }; + uint32_t cached_data32 = 0; + + struct xtensa *xtensa = target_to_xtensa(target); + + for (uint32_t i = 0; i < bufs_num; i++) + total_sz += buf_sz[i]; + if (!IS_ALIGNED(total_sz, 4)) { + cached_bytes = sizeof(uint32_t) - (total_sz & 0x3UL); + total_sz = ALIGN_UP(total_sz, 4); + } + xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - total_sz) / 4); + for (uint32_t i = bufs_num; i > 0; i--) { + uint32_t bsz = buf_sz[i - 1]; + const uint8_t *cur_buf = &bufs[i - 1][bsz]; + uint32_t bytes_to_cache; + /* if there are cached bytes from the previous buffer, combine them with the last + * from the current buffer */ + if (cached_bytes) { + if ((cached_bytes + bsz) < sizeof(uint32_t)) + bytes_to_cache = bsz; + else + bytes_to_cache = sizeof(uint32_t) - cached_bytes; + memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache], + cur_buf - bytes_to_cache, + bytes_to_cache); + cached_data32 = target_buffer_get_u32(target, cached_data8); + cached_bytes += bytes_to_cache; + if (cached_bytes < sizeof(uint32_t)) + continue; + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32); + if (res != ERROR_OK) + return res; + bsz -= bytes_to_cache; + cur_buf -= bytes_to_cache; + memset(cached_data8, 0x00, sizeof(cached_data8)); + cached_bytes = 0; + } + /* write full dwords */ + for (unsigned int k = bsz; k >= sizeof(uint32_t); k -= sizeof(uint32_t)) { + uint32_t temp = target_buffer_get_u32(target, cur_buf - sizeof(uint32_t)); + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp); + if (res != ERROR_OK) + return res; + cur_buf -= sizeof(uint32_t); + } + /* if there are bytes to be cached (1..3) */ + bytes_to_cache = bsz & 0x3UL; + if (bytes_to_cache > 0) { + if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) { + /* filling the cache buffer from the end to beginning */ + uint32_t to_copy = sizeof(uint32_t) - cached_bytes; + memcpy(&cached_data8[0], cur_buf - to_copy, to_copy); + cached_data32 = target_buffer_get_u32(target, cached_data8); + /* write full word of cached bytes */ + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32); + if (res != ERROR_OK) + return res; + /* cache remaining bytes */ + memset(cached_data8, 0x00, sizeof(cached_data8)); + cur_buf -= to_copy; + to_copy = bytes_to_cache + cached_bytes - sizeof(uint32_t); + memcpy(&cached_data8[sizeof(uint32_t) - to_copy], cur_buf - to_copy, to_copy); + cached_bytes = to_copy; + } else { + /* filling the cache buffer from the end to beginning */ + memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache], + cur_buf - bytes_to_cache, + bytes_to_cache); + cached_bytes += bytes_to_cache; + } + } + } + return ERROR_OK; +} + +static int esp_xtensa_apptrace_queue_normal_write(struct target *target, uint32_t bufs_num, + uint32_t buf_sz[], const uint8_t *bufs[]) +{ + int res = ERROR_OK; + uint32_t cached_bytes = 0; + uint8_t cached_data8[4] = { 0 }; + uint32_t cached_data32 = 0; + + struct xtensa *xtensa = target_to_xtensa(target); + + /* | 1 | 2 | 1 | 2 | 4 |.......| + * | 4 | 4 | 4 | */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0); + for (unsigned int i = 0; i < bufs_num; i++) { + uint32_t bsz = buf_sz[i]; + const uint8_t *cur_buf = bufs[i]; + uint32_t bytes_to_cache; + /* if there are cached bytes from the previous buffer, combine them with the last + * from the current buffer */ + if (cached_bytes) { + if ((cached_bytes + bsz) < sizeof(uint32_t)) + bytes_to_cache = bsz; + else + bytes_to_cache = sizeof(uint32_t) - cached_bytes; + memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache); + cached_bytes += bytes_to_cache; + if (cached_bytes < sizeof(uint32_t)) + continue; + cached_data32 = target_buffer_get_u32(target, cached_data8); + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32); + if (res != ERROR_OK) + return res; + bsz -= bytes_to_cache; + cur_buf += bytes_to_cache; + memset(cached_data8, 0x00, sizeof(cached_data8)); + cached_bytes = 0; + } + /* write full dwords */ + for (unsigned int k = 0; (k + sizeof(uint32_t)) <= bsz; k += sizeof(uint32_t)) { + uint32_t temp = target_buffer_get_u32(target, cur_buf); + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp); + if (res != ERROR_OK) + return res; + cur_buf += sizeof(uint32_t); + } + /* if there are bytes to be cached (1..3) */ + bytes_to_cache = bsz & 0x3UL; + if (bytes_to_cache > 0) { + if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) { + memcpy(&cached_data8[0], cur_buf, sizeof(uint32_t) - cached_bytes); + cached_data32 = target_buffer_get_u32(target, cached_data8); + /* write full word of cached bytes */ + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32); + if (res != ERROR_OK) + return res; + /* cache remaining bytes */ + memset(cached_data8, 0x00, sizeof(cached_data8)); + cur_buf += sizeof(uint32_t) - cached_bytes; + cached_bytes = bytes_to_cache + cached_bytes - sizeof(uint32_t); + memcpy(&cached_data8[0], cur_buf, cached_bytes); + } else { + memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache); + cached_bytes += bytes_to_cache; + } + } + } + if (cached_bytes) { + /* write remaining cached bytes */ + cached_data32 = target_buffer_get_u32(target, cached_data8); + res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32); + if (res != ERROR_OK) + return res; + } + return ERROR_OK; +} + +static int esp_xtensa_apptrace_buffs_write(struct target *target, + uint32_t bufs_num, + uint32_t buf_sz[], + const uint8_t *bufs[], + uint32_t block_id, + bool ack, + bool data) +{ + struct xtensa *xtensa = target_to_xtensa(target); + int res = ERROR_OK; + uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT | + (data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) | + XTENSA_APPTRACE_BLOCK_LEN(0); + + if (xtensa->core_config->trace.reversed_mem_access) + res = esp_xtensa_apptrace_queue_reverse_write(target, bufs_num, buf_sz, bufs); + else + res = esp_xtensa_apptrace_queue_normal_write(target, bufs_num, buf_sz, bufs); + if (res != ERROR_OK) + return res; + if (ack) { + LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target)); + res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp); + if (res != ERROR_OK) + return res; + } + xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_ERROR("Failed to exec JTAG queue!"); + return res; + } + return ERROR_OK; +} diff --git a/src/target/espressif/esp_xtensa_apptrace.h b/src/target/espressif/esp_xtensa_apptrace.h new file mode 100644 index 0000000000..0a9be731fe --- /dev/null +++ b/src/target/espressif/esp_xtensa_apptrace.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Xtensa application tracing module for OpenOCD * + * Copyright (C) 2017 Espressif Systems Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H +#define OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H + +#include "esp32_apptrace.h" + +struct esp_xtensa_apptrace_info { + const struct esp32_apptrace_hw *hw; +}; + +extern struct esp32_apptrace_hw esp_xtensa_apptrace_hw; + +int esp_xtensa_apptrace_data_len_read(struct target *target, uint32_t *block_id, uint32_t *len); +int esp_xtensa_apptrace_data_read(struct target *target, + uint32_t size, + uint8_t *buffer, + uint32_t block_id, + bool ack); +int esp_xtensa_apptrace_ctrl_reg_read(struct target *target, uint32_t *block_id, uint32_t *len, bool *conn); +int esp_xtensa_apptrace_ctrl_reg_write(struct target *target, + uint32_t block_id, + uint32_t len, + bool conn, + bool data); +int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat); +int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat); +uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target); +uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target); +int esp_xtensa_apptrace_usr_block_write(struct target *target, uint32_t block_id, const uint8_t *data, uint32_t size); + +#endif /* OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H */ diff --git a/src/target/espressif/esp_xtensa_semihosting.c b/src/target/espressif/esp_xtensa_semihosting.c new file mode 100644 index 0000000000..54e9c4b8df --- /dev/null +++ b/src/target/espressif/esp_xtensa_semihosting.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <target/semihosting_common.h> +#include <target/xtensa/xtensa_regs.h> +#include <target/xtensa/xtensa.h> +#include "esp_xtensa.h" +#include "esp_xtensa_semihosting.h" + +#define ESP_XTENSA_SYSCALL 0x41E0 /* XT_INS_BREAK(1, 14) */ +#define ESP_XTENSA_SYSCALL_SZ 3 + +#define XTENSA_SYSCALL_OP_REG XT_REG_IDX_A2 +#define XTENSA_SYSCALL_RETVAL_REG XT_REG_IDX_A2 +#define XTENSA_SYSCALL_ERRNO_REG XT_REG_IDX_A3 + +static int esp_xtensa_semihosting_setup(struct target *target, int enable) +{ + LOG_TARGET_DEBUG(target, "semihosting enable=%d", enable); + + return ERROR_OK; +} + +static int esp_xtensa_semihosting_post_result(struct target *target) +{ + /* Even with the v2 and later, errno will not retrieved from A3 reg, it is safe to set */ + xtensa_reg_set(target, XTENSA_SYSCALL_RETVAL_REG, target->semihosting->result); + xtensa_reg_set(target, XTENSA_SYSCALL_ERRNO_REG, target->semihosting->sys_errno); + return ERROR_OK; +} + +/** + * Checks and processes an ESP Xtensa semihosting request. This is meant + * to be called when the target is stopped due to a debug mode entry. + * If the value 0 is returned then there was nothing to process. A non-zero + * return value signifies that a request was processed and the target resumed, + * or an error was encountered, in which case the caller must return immediately. + * + * @param target Pointer to the ESP Xtensa target to process. + * @param retval Pointer to a location where the return code will be stored + * @return SEMIHOSTING_HANDLED if a request was processed or SEMIHOSTING_NONE with the proper retval + */ +int esp_xtensa_semihosting(struct target *target, int *retval) +{ + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + + xtensa_reg_val_t dbg_cause = xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE); + if ((dbg_cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN)) == 0) + return SEMIHOSTING_NONE; + + uint8_t brk_insn_buf[sizeof(uint32_t)] = { 0 }; + xtensa_reg_val_t pc = xtensa_reg_get(target, XT_REG_IDX_PC); + *retval = target_read_memory(target, pc, ESP_XTENSA_SYSCALL_SZ, 1, brk_insn_buf); + if (*retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "Failed to read break instruction!"); + return SEMIHOSTING_NONE; + } + + uint32_t syscall_ins = buf_get_u32(brk_insn_buf, 0, 32); + if (syscall_ins != ESP_XTENSA_SYSCALL) { + *retval = ERROR_OK; + return SEMIHOSTING_NONE; + } + + if (esp_xtensa->semihost.ops && esp_xtensa->semihost.ops->prepare) + esp_xtensa->semihost.ops->prepare(target); + + xtensa_reg_val_t a2 = xtensa_reg_get(target, XT_REG_IDX_A2); + xtensa_reg_val_t a3 = xtensa_reg_get(target, XT_REG_IDX_A3); + LOG_TARGET_DEBUG(target, "Semihosting call 0x%" PRIx32 " 0x%" PRIx32 " Base dir '%s'", + a2, + a3, + target->semihosting->basedir ? target->semihosting->basedir : ""); + + target->semihosting->op = a2; + target->semihosting->param = a3; + + *retval = semihosting_common(target); + + /* Most operations are resumable, except the two exit calls. */ + if (*retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "Semihosting operation (op: 0x%x) error! Code: %d", + target->semihosting->op, + *retval); + } + + /* Resume if target it is resumable and we are not waiting on a fileio operation to complete. */ + if (target->semihosting->is_resumable && !target->semihosting->hit_fileio) + target_to_esp_xtensa(target)->semihost.need_resume = true; + + return SEMIHOSTING_HANDLED; +} + +static int xtensa_semihosting_init(struct target *target) +{ + return semihosting_common_init(target, esp_xtensa_semihosting_setup, esp_xtensa_semihosting_post_result); +} + +int esp_xtensa_semihosting_init(struct target *target) +{ + int retval = xtensa_semihosting_init(target); + if (retval != ERROR_OK) + return retval; + target->semihosting->word_size_bytes = 4; /* 32 bits */ + target->semihosting->user_command_extension = esp_semihosting_common; + return ERROR_OK; +} diff --git a/src/target/espressif/esp_xtensa_semihosting.h b/src/target/espressif/esp_xtensa_semihosting.h new file mode 100644 index 0000000000..1da3115796 --- /dev/null +++ b/src/target/espressif/esp_xtensa_semihosting.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H +#define OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H + +#include <target/target.h> + +int esp_xtensa_semihosting_init(struct target *target); +int esp_xtensa_semihosting(struct target *target, int *retval); + +#endif /* OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H */ diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c index 7c2c72331a..b9e2156440 100644 --- a/src/target/espressif/esp_xtensa_smp.c +++ b/src/target/espressif/esp_xtensa_smp.c @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * ESP Xtensa SMP target API for OpenOCD * * Copyright (C) 2020 Espressif Systems Ltd. Co * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -14,7 +13,10 @@ #include <target/target.h> #include <target/target_type.h> #include <target/smp.h> +#include <target/semihosting_common.h> #include "esp_xtensa_smp.h" +#include "esp_xtensa_semihosting.h" +#include "esp_algorithm.h" /* Multiprocessor stuff common: @@ -92,8 +94,11 @@ int esp_xtensa_smp_soft_reset_halt(struct target *target) LOG_TARGET_DEBUG(target, "begin"); /* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU and then call xtensa_assert_reset() for all cores */ - if (target->smp && target->coreid != 0) - return ERROR_OK; + if (target->smp) { + head = list_first_entry(target->smp_targets, struct target_list, lh); + if (head->target != target) + return ERROR_OK; + } /* Reset the SoC first */ if (esp_xtensa_smp->chip_ops->reset) { res = esp_xtensa_smp->chip_ops->reset(target); @@ -111,6 +116,21 @@ int esp_xtensa_smp_soft_reset_halt(struct target *target) return ERROR_OK; } +int esp_xtensa_smp_on_halt(struct target *target) +{ + struct target_list *head; + + if (!target->smp) + return esp_xtensa_on_halt(target); + + foreach_smp_target(head, target->smp_targets) { + int res = esp_xtensa_on_halt(head->target); + if (res != ERROR_OK) + return res; + } + return ERROR_OK; +} + static struct target *get_halted_esp_xtensa_smp(struct target *target, int32_t coreid) { struct target_list *head; @@ -129,6 +149,8 @@ int esp_xtensa_smp_poll(struct target *target) { enum target_state old_state = target->state; struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target); + struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); + uint32_t old_dbg_stubs_base = esp_xtensa->esp.dbg_stubs.base; struct target_list *head; struct target *curr; bool other_core_resume_req = false; @@ -146,6 +168,16 @@ int esp_xtensa_smp_poll(struct target *target) if (ret != ERROR_OK) return ret; + if (esp_xtensa->esp.dbg_stubs.base && old_dbg_stubs_base != esp_xtensa->esp.dbg_stubs.base) { + /* debug stubs base is set only in PRO-CPU TRAX register, so sync this info */ + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + if (curr == target) + continue; + target_to_esp_xtensa(curr)->esp.dbg_stubs.base = esp_xtensa->esp.dbg_stubs.base; + } + } + if (target->smp) { if (target->state == TARGET_RESET) { esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES; @@ -181,10 +213,23 @@ int esp_xtensa_smp_poll(struct target *target) if (old_state == TARGET_DEBUG_RUNNING) { target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } else { + if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) { + if (ret == ERROR_OK && esp_xtensa->semihost.need_resume && + !esp_xtensa_smp->other_core_does_resume) { + esp_xtensa->semihost.need_resume = false; + /* Resume xtensa_resume will handle BREAK instruction. */ + ret = target_resume(target, true, 0, true, false); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to resume target"); + return ret; + } + } + return ret; + } /* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */ if (target->smp && other_core_resume_req) { /* Resume xtensa_resume will handle BREAK instruction. */ - ret = target_resume(target, 1, 0, 1, 0); + ret = target_resume(target, true, 0, true, false); if (ret != ERROR_OK) { LOG_ERROR("Failed to resume target"); return ret; @@ -254,6 +299,11 @@ static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resu if (ret != ERROR_OK) return ret; esp_xtensa_smp->other_core_does_resume = false; + struct esp_xtensa_common *curr_esp_xtensa = target_to_esp_xtensa(curr); + if (curr_esp_xtensa->semihost.need_resume) { + curr_esp_xtensa->semihost.need_resume = false; + *need_resume = true; + } } /* after all targets were updated, poll the gdb serving target */ @@ -284,8 +334,7 @@ static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_ } static int esp_xtensa_smp_resume_cores(struct target *target, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, bool debug_execution) { struct target_list *head; struct target *curr; @@ -298,7 +347,7 @@ static int esp_xtensa_smp_resume_cores(struct target *target, if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) { /* resume current address, not in SMP mode */ curr->smp = 0; - int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution); + int res = esp_xtensa_smp_resume(curr, true, 0, handle_breakpoints, debug_execution); curr->smp = 1; if (res != ERROR_OK) return res; @@ -308,10 +357,10 @@ static int esp_xtensa_smp_resume_cores(struct target *target, } int esp_xtensa_smp_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, + bool debug_execution) { int res; uint32_t smp_break; @@ -370,9 +419,9 @@ int esp_xtensa_smp_resume(struct target *target, } int esp_xtensa_smp_step(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints) + bool handle_breakpoints) { int res; uint32_t smp_break = 0; @@ -449,13 +498,90 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w return ERROR_OK; } +int esp_xtensa_smp_run_func_image(struct target *target, struct esp_algorithm_run_data *run, uint32_t num_args, ...) +{ + struct target *run_target = target; + struct target_list *head; + va_list ap; + uint32_t smp_break = 0; + int res; + + if (target->smp) { + /* find first HALTED and examined core */ + foreach_smp_target(head, target->smp_targets) { + run_target = head->target; + if (target_was_examined(run_target) && run_target->state == TARGET_HALTED) + break; + } + if (!head) { + LOG_ERROR("Failed to find HALTED core!"); + return ERROR_FAIL; + } + + res = esp_xtensa_smp_smpbreak_disable(run_target, &smp_break); + if (res != ERROR_OK) + return res; + } + + va_start(ap, num_args); + int algo_res = esp_algorithm_run_func_image_va(run_target, run, num_args, ap); + va_end(ap); + + if (target->smp) { + res = esp_xtensa_smp_smpbreak_restore(run_target, smp_break); + if (res != ERROR_OK) + return res; + } + return algo_res; +} + +int esp_xtensa_smp_run_onboard_func(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t func_addr, + uint32_t num_args, + ...) +{ + struct target *run_target = target; + struct target_list *head; + va_list ap; + uint32_t smp_break = 0; + int res; + + if (target->smp) { + /* find first HALTED and examined core */ + foreach_smp_target(head, target->smp_targets) { + run_target = head->target; + if (target_was_examined(run_target) && run_target->state == TARGET_HALTED) + break; + } + if (!head) { + LOG_ERROR("Failed to find HALTED core!"); + return ERROR_FAIL; + } + res = esp_xtensa_smp_smpbreak_disable(run_target, &smp_break); + if (res != ERROR_OK) + return res; + } + + va_start(ap, num_args); + int algo_res = esp_algorithm_run_onboard_func_va(run_target, run, func_addr, num_args, ap); + va_end(ap); + + if (target->smp) { + res = esp_xtensa_smp_smpbreak_restore(run_target, smp_break); + if (res != ERROR_OK) + return res; + } + return algo_res; +} + int esp_xtensa_smp_init_arch_info(struct target *target, struct esp_xtensa_smp_common *esp_xtensa_smp, - const struct xtensa_config *xtensa_cfg, struct xtensa_debug_module_config *dm_cfg, - const struct esp_xtensa_smp_chip_ops *chip_ops) + const struct esp_xtensa_smp_chip_ops *chip_ops, + const struct esp_semihost_ops *semihost_ops) { - int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg); + int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg, semihost_ops); if (ret != ERROR_OK) return ret; esp_xtensa_smp->chip_ops = chip_ops; @@ -465,7 +591,157 @@ int esp_xtensa_smp_init_arch_info(struct target *target, int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target) { - return esp_xtensa_target_init(cmd_ctx, target); + int ret = esp_xtensa_target_init(cmd_ctx, target); + if (ret != ERROR_OK) + return ret; + + if (target->smp) { + struct target_list *head; + foreach_smp_target(head, target->smp_targets) { + struct target *curr = head->target; + ret = esp_xtensa_semihosting_init(curr); + if (ret != ERROR_OK) + return ret; + } + } else { + ret = esp_xtensa_semihosting_init(target); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do, + target_to_xtensa(target)); +} + +COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt) +{ + struct target *target = get_current_target(CMD_CTX); + if (target->smp && CMD_ARGC > 0) { + struct target_list *head; + struct target *curr; + foreach_smp_target(head, target->smp_targets) { + curr = head->target; + int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do, + target_to_xtensa(curr)); + if (ret != ERROR_OK) + return ret; + } + return ERROR_OK; + } + return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do, + target_to_xtensa(target)); } COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode) @@ -550,7 +826,7 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump) struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; - LOG_INFO("CPU%d:", curr->coreid); + LOG_TARGET_INFO(curr, ":"); int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do, target_to_xtensa(curr)); if (ret != ERROR_OK) @@ -633,6 +909,62 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump) } const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = { + { + .name = "xtdef", + .handler = esp_xtensa_smp_cmd_xtdef, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa core type", + .usage = "<type>", + }, + { + .name = "xtopt", + .handler = esp_xtensa_smp_cmd_xtopt, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa core option", + .usage = "<name> <value>", + }, + { + .name = "xtmem", + .handler = esp_xtensa_smp_cmd_xtmem, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa memory/cache option", + .usage = "<type> [parameters]", + }, + { + .name = "xtmmu", + .handler = esp_xtensa_smp_cmd_xtmmu, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa MMU option", + .usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>", + }, + { + .name = "xtmpu", + .handler = esp_xtensa_smp_cmd_xtmpu, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa MPU option", + .usage = "<num FG seg> <min seg size> <lockable> <executeonly>", + }, + { + .name = "xtreg", + .handler = esp_xtensa_smp_cmd_xtreg, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa register", + .usage = "<regname> <regnum>", + }, + { + .name = "xtregs", + .handler = esp_xtensa_smp_cmd_xtreg, + .mode = COMMAND_CONFIG, + .help = "Configure number of Xtensa registers", + .usage = "<numregs>", + }, + { + .name = "xtregfmt", + .handler = esp_xtensa_smp_cmd_xtregfmt, + .mode = COMMAND_CONFIG, + .help = "Configure format of Xtensa register map", + .usage = "<numgregs>", + }, { .name = "set_permissive", .handler = esp_xtensa_smp_cmd_permissive_mode, diff --git a/src/target/espressif/esp_xtensa_smp.h b/src/target/espressif/esp_xtensa_smp.h index 159125d37b..ec074c11ce 100644 --- a/src/target/espressif/esp_xtensa_smp.h +++ b/src/target/espressif/esp_xtensa_smp.h @@ -9,6 +9,7 @@ #define OPENOCD_TARGET_XTENSA_ESP_SMP_H #include "esp_xtensa.h" +#include "esp_algorithm.h" struct esp_xtensa_smp_chip_ops { int (*poll)(struct target *target); @@ -26,27 +27,33 @@ struct esp_xtensa_smp_common { int esp_xtensa_smp_poll(struct target *target); int esp_xtensa_smp_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution); + bool handle_breakpoints, + bool debug_execution); int esp_xtensa_smp_step(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints); + bool handle_breakpoints); int esp_xtensa_smp_assert_reset(struct target *target); int esp_xtensa_smp_deassert_reset(struct target *target); int esp_xtensa_smp_soft_reset_halt(struct target *target); +int esp_xtensa_smp_on_halt(struct target *target); int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint); int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint); int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event event, void *priv); int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target); int esp_xtensa_smp_init_arch_info(struct target *target, struct esp_xtensa_smp_common *esp_xtensa_smp, - const struct xtensa_config *xtensa_cfg, struct xtensa_debug_module_config *dm_cfg, - const struct esp_xtensa_smp_chip_ops *chip_ops); - + const struct esp_xtensa_smp_chip_ops *chip_ops, + const struct esp_semihost_ops *semihost_ops); +int esp_xtensa_smp_run_func_image(struct target *target, struct esp_algorithm_run_data *run, uint32_t num_args, ...); +int esp_xtensa_smp_run_onboard_func(struct target *target, + struct esp_algorithm_run_data *run, + uint32_t func_addr, + uint32_t num_args, + ...); extern const struct command_registration esp_xtensa_smp_command_handlers[]; extern const struct command_registration esp_xtensa_smp_xtensa_command_handlers[]; extern const struct command_registration esp_xtensa_smp_esp_command_handlers[]; diff --git a/src/target/espressif/segger_sysview.h b/src/target/espressif/segger_sysview.h new file mode 100644 index 0000000000..d149cab665 --- /dev/null +++ b/src/target/espressif/segger_sysview.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* SPDX-FileCopyrightText: (c) 1995-2021 SEGGER Microcontroller GmbH. All rights reserved. */ +/* SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD */ + +/* +* The contend below is extracted from files SEGGER_SYSVIEW.h and SEGGER_SYSVIEW_Int.h in: +* https://www.segger.com/downloads/systemview/systemview_target_src +* SystemView version: 3.42 +*/ + +#ifndef OPENOCD_TARGET_SEGGER_SYSVIEW_H +#define OPENOCD_TARGET_SEGGER_SYSVIEW_H + +#define SYSVIEW_EVTID_NOP 0 /* Dummy packet. */ +#define SYSVIEW_EVTID_OVERFLOW 1 +#define SYSVIEW_EVTID_ISR_ENTER 2 +#define SYSVIEW_EVTID_ISR_EXIT 3 +#define SYSVIEW_EVTID_TASK_START_EXEC 4 +#define SYSVIEW_EVTID_TASK_STOP_EXEC 5 +#define SYSVIEW_EVTID_TASK_START_READY 6 +#define SYSVIEW_EVTID_TASK_STOP_READY 7 +#define SYSVIEW_EVTID_TASK_CREATE 8 +#define SYSVIEW_EVTID_TASK_INFO 9 +#define SYSVIEW_EVTID_TRACE_START 10 +#define SYSVIEW_EVTID_TRACE_STOP 11 +#define SYSVIEW_EVTID_SYSTIME_CYCLES 12 +#define SYSVIEW_EVTID_SYSTIME_US 13 +#define SYSVIEW_EVTID_SYSDESC 14 +#define SYSVIEW_EVTID_USER_START 15 +#define SYSVIEW_EVTID_USER_STOP 16 +#define SYSVIEW_EVTID_IDLE 17 +#define SYSVIEW_EVTID_ISR_TO_SCHEDULER 18 +#define SYSVIEW_EVTID_TIMER_ENTER 19 +#define SYSVIEW_EVTID_TIMER_EXIT 20 +#define SYSVIEW_EVTID_STACK_INFO 21 +#define SYSVIEW_EVTID_MODULEDESC 22 + +#define SYSVIEW_EVTID_INIT 24 +#define SYSVIEW_EVTID_NAME_RESOURCE 25 +#define SYSVIEW_EVTID_PRINT_FORMATTED 26 +#define SYSVIEW_EVTID_NUMMODULES 27 +#define SYSVIEW_EVTID_END_CALL 28 +#define SYSVIEW_EVTID_TASK_TERMINATE 29 + +#define SYSVIEW_EVTID_EX 31 +// +// SystemView extended events. Sent with ID 31. +// +#define SYSVIEW_EVTID_EX_MARK 0 +#define SYSVIEW_EVTID_EX_NAME_MARKER 1 +#define SYSVIEW_EVTID_EX_HEAP_DEFINE 2 +#define SYSVIEW_EVTID_EX_HEAP_ALLOC 3 +#define SYSVIEW_EVTID_EX_HEAP_ALLOC_EX 4 +#define SYSVIEW_EVTID_EX_HEAP_FREE 5 + +#define SYSVIEW_SYNC_LEN 10 + +#define SYSVIEW_EVENT_ID_MAX (200) + +// +// Commands that Host can send to target +// +enum { + SEGGER_SYSVIEW_COMMAND_ID_START = 1, + SEGGER_SYSVIEW_COMMAND_ID_STOP, + SEGGER_SYSVIEW_COMMAND_ID_GET_SYSTIME, + SEGGER_SYSVIEW_COMMAND_ID_GET_TASKLIST, + SEGGER_SYSVIEW_COMMAND_ID_GET_SYSDESC, + SEGGER_SYSVIEW_COMMAND_ID_GET_NUMMODULES, + SEGGER_SYSVIEW_COMMAND_ID_GET_MODULEDESC, + SEGGER_SYSVIEW_COMMAND_ID_HEARTBEAT = 127, + // Extended commands: Commands >= 128 have a second parameter + SEGGER_SYSVIEW_COMMAND_ID_GET_MODULE = 128 +}; + +/* Minimum compatible SEGGER SystemView tool version */ +#define SYSVIEW_MIN_VER_STRING "SEGGER SystemViewer V2.42" + +#endif diff --git a/src/target/etb.c b/src/target/etb.c index 5247cf02bb..fb3112d70a 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -454,12 +454,12 @@ static int etb_init(struct etm_context *etm_ctx) return ERROR_OK; } -static trace_status_t etb_status(struct etm_context *etm_ctx) +static enum trace_status etb_status(struct etm_context *etm_ctx) { struct etb *etb = etm_ctx->capture_driver_priv; struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL]; struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS]; - trace_status_t retval = 0; + enum trace_status retval = 0; int etb_timeout = 100; etb->etm_ctx = etm_ctx; diff --git a/src/target/etb.h b/src/target/etb.h index fa75600ad6..1d0c08b2c2 100644 --- a/src/target/etb.h +++ b/src/target/etb.h @@ -32,7 +32,7 @@ struct etb { uint32_t ram_width; /** how much trace buffer to fill after trigger */ - unsigned trigger_percent; + unsigned int trigger_percent; }; struct etb_reg { diff --git a/src/target/etm.c b/src/target/etm.c index 74cf1b0d3d..d9a3cdc5e5 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -220,10 +220,10 @@ static const struct reg_arch_type etm_scan6_type = { /* Look up register by ID ... most ETM instances only * support a subset of the possible registers. */ -static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id) +static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned int id) { struct reg_cache *cache = etm_ctx->reg_cache; - unsigned i; + unsigned int i; for (i = 0; i < cache->num_regs; i++) { struct etm_reg *reg = cache->reg_list[i].arch_info; @@ -238,9 +238,9 @@ static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id) return NULL; } -static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info, +static void etm_reg_add(unsigned int bcd_vers, struct arm_jtag *jtag_info, struct reg_cache *cache, struct etm_reg *ereg, - const struct etm_reg_info *r, unsigned nreg) + const struct etm_reg_info *r, unsigned int nreg) { struct reg *reg = cache->reg_list; @@ -281,7 +281,7 @@ struct reg_cache *etm_build_reg_cache(struct target *target, struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = NULL; struct etm_reg *arch_info = NULL; - unsigned bcd_vers, config; + unsigned int bcd_vers, config; /* the actual registers are kept in two arrays */ reg_list = calloc(128, sizeof(struct reg)); @@ -320,9 +320,8 @@ struct reg_cache *etm_build_reg_cache(struct target *target, etm_reg_add(0x20, jtag_info, reg_cache, arch_info, etm_core + 1, 1); etm_get_reg(reg_list + 1); - etm_ctx->id = buf_get_u32( - arch_info[1].value, 0, 32); - LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id); + etm_ctx->id = buf_get_u32(arch_info[1].value, 0, 32); + LOG_DEBUG("ETM ID: %08" PRIx32, etm_ctx->id); bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff); } else { @@ -552,8 +551,8 @@ static int etm_set_reg(struct reg *reg, uint32_t value) } buf_set_u32(reg->value, 0, reg->size, value); - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; return ERROR_OK; } @@ -1495,7 +1494,7 @@ COMMAND_HANDLER(handle_etm_info_command) etm_get_reg(etm_sys_config_reg); config = buf_get_u32(etm_sys_config_reg->value, 0, 32); - LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config); + LOG_DEBUG("ETM SYS CONFIG %08" PRIx32, config); max_port_size = config & 0x7; if (etm->bcd_vers >= 0x30) @@ -1568,7 +1567,7 @@ COMMAND_HANDLER(handle_etm_status_command) struct target *target; struct arm *arm; struct etm_context *etm; - trace_status_t trace_status; + enum trace_status trace_status; target = get_current_target(CMD_CTX); arm = target_to_arm(target); @@ -1591,7 +1590,7 @@ COMMAND_HANDLER(handle_etm_status_command) if (!reg) return ERROR_FAIL; if (etm_get_reg(reg) == ERROR_OK) { - unsigned s = buf_get_u32(reg->value, 0, reg->size); + unsigned int s = buf_get_u32(reg->value, 0, reg->size); command_print(CMD, "etm: %s%s%s%s", /* bit(1) == progbit */ @@ -1706,7 +1705,7 @@ COMMAND_HANDLER(handle_etm_dump_command) return ERROR_FAIL; } - if (etm_ctx->capture_driver->status == TRACE_IDLE) { + if (etm_ctx->capture_driver->status(etm_ctx) == TRACE_IDLE) { command_print(CMD, "trace capture wasn't enabled, no trace data captured"); return ERROR_OK; } diff --git a/src/target/etm.h b/src/target/etm.h index be5f2c7d07..e18549dfe2 100644 --- a/src/target/etm.h +++ b/src/target/etm.h @@ -126,7 +126,7 @@ struct etm_capture_driver { const char *name; const struct command_registration *commands; int (*init)(struct etm_context *etm_ctx); - trace_status_t (*status)(struct etm_context *etm_ctx); + enum trace_status (*status)(struct etm_context *etm_ctx); int (*read_trace)(struct etm_context *etm_ctx); int (*start_capture)(struct etm_context *etm_ctx); int (*stop_capture)(struct etm_context *etm_ctx); @@ -153,7 +153,7 @@ struct etm_context { struct reg_cache *reg_cache; /* ETM register cache */ struct etm_capture_driver *capture_driver; /* driver used to access ETM data */ void *capture_driver_priv; /* capture driver private data */ - trace_status_t capture_status; /* current state of capture run */ + enum trace_status capture_status; /* current state of capture run */ struct etmv1_trace_data *trace_data; /* trace data */ uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */ uint32_t control; /* shadow of ETM_CTRL */ @@ -175,7 +175,7 @@ struct etm_context { }; /* PIPESTAT values */ -typedef enum { +enum etmv1_pipestat { STAT_IE = 0x0, STAT_ID = 0x1, STAT_IN = 0x2, @@ -184,10 +184,10 @@ typedef enum { STAT_BD = 0x5, STAT_TR = 0x6, STAT_TD = 0x7 -} etmv1_pipestat_t; +}; /* branch reason values */ -typedef enum { +enum etmv1_branch_reason { BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */ BR_ENABLE = 0x1, /* Trace has been enabled */ BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */ @@ -196,7 +196,7 @@ typedef enum { BR_RSVD5 = 0x5, /* reserved */ BR_RSVD6 = 0x6, /* reserved */ BR_RSVD7 = 0x7, /* reserved */ -} etmv1_branch_reason_t; +}; struct reg_cache *etm_build_reg_cache(struct target *target, struct arm_jtag *jtag_info, struct etm_context *etm_ctx); diff --git a/src/target/etm_dummy.c b/src/target/etm_dummy.c index 8245da6eee..2709b6e9d8 100644 --- a/src/target/etm_dummy.c +++ b/src/target/etm_dummy.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -65,7 +65,7 @@ static int etm_dummy_init(struct etm_context *etm_ctx) return ERROR_OK; } -static trace_status_t etm_dummy_status(struct etm_context *etm_ctx) +static enum trace_status etm_dummy_status(struct etm_context *etm_ctx) { return TRACE_IDLE; } diff --git a/src/target/fa526.c b/src/target/fa526.c index 5b38d3ce7a..d832d3e7d1 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 by Paulius Zaleckas * @@ -329,7 +329,7 @@ static int fa526_init_arch_info(struct target *target, return ERROR_OK; } -static int fa526_target_create(struct target *target, Jim_Interp *interp) +static int fa526_target_create(struct target *target) { struct arm920t_common *arm920t = calloc(1, sizeof(struct arm920t_common)); diff --git a/src/target/feroceon.c b/src/target/feroceon.c index fe5032763a..cf2c838b7d 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. * @@ -526,7 +526,7 @@ static int feroceon_bulk_write_memory(struct target *target, arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); - arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); + arm7_9_resume(target, false, arm7_9->dcc_working_area->address, true, true); /* send data over */ x = 0; @@ -622,7 +622,7 @@ static void feroceon_common_setup(struct target *target) arm7_9->wp1_used_default = -1; } -static int feroceon_target_create(struct target *target, Jim_Interp *interp) +static int feroceon_target_create(struct target *target) { struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); @@ -640,7 +640,7 @@ static int feroceon_target_create(struct target *target, Jim_Interp *interp) return ERROR_OK; } -static int dragonite_target_create(struct target *target, Jim_Interp *interp) +static int dragonite_target_create(struct target *target) { struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); diff --git a/src/target/hla_target.c b/src/target/hla_target.c index 748905691d..983cd87394 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * @@ -36,7 +36,7 @@ #define ARMV7M_SCS_DCRSR DCB_DCRSR #define ARMV7M_SCS_DCRDR DCB_DCRDR -static inline struct hl_interface_s *target_to_adapter(struct target *target) +static inline struct hl_interface *target_to_adapter(struct target *target) { return target->tap->priv; } @@ -44,14 +44,14 @@ static inline struct hl_interface_s *target_to_adapter(struct target *target) static int adapter_load_core_reg_u32(struct target *target, uint32_t regsel, uint32_t *value) { - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); return adapter->layout->api->read_reg(adapter->handle, regsel, value); } static int adapter_store_core_reg_u32(struct target *target, uint32_t regsel, uint32_t value) { - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); return adapter->layout->api->write_reg(adapter->handle, regsel, value); } @@ -65,7 +65,7 @@ static int adapter_examine_debug_reason(struct target *target) return ERROR_OK; } -static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl) +static int hl_dcc_read(struct hl_interface *hl_if, uint8_t *value, uint8_t *ctrl) { uint16_t dcrdr; int retval = hl_if->layout->api->read_mem(hl_if->handle, @@ -90,7 +90,7 @@ static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ct static int hl_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { - struct hl_interface_s *hl_if = target_to_adapter(target); + struct hl_interface *hl_if = target_to_adapter(target); uint8_t data; uint8_t ctrl; uint32_t i; @@ -113,7 +113,7 @@ static int hl_handle_target_request(void *priv) if (!target_was_examined(target)) return ERROR_OK; - struct hl_interface_s *hl_if = target_to_adapter(target); + struct hl_interface *hl_if = target_to_adapter(target); if (!target->dbg_msg_enabled) return ERROR_OK; @@ -187,8 +187,7 @@ static int adapter_init_target(struct command_context *cmd_ctx, return ERROR_OK; } -static int adapter_target_create(struct target *target, - Jim_Interp *interp) +static int adapter_target_create(struct target *target) { LOG_DEBUG("%s", __func__); struct adiv5_private_config *pc = target->private_config; @@ -227,11 +226,11 @@ static int adapter_load_context(struct target *target) static int adapter_debug_entry(struct target *target) { - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); struct arm *arm = &armv7m->arm; struct reg *r; - uint32_t xPSR; + uint32_t xpsr; int retval; /* preserve the DCRDR across halts */ @@ -249,16 +248,16 @@ static int adapter_debug_entry(struct target *target) adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA); r = arm->cpsr; - xPSR = buf_get_u32(r->value, 0, 32); + xpsr = buf_get_u32(r->value, 0, 32); /* Are we in an exception handler */ - if (xPSR & 0x1FF) { - armv7m->exception_number = (xPSR & 0x1FF); + if (xpsr & 0x1FF) { + armv7m->exception_number = (xpsr & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { - unsigned control = buf_get_u32(arm->core_cache + unsigned int control = buf_get_u32(arm->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 3); /* is this thread privileged? */ @@ -286,7 +285,7 @@ static int adapter_debug_entry(struct target *target) static int adapter_poll(struct target *target) { enum target_state state; - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); enum target_state prev_target_state = target->state; @@ -329,7 +328,7 @@ static int adapter_poll(struct target *target) static int hl_assert_reset(struct target *target) { int res = ERROR_OK; - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); bool use_srst_fallback = true; @@ -347,6 +346,13 @@ static int hl_assert_reset(struct target *target) adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN); + if (!target_was_examined(target) && !target->defer_examine + && srst_asserted && res == ERROR_OK) { + /* If the target is not examined, now under reset it is good time to retry examination */ + LOG_TARGET_DEBUG(target, "Trying to re-examine under reset"); + target_examine_one(target); + } + /* only set vector catch if halt is requested */ if (target->reset_halt) adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET); @@ -399,13 +405,14 @@ static int hl_deassert_reset(struct target *target) target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */ - return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0); + return target->reset_halt ? ERROR_OK : target_resume(target, true, 0, false, + false); } static int adapter_halt(struct target *target) { int res; - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); LOG_DEBUG("%s", __func__); @@ -427,12 +434,12 @@ static int adapter_halt(struct target *target) return ERROR_OK; } -static int adapter_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, - int debug_execution) +static int adapter_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution) { int res; - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); uint32_t resume_pc; struct breakpoint *breakpoint = NULL; @@ -442,7 +449,7 @@ static int adapter_resume(struct target *target, int current, address, handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -518,11 +525,11 @@ static int adapter_resume(struct target *target, int current, return ERROR_OK; } -static int adapter_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int adapter_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { int res; - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); struct breakpoint *breakpoint = NULL; struct reg *pc = armv7m->arm.pc; @@ -531,7 +538,7 @@ static int adapter_step(struct target *target, int current, LOG_DEBUG("%s", __func__); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -586,7 +593,7 @@ static int adapter_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; @@ -601,7 +608,7 @@ static int adapter_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { - struct hl_interface_s *adapter = target_to_adapter(target); + struct hl_interface *adapter = target_to_adapter(target); if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; diff --git a/src/target/image.c b/src/target/image.c index 6e5010ec7c..e8ac066fdd 100644 --- a/src/target/image.c +++ b/src/target/image.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -24,6 +24,7 @@ #include "image.h" #include "target.h" #include <helper/log.h> +#include <server/server.h> /* convert ELF header field to host endianness */ #define field16(elf, field) \ @@ -50,12 +51,15 @@ static int autodetect_image_type(struct image *image, const char *url) if (retval != ERROR_OK) return retval; retval = fileio_read(fileio, 9, buffer, &read_bytes); + fileio_close(fileio); - if (retval == ERROR_OK) { - if (read_bytes != 9) - retval = ERROR_FILEIO_OPERATION_FAILED; + /* If the file is smaller than 9 bytes, it can only be bin */ + if (retval == ERROR_OK && read_bytes != 9) { + LOG_DEBUG("Less than 9 bytes in the image file found."); + LOG_DEBUG("BIN image detected."); + image->type = IMAGE_BINARY; + return ERROR_OK; } - fileio_close(fileio); if (retval != ERROR_OK) return retval; @@ -82,8 +86,10 @@ static int autodetect_image_type(struct image *image, const char *url) && (buffer[1] >= '0') && (buffer[1] < '9')) { LOG_DEBUG("S19 image detected."); image->type = IMAGE_SRECORD; - } else + } else { + LOG_DEBUG("BIN image detected."); image->type = IMAGE_BINARY; + } return ERROR_OK; } @@ -91,20 +97,22 @@ static int autodetect_image_type(struct image *image, const char *url) static int identify_image_type(struct image *image, const char *type_string, const char *url) { if (type_string) { - if (!strcmp(type_string, "bin")) + if (!strcmp(type_string, "bin")) { image->type = IMAGE_BINARY; - else if (!strcmp(type_string, "ihex")) + } else if (!strcmp(type_string, "ihex")) { image->type = IMAGE_IHEX; - else if (!strcmp(type_string, "elf")) + } else if (!strcmp(type_string, "elf")) { image->type = IMAGE_ELF; - else if (!strcmp(type_string, "mem")) + } else if (!strcmp(type_string, "mem")) { image->type = IMAGE_MEMORY; - else if (!strcmp(type_string, "s19")) + } else if (!strcmp(type_string, "s19")) { image->type = IMAGE_SRECORD; - else if (!strcmp(type_string, "build")) + } else if (!strcmp(type_string, "build")) { image->type = IMAGE_BUILDER; - else + } else { + LOG_ERROR("Unknown image type: %s, use one of: bin, ihex, elf, mem, s19, build", type_string); return ERROR_IMAGE_TYPE_UNKNOWN; + } } else return autodetect_image_type(image, url); @@ -187,7 +195,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, } while (count-- > 0) { - unsigned value; + unsigned int value; sscanf(&lpsz_line[bytes_read], "%2x", &value); ihex->buffer[cooked_bytes] = (uint8_t)value; cal_checksum += (uint8_t)ihex->buffer[cooked_bytes]; @@ -856,7 +864,7 @@ static int image_mot_buffer_complete_inner(struct image *image, } while (count-- > 0) { - unsigned value; + unsigned int value; sscanf(&lpsz_line[bytes_read], "%2x", &value); mot->buffer[cooked_bytes] = (uint8_t)value; cal_checksum += (uint8_t)mot->buffer[cooked_bytes]; @@ -961,12 +969,13 @@ int image_open(struct image *image, const char *url, const char *type_string) retval = fileio_open(&image_binary->fileio, url, FILEIO_READ, FILEIO_BINARY); if (retval != ERROR_OK) - return retval; + goto free_mem_on_error; + size_t filesize; retval = fileio_size(image_binary->fileio, &filesize); if (retval != ERROR_OK) { fileio_close(image_binary->fileio); - return retval; + goto free_mem_on_error; } image->num_sections = 1; @@ -981,14 +990,14 @@ int image_open(struct image *image, const char *url, const char *type_string) retval = fileio_open(&image_ihex->fileio, url, FILEIO_READ, FILEIO_TEXT); if (retval != ERROR_OK) - return retval; + goto free_mem_on_error; retval = image_ihex_buffer_complete(image); if (retval != ERROR_OK) { LOG_ERROR( "failed buffering IHEX image, check server output for additional information"); fileio_close(image_ihex->fileio); - return retval; + goto free_mem_on_error; } } else if (image->type == IMAGE_ELF) { struct image_elf *image_elf; @@ -997,12 +1006,12 @@ int image_open(struct image *image, const char *url, const char *type_string) retval = fileio_open(&image_elf->fileio, url, FILEIO_READ, FILEIO_BINARY); if (retval != ERROR_OK) - return retval; + goto free_mem_on_error; retval = image_elf_read_headers(image); if (retval != ERROR_OK) { fileio_close(image_elf->fileio); - return retval; + goto free_mem_on_error; } } else if (image->type == IMAGE_MEMORY) { struct target *target = get_target(url); @@ -1032,14 +1041,14 @@ int image_open(struct image *image, const char *url, const char *type_string) retval = fileio_open(&image_mot->fileio, url, FILEIO_READ, FILEIO_TEXT); if (retval != ERROR_OK) - return retval; + goto free_mem_on_error; retval = image_mot_buffer_complete(image); if (retval != ERROR_OK) { LOG_ERROR( "failed buffering S19 image, check server output for additional information"); fileio_close(image_mot->fileio); - return retval; + goto free_mem_on_error; } } else if (image->type == IMAGE_BUILDER) { image->num_sections = 0; @@ -1060,6 +1069,11 @@ int image_open(struct image *image, const char *url, const char *type_string) } return retval; + +free_mem_on_error: + free(image->type_private); + image->type_private = NULL; + return retval; }; int image_read_section(struct image *image, @@ -1282,6 +1296,8 @@ int image_calculate_checksum(const uint8_t *buffer, uint32_t nbytes, uint32_t *c crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buffer++) & 255]; } keep_alive(); + if (openocd_is_shutdown_pending()) + return ERROR_SERVER_INTERRUPTED; } LOG_DEBUG("Calculating checksum done; checksum=0x%" PRIx32, crc); diff --git a/src/target/lakemont.c b/src/target/lakemont.c index 64da29c641..39a50c7a69 100644 --- a/src/target/lakemont.c +++ b/src/target/lakemont.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright(c) 2013-2016 Intel Corporation. @@ -67,32 +67,32 @@ static const struct { const char *name; uint64_t op; uint8_t pm_idx; - unsigned bits; + unsigned int bits; enum reg_type type; const char *group; const char *feature; } regs[] = { /* general purpose registers */ - { EAX, "eax", 0x000000D01D660000, 0, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { ECX, "ecx", 0x000000501D660000, 1, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { EDX, "edx", 0x000000901D660000, 2, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { EBX, "ebx", 0x000000101D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { ESP, "esp", 0x000000E01D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" }, - { EBP, "ebp", 0x000000601D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" }, - { ESI, "esi", 0x000000A01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { EDI, "edi", 0x000000201D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { EAX, "eax", 0x000000D01D660000ULL, 0, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { ECX, "ecx", 0x000000501D660000ULL, 1, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { EDX, "edx", 0x000000901D660000ULL, 2, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { EBX, "ebx", 0x000000101D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { ESP, "esp", 0x000000E01D660000ULL, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" }, + { EBP, "ebp", 0x000000601D660000ULL, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" }, + { ESI, "esi", 0x000000A01D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { EDI, "edi", 0x000000201D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, /* instruction pointer & flags */ - { EIP, "eip", 0x000000C01D660000, 3, 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.i386.core" }, - { EFLAGS, "eflags", 0x000000401D660000, 4, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { EIP, "eip", 0x000000C01D660000ULL, 3, 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.i386.core" }, + { EFLAGS, "eflags", 0x000000401D660000ULL, 4, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, /* segment registers */ - { CS, "cs", 0x000000281D660000, 5, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { SS, "ss", 0x000000C81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { DS, "ds", 0x000000481D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { ES, "es", 0x000000A81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { FS, "fs", 0x000000881D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, - { GS, "gs", 0x000000081D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { CS, "cs", 0x000000281D660000ULL, 5, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { SS, "ss", 0x000000C81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { DS, "ds", 0x000000481D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { ES, "es", 0x000000A81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { FS, "fs", 0x000000881D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, + { GS, "gs", 0x000000081D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, /* floating point unit registers - not accessible via JTAG - here to satisfy GDB */ { ST0, "st0", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, @@ -113,56 +113,56 @@ static const struct { { FOP, "fop", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" }, /* control registers */ - { CR0, "cr0", 0x000000001D660000, 6, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { CR2, "cr2", 0x000000BC1D660000, 7, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { CR3, "cr3", 0x000000801D660000, 8, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { CR4, "cr4", 0x0000002C1D660000, 9, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CR0, "cr0", 0x000000001D660000ULL, 6, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CR2, "cr2", 0x000000BC1D660000ULL, 7, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CR3, "cr3", 0x000000801D660000ULL, 8, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CR4, "cr4", 0x0000002C1D660000ULL, 9, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, /* debug registers */ - { DR0, "dr0", 0x0000007C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DR1, "dr1", 0x000000FC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DR2, "dr2", 0x000000021D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DR3, "dr3", 0x000000821D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DR6, "dr6", 0x000000301D660000, 10, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DR7, "dr7", 0x000000B01D660000, 11, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR0, "dr0", 0x0000007C1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR1, "dr1", 0x000000FC1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR2, "dr2", 0x000000021D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR3, "dr3", 0x000000821D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR6, "dr6", 0x000000301D660000ULL, 10, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DR7, "dr7", 0x000000B01D660000ULL, 11, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, /* descriptor tables */ - { IDTB, "idtbase", 0x000000581D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { IDTL, "idtlimit", 0x000000D81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { IDTAR, "idtar", 0x000000981D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GDTB, "gdtbase", 0x000000B81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GDTL, "gdtlimit", 0x000000781D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GDTAR, "gdtar", 0x000000381D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { TR, "tr", 0x000000701D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { LDTR, "ldtr", 0x000000F01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { LDTB, "ldbase", 0x000000041D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { LDTL, "ldlimit", 0x000000841D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { LDTAR, "ldtar", 0x000000F81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { IDTB, "idtbase", 0x000000581D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { IDTL, "idtlimit", 0x000000D81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { IDTAR, "idtar", 0x000000981D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GDTB, "gdtbase", 0x000000B81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GDTL, "gdtlimit", 0x000000781D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GDTAR, "gdtar", 0x000000381D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { TR, "tr", 0x000000701D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { LDTR, "ldtr", 0x000000F01D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { LDTB, "ldbase", 0x000000041D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { LDTL, "ldlimit", 0x000000841D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { LDTAR, "ldtar", 0x000000F81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, /* segment registers */ - { CSB, "csbase", 0x000000F41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { CSL, "cslimit", 0x0000000C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { CSAR, "csar", 0x000000741D660000, 12, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DSB, "dsbase", 0x000000941D660000, 13, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DSL, "dslimit", 0x000000541D660000, 14, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { DSAR, "dsar", 0x000000141D660000, 15, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { ESB, "esbase", 0x0000004C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { ESL, "eslimit", 0x000000CC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { ESAR, "esar", 0x0000008C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { FSB, "fsbase", 0x000000641D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { FSL, "fslimit", 0x000000E41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { FSAR, "fsar", 0x000000A41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GSB, "gsbase", 0x000000C41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GSL, "gslimit", 0x000000241D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { GSAR, "gsar", 0x000000441D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { SSB, "ssbase", 0x000000341D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { SSL, "sslimit", 0x000000B41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { SSAR, "ssar", 0x000000D41D660000, 16, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { TSSB, "tssbase", 0x000000E81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { TSSL, "tsslimit", 0x000000181D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, - { TSSAR, "tssar", 0x000000681D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CSB, "csbase", 0x000000F41D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CSL, "cslimit", 0x0000000C1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { CSAR, "csar", 0x000000741D660000ULL, 12, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DSB, "dsbase", 0x000000941D660000ULL, 13, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DSL, "dslimit", 0x000000541D660000ULL, 14, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { DSAR, "dsar", 0x000000141D660000ULL, 15, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { ESB, "esbase", 0x0000004C1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { ESL, "eslimit", 0x000000CC1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { ESAR, "esar", 0x0000008C1D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { FSB, "fsbase", 0x000000641D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { FSL, "fslimit", 0x000000E41D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { FSAR, "fsar", 0x000000A41D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GSB, "gsbase", 0x000000C41D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GSL, "gslimit", 0x000000241D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { GSAR, "gsar", 0x000000441D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { SSB, "ssbase", 0x000000341D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { SSL, "sslimit", 0x000000B41D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { SSAR, "ssar", 0x000000D41D660000ULL, 16, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { TSSB, "tssbase", 0x000000E81D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { TSSL, "tsslimit", 0x000000181D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { TSSAR, "tssar", 0x000000681D660000ULL, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, /* probemode control register */ - { PMCR, "pmcr", 0x000000421D660000, 17, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, + { PMCR, "pmcr", 0x000000421D660000ULL, 17, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" }, }; static const struct { @@ -171,36 +171,36 @@ static const struct { uint64_t op; } instructions[] = { /* memory read/write */ - { MEMRDB32, "MEMRDB32", 0x0909090909090851 }, - { MEMRDB16, "MEMRDB16", 0x09090909090851E6 }, - { MEMRDH32, "MEMRDH32", 0x090909090908D166 }, - { MEMRDH16, "MEMRDH16", 0x090909090908D1E6 }, - { MEMRDW32, "MEMRDW32", 0x09090909090908D1 }, - { MEMRDW16, "MEMRDW16", 0x0909090908D1E666 }, - { MEMWRB32, "MEMWRB32", 0x0909090909090811 }, - { MEMWRB16, "MEMWRB16", 0x09090909090811E6 }, - { MEMWRH32, "MEMWRH32", 0x0909090909089166 }, - { MEMWRH16, "MEMWRH16", 0x09090909090891E6 }, - { MEMWRW32, "MEMWRW32", 0x0909090909090891 }, - { MEMWRW16, "MEMWRW16", 0x090909090891E666 }, + { MEMRDB32, "MEMRDB32", 0x0909090909090851ULL }, + { MEMRDB16, "MEMRDB16", 0x09090909090851E6ULL }, + { MEMRDH32, "MEMRDH32", 0x090909090908D166ULL }, + { MEMRDH16, "MEMRDH16", 0x090909090908D1E6ULL }, + { MEMRDW32, "MEMRDW32", 0x09090909090908D1ULL }, + { MEMRDW16, "MEMRDW16", 0x0909090908D1E666ULL }, + { MEMWRB32, "MEMWRB32", 0x0909090909090811ULL }, + { MEMWRB16, "MEMWRB16", 0x09090909090811E6ULL }, + { MEMWRH32, "MEMWRH32", 0x0909090909089166ULL }, + { MEMWRH16, "MEMWRH16", 0x09090909090891E6ULL }, + { MEMWRW32, "MEMWRW32", 0x0909090909090891ULL }, + { MEMWRW16, "MEMWRW16", 0x090909090891E666ULL }, /* IO read/write */ - { IORDB32, "IORDB32", 0x0909090909090937 }, - { IORDB16, "IORDB16", 0x09090909090937E6 }, - { IORDH32, "IORDH32", 0x090909090909B766 }, - { IORDH16, "IORDH16", 0x090909090909B7E6 }, - { IORDW32, "IORDW32", 0x09090909090909B7 }, - { IORDW16, "IORDW16", 0x0909090909B7E666 }, - { IOWRB32, "IOWRB32", 0x0909090909090977 }, - { IOWRB16, "IOWRB16", 0x09090909090977E6 }, - { IOWRH32, "IOWRH32", 0x090909090909F766 }, - { IOWRH16, "IOWRH16", 0x090909090909F7E6 }, - { IOWRW32, "IOWRW32", 0x09090909090909F7 }, - { IOWRW16, "IOWRW16", 0x0909090909F7E666 }, + { IORDB32, "IORDB32", 0x0909090909090937ULL }, + { IORDB16, "IORDB16", 0x09090909090937E6ULL }, + { IORDH32, "IORDH32", 0x090909090909B766ULL }, + { IORDH16, "IORDH16", 0x090909090909B7E6ULL }, + { IORDW32, "IORDW32", 0x09090909090909B7ULL }, + { IORDW16, "IORDW16", 0x0909090909B7E666ULL }, + { IOWRB32, "IOWRB32", 0x0909090909090977ULL }, + { IOWRB16, "IOWRB16", 0x09090909090977E6ULL }, + { IOWRH32, "IOWRH32", 0x090909090909F766ULL }, + { IOWRH16, "IOWRH16", 0x090909090909F7E6ULL }, + { IOWRW32, "IOWRW32", 0x09090909090909F7ULL }, + { IOWRW16, "IOWRW16", 0x0909090909F7E666ULL }, /* lakemont1 core shadow ram access opcodes */ - { SRAMACCESS, "SRAMACCESS", 0x0000000E9D660000 }, - { SRAM2PDR, "SRAM2PDR", 0x4CF0000000000000 }, - { PDR2SRAM, "PDR2SRAM", 0x0CF0000000000000 }, - { WBINVD, "WBINVD", 0x09090909090990F0 }, + { SRAMACCESS, "SRAMACCESS", 0x0000000E9D660000ULL }, + { SRAM2PDR, "SRAM2PDR", 0x4CF0000000000000ULL }, + { PDR2SRAM, "PDR2SRAM", 0x0CF0000000000000ULL }, + { WBINVD, "WBINVD", 0x09090909090990F0ULL }, }; bool check_not_halted(const struct target *t) @@ -224,10 +224,10 @@ static int irscan(struct target *t, uint8_t *out, if (ir_len != t->tap->ir_length) { retval = ERROR_FAIL; if (t->tap->enabled) - LOG_ERROR("%s tap enabled but tap irlen=%d", + LOG_ERROR("%s tap enabled but tap irlen=%u", __func__, t->tap->ir_length); else - LOG_ERROR("%s tap not enabled and irlen=%d", + LOG_ERROR("%s tap not enabled and irlen=%u", __func__, t->tap->ir_length); return retval; } @@ -597,7 +597,7 @@ static int read_all_core_hw_regs(struct target *t) { int err; uint32_t regval; - unsigned i; + unsigned int i; struct x86_32_common *x86_32 = target_to_x86_32(t); for (i = 0; i < (x86_32->cache->num_regs); i++) { if (regs[i].pm_idx == NOT_AVAIL_REG) @@ -616,7 +616,7 @@ static int read_all_core_hw_regs(struct target *t) static int write_all_core_hw_regs(struct target *t) { int err; - unsigned i; + unsigned int i; struct x86_32_common *x86_32 = target_to_x86_32(t); for (i = 0; i < (x86_32->cache->num_regs); i++) { if (regs[i].pm_idx == NOT_AVAIL_REG) @@ -988,8 +988,8 @@ int lakemont_halt(struct target *t) } } -int lakemont_resume(struct target *t, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +int lakemont_resume(struct target *t, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution) { struct breakpoint *bp = NULL; struct x86_32_common *x86_32 = target_to_x86_32(t); @@ -1004,7 +1004,7 @@ int lakemont_resume(struct target *t, int current, target_addr_t address, bp = breakpoint_find(t, eip); if (bp /*&& bp->type == BKPT_SOFT*/) { /* the step will step over the breakpoint */ - if (lakemont_step(t, 0, 0, 1) != ERROR_OK) { + if (lakemont_step(t, false, 0, true) != ERROR_OK) { LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " " "failed to resume the target", __func__, eip); return ERROR_FAIL; @@ -1029,8 +1029,8 @@ int lakemont_resume(struct target *t, int current, target_addr_t address, return ERROR_OK; } -int lakemont_step(struct target *t, int current, - target_addr_t address, int handle_breakpoints) +int lakemont_step(struct target *t, bool current, target_addr_t address, + bool handle_breakpoints) { struct x86_32_common *x86_32 = target_to_x86_32(t); uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32); diff --git a/src/target/lakemont.h b/src/target/lakemont.h index ca6557fcde..4c84f74aee 100644 --- a/src/target/lakemont.h +++ b/src/target/lakemont.h @@ -84,10 +84,10 @@ int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32); int lakemont_poll(struct target *t); int lakemont_arch_state(struct target *t); int lakemont_halt(struct target *t); -int lakemont_resume(struct target *t, int current, target_addr_t address, - int handle_breakpoints, int debug_execution); -int lakemont_step(struct target *t, int current, - target_addr_t address, int handle_breakpoints); +int lakemont_resume(struct target *t, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution); +int lakemont_step(struct target *t, bool current, + target_addr_t address, bool handle_breakpoints); int lakemont_reset_assert(struct target *t); int lakemont_reset_deassert(struct target *t); int lakemont_update_after_probemode_entry(struct target *t); diff --git a/src/target/ls1_sap.c b/src/target/ls1_sap.c index 0e2f14e76d..49335a8b9f 100644 --- a/src/target/ls1_sap.c +++ b/src/target/ls1_sap.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 by Esben Haabendal <eha@deif.com> @@ -17,7 +17,7 @@ struct ls1_sap { struct jtag_tap *tap; }; -static int ls1_sap_target_create(struct target *target, Jim_Interp *interp) +static int ls1_sap_target_create(struct target *target) { struct ls1_sap *ls1_sap = calloc(1, sizeof(struct ls1_sap)); @@ -55,15 +55,15 @@ static int ls1_sap_halt(struct target *target) return ERROR_OK; } -static int ls1_sap_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int ls1_sap_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { LOG_DEBUG("%s", __func__); return ERROR_OK; } -static int ls1_sap_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int ls1_sap_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { LOG_DEBUG("%s", __func__); return ERROR_OK; diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c index 29229588b0..c5618c9ccd 100644 --- a/src/target/mem_ap.c +++ b/src/target/mem_ap.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016 by Matthias Welwarsky <matthias.welwarsky@sysgo.com> @@ -24,7 +24,7 @@ struct mem_ap { uint64_t ap_num; }; -static int mem_ap_target_create(struct target *target, Jim_Interp *interp) +static int mem_ap_target_create(struct target *target) { struct mem_ap *mem_ap; struct adiv5_private_config *pc; @@ -34,13 +34,13 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; if (pc->ap_num == DP_APSEL_INVALID) { - LOG_ERROR("AP number not specified"); + LOG_TARGET_ERROR(target, "AP number not specified"); return ERROR_FAIL; } mem_ap = calloc(1, sizeof(struct mem_ap)); if (!mem_ap) { - LOG_ERROR("Out of memory"); + LOG_TARGET_ERROR(target, "Out of memory"); return ERROR_FAIL; } @@ -58,7 +58,7 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp) static int mem_ap_init_target(struct command_context *cmd_ctx, struct target *target) { - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); target->state = TARGET_UNKNOWN; target->debug_reason = DBG_REASON_UNDEFINED; return ERROR_OK; @@ -68,19 +68,18 @@ static void mem_ap_deinit_target(struct target *target) { struct mem_ap *mem_ap = target->arch_info; - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); if (mem_ap->ap) dap_put_ap(mem_ap->ap); free(target->private_config); free(target->arch_info); - return; } static int mem_ap_arch_state(struct target *target) { - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); return ERROR_OK; } @@ -96,26 +95,27 @@ static int mem_ap_poll(struct target *target) static int mem_ap_halt(struct target *target) { - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); target->state = TARGET_HALTED; target->debug_reason = DBG_REASON_DBGRQ; target_call_event_callbacks(target, TARGET_EVENT_HALTED); return ERROR_OK; } -static int mem_ap_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int mem_ap_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution) { - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); target->state = TARGET_RUNNING; target->debug_reason = DBG_REASON_NOTHALTED; return ERROR_OK; } -static int mem_ap_step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int mem_ap_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); target->state = TARGET_HALTED; target->debug_reason = DBG_REASON_DBGRQ; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -127,7 +127,7 @@ static int mem_ap_assert_reset(struct target *target) target->state = TARGET_RESET; target->debug_reason = DBG_REASON_UNDEFINED; - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); return ERROR_OK; } @@ -136,15 +136,12 @@ static int mem_ap_examine(struct target *target) struct mem_ap *mem_ap = target->arch_info; if (!target_was_examined(target)) { - if (mem_ap->ap) { - dap_put_ap(mem_ap->ap); - mem_ap->ap = NULL; - } - - mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num); if (!mem_ap->ap) { - LOG_ERROR("Cannot get AP"); - return ERROR_FAIL; + mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num); + if (!mem_ap->ap) { + LOG_TARGET_ERROR(target, "Cannot get AP"); + return ERROR_FAIL; + } } target_set_examined(target); target->state = TARGET_UNKNOWN; @@ -166,7 +163,7 @@ static int mem_ap_deassert_reset(struct target *target) target->debug_reason = DBG_REASON_NOTHALTED; } - LOG_DEBUG("%s", __func__); + LOG_TARGET_DEBUG(target, "%s", __func__); return ERROR_OK; } @@ -185,7 +182,7 @@ static struct reg_arch_type mem_ap_reg_arch_type = { .set = mem_ap_reg_set, }; -const char *mem_ap_get_gdb_arch(struct target *target) +static const char *mem_ap_get_gdb_arch(const struct target *target) { return "arm"; } @@ -197,11 +194,11 @@ const char *mem_ap_get_gdb_arch(struct target *target) * reg[24]: 32 bits, fps * reg[25]: 32 bits, cpsr * - * Set 'exist' only to reg[0..15], so initial response to GDB is correct + * GDB requires only reg[0..15] */ #define NUM_REGS 26 +#define NUM_GDB_REGS 16 #define MAX_REG_SIZE 96 -#define REG_EXIST(n) ((n) < 16) #define REG_SIZE(n) ((((n) >= 16) && ((n) < 24)) ? 96 : 32) struct mem_ap_alloc_reg_list { @@ -216,19 +213,19 @@ static int mem_ap_get_gdb_reg_list(struct target *target, struct reg **reg_list[ { struct mem_ap_alloc_reg_list *mem_ap_alloc = calloc(1, sizeof(struct mem_ap_alloc_reg_list)); if (!mem_ap_alloc) { - LOG_ERROR("Out of memory"); + LOG_TARGET_ERROR(target, "Out of memory"); return ERROR_FAIL; } *reg_list = mem_ap_alloc->reg_list; - *reg_list_size = NUM_REGS; + *reg_list_size = (reg_class == REG_CLASS_ALL) ? NUM_REGS : NUM_GDB_REGS; struct reg *regs = mem_ap_alloc->regs; for (int i = 0; i < NUM_REGS; i++) { regs[i].number = i; regs[i].value = mem_ap_alloc->regs_value; regs[i].size = REG_SIZE(i); - regs[i].exist = REG_EXIST(i); + regs[i].exist = true; regs[i].type = &mem_ap_reg_arch_type; (*reg_list)[i] = ®s[i]; } @@ -241,7 +238,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address, { struct mem_ap *mem_ap = target->arch_info; - LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT + LOG_TARGET_DEBUG(target, "Reading memory at physical address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32, address, size, count); if (count == 0 || !buffer) @@ -256,7 +253,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address, { struct mem_ap *mem_ap = target->arch_info; - LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT + LOG_TARGET_DEBUG(target, "Writing memory at physical address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32, address, size, count); if (count == 0 || !buffer) diff --git a/src/target/mips32.c b/src/target/mips32.c index c89fb0901b..4527c5fa88 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * @@ -18,6 +18,7 @@ #endif #include "mips32.h" +#include "mips_cpu.h" #include "breakpoints.h" #include "algorithm.h" #include "register.h" @@ -26,19 +27,19 @@ static const char *mips_isa_strings[] = { "MIPS32", "MIPS16", "", "MICRO MIPS32", }; -#define MIPS32_GDB_DUMMY_FP_REG 1 +#define MIPS32_GDB_FP_REG 1 /* * GDB registers - * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml + * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu,dsp}.xml */ static const struct { - unsigned id; + unsigned int id; const char *name; enum reg_type type; const char *group; const char *feature; - int flag; + int size; } mips32_regs[] = { { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, @@ -72,87 +73,168 @@ static const struct { { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, - { 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, - { 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, - { 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, - { 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, - { 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, - { 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, - - { 38, "f0", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 39, "f1", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 40, "f2", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 41, "f3", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 42, "f4", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 43, "f5", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 44, "f6", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 45, "f7", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 46, "f8", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 47, "f9", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 48, "f10", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 49, "f11", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 50, "f12", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 51, "f13", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 52, "f14", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 53, "f15", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 54, "f16", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 55, "f17", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 56, "f18", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 57, "f19", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 58, "f20", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 59, "f21", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 60, "f22", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 61, "f23", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 62, "f24", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 63, "f25", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 64, "f26", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 65, "f27", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 66, "f28", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 67, "f29", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 68, "f30", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 69, "f31", REG_TYPE_IEEE_SINGLE, NULL, - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 70, "fcsr", REG_TYPE_INT, "float", - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, - { 71, "fir", REG_TYPE_INT, "float", - "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 32, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 33, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + + { MIPS32_REGLIST_FP_INDEX + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + { MIPS32_REGLIST_FP_INDEX + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG }, + + { MIPS32_REGLIST_FPC_INDEX + 0, "fcsr", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", 0 }, + { MIPS32_REGLIST_FPC_INDEX + 1, "fir", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", 0 }, + + { MIPS32_REGLIST_C0_STATUS_INDEX, "status", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.cp0", 0 }, + { MIPS32_REGLIST_C0_BADVADDR_INDEX, "badvaddr", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.cp0", 0 }, + { MIPS32_REGLIST_C0_CAUSE_INDEX, "cause", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.cp0", 0 }, + { MIPS32_REGLIST_C0_PC_INDEX, "pc", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.cpu", 0 }, + { MIPS32_REGLIST_C0_GUESTCTL1_INDEX, "guestCtl1", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.cp0", 0 }, + + { MIPS32_REGLIST_DSP_INDEX + 0, "hi1", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + { MIPS32_REGLIST_DSP_INDEX + 1, "lo1", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + { MIPS32_REGLIST_DSP_INDEX + 2, "hi2", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + { MIPS32_REGLIST_DSP_INDEX + 3, "lo2", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + { MIPS32_REGLIST_DSP_INDEX + 4, "hi3", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + { MIPS32_REGLIST_DSP_INDEX + 5, "lo3", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, + + { MIPS32_REGLIST_DSP_DSPCTL_INDEX, "dspctl", REG_TYPE_INT, NULL, + "org.gnu.gdb.mips.dsp", 0 }, }; - #define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs) -static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; + + +#define zero 0 + +#define AT 1 + +#define v0 2 +#define v1 3 + +#define a0 4 +#define a1 5 +#define a2 6 +#define a3 7 +#define t0 8 +#define t1 9 +#define t2 10 +#define t3 11 +#define t4 12 +#define t5 13 +#define t6 14 +#define t7 15 +#define ta0 12 /* alias for $t4 */ +#define ta1 13 /* alias for $t5 */ +#define ta2 14 /* alias for $t6 */ +#define ta3 15 /* alias for $t7 */ + +#define s0 16 +#define s1 17 +#define s2 18 +#define s3 19 +#define s4 20 +#define s5 21 +#define s6 22 +#define s7 23 +#define s8 30 /* == fp */ + +#define t8 24 +#define t9 25 +#define k0 26 +#define k1 27 + +#define gp 28 + +#define sp 29 +#define fp 30 +#define ra 31 + + +static const struct { + const char *name; +} mips32_dsp_regs[MIPS32NUMDSPREGS] = { + { "hi1"}, + { "lo1"}, + { "hi2"}, + { "lo2"}, + { "hi3"}, + { "lo3"}, + { "control"}, +}; static int mips32_get_core_reg(struct reg *reg) { @@ -173,21 +255,86 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) { struct mips32_core_reg *mips32_reg = reg->arch_info; struct target *target = mips32_reg->target; - uint32_t value = buf_get_u32(buf, 0, 32); + uint64_t value; + + if (reg->size == 64) + value = buf_get_u64(buf, 0, 64); + else + value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; - buf_set_u32(reg->value, 0, 32, value); + if (reg->size == 64) + buf_set_u64(reg->value, 0, 64, value); + else + buf_set_u32(reg->value, 0, 32, value); + reg->dirty = true; reg->valid = true; return ERROR_OK; } +/** + * mips32_set_all_fpr_width - Set the width of all floating-point registers + * @param[in] mips32: MIPS32 common structure + * @param[in] fp64: Flag indicating whether to set the width to 64 bits (double precision) + * + * @brief Sets the width of all floating-point registers based on the specified flag. + */ +static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64) +{ + struct reg_cache *cache = mips32->core_cache; + struct reg *reg_list = cache->reg_list; + int i; + + for (i = MIPS32_REGLIST_FP_INDEX; i < (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT); i++) { + reg_list[i].size = fp64 ? 64 : 32; + reg_list[i].reg_data_type->type = fp64 ? REG_TYPE_IEEE_DOUBLE : REG_TYPE_IEEE_SINGLE; + } +} + +/** + * mips32_detect_fpr_mode_change - Detect changes in floating-point register mode + * @param[in] mips32: MIPS32 common structure + * @param[in] cp0_status: Value of the CP0 status register + * + * @brief Detects changes in the floating-point register mode based on the CP0 status register. + * If changes are detected, it updates the internal state + * and logs a warning message indicating the mode change. + */ +static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status) +{ + if (!mips32->fp_imp) + return; + + /* CP0.Status.FR indicates the working mode of floating-point register. + * When FP = 0, fpr can contain any 32bit data type, + * 64bit data types are stored in even-odd register pairs. + * When FP = 1, fpr can contain any data types.*/ + bool fpu_in_64bit = ((cp0_status & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0); + + /* CP0.Status.CU1 indicated whether CoProcessor1(which is FPU) is present. */ + bool fp_enabled = ((cp0_status & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0); + + if (mips32->fpu_in_64bit != fpu_in_64bit) { + mips32->fpu_in_64bit = fpu_in_64bit; + mips32_set_all_fpr_width(mips32, fpu_in_64bit); + LOG_WARNING("** FP mode changed to %sbit, you must reconnect GDB **", fpu_in_64bit ? "64" : "32"); + } + + if (mips32->fpu_enabled != fp_enabled) { + mips32->fpu_enabled = fp_enabled; + const char *s = fp_enabled ? "enabled" : "disabled"; + LOG_WARNING("** FP is %s, register update %s **", s, s); + } +} + static int mips32_read_core_reg(struct target *target, unsigned int num) { - uint32_t reg_value; + unsigned int cnum; + uint64_t reg_value = 0; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -195,17 +342,47 @@ static int mips32_read_core_reg(struct target *target, unsigned int num) if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; - reg_value = mips32->core_regs[num]; - buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); + if (num >= MIPS32_REGLIST_DSP_INDEX) { + /* DSP */ + cnum = num - MIPS32_REGLIST_DSP_INDEX; + reg_value = mips32->core_regs.dsp[cnum]; + buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); + } else if (num >= MIPS32_REGLIST_C0_INDEX) { + /* CP0 */ + cnum = num - MIPS32_REGLIST_C0_INDEX; + reg_value = mips32->core_regs.cp0[cnum]; + buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); + if (cnum == MIPS32_REG_C0_STATUS_INDEX) + mips32_detect_fpr_mode_change(mips32, reg_value); + } else if (num >= MIPS32_REGLIST_FPC_INDEX) { + /* FPCR */ + cnum = num - MIPS32_REGLIST_FPC_INDEX; + reg_value = mips32->core_regs.fpcr[cnum]; + buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); + } else if (num >= MIPS32_REGLIST_FP_INDEX) { + /* FPR */ + cnum = num - MIPS32_REGLIST_FP_INDEX; + reg_value = mips32->core_regs.fpr[cnum]; + buf_set_u64(mips32->core_cache->reg_list[num].value, 0, 64, reg_value); + } else { + /* GPR */ + cnum = num - MIPS32_REGLIST_GP_INDEX; + reg_value = mips32->core_regs.gpr[cnum]; + buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); + } + mips32->core_cache->reg_list[num].valid = true; mips32->core_cache->reg_list[num].dirty = false; + LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value); + return ERROR_OK; } static int mips32_write_core_reg(struct target *target, unsigned int num) { - uint32_t reg_value; + unsigned int cnum; + uint64_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -213,9 +390,36 @@ static int mips32_write_core_reg(struct target *target, unsigned int num) if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; - reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); - mips32->core_regs[num] = reg_value; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value); + if (num >= MIPS32_REGLIST_DSP_INDEX) { + /* DSP */ + cnum = num - MIPS32_REGLIST_DSP_INDEX; + reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); + mips32->core_regs.dsp[cnum] = (uint32_t)reg_value; + } else if (num >= MIPS32_REGLIST_C0_INDEX) { + /* CP0 */ + cnum = num - MIPS32_REGLIST_C0_INDEX; + reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); + mips32->core_regs.cp0[cnum] = (uint32_t)reg_value; + if (cnum == MIPS32_REG_C0_STATUS_INDEX) + mips32_detect_fpr_mode_change(mips32, reg_value); + } else if (num >= MIPS32_REGLIST_FPC_INDEX) { + /* FPCR */ + cnum = num - MIPS32_REGLIST_FPC_INDEX; + reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); + mips32->core_regs.fpcr[cnum] = (uint32_t)reg_value; + } else if (num >= MIPS32_REGLIST_FP_INDEX) { + /* FPR */ + cnum = num - MIPS32_REGLIST_FP_INDEX; + reg_value = buf_get_u64(mips32->core_cache->reg_list[num].value, 0, 64); + mips32->core_regs.fpr[cnum] = reg_value; + } else { + /* GPR */ + cnum = num - MIPS32_REGLIST_GP_INDEX; + reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); + mips32->core_regs.gpr[cnum] = (uint32_t)reg_value; + } + + LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value); mips32->core_cache->reg_list[num].valid = true; mips32->core_cache->reg_list[num].dirty = false; @@ -245,10 +449,13 @@ int mips32_save_context(struct target *target) /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - struct mips_ejtag *ejtag_info = &mips32->ejtag_info; /* read core registers */ - mips32_pracc_read_regs(ejtag_info, mips32->core_regs); + int retval = mips32_pracc_read_regs(mips32); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read core registers from target"); + return retval; + } for (i = 0; i < MIPS32_NUM_REGS; i++) { if (!mips32->core_cache->reg_list[i].valid) @@ -264,7 +471,6 @@ int mips32_restore_context(struct target *target) /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - struct mips_ejtag *ejtag_info = &mips32->ejtag_info; for (i = 0; i < MIPS32_NUM_REGS; i++) { if (mips32->core_cache->reg_list[i].dirty) @@ -272,9 +478,7 @@ int mips32_restore_context(struct target *target) } /* write core regs */ - mips32_pracc_write_regs(ejtag_info, mips32->core_regs); - - return ERROR_OK; + return mips32_pracc_write_regs(mips32); } int mips32_arch_state(struct target *target) @@ -284,7 +488,7 @@ int mips32_arch_state(struct target *target) LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "", mips_isa_strings[mips32->isa_mode], debug_reason_name(target), - buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)); + buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32)); return ERROR_OK; } @@ -321,25 +525,19 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) arch_info[i].mips32_common = mips32; reg_list[i].name = mips32_regs[i].name; - reg_list[i].size = 32; - - if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) { - reg_list[i].value = mips32_gdb_dummy_fp_value; - reg_list[i].valid = true; - reg_list[i].arch_info = NULL; - register_init_dummy(®_list[i]); - } else { - reg_list[i].value = calloc(1, 4); - reg_list[i].valid = false; - reg_list[i].type = &mips32_reg_type; - reg_list[i].arch_info = &arch_info[i]; - - reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type)); - if (reg_list[i].reg_data_type) - reg_list[i].reg_data_type->type = mips32_regs[i].type; - else - LOG_ERROR("unable to allocate reg type list"); - } + reg_list[i].size = mips32_regs[i].size ? 64 : 32; + + reg_list[i].value = mips32_regs[i].size ? calloc(1, 8) : calloc(1, 4); + reg_list[i].valid = false; + reg_list[i].type = &mips32_reg_type; + reg_list[i].arch_info = &arch_info[i]; + + reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type)); + if (reg_list[i].reg_data_type) + reg_list[i].reg_data_type->type = mips32_regs[i].type; + else + LOG_ERROR("unable to allocate reg type list"); + reg_list[i].dirty = false; @@ -384,13 +582,13 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s /* run to exit point. return error if exit point was not reached. */ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, - int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32) + unsigned int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32) { uint32_t pc; int retval; /* This code relies on the target specific resume() and poll()->debug_entry() * sequence to write register values to the processor and the read them back */ - retval = target_resume(target, 0, entry_point, 0, 1); + retval = target_resume(target, false, entry_point, false, true); if (retval != ERROR_OK) return retval; @@ -406,7 +604,7 @@ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, return ERROR_TARGET_TIMEOUT; } - pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); + pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32); if (exit_point && (pc != exit_point)) { LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc); return ERROR_TARGET_TIMEOUT; @@ -418,7 +616,7 @@ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, - target_addr_t exit_point, int timeout_ms, void *arch_info) + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { struct mips32_common *mips32 = target_to_mips32(target); struct mips32_algorithm *mips32_algorithm_info = arch_info; @@ -438,7 +636,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (run target algo)"); return ERROR_TARGET_NOT_HALTED; } @@ -693,15 +891,277 @@ int mips32_enable_interrupts(struct target *target, int enable) return ERROR_OK; } +/* read processor identification cp0 register */ +static int mips32_read_c0_prid(struct target *target) +{ + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + int retval; + + retval = mips32_cp0_read(ejtag_info, &mips32->prid, 15, 0); + if (retval != ERROR_OK) { + LOG_ERROR("processor id not available, failed to read cp0 PRId register"); + mips32->prid = 0; + } + + return retval; +} + +/** + * mips32_find_cpu_by_prid - Find CPU information by processor ID. + * @param[in] prid: Processor ID of the CPU. + * + * @brief This function looks up the CPU entry in the mips32_cpu_entry array based on the provided + * processor ID. It also handles special cases like AMD/Alchemy CPUs that use Company Options + * instead of Processor IDs. + * + * @return Pointer to the corresponding cpu_entry struct, or the 'unknown' entry if not found. + */ +static const struct cpu_entry *mips32_find_cpu_by_prid(uint32_t prid) +{ + /* AMD/Alchemy CPU uses Company Options instead of Processor ID. + * Therefore an extra transform step for prid to map it to an assigned ID, + */ + if ((prid & PRID_COMP_MASK) == PRID_COMP_ALCHEMY) { + /* Clears Processor ID field, then put Company Option field to its place */ + prid = (prid & 0xFFFF00FF) | ((prid & 0xFF000000) >> 16); + } + + /* Mask out Company Option */ + prid &= 0x00FFFFFF; + + for (unsigned int i = 0; i < MIPS32_NUM_CPU_ENTRIES; i++) { + const struct cpu_entry *entry = &mips32_cpu_entry[i]; + if ((entry->prid & MIPS32_CORE_MASK) <= prid && prid <= entry->prid) + return entry; + } + + /* If nothing matched, then return unknown entry */ + return &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1]; +} + +static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info) +{ + return (ejtag_info->prid & PRID_COMP_MASK) == PRID_COMP_LEXRA; +} + +static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info) +{ + return (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; +} + +/** + * mips32_cpu_support_sync - Checks CPU supports ordering + * @param[in] ejtag_info: MIPS EJTAG information structure. + * + * @brief MIPS ISA implemented on Lexra CPUs is MIPS-I, similar to R3000, + * which does not have the SYNC instruction alone with unaligned + * load/store instructions. + * + * @returns true if current CPU supports sync instruction(CPU is not Lexra) +*/ +bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info) +{ + return !mips32_cpu_is_lexra(ejtag_info); +} + +/** + * mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier + * @param[in] ejtag_info: MIPS EJTAG information structure. + * + * @brief hazard barrier instructions EHB and *.HB was introduced to MIPS from release 2. + * + * @returns true if current CPU supports hazard barrier(release > 1) +*/ +bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info) +{ + return mips32_cpu_get_release(ejtag_info) > MIPS32_RELEASE_1; +} + +/** + * mips32_cpu_probe - Detects processor type and applies necessary quirks. + * @param[in] target: The target CPU to probe. + * + * @brief This function probes the CPU, reads its PRID (Processor ID), and determines the CPU type. + * It applies any quirks necessary for specific processor types. + * + * NOTE: The proper detection of certain CPUs can become quite complicated. + * Please consult the following Linux kernel code when adding new CPUs: + * arch/mips/include/asm/cpu.h + * arch/mips/kernel/cpu-probe.c + * + * @return ERROR_OK on success; error code on failure. + */ +int mips32_cpu_probe(struct target *target) +{ + struct mips32_common *mips32 = target_to_mips32(target); + int retval; + + if (mips32->prid) + return ERROR_OK; /* Already probed once, return early. */ + + retval = mips32_read_c0_prid(target); + if (retval != ERROR_OK) + return retval; + + const struct cpu_entry *entry = mips32_find_cpu_by_prid(mips32->prid); + + switch (mips32->prid & PRID_COMP_MASK) { + case PRID_COMP_INGENIC_E1: + switch (mips32->prid & PRID_IMP_MASK) { + case PRID_IMP_XBURST_REV1: + mips32->cpu_quirks |= EJTAG_QUIRK_PAD_DRET; + break; + default: + break; + } + break; + + /* Determine which CP0 registers are available in the current processor core */ + case PRID_COMP_MTI: + switch (entry->prid & PRID_IMP_MASK) { + case PRID_IMP_MAPTIV_UC: + mips32->cp0_mask = MIPS_CP0_MAPTIV_UC; + break; + case PRID_IMP_MAPTIV_UP: + case PRID_IMP_M5150: + mips32->cp0_mask = MIPS_CP0_MAPTIV_UP; + break; + case PRID_IMP_IAPTIV: + case PRID_IMP_IAPTIV_CM: + mips32->cp0_mask = MIPS_CP0_IAPTIV; + break; + default: + /* CP0 mask should be the same as MK4 by default */ + mips32->cp0_mask = MIPS_CP0_MK4; + break; + } + + default: + break; + } + + mips32->cpu_info = entry; + LOG_DEBUG("CPU: %s (PRId %08x)", entry->cpu_name, mips32->prid); + + return ERROR_OK; +} + +/* reads dsp implementation info from CP0 Config3 register {DSPP, DSPREV}*/ +static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info) +{ + uint32_t retval, status_value, dsp_present; + bool dsp_enabled; + + retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read cp0 status register"); + return; + } + + dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT); + dsp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0; + if (dsp_present) { + mips32->dsp_imp = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPREV_MASK) >> MIPS32_CONFIG3_DSPREV_SHIFT) + 1; + LOG_USER("DSP implemented: rev %d, %s", mips32->dsp_imp, dsp_enabled ? "enabled" : "disabled"); + } else { + LOG_USER("DSP implemented: %s", "no"); + } +} + +/* read fpu implementation info from CP0 Config1 register {CU1, FP}*/ +static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info) +{ + int retval; + uint32_t fp_imp = (ejtag_info->config[1] & MIPS32_CONFIG1_FP_MASK) >> MIPS32_CONFIG1_FP_SHIFT; + char buf[60] = {0}; + if (!fp_imp) { + LOG_USER("FPU implemented: %s", "no"); + mips32->fp_imp = MIPS32_FP_IMP_NONE; + return ERROR_OK; + } + uint32_t fir_value, status_value; + bool fpu_in_64bit, fp_enabled; + + retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read cp0 status register"); + return retval; + } + + fpu_in_64bit = (status_value & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0; + fp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0; + if (fp_enabled) { + retval = mips32_cp1_control_read(ejtag_info, &fir_value, 0); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read cp1 FIR register"); + return retval; + } + + if ((fir_value >> MIPS32_CP1_FIR_F64_SHIFT) & 0x1) + fp_imp++; + } else { + /* This is the only condition that writes to buf */ + snprintf(buf, sizeof(buf), "yes, disabled"); + fp_imp = MIPS32_FP_IMP_UNKNOWN; + } + + mips32->fpu_in_64bit = fpu_in_64bit; + mips32->fpu_enabled = fp_enabled; + + mips32_set_all_fpr_width(mips32, fpu_in_64bit); + + /* If fpu is not disabled, print out more information */ + if (!buf[0]) + snprintf(buf, sizeof(buf), "yes, %sbit (%s, working in %sbit)", + fp_imp == MIPS32_FP_IMP_64 ? "64" : "32", + fp_enabled ? "enabled" : "disabled", + fpu_in_64bit ? "64" : "32"); + + LOG_USER("FPU implemented: %s", buf); + mips32->fp_imp = fp_imp; + + return ERROR_OK; +} + +/** + * mips32_read_config_fdc - Read Fast Debug Channel configuration + * @param[in,out] mips32: MIPS32 common structure + * @param[in] ejtag_info: EJTAG information structure + * @param[in] dcr: Device Configuration Register value + * + * @brief Checks if the current target implements the Common Device Memory Map (CDMM) and Fast Debug Channel (FDC). + * + * This function examines the configuration registers and the Device Configuration Register (DCR) to determine + * if the current MIPS32 target supports the Common Device Memory Map (CDMM) and the Fast Debug Channel (FDC). + * If supported, it sets the corresponding flags in the MIPS32 common structure. \n + * + * NOTE:These are defined on MD00090, page 67 and MD00047F, page 82, respectively. + * MIPS Documents are pretty much all available online, + * it should pop up first when you search "MDxxxxx" + */ +static void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr) +{ + if (((ejtag_info->config[3] & MIPS32_CONFIG3_CDMM_MASK) != 0) && ((dcr & EJTAG_DCR_FDC) != 0)) { + mips32->fdc = 1; + mips32->semihosting = 1; + } else { + mips32->fdc = 0; + mips32->semihosting = 0; + } +} + /* read config to config3 cp0 registers and log isa implementation */ int mips32_read_config_regs(struct target *target) { struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + char buf[60] = {0}; + int retval; if (ejtag_info->config_regs == 0) for (int i = 0; i != 4; i++) { - int retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i); + retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i); if (retval != ERROR_OK) { LOG_ERROR("isa info not available, failed to read cp0 config register: %" PRId32, i); ejtag_info->config_regs = 0; @@ -716,27 +1176,56 @@ int mips32_read_config_regs(struct target *target) LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs); + mips32->isa_rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; + snprintf(buf, sizeof(buf), ", release %s(AR=%d)", + mips32->isa_rel == MIPS32_RELEASE_1 ? "1" + : mips32->isa_rel == MIPS32_RELEASE_2 ? "2" + : mips32->isa_rel == MIPS32_RELEASE_6 ? "6" + : "unknown", mips32->isa_rel); + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { mips32->isa_imp = MIPS32_MIPS16; - LOG_USER("MIPS32 with MIPS16 support implemented"); - + LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf); } else if (ejtag_info->config_regs >= 4) { /* config3 implemented */ - unsigned isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT; + unsigned int isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT; if (isa_imp == 1) { mips32->isa_imp = MMIPS32_ONLY; - LOG_USER("MICRO MIPS32 only implemented"); + LOG_USER("ISA implemented: %s%s", "microMIPS32", buf); } else if (isa_imp != 0) { mips32->isa_imp = MIPS32_MMIPS32; - LOG_USER("MIPS32 and MICRO MIPS32 implemented"); + LOG_USER("ISA implemented: %s%s", "MIPS32, microMIPS32", buf); } + } else if (mips32->isa_imp == MIPS32_ONLY) { + /* initial default value */ + LOG_USER("ISA implemented: %s%s", "MIPS32", buf); + } + + /* Retrieve DSP info */ + mips32_read_config_dsp(mips32, ejtag_info); + + /* Retrieve if Float Point CoProcessor Implemented */ + retval = mips32_read_config_fpu(mips32, ejtag_info); + if (retval != ERROR_OK) { + LOG_ERROR("fpu info is not available, error while reading cp0 status"); + mips32->fp_imp = MIPS32_FP_IMP_NONE; + return retval; + } + + uint32_t dcr; + + retval = target_read_u32(target, EJTAG_DCR, &dcr); + if (retval != ERROR_OK) { + LOG_ERROR("failed to read EJTAG_DCR register"); + return retval; } - if (mips32->isa_imp == MIPS32_ONLY) /* initial default value */ - LOG_USER("MIPS32 only implemented"); + /* Determine if FDC and CDMM are implemented for this core */ + mips32_read_config_fdc(mips32, ejtag_info, dcr); return ERROR_OK; } + int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum) { @@ -803,7 +1292,7 @@ int mips32_checksum_memory(struct target *target, target_addr_t address, init_reg_param(®_params[1], "r5", 32, PARAM_OUT); buf_set_u32(reg_params[1].value, 0, 32, count); - int timeout = 20000 * (1 + (count / (1024 * 1024))); + unsigned int timeout = 20000 * (1 + (count / (1024 * 1024))); retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout, &mips32_info); @@ -905,16 +1394,852 @@ static int mips32_verify_pointer(struct command_invocation *cmd, } /** - * MIPS32 targets expose command interface - * to manipulate CP0 registers + * mips32_read_config_mmu - Reads MMU configuration and logs relevant information. + * @param[in] ejtag_info: EJTAG interface information. + * + * @brief Reads the MMU configuration from the CP0 register and calculates the number of TLB entries, + * ways, and sets. Handles different MMU types like VTLB only, root RPU/Fixed, and VTLB and FTLB. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_read_config_mmu(struct mips_ejtag *ejtag_info) +{ + uint32_t config4, tlb_entries = 0, ways = 0, sets = 0; + uint32_t config0 = ejtag_info->config[0]; + uint32_t config1 = ejtag_info->config[1]; + uint32_t config3 = ejtag_info->config[3]; + uint32_t mmu_type = (config0 >> 7) & 7; + uint32_t vz_present = (config3 & BIT(23)); + + int retval = mips32_cp0_read(ejtag_info, &config4, 16, 4); + if (retval != ERROR_OK) + return retval; + + /* mmu type = 1: VTLB only (Note: Does not account for Config4.ExtVTLB) + * mmu type = 3: root RPU/Fixed (Note: Only valid with VZ ASE) + * mmu type = 4: VTLB and FTLB + */ + if ((mmu_type == 1 || mmu_type == 4) || (mmu_type == 3 && vz_present)) { + tlb_entries = (uint32_t)(((config1 >> 25) & 0x3f) + 1); + if (mmu_type == 4) { + /* Release 6 definition for Config4[0:15] (MD01251, page 243) */ + /* The FTLB ways field is defined as [2, 3, 4, 5, 6, 7, 8, ...0 (reserved)] */ + int index = ((config4 >> 4) & 0xf); + ways = index > 6 ? 0 : index + 2; + + /* The FTLB sets field is defined as [1, 2, 4, 8, ..., 16384, 32768] (powers of 2) */ + index = (config4 & 0xf); + sets = 1 << index; + tlb_entries = tlb_entries + (ways * sets); + } + } + LOG_USER("TLB Entries: %d (%d ways, %d sets per way)", tlb_entries, ways, sets); + + return ERROR_OK; +} + +/** + * mips32_cp0_find_register_by_name - Find CP0 register by its name. + * @param[in] cp0_mask: Mask to filter out irrelevant registers. + * @param[in] reg_name: Name of the register to find. + * + * @brief This function iterates through mips32_cp0_regs to find a register + * matching reg_name, considering cp0_mask to filter out registers + * not relevant for the current core. + * + * @return Pointer to the found register, or NULL if not found. + */ +static const struct mips32_cp0 *mips32_cp0_find_register_by_name(uint32_t cp0_mask, const char *reg_name) +{ + if (reg_name) + for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) { + if ((mips32_cp0_regs[i].core & cp0_mask) == 0) + continue; + + if (strcmp(mips32_cp0_regs[i].name, reg_name) == 0) + return &mips32_cp0_regs[i]; + } + return NULL; +} + +/** + * mips32_cp0_get_all_regs - Print all CP0 registers and their values. + * @param[in] cmd: Command invocation context. + * @param[in] ejtag_info: EJTAG interface information. + * @param[in] cp0_mask: Mask to identify relevant registers. + * + * @brief Iterates over all CP0 registers, reads their values, and prints them. + * Only considers registers relevant to the current core, as defined by cp0_mask. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_cp0_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask) +{ + uint32_t value; + + for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) { + /* Register name not valid for this core */ + if ((mips32_cp0_regs[i].core & cp0_mask) == 0) + continue; + + int retval = mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel); + if (retval != ERROR_OK) { + command_print(CMD, "Error: couldn't access reg %s", mips32_cp0_regs[i].name); + return retval; + } + + command_print(CMD, "%*s: 0x%8.8" PRIx32, 14, mips32_cp0_regs[i].name, value); + } + return ERROR_OK; +} + +/** + * mips32_cp0_get_reg_by_name - Read and print a CP0 register's value by name. + * @param[in] cmd: Command invocation context. + * @param[in] ejtag_info: EJTAG interface information. + * @param[in] cp0_mask: Mask to identify relevant registers. + * + * @brief Finds a CP0 register by name, reads its value, and prints it. + * Handles error scenarios like register not found or read failure. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_cp0_get_reg_by_name(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask) +{ + const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(cp0_mask, CMD_ARGV[0]); + if (!cp0_regs) { + command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + uint32_t value; + int retval = mips32_cp0_read(ejtag_info, &value, cp0_regs->reg, cp0_regs->sel); + if (retval != ERROR_OK) { + command_print(CMD, "Error: Encounter an Error while reading cp0 reg %d sel %d", + cp0_regs->reg, cp0_regs->sel); + return retval; + } + + command_print(CMD, "0x%8.8" PRIx32, value); + return ERROR_OK; +} + +/** + * mips32_cp0_get_reg_by_number - Read and print a CP0 register's value by number. + * @param[in] cmd: Command invocation context. + * @param[in] ejtag_info: EJTAG interface information. + * + * @brief Reads a specific CP0 register (identified by number and selection) and prints its value. + * The register number and selection are parsed from the command arguments. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_cp0_get_reg_by_number(struct command_invocation *cmd, struct mips_ejtag *ejtag_info) +{ + uint32_t cp0_reg, cp0_sel, value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); + + int retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { + command_print(CMD, + "Error: couldn't access reg %" PRIu32, + cp0_reg); + return retval; + } + + command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32, + cp0_reg, cp0_sel, value); + return ERROR_OK; +} + +/** + * mips32_cp0_set_reg_by_name - Write to a CP0 register identified by name. + * @param[in] cmd: Command invocation context. + * @param[in] mips32: Common MIPS32 data structure. + * @param[in] ejtag_info: EJTAG interface information. + * + * @brief Writes a value to a CP0 register specified by name. Updates internal + * cache if specific registers (STATUS, CAUSE, DEPC, GUESTCTL1) are modified. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_cp0_set_reg_by_name(struct command_invocation *cmd, + struct mips32_common *mips32, struct mips_ejtag *ejtag_info) +{ + const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(mips32->cp0_mask, CMD_ARGV[0]); + if (!cp0_regs) { + command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + + if (cp0_regs->reg == MIPS32_C0_STATUS && cp0_regs->sel == 0) { + /* Update cached Status register if user is writing to Status */ + mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1; + } else if (cp0_regs->reg == MIPS32_C0_CAUSE && cp0_regs->sel == 0) { + /* Update register cache with new value if its Cause */ + mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1; + } else if (cp0_regs->reg == MIPS32_C0_DEPC && cp0_regs->sel == 0) { + /* Update cached PC if its DEPC */ + mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1; + } else if (cp0_regs->reg == MIPS32_C0_GUESTCTL1 && cp0_regs->sel == 4) { + /* Update cached guestCtl1 */ + mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1; + } + + int retval = mips32_cp0_write(ejtag_info, value, + cp0_regs->reg, + cp0_regs->sel); + if (retval != ERROR_OK) { + command_print(CMD, "Error: Encounter an Error while writing to cp0 reg %d, sel %d", + cp0_regs->reg, cp0_regs->sel); + return retval; + } + + command_print(CMD, "cp0 reg %s (%u, select %u: %8.8" PRIx32 ")", + CMD_ARGV[0], cp0_regs->reg, cp0_regs->sel, value); + return ERROR_OK; +} + +/** + * mips32_cp0_set_reg_by_number - Write to a CP0 register identified by number. + * @param[in] cmd: Command invocation context. + * @param[in] mips32: Common MIPS32 data structure. + * @param[in] ejtag_info: EJTAG interface information. + * + * @brief Writes a value to a CP0 register specified by number and selection. + * Handles special cases like updating the internal cache for certain registers. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_cp0_set_reg_by_number(struct command_invocation *cmd, + struct mips32_common *mips32, struct mips_ejtag *ejtag_info) +{ + uint32_t cp0_reg, cp0_sel, value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); + + if (cp0_reg == MIPS32_C0_STATUS && cp0_sel == 0) { + /* Update cached status register if user is writing to Status register */ + mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1; + } else if (cp0_reg == MIPS32_C0_CAUSE && cp0_sel == 0) { + /* Update register cache with new value if its Cause register */ + mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1; + } else if (cp0_reg == MIPS32_C0_DEPC && cp0_sel == 0) { + /* Update cached PC if its DEPC */ + mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1; + } else if (cp0_reg == MIPS32_C0_GUESTCTL1 && cp0_sel == 4) { + /* Update cached guestCtl1, too */ + mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1; + } + + int retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { + command_print(CMD, + "Error: couldn't access cp0 reg %" PRIu32 ", select %" PRIu32, + cp0_reg, cp0_sel); + return retval; + } + + command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32, + cp0_reg, cp0_sel, value); + return ERROR_OK; +} + +/** + * mips32_handle_cp0_command - Handle commands related to CP0 registers. + * @cmd: Command invocation context. + * + * Orchestrates different operations on CP0 registers based on the command arguments. + * Supports operations like reading all registers, reading/writing a specific register + * by name or number. + * + * Return: ERROR_OK on success; error code on failure. */ COMMAND_HANDLER(mips32_handle_cp0_command) +{ + int retval, tmp; + struct target *target = get_current_target(CMD_CTX); + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + + retval = mips32_verify_pointer(CMD, mips32); + if (retval != ERROR_OK) + return retval; + + if (target->state != TARGET_HALTED) { + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; + } + + switch (CMD_ARGC) { + case 0: /* No arg => print out all cp0 regs */ + retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask); + break; + case 1: /* 1 arg => get cp0 #reg/#sel value by name */ + retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask); + break; + case 2: /* 2 args => get cp0 reg/sel value or set value by name */ + tmp = *CMD_ARGV[0]; + if (isdigit(tmp)) /* starts from number then args are #reg and #sel */ + retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info); + else /* or set value by register name */ + retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info); + + break; + case 3: /* 3 args => set cp0 reg/sel value*/ + retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info); + break; + default: /* Other argc => err */ + retval = ERROR_COMMAND_SYNTAX_ERROR; + break; + } + + return retval; +} + +/** + * mips32_dsp_enable - Enable access to DSP registers + * @param[in] ctx: Context information for the pracc queue + * @param[in] isa: Instruction Set Architecture identifier + * + * @brief Enables access to DSP registers by modifying the status register. + * + * This function adds instructions to the context queue for enabling + * access to DSP registers by modifying the status register. + */ +static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa) +{ + /* Save Status Register */ + /* move status to $9 (t1) 2*/ + pracc_add(ctx, 0, MIPS32_MFC0(isa, 9, 12, 0)); + + /* Read it again in order to modify it */ + /* move status to $0 (t0) 3*/ + pracc_add(ctx, 0, MIPS32_MFC0(isa, 8, 12, 0)); + + /* Enable access to DSP registers by setting MX bit in status register */ + /* $15 = MIPS32_PRACC_STACK 4/5/6*/ + pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE))); + pracc_add(ctx, 0, MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_DSP_ENABLE))); + pracc_add(ctx, 0, MIPS32_ISA_OR(8, 8, 15)); + /* Enable DSP - update status registers 7*/ + pracc_add(ctx, 0, MIPS32_MTC0(isa, 8, 12, 0)); +} + +/** + * mips32_dsp_restore - Restore DSP status registers to the previous setting + * @param[in] ctx: Context information pracc queue + * @param[in] isa: isa identifier + * + * @brief Restores the DSP status registers to their previous setting. + * + * This function adds instructions to the context queue for restoring the DSP + * status registers to their values before the operation. + */ +static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa) +{ + pracc_add(ctx, 0, MIPS32_MTC0(isa, 9, 12, 0)); /* Restore status registers to previous setting */ + pracc_add(ctx, 0, MIPS32_NOP); /* nop */ +} + +/** + * mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register + * @param[in] ejtag_info: EJTAG information structure + * @param[out] val: Pointer to store the read value + * @param[in] reg: Index of the DSP register to read + * + * @brief Reads the value from the specified MIPS32 DSP register using EJTAG access. + * + * This function initiates a sequence of instructions to read the value from the + * specified DSP register. It will enable dsp module if its not enabled + * and restoring the status registers after the read operation. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg) +{ + int isa = 0; + + struct pracc_queue_info ctx = { + .max_code = 48, + .ejtag_info = ejtag_info + }; + + uint32_t dsp_read_code[] = { + MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */ + MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */ + MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */ + MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */ + MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/ + MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */ + MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */ + }; + + /* Check status register to determine if dsp register access is enabled */ + /* Get status register so it can be restored later */ + + ctx.pracc_list = NULL; + + /* Init context queue */ + pracc_queue_init(&ctx); + + if (ctx.retval != ERROR_OK) + goto exit; + + /* Enables DSP whether its already enabled or not */ + mips32_dsp_enable(&ctx, isa); + + /* move AC or Control to $8 (t0) 8*/ + pracc_add(&ctx, 0, dsp_read_code[reg]); + /* Restore status registers to previous setting */ + mips32_dsp_restore(&ctx, isa); + + /* $15 = MIPS32_PRACC_BASE_ADDR 1*/ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR)); + /* store $8 to pracc_out 10*/ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(isa, 8, PRACC_OUT_OFFSET, 15)); + /* move COP0 DeSave to $15 11*/ + pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0)); + /* restore upper 16 of $8 12*/ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8))); + /* restore lower 16 of $8 13*/ + pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8))); + /* restore upper 16 of $9 14*/ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9))); + pracc_add(&ctx, 0, MIPS32_SYNC(isa)); + /* jump to start 18*/ + pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1))); + /* restore lower 16 of $9 15*/ + pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9))); + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1); +exit: + pracc_queue_free(&ctx); + return ctx.retval; +} + +/** + * mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register + * @param[in] ejtag_info: EJTAG information structure + * @param[in] val: Value to be written to the register + * @param[in] reg: Index of the DSP register to write + * + * @brief Writes the specified value to the specified MIPS32 DSP register. + * + * This function initiates a sequence of instructions to write the given value to the + * specified DSP register. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg) +{ + int isa = 0; + + struct pracc_queue_info ctx = { + .max_code = 48, + .ejtag_info = ejtag_info + }; + + uint32_t dsp_write_code[] = { + MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */ + MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */ + MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */ + MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */ + MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */ + MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */ + MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/ + }; + + /* Init context queue */ + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + /* Enables DSP whether its already enabled or not */ + mips32_dsp_enable(&ctx, isa); + + /* Load val to $8 (t0) */ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val))); + pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(val))); + + /* move AC or Control to $8 (t0) */ + pracc_add(&ctx, 0, dsp_write_code[reg]); + + /* nop, delay in order to ensure write */ + pracc_add(&ctx, 0, MIPS32_NOP); + /* Restore status registers to previous setting */ + mips32_dsp_restore(&ctx, isa); + + /* move COP0 DeSave to $15 */ + pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0)); + + /* restore $8 */ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8))); + pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8))); + + /* restore upper 16 of $9 */ + pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9))); + + /* jump to start */ + pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1))); + /* restore lower 16 of $9 */ + pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9))); + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1); +exit: + pracc_queue_free(&ctx); + return ctx.retval; +} + +/** + * mips32_handle_cpuinfo_command - Handles the 'cpuinfo' command. + * @param[in] cmd: Command invocation context. + * + * @brief Executes the 'cpuinfo' command which displays detailed information about the current CPU core. + * This includes core type, vendor, instruction set, cache size, and other relevant details. + * + * @return ERROR_OK on success; error code on failure. + */ +COMMAND_HANDLER(mips32_handle_cpuinfo_command) { int retval; struct target *target = get_current_target(CMD_CTX); struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + uint32_t prid = mips32->prid; /* cp0 PRID - 15, 0 */ + uint32_t config0 = ejtag_info->config[0]; /* cp0 config - 16, 0 */ + uint32_t config1 = ejtag_info->config[1]; /* cp0 config - 16, 1 */ + uint32_t config3 = ejtag_info->config[3]; /* cp0 config - 16, 3 */ + + /* Following configs are not read during probe */ + uint32_t config5; /* cp0 config - 16, 5 */ + + /* No args for now */ + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (target->state != TARGET_HALTED) { + command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; + } + + retval = mips32_cp0_read(ejtag_info, &config5, 16, 5); + if (retval != ERROR_OK) + return retval; + + /* Determine Core info */ + const struct cpu_entry *entry = mips32->cpu_info; + /* Display Core Type info */ + command_print(CMD, "CPU Core: %s", entry->cpu_name); + + /* Display Core Vendor ID if it's unknown */ + if (entry == &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1]) + command_print(CMD, "Vendor: Unknown CPU vendor code %x.", ((prid & 0x00ffff00) >> 16)); + else + command_print(CMD, "Vendor: %s", entry->vendor); + + /* If MIPS release 2 or above, then get exception base info */ + enum mips32_isa_rel ar = mips32->isa_rel; + if (ar > MIPS32_RELEASE_1) { /* release 2 and above */ + uint32_t ebase; + retval = mips32_cp0_read(ejtag_info, &ebase, 15, 1); + if (retval != ERROR_OK) + return retval; + + command_print(CMD, "Current CPU ID: %d", (ebase & 0x1ff)); + } else { + command_print(CMD, "Current CPU ID: 0"); + } + + char *instr; + switch ((config3 & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT) { + case 0: + instr = "MIPS32"; + break; + case 1: + instr = "microMIPS"; + break; + case 2: + instr = "MIPS32 (at reset) and microMIPS"; + break; + case 3: + default: + instr = "microMIPS (at reset) and MIPS32"; + break; + } + + /* Display Instruction Set Info */ + command_print(CMD, "Instr set: %s", instr); + command_print(CMD, "Instr rel: %s", + ar == MIPS32_RELEASE_1 ? "1" + : ar == MIPS32_RELEASE_2 ? "2" + : ar == MIPS32_RELEASE_6 ? "6" + : "unknown"); + command_print(CMD, "PRId: %x", prid); + /* Some of MIPS CPU Revisions(for M74K) can be seen on MD00541, page 26 */ + uint32_t rev = prid & 0x000000ff; + command_print(CMD, "RTL Rev: %d.%d.%d", (rev & 0xE0), (rev & 0x1C), (rev & 0x3)); + + command_print(CMD, "Max Number of Instr Breakpoints: %d", mips32->num_inst_bpoints); + command_print(CMD, "Max Number of Data Breakpoints: %d", mips32->num_data_bpoints); + + /* MMU Support */ + uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */ + char *mmu; + switch (mmu_type) { + case MIPS32_MMU_TLB: + mmu = "TLB"; + break; + case MIPS32_MMU_BAT: + mmu = "BAT"; + break; + case MIPS32_MMU_FIXED: + mmu = "FIXED"; + break; + case MIPS32_MMU_DUAL_VTLB_FTLB: + mmu = "DUAL VAR/FIXED"; + break; + default: + mmu = "Unknown"; + } + command_print(CMD, "MMU Type: %s", mmu); + + retval = mips32_read_config_mmu(ejtag_info); + if (retval != ERROR_OK) + return retval; + + /* Definitions of I/D Cache Sizes are available on MD01251, page 224~226 */ + int index; + uint32_t ways, sets, bpl; + + /* Determine Instr Cache Size */ + /* Ways mapping = [1, 2, 3, 4, 5, 6, 7, 8] */ + ways = ((config1 >> MIPS32_CFG1_IASHIFT) & 7); + + /* Sets per way = [64, 128, 256, 512, 1024, 2048, 4096, 32] */ + index = ((config1 >> MIPS32_CFG1_ISSHIFT) & 7); + sets = index == 7 ? 32 : 32 << (index + 1); + + /* Bytes per line = [0, 4, 8, 16, 32, 64, 128, Reserved] */ + index = ((config1 >> MIPS32_CFG1_ILSHIFT) & 7); + bpl = index == 0 ? 0 : 4 << (index - 1); + command_print(CMD, "Instr Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl); + + /* Determine data cache size, same as above */ + ways = ((config1 >> MIPS32_CFG1_DASHIFT) & 7); + + index = ((config1 >> MIPS32_CFG1_DSSHIFT) & 7); + sets = index == 7 ? 32 : 32 << (index + 1); + + index = ((config1 >> MIPS32_CFG1_DLSHIFT) & 7); + bpl = index == 0 ? 0 : 4 << (index - 1); + command_print(CMD, " Data Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl); + + /* does the core hava FPU*/ + mips32_read_config_fpu(mips32, ejtag_info); + + /* does the core support a DSP */ + mips32_read_config_dsp(mips32, ejtag_info); + + /* VZ module */ + uint32_t vzase = (config3 & BIT(23)); + if (vzase) + command_print(CMD, "VZ implemented: yes"); + else + command_print(CMD, "VZ implemented: no"); + + /* multithreading */ + uint32_t mtase = (config3 & BIT(2)); + if (mtase) { + command_print(CMD, "MT implemented: yes"); + + /* Get VPE and Thread info */ + uint32_t tcbind; + uint32_t mvpconf0; + + /* Read tcbind register */ + retval = mips32_cp0_read(ejtag_info, &tcbind, 2, 2); + if (retval != ERROR_OK) + return retval; + + command_print(CMD, " | Current VPE: %d", (tcbind & 0xf)); + command_print(CMD, " | Current TC: %d", ((tcbind >> 21) & 0xff)); + + /* Read mvpconf0 register */ + retval = mips32_cp0_read(ejtag_info, &mvpconf0, 0, 2); + if (retval != ERROR_OK) + return retval; + + command_print(CMD, " | Total TC: %d", (mvpconf0 & 0xf) + 1); + command_print(CMD, " | Total VPE: %d", ((mvpconf0 >> 10) & 0xf) + 1); + } else { + command_print(CMD, "MT implemented: no"); + } + + /* MIPS SIMD Architecture (MSA) */ + uint32_t msa = (config3 & BIT(28)); + command_print(CMD, "MSA implemented: %s", msa ? "yes" : "no"); + + /* Move To/From High COP0 (MTHC0/MFHC0) instructions are implemented. + * Implicates current ISA release >= 5.*/ + uint32_t mvh = (config5 & BIT(5)); + command_print(CMD, "MVH implemented: %s", mvh ? "yes" : "no"); + + /* Common Device Memory Map implemented? */ + uint32_t cdmm = (config3 & BIT(3)); + command_print(CMD, "CDMM implemented: %s", cdmm ? "yes" : "no"); + + return ERROR_OK; +} + +/** + * mips32_dsp_find_register_by_name - Find DSP register index by name + * @param[in] reg_name: Name of the DSP register to find + * + * @brief Searches for a DSP register by name and returns its index. + * If no match is found, it returns MIPS32NUMDSPREGS. + * + * @return Index of the found register or MIPS32NUMDSPREGS if not found. + */ +static int mips32_dsp_find_register_by_name(const char *reg_name) +{ + if (reg_name) + for (int i = 0; i < MIPS32NUMDSPREGS; i++) { + if (strcmp(mips32_dsp_regs[i].name, reg_name) == 0) + return i; + } + return MIPS32NUMDSPREGS; +} + +/** + * mips32_dsp_get_all_regs - Get values of all MIPS32 DSP registers + * @param[in] cmd: Command invocation context + * @param[in] ejtag_info: EJTAG information structure + * + * @brief This function iterates through all DSP registers, reads their values, + * and prints each register name along with its corresponding value. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32) +{ + uint32_t value = 0; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + for (int i = 0; i < MIPS32NUMDSPREGS; i++) { + int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i); + if (retval != ERROR_OK) { + command_print(CMD, "couldn't access reg %s", mips32_dsp_regs[i].name); + return retval; + } + mips32->core_regs.dsp[i] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + i].dirty = 1; + command_print(CMD, "%*s: 0x%8.8x", 7, mips32_dsp_regs[i].name, value); + } + return ERROR_OK; +} + +/** + * mips32_dsp_get_register - Get the value of a MIPS32 DSP register + * @param[in] cmd: Command invocation context + * @param[in] ejtag_info: EJTAG information structure + * + * @brief Retrieves the value of a specified MIPS32 DSP register. + * If the register is found, it reads the register value and prints the result. + * If the register is not found, it prints an error message. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32) +{ + uint32_t value = 0; + int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + if (index == MIPS32NUMDSPREGS) { + command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, index); + if (retval != ERROR_OK) { + command_print(CMD, "ERROR: Could not access dsp register %s", CMD_ARGV[0]); + return retval; + } + + command_print(CMD, "0x%8.8x", value); + + if (mips32->core_regs.dsp[index] != value) { + mips32->core_regs.dsp[index] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1; + } + + return retval; +} + +/** + * mips32_dsp_set_register - Set the value of a MIPS32 DSP register + * @param[in] cmd: Command invocation context + * @param[in] ejtag_info: EJTAG information structure + * + * @brief Sets the value of a specified MIPS32 DSP register. + * If the register is found, it writes provided value to the register. + * If the register is not found or there is an error in writing the value, + * it prints an error message. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32) +{ + uint32_t value; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]); + if (index == MIPS32NUMDSPREGS) { + command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + + int retval = mips32_pracc_write_dsp_reg(ejtag_info, value, index); + if (retval != ERROR_OK) { + command_print(CMD, "Error: could not write to dsp register %s", CMD_ARGV[0]); + return retval; + } + + mips32->core_regs.dsp[index] = value; + mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1; + + return retval; +} + +/** + * mips32_handle_dsp_command - Handles mips dsp related command + * @param[in] cmd: Command invocation context + * + * @brief Reads or sets the content of each dsp register. + * + * @return ERROR_OK on success; error code on failure. +*/ +COMMAND_HANDLER(mips32_handle_dsp_command) +{ + int retval, tmp; + struct target *target = get_current_target(CMD_CTX); + struct mips32_common *mips32 = target_to_mips32(target); retval = mips32_verify_pointer(CMD, mips32); if (retval != ERROR_OK) @@ -925,45 +2250,104 @@ COMMAND_HANDLER(mips32_handle_cp0_command) return ERROR_OK; } - /* two or more argument, access a single register/select (write if third argument is given) */ - if (CMD_ARGC < 2) + /* Check for too many command args */ + if (CMD_ARGC >= 3) return ERROR_COMMAND_SYNTAX_ERROR; - else { - uint32_t cp0_reg, cp0_sel; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); - if (CMD_ARGC == 2) { - uint32_t value; + /* Check if DSP access supported or not */ + if (!mips32->dsp_imp) { + /* Issue Error Message */ + command_print(CMD, "DSP not implemented by this processor"); + return ERROR_OK; + } - retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); - if (retval != ERROR_OK) { - command_print(CMD, - "couldn't access reg %" PRIu32, - cp0_reg); - return ERROR_OK; + switch (CMD_ARGC) { + case 0: + retval = mips32_dsp_get_all_regs(CMD, mips32); + break; + case 1: + retval = mips32_dsp_get_register(CMD, mips32); + break; + case 2: + tmp = *CMD_ARGV[0]; + if (isdigit(tmp)) { + command_print(CMD, "Error: invalid dsp command format"); + retval = ERROR_COMMAND_ARGUMENT_INVALID; + } else { + retval = mips32_dsp_set_register(CMD, mips32); } - command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); + break; + default: + command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC); + retval = ERROR_COMMAND_ARGUMENT_INVALID; + break; + } + return retval; +} - } else if (CMD_ARGC == 3) { - uint32_t value; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); - retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); - if (retval != ERROR_OK) { - command_print(CMD, - "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32, - cp0_reg, cp0_sel); - return ERROR_OK; - } - command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); - } +/** + * mips32_handle_ejtag_reg_command - Handler commands related to EJTAG + * @param[in] cmd: Command invocation context + * + * @brief Prints all EJTAG Registers including DCR features. + * + * @return ERROR_OK on success; error code on failure. + */ +COMMAND_HANDLER(mips32_handle_ejtag_reg_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + uint32_t ejtag_ctrl; + uint32_t dcr; + int retval; + + retval = mips_ejtag_get_idcode(ejtag_info); + if (retval != ERROR_OK) + command_print(CMD, "Error: Encounter an Error while getting idcode"); + else + command_print(CMD, " idcode: 0x%8.8" PRIx32, ejtag_info->idcode); + + retval = mips_ejtag_get_impcode(ejtag_info); + if (retval != ERROR_OK) + command_print(CMD, "Error: Encounter an Error while getting impcode"); + else + command_print(CMD, " impcode: 0x%8.8" PRIx32, ejtag_info->impcode); + + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + ejtag_ctrl = ejtag_info->ejtag_ctrl; + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + command_print(CMD, "Error: Encounter an Error while executing drscan reading EJTAG Control register"); + else + command_print(CMD, "ejtag control: 0x%8.8" PRIx32, ejtag_ctrl); + + ejtag_main_print_imp(ejtag_info); + + /* Display current DCR */ + retval = target_read_u32(target, EJTAG_DCR, &dcr); + if (retval != ERROR_OK) + command_print(CMD, "Error: Encounter an Error while reading Debug Control Register"); + else + command_print(CMD, " DCR: 0x%8.8" PRIx32, dcr); + + for (unsigned int i = 0; i < EJTAG_DCR_ENTRIES; i++) { + if (dcr & BIT(dcr_features[i].bit)) + command_print(CMD, "%s supported", dcr_features[i].name); } return ERROR_OK; } +/** + * mips32_handle_scan_delay_command - Handler command for changing scan delay + * @param[in] cmd: Command invocation context + * + * @brief Changes current scan mode between legacy and fast queued mode. + * + * @return ERROR_OK on success; error code on failure. + */ COMMAND_HANDLER(mips32_handle_scan_delay_command) { struct target *target = get_current_target(CMD_CTX); @@ -973,7 +2357,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command) if (CMD_ARGC == 1) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); else if (CMD_ARGC > 1) - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_SYNTAX_ERROR; command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay); if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { @@ -992,16 +2376,38 @@ static const struct command_registration mips32_exec_command_handlers[] = { .name = "cp0", .handler = mips32_handle_cp0_command, .mode = COMMAND_EXEC, - .usage = "regnum select [value]", + .usage = "[[reg_name|regnum select] [value]]", .help = "display/modify cp0 register", }, - { + { + .name = "cpuinfo", + .handler = mips32_handle_cpuinfo_command, + .mode = COMMAND_EXEC, + .help = "display CPU information", + .usage = "", + }, + { + .name = "dsp", + .handler = mips32_handle_dsp_command, + .mode = COMMAND_EXEC, + .help = "display or set DSP register; " + "with no arguments, displays all registers and their values", + .usage = "[[register_name] [value]]", + }, + { .name = "scan_delay", .handler = mips32_handle_scan_delay_command, .mode = COMMAND_ANY, .help = "display/set scan delay in nano seconds", .usage = "[value]", }, + { + .name = "ejtag_reg", + .handler = mips32_handle_ejtag_reg_command, + .mode = COMMAND_ANY, + .help = "read ejtag registers", + .usage = "", + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/mips32.h b/src/target/mips32.h index ca02dda451..3d919e7ddb 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -13,10 +13,12 @@ #ifndef OPENOCD_TARGET_MIPS32_H #define OPENOCD_TARGET_MIPS32_H +#include <helper/bits.h> + #include "target.h" #include "mips32_pracc.h" -#define MIPS32_COMMON_MAGIC 0xB320B320 +#define MIPS32_COMMON_MAGIC 0xB320B320U /** * Memory segments (32bit kernel mode addresses) @@ -44,9 +46,21 @@ #define MIPS32_CONFIG0_AR_SHIFT 10 #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT) +#define MIPS32_CONFIG1_FP_SHIFT 0 +#define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT) + #define MIPS32_CONFIG1_DL_SHIFT 10 #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT) +#define MIPS32_CONFIG3_CDMM_SHIFT 3 +#define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT) + +#define MIPS32_CONFIG3_DSPP_SHIFT 10 +#define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT) + +#define MIPS32_CONFIG3_DSPREV_SHIFT 11 +#define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT) + #define MIPS32_CONFIG3_ISA_SHIFT 14 #define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT) @@ -55,13 +69,183 @@ #define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000 +#define MIPS32NUMDSPREGS 7 + +/* Bit Mask indicating CP0 register supported by this core */ +#define MIPS_CP0_MK4 0x0001 +#define MIPS_CP0_MAPTIV_UC 0x0002 +#define MIPS_CP0_MAPTIV_UP 0x0004 +#define MIPS_CP0_IAPTIV 0x0008 + +/* CP0 Status register fields */ +#define MIPS32_CP0_STATUS_MX_SHIFT 24 +#define MIPS32_CP0_STATUS_FR_SHIFT 26 +#define MIPS32_CP0_STATUS_CU1_SHIFT 29 + +/* CP1 FIR register fields */ +#define MIPS32_CP1_FIR_F64_SHIFT 22 + +static const struct mips32_cp0 { + unsigned int reg; + unsigned int sel; + const char *name; + const unsigned int core; +} mips32_cp0_regs[] = { + {0, 0, "index", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {0, 1, "mvpcontrol", MIPS_CP0_IAPTIV}, + {0, 2, "mvpconf0", MIPS_CP0_IAPTIV}, + {0, 3, "mvpconf1", MIPS_CP0_IAPTIV}, + {1, 0, "random", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {1, 1, "vpecontrol", MIPS_CP0_IAPTIV}, + {1, 2, "vpeconf0", MIPS_CP0_IAPTIV}, + {1, 3, "vpeconf1", MIPS_CP0_IAPTIV}, + {1, 4, "yqmask", MIPS_CP0_IAPTIV}, + {1, 5, "vpeschedule", MIPS_CP0_IAPTIV}, + {1, 6, "vpeschefback", MIPS_CP0_IAPTIV}, + {1, 7, "vpeopt", MIPS_CP0_IAPTIV}, + {2, 0, "entrylo0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {2, 1, "tcstatus", MIPS_CP0_IAPTIV}, + {2, 2, "tcbind", MIPS_CP0_IAPTIV}, + {2, 3, "tcrestart", MIPS_CP0_IAPTIV}, + {2, 4, "tchalt", MIPS_CP0_IAPTIV}, + {2, 5, "tccontext", MIPS_CP0_IAPTIV}, + {2, 6, "tcschedule", MIPS_CP0_IAPTIV}, + {2, 7, "tcschefback", MIPS_CP0_IAPTIV}, + {3, 0, "entrylo1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {3, 7, "tcopt", MIPS_CP0_IAPTIV}, + {4, 0, "context", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {4, 2, "userlocal", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {5, 0, "pagemask", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {5, 1, "pagegrain", MIPS_CP0_MAPTIV_UP}, + {5, 2, "segctl0", MIPS_CP0_IAPTIV}, + {5, 3, "segctl1", MIPS_CP0_IAPTIV}, + {5, 4, "segctl2", MIPS_CP0_IAPTIV}, + {6, 0, "wired", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {6, 1, "srsconf0", MIPS_CP0_IAPTIV}, + {6, 2, "srsconf1", MIPS_CP0_IAPTIV}, + {6, 3, "srsconf2", MIPS_CP0_IAPTIV}, + {6, 4, "srsconf3", MIPS_CP0_IAPTIV}, + {6, 5, "srsconf4", MIPS_CP0_IAPTIV}, + {7, 0, "hwrena", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {8, 0, "badvaddr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {8, 1, "badinstr", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, + {8, 2, "badinstrp", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, + {9, 0, "count", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {10, 0, "entryhi", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP}, + {10, 4, "guestctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {10, 5, "guestctl2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {10, 6, "guestctl3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {11, 0, "compare", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {11, 4, "guestctl0ext", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {12, 0, "status", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {12, 1, "intctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {12, 2, "srsctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {12, 3, "srsmap", MIPS_CP0_IAPTIV}, + {12, 3, "srsmap1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, + {12, 4, "view_ipl", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {12, 5, "srsmap2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, + {12, 6, "guestctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {12, 7, "gtoffset", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4}, + {13, 0, "cause", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {13, 5, "nestedexc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {14, 0, "epc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {14, 2, "nestedepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {15, 0, "prid", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {15, 1, "ebase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {15, 2, "cdmmbase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {15, 3, "cmgcrbase", MIPS_CP0_IAPTIV}, + {16, 0, "config", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 1, "config1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 2, "config2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 3, "config3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 4, "config4", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 5, "config5", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {16, 7, "config7", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {17, 0, "lladdr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {18, 0, "watchlo0", MIPS_CP0_IAPTIV}, + {18, 1, "watchlo1", MIPS_CP0_IAPTIV}, + {18, 2, "watchlo2", MIPS_CP0_IAPTIV}, + {18, 3, "watchlo3", MIPS_CP0_IAPTIV}, + {19, 0, "watchhi0", MIPS_CP0_IAPTIV}, + {19, 1, "watchhi1", MIPS_CP0_IAPTIV}, + {19, 2, "watchhi2", MIPS_CP0_IAPTIV}, + {19, 3, "watchhi3", MIPS_CP0_IAPTIV}, + {23, 0, "debug", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {23, 1, "tracecontrol", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {23, 2, "tracecontrol2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {23, 3, "usertracedata1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {23, 4, "tracebpc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {23, 4, "traceibpc", MIPS_CP0_IAPTIV}, + {23, 5, "tracedbpc", MIPS_CP0_IAPTIV}, + {24, 0, "depc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {24, 2, "tracecontrol3", MIPS_CP0_IAPTIV}, + {24, 3, "usertracedata2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {25, 0, "perfctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {25, 1, "perfcnt0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {25, 2, "perfctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {25, 3, "perfcnt1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {26, 0, "errctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {27, 0, "cacheerr", MIPS_CP0_IAPTIV}, + {28, 0, "itaglo", MIPS_CP0_IAPTIV}, + {28, 0, "taglo", MIPS_CP0_IAPTIV}, + {28, 1, "idatalo", MIPS_CP0_IAPTIV}, + {28, 1, "datalo", MIPS_CP0_IAPTIV}, + {28, 2, "dtaglo", MIPS_CP0_IAPTIV}, + {28, 3, "ddatalo", MIPS_CP0_IAPTIV}, + {28, 4, "l23taglo", MIPS_CP0_IAPTIV}, + {28, 5, "l23datalo", MIPS_CP0_IAPTIV}, + {29, 1, "idatahi", MIPS_CP0_IAPTIV}, + {29, 2, "dtaghi", MIPS_CP0_IAPTIV}, + {29, 5, "l23datahi", MIPS_CP0_IAPTIV}, + {30, 0, "errorepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {31, 0, "desave", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4}, + {31, 2, "kscratch1", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, + {31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, +}; + +#define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs)) + +/* Insert extra NOPs after the DRET instruction on exit from debug. */ +#define EJTAG_QUIRK_PAD_DRET BIT(0) + /* offsets into mips32 core register cache */ enum { MIPS32_PC = 37, MIPS32_FIR = 71, + MIPS32_DSPCTL = 78, MIPS32NUMCOREREGS }; +/* offsets into mips32 core register cache */ + +#define MIPS32_REG_GP_COUNT 34 +#define MIPS32_REG_FP_COUNT 32 +#define MIPS32_REG_FPC_COUNT 2 +#define MIPS32_REG_C0_COUNT 5 +#define MIPS32_REG_DSP_COUNT 7 + +#define MIPS32_REGLIST_GP_INDEX 0 +#define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT) +#define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT) +#define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT) +#define MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT) + +#define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0) +#define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1) +#define MIPS32_REGLIST_C0_CAUSE_INDEX (MIPS32_REGLIST_C0_INDEX + 2) +#define MIPS32_REGLIST_C0_PC_INDEX (MIPS32_REGLIST_C0_INDEX + 3) +#define MIPS32_REGLIST_C0_GUESTCTL1_INDEX (MIPS32_REGLIST_C0_INDEX + 4) + +#define MIPS32_REG_C0_STATUS_INDEX 0 +#define MIPS32_REG_C0_BADVADDR_INDEX 1 +#define MIPS32_REG_C0_CAUSE_INDEX 2 +#define MIPS32_REG_C0_PC_INDEX 3 +#define MIPS32_REG_C0_GUESTCTL1_INDEX 4 + +#define MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6) + +#define MIPS32_REG_DSP_DSPCTL_INDEX 6 + enum mips32_isa_mode { MIPS32_ISA_MIPS32 = 0, MIPS32_ISA_MIPS16E = 1, @@ -75,20 +259,170 @@ enum mips32_isa_imp { MIPS32_MMIPS32 = 3, }; +/* Release 2~5 does not have much change regarding to the ISA under User mode, +* therefore no new Architecture Revision(AR) level is assigned to them. +* Release 6 changed some instruction's encoding/mnemonic, removed instructions that +* has lost its purposes/none are using, and added some new instructions as well. +*/ +enum mips32_isa_rel { + MIPS32_RELEASE_1 = 0, + MIPS32_RELEASE_2 = 1, + MIPS32_RELEASE_6 = 2, + MIPS32_RELEASE_UNKNOWN, +}; + +enum mips32_isa_supported { + MIPS16, + MIPS32, + MIPS64, + MICROMIPS_ONLY, + MIPS32_AT_RESET_AND_MICROMIPS, + MICROMIPS_AT_RESET_AND_MIPS32, +}; +#define MIPS32_CORE_MASK 0xFFFFFF00 +#define MIPS32_VARIANT_MASK 0x00FF + +/* This struct contains mips cpu types with their name respectively. + * The PrID register format is as following: + * - Company Optionsp[31:24] + * - Company ID[23:16] + * - Processor ID[15:8] + * - Revision[7:0] + * Here the revision field represents the maximum value of revision. + */ +static const struct cpu_entry { + uint32_t prid; + enum mips32_isa_supported isa; + const char *vendor; + const char *cpu_name; +} mips32_cpu_entry[] = { + /* MIPS Technologies cores */ + {0x000180FF, MIPS32, "MIPS", "4Kc"}, + {0x000181FF, MIPS64, "MIPS", "5Kc"}, + {0x000182FF, MIPS64, "MIPS", "20Kc"}, + {0x000183FF, MIPS32, "MIPS", "4KM"}, + + {0x000184FF, MIPS32, "MIPS", "4KEc"}, + {0x000190FF, MIPS32, "MIPS", "4KEc"}, + + {0x000185FF, MIPS32, "MIPS", "4KEm"}, + {0x000191FF, MIPS32, "MIPS", "4KEm"}, + + {0x000186FF, MIPS32, "MIPS", "4KSc"}, + {0x000187FF, MIPS32, "MIPS", "M4K"}, + {0x000188FF, MIPS64, "MIPS", "25Kf"}, + {0x000189FF, MIPS64, "MIPS", "5KEc"}, + {0x000192FF, MIPS32, "MIPS", "4KSD"}, + {0x000193FF, MIPS32, "MIPS", "24Kc"}, + {0x000195FF, MIPS32, "MIPS", "34Kc"}, + {0x000196FF, MIPS32, "MIPS", "24KEc"}, + {0x000197FF, MIPS32, "MIPS", "74Kc"}, + {0x000199FF, MIPS32, "MIPS", "1004Kc"}, + {0x00019AFF, MIPS32, "MIPS", "1074Kc"}, + {0x00019BFF, MIPS32, "MIPS", "M14K"}, + {0x00019CFF, MIPS32, "MIPS", "M14Kc"}, + {0x00019DFF, MIPS32, "MIPS", "microAptiv_UC(M14KE)"}, + {0x00019EFF, MIPS32, "MIPS", "microAptiv_UP(M14KEc)"}, + {0x0001A0FF, MIPS32, "MIPS", "interAptiv"}, + {0x0001A1FF, MIPS32, "MIPS", "interAptiv_CM"}, + {0x0001A2FF, MIPS32, "MIPS", "proAptiv"}, + {0x0001A3FF, MIPS32, "MIPS", "proAptiv_CM"}, + {0x0001A6FF, MIPS32, "MIPS", "M5100"}, + {0x0001A7FF, MIPS32, "MIPS", "M5150"}, + {0x0001A8FF, MIPS32, "MIPS", "P5600"}, + {0x0001A9FF, MIPS32, "MIPS", "I5500"}, + + /* Broadcom */ + {0x000200FF, MIPS32, "Broadcom", "Broadcom"}, + + /* AMD Alchemy Series*/ + /* NOTE: AMD/Alchemy series uses Company Option instead of + * Processor ID, to match the find function, Processor ID field + * is the copy of Company Option field */ + {0x000300FF, MIPS32, "AMD Alchemy", "AU1000"}, + {0x010301FF, MIPS32, "AMD Alchemy", "AU1500"}, + {0x020302FF, MIPS32, "AMD Alchemy", "AU1100"}, + {0x030303FF, MIPS32, "AMD Alchemy", "AU1550"}, + {0x04030401, MIPS32, "AMD Alchemy", "AU1200"}, + {0x040304FF, MIPS32, "AMD Alchemy", "AU1250"}, + {0x050305FF, MIPS32, "AMD Alchemy", "AU1210"}, + + /* Altera */ + {0x001000FF, MIPS32, "Altera", "Altera"}, + + /* Lexra */ + {0x000B00FF, MIPS32, "Lexra", "Lexra"}, + + /* Ingenic */ + {0x00e102FF, MIPS32, "Ingenic", "Ingenic XBurst rev1"}, + + {0xFFFFFFFF, MIPS32, "Unknown", "Unknown"} +}; + +#define MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry)) + +enum mips32_fp_imp { + MIPS32_FP_IMP_NONE = 0, + MIPS32_FP_IMP_32 = 1, + MIPS32_FP_IMP_64 = 2, + MIPS32_FP_IMP_UNKNOWN = 3, +}; + +enum mips32_dsp_imp { + MIPS32_DSP_IMP_NONE = 0, + MIPS32_DSP_IMP_REV1 = 1, + MIPS32_DSP_IMP_REV2 = 2, +}; + struct mips32_comparator { int used; uint32_t bp_value; uint32_t reg_address; }; +struct mips32_core_regs { + uint32_t gpr[MIPS32_REG_GP_COUNT]; + uint64_t fpr[MIPS32_REG_FP_COUNT]; + uint32_t fpcr[MIPS32_REG_FPC_COUNT]; + uint32_t cp0[MIPS32_REG_C0_COUNT]; + uint32_t dsp[MIPS32_REG_DSP_COUNT]; +}; + struct mips32_common { - uint32_t common_magic; + unsigned int common_magic; + void *arch_info; struct reg_cache *core_cache; struct mips_ejtag ejtag_info; - uint32_t core_regs[MIPS32NUMCOREREGS]; + + struct mips32_core_regs core_regs; + enum mips32_isa_mode isa_mode; enum mips32_isa_imp isa_imp; + enum mips32_isa_rel isa_rel; + enum mips32_fp_imp fp_imp; + enum mips32_dsp_imp dsp_imp; + + int fdc; + int semihosting; + + /* The cp0 registers implemented on different processor cores could be different, too. + * Here you can see most of the registers are implemented on interAptiv, which is + * a 2c4t SMP processor, it has more features than M-class processors, like vpe + * and other config registers for multhreading. */ + uint32_t cp0_mask; + + /* FPU enabled (cp0.status.cu1) */ + bool fpu_enabled; + /* FPU mode (cp0.status.fr) */ + bool fpu_in_64bit; + + /* processor identification register */ + uint32_t prid; + /* detected CPU type */ + const struct cpu_entry *cpu_info; + /* CPU specific quirks */ + uint32_t cpu_quirks; /* working area for fastdata access */ struct working_area *fast_data_area; @@ -119,7 +453,7 @@ struct mips32_core_reg { }; struct mips32_algorithm { - int common_magic; + unsigned int common_magic; enum mips32_isa_mode isa_mode; }; @@ -129,14 +463,18 @@ struct mips32_algorithm { #define MIPS32_OP_BEQ 0x04u #define MIPS32_OP_BGTZ 0x07u #define MIPS32_OP_BNE 0x05u +#define MIPS32_OP_ADD 0x20u #define MIPS32_OP_ADDI 0x08u #define MIPS32_OP_AND 0x24u #define MIPS32_OP_CACHE 0x2Fu #define MIPS32_OP_COP0 0x10u +#define MIPS32_OP_COP1 0x11u #define MIPS32_OP_J 0x02u #define MIPS32_OP_JR 0x08u #define MIPS32_OP_LUI 0x0Fu #define MIPS32_OP_LW 0x23u +#define MIPS32_OP_LWC1 0x31u +#define MIPS32_OP_LDC1 0x35u #define MIPS32_OP_LB 0x20u #define MIPS32_OP_LBU 0x24u #define MIPS32_OP_LHU 0x25u @@ -144,6 +482,7 @@ struct mips32_algorithm { #define MIPS32_OP_MTHI 0x11u #define MIPS32_OP_MFLO 0x12u #define MIPS32_OP_MTLO 0x13u +#define MIPS32_OP_MUL 0x02u #define MIPS32_OP_RDHWR 0x3Bu #define MIPS32_OP_SB 0x28u #define MIPS32_OP_SH 0x29u @@ -152,11 +491,15 @@ struct mips32_algorithm { #define MIPS32_OP_XORI 0x0Eu #define MIPS32_OP_XOR 0x26u #define MIPS32_OP_SLTU 0x2Bu -#define MIPS32_OP_SRL 0x03u +#define MIPS32_OP_SRL 0x02u +#define MIPS32_OP_SRA 0x03u #define MIPS32_OP_SYNCI 0x1Fu #define MIPS32_OP_SLL 0x00u +#define MIPS32_OP_SLLV 0x04u #define MIPS32_OP_SLTI 0x0Au #define MIPS32_OP_MOVN 0x0Bu +#define MIPS32_OP_SWC1 0x39u +#define MIPS32_OP_SDC1 0x3Du #define MIPS32_OP_REGIMM 0x01u #define MIPS32_OP_SDBBP 0x3Fu @@ -164,8 +507,11 @@ struct mips32_algorithm { #define MIPS32_OP_SPECIAL2 0x07u #define MIPS32_OP_SPECIAL3 0x1Fu -#define MIPS32_COP0_MF 0x00u -#define MIPS32_COP0_MT 0x04u +#define MIPS32_COP_MF 0x00u +#define MIPS32_COP_CF 0x02u +#define MIPS32_COP_MFH 0x03u +#define MIPS32_COP_MT 0x04u +#define MIPS32_COP_MTH 0x07u #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \ (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct)) @@ -174,6 +520,7 @@ struct mips32_algorithm { #define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr)) #define MIPS32_ISA_NOP 0 +#define MIPS32_ISA_ADD(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD) #define MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) #define MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val) #define MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU) @@ -185,33 +532,47 @@ struct mips32_algorithm { #define MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) #define MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) #define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) +#define MIPS32_ISA_CFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_CF, gpr, cpr, 0, 0) #define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2) #define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) +#define MIPS32_ISA_JRHB(reg) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR) #define MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off) #define MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off) #define MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) #define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) #define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) - -#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) -#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) +#define MIPS32_ISA_LWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LWC1, base, reg, off) +#define MIPS32_ISA_LDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LDC1, base, reg, off) + +#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel) +#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel) +#define MIPS32_ISA_MFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MF, gpr, cpr, 0, 0) +#define MIPS32_ISA_MFHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MFH, gpr, cpr, 0, 0) +#define MIPS32_ISA_MTC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MT, gpr, cpr, 0, 0) +#define MIPS32_ISA_MTHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MTH, gpr, cpr, 0, 0) #define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) #define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) #define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) #define MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) +#define MIPS32_ISA_MUL(dst, src, t) MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL) #define MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN) +#define MIPS32_ISA_OR(dst, src, val) MIPS32_R_INST(0, src, val, dst, 0, 37) #define MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) #define MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR) #define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) #define MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) #define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off) +#define MIPS32_ISA_SWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SWC1, base, reg, off) +#define MIPS32_ISA_SDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SDC1, base, reg, off) #define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL) +#define MIPS32_ISA_SLLV(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV) #define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val) #define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU) -#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) +#define MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA) +#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL) #define MIPS32_ISA_SYNC 0xFu #define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off) @@ -236,10 +597,12 @@ struct mips32_algorithm { #define MIPS16_ISA_SDBBP 0xE801u /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */ -#define POOL32A 0X00u -#define POOL32AXF 0x3Cu -#define POOL32B 0x08u -#define POOL32I 0x10u +#define MMIPS32_POOL32A 0x00u +#define MMIPS32_POOL32F 0x15u +#define MMIPS32_POOL32FXF 0x3Bu +#define MMIPS32_POOL32AXF 0x3Cu +#define MMIPS32_POOL32B 0x08u +#define MMIPS32_POOL32I 0x10u #define MMIPS32_OP_ADDI 0x04u #define MMIPS32_OP_ADDIU 0x0Cu #define MMIPS32_OP_ADDU 0x150u @@ -249,15 +612,23 @@ struct mips32_algorithm { #define MMIPS32_OP_BGTZ 0x06u #define MMIPS32_OP_BNE 0x2Du #define MMIPS32_OP_CACHE 0x06u +#define MMIPS32_OP_CFC1 0x40u #define MMIPS32_OP_J 0x35u #define MMIPS32_OP_JALR 0x03Cu +#define MMIPS32_OP_JALRHB 0x07Cu #define MMIPS32_OP_LB 0x07u #define MMIPS32_OP_LBU 0x05u #define MMIPS32_OP_LHU 0x0Du #define MMIPS32_OP_LUI 0x0Du #define MMIPS32_OP_LW 0x3Fu +#define MMIPS32_OP_LWC1 0x27u +#define MMIPS32_OP_LDC1 0x2Fu #define MMIPS32_OP_MFC0 0x03u +#define MMIPS32_OP_MFC1 0x80u +#define MMIPS32_OP_MFHC1 0xC0u #define MMIPS32_OP_MTC0 0x0Bu +#define MMIPS32_OP_MTC1 0xA0u +#define MMIPS32_OP_MTHC1 0xE0u #define MMIPS32_OP_MFLO 0x075u #define MMIPS32_OP_MFHI 0x035u #define MMIPS32_OP_MTLO 0x0F5u @@ -268,6 +639,8 @@ struct mips32_algorithm { #define MMIPS32_OP_SB 0x06u #define MMIPS32_OP_SH 0x0Eu #define MMIPS32_OP_SW 0x3Eu +#define MMIPS32_OP_SWC1 0x26u +#define MMIPS32_OP_SDC1 0x2Eu #define MMIPS32_OP_SLTU 0x390u #define MMIPS32_OP_SLL 0x000u #define MMIPS32_OP_SLTI 0x24u @@ -278,55 +651,68 @@ struct mips32_algorithm { #define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val) #define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val) -#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU) -#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND) +#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU) +#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND) #define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val) #define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off) #define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off) -#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off) +#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off) #define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off) -#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) +#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) +#define MMIPS32_CFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF) #define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1)))) -#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF) +#define MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF) +#define MMIPS32_JRHB(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF) #define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off) #define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off) #define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off) -#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val) +#define MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val) #define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off) - -#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF) -#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF) -#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF) -#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF) -#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF) -#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF) - -#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) +#define MMIPS32_LWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off) +#define MMIPS32_LDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off) + +#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\ + MMIPS32_OP_MFC0, MMIPS32_POOL32AXF) +#define MMIPS32_MFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF) +#define MMIPS32_MFHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF) +#define MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF) +#define MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF) +#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\ + MMIPS32_OP_MTC0, MMIPS32_POOL32AXF) +#define MMIPS32_MTC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF) +#define MMIPS32_MTHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF) +#define MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF) +#define MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF) + +#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) #define MMIPS32_NOP 0 #define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val) -#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF) +#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF) #define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off) #define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off) #define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off) - -#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL) -#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU) -#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off) -#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) +#define MMIPS32_SWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off) +#define MMIPS32_SDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off) + +#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL) +#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU) +#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off) +#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) +#define MMIPS32_SLLV(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV) #define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val) -#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */ +#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */ -#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) +#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) #define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val) #define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */ /* ejtag specific instructions */ -#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */ -#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */ +#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */ +#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */ #define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */ /* instruction code with isa selection */ @@ -342,30 +728,42 @@ struct mips32_algorithm { #define MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off)) #define MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off)) #define MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base)) +#define MIPS32_CFC1(isa, gpr, cpr) (isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr)) #define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar)) #define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg)) +#define MIPS32_JRHB(isa, reg) (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg)) #define MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base)) #define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base)) #define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base)) #define MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base)) +#define MIPS32_LWC1(isa, reg, off, base) (isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base)) #define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val)) #define MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel)) #define MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel)) +#define MIPS32_MFC1(isa, gpr, cpr) (isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr)) +#define MIPS32_MFHC1(isa, gpr, cpr) (isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr)) +#define MIPS32_MTC1(isa, gpr, cpr) (isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr)) +#define MIPS32_MTHC1(isa, gpr, cpr) (isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr)) #define MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg)) #define MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg)) #define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg)) #define MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg)) +#define MIPS32_MUL(isa, dst, src, t) (MIPS32_ISA_MUL(dst, src, t)) #define MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar)) #define MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val)) #define MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst)) #define MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base)) #define MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base)) #define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base)) +#define MIPS32_SWC1(isa, reg, off, base) (isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base)) +#define MIPS32_SDC1(isa, reg, off, base) (isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base)) #define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa)) +#define MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3)) +#define MIPS32_SLLV(isa, dst, src, sa) (MIPS32_ISA_SLLV(dst, src, sa)) #define MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val)) #define MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar)) #define MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off)) @@ -383,6 +781,122 @@ struct mips32_algorithm { #define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP) +/* ejtag specific instructions */ +#define MICRO_MIPS32_SDBBP 0x000046C0 +#define MICRO_MIPS_SDBBP 0x46C0 +#define MIPS32_DSP_ENABLE 0x1000000 + +#define MIPS32_S_INST(rs, rac, opcode) \ + (((rs) << 21) | ((rac) << 11) | (opcode)) + +#define MIPS32_DSP_R_INST(rt, immd, opcode, extrw) \ + ((0x1F << 26) | ((immd) << 16) | ((rt) << 11) | ((opcode) << 6) | (extrw)) +#define MIPS32_DSP_W_INST(rs, immd, opcode, extrw) \ + ((0x1F << 26) | ((rs) << 21) | ((immd) << 11) | ((opcode) << 6) | (extrw)) + +#define MIPS32_DSP_MFHI(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI) +#define MIPS32_DSP_MFLO(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO) +#define MIPS32_DSP_MTLO(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO) +#define MIPS32_DSP_MTHI(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI) +#define MIPS32_DSP_RDDSP(rt, mask) MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38) +#define MIPS32_DSP_WRDSP(rs, mask) MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38) + + +/* + * MIPS32 Config1 Register (CP0 Register 16, Select 1) + */ +#define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */ +#define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */ +#define MIPS32_CFG1_MMUSSHIFT 25 +#define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */ +#define MIPS32_CFG1_ISSHIFT 22 +#define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */ +#define MIPS32_CFG1_ILSHIFT 19 +#define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */ +#define MIPS32_CFG1_IASHIFT 16 +#define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */ +#define MIPS32_CFG1_DSSHIFT 13 +#define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */ +#define MIPS32_CFG1_DLSHIFT 10 +#define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */ +#define MIPS32_CFG1_DASHIFT 7 +#define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */ +#define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */ +#define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */ +#define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */ +#define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */ +#define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */ +#define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */ + +/* + * MIPS32 Coprocessor 0 register numbers + */ +#define MIPS32_C0_INDEX 0 +#define MIPS32_C0_INX 0 +#define MIPS32_C0_RANDOM 1 +#define MIPS32_C0_RAND 1 +#define MIPS32_C0_ENTRYLO0 2 +#define MIPS32_C0_TLBLO0 2 +#define MIPS32_C0_ENTRYLO1 3 +#define MIPS32_C0_TLBLO1 3 +#define MIPS32_C0_CONTEXT 4 +#define MIPS32_C0_CTXT 4 +#define MIPS32_C0_PAGEMASK 5 +#define MIPS32_C0_PAGEGRAIN (5, 1) +#define MIPS32_C0_WIRED 6 +#define MIPS32_C0_HWRENA 7 +#define MIPS32_C0_BADVADDR 8 +#define MIPS32_C0_VADDR 8 +#define MIPS32_C0_COUNT 9 +#define MIPS32_C0_ENTRYHI 10 +#define MIPS32_C0_TLBHI 10 +#define MIPS32_C0_GUESTCTL1 10 +#define MIPS32_C0_COMPARE 11 +#define MIPS32_C0_STATUS 12 +#define MIPS32_C0_SR 12 +#define MIPS32_C0_INTCTL (12, 1) +#define MIPS32_C0_SRSCTL (12, 2) +#define MIPS32_C0_SRSMAP (12, 3) +#define MIPS32_C0_CAUSE 13 +#define MIPS32_C0_CR 13 +#define MIPS32_C0_EPC 14 +#define MIPS32_C0_PRID 15 +#define MIPS32_C0_EBASE (15, 1) +#define MIPS32_C0_CONFIG 16 +#define MIPS32_C0_CONFIG0 (16, 0) +#define MIPS32_C0_CONFIG1 (16, 1) +#define MIPS32_C0_CONFIG2 (16, 2) +#define MIPS32_C0_CONFIG3 (16, 3) +#define MIPS32_C0_LLADDR 17 +#define MIPS32_C0_WATCHLO 18 +#define MIPS32_C0_WATCHHI 19 +#define MIPS32_C0_DEBUG 23 +#define MIPS32_C0_DEPC 24 +#define MIPS32_C0_PERFCNT 25 +#define MIPS32_C0_ERRCTL 26 +#define MIPS32_C0_CACHEERR 27 +#define MIPS32_C0_TAGLO 28 +#define MIPS32_C0_ITAGLO 28 +#define MIPS32_C0_DTAGLO (28, 2) +#define MIPS32_C0_TAGLO2 (28, 4) +#define MIPS32_C0_DATALO (28, 1) +#define MIPS32_C0_IDATALO (28, 1) +#define MIPS32_C0_DDATALO (28, 3) +#define MIPS32_C0_DATALO2 (28, 5) +#define MIPS32_C0_TAGHI 29 +#define MIPS32_C0_ITAGHI 29 +#define MIPS32_C0_DATAHI (29, 1) +#define MIPS32_C0_ERRPC 30 +#define MIPS32_C0_DESAVE 31 + +/* + * MIPS32 MMU types + */ +#define MIPS32_MMU_TLB 1 +#define MIPS32_MMU_BAT 2 +#define MIPS32_MMU_FIXED 3 +#define MIPS32_MMU_DUAL_VTLB_FTLB 4 + extern const struct command_registration mips32_command_handlers[]; int mips32_arch_state(struct target *target); @@ -399,7 +913,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); int mips32_configure_break_unit(struct target *target); @@ -407,6 +921,8 @@ int mips32_enable_interrupts(struct target *target, int enable); int mips32_examine(struct target *target); +int mips32_cpu_probe(struct target *target); + int mips32_read_config_regs(struct target *target); int mips32_register_commands(struct command_context *cmd_ctx); @@ -419,4 +935,7 @@ int mips32_checksum_memory(struct target *target, target_addr_t address, int mips32_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); +bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info); +bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info); + #endif /* OPENOCD_TARGET_MIPS32_H */ diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index 8c48754917..beffbf51ee 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by John McCarthy * diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 79d929c548..ea90d6f83a 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * @@ -61,6 +61,7 @@ #include <helper/time_support.h> #include <jtag/adapter.h> +#include "mips_cpu.h" #include "mips32.h" #include "mips32_pracc.h" @@ -150,7 +151,7 @@ static int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info) return ERROR_OK; } -int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, +static int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out, bool check_last) { int code_count = 0; @@ -211,7 +212,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct store_pending--; } else { /* read/fetch access */ - if (!final_check) { /* executing function code */ + if (!final_check) { /* executing function code */ /* check address */ if (ejtag_info->pa_addr != (MIPS32_PRACC_TEXT + code_count * 4)) { LOG_DEBUG("reading at unexpected address %" PRIx32 ", expected %x", @@ -242,7 +243,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct if (code_count == ctx->code_count) /* last instruction, start final check */ final_check = 1; - } else { /* final check after function code shifted out */ + } else { /* final check after function code shifted out */ /* check address */ if (ejtag_info->pa_addr == MIPS32_PRACC_TEXT) { if (!pass) { /* first pass through pracc text */ @@ -274,7 +275,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct } instr = MIPS32_NOP; /* shift out NOPs instructions */ code_count++; - } + } /* Send instruction out */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); @@ -323,7 +324,7 @@ void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr) ctx->store_count++; } -void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize) +static void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize) { if (LOWER16(data) == 0 && optimize) pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, reg_num, UPPER16(data))); /* load only upper value */ @@ -369,7 +370,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in return ERROR_FAIL; } - unsigned num_clocks = + unsigned int num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000; uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; @@ -399,7 +400,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32); uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32); if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) { - LOG_ERROR("Error: access not pending count: %d", scan_count); + LOG_ERROR("Access not pending, count: %d", scan_count); retval = ERROR_FAIL; goto exit; } @@ -452,6 +453,8 @@ static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, u pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper addr */ pracc_add(&ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */ + if (mips32_cpu_support_sync(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa)); pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */ @@ -508,6 +511,8 @@ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size else pracc_add(&ctx, 0, MIPS32_LBU(ctx.isa, 8, LOWER16(addr), 9)); + if (mips32_cpu_support_sync(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa)); pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + i * 4, /* store $8 at param out */ MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + i * 4, 15)); addr += size; @@ -550,6 +555,8 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r pracc_queue_init(&ctx); pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + if (mips32_cpu_support_hazard_barrier(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */ @@ -571,6 +578,8 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_r pracc_add_li32(&ctx, 15, val, 0); /* Load val to $15 */ pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */ + if (mips32_cpu_support_hazard_barrier(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */ @@ -579,6 +588,26 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_r return ctx.retval; } +int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp1_c_reg) +{ + struct pracc_queue_info ctx = {.ejtag_info = ejtag_info}; + pracc_queue_init(&ctx); + + pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); + pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, cp1_c_reg)); /* move cp1c reg to $8 */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */ + pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */ + pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */ + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1); + pracc_queue_free(&ctx); + return ctx.retval; +} + /** * \b mips32_pracc_sync_cache * @@ -786,6 +815,7 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz if ((KSEGX(addr) == KSEG1) || ((addr >= 0xff200000) && (addr <= 0xff3fffff))) return retval; /*Nothing to do*/ + /* Reads Config0 */ mips32_cp0_read(ejtag_info, &conf, 16, 0); switch (KSEGX(addr)) { @@ -813,19 +843,44 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz uint32_t start_addr = addr; uint32_t end_addr = addr + count * size; uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; - if (rel > 1) { - LOG_DEBUG("Unknown release in cache code"); + /* FIXME: In MIPS Release 6, the encoding of CACHE instr has changed */ + if (rel > MIPS32_RELEASE_2) { + LOG_DEBUG("Unsupported MIPS Release ( > 5)"); return ERROR_FAIL; } retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel); + } else { + struct pracc_queue_info ctx = {.ejtag_info = ejtag_info}; + + pracc_queue_init(&ctx); + if (mips32_cpu_support_sync(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa)); + if (mips32_cpu_support_hazard_barrier(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_NOP); + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1); + if (ctx.retval != ERROR_OK) { + LOG_ERROR("Unable to barrier"); + retval = ctx.retval; + } + pracc_queue_free(&ctx); } return retval; } -int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) +int mips32_pracc_write_regs(struct mips32_common *mips32) { + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct pracc_queue_info ctx = {.ejtag_info = ejtag_info}; + uint32_t *gprs = mips32->core_regs.gpr; + uint32_t *c0rs = mips32->core_regs.cp0; + bool fpu_in_64bit = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0); + bool fp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0); + bool dsp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0); + uint32_t rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; + pracc_queue_init(&ctx); uint32_t cp0_write_code[] = { @@ -837,69 +892,405 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) MIPS32_MTC0(ctx.isa, 1, 24, 0), /* move $1 to depc (pc) */ }; + uint32_t cp0_write_data[] = { + /* status */ + c0rs[0], + /* lo */ + gprs[32], + /* hi */ + gprs[33], + /* badvaddr */ + c0rs[1], + /* cause */ + c0rs[2], + /* depc (pc) */ + c0rs[3], + }; + + /* Write CP0 Status Register first, changes on EXL or ERL bits + * may lead to different behaviour on writing to other CP0 registers. + */ + for (size_t i = 0; i < ARRAY_SIZE(cp0_write_code); i++) { + /* load CP0 value in $1 */ + pracc_add_li32(&ctx, 1, cp0_write_data[i], 0); + /* write value from $1 to CP0 register */ + pracc_add(&ctx, 0, cp0_write_code[i]); + } + + if (mips32_cpu_support_hazard_barrier(ejtag_info)) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); + + /* store FPRs */ + if (mips32->fp_imp && fp_enabled) { + uint64_t *fprs = mips32->core_regs.fpr; + if (fpu_in_64bit) { + for (int i = 0; i != MIPS32_REG_FP_COUNT; i++) { + uint32_t fp_lo = fprs[i] & 0xffffffff; + uint32_t fp_hi = (fprs[i] >> 32) & 0xffffffff; + pracc_add_li32(&ctx, 2, fp_lo, 0); + pracc_add_li32(&ctx, 3, fp_hi, 0); + pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i)); + pracc_add(&ctx, 0, MIPS32_MTHC1(ctx.isa, 3, i)); + } + } else { + for (int i = 0; i != MIPS32_REG_FP_COUNT; i++) { + uint32_t fp_lo = fprs[i] & 0xffffffff; + pracc_add_li32(&ctx, 2, fp_lo, 0); + pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i)); + } + } + + if (rel > MIPS32_RELEASE_1) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); + } + + /* Store DSP Accumulators */ + if (mips32->dsp_imp && dsp_enabled) { + /* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */ + uint32_t *dspr = mips32->core_regs.dsp; + size_t dsp_regs = ARRAY_SIZE(mips32->core_regs.dsp); + + /* Starts from ac1, core_regs.dsp contains dspctl register, therefore - 1 */ + for (size_t index = 0; index != ((dsp_regs - 1) / 2); index++) { + /* Every accumulator have 2 registers, hi and lo, and core_regs.dsp stores ac[1~3] */ + /* reads hi[ac] from core_regs array */ + pracc_add_li32(&ctx, 2, dspr[index * 2], 0); + /* reads lo[ac] from core_regs array */ + pracc_add_li32(&ctx, 3, dspr[(index * 2) + 1], 0); + + /* Write to accumulator 1~3 and index starts from 0, therefore ac = index + 1 */ + size_t ac = index + 1; + pracc_add(&ctx, 0, MIPS32_DSP_MTHI(2, ac)); + pracc_add(&ctx, 0, MIPS32_DSP_MTLO(3, ac)); + } + + /* DSPCTL is the last element of register store */ + pracc_add_li32(&ctx, 2, dspr[6], 0); + pracc_add(&ctx, 0, MIPS32_DSP_WRDSP(2, 0x1F)); + + if (rel > MIPS32_RELEASE_1) + pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa)); + } + /* load registers 2 to 31 with li32, optimize */ for (int i = 2; i < 32; i++) - pracc_add_li32(&ctx, i, regs[i], 1); + pracc_add_li32(&ctx, i, gprs[i], 1); - for (int i = 0; i != 6; i++) { - pracc_add_li32(&ctx, 1, regs[i + 32], 0); /* load CPO value in $1 */ - pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */ - } - pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */ - pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((regs[1])))); /* load upper half word in $1 */ - pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ - pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */ + /* load $15 in DeSave */ + pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); + /* load upper half word in $1 */ + pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((gprs[1])))); + /* jump to start */ + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); + /* load lower half word in $1 */ + pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((gprs[1])))); ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1); - ejtag_info->reg8 = regs[8]; - ejtag_info->reg9 = regs[9]; + ejtag_info->reg8 = gprs[8]; + ejtag_info->reg9 = gprs[9]; pracc_queue_free(&ctx); return ctx.retval; } -int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) +/* Saves content in `$1` to `DeSave(cp0.31.0)` and loads `MIPS32_PRACC_BASE_ADDR` into `$1` */ +static void mips32_pracc_store_regs_set_base_addr(struct pracc_queue_info *ctx) { - struct pracc_queue_info ctx = {.ejtag_info = ejtag_info}; - pracc_queue_init(&ctx); + /* move $1 to COP0 DeSave */ + pracc_add(ctx, 0, MIPS32_MTC0(ctx->isa, 1, 31, 0)); + /* $1 = MIP32_PRACC_BASE_ADDR */ + pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, 1, PRACC_UPPER_BASE_ADDR)); +} - uint32_t cp0_read_code[] = { - MIPS32_MFC0(ctx.isa, 8, 12, 0), /* move status to $8 */ - MIPS32_MFLO(ctx.isa, 8), /* move lo to $8 */ - MIPS32_MFHI(ctx.isa, 8), /* move hi to $8 */ - MIPS32_MFC0(ctx.isa, 8, 8, 0), /* move badvaddr to $8 */ - MIPS32_MFC0(ctx.isa, 8, 13, 0), /* move cause to $8 */ - MIPS32_MFC0(ctx.isa, 8, 24, 0), /* move depc (pc) to $8 */ +/* This function assumes the address for saving is stored in `$1`. + * And that action is performed in `mips32_pracc_set_save_base_addr`. + */ +static void mips32_pracc_store_regs_gpr(struct pracc_queue_info *ctx, unsigned int offset_gpr) +{ + for (int i = 2; i != 32; i++) + pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset_gpr + (i * 4), + MIPS32_SW(ctx->isa, i, PRACC_OUT_OFFSET + offset_gpr + (i * 4), 1)); +} + +static void mips32_pracc_store_regs_lohi(struct pracc_queue_info *ctx) +{ + uint32_t lohi_read_code[] = { + MIPS32_MFLO(ctx->isa, 8), /* move lo to $8 */ + MIPS32_MFHI(ctx->isa, 8), /* move hi to $8 */ }; - pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 1, 31, 0)); /* move $1 to COP0 DeSave */ - pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */ + /* store lo & hi */ + for (int i = 0; i < 2; i++) { + /* load COP0 needed registers to $8 */ + pracc_add(ctx, 0, lohi_read_code[i]); + /* store $8 at PARAM OUT */ + pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, + MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1)); + } +} + +/* Saves CP0 registers [status, badvaddr, cause, depc] */ +static void mips32_pracc_store_regs_cp0_context(struct pracc_queue_info *ctx, unsigned int offset_cp0) +{ + uint32_t cp0_read_code[] = { + MIPS32_MFC0(ctx->isa, 8, 12, 0), /* move status to $8 */ + MIPS32_MFC0(ctx->isa, 8, 8, 0), /* move badvaddr to $8 */ + MIPS32_MFC0(ctx->isa, 8, 13, 0), /* move cause to $8 */ + MIPS32_MFC0(ctx->isa, 8, 24, 0), /* move depc (pc) to $8 */ + }; - for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */ - pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4), - MIPS32_SW(ctx.isa, i, PRACC_OUT_OFFSET + (i * 4), 1)); + /* store cp0 */ + for (size_t i = 0; i < ARRAY_SIZE(cp0_read_code); i++) { + size_t offset = offset_cp0 + (i * 4); - for (int i = 0; i != 6; i++) { - pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */ - pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */ - MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1)); + /* load COP0 needed registers to $8 */ + pracc_add(ctx, 0, cp0_read_code[i]); + /* store $8 at PARAM OUT */ + pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset, + MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + offset, 1)); } - pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 31, 0)); /* move DeSave to $8, reg1 value */ - pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */ - MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + 4, 1)); +} - pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */ - pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ - pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */ +/* Loads original content of $1 into $8, + * then store it to the batch data access address. + * Finally it restores $1 from DeSave. + */ +static void mips32_pracc_store_regs_restore(struct pracc_queue_info *ctx) +{ + /* move DeSave to $8, reg1 value */ + pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 8, 31, 0)); + /* store reg1 value from $8 to param out */ + pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + 4, + MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + 4, 1)); + + /* move COP0 DeSave to $1, restore reg1 */ + pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 1, 31, 0)); +} - ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs, 1); +/* This function performs following actions: + * Saves `$1` to `DeSave`, + * then load `PRACC_UPPER_BASE_ADDR` for saving the register data structure into `$1`, + * Saves `$2` ~ `$31` to `PRACC_UPPER_BASE_ADDR + offset_gpr` + * Saves HI and LO, + * Saves necessary cp0 registers. +*/ +static void mips32_pracc_store_regs(struct pracc_queue_info *ctx, + unsigned int offset_gpr, unsigned int offset_cp0) +{ + mips32_pracc_store_regs_set_base_addr(ctx); + mips32_pracc_store_regs_gpr(ctx, offset_gpr); + mips32_pracc_store_regs_lohi(ctx); + mips32_pracc_store_regs_cp0_context(ctx, offset_cp0); + mips32_pracc_store_regs_restore(ctx); +} + +int mips32_pracc_read_regs(struct mips32_common *mips32) +{ + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct pracc_queue_info ctx = {.ejtag_info = ejtag_info}; + struct mips32_core_regs *core_regs = &mips32->core_regs; + unsigned int offset_gpr = ((uint8_t *)&core_regs->gpr[0]) - (uint8_t *)core_regs; + unsigned int offset_cp0 = ((uint8_t *)&core_regs->cp0[0]) - (uint8_t *)core_regs; + unsigned int offset_fpr = ((uint8_t *)&core_regs->fpr[0]) - (uint8_t *)core_regs; + unsigned int offset_fpcr = ((uint8_t *)&core_regs->fpcr[0]) - (uint8_t *)core_regs; + unsigned int offset_dsp = ((uint8_t *)&core_regs->dsp[0]) - (uint8_t *)core_regs; + bool fp_enabled, dsp_enabled; + + /* + * This procedure has to be in 3 distinctive steps, because we can + * only know whether FP and DSP are enabled after reading CP0. + * + * Step 1: Read everything except CP1 and DSP stuff + * Step 2: Read CP1 stuff if FP is implemented + * Step 3: Read DSP registers if dsp is implemented + */ + + pracc_queue_init(&ctx); + + mips32_pracc_store_regs(&ctx, offset_gpr, offset_cp0); + + /* jump to start */ + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); + /* load $15 in DeSave */ + pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1); - ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */ - ejtag_info->reg9 = regs[9]; pracc_queue_free(&ctx); + + /* reg8 is saved but not restored, next called function should restore it */ + ejtag_info->reg8 = mips32->core_regs.gpr[8]; + ejtag_info->reg9 = mips32->core_regs.gpr[9]; + + if (ctx.retval != ERROR_OK) + return ctx.retval; + + /* we only care if FP is actually impl'd and if cp1 is enabled */ + /* since we already read cp0 in the prev step */ + /* now we know what's in cp0.status */ + fp_enabled = (mips32->core_regs.cp0[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0; + if (mips32->fp_imp && fp_enabled) { + pracc_queue_init(&ctx); + + mips32_pracc_store_regs_set_base_addr(&ctx); + + /* FCSR */ + pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 31)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_fpcr, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr, 1)); + + /* FIR */ + pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 0)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_fpcr + 4, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr + 4, 1)); + + /* f0 to f31 */ + if (mips32->fpu_in_64bit) { + for (int i = 0; i != 32; i++) { + size_t offset = offset_fpr + (i * 8); + /* current pracc implementation (or EJTAG itself) only supports 32b access */ + /* so there is no way to use SDC1 */ + + /* lower half */ + pracc_add(&ctx, 0, MIPS32_MFC1(ctx.isa, 8, i)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset, 1)); + + /* upper half */ + pracc_add(&ctx, 0, MIPS32_MFHC1(ctx.isa, 8, i)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset + 4, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset + 4, 1)); + } + } else { + for (int i = 0; i != 32; i++) { + size_t offset = offset_fpr + (i * 8); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset, + MIPS32_SWC1(ctx.isa, i, PRACC_OUT_OFFSET + offset, 1)); + } + } + + mips32_pracc_store_regs_restore(&ctx); + + /* jump to start */ + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); + /* load $15 in DeSave */ + pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1); + + pracc_queue_free(&ctx); + } + + dsp_enabled = (mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0; + if (mips32->dsp_imp && dsp_enabled) { + pracc_queue_init(&ctx); + + mips32_pracc_store_regs_set_base_addr(&ctx); + + /* Struct of mips32_dsp_regs[7]: {ac{hi, lo}1-3, dspctl} */ + size_t dsp_regs = ARRAY_SIZE(mips32->core_regs.dsp); + /* Starts from ac1, core_regs.dsp have dspctl register, therefore - 1 */ + for (size_t index = 0; index != ((dsp_regs - 1) / 2); index++) { + /* Every accumulator have 2 registers, hi&lo, and core_regs.dsp stores ac[1~3] */ + /* Reads offset of hi[ac] from core_regs array */ + size_t offset_hi = offset_dsp + ((index * 2) * sizeof(uint32_t)); + /* Reads offset of lo[ac] from core_regs array */ + size_t offset_lo = offset_dsp + (((index * 2) + 1) * sizeof(uint32_t)); + + /* DSP Ac registers starts from 1 and index starts from 0, therefore ac = index + 1 */ + size_t ac = index + 1; + pracc_add(&ctx, 0, MIPS32_DSP_MFHI(8, ac)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_hi, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_hi, 1)); + pracc_add(&ctx, 0, MIPS32_DSP_MFLO(8, ac)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_lo, + MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_lo, 1)); + } + + /* DSPCTL is the last element of register store */ + pracc_add(&ctx, 0, MIPS32_DSP_RDDSP(8, 0x3F)); + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_dsp + ((dsp_regs - 1) * sizeof(uint32_t)), + MIPS32_SW(ctx.isa, 8, + PRACC_OUT_OFFSET + offset_dsp + ((dsp_regs - 1) * sizeof(uint32_t)), 1)); + + mips32_pracc_store_regs_restore(&ctx); + + /* jump to start */ + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); + /* load $15 in DeSave */ + pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1); + + pracc_queue_free(&ctx); + } return ctx.retval; } +/** + * mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer + * @param[in] ejtag_info: EJTAG information structure + * @param[in] addr: Starting address for cache synchronization + * @param[in] size: Size of each data element + * @param[in] count: Number of data elements + * + * @brief Synchronizes the cache for fast data transfer based on + * the specified address and cache configuration. + * If the region is cacheable (write-back cache or write-through cache), + * it synchronizes the cache for the specified range. + * The synchronization is performed using the MIPS32 cache synchronization function. + * + * @return ERROR_OK on success; error code on failure. + */ +static int mips32_pracc_fastdata_xfer_synchronize_cache(struct mips_ejtag *ejtag_info, + uint32_t addr, int size, int count) +{ + int retval = ERROR_OK; + + if ((KSEGX(addr) == KSEG1) || (addr >= 0xff200000 && addr <= 0xff3fffff)) // DESEG? + return retval; /*Nothing to do*/ + + int cached = 0; + uint32_t conf = 0; + + mips32_cp0_read(ejtag_info, &conf, 16, 0); + + switch (KSEGX(addr)) { + case KUSEG: + cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; + break; + case KSEG0: + cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; + break; + case KSEG2: + case KSEG3: + cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; + break; + default: + /* what ? */ + break; + } + + /** + * Check cacheability bits coherency algorithm + * is the region cacheable or uncached. + * If cacheable we have to synchronize the cache + */ + if (cached == 3 || cached == 0) { /* Write back cache or write through cache */ + uint32_t start_addr = addr; + uint32_t end_addr = addr + count * size; + uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; + /* FIXME: In MIPS Release 6, the encoding of CACHE instr has changed */ + if (rel > MIPS32_RELEASE_2) { + LOG_DEBUG("Unsupported MIPS Release ( > 5)"); + return ERROR_FAIL; + } + retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel); + } + + return retval; +} + /* fastdata upload/download requires an initialized working area * to load the download code; it should not be called otherwise * fetch order from the fastdata area @@ -920,13 +1311,17 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are /* start of fastdata area in t0 */ MIPS32_LUI(isa, 8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)), MIPS32_ORI(isa, 8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)), - MIPS32_LW(isa, 9, 0, 8), /* start addr in t1 */ - MIPS32_LW(isa, 10, 0, 8), /* end addr to t2 */ - /* loop: */ + MIPS32_LW(isa, 9, 0, 8), /* start addr in t1 */ + mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */ + MIPS32_LW(isa, 10, 0, 8), /* end addr to t2 */ + mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */ + /* loop: */ write_t ? MIPS32_LW(isa, 11, 0, 8) : MIPS32_LW(isa, 11, 0, 9), /* from xfer area : from memory */ write_t ? MIPS32_SW(isa, 11, 0, 9) : MIPS32_SW(isa, 11, 0, 8), /* to memory : to xfer area */ - MIPS32_BNE(isa, 10, 9, NEG16(3 << isa)), /* bne $t2,t1,loop */ + mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */ + + MIPS32_BNE(isa, 10, 9, NEG16(4 << isa)), /* bne $t2,t1,loop */ MIPS32_ADDI(isa, 9, 9, 4), /* addi t1,t1,4 */ MIPS32_LW(isa, 8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15), @@ -936,7 +1331,9 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are MIPS32_LUI(isa, 15, UPPER16(MIPS32_PRACC_TEXT)), MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_PRACC_TEXT) | isa), /* isa bit for JR instr */ - MIPS32_JR(isa, 15), /* jr start */ + mips32_cpu_support_hazard_barrier(ejtag_info) + ? MIPS32_JRHB(isa, 15) + : MIPS32_JR(isa, 15), /* jr start */ MIPS32_MFC0(isa, 15, 31, 0), /* move COP0 DeSave to $15 */ }; @@ -956,14 +1353,16 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are uint32_t jmp_code[] = { MIPS32_LUI(isa, 15, UPPER16(source->address)), /* load addr of jump in $15 */ MIPS32_ORI(isa, 15, 15, LOWER16(source->address) | isa), /* isa bit for JR instr */ - MIPS32_JR(isa, 15), /* jump to ram program */ + mips32_cpu_support_hazard_barrier(ejtag_info) + ? MIPS32_JRHB(isa, 15) + : MIPS32_JR(isa, 15), /* jump to ram program */ isa ? MIPS32_XORI(isa, 15, 15, 1) : MIPS32_NOP, /* drop isa bit, needed for LW/SW instructions */ }; pracc_swap16_array(ejtag_info, jmp_code, ARRAY_SIZE(jmp_code)); /* execute jump code, with no address check */ - for (unsigned i = 0; i < ARRAY_SIZE(jmp_code); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(jmp_code); i++) { int retval = wait_for_pracc_rw(ejtag_info); if (retval != ERROR_OK) return retval; @@ -998,7 +1397,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); - unsigned num_clocks = 0; /* like in legacy code */ + unsigned int num_clocks = 0; /* like in legacy code */ if (ejtag_info->mode != 0) num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000; @@ -1020,5 +1419,5 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) LOG_ERROR("mini program did not return to start"); - return retval; + return mips32_pracc_fastdata_xfer_synchronize_cache(ejtag_info, addr, 4, count); } diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index a736e668a4..a0244a695d 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -36,6 +36,8 @@ #define PRACC_BLOCK 128 /* 1 Kbyte */ +struct mips32_common; + struct pa_list { uint32_t instr; uint32_t addr; @@ -43,7 +45,7 @@ struct pa_list { struct pracc_queue_info { struct mips_ejtag *ejtag_info; - unsigned isa; + unsigned int isa; int retval; int code_count; int store_count; @@ -51,9 +53,10 @@ struct pracc_queue_info { struct pa_list *pracc_list; /* Code and store addresses at dmseg */ }; +struct mips32_common; + void pracc_queue_init(struct pracc_queue_info *ctx); void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr); -void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize); void pracc_queue_free(struct pracc_queue_info *ctx); int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf, bool check_last); @@ -65,11 +68,8 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, int write_t, uint32_t addr, int count, uint32_t *buf); -int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs); -int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs); - -int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, - uint32_t *param_out, bool check_last); +int mips32_pracc_read_regs(struct mips32_common *mips32); +int mips32_pracc_write_regs(struct mips32_common *mips32); /** * \b mips32_cp0_read @@ -103,6 +103,21 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); +/** + * mips32_cp1_control_read + * + * @brief Simulates cfc1 ASM instruction (Move Control Word From Floating Point), + * i.e. implements copro C1 Control Register read. + * + * @param[in] ejtag_info + * @param[in] val Storage to hold read value + * @param[in] cp1_c_reg Number of copro C1 control register we want to read + * + * @return ERROR_OK on Success, ERROR_FAIL otherwise + */ +int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, + uint32_t *val, uint32_t cp1_c_reg); + static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count) { if (ejtag_info->isa && ejtag_info->endianness) diff --git a/src/target/mips64.c b/src/target/mips64.c index f9f54c25c0..3d193a3009 100644 --- a/src/target/mips64.c +++ b/src/target/mips64.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Support for processors implementing MIPS64 instruction set @@ -21,7 +21,7 @@ #include "mips64.h" static const struct { - unsigned id; + unsigned int id; const char *name; enum reg_type type; const char *group; @@ -247,8 +247,8 @@ static int mips64_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u64(reg->value, 0, 64, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -265,8 +265,8 @@ static int mips64_read_core_reg(struct target *target, int num) reg_value = mips64->core_regs[num]; buf_set_u64(mips64->core_cache->reg_list[num].value, 0, 64, reg_value); - mips64->core_cache->reg_list[num].valid = 1; - mips64->core_cache->reg_list[num].dirty = 0; + mips64->core_cache->reg_list[num].valid = true; + mips64->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -284,8 +284,8 @@ static int mips64_write_core_reg(struct target *target, int num) reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64); mips64->core_regs[num] = reg_value; LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value); - mips64->core_cache->reg_list[num].valid = 1; - mips64->core_cache->reg_list[num].dirty = 0; + mips64->core_cache->reg_list[num].valid = true; + mips64->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -297,8 +297,8 @@ int mips64_invalidate_core_regs(struct target *target) unsigned int i; for (i = 0; i < mips64->core_cache->num_regs; i++) { - mips64->core_cache->reg_list[i].valid = 0; - mips64->core_cache->reg_list[i].dirty = 0; + mips64->core_cache->reg_list[i].valid = false; + mips64->core_cache->reg_list[i].dirty = false; } return ERROR_OK; @@ -332,8 +332,8 @@ int mips64_save_context(struct target *target) if (retval != ERROR_OK) return retval; - for (unsigned i = 0; i < MIPS64_NUM_REGS; i++) - retval = mips64->read_core_reg(target, i); + for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++) + retval = mips64->read_core_reg(target, i); return retval; } @@ -343,7 +343,7 @@ int mips64_restore_context(struct target *target) struct mips64_common *mips64 = target->arch_info; struct mips_ejtag *ejtag_info = &mips64->ejtag_info; - for (unsigned i = 0; i < MIPS64_NUM_REGS; i++) { + for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++) { if (mips64->core_cache->reg_list[i].dirty) mips64->write_core_reg(target, i); } @@ -379,7 +379,7 @@ int mips64_build_reg_cache(struct target *target) struct reg_cache **cache_p, *cache; struct mips64_core_reg *arch_info = NULL; struct reg *reg_list = NULL; - unsigned i; + unsigned int i; cache = calloc(1, sizeof(*cache)); if (!cache) { @@ -459,7 +459,7 @@ int mips64_init_arch_info(struct target *target, struct mips64_common *mips64, int mips64_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, - target_addr_t exit_point, int timeout_ms, void *arch_info) + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { /* TODO */ return ERROR_OK; diff --git a/src/target/mips64.h b/src/target/mips64.h index 3453e4ed1a..ae0811c547 100644 --- a/src/target/mips64.h +++ b/src/target/mips64.h @@ -19,7 +19,7 @@ #include "register.h" #include "mips64_pracc.h" -#define MIPS64_COMMON_MAGIC 0xB640B640 +#define MIPS64_COMMON_MAGIC 0xB640B640U /* MIPS64 CP0 registers */ #define MIPS64_C0_INDEX 0 @@ -81,7 +81,8 @@ struct mips64_comparator { }; struct mips64_common { - uint32_t common_magic; + unsigned int common_magic; + void *arch_info; struct reg_cache *core_cache; struct mips_ejtag ejtag_info; @@ -212,7 +213,7 @@ int mips64_build_reg_cache(struct target *target); int mips64_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); int mips64_configure_break_unit(struct target *target); int mips64_enable_interrupts(struct target *target, bool enable); int mips64_examine(struct target *target); diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c index ee0d74d212..11783fe972 100644 --- a/src/target/mips64_pracc.c +++ b/src/target/mips64_pracc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Support for processors implementing MIPS64 instruction set @@ -27,13 +27,13 @@ struct mips64_pracc_context { uint64_t *local_iparam; - unsigned num_iparam; + unsigned int num_iparam; uint64_t *local_oparam; - unsigned num_oparam; + unsigned int num_oparam; const uint32_t *code; - unsigned code_len; + unsigned int code_len; uint64_t stack[STACK_DEPTH]; - unsigned stack_offset; + unsigned int stack_offset; struct mips_ejtag *ejtag_info; }; @@ -65,7 +65,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t address) { struct mips_ejtag *ejtag_info = ctx->ejtag_info; - unsigned offset; + unsigned int offset; uint32_t ejtag_ctrl; uint64_t data; int rc; @@ -76,12 +76,12 @@ static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t add offset = (address - MIPS64_PRACC_PARAM_IN) / MIPS64_PRACC_DATA_STEP; if (offset >= MIPS64_PRACC_PARAM_IN_SIZE) { - LOG_ERROR("Error: iparam size exceeds MIPS64_PRACC_PARAM_IN_SIZE"); + LOG_ERROR("iparam size exceeds MIPS64_PRACC_PARAM_IN_SIZE"); return ERROR_JTAG_DEVICE_ERROR; } if (!ctx->local_iparam) { - LOG_ERROR("Error: unexpected reading of input parameter"); + LOG_ERROR("unexpected reading of input parameter"); return ERROR_JTAG_DEVICE_ERROR; } @@ -93,7 +93,7 @@ static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t add offset = (address - MIPS64_PRACC_PARAM_OUT) / MIPS64_PRACC_DATA_STEP; if (!ctx->local_oparam) { - LOG_ERROR("Error: unexpected reading of output parameter"); + LOG_ERROR("unexpected reading of output parameter"); return ERROR_JTAG_DEVICE_ERROR; } @@ -154,7 +154,7 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad { uint32_t ejtag_ctrl; uint64_t data; - unsigned offset; + unsigned int offset; struct mips_ejtag *ejtag_info = ctx->ejtag_info; int rc; @@ -181,7 +181,7 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad && (address < MIPS64_PRACC_PARAM_IN + ctx->num_iparam * MIPS64_PRACC_DATA_STEP)) { offset = (address - MIPS64_PRACC_PARAM_IN) / MIPS64_PRACC_DATA_STEP; if (!ctx->local_iparam) { - LOG_ERROR("Error: unexpected writing of input parameter"); + LOG_ERROR("unexpected writing of input parameter"); return ERROR_JTAG_DEVICE_ERROR; } ctx->local_iparam[offset] = data; @@ -189,14 +189,14 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad && (address < MIPS64_PRACC_PARAM_OUT + ctx->num_oparam * MIPS64_PRACC_DATA_STEP)) { offset = (address - MIPS64_PRACC_PARAM_OUT) / MIPS64_PRACC_DATA_STEP; if (!ctx->local_oparam) { - LOG_ERROR("Error: unexpected writing of output parameter"); + LOG_ERROR("unexpected writing of output parameter"); return ERROR_JTAG_DEVICE_ERROR; } ctx->local_oparam[offset] = data; } else if (address == MIPS64_PRACC_STACK) { /* save data onto our stack */ if (ctx->stack_offset >= STACK_DEPTH) { - LOG_ERROR("Error: PrAcc stack depth exceeded"); + LOG_ERROR("PrAcc stack depth exceeded"); return ERROR_FAIL; } ctx->stack[ctx->stack_offset++] = data; @@ -209,9 +209,9 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad } int mips64_pracc_exec(struct mips_ejtag *ejtag_info, - unsigned code_len, const uint32_t *code, - unsigned num_param_in, uint64_t *param_in, - unsigned num_param_out, uint64_t *param_out) + unsigned int code_len, const uint32_t *code, + unsigned int num_param_in, uint64_t *param_in, + unsigned int num_param_out, uint64_t *param_out) { uint32_t ejtag_ctrl; uint64_t address = 0, address_prev = 0; @@ -219,7 +219,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info, int retval; int pass = 0; bool first_time_call = true; - unsigned i; + unsigned int i; for (i = 0; i < code_len; i++) LOG_DEBUG("%08" PRIx32, code[i]); @@ -354,11 +354,11 @@ static int mips64_pracc_read_u64(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_read_mem64(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned count, uint64_t *buf) + unsigned int count, uint64_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_read_u64(ejtag_info, addr + 8*i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -414,11 +414,11 @@ static int mips64_pracc_read_u32(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned count, uint32_t *buf) + unsigned int count, uint32_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_read_u32(ejtag_info, addr + 4 * i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -474,11 +474,11 @@ static int mips64_pracc_read_u16(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned count, uint16_t *buf) + unsigned int count, uint16_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_read_u16(ejtag_info, addr + 2*i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -534,11 +534,11 @@ static int mips64_pracc_read_u8(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned count, uint8_t *buf) + unsigned int count, uint8_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_read_u8(ejtag_info, addr + i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -547,7 +547,7 @@ static int mips64_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint64_t addr, } int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned size, unsigned count, void *buf) + unsigned int size, unsigned int count, void *buf) { switch (size) { case 1: @@ -612,11 +612,11 @@ static int mips64_pracc_write_u64(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_write_mem64(struct mips_ejtag *ejtag_info, - uint64_t addr, unsigned count, uint64_t *buf) + uint64_t addr, unsigned int count, uint64_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_write_u64(ejtag_info, addr + 8 * i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -674,11 +674,11 @@ static int mips64_pracc_write_u32(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint64_t addr, - unsigned count, uint32_t *buf) + unsigned int count, uint32_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_write_u32(ejtag_info, addr + 4 * i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -734,11 +734,11 @@ static int mips64_pracc_write_u16(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_write_mem16(struct mips_ejtag *ejtag_info, - uint64_t addr, unsigned count, uint16_t *buf) + uint64_t addr, unsigned int count, uint16_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_write_u16(ejtag_info, addr + 2 * i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -795,11 +795,11 @@ static int mips64_pracc_write_u8(struct mips_ejtag *ejtag_info, uint64_t addr, } static int mips64_pracc_write_mem8(struct mips_ejtag *ejtag_info, - uint64_t addr, unsigned count, uint8_t *buf) + uint64_t addr, unsigned int count, uint8_t *buf) { int retval = ERROR_OK; - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { retval = mips64_pracc_write_u8(ejtag_info, addr + i, &buf[i]); if (retval != ERROR_OK) return retval; @@ -808,8 +808,8 @@ static int mips64_pracc_write_mem8(struct mips_ejtag *ejtag_info, } int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, - uint64_t addr, unsigned size, - unsigned count, void *buf) + uint64_t addr, unsigned int size, + unsigned int count, void *buf) { switch (size) { case 1: @@ -1270,7 +1270,7 @@ int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs) int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, bool write_t, uint64_t addr, - unsigned count, uint64_t *buf) + unsigned int count, uint64_t *buf) { uint32_t handler_code[] = { /* caution when editing, table is modified below */ @@ -1321,7 +1321,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, }; int retval; - unsigned i; + unsigned int i; uint32_t ejtag_ctrl, address32; uint64_t address, val; @@ -1385,7 +1385,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, mips64_ejtag_fastdata_scan(ejtag_info, 1, &val); /* like in legacy code */ - unsigned num_clocks = 0; + unsigned int num_clocks = 0; if (ejtag_info->mode != 0) num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000; LOG_DEBUG("num_clocks=%d", num_clocks); diff --git a/src/target/mips64_pracc.h b/src/target/mips64_pracc.h index 65ff6e6ac8..2bdc856b91 100644 --- a/src/target/mips64_pracc.h +++ b/src/target/mips64_pracc.h @@ -29,7 +29,7 @@ #undef LOWER16 #define UPPER16(v) ((uint32_t)((v >> 16) & 0xFFFF)) #define LOWER16(v) ((uint32_t)(v & 0xFFFF)) -#define MIPS64_PRACC_FASTDATA_AREA 0xffffffffFF200000 +#define MIPS64_PRACC_FASTDATA_AREA 0xffffffffFF200000ull #define MIPS64_PRACC_FASTDATA_SIZE 16 #define MIPS64_FASTDATA_HANDLER_SIZE 0x80 @@ -40,20 +40,22 @@ #define MIPS64_PRACC_ADDR_STEP 4 #define MIPS64_PRACC_DATA_STEP 8 -int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf); -int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf); +int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned int size, + unsigned int count, void *buf); +int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned int size, + unsigned int count, void *buf); int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs); int mips64_pracc_write_regs(struct mips_ejtag *ejtag_info, uint64_t *regs); int mips64_pracc_exec(struct mips_ejtag *ejtag_info, - unsigned code_len, const uint32_t *code, - unsigned num_param_in, uint64_t *param_in, - unsigned num_param_out, uint64_t *param_out); + unsigned int code_len, const uint32_t *code, + unsigned int num_param_in, uint64_t *param_in, + unsigned int num_param_out, uint64_t *param_out); int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, bool write_t, uint64_t addr, - unsigned count, uint64_t *buf); + unsigned int count, uint64_t *buf); #endif /* OPENOCD_TARGET_MIPS64_PRACC_H */ diff --git a/src/target/mips_cpu.h b/src/target/mips_cpu.h new file mode 100644 index 0000000000..c3b7b54ba7 --- /dev/null +++ b/src/target/mips_cpu.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef OPENOCD_TARGET_MIPS_CPU_H +#define OPENOCD_TARGET_MIPS_CPU_H + +/* + * NOTE: The proper detection of certain CPUs can become quite complicated. + * Please consult the following Linux kernel code when adding new CPUs: + * arch/mips/include/asm/cpu.h + * arch/mips/kernel/cpu-probe.c + */ + +/* Assigned Company values for bits 23:16 of the PRId register. */ +#define PRID_COMP_MASK 0xff0000 + +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MTI 0x010000 +#define PRID_COMP_BROADCOM 0x020000 +#define PRID_COMP_ALCHEMY 0x030000 +#define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_ALTERA 0x100000 +#define PRID_COMP_INGENIC_E1 0xe10000 + +/* + * Assigned Processor ID (implementation) values for bits 15:8 of the PRId + * register. In order to detect a certain CPU type exactly eventually additional + * registers may need to be examined. + */ +#define PRID_IMP_MASK 0xff00 + +#define PRID_IMP_MAPTIV_UC 0x9D00 +#define PRID_IMP_MAPTIV_UP 0x9E00 +#define PRID_IMP_IAPTIV_CM 0xA000 +#define PRID_IMP_IAPTIV 0xA100 +#define PRID_IMP_M5150 0xA700 + +#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ + +#endif /* OPENOCD_TARGET_MIPS_CPU_H */ diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index a440bc4d4e..2ff4aa926f 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * @@ -47,7 +47,7 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info) return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->idcode); } -static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info) +int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info) { mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE); @@ -259,9 +259,12 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info) { struct pa_list pracc_list = {.instr = MIPS32_DRET(ejtag_info->isa), .addr = 0}; struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0}; + struct mips32_common *mips32 = container_of(ejtag_info, + struct mips32_common, ejtag_info); /* execute our dret instruction */ - ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 0); /* shift out instr, omit last check */ + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, + mips32->cpu_quirks & EJTAG_QUIRK_PAD_DRET); /* pic32mx workaround, false pending at low core clock */ jtag_add_sleep(1000); @@ -329,7 +332,7 @@ static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info) EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : ""); } -static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info) +void ejtag_main_print_imp(struct mips_ejtag *ejtag_info) { LOG_DEBUG("EJTAG main: features:%s%s%s%s%s", EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "", @@ -490,7 +493,7 @@ int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step) MIPS64_NOP, }; const uint32_t *code = enable_step ? code_enable : code_disable; - unsigned code_len = enable_step ? ARRAY_SIZE(code_enable) : + unsigned int code_len = enable_step ? ARRAY_SIZE(code_enable) : ARRAY_SIZE(code_disable); return mips64_pracc_exec(ejtag_info, diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index eb80742d65..30a46903f5 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -123,11 +123,12 @@ /* Debug Control Register DCR */ #define EJTAG_DCR 0xFF300000 -#define EJTAG_DCR_ENM (1 << 29) -#define EJTAG_DCR_DB (1 << 17) -#define EJTAG_DCR_IB (1 << 16) -#define EJTAG_DCR_INTE (1 << 4) -#define EJTAG_DCR_MP (1 << 2) +#define EJTAG_DCR_ENM BIT(29) +#define EJTAG_DCR_FDC BIT(18) +#define EJTAG_DCR_DB BIT(17) +#define EJTAG_DCR_IB BIT(16) +#define EJTAG_DCR_INTE BIT(4) +#define EJTAG_DCR_MP BIT(2) /* breakpoint support */ /* EJTAG_V20_* was tested on Broadcom BCM7401 @@ -185,10 +186,27 @@ #define EJTAG64_V25_IBA0 0xFFFFFFFFFF301100ull #define EJTAG64_V25_IBS 0xFFFFFFFFFF301000ull +static const struct dcr_feature { + int bit; + const char *name; +} dcr_features[] = { + {22, "DAS"}, + {18, "FDC"}, + {17, "DataBrk"}, + {16, "InstBrk"}, + {15, "Inverted Data value"}, + {14, "Data value stored"}, + {10, "Complex Breakpoints"}, + { 9, "PC Sampling"}, +}; + +#define EJTAG_DCR_ENTRIES (ARRAY_SIZE(dcr_features)) + struct mips_ejtag { struct jtag_tap *tap; uint32_t impcode; uint32_t idcode; + uint32_t prid; uint32_t ejtag_ctrl; int fast_access_save; uint32_t config_regs; /* number of config registers read */ @@ -196,7 +214,7 @@ struct mips_ejtag { uint32_t reg8; uint32_t reg9; - unsigned scan_delay; + unsigned int scan_delay; int mode; uint32_t pa_ctrl; uint32_t pa_addr; @@ -243,6 +261,9 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info); int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step); int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step); +void ejtag_main_print_imp(struct mips_ejtag *ejtag_info); +int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info); + static inline void mips_le_to_h_u32(jtag_callback_data_t arg) { uint8_t *in = (uint8_t *)arg; diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 8d13447a09..4e27914a9d 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * @@ -30,12 +30,14 @@ static int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint); static int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); -static int mips_m4k_internal_restore(struct target *target, int current, - target_addr_t address, int handle_breakpoints, - int debug_execution); +static int mips_m4k_internal_restore(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution); static int mips_m4k_halt(struct target *target); static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer); +static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address, + uint32_t count, uint8_t *buffer); static int mips_m4k_examine_debug_reason(struct target *target) { @@ -98,17 +100,19 @@ static int mips_m4k_debug_entry(struct target *target) /* attempt to find halt reason */ mips_m4k_examine_debug_reason(target); + mips32_cpu_probe(target); + mips32_read_config_regs(target); /* default to mips32 isa, it will be changed below if required */ mips32->isa_mode = MIPS32_ISA_MIPS32; /* other than mips32 only and isa bit set ? */ - if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1)) + if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1)) mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32; LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s", - buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32), + buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32), target_state_name(target)); return ERROR_OK; @@ -138,7 +142,7 @@ static int mips_m4k_halt_smp(struct target *target) ret = mips_m4k_halt(curr); if (ret != ERROR_OK) { - LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid); + LOG_TARGET_ERROR(curr, "halt failed."); retval = ret; } } @@ -394,7 +398,8 @@ static int mips_m4k_single_step_core(struct target *target) return ERROR_OK; } -static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints) +static int mips_m4k_restore_smp(struct target *target, uint32_t address, + bool handle_breakpoints) { int retval = ERROR_OK; struct target_list *head; @@ -404,12 +409,12 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han struct target *curr = head->target; if ((curr != target) && (curr->state != TARGET_RUNNING)) { /* resume current address , not in step mode */ - ret = mips_m4k_internal_restore(curr, 1, address, - handle_breakpoints, 0); + ret = mips_m4k_internal_restore(curr, true, address, + handle_breakpoints, false); if (ret != ERROR_OK) { - LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32, - curr->coreid, address); + LOG_TARGET_ERROR(curr, "failed to resume at address: 0x%" PRIx32, + address); retval = ret; } } @@ -417,8 +422,9 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han return retval; } -static int mips_m4k_internal_restore(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int mips_m4k_internal_restore(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution) { struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; @@ -436,21 +442,21 @@ static int mips_m4k_internal_restore(struct target *target, int current, mips_m4k_enable_watchpoints(target); } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { mips_m4k_isa_filter(mips32->isa_imp, &address); - buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); - mips32->core_cache->reg_list[MIPS32_PC].dirty = true; - mips32->core_cache->reg_list[MIPS32_PC].valid = true; + buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address); + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true; } - if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */ - buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode); + if (mips32->isa_imp > 1 && debug_execution) /* if more than one isa supported */ + buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode); if (!current) resume_pc = address; else - resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); + resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32); mips32_restore_context(target); @@ -490,8 +496,8 @@ static int mips_m4k_internal_restore(struct target *target, int current, return ERROR_OK; } -static int mips_m4k_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int mips_m4k_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { int retval = ERROR_OK; @@ -517,8 +523,8 @@ static int mips_m4k_resume(struct target *target, int current, return retval; } -static int mips_m4k_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int mips_m4k_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -530,18 +536,18 @@ static int mips_m4k_step(struct target *target, int current, return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { mips_m4k_isa_filter(mips32->isa_imp, &address); - buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); - mips32->core_cache->reg_list[MIPS32_PC].dirty = true; - mips32->core_cache->reg_list[MIPS32_PC].valid = true; + buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address); + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true; + mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true; } /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { breakpoint = breakpoint_find(target, - buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)); + buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32)); if (breakpoint) mips_m4k_unset_breakpoint(target, breakpoint); } @@ -900,7 +906,7 @@ static int mips_m4k_set_watchpoint(struct target *target, LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } - watchpoint->number = wp_num; + watchpoint_set(watchpoint, wp_num); comparator_list[wp_num].used = 1; comparator_list[wp_num].bp_value = watchpoint->address; @@ -1021,6 +1027,12 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address, if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; + if (size == 4 && count > 32) { + int retval = mips_m4k_bulk_read_memory(target, address, count, buffer); + if (retval == ERROR_OK) + return ERROR_OK; + LOG_WARNING("Falling back to non-bulk read"); + } /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */ void *t = NULL; @@ -1146,7 +1158,7 @@ static int mips_m4k_init_arch_info(struct target *target, return ERROR_OK; } -static int mips_m4k_target_create(struct target *target, Jim_Interp *interp) +static int mips_m4k_target_create(struct target *target) { struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common)); @@ -1218,8 +1230,8 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre fast_data_area = mips32->fast_data_area; - if (address <= fast_data_area->address + fast_data_area->size && - fast_data_area->address <= address + count) { + if (address < (fast_data_area->address + fast_data_area->size) && + fast_data_area->address < (address + count)) { LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area " "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").", fast_data_area->address, address, address + count); @@ -1249,6 +1261,71 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre return retval; } +static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address, + uint32_t count, uint8_t *buffer) +{ + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct working_area *fast_data_area; + int retval; + int write_t = 0; + + LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "", + address, count); + + /* check alignment */ + if (address & 0x3u) + return ERROR_TARGET_UNALIGNED_ACCESS; + + if (!mips32->fast_data_area) { + /* Get memory for block read handler + * we preserve this area between calls and gain a speed increase + * of about 3kb/sec when reading flash + * this will be released/nulled by the system when the target is resumed or reset */ + retval = target_alloc_working_area(target, + MIPS32_FASTDATA_HANDLER_SIZE, + &mips32->fast_data_area); + if (retval != ERROR_OK) { + LOG_ERROR("No working area available"); + return retval; + } + + /* reset fastadata state so the algo get reloaded */ + ejtag_info->fast_access_save = -1; + } + + fast_data_area = mips32->fast_data_area; + + if (address < (fast_data_area->address + fast_data_area->size) && + fast_data_area->address < (address + count)) { + LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within read area " + "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").", + fast_data_area->address, address, address + count); + LOG_ERROR("Change work-area-phys or load_image address!"); + return ERROR_FAIL; + } + + /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */ + /* but byte array represents target endianness */ + uint32_t *t = malloc(count * sizeof(uint32_t)); + if (!t) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address, + count, t); + + target_buffer_set_u32_array(target, buffer, count, t); + + free(t); + + if (retval != ERROR_OK) + LOG_ERROR("Fastdata access Failed"); + + return retval; +} + static int mips_m4k_verify_pointer(struct command_invocation *cmd, struct mips_m4k_common *mips_m4k) { @@ -1322,7 +1399,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) if (CMD_ARGC == 1) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); else if (CMD_ARGC > 1) - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_SYNTAX_ERROR; command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay); if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { @@ -1357,7 +1434,7 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -const struct command_registration mips_m4k_command_handlers[] = { +static const struct command_registration mips_m4k_command_handlers[] = { { .chain = mips32_command_handlers, }, diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h index ae4a0ff722..f63d72f73c 100644 --- a/src/target/mips_m4k.h +++ b/src/target/mips_m4k.h @@ -15,12 +15,14 @@ struct target; -#define MIPSM4K_COMMON_MAGIC 0xB321B321 +#define MIPSM4K_COMMON_MAGIC 0xB321B321U struct mips_m4k_common { - uint32_t common_magic; - bool is_pic32mx; + unsigned int common_magic; + struct mips32_common mips32; + + bool is_pic32mx; }; static inline struct mips_m4k_common * @@ -41,6 +43,5 @@ static inline void mips_m4k_isa_filter(enum mips32_isa_imp isa_imp, target_addr_ } } } -extern const struct command_registration mips_m4k_command_handlers[]; #endif /* OPENOCD_TARGET_MIPS_M4K_H */ diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c index 449f5a217a..a181a154ee 100644 --- a/src/target/mips_mips64.c +++ b/src/target/mips_mips64.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * MIPS64 generic target support @@ -205,12 +205,6 @@ static int mips_mips64_deassert_reset(struct target *target) return ERROR_OK; } -static int mips_mips64_soft_reset_halt(struct target *target) -{ - /* TODO */ - return ERROR_OK; -} - static int mips_mips64_single_step_core(struct target *target) { struct mips64_common *mips64 = target->arch_info; @@ -598,9 +592,9 @@ static int mips_mips64_unset_breakpoint(struct target *target, return ERROR_OK; } -static int mips_mips64_resume(struct target *target, int current, - uint64_t address, int handle_breakpoints, - int debug_execution) +static int mips_mips64_resume(struct target *target, bool current, + uint64_t address, bool handle_breakpoints, + bool debug_execution) { struct mips64_common *mips64 = target->arch_info; struct mips_ejtag *ejtag_info = &mips64->ejtag_info; @@ -612,7 +606,7 @@ static int mips_mips64_resume(struct target *target, int current, address = mips64_extend_sign(address); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted %d", target->state); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -628,11 +622,11 @@ static int mips_mips64_resume(struct target *target, int current, } pc = &mips64->core_cache->reg_list[MIPS64_PC]; - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { buf_set_u64(pc->value, 0, 64, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } resume_pc = buf_get_u64(pc->value, 0, 64); @@ -702,8 +696,8 @@ static int mips_mips64_resume(struct target *target, int current, return ERROR_OK; } -static int mips_mips64_step(struct target *target, int current, - uint64_t address, int handle_breakpoints) +static int mips_mips64_step(struct target *target, bool current, + uint64_t address, bool handle_breakpoints) { struct mips64_common *mips64 = target->arch_info; struct mips_ejtag *ejtag_info = &mips64->ejtag_info; @@ -712,19 +706,19 @@ static int mips_mips64_step(struct target *target, int current, int retval = ERROR_OK; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } if (mips64->mips64mode32) address = mips64_extend_sign(address); - /* current = 1: continue on current pc, otherwise continue at + /* current = true: continue on current pc, otherwise continue at * <address> */ if (!current) { buf_set_u64(pc->value, 0, 64, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } /* the front-end may request us not to handle breakpoints */ @@ -810,7 +804,7 @@ static int mips_mips64_remove_breakpoint(struct target *target, int retval = ERROR_OK; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -871,7 +865,7 @@ static int mips_mips64_remove_watchpoint(struct target *target, int retval = ERROR_OK; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -892,7 +886,7 @@ static int mips_mips64_read_memory(struct target *target, uint64_t address, void *t; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted %d", target->state); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1020,7 +1014,7 @@ static int mips_mips64_write_memory(struct target *target, uint64_t address, int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1088,7 +1082,7 @@ static int mips_mips64_init_target(struct command_context *cmd_ctx, return mips64_build_reg_cache(target); } -static int mips_mips64_target_create(struct target *target, Jim_Interp *interp) +static int mips_mips64_target_create(struct target *target) { struct mips_mips64_common *mips_mips64; struct mips64_common *mips64; @@ -1168,7 +1162,7 @@ struct target_type mips_mips64_target = { .assert_reset = mips_mips64_assert_reset, .deassert_reset = mips_mips64_deassert_reset, - .soft_reset_halt = mips_mips64_soft_reset_halt, + /* TODO: add .soft_reset_halt */ .get_gdb_reg_list = mips64_get_gdb_reg_list, diff --git a/src/target/mips_mips64.h b/src/target/mips_mips64.h index 69fb2a6f98..9841deb2fd 100644 --- a/src/target/mips_mips64.h +++ b/src/target/mips_mips64.h @@ -17,7 +17,8 @@ #include "helper/types.h" struct mips_mips64_common { - int common_magic; + unsigned int common_magic; + struct mips64_common mips64_common; }; diff --git a/src/target/nds32.c b/src/target/nds32.c deleted file mode 100644 index b15a7dd68d..0000000000 --- a/src/target/nds32.c +++ /dev/null @@ -1,2613 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/log.h> -#include <helper/binarybuffer.h> -#include "nds32.h" -#include "nds32_aice.h" -#include "nds32_tlb.h" -#include "nds32_disassembler.h" - -struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM]; -uint32_t nds32_edm_ops_num; - -const char *nds32_debug_type_name[11] = { - "SOFTWARE BREAK", - "SOFTWARE BREAK_16", - "HARDWARE BREAKPOINT", - "DATA ADDR WATCHPOINT PRECISE", - "DATA VALUE WATCHPOINT PRECISE", - "DATA VALUE WATCHPOINT IMPRECISE", - "DEBUG INTERRUPT", - "HARDWARE SINGLE STEP", - "DATA ADDR WATCHPOINT NEXT PRECISE", - "DATA VALUE WATCHPOINT NEXT PRECISE", - "LOAD STORE GLOBAL STOP", -}; - -static const int nds32_lm_size_table[16] = { - 4 * 1024, - 8 * 1024, - 16 * 1024, - 32 * 1024, - 64 * 1024, - 128 * 1024, - 256 * 1024, - 512 * 1024, - 1024 * 1024, - 1 * 1024, - 2 * 1024, -}; - -static const int nds32_line_size_table[6] = { - 0, - 8, - 16, - 32, - 64, - 128, -}; - -static int nds32_get_core_reg(struct reg *reg) -{ - int retval; - struct nds32_reg *reg_arch_info = reg->arch_info; - struct target *target = reg_arch_info->target; - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - - if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (reg->valid) { - uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); - LOG_DEBUG("reading register(cached) %" PRIi32 "(%s), value: 0x%8.8" PRIx32, - reg_arch_info->num, reg->name, val); - return ERROR_OK; - } - - int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num); - - if (reg_arch_info->enable == false) { - buf_set_u32(reg_arch_info->value, 0, 32, NDS32_REGISTER_DISABLE); - retval = ERROR_FAIL; - } else { - uint32_t val = 0; - if ((nds32->fpu_enable == false) - && (nds32_reg_type(mapped_regnum) == NDS32_REG_TYPE_FPU)) { - retval = ERROR_OK; - } else if ((nds32->audio_enable == false) - && (nds32_reg_type(mapped_regnum) == NDS32_REG_TYPE_AUMR)) { - retval = ERROR_OK; - } else { - retval = aice_read_register(aice, mapped_regnum, &val); - } - buf_set_u32(reg_arch_info->value, 0, 32, val); - - LOG_DEBUG("reading register %" PRIi32 "(%s), value: 0x%8.8" PRIx32, - reg_arch_info->num, reg->name, val); - } - - if (retval == ERROR_OK) { - reg->valid = true; - reg->dirty = false; - } - - return retval; -} - -static int nds32_get_core_reg_64(struct reg *reg) -{ - int retval; - struct nds32_reg *reg_arch_info = reg->arch_info; - struct target *target = reg_arch_info->target; - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - - if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (reg->valid) - return ERROR_OK; - - if (reg_arch_info->enable == false) { - buf_set_u64(reg_arch_info->value, 0, 64, NDS32_REGISTER_DISABLE); - retval = ERROR_FAIL; - } else { - uint64_t val = 0; - if ((nds32->fpu_enable == false) - && ((reg_arch_info->num >= FD0) && (reg_arch_info->num <= FD31))) { - retval = ERROR_OK; - } else { - retval = aice_read_reg_64(aice, reg_arch_info->num, &val); - } - buf_set_u64(reg_arch_info->value, 0, 64, val); - } - - if (retval == ERROR_OK) { - reg->valid = true; - reg->dirty = false; - } - - return retval; -} - -static int nds32_update_psw(struct nds32 *nds32) -{ - uint32_t value_ir0; - struct aice_port_s *aice = target_to_aice(nds32->target); - - nds32_get_mapped_reg(nds32, IR0, &value_ir0); - - /* Save data memory endian */ - if ((value_ir0 >> 5) & 0x1) { - nds32->data_endian = TARGET_BIG_ENDIAN; - aice_set_data_endian(aice, AICE_BIG_ENDIAN); - } else { - nds32->data_endian = TARGET_LITTLE_ENDIAN; - aice_set_data_endian(aice, AICE_LITTLE_ENDIAN); - } - - /* Save translation status */ - nds32->memory.address_translation = ((value_ir0 >> 7) & 0x1) ? true : false; - - return ERROR_OK; -} - -static int nds32_update_mmu_info(struct nds32 *nds32) -{ - uint32_t value; - - /* Update MMU control status */ - nds32_get_mapped_reg(nds32, MR0, &value); - nds32->mmu_config.default_min_page_size = value & 0x1; - nds32->mmu_config.multiple_page_size_in_use = (value >> 10) & 0x1; - - return ERROR_OK; -} - -static int nds32_update_cache_info(struct nds32 *nds32) -{ - uint32_t value; - - if (nds32_get_mapped_reg(nds32, MR8, &value) == ERROR_OK) { - if (value & 0x1) - nds32->memory.icache.enable = true; - else - nds32->memory.icache.enable = false; - - if (value & 0x2) - nds32->memory.dcache.enable = true; - else - nds32->memory.dcache.enable = false; - } else { - nds32->memory.icache.enable = false; - nds32->memory.dcache.enable = false; - } - - return ERROR_OK; -} - -static int nds32_update_lm_info(struct nds32 *nds32) -{ - struct nds32_memory *memory = &(nds32->memory); - uint32_t value_mr6; - uint32_t value_mr7; - - nds32_get_mapped_reg(nds32, MR6, &value_mr6); - if (value_mr6 & 0x1) - memory->ilm_enable = true; - else - memory->ilm_enable = false; - - if (memory->ilm_align_ver == 0) { /* 1MB aligned */ - memory->ilm_start = value_mr6 & 0xFFF00000; - memory->ilm_end = memory->ilm_start + memory->ilm_size; - } else if (memory->ilm_align_ver == 1) { /* aligned to local memory size */ - memory->ilm_start = value_mr6 & 0xFFFFFC00; - memory->ilm_end = memory->ilm_start + memory->ilm_size; - } else { - memory->ilm_start = -1; - memory->ilm_end = -1; - } - - nds32_get_mapped_reg(nds32, MR7, &value_mr7); - if (value_mr7 & 0x1) - memory->dlm_enable = true; - else - memory->dlm_enable = false; - - if (memory->dlm_align_ver == 0) { /* 1MB aligned */ - memory->dlm_start = value_mr7 & 0xFFF00000; - memory->dlm_end = memory->dlm_start + memory->dlm_size; - } else if (memory->dlm_align_ver == 1) { /* aligned to local memory size */ - memory->dlm_start = value_mr7 & 0xFFFFFC00; - memory->dlm_end = memory->dlm_start + memory->dlm_size; - } else { - memory->dlm_start = -1; - memory->dlm_end = -1; - } - - return ERROR_OK; -} - -/** - * If fpu/audio is disabled, to access fpu/audio registers will cause - * exceptions. So, we need to check if fpu/audio is enabled or not as - * target is halted. If fpu/audio is disabled, as users access fpu/audio - * registers, OpenOCD will return fake value 0 instead of accessing - * registers through DIM. - */ -static int nds32_check_extension(struct nds32 *nds32) -{ - uint32_t value; - - nds32_get_mapped_reg(nds32, FUCPR, &value); - if (value == NDS32_REGISTER_DISABLE) { - nds32->fpu_enable = false; - nds32->audio_enable = false; - return ERROR_OK; - } - - if (value & 0x1) - nds32->fpu_enable = true; - else - nds32->fpu_enable = false; - - if (value & 0x80000000) - nds32->audio_enable = true; - else - nds32->audio_enable = false; - - return ERROR_OK; -} - -static int nds32_set_core_reg(struct reg *reg, uint8_t *buf) -{ - struct nds32_reg *reg_arch_info = reg->arch_info; - struct target *target = reg_arch_info->target; - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - uint32_t value = buf_get_u32(buf, 0, 32); - - if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num); - - /* ignore values that will generate exception */ - if (nds32_reg_exception(mapped_regnum, value)) - return ERROR_OK; - - LOG_DEBUG("writing register %" PRIi32 "(%s) with value 0x%8.8" PRIx32, - reg_arch_info->num, reg->name, value); - - if ((nds32->fpu_enable == false) && - (nds32_reg_type(mapped_regnum) == NDS32_REG_TYPE_FPU)) { - - buf_set_u32(reg->value, 0, 32, 0); - } else if ((nds32->audio_enable == false) && - (nds32_reg_type(mapped_regnum) == NDS32_REG_TYPE_AUMR)) { - - buf_set_u32(reg->value, 0, 32, 0); - } else { - buf_set_u32(reg->value, 0, 32, value); - uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); - aice_write_register(aice, mapped_regnum, val); - - /* After set value to registers, read the value from target - * to avoid W1C inconsistency. */ - aice_read_register(aice, mapped_regnum, &val); - buf_set_u32(reg_arch_info->value, 0, 32, val); - } - - reg->valid = true; - reg->dirty = false; - - /* update registers to take effect right now */ - if (mapped_regnum == IR0) { - nds32_update_psw(nds32); - } else if (mapped_regnum == MR0) { - nds32_update_mmu_info(nds32); - } else if ((mapped_regnum == MR6) || (mapped_regnum == MR7)) { - /* update lm information */ - nds32_update_lm_info(nds32); - } else if (mapped_regnum == MR8) { - nds32_update_cache_info(nds32); - } else if (mapped_regnum == FUCPR) { - /* update audio/fpu setting */ - nds32_check_extension(nds32); - } - - return ERROR_OK; -} - -static int nds32_set_core_reg_64(struct reg *reg, uint8_t *buf) -{ - struct nds32_reg *reg_arch_info = reg->arch_info; - struct target *target = reg_arch_info->target; - struct nds32 *nds32 = target_to_nds32(target); - uint32_t low_part = buf_get_u32(buf, 0, 32); - uint32_t high_part = buf_get_u32(buf, 32, 32); - - if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if ((nds32->fpu_enable == false) && - ((reg_arch_info->num >= FD0) && (reg_arch_info->num <= FD31))) { - - buf_set_u32(reg->value, 0, 32, 0); - buf_set_u32(reg->value, 32, 32, 0); - - reg->valid = true; - reg->dirty = false; - } else { - buf_set_u32(reg->value, 0, 32, low_part); - buf_set_u32(reg->value, 32, 32, high_part); - - reg->valid = true; - reg->dirty = true; - } - - return ERROR_OK; -} - -static const struct reg_arch_type nds32_reg_access_type = { - .get = nds32_get_core_reg, - .set = nds32_set_core_reg, -}; - -static const struct reg_arch_type nds32_reg_access_type_64 = { - .get = nds32_get_core_reg_64, - .set = nds32_set_core_reg_64, -}; - -static struct reg_cache *nds32_build_reg_cache(struct target *target, - struct nds32 *nds32) -{ - struct reg_cache *cache = calloc(sizeof(struct reg_cache), 1); - struct reg *reg_list = calloc(TOTAL_REG_NUM, sizeof(struct reg)); - struct nds32_reg *reg_arch_info = calloc(TOTAL_REG_NUM, sizeof(struct nds32_reg)); - int i; - - if (!cache || !reg_list || !reg_arch_info) { - free(cache); - free(reg_list); - free(reg_arch_info); - return NULL; - } - - cache->name = "Andes registers"; - cache->next = NULL; - cache->reg_list = reg_list; - cache->num_regs = 0; - - for (i = 0; i < TOTAL_REG_NUM; i++) { - reg_arch_info[i].num = i; - reg_arch_info[i].target = target; - reg_arch_info[i].nds32 = nds32; - reg_arch_info[i].enable = false; - - reg_list[i].name = nds32_reg_simple_name(i); - reg_list[i].number = reg_arch_info[i].num; - reg_list[i].size = nds32_reg_size(i); - reg_list[i].arch_info = ®_arch_info[i]; - - reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1); - - if (reg_arch_info[i].num >= FD0 && reg_arch_info[i].num <= FD31) { - reg_list[i].value = reg_arch_info[i].value; - reg_list[i].type = &nds32_reg_access_type_64; - - reg_list[i].reg_data_type->type = REG_TYPE_IEEE_DOUBLE; - reg_list[i].reg_data_type->id = "ieee_double"; - reg_list[i].group = "float"; - } else { - reg_list[i].value = reg_arch_info[i].value; - reg_list[i].type = &nds32_reg_access_type; - reg_list[i].group = "general"; - - if ((reg_arch_info[i].num >= FS0) && (reg_arch_info[i].num <= FS31)) { - reg_list[i].reg_data_type->type = REG_TYPE_IEEE_SINGLE; - reg_list[i].reg_data_type->id = "ieee_single"; - reg_list[i].group = "float"; - } else if ((reg_arch_info[i].num == FPCSR) || - (reg_arch_info[i].num == FPCFG)) { - reg_list[i].group = "float"; - } else if ((reg_arch_info[i].num == R28) || - (reg_arch_info[i].num == R29) || - (reg_arch_info[i].num == R31)) { - reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR; - reg_list[i].reg_data_type->id = "data_ptr"; - } else if ((reg_arch_info[i].num == R30) || - (reg_arch_info[i].num == PC)) { - reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR; - reg_list[i].reg_data_type->id = "code_ptr"; - } else { - reg_list[i].reg_data_type->type = REG_TYPE_UINT32; - reg_list[i].reg_data_type->id = "uint32"; - } - } - - if (reg_arch_info[i].num >= R16 && reg_arch_info[i].num <= R25) - reg_list[i].caller_save = true; - else - reg_list[i].caller_save = false; - - reg_list[i].feature = malloc(sizeof(struct reg_feature)); - - if (reg_arch_info[i].num >= R0 && reg_arch_info[i].num <= IFC_LP) - reg_list[i].feature->name = "org.gnu.gdb.nds32.core"; - else if (reg_arch_info[i].num >= CR0 && reg_arch_info[i].num <= SECUR0) - reg_list[i].feature->name = "org.gnu.gdb.nds32.system"; - else if (reg_arch_info[i].num >= D0L24 && reg_arch_info[i].num <= CBE3) - reg_list[i].feature->name = "org.gnu.gdb.nds32.audio"; - else if (reg_arch_info[i].num >= FPCSR && reg_arch_info[i].num <= FD31) - reg_list[i].feature->name = "org.gnu.gdb.nds32.fpu"; - - cache->num_regs++; - } - - nds32->core_cache = cache; - - return cache; -} - -static int nds32_reg_cache_init(struct target *target, struct nds32 *nds32) -{ - struct reg_cache *cache; - - cache = nds32_build_reg_cache(target, nds32); - if (!cache) - return ERROR_FAIL; - - *register_get_last_cache_p(&target->reg_cache) = cache; - - return ERROR_OK; -} - -static struct reg *nds32_reg_current(struct nds32 *nds32, unsigned regnum) -{ - struct reg *r; - - r = nds32->core_cache->reg_list + regnum; - - return r; -} - -int nds32_full_context(struct nds32 *nds32) -{ - uint32_t value, value_ir0; - - /* save $pc & $psw */ - nds32_get_mapped_reg(nds32, PC, &value); - nds32_get_mapped_reg(nds32, IR0, &value_ir0); - - nds32_update_psw(nds32); - nds32_update_mmu_info(nds32); - nds32_update_cache_info(nds32); - nds32_update_lm_info(nds32); - - nds32_check_extension(nds32); - - return ERROR_OK; -} - -/* get register value internally */ -int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value) -{ - struct reg_cache *reg_cache = nds32->core_cache; - struct reg *r; - - if (regnum > reg_cache->num_regs) - return ERROR_FAIL; - - r = nds32_reg_current(nds32, regnum); - - if (r->type->get(r) != ERROR_OK) - return ERROR_FAIL; - - *value = buf_get_u32(r->value, 0, 32); - - return ERROR_OK; -} - -/** set register internally */ -int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value) -{ - struct reg_cache *reg_cache = nds32->core_cache; - struct reg *r; - uint8_t set_value[4]; - - if (regnum > reg_cache->num_regs) - return ERROR_FAIL; - - r = nds32_reg_current(nds32, regnum); - - buf_set_u32(set_value, 0, 32, value); - - return r->type->set(r, set_value); -} - -/** get general register list */ -static int nds32_get_general_reg_list(struct nds32 *nds32, - struct reg **reg_list[], int *reg_list_size) -{ - struct reg *reg_current; - int i; - int current_idx; - - /** freed in gdb_server.c */ - *reg_list = malloc(sizeof(struct reg *) * (IFC_LP - R0 + 1)); - current_idx = 0; - - for (i = R0; i < IFC_LP + 1; i++) { - reg_current = nds32_reg_current(nds32, i); - if (((struct nds32_reg *)reg_current->arch_info)->enable) { - (*reg_list)[current_idx] = reg_current; - current_idx++; - } - } - *reg_list_size = current_idx; - - return ERROR_OK; -} - -/** get all register list */ -static int nds32_get_all_reg_list(struct nds32 *nds32, - struct reg **reg_list[], int *reg_list_size) -{ - struct reg_cache *reg_cache = nds32->core_cache; - struct reg *reg_current; - unsigned int i; - - *reg_list_size = reg_cache->num_regs; - - /** freed in gdb_server.c */ - *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); - - for (i = 0; i < reg_cache->num_regs; i++) { - reg_current = nds32_reg_current(nds32, i); - reg_current->exist = ((struct nds32_reg *) - reg_current->arch_info)->enable; - (*reg_list)[i] = reg_current; - } - - return ERROR_OK; -} - -/** get all register list */ -int nds32_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size, - enum target_register_class reg_class) -{ - struct nds32 *nds32 = target_to_nds32(target); - - switch (reg_class) { - case REG_CLASS_ALL: - return nds32_get_all_reg_list(nds32, reg_list, reg_list_size); - case REG_CLASS_GENERAL: - return nds32_get_general_reg_list(nds32, reg_list, reg_list_size); - default: - return ERROR_FAIL; - } - - return ERROR_FAIL; -} - -static int nds32_select_memory_mode(struct target *target, uint32_t address, - uint32_t length, uint32_t *end_address) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_memory *memory = &(nds32->memory); - struct nds32_edm *edm = &(nds32->edm); - uint32_t dlm_start, dlm_end; - uint32_t ilm_start, ilm_end; - uint32_t address_end = address + length; - - /* init end_address */ - *end_address = address_end; - - if (memory->access_channel == NDS_MEMORY_ACC_CPU) - return ERROR_OK; - - if (edm->access_control == false) { - LOG_DEBUG("EDM does not support ACC_CTL"); - return ERROR_OK; - } - - if (edm->direct_access_local_memory == false) { - LOG_DEBUG("EDM does not support DALM"); - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - return ERROR_OK; - } - - if (memory->mode != NDS_MEMORY_SELECT_AUTO) { - LOG_DEBUG("Memory mode is not AUTO"); - return ERROR_OK; - } - - /* set default mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - - if ((memory->ilm_base != 0) && (memory->ilm_enable == true)) { - ilm_start = memory->ilm_start; - ilm_end = memory->ilm_end; - - /* case 1, address < ilm_start */ - if (address < ilm_start) { - if (ilm_start < address_end) { - /* update end_address to split non-ILM from ILM */ - *end_address = ilm_start; - } - /* MEM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - } else if ((ilm_start <= address) && (address < ilm_end)) { - /* case 2, ilm_start <= address < ilm_end */ - if (ilm_end < address_end) { - /* update end_address to split non-ILM from ILM */ - *end_address = ilm_end; - } - /* ILM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_ILM); - } else { /* case 3, ilm_end <= address */ - /* MEM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - } - - return ERROR_OK; - } else { - LOG_DEBUG("ILM is not enabled"); - } - - if ((memory->dlm_base != 0) && (memory->dlm_enable == true)) { - dlm_start = memory->dlm_start; - dlm_end = memory->dlm_end; - - /* case 1, address < dlm_start */ - if (address < dlm_start) { - if (dlm_start < address_end) { - /* update end_address to split non-DLM from DLM */ - *end_address = dlm_start; - } - /* MEM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - } else if ((dlm_start <= address) && (address < dlm_end)) { - /* case 2, dlm_start <= address < dlm_end */ - if (dlm_end < address_end) { - /* update end_address to split non-DLM from DLM */ - *end_address = dlm_end; - } - /* DLM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_DLM); - } else { /* case 3, dlm_end <= address */ - /* MEM mode */ - aice_memory_mode(aice, NDS_MEMORY_SELECT_MEM); - } - - return ERROR_OK; - } else { - LOG_DEBUG("DLM is not enabled"); - } - - return ERROR_OK; -} - -int nds32_read_buffer(struct target *target, uint32_t address, - uint32_t size, uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - LOG_DEBUG("READ BUFFER: ADDR %08" PRIx32 " SIZE %08" PRIx32, - address, - size); - - int retval = ERROR_OK; - struct aice_port_s *aice = target_to_aice(target); - uint32_t end_address; - - if (((address % 2) == 0) && (size == 2)) { - nds32_select_memory_mode(target, address, 2, &end_address); - return aice_read_mem_unit(aice, address, 2, 1, buffer); - } - - /* handle unaligned head bytes */ - if (address % 4) { - uint32_t unaligned = 4 - (address % 4); - - if (unaligned > size) - unaligned = size; - - nds32_select_memory_mode(target, address, unaligned, &end_address); - retval = aice_read_mem_unit(aice, address, 1, unaligned, buffer); - if (retval != ERROR_OK) - return retval; - - buffer += unaligned; - address += unaligned; - size -= unaligned; - } - - /* handle aligned words */ - if (size >= 4) { - int aligned = size - (size % 4); - int read_len; - - do { - nds32_select_memory_mode(target, address, aligned, &end_address); - - read_len = end_address - address; - - if (read_len > 8) - retval = aice_read_mem_bulk(aice, address, read_len, buffer); - else - retval = aice_read_mem_unit(aice, address, 4, read_len / 4, buffer); - - if (retval != ERROR_OK) - return retval; - - buffer += read_len; - address += read_len; - size -= read_len; - aligned -= read_len; - - } while (aligned != 0); - } - - /*prevent byte access when possible (avoid AHB access limitations in some cases)*/ - if (size >= 2) { - int aligned = size - (size % 2); - nds32_select_memory_mode(target, address, aligned, &end_address); - retval = aice_read_mem_unit(aice, address, 2, aligned / 2, buffer); - if (retval != ERROR_OK) - return retval; - - buffer += aligned; - address += aligned; - size -= aligned; - } - /* handle tail writes of less than 4 bytes */ - if (size > 0) { - nds32_select_memory_mode(target, address, size, &end_address); - retval = aice_read_mem_unit(aice, address, 1, size, buffer); - if (retval != ERROR_OK) - return retval; - } - - return ERROR_OK; -} - -int nds32_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) -{ - struct aice_port_s *aice = target_to_aice(target); - - return aice_read_mem_unit(aice, address, size, count, buffer); -} - -int nds32_read_phys_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, uint8_t *buffer) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - enum nds_memory_access orig_channel; - int result; - - /* switch to BUS access mode to skip MMU */ - orig_channel = memory->access_channel; - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, memory->access_channel); - - /* The input address is physical address. No need to do address translation. */ - result = aice_read_mem_unit(aice, address, size, count, buffer); - - /* restore to origin access mode */ - memory->access_channel = orig_channel; - aice_memory_access(aice, memory->access_channel); - - return result; -} - -int nds32_write_buffer(struct target *target, uint32_t address, - uint32_t size, const uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - LOG_DEBUG("WRITE BUFFER: ADDR %08" PRIx32 " SIZE %08" PRIx32, - address, - size); - - struct aice_port_s *aice = target_to_aice(target); - int retval = ERROR_OK; - uint32_t end_address; - - if (((address % 2) == 0) && (size == 2)) { - nds32_select_memory_mode(target, address, 2, &end_address); - return aice_write_mem_unit(aice, address, 2, 1, buffer); - } - - /* handle unaligned head bytes */ - if (address % 4) { - uint32_t unaligned = 4 - (address % 4); - - if (unaligned > size) - unaligned = size; - - nds32_select_memory_mode(target, address, unaligned, &end_address); - retval = aice_write_mem_unit(aice, address, 1, unaligned, buffer); - if (retval != ERROR_OK) - return retval; - - buffer += unaligned; - address += unaligned; - size -= unaligned; - } - - /* handle aligned words */ - if (size >= 4) { - int aligned = size - (size % 4); - int write_len; - - do { - nds32_select_memory_mode(target, address, aligned, &end_address); - - write_len = end_address - address; - if (write_len > 8) - retval = aice_write_mem_bulk(aice, address, write_len, buffer); - else - retval = aice_write_mem_unit(aice, address, 4, write_len / 4, buffer); - if (retval != ERROR_OK) - return retval; - - buffer += write_len; - address += write_len; - size -= write_len; - aligned -= write_len; - - } while (aligned != 0); - } - - /* handle tail writes of less than 4 bytes */ - if (size > 0) { - nds32_select_memory_mode(target, address, size, &end_address); - retval = aice_write_mem_unit(aice, address, 1, size, buffer); - if (retval != ERROR_OK) - return retval; - } - - return retval; -} - -int nds32_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) -{ - struct aice_port_s *aice = target_to_aice(target); - - return aice_write_mem_unit(aice, address, size, count, buffer); -} - -int nds32_write_phys_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - enum nds_memory_access orig_channel; - int result; - - /* switch to BUS access mode to skip MMU */ - orig_channel = memory->access_channel; - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, memory->access_channel); - - /* The input address is physical address. No need to do address translation. */ - result = aice_write_mem_unit(aice, address, size, count, buffer); - - /* restore to origin access mode */ - memory->access_channel = orig_channel; - aice_memory_access(aice, memory->access_channel); - - return result; -} - -int nds32_mmu(struct target *target, int *enabled) -{ - if (target->state != TARGET_HALTED) { - LOG_ERROR("%s: target not halted", __func__); - return ERROR_TARGET_INVALID; - } - - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - struct nds32_mmu_config *mmu_config = &(nds32->mmu_config); - - if ((mmu_config->memory_protection == 2) && (memory->address_translation == true)) - *enabled = 1; - else - *enabled = 0; - - return ERROR_OK; -} - -int nds32_arch_state(struct target *target) -{ - struct nds32 *nds32 = target_to_nds32(target); - - if (nds32->common_magic != NDS32_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-Andes target"); - return ERROR_FAIL; - } - - uint32_t value_pc, value_psw; - - nds32_get_mapped_reg(nds32, PC, &value_pc); - nds32_get_mapped_reg(nds32, IR0, &value_psw); - - LOG_USER("target halted due to %s\n" - "psw: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", - debug_reason_name(target), - value_psw, - value_pc, - nds32->virtual_hosting ? ", virtual hosting" : ""); - - /* save pc value to pseudo register pc */ - struct reg *reg = register_get_by_name(target->reg_cache, "pc", true); - buf_set_u32(reg->value, 0, 32, value_pc); - - return ERROR_OK; -} - -static void nds32_init_must_have_registers(struct nds32 *nds32) -{ - struct reg_cache *reg_cache = nds32->core_cache; - - /** MUST have general registers */ - ((struct nds32_reg *)reg_cache->reg_list[R0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R4].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R5].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R7].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R8].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R9].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R10].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R15].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R28].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R29].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R30].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R31].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[PC].arch_info)->enable = true; - - /** MUST have configuration system registers */ - ((struct nds32_reg *)reg_cache->reg_list[CR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CR1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CR2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CR3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CR4].arch_info)->enable = true; - - /** MUST have interrupt system registers */ - ((struct nds32_reg *)reg_cache->reg_list[IR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR4].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR9].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR11].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR14].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR15].arch_info)->enable = true; - - /** MUST have MMU system registers */ - ((struct nds32_reg *)reg_cache->reg_list[MR0].arch_info)->enable = true; - - /** MUST have EDM system registers */ - ((struct nds32_reg *)reg_cache->reg_list[DR40].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DR42].arch_info)->enable = true; -} - -static int nds32_init_memory_config(struct nds32 *nds32) -{ - uint32_t value_cr1; /* ICM_CFG */ - uint32_t value_cr2; /* DCM_CFG */ - struct nds32_memory *memory = &(nds32->memory); - - /* read $cr1 to init instruction memory information */ - nds32_get_mapped_reg(nds32, CR1, &value_cr1); - memory->icache.set = value_cr1 & 0x7; - memory->icache.way = (value_cr1 >> 3) & 0x7; - memory->icache.line_size = (value_cr1 >> 6) & 0x7; - memory->icache.lock_support = (value_cr1 >> 9) & 0x1; - - memory->ilm_base = (value_cr1 >> 10) & 0x7; - memory->ilm_align_ver = (value_cr1 >> 13) & 0x3; - - /* read $cr2 to init data memory information */ - nds32_get_mapped_reg(nds32, CR2, &value_cr2); - memory->dcache.set = value_cr2 & 0x7; - memory->dcache.way = (value_cr2 >> 3) & 0x7; - memory->dcache.line_size = (value_cr2 >> 6) & 0x7; - memory->dcache.lock_support = (value_cr2 >> 9) & 0x1; - - memory->dlm_base = (value_cr2 >> 10) & 0x7; - memory->dlm_align_ver = (value_cr2 >> 13) & 0x3; - - return ERROR_OK; -} - -static void nds32_init_config(struct nds32 *nds32) -{ - uint32_t value_cr0; - uint32_t value_cr3; - uint32_t value_cr4; - struct nds32_cpu_version *cpu_version = &(nds32->cpu_version); - struct nds32_mmu_config *mmu_config = &(nds32->mmu_config); - struct nds32_misc_config *misc_config = &(nds32->misc_config); - - nds32_get_mapped_reg(nds32, CR0, &value_cr0); - nds32_get_mapped_reg(nds32, CR3, &value_cr3); - nds32_get_mapped_reg(nds32, CR4, &value_cr4); - - /* config cpu version */ - cpu_version->performance_extension = value_cr0 & 0x1; - cpu_version->_16bit_extension = (value_cr0 >> 1) & 0x1; - cpu_version->performance_extension_2 = (value_cr0 >> 2) & 0x1; - cpu_version->cop_fpu_extension = (value_cr0 >> 3) & 0x1; - cpu_version->string_extension = (value_cr0 >> 4) & 0x1; - cpu_version->revision = (value_cr0 >> 16) & 0xFF; - cpu_version->cpu_id_family = (value_cr0 >> 24) & 0xF; - cpu_version->cpu_id_version = (value_cr0 >> 28) & 0xF; - - /* config MMU */ - mmu_config->memory_protection = value_cr3 & 0x3; - mmu_config->memory_protection_version = (value_cr3 >> 2) & 0x1F; - mmu_config->fully_associative_tlb = (value_cr3 >> 7) & 0x1; - if (mmu_config->fully_associative_tlb) { - mmu_config->tlb_size = (value_cr3 >> 8) & 0x7F; - } else { - mmu_config->tlb_ways = (value_cr3 >> 8) & 0x7; - mmu_config->tlb_sets = (value_cr3 >> 11) & 0x7; - } - mmu_config->_8k_page_support = (value_cr3 >> 15) & 0x1; - mmu_config->extra_page_size_support = (value_cr3 >> 16) & 0xFF; - mmu_config->tlb_lock = (value_cr3 >> 24) & 0x1; - mmu_config->hardware_page_table_walker = (value_cr3 >> 25) & 0x1; - mmu_config->default_endian = (value_cr3 >> 26) & 0x1; - mmu_config->partition_num = (value_cr3 >> 27) & 0x1; - mmu_config->invisible_tlb = (value_cr3 >> 28) & 0x1; - mmu_config->vlpt = (value_cr3 >> 29) & 0x1; - mmu_config->ntme = (value_cr3 >> 30) & 0x1; - mmu_config->drde = (value_cr3 >> 31) & 0x1; - - /* config misc */ - misc_config->edm = value_cr4 & 0x1; - misc_config->local_memory_dma = (value_cr4 >> 1) & 0x1; - misc_config->performance_monitor = (value_cr4 >> 2) & 0x1; - misc_config->high_speed_memory_port = (value_cr4 >> 3) & 0x1; - misc_config->debug_tracer = (value_cr4 >> 4) & 0x1; - misc_config->div_instruction = (value_cr4 >> 5) & 0x1; - misc_config->mac_instruction = (value_cr4 >> 6) & 0x1; - misc_config->audio_isa = (value_cr4 >> 7) & 0x3; - misc_config->l2_cache = (value_cr4 >> 9) & 0x1; - misc_config->reduce_register = (value_cr4 >> 10) & 0x1; - misc_config->addr_24 = (value_cr4 >> 11) & 0x1; - misc_config->interruption_level = (value_cr4 >> 12) & 0x1; - misc_config->baseline_instruction = (value_cr4 >> 13) & 0x7; - misc_config->no_dx_register = (value_cr4 >> 16) & 0x1; - misc_config->implement_dependant_register = (value_cr4 >> 17) & 0x1; - misc_config->implement_dependant_sr_encoding = (value_cr4 >> 18) & 0x1; - misc_config->ifc = (value_cr4 >> 19) & 0x1; - misc_config->mcu = (value_cr4 >> 20) & 0x1; - misc_config->shadow = (value_cr4 >> 21) & 0x7; - misc_config->ex9 = (value_cr4 >> 24) & 0x1; - - nds32_init_memory_config(nds32); -} - -static int nds32_init_option_registers(struct nds32 *nds32) -{ - struct reg_cache *reg_cache = nds32->core_cache; - struct nds32_cpu_version *cpu_version = &(nds32->cpu_version); - struct nds32_mmu_config *mmu_config = &(nds32->mmu_config); - struct nds32_misc_config *misc_config = &(nds32->misc_config); - struct nds32_memory *memory_config = &(nds32->memory); - - bool no_cr5; - bool mr10_exist; - bool no_racr0; - - if (((cpu_version->cpu_id_family == 0xC) || (cpu_version->cpu_id_family == 0xD)) && - ((cpu_version->revision & 0xFC) == 0)) { - no_cr5 = true; - mr10_exist = true; - no_racr0 = true; - } else { - no_cr5 = false; - mr10_exist = false; - no_racr0 = false; - } - - if (misc_config->reduce_register == false) { - ((struct nds32_reg *)reg_cache->reg_list[R11].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R12].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R13].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R14].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R16].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R17].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R18].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R19].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R20].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R21].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R22].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R23].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R24].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R25].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R26].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[R27].arch_info)->enable = true; - } - - if (misc_config->no_dx_register == false) { - ((struct nds32_reg *)reg_cache->reg_list[D0LO].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[D0HI].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[D1LO].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[D1HI].arch_info)->enable = true; - } - - if (misc_config->ex9) - ((struct nds32_reg *)reg_cache->reg_list[ITB].arch_info)->enable = true; - - if (no_cr5 == false) - ((struct nds32_reg *)reg_cache->reg_list[CR5].arch_info)->enable = true; - - if (cpu_version->cop_fpu_extension) { - ((struct nds32_reg *)reg_cache->reg_list[CR6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[FPCSR].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[FPCFG].arch_info)->enable = true; - } - - if (mmu_config->memory_protection == 1) { - /* Secure MPU has no IPC, IPSW, P_ITYPE */ - ((struct nds32_reg *)reg_cache->reg_list[IR1].arch_info)->enable = false; - ((struct nds32_reg *)reg_cache->reg_list[IR9].arch_info)->enable = false; - } - - if (nds32->privilege_level != 0) - ((struct nds32_reg *)reg_cache->reg_list[IR3].arch_info)->enable = false; - - if (misc_config->mcu == true) - ((struct nds32_reg *)reg_cache->reg_list[IR4].arch_info)->enable = false; - - if (misc_config->interruption_level == false) { - ((struct nds32_reg *)reg_cache->reg_list[IR2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR5].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR10].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR12].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR13].arch_info)->enable = true; - - /* Secure MPU has no IPC, IPSW, P_ITYPE */ - if (mmu_config->memory_protection != 1) - ((struct nds32_reg *)reg_cache->reg_list[IR7].arch_info)->enable = true; - } - - if ((cpu_version->cpu_id_family == 0x9) || - (cpu_version->cpu_id_family == 0xA) || - (cpu_version->cpu_id_family == 0xC) || - (cpu_version->cpu_id_family == 0xD)) - ((struct nds32_reg *)reg_cache->reg_list[IR8].arch_info)->enable = true; - - if (misc_config->shadow == 1) { - ((struct nds32_reg *)reg_cache->reg_list[IR16].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR17].arch_info)->enable = true; - } - - if (misc_config->ifc) - ((struct nds32_reg *)reg_cache->reg_list[IFC_LP].arch_info)->enable = true; - - if (nds32->privilege_level != 0) - ((struct nds32_reg *)reg_cache->reg_list[MR0].arch_info)->enable = false; - - if (mmu_config->memory_protection == 1) { - if (mmu_config->memory_protection_version == 24) - ((struct nds32_reg *)reg_cache->reg_list[MR4].arch_info)->enable = true; - - if (nds32->privilege_level == 0) { - if ((mmu_config->memory_protection_version == 16) || - (mmu_config->memory_protection_version == 24)) { - ((struct nds32_reg *)reg_cache->reg_list[MR11].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[SECUR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR20].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR22].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR24].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR30].arch_info)->enable = true; - - if (misc_config->shadow == 1) { - ((struct nds32_reg *)reg_cache->reg_list[IR21].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR23].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR25].arch_info)->enable = true; - } - } - } - } else if (mmu_config->memory_protection == 2) { - ((struct nds32_reg *)reg_cache->reg_list[MR1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[MR4].arch_info)->enable = true; - - if ((cpu_version->cpu_id_family != 0xA) && (cpu_version->cpu_id_family != 0xC) && - (cpu_version->cpu_id_family != 0xD)) - ((struct nds32_reg *)reg_cache->reg_list[MR5].arch_info)->enable = true; - } - - if (mmu_config->memory_protection > 0) { - ((struct nds32_reg *)reg_cache->reg_list[MR2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[MR3].arch_info)->enable = true; - } - - if (memory_config->ilm_base != 0) - if (nds32->privilege_level == 0) - ((struct nds32_reg *)reg_cache->reg_list[MR6].arch_info)->enable = true; - - if (memory_config->dlm_base != 0) - if (nds32->privilege_level == 0) - ((struct nds32_reg *)reg_cache->reg_list[MR7].arch_info)->enable = true; - - if ((memory_config->icache.line_size != 0) && (memory_config->dcache.line_size != 0)) - ((struct nds32_reg *)reg_cache->reg_list[MR8].arch_info)->enable = true; - - if (misc_config->high_speed_memory_port) - ((struct nds32_reg *)reg_cache->reg_list[MR9].arch_info)->enable = true; - - if (mr10_exist) - ((struct nds32_reg *)reg_cache->reg_list[MR10].arch_info)->enable = true; - - if (misc_config->edm) { - int dr_reg_n = nds32->edm.breakpoint_num * 5; - - for (int i = 0 ; i < dr_reg_n ; i++) - ((struct nds32_reg *)reg_cache->reg_list[DR0 + i].arch_info)->enable = true; - - ((struct nds32_reg *)reg_cache->reg_list[DR41].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DR43].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DR44].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DR45].arch_info)->enable = true; - } - - if (misc_config->debug_tracer) { - ((struct nds32_reg *)reg_cache->reg_list[DR46].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DR47].arch_info)->enable = true; - } - - if (misc_config->performance_monitor) { - ((struct nds32_reg *)reg_cache->reg_list[PFR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[PFR1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[PFR2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[PFR3].arch_info)->enable = true; - } - - if (misc_config->local_memory_dma) { - ((struct nds32_reg *)reg_cache->reg_list[DMAR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR4].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR5].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR7].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR8].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR9].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[DMAR10].arch_info)->enable = true; - } - - if ((misc_config->local_memory_dma || misc_config->performance_monitor) && - (no_racr0 == false)) - ((struct nds32_reg *)reg_cache->reg_list[RACR].arch_info)->enable = true; - - if (cpu_version->cop_fpu_extension || (misc_config->audio_isa != 0)) - ((struct nds32_reg *)reg_cache->reg_list[FUCPR].arch_info)->enable = true; - - if (misc_config->audio_isa != 0) { - if (misc_config->audio_isa > 1) { - ((struct nds32_reg *)reg_cache->reg_list[D0L24].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[D1L24].arch_info)->enable = true; - } - - ((struct nds32_reg *)reg_cache->reg_list[I0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I4].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I5].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[I7].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M5].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M6].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[M7].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[MOD].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[LBE].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[LE].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[LC].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[ADM_VBASE].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[SHFT_CTL0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[SHFT_CTL1].arch_info)->enable = true; - - uint32_t value_mod; - uint32_t fucpr_backup; - /* enable fpu and get configuration */ - nds32_get_mapped_reg(nds32, FUCPR, &fucpr_backup); - if ((fucpr_backup & 0x80000000) == 0) - nds32_set_mapped_reg(nds32, FUCPR, fucpr_backup | 0x80000000); - nds32_get_mapped_reg(nds32, MOD, &value_mod); - /* restore origin fucpr value */ - if ((fucpr_backup & 0x80000000) == 0) - nds32_set_mapped_reg(nds32, FUCPR, fucpr_backup); - - if ((value_mod >> 6) & 0x1) { - ((struct nds32_reg *)reg_cache->reg_list[CB_CTL].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBB0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBB1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBB2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBB3].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBE0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBE1].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBE2].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[CBE3].arch_info)->enable = true; - } - } - - if ((cpu_version->cpu_id_family == 0x9) || - (cpu_version->cpu_id_family == 0xA) || - (cpu_version->cpu_id_family == 0xC)) { - - ((struct nds32_reg *)reg_cache->reg_list[IDR0].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IDR1].arch_info)->enable = true; - - if ((cpu_version->cpu_id_family == 0xC) && (cpu_version->revision == 0x0C)) - ((struct nds32_reg *)reg_cache->reg_list[IDR0].arch_info)->enable = false; - } - - uint32_t ir3_value; - uint32_t ivb_prog_pri_lvl; - uint32_t ivb_ivic_ver; - - nds32_get_mapped_reg(nds32, IR3, &ir3_value); - ivb_prog_pri_lvl = ir3_value & 0x1; - ivb_ivic_ver = (ir3_value >> 11) & 0x3; - - if ((ivb_prog_pri_lvl == 1) || (ivb_ivic_ver >= 1)) { - ((struct nds32_reg *)reg_cache->reg_list[IR18].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR19].arch_info)->enable = true; - } - - if (ivb_ivic_ver >= 1) { - ((struct nds32_reg *)reg_cache->reg_list[IR26].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR27].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR28].arch_info)->enable = true; - ((struct nds32_reg *)reg_cache->reg_list[IR29].arch_info)->enable = true; - } - - return ERROR_OK; -} - -int nds32_init_register_table(struct nds32 *nds32) -{ - nds32_init_must_have_registers(nds32); - - return ERROR_OK; -} - -int nds32_add_software_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - uint32_t data; - uint32_t check_data; - uint32_t break_insn; - - /* check the breakpoint size */ - target->type->read_buffer(target, breakpoint->address, 4, (uint8_t *)&data); - - /* backup origin instruction - * instruction is big-endian */ - if (*(char *)&data & 0x80) { /* 16-bits instruction */ - breakpoint->length = 2; - break_insn = NDS32_BREAK_16; - } else { /* 32-bits instruction */ - breakpoint->length = 4; - break_insn = NDS32_BREAK_32; - } - - free(breakpoint->orig_instr); - - breakpoint->orig_instr = malloc(breakpoint->length); - memcpy(breakpoint->orig_instr, &data, breakpoint->length); - - /* self-modified code */ - target->type->write_buffer(target, breakpoint->address, breakpoint->length, (const uint8_t *)&break_insn); - /* write_back & invalidate dcache & invalidate icache */ - nds32_cache_sync(target, breakpoint->address, breakpoint->length); - - /* read back to check */ - target->type->read_buffer(target, breakpoint->address, breakpoint->length, (uint8_t *)&check_data); - if (memcmp(&check_data, &break_insn, breakpoint->length) == 0) - return ERROR_OK; - - return ERROR_FAIL; -} - -int nds32_remove_software_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - uint32_t check_data; - uint32_t break_insn; - - if (breakpoint->length == 2) - break_insn = NDS32_BREAK_16; - else if (breakpoint->length == 4) - break_insn = NDS32_BREAK_32; - else - return ERROR_FAIL; - - target->type->read_buffer(target, breakpoint->address, breakpoint->length, - (uint8_t *)&check_data); - - /* break instruction is modified */ - if (memcmp(&check_data, &break_insn, breakpoint->length) != 0) - return ERROR_FAIL; - - /* self-modified code */ - target->type->write_buffer(target, breakpoint->address, breakpoint->length, - breakpoint->orig_instr); - - /* write_back & invalidate dcache & invalidate icache */ - nds32_cache_sync(target, breakpoint->address, breakpoint->length); - - return ERROR_OK; -} - -/** - * Restore the processor context on an Andes target. The full processor - * context is analyzed to see if any of the registers are dirty on this end, but - * have a valid new value. If this is the case, the processor is changed to the - * appropriate mode and the new register values are written out to the - * processor. If there happens to be a dirty register with an invalid value, an - * error will be logged. - * - * @param target Pointer to the Andes target to have its context restored - * @return Error status if the target is not halted. - */ -int nds32_restore_context(struct target *target) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct reg_cache *reg_cache = nds32->core_cache; - struct reg *reg; - struct nds32_reg *reg_arch_info; - unsigned int i; - - LOG_DEBUG("-"); - - if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* check if there are dirty registers */ - for (i = 0; i < reg_cache->num_regs; i++) { - reg = &(reg_cache->reg_list[i]); - if (reg->dirty == true) { - if (reg->valid == true) { - - LOG_DEBUG("examining dirty reg: %s", reg->name); - LOG_DEBUG("writing register %d with value 0x%8.8" PRIx32, - i, buf_get_u32(reg->value, 0, 32)); - - reg_arch_info = reg->arch_info; - if (reg_arch_info->num >= FD0 && reg_arch_info->num <= FD31) { - uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64); - aice_write_reg_64(aice, reg_arch_info->num, val); - } else { - uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); - aice_write_register(aice, reg_arch_info->num, val); - } - - reg->valid = true; - reg->dirty = false; - } - } - } - - return ERROR_OK; -} - -int nds32_edm_config(struct nds32 *nds32) -{ - struct target *target = nds32->target; - struct aice_port_s *aice = target_to_aice(target); - uint32_t edm_cfg; - uint32_t edm_ctl; - - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); - - nds32->edm.version = (edm_cfg >> 16) & 0xFFFF; - LOG_INFO("EDM version 0x%04x", nds32->edm.version); - - nds32->edm.breakpoint_num = (edm_cfg & 0x7) + 1; - - if ((nds32->edm.version & 0x1000) || (nds32->edm.version >= 0x60)) - nds32->edm.access_control = true; - else - nds32->edm.access_control = false; - - if ((edm_cfg >> 4) & 0x1) - nds32->edm.direct_access_local_memory = true; - else - nds32->edm.direct_access_local_memory = false; - - if (nds32->edm.version <= 0x20) - nds32->edm.direct_access_local_memory = false; - - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl); - if (edm_ctl & (0x1 << 29)) - nds32->edm.support_max_stop = true; - else - nds32->edm.support_max_stop = false; - - /* set passcode for secure MCU */ - nds32_login(nds32); - - return ERROR_OK; -} - -int nds32_config(struct nds32 *nds32) -{ - nds32_init_config(nds32); - - /* init optional system registers according to config registers */ - nds32_init_option_registers(nds32); - - /* get max interrupt level */ - if (nds32->misc_config.interruption_level) - nds32->max_interrupt_level = 2; - else - nds32->max_interrupt_level = 3; - - /* get ILM/DLM size from MR6/MR7 */ - uint32_t value_mr6, value_mr7; - uint32_t size_index; - nds32_get_mapped_reg(nds32, MR6, &value_mr6); - size_index = (value_mr6 >> 1) & 0xF; - nds32->memory.ilm_size = nds32_lm_size_table[size_index]; - - nds32_get_mapped_reg(nds32, MR7, &value_mr7); - size_index = (value_mr7 >> 1) & 0xF; - nds32->memory.dlm_size = nds32_lm_size_table[size_index]; - - return ERROR_OK; -} - -int nds32_init_arch_info(struct target *target, struct nds32 *nds32) -{ - target->arch_info = nds32; - nds32->target = target; - - nds32->common_magic = NDS32_COMMON_MAGIC; - nds32->init_arch_info_after_halted = false; - nds32->auto_convert_hw_bp = true; - nds32->global_stop = false; - nds32->soft_reset_halt = false; - nds32->edm_passcode = NULL; - nds32->privilege_level = 0; - nds32->boot_time = 1500; - nds32->reset_halt_as_examine = false; - nds32->keep_target_edm_ctl = false; - nds32->word_access_mem = false; - nds32->virtual_hosting = true; - nds32->hit_syscall = false; - nds32->active_syscall_id = NDS32_SYSCALL_UNDEFINED; - nds32->virtual_hosting_errno = 0; - nds32->virtual_hosting_ctrl_c = false; - nds32->attached = false; - - nds32->syscall_break.asid = 0; - nds32->syscall_break.length = 4; - nds32->syscall_break.is_set = false; - nds32->syscall_break.orig_instr = NULL; - nds32->syscall_break.next = NULL; - nds32->syscall_break.unique_id = 0x515CAll + target->target_number; - nds32->syscall_break.linked_brp = 0; - - nds32_reg_init(); - - if (nds32_reg_cache_init(target, nds32) == ERROR_FAIL) - return ERROR_FAIL; - - if (nds32_init_register_table(nds32) != ERROR_OK) - return ERROR_FAIL; - - return ERROR_OK; -} - -int nds32_virtual_to_physical(struct target *target, target_addr_t address, target_addr_t *physical) -{ - struct nds32 *nds32 = target_to_nds32(target); - - if (nds32->memory.address_translation == false) { - *physical = address; - return ERROR_OK; - } - - if (nds32_probe_tlb(nds32, address, physical) == ERROR_OK) - return ERROR_OK; - - if (nds32_walk_page_table(nds32, address, physical) == ERROR_OK) - return ERROR_OK; - - return ERROR_FAIL; -} - -int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_cache *dcache = &(nds32->memory.dcache); - struct nds32_cache *icache = &(nds32->memory.icache); - uint32_t dcache_line_size = nds32_line_size_table[dcache->line_size]; - uint32_t icache_line_size = nds32_line_size_table[icache->line_size]; - uint32_t cur_address; - int result; - uint32_t start_line, end_line; - uint32_t cur_line; - - if ((dcache->line_size != 0) && (dcache->enable == true)) { - /* address / dcache_line_size */ - start_line = address >> (dcache->line_size + 2); - /* (address + length - 1) / dcache_line_size */ - end_line = (address + length - 1) >> (dcache->line_size + 2); - - for (cur_address = address, cur_line = start_line; - cur_line <= end_line; - cur_address += dcache_line_size, cur_line++) { - /* D$ write back */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_WB, cur_address); - if (result != ERROR_OK) - return result; - - /* D$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_INVAL, cur_address); - if (result != ERROR_OK) - return result; - } - } - - if ((icache->line_size != 0) && (icache->enable == true)) { - /* address / icache_line_size */ - start_line = address >> (icache->line_size + 2); - /* (address + length - 1) / icache_line_size */ - end_line = (address + length - 1) >> (icache->line_size + 2); - - for (cur_address = address, cur_line = start_line; - cur_line <= end_line; - cur_address += icache_line_size, cur_line++) { - /* Because PSW.IT is turned off under debug exception, address MUST - * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide - * address translation or not. */ - target_addr_t physical_addr; - if (target->type->virt2phys(target, cur_address, &physical_addr) == ERROR_FAIL) - return ERROR_FAIL; - - /* I$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_VA_INVAL, physical_addr); - if (result != ERROR_OK) - return result; - } - } - - return ERROR_OK; -} - -uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address) -{ - if (!current) - nds32_set_mapped_reg(nds32, PC, address); - else - nds32_get_mapped_reg(nds32, PC, &address); - - return address; -} - -int nds32_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) -{ - LOG_DEBUG("target->state: %s", - target_state_name(target)); - - if (target->state != TARGET_HALTED) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - struct nds32 *nds32 = target_to_nds32(target); - - address = nds32_nextpc(nds32, current, address); - - LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : ""); - - /** set DSSIM */ - uint32_t ir14_value; - nds32_get_mapped_reg(nds32, IR14, &ir14_value); - if (nds32->step_isr_enable) - ir14_value |= (0x1 << 31); - else - ir14_value &= ~(0x1 << 31); - nds32_set_mapped_reg(nds32, IR14, ir14_value); - - /* check hit_syscall before leave_debug_state() because - * leave_debug_state() may clear hit_syscall flag */ - bool no_step = false; - if (nds32->hit_syscall) - /* step after hit_syscall should be ignored because - * leave_debug_state will step implicitly to skip the - * syscall */ - no_step = true; - - /********* TODO: maybe create another function to handle this part */ - CHECK_RETVAL(nds32->leave_debug_state(nds32, true)); - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - - if (no_step == false) { - struct aice_port_s *aice = target_to_aice(target); - if (aice_step(aice) != ERROR_OK) - return ERROR_FAIL; - } - - /* save state */ - CHECK_RETVAL(nds32->enter_debug_state(nds32, true)); - /********* TODO: maybe create another function to handle this part */ - - /* restore DSSIM */ - if (nds32->step_isr_enable) { - nds32_get_mapped_reg(nds32, IR14, &ir14_value); - ir14_value &= ~(0x1 << 31); - nds32_set_mapped_reg(nds32, IR14, ir14_value); - } - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); - - return ERROR_OK; -} - -static int nds32_step_without_watchpoint(struct nds32 *nds32) -{ - struct target *target = nds32->target; - - if (target->state != TARGET_HALTED) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /** set DSSIM */ - uint32_t ir14_value; - nds32_get_mapped_reg(nds32, IR14, &ir14_value); - if (nds32->step_isr_enable) - ir14_value |= (0x1 << 31); - else - ir14_value &= ~(0x1 << 31); - nds32_set_mapped_reg(nds32, IR14, ir14_value); - - /********* TODO: maybe create another function to handle this part */ - CHECK_RETVAL(nds32->leave_debug_state(nds32, false)); - - struct aice_port_s *aice = target_to_aice(target); - - if (aice_step(aice) != ERROR_OK) - return ERROR_FAIL; - - /* save state */ - CHECK_RETVAL(nds32->enter_debug_state(nds32, false)); - /********* TODO: maybe create another function to handle this part */ - - /* restore DSSIM */ - if (nds32->step_isr_enable) { - nds32_get_mapped_reg(nds32, IR14, &ir14_value); - ir14_value &= ~(0x1 << 31); - nds32_set_mapped_reg(nds32, IR14, ir14_value); - } - - return ERROR_OK; -} - -int nds32_target_state(struct nds32 *nds32, enum target_state *state) -{ - struct aice_port_s *aice = target_to_aice(nds32->target); - enum aice_target_state_s nds32_state; - - if (aice_state(aice, &nds32_state) != ERROR_OK) - return ERROR_FAIL; - - switch (nds32_state) { - case AICE_DISCONNECT: - LOG_INFO("USB is disconnected"); - return ERROR_FAIL; - case AICE_TARGET_DETACH: - LOG_INFO("Target is disconnected"); - return ERROR_FAIL; - case AICE_TARGET_UNKNOWN: - *state = TARGET_UNKNOWN; - break; - case AICE_TARGET_RUNNING: - *state = TARGET_RUNNING; - break; - case AICE_TARGET_HALTED: - *state = TARGET_HALTED; - break; - case AICE_TARGET_RESET: - *state = TARGET_RESET; - break; - case AICE_TARGET_DEBUG_RUNNING: - *state = TARGET_DEBUG_RUNNING; - break; - default: - return ERROR_FAIL; - } - - return ERROR_OK; -} - -int nds32_examine_debug_reason(struct nds32 *nds32) -{ - uint32_t reason; - struct target *target = nds32->target; - - if (nds32->hit_syscall == true) { - LOG_DEBUG("Hit syscall breakpoint"); - target->debug_reason = DBG_REASON_BREAKPOINT; - return ERROR_OK; - } - - nds32->get_debug_reason(nds32, &reason); - - LOG_DEBUG("nds32 examines debug reason: %s", nds32_debug_type_name[reason]); - - /* Examine debug reason */ - switch (reason) { - case NDS32_DEBUG_BREAK: - case NDS32_DEBUG_BREAK_16: - case NDS32_DEBUG_INST_BREAK: - { - uint32_t value_pc; - uint32_t opcode; - struct nds32_instruction instruction; - - nds32_get_mapped_reg(nds32, PC, &value_pc); - - if (nds32_read_opcode(nds32, value_pc, &opcode) != ERROR_OK) - return ERROR_FAIL; - if (nds32_evaluate_opcode(nds32, opcode, value_pc, &instruction) != ERROR_OK) - return ERROR_FAIL; - - /* hit 'break 0x7FFF' */ - if ((instruction.info.opc_6 == 0x32) && - (instruction.info.sub_opc == 0xA) && - (instruction.info.imm == 0x7FFF)) { - target->debug_reason = DBG_REASON_EXIT; - } else - target->debug_reason = DBG_REASON_BREAKPOINT; - } - break; - case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE: - case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE: - case NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP: /* GLOBAL_STOP is precise exception */ - { - int result; - - result = nds32->get_watched_address(nds32, - &(nds32->watched_address), reason); - /* do single step(without watchpoints) to skip the "watched" instruction */ - nds32_step_without_watchpoint(nds32); - - /* before single_step, save exception address */ - if (result != ERROR_OK) - return ERROR_FAIL; - - target->debug_reason = DBG_REASON_WATCHPOINT; - } - break; - case NDS32_DEBUG_DEBUG_INTERRUPT: - target->debug_reason = DBG_REASON_DBGRQ; - break; - case NDS32_DEBUG_HARDWARE_SINGLE_STEP: - target->debug_reason = DBG_REASON_SINGLESTEP; - break; - case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE: - case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE: - case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE: - if (nds32->get_watched_address(nds32, &(nds32->watched_address), reason) != ERROR_OK) - return ERROR_FAIL; - - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - default: - target->debug_reason = DBG_REASON_UNDEFINED; - break; - } - - return ERROR_OK; -} - -int nds32_login(struct nds32 *nds32) -{ - struct target *target = nds32->target; - struct aice_port_s *aice = target_to_aice(target); - uint32_t passcode_length; - char command_sequence[129]; - char command_str[33]; - char code_str[9]; - uint32_t copy_length; - uint32_t code; - uint32_t i; - - LOG_DEBUG("nds32_login"); - - if (nds32->edm_passcode) { - /* convert EDM passcode to command sequences */ - passcode_length = strlen(nds32->edm_passcode); - command_sequence[0] = '\0'; - for (i = 0; i < passcode_length; i += 8) { - if (passcode_length - i < 8) - copy_length = passcode_length - i; - else - copy_length = 8; - - strncpy(code_str, nds32->edm_passcode + i, copy_length); - code_str[copy_length] = '\0'; - code = strtoul(code_str, NULL, 16); - - sprintf(command_str, "write_misc gen_port0 0x%" PRIx32 ";", code); - strcat(command_sequence, command_str); - } - - if (aice_program_edm(aice, command_sequence) != ERROR_OK) - return ERROR_FAIL; - - /* get current privilege level */ - uint32_t value_edmsw; - aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &value_edmsw); - nds32->privilege_level = (value_edmsw >> 16) & 0x3; - LOG_INFO("Current privilege level: %d", nds32->privilege_level); - } - - if (nds32_edm_ops_num > 0) { - const char *reg_name; - for (i = 0 ; i < nds32_edm_ops_num ; i++) { - code = nds32_edm_ops[i].value; - if (nds32_edm_ops[i].reg_no == 6) - reg_name = "gen_port0"; - else if (nds32_edm_ops[i].reg_no == 7) - reg_name = "gen_port1"; - else - return ERROR_FAIL; - - sprintf(command_str, "write_misc %s 0x%" PRIx32 ";", reg_name, code); - if (aice_program_edm(aice, command_str) != ERROR_OK) - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -int nds32_halt(struct target *target) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - enum target_state state; - - LOG_DEBUG("target->state: %s", - target_state_name(target)); - - if (target->state == TARGET_HALTED) { - LOG_DEBUG("target was already halted"); - return ERROR_OK; - } - - if (nds32_target_state(nds32, &state) != ERROR_OK) - return ERROR_FAIL; - - if (state != TARGET_HALTED) - /* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */ - if (aice_halt(aice) != ERROR_OK) - return ERROR_FAIL; - - CHECK_RETVAL(nds32->enter_debug_state(nds32, true)); - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); - - return ERROR_OK; -} - -/* poll current target status */ -int nds32_poll(struct target *target) -{ - struct nds32 *nds32 = target_to_nds32(target); - enum target_state state; - - if (nds32_target_state(nds32, &state) != ERROR_OK) - return ERROR_FAIL; - - if (state == TARGET_HALTED) { - if (target->state != TARGET_HALTED) { - /* if false_hit, continue free_run */ - if (nds32->enter_debug_state(nds32, true) != ERROR_OK) { - struct aice_port_s *aice = target_to_aice(target); - aice_run(aice); - return ERROR_OK; - } - - LOG_DEBUG("Change target state to TARGET_HALTED."); - - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - } else if (state == TARGET_RESET) { - if (target->state == TARGET_HALTED) { - /* similar to assert srst */ - register_cache_invalidate(nds32->core_cache); - target->state = TARGET_RESET; - - /* TODO: deassert srst */ - } else if (target->state == TARGET_RUNNING) { - /* reset as running */ - LOG_WARNING("<-- TARGET WARNING! The debug target has been reset. -->"); - } - } else { - if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) { - LOG_DEBUG("Change target state to TARGET_RUNNING."); - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - } - } - - return ERROR_OK; -} - -int nds32_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) -{ - LOG_DEBUG("current %d address %08" TARGET_PRIxADDR - " handle_breakpoints %d" - " debug_execution %d", - current, address, handle_breakpoints, debug_execution); - - struct nds32 *nds32 = target_to_nds32(target); - - if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - address = nds32_nextpc(nds32, current, address); - - LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : ""); - - if (!debug_execution) - target_free_all_working_areas(target); - - /* Disable HSS to avoid users misuse HSS */ - if (nds32_reach_max_interrupt_level(nds32) == false) { - uint32_t value_ir0; - nds32_get_mapped_reg(nds32, IR0, &value_ir0); - value_ir0 &= ~(0x1 << 11); - nds32_set_mapped_reg(nds32, IR0, value_ir0); - } - - CHECK_RETVAL(nds32->leave_debug_state(nds32, true)); - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - - if (nds32->virtual_hosting_ctrl_c == false) { - struct aice_port_s *aice = target_to_aice(target); - aice_run(aice); - } else - nds32->virtual_hosting_ctrl_c = false; - - target->debug_reason = DBG_REASON_NOTHALTED; - if (!debug_execution) - target->state = TARGET_RUNNING; - else - target->state = TARGET_DEBUG_RUNNING; - - LOG_DEBUG("target->state: %s", - target_state_name(target)); - - return ERROR_OK; -} - -static int nds32_soft_reset_halt(struct target *target) -{ - /* TODO: test it */ - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - - aice_assert_srst(aice, AICE_SRST); - - /* halt core and set pc to 0x0 */ - int retval = target_halt(target); - if (retval != ERROR_OK) - return retval; - - /* start fetching from IVB */ - uint32_t value_ir3; - nds32_get_mapped_reg(nds32, IR3, &value_ir3); - nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000); - - return ERROR_OK; -} - -int nds32_assert_reset(struct target *target) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_cpu_version *cpu_version = &(nds32->cpu_version); - - /* TODO: apply hw reset signal in not examined state */ - if (!(target_was_examined(target))) { - LOG_WARNING("Reset is not asserted because the target is not examined."); - LOG_WARNING("Use a reset button or power cycle the target."); - return ERROR_TARGET_NOT_EXAMINED; - } - - if (target->reset_halt) { - if ((nds32->soft_reset_halt) - || (nds32->edm.version < 0x51) - || ((nds32->edm.version == 0x51) - && (cpu_version->revision == 0x1C) - && (cpu_version->cpu_id_family == 0xC) - && (cpu_version->cpu_id_version == 0x0))) - nds32_soft_reset_halt(target); - else - aice_assert_srst(aice, AICE_RESET_HOLD); - } else { - aice_assert_srst(aice, AICE_SRST); - alive_sleep(nds32->boot_time); - } - - /* set passcode for secure MCU after core reset */ - nds32_login(nds32); - - /* registers are now invalid */ - register_cache_invalidate(nds32->core_cache); - - target->state = TARGET_RESET; - - return ERROR_OK; -} - -static int nds32_gdb_attach(struct nds32 *nds32) -{ - LOG_DEBUG("nds32_gdb_attach, target coreid: %" PRId32, nds32->target->coreid); - - if (nds32->attached == false) { - - if (nds32->keep_target_edm_ctl) { - /* backup target EDM_CTL */ - struct aice_port_s *aice = target_to_aice(nds32->target); - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &nds32->backup_edm_ctl); - } - - target_halt(nds32->target); - - nds32->attached = true; - } - - return ERROR_OK; -} - -static int nds32_gdb_detach(struct nds32 *nds32) -{ - LOG_DEBUG("nds32_gdb_detach"); - bool backup_virtual_hosting_setting; - - if (nds32->attached) { - - backup_virtual_hosting_setting = nds32->virtual_hosting; - /* turn off virtual hosting before resume as gdb-detach */ - nds32->virtual_hosting = false; - target_resume(nds32->target, 1, 0, 0, 0); - nds32->virtual_hosting = backup_virtual_hosting_setting; - - if (nds32->keep_target_edm_ctl) { - /* restore target EDM_CTL */ - struct aice_port_s *aice = target_to_aice(nds32->target); - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, nds32->backup_edm_ctl); - } - - nds32->attached = false; - } - - return ERROR_OK; -} - -static int nds32_callback_event_handler(struct target *target, - enum target_event event, void *priv) -{ - int retval = ERROR_OK; - int target_number = *(int *)priv; - - if (target_number != target->target_number) - return ERROR_OK; - - struct nds32 *nds32 = target_to_nds32(target); - - switch (event) { - case TARGET_EVENT_GDB_ATTACH: - retval = nds32_gdb_attach(nds32); - break; - case TARGET_EVENT_GDB_DETACH: - retval = nds32_gdb_detach(nds32); - break; - default: - break; - } - - return retval; -} - -int nds32_init(struct nds32 *nds32) -{ - /* Initialize anything we can set up without talking to the target */ - nds32->memory.access_channel = NDS_MEMORY_ACC_CPU; - - /* register event callback */ - target_register_event_callback(nds32_callback_event_handler, - &(nds32->target->target_number)); - - return ERROR_OK; -} - -int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info) -{ - /* fill syscall parameters to file-I/O info */ - if (!fileio_info) { - LOG_ERROR("Target has not initial file-I/O data structure"); - return ERROR_FAIL; - } - - struct nds32 *nds32 = target_to_nds32(target); - uint32_t value_ir6; - uint32_t syscall_id; - - if (nds32->hit_syscall == false) - return ERROR_FAIL; - - nds32_get_mapped_reg(nds32, IR6, &value_ir6); - syscall_id = (value_ir6 >> 16) & 0x7FFF; - nds32->active_syscall_id = syscall_id; - - LOG_DEBUG("hit syscall ID: 0x%" PRIx32, syscall_id); - - /* free previous identifier storage */ - free(fileio_info->identifier); - fileio_info->identifier = NULL; - - uint32_t reg_r0, reg_r1, reg_r2; - nds32_get_mapped_reg(nds32, R0, ®_r0); - nds32_get_mapped_reg(nds32, R1, ®_r1); - nds32_get_mapped_reg(nds32, R2, ®_r2); - - switch (syscall_id) { - case NDS32_SYSCALL_EXIT: - fileio_info->identifier = malloc(5); - sprintf(fileio_info->identifier, "exit"); - fileio_info->param_1 = reg_r0; - break; - case NDS32_SYSCALL_OPEN: - { - uint8_t filename[256]; - fileio_info->identifier = malloc(5); - sprintf(fileio_info->identifier, "open"); - fileio_info->param_1 = reg_r0; - /* reserve fileio_info->param_2 for length of path */ - fileio_info->param_3 = reg_r1; - fileio_info->param_4 = reg_r2; - - target->type->read_buffer(target, reg_r0, 256, filename); - fileio_info->param_2 = strlen((char *)filename); - } - break; - case NDS32_SYSCALL_CLOSE: - fileio_info->identifier = malloc(6); - sprintf(fileio_info->identifier, "close"); - fileio_info->param_1 = reg_r0; - break; - case NDS32_SYSCALL_READ: - fileio_info->identifier = malloc(5); - sprintf(fileio_info->identifier, "read"); - fileio_info->param_1 = reg_r0; - fileio_info->param_2 = reg_r1; - fileio_info->param_3 = reg_r2; - break; - case NDS32_SYSCALL_WRITE: - fileio_info->identifier = malloc(6); - sprintf(fileio_info->identifier, "write"); - fileio_info->param_1 = reg_r0; - fileio_info->param_2 = reg_r1; - fileio_info->param_3 = reg_r2; - break; - case NDS32_SYSCALL_LSEEK: - fileio_info->identifier = malloc(6); - sprintf(fileio_info->identifier, "lseek"); - fileio_info->param_1 = reg_r0; - fileio_info->param_2 = reg_r1; - fileio_info->param_3 = reg_r2; - break; - case NDS32_SYSCALL_UNLINK: - { - uint8_t filename[256]; - fileio_info->identifier = malloc(7); - sprintf(fileio_info->identifier, "unlink"); - fileio_info->param_1 = reg_r0; - /* reserve fileio_info->param_2 for length of path */ - - target->type->read_buffer(target, reg_r0, 256, filename); - fileio_info->param_2 = strlen((char *)filename); - } - break; - case NDS32_SYSCALL_RENAME: - { - uint8_t filename[256]; - fileio_info->identifier = malloc(7); - sprintf(fileio_info->identifier, "rename"); - fileio_info->param_1 = reg_r0; - /* reserve fileio_info->param_2 for length of old path */ - fileio_info->param_3 = reg_r1; - /* reserve fileio_info->param_4 for length of new path */ - - target->type->read_buffer(target, reg_r0, 256, filename); - fileio_info->param_2 = strlen((char *)filename); - - target->type->read_buffer(target, reg_r1, 256, filename); - fileio_info->param_4 = strlen((char *)filename); - } - break; - case NDS32_SYSCALL_FSTAT: - fileio_info->identifier = malloc(6); - sprintf(fileio_info->identifier, "fstat"); - fileio_info->param_1 = reg_r0; - fileio_info->param_2 = reg_r1; - break; - case NDS32_SYSCALL_STAT: - { - uint8_t filename[256]; - fileio_info->identifier = malloc(5); - sprintf(fileio_info->identifier, "stat"); - fileio_info->param_1 = reg_r0; - /* reserve fileio_info->param_2 for length of old path */ - fileio_info->param_3 = reg_r1; - - target->type->read_buffer(target, reg_r0, 256, filename); - fileio_info->param_2 = strlen((char *)filename) + 1; - } - break; - case NDS32_SYSCALL_GETTIMEOFDAY: - fileio_info->identifier = malloc(13); - sprintf(fileio_info->identifier, "gettimeofday"); - fileio_info->param_1 = reg_r0; - fileio_info->param_2 = reg_r1; - break; - case NDS32_SYSCALL_ISATTY: - fileio_info->identifier = malloc(7); - sprintf(fileio_info->identifier, "isatty"); - fileio_info->param_1 = reg_r0; - break; - case NDS32_SYSCALL_SYSTEM: - { - uint8_t command[256]; - fileio_info->identifier = malloc(7); - sprintf(fileio_info->identifier, "system"); - fileio_info->param_1 = reg_r0; - /* reserve fileio_info->param_2 for length of old path */ - - target->type->read_buffer(target, reg_r0, 256, command); - fileio_info->param_2 = strlen((char *)command); - } - break; - case NDS32_SYSCALL_ERRNO: - fileio_info->identifier = malloc(6); - sprintf(fileio_info->identifier, "errno"); - nds32_set_mapped_reg(nds32, R0, nds32->virtual_hosting_errno); - break; - default: - fileio_info->identifier = malloc(8); - sprintf(fileio_info->identifier, "unknown"); - break; - } - - return ERROR_OK; -} - -int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c) -{ - LOG_DEBUG("syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s", - retcode, fileio_errno, ctrl_c ? "true" : "false"); - - struct nds32 *nds32 = target_to_nds32(target); - - nds32_set_mapped_reg(nds32, R0, (uint32_t)retcode); - - nds32->virtual_hosting_errno = fileio_errno; - nds32->virtual_hosting_ctrl_c = ctrl_c; - nds32->active_syscall_id = NDS32_SYSCALL_UNDEFINED; - - return ERROR_OK; -} - -int nds32_profiling(struct target *target, uint32_t *samples, - uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds) -{ - /* sample $PC every 10 milliseconds */ - uint32_t iteration = seconds * 100; - struct aice_port_s *aice = target_to_aice(target); - struct nds32 *nds32 = target_to_nds32(target); - - /* REVISIT: can nds32 profile without halting? */ - if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (profiling)", target->cmd_name); - return ERROR_TARGET_NOT_HALTED; - } - - if (max_num_samples < iteration) - iteration = max_num_samples; - - int pc_regnum = nds32->register_map(nds32, PC); - aice_profiling(aice, 10, iteration, pc_regnum, samples, num_samples); - - register_cache_invalidate(nds32->core_cache); - - return ERROR_OK; -} - -int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address, - uint32_t size, const uint8_t *buffer) -{ - if ((nds32->active_syscall_id == NDS32_SYSCALL_FSTAT) || - (nds32->active_syscall_id == NDS32_SYSCALL_STAT)) { - /* If doing GDB file-I/O, target should convert 'struct stat' - * from gdb-format to target-format */ - uint8_t stat_buffer[NDS32_STRUCT_STAT_SIZE]; - /* st_dev 2 */ - stat_buffer[0] = buffer[3]; - stat_buffer[1] = buffer[2]; - /* st_ino 2 */ - stat_buffer[2] = buffer[7]; - stat_buffer[3] = buffer[6]; - /* st_mode 4 */ - stat_buffer[4] = buffer[11]; - stat_buffer[5] = buffer[10]; - stat_buffer[6] = buffer[9]; - stat_buffer[7] = buffer[8]; - /* st_nlink 2 */ - stat_buffer[8] = buffer[15]; - stat_buffer[9] = buffer[16]; - /* st_uid 2 */ - stat_buffer[10] = buffer[19]; - stat_buffer[11] = buffer[18]; - /* st_gid 2 */ - stat_buffer[12] = buffer[23]; - stat_buffer[13] = buffer[22]; - /* st_rdev 2 */ - stat_buffer[14] = buffer[27]; - stat_buffer[15] = buffer[26]; - /* st_size 4 */ - stat_buffer[16] = buffer[35]; - stat_buffer[17] = buffer[34]; - stat_buffer[18] = buffer[33]; - stat_buffer[19] = buffer[32]; - /* st_atime 4 */ - stat_buffer[20] = buffer[55]; - stat_buffer[21] = buffer[54]; - stat_buffer[22] = buffer[53]; - stat_buffer[23] = buffer[52]; - /* st_spare1 4 */ - stat_buffer[24] = 0; - stat_buffer[25] = 0; - stat_buffer[26] = 0; - stat_buffer[27] = 0; - /* st_mtime 4 */ - stat_buffer[28] = buffer[59]; - stat_buffer[29] = buffer[58]; - stat_buffer[30] = buffer[57]; - stat_buffer[31] = buffer[56]; - /* st_spare2 4 */ - stat_buffer[32] = 0; - stat_buffer[33] = 0; - stat_buffer[34] = 0; - stat_buffer[35] = 0; - /* st_ctime 4 */ - stat_buffer[36] = buffer[63]; - stat_buffer[37] = buffer[62]; - stat_buffer[38] = buffer[61]; - stat_buffer[39] = buffer[60]; - /* st_spare3 4 */ - stat_buffer[40] = 0; - stat_buffer[41] = 0; - stat_buffer[42] = 0; - stat_buffer[43] = 0; - /* st_blksize 4 */ - stat_buffer[44] = buffer[43]; - stat_buffer[45] = buffer[42]; - stat_buffer[46] = buffer[41]; - stat_buffer[47] = buffer[40]; - /* st_blocks 4 */ - stat_buffer[48] = buffer[51]; - stat_buffer[49] = buffer[50]; - stat_buffer[50] = buffer[49]; - stat_buffer[51] = buffer[48]; - /* st_spare4 8 */ - stat_buffer[52] = 0; - stat_buffer[53] = 0; - stat_buffer[54] = 0; - stat_buffer[55] = 0; - stat_buffer[56] = 0; - stat_buffer[57] = 0; - stat_buffer[58] = 0; - stat_buffer[59] = 0; - - return nds32_write_buffer(nds32->target, address, NDS32_STRUCT_STAT_SIZE, stat_buffer); - } else if (nds32->active_syscall_id == NDS32_SYSCALL_GETTIMEOFDAY) { - /* If doing GDB file-I/O, target should convert 'struct timeval' - * from gdb-format to target-format */ - uint8_t timeval_buffer[NDS32_STRUCT_TIMEVAL_SIZE]; - timeval_buffer[0] = buffer[3]; - timeval_buffer[1] = buffer[2]; - timeval_buffer[2] = buffer[1]; - timeval_buffer[3] = buffer[0]; - timeval_buffer[4] = buffer[11]; - timeval_buffer[5] = buffer[10]; - timeval_buffer[6] = buffer[9]; - timeval_buffer[7] = buffer[8]; - - return nds32_write_buffer(nds32->target, address, NDS32_STRUCT_TIMEVAL_SIZE, timeval_buffer); - } - - return nds32_write_buffer(nds32->target, address, size, buffer); -} - -int nds32_reset_halt(struct nds32 *nds32) -{ - LOG_INFO("reset halt as init"); - - struct aice_port_s *aice = target_to_aice(nds32->target); - aice_assert_srst(aice, AICE_RESET_HOLD); - - return ERROR_OK; -} diff --git a/src/target/nds32.h b/src/target/nds32.h deleted file mode 100644 index 1c8675e731..0000000000 --- a/src/target/nds32.h +++ /dev/null @@ -1,446 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_H -#define OPENOCD_TARGET_NDS32_H - -#include <jtag/jtag.h> -#include "target.h" -#include "target_type.h" -#include "register.h" -#include "breakpoints.h" -#include "nds32_reg.h" -#include "nds32_insn.h" -#include "nds32_edm.h" - -#define NDS32_EDM_OPERATION_MAX_NUM 64 - -#define CHECK_RETVAL(action) \ - do { \ - int __retval = (action); \ - if (__retval != ERROR_OK) { \ - LOG_DEBUG("error while calling \"%s\"", \ - # action); \ - return __retval; \ - } \ - } while (0) - -/** - * @file - * Holds the interface to Andes cores. - */ - -extern const char *nds32_debug_type_name[11]; - -enum nds32_debug_reason { - NDS32_DEBUG_BREAK = 0, - NDS32_DEBUG_BREAK_16, - NDS32_DEBUG_INST_BREAK, - NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE, - NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE, - NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE, - NDS32_DEBUG_DEBUG_INTERRUPT, - NDS32_DEBUG_HARDWARE_SINGLE_STEP, - NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE, - NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE, - NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP, -}; - -#define NDS32_STRUCT_STAT_SIZE 60 -#define NDS32_STRUCT_TIMEVAL_SIZE 8 - -enum nds32_syscall_id { - NDS32_SYSCALL_UNDEFINED = 0, - NDS32_SYSCALL_EXIT = 1, - NDS32_SYSCALL_OPEN = 2, - NDS32_SYSCALL_CLOSE = 3, - NDS32_SYSCALL_READ = 4, - NDS32_SYSCALL_WRITE = 5, - NDS32_SYSCALL_LSEEK = 6, - NDS32_SYSCALL_UNLINK = 7, - NDS32_SYSCALL_RENAME = 3001, - NDS32_SYSCALL_FSTAT = 10, - NDS32_SYSCALL_STAT = 15, - NDS32_SYSCALL_GETTIMEOFDAY = 19, - NDS32_SYSCALL_ISATTY = 3002, - NDS32_SYSCALL_SYSTEM = 3003, - NDS32_SYSCALL_ERRNO = 6001, -}; - -#define NDS32_COMMON_MAGIC 0xADE5ADE5U - -struct nds32_edm { - - /** EDM_CFG.VER, indicate the EDM version */ - int version; - - /** The number of hardware breakpoints */ - int breakpoint_num; - - /** EDM_CFG.DALM, indicate if direct local memory access - * feature is supported or not */ - bool direct_access_local_memory; - - /** Support ACC_CTL register */ - bool access_control; - - /** */ - bool support_max_stop; -}; - -struct nds32_cache { - - /** enable cache or not */ - bool enable; - - /** cache sets per way */ - int set; - - /** cache ways */ - int way; - - /** cache line size */ - int line_size; - - /** cache locking support */ - bool lock_support; -}; - -struct nds32_memory { - - /** ICache */ - struct nds32_cache icache; - - /** DCache */ - struct nds32_cache dcache; - - /** On-chip instruction local memory base */ - int ilm_base; - - /** On-chip instruction local memory size */ - int ilm_size; - - /** ILM base register alignment version */ - int ilm_align_ver; - - /** DLM is enabled or not */ - bool ilm_enable; - - /** DLM start address */ - int ilm_start; - - /** DLM end address */ - int ilm_end; - - /** On-chip data local memory base */ - int dlm_base; - - /** On-chip data local memory size */ - int dlm_size; - - /** DLM base register alignment version */ - int dlm_align_ver; - - /** DLM is enabled or not */ - bool dlm_enable; - - /** DLM start address */ - int dlm_start; - - /** DLM end address */ - int dlm_end; - - /** Memory access method */ - enum nds_memory_access access_channel; - - /** Memory access mode */ - enum nds_memory_select mode; - - /** Address translation */ - bool address_translation; -}; - -struct nds32_cpu_version { - bool performance_extension; - bool _16bit_extension; - bool performance_extension_2; - bool cop_fpu_extension; - bool string_extension; - - int revision; - int cpu_id_family; - int cpu_id_version; -}; - -struct nds32_mmu_config { - int memory_protection; - int memory_protection_version; - bool fully_associative_tlb; - int tlb_size; - int tlb_ways; - int tlb_sets; - bool _8k_page_support; - int extra_page_size_support; - bool tlb_lock; - bool hardware_page_table_walker; - bool default_endian; - int partition_num; - bool invisible_tlb; - bool vlpt; - bool ntme; - bool drde; - int default_min_page_size; - bool multiple_page_size_in_use; -}; - -struct nds32_misc_config { - bool edm; - bool local_memory_dma; - bool performance_monitor; - bool high_speed_memory_port; - bool debug_tracer; - bool div_instruction; - bool mac_instruction; - int audio_isa; - bool l2_cache; - bool reduce_register; - bool addr_24; - bool interruption_level; - int baseline_instruction; - bool no_dx_register; - bool implement_dependant_register; - bool implement_dependant_sr_encoding; - bool ifc; - bool mcu; - bool ex9; - int shadow; -}; - -/** - * Represents a generic Andes core. - */ -struct nds32 { - uint32_t common_magic; - struct reg_cache *core_cache; - - /** Handle for the debug module. */ - struct nds32_edm edm; - - /** Memory information */ - struct nds32_memory memory; - - /** cpu version */ - struct nds32_cpu_version cpu_version; - - /** MMU configuration */ - struct nds32_mmu_config mmu_config; - - /** Misc configuration */ - struct nds32_misc_config misc_config; - - /** Retrieve all core registers, for display. */ - int (*full_context)(struct nds32 *nds32); - - /** Register mappings */ - int (*register_map)(struct nds32 *nds32, int reg_no); - - /** Get debug exception virtual address */ - int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason); - - /** Restore target registers may be modified in debug state */ - int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint); - - /** Backup target registers may be modified in debug state */ - int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint); - - /** Get address hit watchpoint */ - int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason); - - /** maximum interrupt level */ - uint32_t max_interrupt_level; - - /** current interrupt level */ - uint32_t current_interrupt_level; - - uint32_t watched_address; - - /** Flag reporting whether virtual hosting is active. */ - bool virtual_hosting; - - /** Flag reporting whether continue/step hits syscall or not */ - bool hit_syscall; - - /** Value to be returned by virtual hosting SYS_ERRNO request. */ - int virtual_hosting_errno; - - /** Flag reporting whether syscall is aborted */ - bool virtual_hosting_ctrl_c; - - /** Record syscall ID for other operations to do special processing for target */ - int active_syscall_id; - - struct breakpoint syscall_break; - - /** Flag reporting whether global stop is active. */ - bool global_stop; - - /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */ - bool soft_reset_halt; - - /** reset-halt as target examine */ - bool reset_halt_as_examine; - - /** backup/restore target EDM_CTL value. As debugging target debug - * handler, it should be true. */ - bool keep_target_edm_ctl; - - /* Value of $EDM_CTL before target enters debug mode */ - uint32_t backup_edm_ctl; - - /** always use word-aligned address to access memory */ - bool word_access_mem; - - /** EDM passcode for debugging secure MCU */ - char *edm_passcode; - - /** current privilege_level if using secure MCU. value 0 is the highest level. */ - int privilege_level; - - /** Period to wait after SRST. */ - uint32_t boot_time; - - /** Flag to indicate HSS steps into ISR or not */ - bool step_isr_enable; - - /** Flag to indicate register table is ready or not */ - bool init_arch_info_after_halted; - - /** Flag to indicate audio-extension is enabled or not */ - bool audio_enable; - - /** Flag to indicate fpu-extension is enabled or not */ - bool fpu_enable; - - /* Andes Core has mixed endian model. Instruction is always big-endian. - * Data may be big or little endian. Device registers may have different - * endian from data and instruction. */ - /** Endian of data memory */ - enum target_endianness data_endian; - - /** Endian of device registers */ - enum target_endianness device_reg_endian; - - /** Flag to indicate if auto convert software breakpoints to - * hardware breakpoints or not in ROM */ - bool auto_convert_hw_bp; - - /* Flag to indicate the target is attached by debugger or not */ - bool attached; - - /** Backpointer to the target. */ - struct target *target; - - void *arch_info; -}; - -struct nds32_reg { - int32_t num; - uint8_t value[8]; - struct target *target; - struct nds32 *nds32; - bool enable; -}; - -struct nds32_edm_operation { - uint32_t reg_no; - uint32_t value; -}; - -extern int nds32_config(struct nds32 *nds32); -extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32); -extern int nds32_full_context(struct nds32 *nds32); -extern int nds32_arch_state(struct target *target); -extern int nds32_add_software_breakpoint(struct target *target, - struct breakpoint *breakpoint); -extern int nds32_remove_software_breakpoint(struct target *target, - struct breakpoint *breakpoint); - -extern int nds32_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size, - enum target_register_class reg_class); - -extern int nds32_write_buffer(struct target *target, uint32_t address, - uint32_t size, const uint8_t *buffer); -extern int nds32_read_buffer(struct target *target, uint32_t address, - uint32_t size, uint8_t *buffer); -extern int nds32_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer); -extern int nds32_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer); - -extern int nds32_init_register_table(struct nds32 *nds32); -extern int nds32_init_memory_info(struct nds32 *nds32); -extern int nds32_restore_context(struct target *target); -extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value); -extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value); - -extern int nds32_edm_config(struct nds32 *nds32); -extern int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length); -extern int nds32_mmu(struct target *target, int *enabled); -extern int nds32_virtual_to_physical(struct target *target, target_addr_t address, - target_addr_t *physical); -extern int nds32_read_phys_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, uint8_t *buffer); -extern int nds32_write_phys_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, const uint8_t *buffer); -extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address); -extern int nds32_examine_debug_reason(struct nds32 *nds32); -extern int nds32_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints); -extern int nds32_target_state(struct nds32 *nds32, enum target_state *state); -extern int nds32_halt(struct target *target); -extern int nds32_poll(struct target *target); -extern int nds32_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution); -extern int nds32_assert_reset(struct target *target); -extern int nds32_init(struct nds32 *nds32); -extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info); -extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address, - uint32_t size, const uint8_t *buffer); -extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c); -extern int nds32_reset_halt(struct nds32 *nds32); -extern int nds32_login(struct nds32 *nds32); -extern int nds32_profiling(struct target *target, uint32_t *samples, - uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); - -/** Convert target handle to generic Andes target state handle. */ -static inline struct nds32 *target_to_nds32(struct target *target) -{ - assert(target); - return target->arch_info; -} - -/** */ -static inline struct aice_port_s *target_to_aice(struct target *target) -{ - assert(target); - return target->tap->priv; -} - -static inline bool is_nds32(struct nds32 *nds32) -{ - assert(nds32); - return nds32->common_magic == NDS32_COMMON_MAGIC; -} - -static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32) -{ - assert(nds32); - return nds32->max_interrupt_level == nds32->current_interrupt_level; -} - -#endif /* OPENOCD_TARGET_NDS32_H */ diff --git a/src/target/nds32_aice.c b/src/target/nds32_aice.c deleted file mode 100644 index 9d88adf143..0000000000 --- a/src/target/nds32_aice.c +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes technology. * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/log.h> -#include "nds32_aice.h" - -int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val) -{ - if (!aice->port->api->read_reg_64) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->read_reg_64(aice->coreid, num, val); -} - -int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val) -{ - if (!aice->port->api->write_reg_64) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->write_reg_64(aice->coreid, num, val); -} - -int aice_read_tlb(struct aice_port_s *aice, target_addr_t virtual_address, - target_addr_t *physical_address) -{ - if (!aice->port->api->read_tlb) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->read_tlb(aice->coreid, virtual_address, physical_address); -} - -int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address) -{ - if (!aice->port->api->cache_ctl) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->cache_ctl(aice->coreid, subtype, address); -} - -int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times) -{ - if (!aice->port->api->set_retry_times) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_retry_times(a_retry_times); -} - -int aice_program_edm(struct aice_port_s *aice, char *command_sequence) -{ - if (!aice->port->api->program_edm) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->program_edm(aice->coreid, command_sequence); -} - -int aice_set_command_mode(struct aice_port_s *aice, - enum aice_command_mode command_mode) -{ - if (!aice->port->api->set_command_mode) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_command_mode(command_mode); -} - -int aice_execute(struct aice_port_s *aice, uint32_t *instructions, - uint32_t instruction_num) -{ - if (!aice->port->api->execute) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->execute(aice->coreid, instructions, instruction_num); -} - -int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script) -{ - if (!aice->port->api->set_custom_srst_script) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_custom_srst_script(script); -} - -int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script) -{ - if (!aice->port->api->set_custom_trst_script) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_custom_trst_script(script); -} - -int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script) -{ - if (!aice->port->api->set_custom_restart_script) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_custom_restart_script(script); -} - -int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check) -{ - if (!aice->port->api->set_count_to_check_dbger) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->set_count_to_check_dbger(count_to_check); -} - -int aice_profiling(struct aice_port_s *aice, uint32_t interval, uint32_t iteration, - uint32_t reg_no, uint32_t *samples, uint32_t *num_samples) -{ - if (!aice->port->api->profiling) { - LOG_WARNING("Not implemented: %s", __func__); - return ERROR_FAIL; - } - - return aice->port->api->profiling(aice->coreid, interval, iteration, - reg_no, samples, num_samples); -} diff --git a/src/target/nds32_aice.h b/src/target/nds32_aice.h deleted file mode 100644 index 2a6c879ff4..0000000000 --- a/src/target/nds32_aice.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes technology. * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_AICE_H -#define OPENOCD_TARGET_NDS32_AICE_H - -#include <jtag/aice/aice_port.h> - -int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val); -int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val); -int aice_read_tlb(struct aice_port_s *aice, target_addr_t virtual_address, - target_addr_t *physical_address); -int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address); -int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times); -int aice_program_edm(struct aice_port_s *aice, char *command_sequence); -int aice_set_command_mode(struct aice_port_s *aice, - enum aice_command_mode command_mode); -int aice_execute(struct aice_port_s *aice, uint32_t *instructions, - uint32_t instruction_num); -int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script); -int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script); -int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script); -int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check); -int aice_profiling(struct aice_port_s *aice, uint32_t interval, uint32_t iteration, - uint32_t reg_no, uint32_t *samples, uint32_t *num_samples); - -static inline int aice_open(struct aice_port_s *aice, struct aice_port_param_s *param) -{ - return aice->port->api->open(param); -} - -static inline int aice_close(struct aice_port_s *aice) -{ - return aice->port->api->close(); -} - -static inline int aice_reset(struct aice_port_s *aice) -{ - return aice->port->api->reset(); -} - -static inline int aice_assert_srst(struct aice_port_s *aice, - enum aice_srst_type_s srst) -{ - return aice->port->api->assert_srst(aice->coreid, srst); -} - -static inline int aice_run(struct aice_port_s *aice) -{ - return aice->port->api->run(aice->coreid); -} - -static inline int aice_halt(struct aice_port_s *aice) -{ - return aice->port->api->halt(aice->coreid); -} - -static inline int aice_step(struct aice_port_s *aice) -{ - return aice->port->api->step(aice->coreid); -} - -static inline int aice_read_register(struct aice_port_s *aice, uint32_t num, - uint32_t *val) -{ - return aice->port->api->read_reg(aice->coreid, num, val); -} - -static inline int aice_write_register(struct aice_port_s *aice, uint32_t num, - uint32_t val) -{ - return aice->port->api->write_reg(aice->coreid, num, val); -} - -static inline int aice_read_debug_reg(struct aice_port_s *aice, uint32_t addr, - uint32_t *val) -{ - return aice->port->api->read_debug_reg(aice->coreid, addr, val); -} - -static inline int aice_write_debug_reg(struct aice_port_s *aice, uint32_t addr, - const uint32_t val) -{ - return aice->port->api->write_debug_reg(aice->coreid, addr, val); -} - -static inline int aice_read_mem_unit(struct aice_port_s *aice, uint32_t addr, - uint32_t size, uint32_t count, uint8_t *buffer) -{ - return aice->port->api->read_mem_unit(aice->coreid, addr, size, count, buffer); -} - -static inline int aice_write_mem_unit(struct aice_port_s *aice, uint32_t addr, - uint32_t size, uint32_t count, const uint8_t *buffer) -{ - return aice->port->api->write_mem_unit(aice->coreid, addr, size, count, buffer); -} - -static inline int aice_read_mem_bulk(struct aice_port_s *aice, uint32_t addr, - uint32_t length, uint8_t *buffer) -{ - return aice->port->api->read_mem_bulk(aice->coreid, addr, length, buffer); -} - -static inline int aice_write_mem_bulk(struct aice_port_s *aice, uint32_t addr, - uint32_t length, const uint8_t *buffer) -{ - return aice->port->api->write_mem_bulk(aice->coreid, addr, length, buffer); -} - -static inline int aice_idcode(struct aice_port_s *aice, uint32_t *idcode, - uint8_t *num_of_idcode) -{ - return aice->port->api->idcode(idcode, num_of_idcode); -} - -static inline int aice_state(struct aice_port_s *aice, - enum aice_target_state_s *state) -{ - return aice->port->api->state(aice->coreid, state); -} - -static inline int aice_set_jtag_clock(struct aice_port_s *aice, uint32_t a_clock) -{ - return aice->port->api->set_jtag_clock(a_clock); -} - -static inline int aice_memory_access(struct aice_port_s *aice, - enum nds_memory_access a_access) -{ - return aice->port->api->memory_access(aice->coreid, a_access); -} - -static inline int aice_memory_mode(struct aice_port_s *aice, - enum nds_memory_select mem_select) -{ - return aice->port->api->memory_mode(aice->coreid, mem_select); -} - -static inline int aice_set_data_endian(struct aice_port_s *aice, - enum aice_target_endian target_data_endian) -{ - return aice->port->api->set_data_endian(aice->coreid, target_data_endian); -} - -#endif /* OPENOCD_TARGET_NDS32_AICE_H */ diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c deleted file mode 100644 index 0e24009dba..0000000000 --- a/src/target/nds32_cmd.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/command.h> -#include "nds32.h" -#include "nds32_aice.h" -#include "nds32_disassembler.h" - -extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM]; -extern uint32_t nds32_edm_ops_num; - -static const char *const nds_memory_access_name[] = { - "BUS", - "CPU", -}; - -static const char *const nds_memory_select_name[] = { - "AUTO", - "MEM", - "ILM", - "DLM", -}; - -COMMAND_HANDLER(handle_nds32_dssim_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->step_isr_enable = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->step_isr_enable = false; - } - - command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target), - nds32->step_isr_enable); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_memory_access_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_memory *memory = &(nds32->memory); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "bus") == 0) - memory->access_channel = NDS_MEMORY_ACC_BUS; - else if (strcmp(CMD_ARGV[0], "cpu") == 0) - memory->access_channel = NDS_MEMORY_ACC_CPU; - else /* default access channel is NDS_MEMORY_ACC_CPU */ - memory->access_channel = NDS_MEMORY_ACC_CPU; - - LOG_DEBUG("memory access channel is changed to %s", - nds_memory_access_name[memory->access_channel]); - - aice_memory_access(aice, memory->access_channel); - } else { - command_print(CMD, "%s: memory access channel: %s", - target_name(target), - nds_memory_access_name[memory->access_channel]); - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_memory_mode_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - - if (nds32->edm.access_control == false) { - command_print(CMD, "%s does not support ACC_CTL. " - "Set memory mode to MEMORY", target_name(target)); - nds32->memory.mode = NDS_MEMORY_SELECT_MEM; - } else if (nds32->edm.direct_access_local_memory == false) { - command_print(CMD, "%s does not support direct access " - "local memory. Set memory mode to MEMORY", - target_name(target)); - nds32->memory.mode = NDS_MEMORY_SELECT_MEM; - - /* set to ACC_CTL */ - aice_memory_mode(aice, nds32->memory.mode); - } else { - if (strcmp(CMD_ARGV[0], "auto") == 0) { - nds32->memory.mode = NDS_MEMORY_SELECT_AUTO; - } else if (strcmp(CMD_ARGV[0], "mem") == 0) { - nds32->memory.mode = NDS_MEMORY_SELECT_MEM; - } else if (strcmp(CMD_ARGV[0], "ilm") == 0) { - if (nds32->memory.ilm_base == 0) - command_print(CMD, "%s does not support ILM", - target_name(target)); - else - nds32->memory.mode = NDS_MEMORY_SELECT_ILM; - } else if (strcmp(CMD_ARGV[0], "dlm") == 0) { - if (nds32->memory.dlm_base == 0) - command_print(CMD, "%s does not support DLM", - target_name(target)); - else - nds32->memory.mode = NDS_MEMORY_SELECT_DLM; - } - - /* set to ACC_CTL */ - aice_memory_mode(aice, nds32->memory.mode); - } - } - - command_print(CMD, "%s: memory mode: %s", - target_name(target), - nds_memory_select_name[nds32->memory.mode]); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_cache_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_cache *icache = &(nds32->memory.icache); - struct nds32_cache *dcache = &(nds32->memory.dcache); - int result; - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - - if (strcmp(CMD_ARGV[0], "invalidate") == 0) { - if ((dcache->line_size != 0) && (dcache->enable == true)) { - /* D$ write back */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Write back data cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Write back data cache...done", - target_name(target)); - - /* D$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Invalidate data cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Invalidate data cache...done", - target_name(target)); - } else { - if (dcache->line_size == 0) - command_print(CMD, "%s: No data cache", - target_name(target)); - else - command_print(CMD, "%s: Data cache disabled", - target_name(target)); - } - - if ((icache->line_size != 0) && (icache->enable == true)) { - /* I$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Invalidate instruction cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Invalidate instruction cache...done", - target_name(target)); - } else { - if (icache->line_size == 0) - command_print(CMD, "%s: No instruction cache", - target_name(target)); - else - command_print(CMD, "%s: Instruction cache disabled", - target_name(target)); - } - } else - command_print(CMD, "No valid parameter"); - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_icache_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_cache *icache = &(nds32->memory.icache); - int result; - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - - if (icache->line_size == 0) { - command_print(CMD, "%s: No instruction cache", - target_name(target)); - return ERROR_OK; - } - - if (strcmp(CMD_ARGV[0], "invalidate") == 0) { - if (icache->enable == true) { - /* I$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Invalidate instruction cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Invalidate instruction cache...done", - target_name(target)); - } else { - command_print(CMD, "%s: Instruction cache disabled", - target_name(target)); - } - } else if (strcmp(CMD_ARGV[0], "enable") == 0) { - uint32_t value; - nds32_get_mapped_reg(nds32, IR8, &value); - nds32_set_mapped_reg(nds32, IR8, value | 0x1); - } else if (strcmp(CMD_ARGV[0], "disable") == 0) { - uint32_t value; - nds32_get_mapped_reg(nds32, IR8, &value); - nds32_set_mapped_reg(nds32, IR8, value & ~0x1); - } else if (strcmp(CMD_ARGV[0], "dump") == 0) { - /* TODO: dump cache content */ - } else { - command_print(CMD, "%s: No valid parameter", target_name(target)); - } - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_dcache_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - struct aice_port_s *aice = target_to_aice(target); - struct nds32_cache *dcache = &(nds32->memory.dcache); - int result; - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - - if (dcache->line_size == 0) { - command_print(CMD, "%s: No data cache", target_name(target)); - return ERROR_OK; - } - - if (strcmp(CMD_ARGV[0], "invalidate") == 0) { - if (dcache->enable == true) { - /* D$ write back */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Write back data cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Write back data cache...done", - target_name(target)); - - /* D$ invalidate */ - result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0); - if (result != ERROR_OK) { - command_print(CMD, "%s: Invalidate data cache...failed", - target_name(target)); - return result; - } - - command_print(CMD, "%s: Invalidate data cache...done", - target_name(target)); - } else { - command_print(CMD, "%s: Data cache disabled", - target_name(target)); - } - } else if (strcmp(CMD_ARGV[0], "enable") == 0) { - uint32_t value; - nds32_get_mapped_reg(nds32, IR8, &value); - nds32_set_mapped_reg(nds32, IR8, value | 0x2); - } else if (strcmp(CMD_ARGV[0], "disable") == 0) { - uint32_t value; - nds32_get_mapped_reg(nds32, IR8, &value); - nds32_set_mapped_reg(nds32, IR8, value & ~0x2); - } else if (strcmp(CMD_ARGV[0], "dump") == 0) { - /* TODO: dump cache content */ - } else { - command_print(CMD, "%s: No valid parameter", target_name(target)); - } - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_auto_break_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->auto_convert_hw_bp = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->auto_convert_hw_bp = false; - } - - if (nds32->auto_convert_hw_bp) - command_print(CMD, "%s: convert sw break to hw break on ROM: on", - target_name(target)); - else - command_print(CMD, "%s: convert sw break to hw break on ROM: off", - target_name(target)); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_virtual_hosting_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->virtual_hosting = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->virtual_hosting = false; - } - - if (nds32->virtual_hosting) - command_print(CMD, "%s: virtual hosting: on", target_name(target)); - else - command_print(CMD, "%s: virtual hosting: off", target_name(target)); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_global_stop_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->global_stop = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->global_stop = false; - } - - if (nds32->global_stop) - LOG_INFO("%s: global stop: on", target_name(target)); - else - LOG_INFO("%s: global stop: off", target_name(target)); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_soft_reset_halt_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->soft_reset_halt = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->soft_reset_halt = false; - } - - if (nds32->soft_reset_halt) - LOG_INFO("%s: soft-reset-halt: on", target_name(target)); - else - LOG_INFO("%s: soft-reset-halt: off", target_name(target)); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_boot_time_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_login_edm_passcode_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - nds32->edm_passcode = strdup(CMD_ARGV[0]); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_login_edm_operation_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 1) { - - uint32_t misc_reg_no; - uint32_t data; - - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data); - - if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM) - return ERROR_FAIL; - - /* Just save the operation. Execute it in nds32_login() */ - nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no; - nds32_edm_ops[nds32_edm_ops_num].value = data; - nds32_edm_ops_num++; - } else - return ERROR_FAIL; - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->reset_halt_as_examine = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->reset_halt_as_examine = false; - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->keep_target_edm_ctl = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->keep_target_edm_ctl = false; - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_decode_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 1) { - - uint32_t addr; - uint32_t insn_count; - uint32_t opcode; - uint32_t read_addr; - uint32_t i; - struct nds32_instruction instruction; - - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count); - - read_addr = addr; - i = 0; - while (i < insn_count) { - if (nds32_read_opcode(nds32, read_addr, &opcode) != ERROR_OK) - return ERROR_FAIL; - if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK) - return ERROR_FAIL; - - command_print(CMD, "%s", instruction.text); - - read_addr += instruction.instruction_size; - i++; - } - } else if (CMD_ARGC == 1) { - - uint32_t addr; - uint32_t opcode; - struct nds32_instruction instruction; - - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); - - if (nds32_read_opcode(nds32, addr, &opcode) != ERROR_OK) - return ERROR_FAIL; - if (nds32_evaluate_opcode(nds32, opcode, addr, &instruction) != ERROR_OK) - return ERROR_FAIL; - - command_print(CMD, "%s", instruction.text); - } else - return ERROR_FAIL; - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_word_access_mem_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - if (CMD_ARGC > 0) { - if (strcmp(CMD_ARGV[0], "on") == 0) - nds32->word_access_mem = true; - if (strcmp(CMD_ARGV[0], "off") == 0) - nds32->word_access_mem = false; - } - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_query_target_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - command_print(CMD, "OCD"); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_query_endian_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - uint32_t value_psw; - nds32_get_mapped_reg(nds32, IR0, &value_psw); - - if (value_psw & 0x20) - command_print(CMD, "%s: BE", target_name(target)); - else - command_print(CMD, "%s: LE", target_name(target)); - - return ERROR_OK; -} - -COMMAND_HANDLER(handle_nds32_query_cpuid_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct nds32 *nds32 = target_to_nds32(target); - - if (!is_nds32(nds32)) { - command_print(CMD, "current target isn't an Andes core"); - return ERROR_FAIL; - } - - command_print(CMD, "CPUID: %s", target_name(target)); - - return ERROR_OK; -} - -static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - const char *cmd_name = Jim_GetString(argv[0], NULL); - - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - if (goi.argc < 3) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <address> <count> <data>", cmd_name); - return JIM_ERR; - } - - int e; - jim_wide address; - e = jim_getopt_wide(&goi, &address); - if (e != JIM_OK) - return e; - - jim_wide count; - e = jim_getopt_wide(&goi, &count); - if (e != JIM_OK) - return e; - - uint32_t *data = malloc(count * sizeof(uint32_t)); - if (!data) - return JIM_ERR; - - jim_wide i; - for (i = 0; i < count; i++) { - jim_wide tmp; - e = jim_getopt_wide(&goi, &tmp); - if (e != JIM_OK) { - free(data); - return e; - } - data[i] = (uint32_t)tmp; - } - - /* all args must be consumed */ - if (goi.argc != 0) { - free(data); - return JIM_ERR; - } - - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - int result; - - result = target_write_buffer(target, address, count * 4, (const uint8_t *)data); - - free(data); - - return result; -} - -static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - const char *cmd_name = Jim_GetString(argv[0], NULL); - - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - if (goi.argc < 3) { - Jim_SetResultFormatted(goi.interp, - "usage: %s # of pairs [<address> <data>]+", cmd_name); - return JIM_ERR; - } - - int e; - jim_wide num_of_pairs; - e = jim_getopt_wide(&goi, &num_of_pairs); - if (e != JIM_OK) - return e; - - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - struct aice_port_s *aice = target_to_aice(target); - int result; - uint32_t address; - uint32_t data; - jim_wide i; - - aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK); - for (i = 0; i < num_of_pairs; i++) { - jim_wide tmp; - e = jim_getopt_wide(&goi, &tmp); - if (e != JIM_OK) - break; - address = (uint32_t)tmp; - - e = jim_getopt_wide(&goi, &tmp); - if (e != JIM_OK) - break; - data = (uint32_t)tmp; - - result = target_write_buffer(target, address, 4, (const uint8_t *)&data); - if (result != ERROR_OK) - break; - } - aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL); - - /* all args must be consumed */ - if (goi.argc != 0) - return JIM_ERR; - - return ERROR_OK; -} - -static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - const char *cmd_name = Jim_GetString(argv[0], NULL); - - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - if (goi.argc < 2) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <address> <count>", cmd_name); - return JIM_ERR; - } - - int e; - jim_wide address; - e = jim_getopt_wide(&goi, &address); - if (e != JIM_OK) - return e; - - jim_wide count; - e = jim_getopt_wide(&goi, &count); - if (e != JIM_OK) - return e; - - /* all args must be consumed */ - if (goi.argc != 0) - return JIM_ERR; - - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - uint32_t *data = malloc(count * sizeof(uint32_t)); - int result; - result = target_read_buffer(target, address, count * 4, (uint8_t *)data); - char data_str[12]; - - jim_wide i; - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - for (i = 0; i < count; i++) { - sprintf(data_str, "0x%08" PRIx32 " ", data[i]); - Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL); - } - - free(data); - - return result; -} - -static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - const char *cmd_name = Jim_GetString(argv[0], NULL); - - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - if (goi.argc < 1) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <edm_sr_name>", cmd_name); - return JIM_ERR; - } - - int e; - const char *edm_sr_name; - int edm_sr_name_len; - e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len); - if (e != JIM_OK) - return e; - - /* all args must be consumed */ - if (goi.argc != 0) - return JIM_ERR; - - uint32_t edm_sr_number; - uint32_t edm_sr_value; - if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0) - edm_sr_number = NDS_EDM_SR_EDM_DTR; - else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0) - edm_sr_number = NDS_EDM_SR_EDMSW; - else - return ERROR_FAIL; - - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - struct aice_port_s *aice = target_to_aice(target); - char data_str[11]; - - aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value); - - sprintf(data_str, "0x%08" PRIx32, edm_sr_value); - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL); - - return ERROR_OK; -} - -static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv) -{ - const char *cmd_name = Jim_GetString(argv[0], NULL); - - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - if (goi.argc < 2) { - Jim_SetResultFormatted(goi.interp, - "usage: %s <edm_sr_name> <value>", cmd_name); - return JIM_ERR; - } - - int e; - const char *edm_sr_name; - int edm_sr_name_len; - e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len); - if (e != JIM_OK) - return e; - - jim_wide value; - e = jim_getopt_wide(&goi, &value); - if (e != JIM_OK) - return e; - - /* all args must be consumed */ - if (goi.argc != 0) - return JIM_ERR; - - uint32_t edm_sr_number; - if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0) - edm_sr_number = NDS_EDM_SR_EDM_DTR; - else - return ERROR_FAIL; - - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - struct aice_port_s *aice = target_to_aice(target); - - aice_write_debug_reg(aice, edm_sr_number, value); - - return ERROR_OK; -} - -static const struct command_registration nds32_query_command_handlers[] = { - { - .name = "target", - .handler = handle_nds32_query_target_command, - .mode = COMMAND_EXEC, - .usage = "", - .help = "reply 'OCD' for gdb to identify server-side is OpenOCD", - }, - { - .name = "endian", - .handler = handle_nds32_query_endian_command, - .mode = COMMAND_EXEC, - .usage = "", - .help = "query target endian", - }, - { - .name = "cpuid", - .handler = handle_nds32_query_cpuid_command, - .mode = COMMAND_EXEC, - .usage = "", - .help = "query CPU ID", - }, - - COMMAND_REGISTRATION_DONE -}; - -static const struct command_registration nds32_exec_command_handlers[] = { - { - .name = "dssim", - .handler = handle_nds32_dssim_command, - .mode = COMMAND_EXEC, - .usage = "['on'|'off']", - .help = "display/change $INT_MASK.DSSIM status", - }, - { - .name = "mem_access", - .handler = handle_nds32_memory_access_command, - .mode = COMMAND_EXEC, - .usage = "['bus'|'cpu']", - .help = "display/change memory access channel", - }, - { - .name = "mem_mode", - .handler = handle_nds32_memory_mode_command, - .mode = COMMAND_EXEC, - .usage = "['auto'|'mem'|'ilm'|'dlm']", - .help = "display/change memory mode", - }, - { - .name = "cache", - .handler = handle_nds32_cache_command, - .mode = COMMAND_EXEC, - .usage = "['invalidate']", - .help = "cache control", - }, - { - .name = "icache", - .handler = handle_nds32_icache_command, - .mode = COMMAND_EXEC, - .usage = "['invalidate'|'enable'|'disable'|'dump']", - .help = "icache control", - }, - { - .name = "dcache", - .handler = handle_nds32_dcache_command, - .mode = COMMAND_EXEC, - .usage = "['invalidate'|'enable'|'disable'|'dump']", - .help = "dcache control", - }, - { - .name = "auto_break", - .handler = handle_nds32_auto_break_command, - .mode = COMMAND_EXEC, - .usage = "['on'|'off']", - .help = "convert software breakpoints to hardware breakpoints if needed", - }, - { - .name = "virtual_hosting", - .handler = handle_nds32_virtual_hosting_command, - .mode = COMMAND_ANY, - .usage = "['on'|'off']", - .help = "turn on/off virtual hosting", - }, - { - .name = "global_stop", - .handler = handle_nds32_global_stop_command, - .mode = COMMAND_ANY, - .usage = "['on'|'off']", - .help = "turn on/off global stop. After turning on, every load/store " - "instructions will be stopped to check memory access.", - }, - { - .name = "soft_reset_halt", - .handler = handle_nds32_soft_reset_halt_command, - .mode = COMMAND_ANY, - .usage = "['on'|'off']", - .help = "as issuing rest-halt, to use soft-reset-halt or not." - "the feature is for backward-compatible.", - }, - { - .name = "boot_time", - .handler = handle_nds32_boot_time_command, - .mode = COMMAND_CONFIG, - .usage = "milliseconds", - .help = "set the period to wait after srst.", - }, - { - .name = "login_edm_passcode", - .handler = handle_nds32_login_edm_passcode_command, - .mode = COMMAND_CONFIG, - .usage = "passcode", - .help = "set EDM passcode for secure MCU debugging.", - }, - { - .name = "login_edm_operation", - .handler = handle_nds32_login_edm_operation_command, - .mode = COMMAND_CONFIG, - .usage = "misc_reg_no value", - .help = "add EDM operations for secure MCU debugging.", - }, - { - .name = "reset_halt_as_init", - .handler = handle_nds32_reset_halt_as_init_command, - .mode = COMMAND_CONFIG, - .usage = "['on'|'off']", - .help = "reset halt as openocd init.", - }, - { - .name = "keep_target_edm_ctl", - .handler = handle_nds32_keep_target_edm_ctl_command, - .mode = COMMAND_CONFIG, - .usage = "['on'|'off']", - .help = "Backup/Restore target EDM_CTL register.", - }, - { - .name = "decode", - .handler = handle_nds32_decode_command, - .mode = COMMAND_EXEC, - .usage = "address icount", - .help = "decode instruction.", - }, - { - .name = "word_access_mem", - .handler = handle_nds32_word_access_mem_command, - .mode = COMMAND_ANY, - .usage = "['on'|'off']", - .help = "Always use word-aligned address to access memory.", - }, - { - .name = "bulk_write", - .jim_handler = jim_nds32_bulk_write, - .mode = COMMAND_EXEC, - .help = "Write multiple 32-bit words to target memory", - .usage = "address count data", - }, - { - .name = "multi_write", - .jim_handler = jim_nds32_multi_write, - .mode = COMMAND_EXEC, - .help = "Write multiple addresses/words to target memory", - .usage = "num_of_pairs [address data]+", - }, - { - .name = "bulk_read", - .jim_handler = jim_nds32_bulk_read, - .mode = COMMAND_EXEC, - .help = "Read multiple 32-bit words from target memory", - .usage = "address count", - }, - { - .name = "read_edmsr", - .jim_handler = jim_nds32_read_edm_sr, - .mode = COMMAND_EXEC, - .help = "Read EDM system register", - .usage = "['edmsw'|'edm_dtr']", - }, - { - .name = "write_edmsr", - .jim_handler = jim_nds32_write_edm_sr, - .mode = COMMAND_EXEC, - .help = "Write EDM system register", - .usage = "['edm_dtr'] value", - }, - { - .name = "query", - .mode = COMMAND_EXEC, - .help = "Andes query command group", - .usage = "", - .chain = nds32_query_command_handlers, - }, - - COMMAND_REGISTRATION_DONE -}; - -const struct command_registration nds32_command_handlers[] = { - { - .name = "nds", - .mode = COMMAND_ANY, - .help = "Andes command group", - .usage = "", - .chain = nds32_exec_command_handlers, - }, - COMMAND_REGISTRATION_DONE -}; diff --git a/src/target/nds32_cmd.h b/src/target/nds32_cmd.h deleted file mode 100644 index 15932438c0..0000000000 --- a/src/target/nds32_cmd.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_CMD_H -#define OPENOCD_TARGET_NDS32_CMD_H - -#include <helper/command.h> - -extern const struct command_registration nds32_command_handlers[]; - -#endif /* OPENOCD_TARGET_NDS32_CMD_H */ diff --git a/src/target/nds32_disassembler.c b/src/target/nds32_disassembler.c deleted file mode 100644 index 7cdf3a712c..0000000000 --- a/src/target/nds32_disassembler.c +++ /dev/null @@ -1,3847 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/log.h> -#include <target/target.h> -#include "nds32_disassembler.h" - -static const int enable4_bits[] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4}; - -int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value) -{ - struct target *target = nds32->target; - uint8_t value_buf[4]; - - if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; - } - - int retval = target_read_buffer(target, address, 4, value_buf); - - if (retval == ERROR_OK) { - /* instructions are always big-endian */ - *value = be_to_h_u32(value_buf); - - LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "", - address, - *value); - } else { - *value = 0x0; - LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", - address); - } - - return retval; -} - -static int nds32_parse_type_0(uint32_t opcode, int32_t *imm) -{ - *imm = opcode & 0x1FFFFFF; - - return ERROR_OK; -} - -static int nds32_parse_type_1(uint32_t opcode, uint8_t *rt, int32_t *imm) -{ - *rt = (opcode >> 20) & 0x1F; - *imm = opcode & 0xFFFFF; - - return ERROR_OK; -} - -static int nds32_parse_type_2(uint32_t opcode, uint8_t *rt, uint8_t *ra, int32_t *imm) -{ - *rt = (opcode >> 20) & 0x1F; - *ra = (opcode >> 15) & 0x1F; - *imm = opcode & 0x7FFF; - - return ERROR_OK; -} - -static int nds32_parse_type_3(uint32_t opcode, uint8_t *rt, uint8_t *ra, - uint8_t *rb, int32_t *imm) -{ - *rt = (opcode >> 20) & 0x1F; - *ra = (opcode >> 15) & 0x1F; - *rb = (opcode >> 10) & 0x1F; - *imm = opcode & 0x3FF; - - return ERROR_OK; -} - -static int nds32_parse_type_4(uint32_t opcode, uint8_t *rt, uint8_t *ra, - uint8_t *rb, uint8_t *rd, uint8_t *sub_opc) -{ - *rt = (opcode >> 20) & 0x1F; - *ra = (opcode >> 15) & 0x1F; - *rb = (opcode >> 10) & 0x1F; - *rd = (opcode >> 5) & 0x1F; - *sub_opc = opcode & 0x1F; - - return ERROR_OK; -} - -/* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */ -static int nds32_parse_group_0_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, - struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 0: /* LBI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 1: /* LHI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 2: /* LWI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 4: /* LBI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 5: /* LHI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 6: /* LWI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32 "", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_1_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 0: /* SBI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 1: /* SHI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 2: /* SWI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 4: /* SBI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 5: /* SHI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 6: /* SWI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_2_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 0: /* LBSI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 1: /* LHSI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 3: { /* DPREFI */ - uint8_t sub_type; - nds32_parse_type_2(opcode, &sub_type, &(instruction->info.ra), - &(instruction->info.imm)); - instruction->info.sub_opc = sub_type & 0xF; - instruction->type = NDS32_INSN_MISC; - if (sub_type & 0x10) { /* DPREFI.d */ - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 17) >> 14; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDPREFI.d\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.sub_opc, - instruction->info.ra, instruction->info.imm); - } else { /* DPREFI.w */ - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 17) >> 15; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDPREFI.w\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]", - address, - opcode, instruction->info.sub_opc, - instruction->info.ra, instruction->info.imm); - } - } - break; - case 4: /* LBSI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 5: /* LHSI.bi */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 6: /* LBGP */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - if ((instruction->info.imm >> 19) & 0x1) { /* LBSI.gp */ - instruction->info.imm = (instruction->info.imm << 13) >> 13; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* LBI.gp */ - instruction->info.imm = (instruction->info.imm << 13) >> 13; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_mem(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - uint32_t sub_opcode = opcode & 0x3F; - uint32_t val_ra, val_rb; - switch (sub_opcode >> 3) { - case 0: - switch (sub_opcode & 0x7) { - case 0: /* LB */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 1: /* LH */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 2: /* LW */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 4: /* LB.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, - instruction->info.ra, instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 5: /* LH.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 6: /* LW.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - case 1: - switch (sub_opcode & 0x7) { - case 0: /* SB */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, - instruction->info.ra, instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 1: /* SH */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 2: /* SW */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, - instruction->info.ra, instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 4: /* SB.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 5: /* SH.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 6: /* SW.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - case 2: - switch (sub_opcode & 0x7) { - case 0: /* LBS */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, - instruction->info.ra, instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 1: /* LHS */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 3: /* DPREF */ - nds32_parse_type_3(opcode, &(instruction->info.sub_opc), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDPREF\t#%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<#%" PRId32 ")]", - address, - opcode, instruction->info.sub_opc, - instruction->info.ra, instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 4: /* LBS.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 5: /* LHS.bi */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - case 3: - switch (sub_opcode & 0x7) { - case 0: /* LLW */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 1: /* SCW */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSCW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - case 4: - switch (sub_opcode & 0x7) { - case 0: /* LBUP */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 2: /* LWUP */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - case 5: - switch (sub_opcode & 0x7) { - case 0: /* SBUP */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - case 2: /* SWUP */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra); - nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb); - instruction->access_start = val_ra + - (val_rb << ((instruction->info.imm >> 8) & 0x3)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - (instruction->info.imm >> 8) & 0x3); - break; - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_calculate_lsmw_access_range(struct nds32 *nds32, - struct nds32_instruction *instruction) -{ - uint8_t ba; - uint8_t id; - uint8_t enable4; - - enable4 = (instruction->info.imm >> 6) & 0xF; - ba = (instruction->info.imm >> 4) & 0x1; - id = (instruction->info.imm >> 3) & 0x1; - - if (ba) { - nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start)); - if (id) { /* decrease */ - /* access_end is the (last_element+1), so no need to minus 4 */ - /* instruction->access_end -= 4; */ - instruction->access_end = instruction->access_start; - } else { /* increase */ - instruction->access_start += 4; - } - } else { - nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start)); - instruction->access_end = instruction->access_start - 4; - } - - if (id) { /* decrease */ - instruction->access_start = instruction->access_end - - 4 * (instruction->info.rd - instruction->info.rb + 1); - instruction->access_start -= (4 * enable4_bits[enable4]); - } else { /* increase */ - instruction->access_end = instruction->access_start + - 4 * (instruction->info.rd - instruction->info.rb + 1); - instruction->access_end += (4 * enable4_bits[enable4]); - } - - return ERROR_OK; -} - -static int nds32_parse_lsmw(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - if (opcode & 0x20) { /* SMW, SMWA, SMWZB */ - switch (opcode & 0x3) { - /* TODO */ - case 0: /* SMW */ - /* use rd as re */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_calculate_lsmw_access_range(nds32, instruction); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - case 1: /* SMWA */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_calculate_lsmw_access_range(nds32, instruction); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - case 2: /* SMWZB */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - /* TODO: calculate access_start/access_end */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } else { /* LMW, LMWA, LMWZB */ - switch (opcode & 0x3) { - case 0: /* LMW */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_calculate_lsmw_access_range(nds32, instruction); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - case 1: /* LMWA */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_calculate_lsmw_access_range(nds32, instruction); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - case 2: /* LMWZB */ - nds32_parse_type_3(opcode, &(instruction->info.rb), - &(instruction->info.ra), - &(instruction->info.rd), &(instruction->info.imm)); - instruction->type = NDS32_INSN_LOAD_STORE; - /* TODO: calculate access_start/access_end */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rb, instruction->info.ra, - instruction->info.rd, - (instruction->info.imm >> 6) & 0xF); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int nds32_parse_hwgp(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - switch ((opcode >> 18) & 0x3) { - case 0: /* LHI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHI.gp\t$r%" PRIu8 ",[#%" PRId32"]", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 1: /* LHSI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLHSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 2: /* SHI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSHI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 3: - instruction->type = NDS32_INSN_LOAD_STORE; - if ((opcode >> 17) & 0x1) { /* SWI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 15) >> 13; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* LWI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 15) >> 13; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tLWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } - - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_sbgp(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - switch ((opcode >> 19) & 0x1) { - case 0: /* SBI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */ - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R29, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 1: /* ADDI.gp */ - nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */ - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADDI.gp\t$r%" PRIu8 ",#%" PRId32 "", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_3_insn(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 4: /* MEM */ - nds32_parse_mem(nds32, opcode, address, instruction); - break; - case 5: /* LSMW */ - nds32_parse_lsmw(nds32, opcode, address, instruction); - break; - case 6: /* HWGP */ - nds32_parse_hwgp(nds32, opcode, address, instruction); - break; - case 7: /* SBGP */ - nds32_parse_sbgp(nds32, opcode, address, instruction); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_alu_1(uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - switch (opcode & 0x1F) { - case 0: /* ADD */ - nds32_parse_type_3(opcode, &(instruction->info.rt), &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADD_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 1: /* SUB */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSUB_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 2: /* AND */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAND_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 3: /* XOR */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tXOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 4: /* OR */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 5: /* NOR */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tNOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 6: /* SLT */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLT\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 7: /* SLTS */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLTS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 8: { /* SLLI */ - uint8_t imm; - int32_t sub_op; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &sub_op); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 9: { /* SRLI */ - uint8_t imm; - int32_t sub_op; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &sub_op); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSRLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 10: { /* SRAI */ - uint8_t imm; - int32_t sub_op; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &sub_op); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSRAI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 11: { /* ROTRI */ - uint8_t imm; - int32_t sub_op; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &sub_op); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tROTRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 12: { /* SLL */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 13: { /* SRL */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSRL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 14: { /* SRA */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSRA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 15: { /* ROTR */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tROTR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 16: { /* SEB */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSEB\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - } - break; - case 17: { /* SEH */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSEH\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - } - break; - case 18: /* BITC */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBITC\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 19: { /* ZEH */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tZEH\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - } - break; - case 20: { /* WSBH */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tWSBH\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - } - break; - case 21: /* OR_SRLI */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 22: { /* DIVSR */ - nds32_parse_type_4(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.rd), - &(instruction->info.sub_opc)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDIVSR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.rd); - } - break; - case 23: { /* DIVR */ - nds32_parse_type_4(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.rd), - &(instruction->info.sub_opc)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDIVR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.rd); - } - break; - case 24: { /* SVA */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSVA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 25: { /* SVS */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSVS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 26: { /* CMOVZ */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCMOVZ\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 27: { /* CMOVN */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCMOVN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 28: /* ADD_SRLI */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADD_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 29: /* SUB_SRLI */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSUB_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 30: /* AND_SRLI */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAND_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 31: /* XOR_SRLI */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - instruction->info.imm = (instruction->info.imm >> 5) & 0x1F; - if (instruction->info.imm) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tXOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb, - instruction->info.imm); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_alu_2(uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - switch (opcode & 0x3F) { - case 0: /* MAX */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMAX\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 1: /* MIN */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMIN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 2: /* AVE */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAVE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 3: /* ABS */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tAVE\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 4: { /* CLIPS */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCLIPS\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 5: { /* CLIP */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCLIP\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 6: /* CLO */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCLO\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 7: /* CLZ */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tCLZ\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 8: { /* BSET */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBSET\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 9: { /* BCLR */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBCLR\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 10: { /* BTGL */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBTGL\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 11: { /* BTST */ - uint8_t imm; - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &imm, &(instruction->info.imm)); - instruction->info.imm = imm; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBTST\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - case 12: /* BSE */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBSE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 13: /* BSP */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBSP\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 14: /* FFB */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tFFB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 15: /* FFMISM */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tFFMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 23: /* FFZMISM */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tFFZMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 32: /* MFUSR */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_RESOURCE_ACCESS; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMFUSR\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, - (instruction->info.imm >> 10) & 0x3FF); - break; - case 33: /* MTUSR */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_RESOURCE_ACCESS; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMTUSR\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, - (instruction->info.imm >> 10) & 0x3FF); - break; - case 36: /* MUL */ - nds32_parse_type_3(opcode, &(instruction->info.rt), - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMUL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - break; - case 40: { /* MULTS64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMULTS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 41: { /* MULT64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, - &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMULT64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 42: { /* MADDS64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMADDS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 43: { /* MADD64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMADD64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 44: { /* MSUBS64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMSUBS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 45: { /* MSUB64 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMSUB64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 46: { /* DIVS */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDIVS\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 47: { /* DIV */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tDIV\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 49: { /* MULT32 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMULT32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 51: { /* MADD32 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMADD32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - case 53: { /* MSUB32 */ - uint8_t dt_val; - nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra), - &(instruction->info.rb), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMSUB32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra, - instruction->info.rb); - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_4_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 0: /* ALU_1 */ - nds32_parse_alu_1(opcode, address, instruction); - break; - case 1: /* ALU_2 */ - nds32_parse_alu_2(opcode, address, instruction); - break; - case 2: /* MOVI */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 12) >> 12; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMOVI\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 3: /* SETHI */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSETHI\t$r%" PRIu8 ",0x%8.8" PRIx32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 4: /* JI */ - nds32_parse_type_0(opcode, &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 8) >> 8; - instruction->type = NDS32_INSN_JUMP_BRANCH; - if ((instruction->info.imm >> 24) & 0x1) { /* JAL */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJAL\t#%" PRId32, - address, - opcode, instruction->info.imm); - } else { /* J */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJ\t#%" PRId32, - address, - opcode, instruction->info.imm); - } - break; - case 5: { /* JREG */ - int32_t imm; - nds32_parse_type_0(opcode, &imm); - instruction->info.rb = (imm >> 10) & 0x1F; - instruction->type = NDS32_INSN_JUMP_BRANCH; - switch (imm & 0x1F) { - /* TODO */ - case 0: /* JR */ - if (imm & 0x20) { /* RET */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tRET\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - } else { /* JR */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJR\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - } - break; - case 1: /* JRAL */ - instruction->info.rt = (imm >> 20) & 0x1F; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJRAL\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.rb); - break; - case 2: /* JRNEZ */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJRNEZ\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - break; - case 3: /* JRALNEZ */ - instruction->info.rt = (imm >> 20) & 0x1F; - if (instruction->info.rt == R30) - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJRALNEZ\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - else - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tJRALNEZ\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, - instruction->info.rt, - instruction->info.rb); - break; - } - } - break; - case 6: { /* BR1 */ - int32_t imm; - - nds32_parse_type_0(opcode, &imm); - instruction->type = NDS32_INSN_JUMP_BRANCH; - if ((imm >> 14) & 0x1) { /* BNE */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 18) >> 18; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBNE\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } else { /* BEQ */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - /* sign-extend */ - instruction->info.imm = (instruction->info.imm << 18) >> 18; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBEQ\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, - instruction->info.ra, - instruction->info.imm); - } - } - break; - case 7: { /* BR2 */ - int32_t imm; - - nds32_parse_type_0(opcode, &imm); - instruction->type = NDS32_INSN_JUMP_BRANCH; - switch ((imm >> 16) & 0xF) { - case 2: /* BEQZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBEQZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 3: /* BNEZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBNEZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 4: /* BGEZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBGEZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 5: /* BLTZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBLTZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 6: /* BGTZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBGTZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 7: /* BLEZ */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBLEZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 12: /* BGEZAL */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBGEZAL\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 13: /* BLTZAL */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 16) >> 16; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBLTZAL\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - } - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_5_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 0: /* ADDI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tADDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 1: /* SUBRI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSUBRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 2: /* ANDI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tANDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 3: /* XORI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tXORI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 4: /* ORI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tORI\t$r%" PRIu8 ",$r%" PRIu8 ",0x%8.8" PRIx32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 6: /* SLTI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLTI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 7: /* SLTSI */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */ - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSLTSI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_6_insn(struct nds32 *nds32, uint32_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - uint8_t opc_6; - - opc_6 = instruction->info.opc_6; - - switch (opc_6 & 0x7) { - case 2: { /* MISC */ - int32_t imm; - uint8_t sub_opc; - - nds32_parse_type_0(opcode, &imm); - - sub_opc = imm & 0x1F; - switch (sub_opc) { - case 0: /* STANDBY */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSTANDBY\t#%" PRIu32, - address, - opcode, (opcode >> 5) & 0x3); - break; - case 1: /* CCTL */ - /* TODO */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCCTL", - address, - opcode); - break; - case 2: /* MFSR */ - nds32_parse_type_1(opcode, &(instruction->info.rt), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_RESOURCE_ACCESS; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMFSR\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, - (instruction->info.imm >> 10) & 0x3FF); - break; - case 3: /* MTSR */ - nds32_parse_type_1(opcode, &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_RESOURCE_ACCESS; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMTSR\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.ra, - (instruction->info.imm >> 10) & 0x3FF); - break; - case 4: /* IRET */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tIRET", - address, - opcode); - break; - case 5: /* TRAP */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tTRAP\t#%" PRId32, - address, - opcode, (imm >> 5) & 0x7FFF); - break; - case 6: /* TEQZ */ - nds32_parse_type_1(opcode, &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tTEQZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.ra, - (instruction->info.imm >> 5) & 0x7FFF); - break; - case 7: /* TNEZ */ - nds32_parse_type_1(opcode, &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tTNEZ\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.ra, - (instruction->info.imm >> 5) & 0x7FFF); - break; - case 8: /* DSB */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB", - address, - opcode); - break; - case 9: /* ISB */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB", - address, - opcode); - break; - case 10: /* BREAK */ - instruction->type = NDS32_INSN_MISC; - instruction->info.sub_opc = imm & 0x1F; - instruction->info.imm = (imm >> 5) & 0x7FFF; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tBREAK\t#%" PRId32, - address, - opcode, instruction->info.imm); - break; - case 11: /* SYSCALL */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tSYSCALL\t#%" PRId32, - address, - opcode, (imm >> 5) & 0x7FFF); - break; - case 12: /* MSYNC */ - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tMSYNC\t#%" PRId32, - address, - opcode, (imm >> 5) & 0x7); - break; - case 13: /* ISYNC */ - nds32_parse_type_1(opcode, &(instruction->info.ra), - &(instruction->info.imm)); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 - "\tISYNC\t$r%" PRIu8, - address, - opcode, instruction->info.ra); - break; - case 14: /* TLBOP */ - /* TODO */ - nds32_parse_type_2(opcode, &(instruction->info.rt), - &(instruction->info.ra), &(instruction->info.imm)); - instruction->type = NDS32_INSN_RESOURCE_ACCESS; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tTLBOP", - address, - opcode); - break; - } - - break; - } - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static uint32_t field_mask[9] = { - 0x0, - 0x1, - 0x3, - 0x7, - 0xF, - 0x1F, - 0x3F, - 0x7F, - 0xFF, -}; - -static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length) -{ - if (length > 0 && length < 9) - return (opcode >> start) & field_mask[length]; - - return 0; -} - -static int nds32_parse_group_0_insn_16(struct nds32 *nds32, uint16_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - switch ((opcode >> 10) & 0x7) { - case 0: /* MOV55 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5); - instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tMOV55\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 1: /* MOVI55 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->info.imm = (instruction->info.imm << 27) >> 27; - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tMOVI55\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 2: /* ADD45, SUB45 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD45 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADD45\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.rb); - } else { /* SUB45 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSUB45\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.rb); - } - - break; - case 3: /* ADDI45, SUBI45 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI45 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADDI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* SUBI45 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSUBI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - case 4: /* SRAI45, SRLI45 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SRAI45 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSRAI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* SRLI45 */ - if ((instruction->info.rt == 0) && (instruction->info.imm == 0)) { - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 "\t\tNOP", - address, - opcode); - } else { - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSRLI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } - } - break; - case 5: - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SLLI333 */ - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSLLI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } else { - instruction->info.sub_opc = nds32_extract_field_8u(opcode, 0, 3); - switch (instruction->info.sub_opc) { - case 0: /* ZEB33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tZEB33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 1: /* ZEH33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tZEH33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 2: /* SEB33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSEB33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 3: /* SEH33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSEH33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 4: /* XLSB33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tXLSB33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 5: /* XLLB33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tXLLB33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 6: /* BMSKI33 */ - instruction->info.ra = 0; - instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBMSKI33\t$r%" PRIu8 ",$r%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 7: /* FEXTI33 */ - instruction->info.ra = 0; - instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3); - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tFEXTI33\t$r%" PRIu8 ",$r%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 - "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } - break; - case 6: /* ADD333, SUB333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.rb = nds32_extract_field_8u(opcode, 0, 3); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD333 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADD333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } else { /* SUB333 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSUB333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.rb); - } - break; - case 7: /* ADDI333, SUBI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3); - instruction->type = NDS32_INSN_DATA_PROC; - if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI333 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADDI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } else { /* SUBI333 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSUBI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_1_insn_16(struct nds32 *nds32, uint16_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - switch ((opcode >> 9) & 0xF) { - case 0: /* LWI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 1: /* LWI333.BI */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm << 2); - break; - case 2: /* LHI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 3: /* LBI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLBI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 4: /* SWI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 5: /* SWI333.BI */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 6: /* SHI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 2; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 7: /* SBI333 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 1; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]", - address, - opcode, instruction->info.rt, instruction->info.ra, - instruction->info.imm); - break; - case 8: /* ADDRI36.SP */ - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 6) << 2; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADDRI36.SP\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 9: /* LWI45.FE */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->info.imm -= 32; - instruction->info.imm <<= 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R8, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI45.FE\t$r%" PRIu8 ",[#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 10: /* LWI450 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI450\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 11: /* SWI450 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, instruction->info.ra, - &(instruction->access_start)); - instruction->access_end = instruction->access_start + 4; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSWI450\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 12: - case 13: - case 14: - case 15: /* LWI37, SWI37 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R28, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* SWI37 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - default: /* ERROR */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_parse_group_2_insn_16(struct nds32 *nds32, uint16_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - switch ((opcode >> 11) & 0x3) { - case 0: /* BEQZ38 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8); - instruction->info.imm = (instruction->info.imm << 24) >> 24; - instruction->type = NDS32_INSN_JUMP_BRANCH; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBEQZ38\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 1: /* BNEZ38 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8); - instruction->info.imm = (instruction->info.imm << 24) >> 24; - instruction->type = NDS32_INSN_JUMP_BRANCH; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBNEZ38\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 2: /* BEQS38,J8 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8); - instruction->info.imm = (instruction->info.imm << 24) >> 24; - instruction->type = NDS32_INSN_JUMP_BRANCH; - if (instruction->info.rt == 5) { /* J8 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tJ8\t#%" PRId32, - address, - opcode, instruction->info.imm); - } else { /* BEQS38 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBEQS38\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - case 3: /* BNES38, JR5, RET5, JRAL5 */ - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8); - instruction->info.imm = (instruction->info.imm << 24) >> 24; - instruction->type = NDS32_INSN_JUMP_BRANCH; - if (instruction->info.rt == 5) { - instruction->info.imm = 0; - instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5); - switch (nds32_extract_field_8u(opcode, 5, 3)) { - case 0: /* JR5 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tJR5\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - break; - case 1: /* JRAL5 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tJRAL5\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - break; - case 2: /* EX9.IT */ - instruction->info.rb = 0; - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - /* TODO: implement real instruction semantics */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tEX9.IT\t#%" PRId32, - address, - opcode, instruction->info.imm); - break; - case 4: /* RET5 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tRET5\t$r%" PRIu8, - address, - opcode, instruction->info.rb); - break; - case 5: /* ADD5.PC */ - instruction->info.rt = 0; - instruction->info.rt = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADD5.PC\t$r%" PRIu8, - address, - opcode, instruction->info.rt); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 - "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } else { /* BNES38 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBNES38\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - } - - return ERROR_OK; -} - -static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode, - uint32_t address, struct nds32_instruction *instruction) -{ - switch ((opcode >> 11) & 0x3) { - case 0: - switch ((opcode >> 9) & 0x3) { - case 0: /* SLTS45 */ - instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSLTS45\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.ra, instruction->info.rb); - break; - case 1: /* SLT45 */ - instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSLT45\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.ra, instruction->info.rb); - break; - case 2: /* SLTSI45 */ - instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSLTSI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.ra, instruction->info.imm); - break; - case 3: /* SLTI45 */ - instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5); - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSLTI45\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.ra, instruction->info.imm); - break; - } - break; - case 1: - switch ((opcode >> 9) & 0x3) { - case 0: - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8); - instruction->info.imm = (instruction->info.imm << 24) >> 24; - instruction->type = NDS32_INSN_JUMP_BRANCH; - if (nds32_extract_field_8u(opcode, 8, 1) == 0) { /* BEQZS8 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBEQZS8\t#%" PRId32, - address, - opcode, instruction->info.imm); - } else { /* BNEZS8 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBNEZS8\t#%" PRId32, - address, - opcode, instruction->info.imm); - } - break; - case 1: /* BREAK16 */ - if (((opcode >> 5) & 0xF) == 0) { - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tBREAK16\t#%" PRId16, - address, - opcode, (int16_t)(opcode & 0x1F)); - } else { /* EX9.IT */ - instruction->type = NDS32_INSN_MISC; - /* TODO: implement real instruction semantics */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tEX9.IT\t#%" PRId16, - address, - opcode, (int16_t)(opcode & 0x1FF)); - } - break; - case 2: /* ADDI10S */ - case 3: - instruction->info.imm = opcode & 0x3FF; - instruction->info.imm = (instruction->info.imm << 22) >> 22; - instruction->type = NDS32_INSN_DATA_PROC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tADDI10.SP\t#%" PRId32, - address, - opcode, instruction->info.imm); - break; - } - break; - case 2: - instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3); - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2; - instruction->type = NDS32_INSN_LOAD_STORE; - nds32_get_mapped_reg(nds32, R31, &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = instruction->access_start + 4; - if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37.SP */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tLWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } else { /* SWI37.SP */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tSWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]", - address, - opcode, instruction->info.rt, instruction->info.imm); - } - break; - case 3: - switch ((opcode >> 9) & 0x3) { - case 0: /* IFCALL9 */ - instruction->info.imm = opcode & 0x1FF; - instruction->type = NDS32_INSN_JUMP_BRANCH; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tIFCALL9\t#%" PRId32 "", - address, - opcode, instruction->info.imm); - break; - case 1: /* MOVPI45 */ - instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5) + 16; - instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4); - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tMOVPI45\t$r%" PRIu8 ",#%" PRId32 "", - address, - opcode, instruction->info.rt, instruction->info.imm); - break; - case 2: /* PUSH25, POP25, MOVD44 */ - switch ((opcode >> 7) & 0x3) { - case 0: /* PUSH25 */ - { - uint8_t re; - uint8_t gpr_count; - - instruction->type = NDS32_INSN_LOAD_STORE; - instruction->info.imm = - nds32_extract_field_8u(opcode, 0, 5) << 3; - re = nds32_extract_field_8u(opcode, 5, 2); - - if (re == 0) - re = 6; - else if (re == 1) - re = 8; - else if (re == 2) - re = 10; - else if (re == 3) - re = 14; - - instruction->info.rd = re; - /* GPRs list: R6 ~ Re and fp, gp, lp */ - gpr_count = 3 + (re - 5); - - nds32_get_mapped_reg(nds32, R31, - &(instruction->access_end)); - instruction->access_start = - instruction->access_end - (gpr_count * 4); - - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tPUSH25\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rd, - instruction->info.imm); - } - break; - case 1: /* POP25 */ - { - uint8_t re; - uint8_t gpr_count; - - instruction->type = NDS32_INSN_LOAD_STORE; - instruction->info.imm = - nds32_extract_field_8u(opcode, 0, 5) << 3; - re = nds32_extract_field_8u(opcode, 5, 2); - - if (re == 0) - re = 6; - else if (re == 1) - re = 8; - else if (re == 2) - re = 10; - else if (re == 3) - re = 14; - - instruction->info.rd = re; - /* GPRs list: R6 ~ Re and fp, gp, lp */ - gpr_count = 3 + (re - 5); - - nds32_get_mapped_reg(nds32, R31, - &(instruction->access_start)); - instruction->access_start += instruction->info.imm; - instruction->access_end = - instruction->access_start + (gpr_count * 4); - - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tPOP25\t$r%" PRIu8 ",#%" PRId32, - address, - opcode, instruction->info.rd, - instruction->info.imm); - } - break; - case 2: /* MOVD44 */ - case 3: - instruction->info.ra = - nds32_extract_field_8u(opcode, 0, 4) * 2; - instruction->info.rt = - nds32_extract_field_8u(opcode, 4, 4) * 2; - instruction->type = NDS32_INSN_MISC; - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tMOVD44\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - } - break; - case 3: /* NEG33, NOT33, MUL33, XOR33, AND33, OR33 */ - instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3); - instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3); - instruction->type = NDS32_INSN_DATA_PROC; - switch (opcode & 0x7) { - case 2: /* NEG33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tNEG33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 3: /* NOT33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tNOT33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 4: /* MUL33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tMUL33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 5: /* XOR33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tXOR33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 6: /* AND33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tAND33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - case 7: /* OR33 */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 - "\t\tOR33\t$r%" PRIu8 ",$r%" PRIu8, - address, - opcode, instruction->info.rt, instruction->info.ra); - break; - } - break; - } - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - - return ERROR_OK; -} - -int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction) -{ - int retval = ERROR_OK; - - /* clear fields, to avoid confusion */ - memset(instruction, 0, sizeof(struct nds32_instruction)); - - if (opcode >> 31) { - /* 16 bits instruction */ - instruction->instruction_size = 2; - opcode = (opcode >> 16) & 0xFFFF; - instruction->opcode = opcode; - - switch ((opcode >> 13) & 0x3) { - case 0: - retval = nds32_parse_group_0_insn_16(nds32, opcode, address, instruction); - break; - case 1: - retval = nds32_parse_group_1_insn_16(nds32, opcode, address, instruction); - break; - case 2: - retval = nds32_parse_group_2_insn_16(nds32, opcode, address, instruction); - break; - case 3: - retval = nds32_parse_group_3_insn_16(nds32, opcode, address, instruction); - break; - default: - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } else { - /* 32 bits instruction */ - instruction->instruction_size = 4; - instruction->opcode = opcode; - - uint8_t opc_6; - opc_6 = opcode >> 25; - instruction->info.opc_6 = opc_6; - - switch ((opc_6 >> 3) & 0x7) { - case 0: /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */ - retval = nds32_parse_group_0_insn(nds32, opcode, address, instruction); - break; - case 1: /* SBI, SHI, SWI, SBI.bi, SHI.bi, SWI.bi */ - retval = nds32_parse_group_1_insn(nds32, opcode, address, instruction); - break; - case 2: /* LBSI, LHSI, DPREFI, LBSI.bi, LHSI.bi, LBGP */ - retval = nds32_parse_group_2_insn(nds32, opcode, address, instruction); - break; - case 3: /* MEM, LSMW, HWGP, SBGP */ - retval = nds32_parse_group_3_insn(nds32, opcode, address, instruction); - break; - case 4: /* ALU_1, ALU_2, MOVI, SETHI, JI, JREG, BR1, BR2 */ - retval = nds32_parse_group_4_insn(nds32, opcode, address, instruction); - break; - case 5: /* ADDI, SUBRI, ANDI, XORI, ORI, SLTI, SLTSI */ - retval = nds32_parse_group_5_insn(nds32, opcode, address, instruction); - break; - case 6: /* MISC */ - retval = nds32_parse_group_6_insn(nds32, opcode, address, instruction); - break; - default: /* ERROR */ - snprintf(instruction->text, - 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", - address, - opcode); - return ERROR_FAIL; - } - } - - return retval; -} diff --git a/src/target/nds32_disassembler.h b/src/target/nds32_disassembler.h deleted file mode 100644 index f2c8e8596c..0000000000 --- a/src/target/nds32_disassembler.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_DISASSEMBLER_H -#define OPENOCD_TARGET_NDS32_DISASSEMBLER_H - -#include <target/nds32.h> - -enum nds32_instruction_type { - NDS32_INSN_DATA_PROC = 0, - NDS32_INSN_LOAD_STORE, - NDS32_INSN_JUMP_BRANCH, - NDS32_INSN_RESOURCE_ACCESS, - NDS32_INSN_MISC, -}; - -struct nds32_instruction { - enum nds32_instruction_type type; - char text[128]; - uint32_t opcode; - uint8_t instruction_size; - uint32_t access_start; - uint32_t access_end; - - struct { - uint8_t opc_6; - uint8_t rt; - uint8_t ra; - uint8_t rb; - uint8_t rd; - uint8_t sub_opc; - int32_t imm; - } info; - -}; - -int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value); -int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address, - struct nds32_instruction *instruction); - -#endif /* OPENOCD_TARGET_NDS32_DISASSEMBLER_H */ diff --git a/src/target/nds32_edm.h b/src/target/nds32_edm.h deleted file mode 100644 index 3213604b91..0000000000 --- a/src/target/nds32_edm.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_EDM_H -#define OPENOCD_TARGET_NDS32_EDM_H - -#include "helper/types.h" - -/** - * @file - * This is the interface to the Embedded Debug Module for Andes cores. - */ - -/* EDM misc registers */ -enum nds_edm_misc_reg { - NDS_EDM_MISC_DIMIR = 0x0, - NDS_EDM_MISC_SBAR, - NDS_EDM_MISC_EDM_CMDR, - NDS_EDM_MISC_DBGER, - NDS_EDM_MISC_ACC_CTL, - NDS_EDM_MISC_EDM_PROBE, - NDS_EDM_MISC_GEN_PORT0, - NDS_EDM_MISC_GEN_PORT1, -}; - -/* EDM system registers */ -enum nds_edm_system_reg { - NDS_EDM_SR_BPC0 = 0x00, - NDS_EDM_SR_BPC1, - NDS_EDM_SR_BPC2, - NDS_EDM_SR_BPC3, - NDS_EDM_SR_BPC4, - NDS_EDM_SR_BPC5, - NDS_EDM_SR_BPC6, - NDS_EDM_SR_BPC7, - NDS_EDM_SR_BPA0 = 0x08, - NDS_EDM_SR_BPA1, - NDS_EDM_SR_BPA2, - NDS_EDM_SR_BPA3, - NDS_EDM_SR_BPA4, - NDS_EDM_SR_BPA5, - NDS_EDM_SR_BPA6, - NDS_EDM_SR_BPA7, - NDS_EDM_SR_BPAM0 = 0x10, - NDS_EDM_SR_BPAM1, - NDS_EDM_SR_BPAM2, - NDS_EDM_SR_BPAM3, - NDS_EDM_SR_BPAM4, - NDS_EDM_SR_BPAM5, - NDS_EDM_SR_BPAM6, - NDS_EDM_SR_BPAM7, - NDS_EDM_SR_BPV0 = 0x18, - NDS_EDM_SR_BPV1, - NDS_EDM_SR_BPV2, - NDS_EDM_SR_BPV3, - NDS_EDM_SR_BPV4, - NDS_EDM_SR_BPV5, - NDS_EDM_SR_BPV6, - NDS_EDM_SR_BPV7, - NDS_EDM_SR_BPCID0 = 0x20, - NDS_EDM_SR_BPCID1, - NDS_EDM_SR_BPCID2, - NDS_EDM_SR_BPCID3, - NDS_EDM_SR_BPCID4, - NDS_EDM_SR_BPCID5, - NDS_EDM_SR_BPCID6, - NDS_EDM_SR_BPCID7, - NDS_EDM_SR_EDM_CFG = 0x28, - NDS_EDM_SR_EDMSW = 0x30, - NDS_EDM_SR_EDM_CTL = 0x38, - NDS_EDM_SR_EDM_DTR = 0x40, - NDS_EDM_SR_BPMTV = 0x48, - NDS_EDM_SR_DIMBR = 0x50, - NDS_EDM_SR_TECR0 = 0x70, - NDS_EDM_SR_TECR1 = 0x71, -}; - -enum nds_memory_access { - NDS_MEMORY_ACC_BUS = 0, - NDS_MEMORY_ACC_CPU, -}; - -enum nds_memory_select { - NDS_MEMORY_SELECT_AUTO = 0, - NDS_MEMORY_SELECT_MEM = 1, - NDS_MEMORY_SELECT_ILM = 2, - NDS_MEMORY_SELECT_DLM = 3, -}; - -#define NDS_DBGER_DEX (0x1) -#define NDS_DBGER_DPED (0x2) -#define NDS_DBGER_CRST (0x4) -#define NDS_DBGER_AT_MAX (0x8) -#define NDS_DBGER_ILL_SEC_ACC (0x10) -#define NDS_DBGER_ALL_SUPRS_EX (0x40000000) -#define NDS_DBGER_RESACC (0x80000000) -#define NDS_DBGER_CLEAR_ALL (0x1F) - -#define NDS_EDMSW_WDV (1 << 0) -#define NDS_EDMSW_RDV (1 << 1) - -#endif /* OPENOCD_TARGET_NDS32_EDM_H */ diff --git a/src/target/nds32_insn.h b/src/target/nds32_insn.h deleted file mode 100644 index 25eb9ab8c8..0000000000 --- a/src/target/nds32_insn.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_INSN_H -#define OPENOCD_TARGET_NDS32_INSN_H - -#define NOP (0x40000009) -#define DSB (0x64000008) -#define ISB (0x64000009) -#define BEQ_MINUS_12 (0x4C000000 | 0x3FFA) -#define MTSR_DTR(a) (0x64000003 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) -#define MFSR_DTR(a) (0x64000002 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) -#define SETHI(a, b) (0x46000000 | ((a) << 20) | (b)) -#define ORI(a, b, c) (0x58000000 | ((a) << 20) | ((b) << 15) | (c)) -#define LWI_BI(a, b) (0x0C000001 | (a << 20) | (b << 15)) -#define LHI_BI(a, b) (0x0A000001 | (a << 20) | (b << 15)) -#define LBI_BI(a, b) (0x08000001 | (a << 20) | (b << 15)) -#define SWI_BI(a, b) (0x1C000001 | (a << 20) | (b << 15)) -#define SHI_BI(a, b) (0x1A000001 | (a << 20) | (b << 15)) -#define SBI_BI(a, b) (0x18000001 | (a << 20) | (b << 15)) -#define IRET (0x64000004) -#define L1D_IX_WB(a) (0x64000021 | ((a) << 15)) -#define L1D_IX_INVAL(a) (0x64000001 | ((a) << 15)) -#define L1D_VA_INVAL(a) (0x64000101 | ((a) << 15)) -#define L1D_VA_WB(a) (0x64000121 | ((a) << 15)) -#define L1D_IX_RTAG(a) (0x64000061 | ((a) << 15)) -#define L1D_IX_RWD(a) (0x64000081 | ((a) << 15)) -#define L1I_IX_INVAL(a) (0x64000201 | ((a) << 15)) -#define L1I_VA_INVAL(a) (0x64000301 | ((a) << 15)) -#define L1I_IX_RTAG(a) (0x64000261 | ((a) << 15)) -#define L1I_IX_RWD(a) (0x64000281 | ((a) << 15)) -#define L1I_VA_FILLCK(a) (0x64000361 | ((a) << 15)) -#define ISYNC(a) (0x6400000d | ((a) << 20)) -#define MSYNC_STORE (0x6400002c) -#define MSYNC_ALL (0x6400000c) -#define TLBOP_TARGET_READ(a) (0x6400000e | ((a) << 15)) -#define TLBOP_TARGET_PROBE(a, b) (0x640000AE | ((a) << 20) | ((b) << 15)) -#define MFCPD(a, b, c) (0x6A000041 | (a << 20) | (b << 8) | (c << 4)) -#define MFCPW(a, b, c) (0x6A000001 | (a << 20) | (b << 8) | (c << 4)) -#define MTCPD(a, b, c) (0x6A000049 | (a << 20) | (b << 8) | (c << 4)) -#define MTCPW(a, b, c) (0x6A000009 | (a << 20) | (b << 8) | (c << 4)) -#define MOVI_(a, b) (0x44000000 | (a << 20) | (b & 0xFFFFF)) -#define MFUSR_G0(a, b) (0x42000020 | (a << 20) | (b << 15)) -#define MTUSR_G0(a, b) (0x42000021 | (a << 20) | (b << 15)) -#define MFSR(a, b) (0x64000002 | (b << 10) | (a << 20)) -#define MTSR(a, b) (0x64000003 | (b << 10) | (a << 20)) -#define AMFAR(a, b) (0x60300060 | (a << 15) | b) -#define AMTAR(a, b) (0x60300040 | (a << 15) | b) -#define AMFAR2(a, b) (0x60300260 | (a << 15) | b) -#define AMTAR2(a, b) (0x60300240 | (a << 15) | b) -#define FMFCSR (0x6A000701) -#define FMTCSR (0x6A000709) -#define FMFCFG (0x6A000301) -#define FMFSR(a, b) (0x6A000001 | ((a) << 20) | ((b) << 15)) -#define FMTSR(a, b) (0x6A000009 | ((a) << 20) | ((b) << 15)) -#define FMFDR(a, b) (0x6A000041 | ((a) << 20) | ((b) << 15)) -#define FMTDR(a, b) (0x6A000049 | ((a) << 20) | ((b) << 15)) - -/* break instructions */ -#define NDS32_BREAK_16 (0x00EA) -#define NDS32_BREAK_32 (0x0A000064) - -#endif /* OPENOCD_TARGET_NDS32_INSN_H */ diff --git a/src/target/nds32_reg.c b/src/target/nds32_reg.c deleted file mode 100644 index d7b32e7fb3..0000000000 --- a/src/target/nds32_reg.c +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/log.h> -#include "nds32_reg.h" - -static bool nds32_reg_init_done; -static struct nds32_reg_s nds32_regs[TOTAL_REG_NUM]; -static const struct nds32_reg_exception_s nds32_ex_reg_values[] = { - {IR0, 3, 0x3, 2}, - {IR0, 3, 0x3, 3}, - {IR1, 3, 0x3, 2}, - {IR1, 3, 0x3, 3}, - {IR2, 3, 0x3, 2}, - {IR2, 3, 0x3, 3}, - {MR3, 1, 0x7, 0}, - {MR3, 1, 0x7, 4}, - {MR3, 1, 0x7, 6}, - {MR3, 8, 0x7, 3}, - {0, 0, 0, 0}, -}; - -static inline void nds32_reg_set(uint32_t number, const char *simple_mnemonic, - const char *symbolic_mnemonic, uint32_t sr_index, - enum nds32_reg_type_s type, uint8_t size) -{ - nds32_regs[number].simple_mnemonic = simple_mnemonic; - nds32_regs[number].symbolic_mnemonic = symbolic_mnemonic; - nds32_regs[number].sr_index = sr_index; - nds32_regs[number].type = type; - nds32_regs[number].size = size; -} - -void nds32_reg_init(void) -{ - if (nds32_reg_init_done == true) - return; - - nds32_reg_set(R0, "r0", "r0", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R1, "r1", "r1", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R2, "r2", "r2", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R3, "r3", "r3", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R4, "r4", "r4", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R5, "r5", "r5", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R6, "r6", "r6", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R7, "r7", "r7", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R8, "r8", "r8", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R9, "r9", "r9", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R10, "r10", "r10", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R11, "r11", "r11", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R12, "r12", "r12", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R13, "r13", "r13", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R14, "r14", "r14", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R15, "r15", "r15", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R16, "r16", "r16", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R17, "r17", "r17", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R18, "r18", "r18", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R19, "r19", "r19", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R20, "r20", "r20", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R21, "r21", "r21", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R22, "r22", "r22", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R23, "r23", "r23", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R24, "r24", "r24", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R25, "r25", "r25", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R26, "r26", "p0", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R27, "r27", "p1", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R28, "fp", "fp", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R29, "gp", "gp", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R30, "lp", "lp", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(R31, "sp", "sp", 0, NDS32_REG_TYPE_GPR, 32); - nds32_reg_set(PC, "pc", "pc", 31, NDS32_REG_TYPE_SPR, 32); - - nds32_reg_set(D0LO, "d0lo", "d0lo", 0, NDS32_REG_TYPE_SPR, 32); - nds32_reg_set(D0HI, "d0hi", "d0hi", 1, NDS32_REG_TYPE_SPR, 32); - nds32_reg_set(D1LO, "d1lo", "d1lo", 2, NDS32_REG_TYPE_SPR, 32); - nds32_reg_set(D1HI, "d1hi", "d1hi", 3, NDS32_REG_TYPE_SPR, 32); - nds32_reg_set(ITB, "itb", "itb", 28, NDS32_REG_TYPE_SPR, 32); - nds32_reg_set(IFC_LP, "ifc_lp", "ifc_lp", 29, NDS32_REG_TYPE_SPR, 32); - - nds32_reg_set(CR0, "cr0", "CPU_VER", SRIDX(0, 0, 0), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR1, "cr1", "ICM_CFG", SRIDX(0, 1, 0), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR2, "cr2", "DCM_CFG", SRIDX(0, 2, 0), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR3, "cr3", "MMU_CFG", SRIDX(0, 3, 0), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR4, "cr4", "MSC_CFG", SRIDX(0, 4, 0), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR5, "cr5", "CORE_ID", SRIDX(0, 0, 1), NDS32_REG_TYPE_CR, 32); - nds32_reg_set(CR6, "cr6", "FUCOP_EXIST", SRIDX(0, 5, 0), NDS32_REG_TYPE_CR, 32); - - nds32_reg_set(IR0, "ir0", "PSW", SRIDX(1, 0, 0), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR1, "ir1", "IPSW", SRIDX(1, 0, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR2, "ir2", "P_IPSW", SRIDX(1, 0, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR3, "ir3", "IVB", SRIDX(1, 1, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR4, "ir4", "EVA", SRIDX(1, 2, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR5, "ir5", "P_EVA", SRIDX(1, 2, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR6, "ir6", "ITYPE", SRIDX(1, 3, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR7, "ir7", "P_ITYPE", SRIDX(1, 3, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR8, "ir8", "MERR", SRIDX(1, 4, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR9, "ir9", "IPC", SRIDX(1, 5, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR10, "ir10", "P_IPC", SRIDX(1, 5, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR11, "ir11", "OIPC", SRIDX(1, 5, 3), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR12, "ir12", "P_P0", SRIDX(1, 6, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR13, "ir13", "P_P1", SRIDX(1, 7, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR14, "ir14", "INT_MASK", SRIDX(1, 8, 0), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR15, "ir15", "INT_PEND", SRIDX(1, 9, 0), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR16, "ir16", "", SRIDX(1, 10, 0), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR17, "ir17", "", SRIDX(1, 10, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR18, "ir18", "", SRIDX(1, 11, 0), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR19, "ir19", "", SRIDX(1, 1, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR20, "ir20", "", SRIDX(1, 10, 2), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR21, "ir21", "", SRIDX(1, 10, 3), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR22, "ir22", "", SRIDX(1, 10, 4), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR23, "ir23", "", SRIDX(1, 10, 5), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR24, "ir24", "", SRIDX(1, 10, 6), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR25, "ir25", "", SRIDX(1, 10, 7), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR26, "ir26", "", SRIDX(1, 8, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR27, "ir27", "", SRIDX(1, 9, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR28, "ir28", "", SRIDX(1, 11, 1), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR29, "ir29", "", SRIDX(1, 9, 4), NDS32_REG_TYPE_IR, 32); - nds32_reg_set(IR30, "ir30", "", SRIDX(1, 1, 3), NDS32_REG_TYPE_IR, 32); - - nds32_reg_set(MR0, "mr0", "MMU_CTL", SRIDX(2, 0, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR1, "mr1", "L1_PPTB", SRIDX(2, 1, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR2, "mr2", "TLB_VPN", SRIDX(2, 2, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR3, "mr3", "TLB_DATA", SRIDX(2, 3, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR4, "mr4", "TLB_MISC", SRIDX(2, 4, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR5, "mr5", "VLPT_IDX", SRIDX(2, 5, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR6, "mr6", "ILMB", SRIDX(2, 6, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR7, "mr7", "DLMB", SRIDX(2, 7, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR8, "mr8", "CACHE_CTL", SRIDX(2, 8, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR9, "mr9", "HSMP_SADDR", SRIDX(2, 9, 0), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR10, "mr10", "HSMP_EADDR", SRIDX(2, 9, 1), NDS32_REG_TYPE_MR, 32); - nds32_reg_set(MR11, "mr11", "", SRIDX(2, 0, 1), NDS32_REG_TYPE_MR, 32); - - nds32_reg_set(DR0, "dr0", "BPC0", SRIDX(3, 0, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR1, "dr1", "BPA0", SRIDX(3, 1, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR2, "dr2", "BPAM0", SRIDX(3, 2, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR3, "dr3", "BPV0", SRIDX(3, 3, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR4, "dr4", "BPCID0", SRIDX(3, 4, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR5, "dr5", "BPC1", SRIDX(3, 0, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR6, "dr6", "BPA1", SRIDX(3, 1, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR7, "dr7", "BPAM1", SRIDX(3, 2, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR8, "dr8", "BPV1", SRIDX(3, 3, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR9, "dr9", "BPCID1", SRIDX(3, 4, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR10, "dr10", "BPC2", SRIDX(3, 0, 2), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR11, "dr11", "BPA2", SRIDX(3, 1, 2), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR12, "dr12", "BPAM2", SRIDX(3, 2, 2), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR13, "dr13", "BPV2", SRIDX(3, 3, 2), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR14, "dr14", "BPCID2", SRIDX(3, 4, 2), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR15, "dr15", "BPC3", SRIDX(3, 0, 3), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR16, "dr16", "BPA3", SRIDX(3, 1, 3), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR17, "dr17", "BPAM3", SRIDX(3, 2, 3), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR18, "dr18", "BPV3", SRIDX(3, 3, 3), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR19, "dr19", "BPCID3", SRIDX(3, 4, 3), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR20, "dr20", "BPC4", SRIDX(3, 0, 4), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR21, "dr21", "BPA4", SRIDX(3, 1, 4), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR22, "dr22", "BPAM4", SRIDX(3, 2, 4), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR23, "dr23", "BPV4", SRIDX(3, 3, 4), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR24, "dr24", "BPCID4", SRIDX(3, 4, 4), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR25, "dr25", "BPC5", SRIDX(3, 0, 5), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR26, "dr26", "BPA5", SRIDX(3, 1, 5), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR27, "dr27", "BPAM5", SRIDX(3, 2, 5), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR28, "dr28", "BPV5", SRIDX(3, 3, 5), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR29, "dr29", "BPCID5", SRIDX(3, 4, 5), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR30, "dr30", "BPC6", SRIDX(3, 0, 6), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR31, "dr31", "BPA6", SRIDX(3, 1, 6), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR32, "dr32", "BPAM6", SRIDX(3, 2, 6), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR33, "dr33", "BPV6", SRIDX(3, 3, 6), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR34, "dr34", "BPCID6", SRIDX(3, 4, 6), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR35, "dr35", "BPC7", SRIDX(3, 0, 7), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR36, "dr36", "BPA7", SRIDX(3, 1, 7), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR37, "dr37", "BPAM7", SRIDX(3, 2, 7), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR38, "dr38", "BPV7", SRIDX(3, 3, 7), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR39, "dr39", "BPCID7", SRIDX(3, 4, 7), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR40, "dr40", "EDM_CFG", SRIDX(3, 5, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR41, "dr41", "EDMSW", SRIDX(3, 6, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR42, "dr42", "EDM_CTL", SRIDX(3, 7, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR43, "dr43", "EDM_DTR", SRIDX(3, 8, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR44, "dr44", "BPMTC", SRIDX(3, 9, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR45, "dr45", "DIMBR", SRIDX(3, 10, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR46, "dr46", "TECR0", SRIDX(3, 14, 0), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR47, "dr47", "TECR1", SRIDX(3, 14, 1), NDS32_REG_TYPE_DR, 32); - nds32_reg_set(DR48, "dr48", "", SRIDX(3, 11, 0), NDS32_REG_TYPE_DR, 32); - - nds32_reg_set(PFR0, "pfr0", "PFMC0", SRIDX(4, 0, 0), NDS32_REG_TYPE_PFR, 32); - nds32_reg_set(PFR1, "pfr1", "PFMC1", SRIDX(4, 0, 1), NDS32_REG_TYPE_PFR, 32); - nds32_reg_set(PFR2, "pfr2", "PFMC2", SRIDX(4, 0, 2), NDS32_REG_TYPE_PFR, 32); - nds32_reg_set(PFR3, "pfr3", "PFM_CTL", SRIDX(4, 1, 0), NDS32_REG_TYPE_PFR, 32); - - nds32_reg_set(DMAR0, "dmar0", "DMA_CFG", SRIDX(5, 0, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR1, "dmar1", "DMA_GCSW", SRIDX(5, 1, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR2, "dmar2", "DMA_CHNSEL", SRIDX(5, 2, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR3, "dmar3", "DMA_ACT", SRIDX(5, 3, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR4, "dmar4", "DMA_SETUP", SRIDX(5, 4, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR5, "dmar5", "DMA_ISADDR", SRIDX(5, 5, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR6, "dmar6", "DMA_ESADDR", SRIDX(5, 6, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR7, "dmar7", "DMA_TCNT", SRIDX(5, 7, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR8, "dmar8", "DMA_STATUS", SRIDX(5, 8, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR9, "dmar9", "DMA_2DSET", SRIDX(5, 9, 0), NDS32_REG_TYPE_DMAR, 32); - nds32_reg_set(DMAR10, "dmar10", "DMA_2DSCTL", SRIDX(5, 9, 1), NDS32_REG_TYPE_DMAR, 32); - - nds32_reg_set(RACR, "racr", "PRUSR_ACC_CTL", SRIDX(4, 4, 0), NDS32_REG_TYPE_RACR, 32); - nds32_reg_set(FUCPR, "fucpr", "FUCOP_CTL", SRIDX(4, 5, 0), NDS32_REG_TYPE_RACR, 32); - - nds32_reg_set(IDR0, "idr0", "SDZ_CTL", SRIDX(2, 15, 0), NDS32_REG_TYPE_IDR, 32); - nds32_reg_set(IDR1, "idr1", "MISC_CTL", SRIDX(2, 15, 1), NDS32_REG_TYPE_IDR, 32); - - nds32_reg_set(SECUR0, "secur0", "", SRIDX(6, 0, 0), NDS32_REG_TYPE_SECURE, 32); - - nds32_reg_set(D0L24, "D0L24", "D0L24", 0x10, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(D1L24, "D1L24", "D1L24", 0x11, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I0, "I0", "I0", 0x0, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I1, "I1", "I1", 0x1, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I2, "I2", "I2", 0x2, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I3, "I3", "I3", 0x3, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I4, "I4", "I4", 0x4, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I5, "I5", "I5", 0x5, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I6, "I6", "I6", 0x6, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(I7, "I7", "I7", 0x7, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M1, "M1", "M1", 0x9, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M2, "M2", "M2", 0xA, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M3, "M3", "M3", 0xB, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M5, "M5", "M5", 0xD, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M6, "M6", "M6", 0xE, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(M7, "M7", "M7", 0xF, NDS32_REG_TYPE_AUMR, 32); - - nds32_reg_set(MOD, "MOD", "MOD", 0x8, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(LBE, "LBE", "LBE", 0x18, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(LE, "LE", "LE", 0x19, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(LC, "LC", "LC", 0x1A, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(ADM_VBASE, "ADM_VBASE", "ADM_VBASE", 0x1B, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(SHFT_CTL0, "SHFT_CTL0", "SHFT_CTL0", 0x12, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(SHFT_CTL1, "SHFT_CTL1", "SHFT_CTL1", 0x13, NDS32_REG_TYPE_AUMR, 32); - - nds32_reg_set(CB_CTL, "CB_CTL", "CB_CTL", 0x1F, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBB0, "CBB0", "CBB0", 0x0, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBB1, "CBB1", "CBB1", 0x1, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBB2, "CBB2", "CBB2", 0x2, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBB3, "CBB3", "CBB3", 0x3, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBE0, "CBE0", "CBE0", 0x4, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBE1, "CBE1", "CBE1", 0x5, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBE2, "CBE2", "CBE2", 0x6, NDS32_REG_TYPE_AUMR, 32); - nds32_reg_set(CBE3, "CBE3", "CBE3", 0x7, NDS32_REG_TYPE_AUMR, 32); - - nds32_reg_set(FPCSR, "fpcsr", "FPCSR", 0x7, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FPCFG, "fpcfg", "FPCFG", 0x7, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS0, "fs0", "FS0", 0, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS1, "fs1", "FS1", 1, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS2, "fs2", "FS2", 2, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS3, "fs3", "FS3", 3, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS4, "fs4", "FS4", 4, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS5, "fs5", "FS5", 5, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS6, "fs6", "FS6", 6, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS7, "fs7", "FS7", 7, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS8, "fs8", "FS8", 8, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS9, "fs9", "FS9", 9, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS10, "fs10", "FS10", 10, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS11, "fs11", "FS11", 11, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS12, "fs12", "FS12", 12, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS13, "fs13", "FS13", 13, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS14, "fs14", "FS14", 14, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS15, "fs15", "FS15", 15, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS16, "fs16", "FS16", 16, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS17, "fs17", "FS17", 17, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS18, "fs18", "FS18", 18, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS19, "fs19", "FS19", 19, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS20, "fs20", "FS20", 20, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS21, "fs21", "FS21", 21, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS22, "fs22", "FS22", 22, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS23, "fs23", "FS23", 23, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS24, "fs24", "FS24", 24, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS25, "fs25", "FS25", 25, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS26, "fs26", "FS26", 26, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS27, "fs27", "FS27", 27, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS28, "fs28", "FS28", 28, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS29, "fs29", "FS29", 29, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS30, "fs30", "FS30", 30, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FS31, "fs31", "FS31", 31, NDS32_REG_TYPE_FPU, 32); - nds32_reg_set(FD0, "fd0", "FD0", 0, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD1, "fd1", "FD1", 1, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD2, "fd2", "FD2", 2, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD3, "fd3", "FD3", 3, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD4, "fd4", "FD4", 4, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD5, "fd5", "FD5", 5, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD6, "fd6", "FD6", 6, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD7, "fd7", "FD7", 7, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD8, "fd8", "FD8", 8, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD9, "fd9", "FD9", 9, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD10, "fd10", "FD10", 10, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD11, "fd11", "FD11", 11, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD12, "fd12", "FD12", 12, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD13, "fd13", "FD13", 13, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD14, "fd14", "FD14", 14, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD15, "fd15", "FD15", 15, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD16, "fd16", "FD16", 16, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD17, "fd17", "FD17", 17, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD18, "fd18", "FD18", 18, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD19, "fd19", "FD19", 19, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD20, "fd20", "FD20", 20, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD21, "fd21", "FD21", 21, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD22, "fd22", "FD22", 22, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD23, "fd23", "FD23", 23, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD24, "fd24", "FD24", 24, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD25, "fd25", "FD25", 25, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD26, "fd26", "FD26", 26, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD27, "fd27", "FD27", 27, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD28, "fd28", "FD28", 28, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD29, "fd29", "FD29", 29, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD30, "fd30", "FD30", 30, NDS32_REG_TYPE_FPU, 64); - nds32_reg_set(FD31, "fd31", "FD31", 31, NDS32_REG_TYPE_FPU, 64); - - nds32_reg_init_done = true; -} - -uint32_t nds32_reg_sr_index(uint32_t number) -{ - return nds32_regs[number].sr_index; -} - -enum nds32_reg_type_s nds32_reg_type(uint32_t number) -{ - return nds32_regs[number].type; -} - -uint8_t nds32_reg_size(uint32_t number) -{ - return nds32_regs[number].size; -} - -const char *nds32_reg_simple_name(uint32_t number) -{ - return nds32_regs[number].simple_mnemonic; -} - -const char *nds32_reg_symbolic_name(uint32_t number) -{ - return nds32_regs[number].symbolic_mnemonic; -} - -bool nds32_reg_exception(uint32_t number, uint32_t value) -{ - int i; - const struct nds32_reg_exception_s *ex_reg_value; - uint32_t field_value; - - i = 0; - while (nds32_ex_reg_values[i].reg_num != 0) { - ex_reg_value = nds32_ex_reg_values + i; - - if (ex_reg_value->reg_num == number) { - field_value = (value >> ex_reg_value->ex_value_bit_pos) & - ex_reg_value->ex_value_mask; - if (field_value == ex_reg_value->ex_value) { - LOG_WARNING("It will generate exceptions as setting %" PRIu32 " to %s", - value, nds32_regs[number].simple_mnemonic); - return true; - } - } - - i++; - } - - return false; -} diff --git a/src/target/nds32_reg.h b/src/target/nds32_reg.h deleted file mode 100644 index 30cd241724..0000000000 --- a/src/target/nds32_reg.h +++ /dev/null @@ -1,314 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_REG_H -#define OPENOCD_TARGET_NDS32_REG_H - -#define SRIDX(a, b, c) ((a << 7) | (b << 3) | c) -#define NDS32_REGISTER_DISABLE (0x0) - -enum nds32_reg_number_s { - R0 = 0, /* general registers */ - R1, - R2, - R3, - R4, - R5, - R6, - R7, - R8, - R9, - R10, - R11, - R12, - R13, - R14, - R15, - R16, - R17, - R18, - R19, - R20, - R21, - R22, - R23, - R24, - R25, - R26, - R27, - R28, - R29, - R30, - R31, - PC, - D0LO, - D0HI, - D1LO, - D1HI, - ITB, - IFC_LP, - CR0, /* system registers */ - CR1, - CR2, - CR3, - CR4, - CR5, - CR6, - IR0, - IR1, - IR2, - IR3, - IR4, - IR5, - IR6, - IR7, - IR8, - IR9, - IR10, - IR11, - IR12, - IR13, - IR14, - IR15, - IR16, - IR17, - IR18, - IR19, - IR20, - IR21, - IR22, - IR23, - IR24, - IR25, - IR26, - IR27, - IR28, - IR29, - IR30, - MR0, - MR1, - MR2, - MR3, - MR4, - MR5, - MR6, - MR7, - MR8, - MR9, - MR10, - MR11, - DR0, - DR1, - DR2, - DR3, - DR4, - DR5, - DR6, - DR7, - DR8, - DR9, - DR10, - DR11, - DR12, - DR13, - DR14, - DR15, - DR16, - DR17, - DR18, - DR19, - DR20, - DR21, - DR22, - DR23, - DR24, - DR25, - DR26, - DR27, - DR28, - DR29, - DR30, - DR31, - DR32, - DR33, - DR34, - DR35, - DR36, - DR37, - DR38, - DR39, - DR40, - DR41, - DR42, - DR43, - DR44, - DR45, - DR46, - DR47, - DR48, - PFR0, - PFR1, - PFR2, - PFR3, - DMAR0, - DMAR1, - DMAR2, - DMAR3, - DMAR4, - DMAR5, - DMAR6, - DMAR7, - DMAR8, - DMAR9, - DMAR10, - RACR, - FUCPR, - IDR0, - IDR1, - SECUR0, - D0L24, /* audio registers */ - D1L24, - I0, - I1, - I2, - I3, - I4, - I5, - I6, - I7, - M1, - M2, - M3, - M5, - M6, - M7, - MOD, - LBE, - LE, - LC, - ADM_VBASE, - SHFT_CTL0, - SHFT_CTL1, - CB_CTL, - CBB0, - CBB1, - CBB2, - CBB3, - CBE0, - CBE1, - CBE2, - CBE3, - FPCSR, /* fpu */ - FPCFG, - FS0, - FS1, - FS2, - FS3, - FS4, - FS5, - FS6, - FS7, - FS8, - FS9, - FS10, - FS11, - FS12, - FS13, - FS14, - FS15, - FS16, - FS17, - FS18, - FS19, - FS20, - FS21, - FS22, - FS23, - FS24, - FS25, - FS26, - FS27, - FS28, - FS29, - FS30, - FS31, - FD0, - FD1, - FD2, - FD3, - FD4, - FD5, - FD6, - FD7, - FD8, - FD9, - FD10, - FD11, - FD12, - FD13, - FD14, - FD15, - FD16, - FD17, - FD18, - FD19, - FD20, - FD21, - FD22, - FD23, - FD24, - FD25, - FD26, - FD27, - FD28, - FD29, - FD30, - FD31, - - TOTAL_REG_NUM, -}; - -enum nds32_reg_type_s { - NDS32_REG_TYPE_GPR = 0, - NDS32_REG_TYPE_SPR, - NDS32_REG_TYPE_CR, - NDS32_REG_TYPE_IR, - NDS32_REG_TYPE_MR, - NDS32_REG_TYPE_DR, - NDS32_REG_TYPE_PFR, - NDS32_REG_TYPE_DMAR, - NDS32_REG_TYPE_RACR, - NDS32_REG_TYPE_IDR, - NDS32_REG_TYPE_AUMR, - NDS32_REG_TYPE_SECURE, - NDS32_REG_TYPE_FPU, -}; - -struct nds32_reg_s { - const char *simple_mnemonic; - const char *symbolic_mnemonic; - uint32_t sr_index; - enum nds32_reg_type_s type; - uint8_t size; -}; - -struct nds32_reg_exception_s { - uint32_t reg_num; - uint32_t ex_value_bit_pos; - uint32_t ex_value_mask; - uint32_t ex_value; -}; - -void nds32_reg_init(void); -uint32_t nds32_reg_sr_index(uint32_t number); -enum nds32_reg_type_s nds32_reg_type(uint32_t number); -uint8_t nds32_reg_size(uint32_t number); -const char *nds32_reg_simple_name(uint32_t number); -const char *nds32_reg_symbolic_name(uint32_t number); -bool nds32_reg_exception(uint32_t number, uint32_t value); - -#endif /* OPENOCD_TARGET_NDS32_REG_H */ diff --git a/src/target/nds32_tlb.c b/src/target/nds32_tlb.c deleted file mode 100644 index 82123a3dd0..0000000000 --- a/src/target/nds32_tlb.c +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "nds32_aice.h" -#include "nds32_tlb.h" - -int nds32_probe_tlb(struct nds32 *nds32, const target_addr_t virtual_address, - target_addr_t *physical_address) -{ - struct target *target = nds32->target; - struct aice_port_s *aice = target_to_aice(target); - - return aice_read_tlb(aice, virtual_address, physical_address); -} - -static struct page_table_walker_info_s page_table_info[PAGE_SIZE_NUM] = { - /* 4K page */ - {0xFFC00000, 20, 0x003FF000, 10, 0x00000FFF, 0xFFFFF000, 0xFFFFF000, 0xFFFFF000}, - /* 8K page */ - {0xFF000000, 22, 0x00FFE000, 11, 0x00001FFF, 0xFFFFF000, 0xFFFFE000, 0xFFFFE000}, -}; - -int nds32_walk_page_table(struct nds32 *nds32, const target_addr_t virtual_address, - target_addr_t *physical_address) -{ - struct target *target = nds32->target; - uint32_t value_mr1; - uint32_t load_address; - uint32_t l1_page_table_entry; - uint32_t l2_page_table_entry; - uint32_t page_size_index = nds32->mmu_config.default_min_page_size; - struct page_table_walker_info_s *page_table_info_p = - &(page_table_info[page_size_index]); - - /* Read L1 Physical Page Table */ - nds32_get_mapped_reg(nds32, MR1, &value_mr1); - load_address = (value_mr1 & page_table_info_p->l1_base_mask) | - ((virtual_address & page_table_info_p->l1_offset_mask) >> - page_table_info_p->l1_offset_shift); - /* load_address is physical address */ - nds32_read_buffer(target, load_address, 4, (uint8_t *)&l1_page_table_entry); - - /* Read L2 Physical Page Table */ - if (l1_page_table_entry & 0x1) /* L1_PTE not present */ - return ERROR_FAIL; - - load_address = (l1_page_table_entry & page_table_info_p->l2_base_mask) | - ((virtual_address & page_table_info_p->l2_offset_mask) >> - page_table_info_p->l2_offset_shift); - /* load_address is physical address */ - nds32_read_buffer(target, load_address, 4, (uint8_t *)&l2_page_table_entry); - - if ((l2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */ - return ERROR_FAIL; - - *physical_address = (l2_page_table_entry & page_table_info_p->ppn_mask) | - (virtual_address & page_table_info_p->va_offset_mask); - - return ERROR_OK; -} diff --git a/src/target/nds32_tlb.h b/src/target/nds32_tlb.h deleted file mode 100644 index 1edff294fd..0000000000 --- a/src/target/nds32_tlb.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_TLB_H -#define OPENOCD_TARGET_NDS32_TLB_H - -#include "nds32.h" - -enum { - PAGE_SIZE_4K = 0, - PAGE_SIZE_8K, - PAGE_SIZE_NUM, -}; - -struct page_table_walker_info_s { - - uint32_t l1_offset_mask; - uint32_t l1_offset_shift; - uint32_t l2_offset_mask; - uint32_t l2_offset_shift; - uint32_t va_offset_mask; - uint32_t l1_base_mask; - uint32_t l2_base_mask; - uint32_t ppn_mask; -}; - -extern int nds32_probe_tlb(struct nds32 *nds32, const target_addr_t virtual_address, - target_addr_t *physical_address); -extern int nds32_walk_page_table(struct nds32 *nds32, const target_addr_t virtual_address, - target_addr_t *physical_address); - -#endif /* OPENOCD_TARGET_NDS32_TLB_H */ diff --git a/src/target/nds32_v2.c b/src/target/nds32_v2.c deleted file mode 100644 index 48cf65f1d4..0000000000 --- a/src/target/nds32_v2.c +++ /dev/null @@ -1,774 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <helper/time_support.h> -#include <helper/binarybuffer.h> -#include "breakpoints.h" -#include "nds32_insn.h" -#include "nds32_reg.h" -#include "nds32_edm.h" -#include "nds32_cmd.h" -#include "nds32_v2.h" -#include "nds32_aice.h" -#include "target_type.h" - -static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no) -{ - uint32_t max_level = nds32->max_interrupt_level; - uint32_t cur_level = nds32->current_interrupt_level; - - if ((cur_level >= 1) && (cur_level < max_level)) { - if (reg_no == IR0) { - LOG_DEBUG("Map PSW to IPSW"); - return IR1; - } else if (reg_no == PC) { - LOG_DEBUG("Map PC to IPC"); - return IR9; - } - } else if ((cur_level >= 2) && (cur_level < max_level)) { - if (reg_no == R26) { - LOG_DEBUG("Mapping P0 to P_P0"); - return IR12; - } else if (reg_no == R27) { - LOG_DEBUG("Mapping P1 to P_P1"); - return IR13; - } else if (reg_no == IR1) { - LOG_DEBUG("Mapping IPSW to P_IPSW"); - return IR2; - } else if (reg_no == IR4) { - LOG_DEBUG("Mapping EVA to P_EVA"); - return IR5; - } else if (reg_no == IR6) { - LOG_DEBUG("Mapping ITYPE to P_ITYPE"); - return IR7; - } else if (reg_no == IR9) { - LOG_DEBUG("Mapping IPC to P_IPC"); - return IR10; - } - } else if (cur_level == max_level) { - if (reg_no == PC) { - LOG_DEBUG("Mapping PC to O_IPC"); - return IR11; - } - } - - return reg_no; -} - -static int nds32_v2_get_debug_reason(struct nds32 *nds32, uint32_t *reason) -{ - uint32_t val_itype; - struct aice_port_s *aice = target_to_aice(nds32->target); - - aice_read_register(aice, IR6, &val_itype); - - *reason = val_itype & 0x0F; - - return ERROR_OK; -} - -static int nds32_v2_activate_hardware_breakpoint(struct target *target) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - int32_t hbr_index = 0; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) { - /* already set at nds32_v2_add_breakpoint() */ - continue; - } else if (bp->type == BKPT_HARD) { - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0); - /* set value */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0); - - if (nds32_v2->nds32.memory.address_translation) - /* enable breakpoint (virtual address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2); - else - /* enable breakpoint (physical address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA); - - LOG_DEBUG("Add hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index, - bp->address); - - hbr_index++; - } else { - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int nds32_v2_deactivate_hardware_breakpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - int32_t hbr_index = 0; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) - continue; - else if (bp->type == BKPT_HARD) - /* disable breakpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0); - else - return ERROR_FAIL; - - LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index, - bp->address); - - hbr_index++; - } - - return ERROR_OK; -} - -static int nds32_v2_activate_hardware_watchpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - struct watchpoint *wp; - int32_t wp_num = nds32_v2->next_hbr_index; - uint32_t wp_config = 0; - - for (wp = target->watchpoints; wp; wp = wp->next) { - - wp_num--; - wp->mask = wp->length - 1; - if ((wp->address % wp->length) != 0) - wp->mask = (wp->mask << 1) + 1; - - if (wp->rw == WPT_READ) - wp_config = 0x3; - else if (wp->rw == WPT_WRITE) - wp_config = 0x5; - else if (wp->rw == WPT_ACCESS) - wp_config = 0x7; - - /* set/unset physical address bit of BPCn according to PSW.DT */ - if (nds32_v2->nds32.memory.address_translation == false) - wp_config |= 0x8; - - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num, - wp->address - (wp->address % wp->length)); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask); - /* enable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config); - /* set value */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0); - - LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32, wp_num, - wp->address, wp->mask); - - } - - return ERROR_OK; -} - -static int nds32_v2_deactivate_hardware_watchpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - int32_t wp_num = nds32_v2->next_hbr_index; - struct watchpoint *wp; - - for (wp = target->watchpoints; wp; wp = wp->next) { - wp_num--; - /* disable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0); - - LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32, - wp_num, wp->address, wp->mask); - } - - return ERROR_OK; -} - -static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2) -{ - struct nds32 *nds32 = &(nds32_v2->nds32); - struct aice_port_s *aice = target_to_aice(nds32->target); - uint32_t val_ir0; - uint32_t val_ir1; - uint32_t val_ir2; - uint32_t modified_psw; - - /* Save interrupt level */ - aice_read_register(aice, IR0, &val_ir0); /* get $IR0 directly */ - - /* backup $IR0 */ - nds32_v2->backup_ir0 = val_ir0; - - nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3; - - if (nds32_reach_max_interrupt_level(nds32)) { - LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->", - nds32->current_interrupt_level); - - /* decrease interrupt level */ - modified_psw = val_ir0 - 0x2; - - /* disable GIE, IT, DT, HSS */ - modified_psw &= (~0x8C1); - - aice_write_register(aice, IR0, modified_psw); - - return ERROR_OK; - } - - /* There is a case that single step also trigger another interrupt, - then HSS bit in psw(ir0) will push to ipsw(ir1). - Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2 - Therefore, HSS bit in p_ipsw(ir2) also need clear. - - Only update $ir2 as current interrupt level is 2, because $ir2 will be random - value if the target never reaches interrupt level 2. */ - if ((nds32->max_interrupt_level == 3) && (nds32->current_interrupt_level == 2)) { - aice_read_register(aice, IR2, &val_ir2); /* get $IR2 directly */ - val_ir2 &= ~(0x01 << 11); - aice_write_register(aice, IR2, val_ir2); - } - - /* get original DT bit and set to current state let debugger has same memory view - PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */ - aice_read_register(aice, IR1, &val_ir1); - modified_psw = val_ir0 | (val_ir1 & 0x80); - aice_write_register(aice, IR0, modified_psw); - - return ERROR_OK; -} - -static int nds32_v2_restore_interrupt_stack(struct nds32_v2_common *nds32_v2) -{ - struct nds32 *nds32 = &(nds32_v2->nds32); - struct aice_port_s *aice = target_to_aice(nds32->target); - - /* restore origin $IR0 */ - aice_write_register(aice, IR0, nds32_v2->backup_ir0); - - return ERROR_OK; -} - -/** - * Save processor state. This is called after a HALT instruction - * succeeds, and on other occasions the processor enters debug mode - * (breakpoint, watchpoint, etc). - */ -static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint) -{ - LOG_DEBUG("nds32_v2_debug_entry"); - - if (nds32->virtual_hosting) - LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported " - "under V1/V2 architecture. -->"); - - enum target_state backup_state = nds32->target->state; - nds32->target->state = TARGET_HALTED; - - if (nds32->init_arch_info_after_halted == false) { - /* init architecture info according to config registers */ - CHECK_RETVAL(nds32_config(nds32)); - - nds32->init_arch_info_after_halted = true; - } - - /* REVISIT entire cache should already be invalid !!! */ - register_cache_invalidate(nds32->core_cache); - - /* deactivate all hardware breakpoints */ - CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target)); - - if (enable_watchpoint) - CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target)); - - if (nds32_examine_debug_reason(nds32) != ERROR_OK) { - nds32->target->state = backup_state; - - /* re-activate all hardware breakpoints & watchpoints */ - CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target)); - - if (enable_watchpoint) { - /* activate all watchpoints */ - CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target)); - } - - return ERROR_FAIL; - } - - /* check interrupt level before .full_context(), because - * get_mapped_reg() in nds32_full_context() needs current_interrupt_level - * information */ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target); - nds32_v2_check_interrupt_stack(nds32_v2); - - /* Save registers. */ - nds32_full_context(nds32); - - return ERROR_OK; -} - -/* target request support */ -static int nds32_v2_target_request_data(struct target *target, - uint32_t size, uint8_t *buffer) -{ - /* AndesCore could use DTR register to communicate with OpenOCD - * to output messages - * Target data will be put in buffer - * The format of DTR is as follow - * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd - * target_req_cmd has three possible values: - * TARGET_REQ_TRACEMSG - * TARGET_REQ_DEBUGMSG - * TARGET_REQ_DEBUGCHAR - * if size == 0, target will call target_asciimsg(), - * else call target_hexmsg() - */ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_OK; -} - -/** - * Restore processor state. - */ -static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint) -{ - LOG_DEBUG("nds32_v2_leave_debug_state"); - - struct target *target = nds32->target; - - /* activate all hardware breakpoints */ - CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target)); - - if (enable_watchpoint) { - /* activate all watchpoints */ - CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target)); - } - - /* restore interrupt stack */ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target); - nds32_v2_restore_interrupt_stack(nds32_v2); - - /* restore PSW, PC, and R0 ... after flushing any modified - * registers. - */ - CHECK_RETVAL(nds32_restore_context(target)); - - register_cache_invalidate(nds32->core_cache); - - return ERROR_OK; -} - -static int nds32_v2_deassert_reset(struct target *target) -{ - int retval; - - CHECK_RETVAL(nds32_poll(target)); - - if (target->state != TARGET_HALTED) { - /* reset only */ - LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - retval = target_halt(target); - if (retval != ERROR_OK) - return retval; - } - - return ERROR_OK; -} - -static int nds32_v2_checksum_memory(struct target *target, - target_addr_t address, uint32_t count, uint32_t *checksum) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - -static int nds32_v2_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - struct nds32 *nds32 = &(nds32_v2->nds32); - int result; - - if (breakpoint->type == BKPT_HARD) { - /* check hardware resource */ - if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) { - LOG_WARNING("<-- TARGET WARNING! Insert too many hardware " - "breakpoints/watchpoints! The limit of " - "combined hardware breakpoints/watchpoints " - "is %" PRId32 ". -->", nds32_v2->n_hbr); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware breakpoint */ - nds32_v2->next_hbr_index++; - - /* hardware breakpoint insertion occurs before 'continue' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - result = nds32_add_software_breakpoint(target, breakpoint); - if (result != ERROR_OK) { - /* auto convert to hardware breakpoint if failed */ - if (nds32->auto_convert_hw_bp) { - /* convert to hardware breakpoint */ - breakpoint->type = BKPT_HARD; - - return nds32_v2_add_breakpoint(target, breakpoint); - } - } - - return result; - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v2_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - - if (breakpoint->type == BKPT_HARD) { - if (nds32_v2->next_hbr_index <= 0) - return ERROR_FAIL; - - /* update next place to put hardware breakpoint */ - nds32_v2->next_hbr_index--; - - /* hardware breakpoint removal occurs after 'halted' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - return nds32_remove_software_breakpoint(target, breakpoint); - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v2_add_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - - /* check hardware resource */ - if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) { - LOG_WARNING("<-- TARGET WARNING! Insert too many hardware " - "breakpoints/watchpoints! The limit of " - "combined hardware breakpoints/watchpoints is %" PRId32 ". -->", nds32_v2->n_hbr); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware watchpoint */ - nds32_v2->next_hbr_index++; - - return ERROR_OK; -} - -static int nds32_v2_remove_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - - if (nds32_v2->next_hbr_index <= 0) - return ERROR_FAIL; - - /* update next place to put hardware breakpoint */ - nds32_v2->next_hbr_index--; - - return ERROR_OK; -} - -static int nds32_v2_get_exception_address(struct nds32 *nds32, - uint32_t *address, uint32_t reason) -{ - struct aice_port_s *aice = target_to_aice(nds32->target); - - aice_read_register(aice, IR4, address); /* read $EVA directly */ - - /* TODO: hit multiple watchpoints */ - - return ERROR_OK; -} - -/** - * find out which watchpoint hits - * get exception address and compare the address to watchpoints - */ -static int nds32_v2_hit_watchpoint(struct target *target, - struct watchpoint **hit_watchpoint) -{ - uint32_t exception_address; - struct watchpoint *wp; - static struct watchpoint scan_all_watchpoint; - struct nds32 *nds32 = target_to_nds32(target); - - scan_all_watchpoint.address = 0; - scan_all_watchpoint.rw = WPT_WRITE; - scan_all_watchpoint.next = 0; - scan_all_watchpoint.unique_id = 0x5CA8; - - exception_address = nds32->watched_address; - - if (exception_address == 0) { - /* send watch:0 to tell GDB to do software scan for hitting multiple watchpoints */ - *hit_watchpoint = &scan_all_watchpoint; - return ERROR_OK; - } - - for (wp = target->watchpoints; wp; wp = wp->next) { - if (((exception_address ^ wp->address) & (~wp->mask)) == 0) { - /* TODO: dispel false match */ - *hit_watchpoint = wp; - return ERROR_OK; - } - } - - return ERROR_FAIL; -} - -static int nds32_v2_run_algorithm(struct target *target, - int num_mem_params, - struct mem_param *mem_params, - int num_reg_params, - struct reg_param *reg_params, - target_addr_t entry_point, - target_addr_t exit_point, - int timeout_ms, - void *arch_info) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - -static int nds32_v2_target_create(struct target *target, Jim_Interp *interp) -{ - struct nds32_v2_common *nds32_v2; - - nds32_v2 = calloc(1, sizeof(*nds32_v2)); - if (!nds32_v2) - return ERROR_FAIL; - - nds32_v2->nds32.register_map = nds32_v2_register_mapping; - nds32_v2->nds32.get_debug_reason = nds32_v2_get_debug_reason; - nds32_v2->nds32.enter_debug_state = nds32_v2_debug_entry; - nds32_v2->nds32.leave_debug_state = nds32_v2_leave_debug_state; - nds32_v2->nds32.get_watched_address = nds32_v2_get_exception_address; - - nds32_init_arch_info(target, &(nds32_v2->nds32)); - - return ERROR_OK; -} - -static int nds32_v2_init_target(struct command_context *cmd_ctx, - struct target *target) -{ - /* Initialize anything we can set up without talking to the target */ - - struct nds32 *nds32 = target_to_nds32(target); - - nds32_init(nds32); - - return ERROR_OK; -} - -/* talk to the target and set things up */ -static int nds32_v2_examine(struct target *target) -{ - struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target); - struct nds32 *nds32 = &(nds32_v2->nds32); - struct aice_port_s *aice = target_to_aice(target); - - if (!target_was_examined(target)) { - CHECK_RETVAL(nds32_edm_config(nds32)); - - if (nds32->reset_halt_as_examine) - CHECK_RETVAL(nds32_reset_halt(nds32)); - } - - uint32_t edm_cfg; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); - - /* get the number of hardware breakpoints */ - nds32_v2->n_hbr = (edm_cfg & 0x7) + 1; - - nds32_v2->next_hbr_index = 0; - - LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target), - nds32_v2->n_hbr); - - nds32->target->state = TARGET_RUNNING; - nds32->target->debug_reason = DBG_REASON_NOTHALTED; - - target_set_examined(target); - - return ERROR_OK; -} - -static int nds32_v2_translate_address(struct target *target, target_addr_t *address) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - target_addr_t physical_address; - - /* Following conditions need to do address translation - * 1. BUS mode - * 2. CPU mode under maximum interrupt level */ - if ((memory->access_channel == NDS_MEMORY_ACC_BUS) || - ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - nds32_reach_max_interrupt_level(nds32))) { - if (target->type->virt2phys(target, *address, &physical_address) == ERROR_OK) - *address = physical_address; - else - return ERROR_FAIL; - } - - return ERROR_OK; -} - -static int nds32_v2_read_buffer(struct target *target, target_addr_t address, - uint32_t size, uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - nds32_v2_translate_address(target, &address); - - return nds32_read_buffer(target, address, size, buffer); -} - -static int nds32_v2_write_buffer(struct target *target, target_addr_t address, - uint32_t size, const uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - nds32_v2_translate_address(target, &address); - - return nds32_write_buffer(target, address, size, buffer); -} - -static int nds32_v2_read_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - nds32_v2_translate_address(target, &address); - - return nds32_read_memory(target, address, size, count, buffer); -} - -static int nds32_v2_write_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - nds32_v2_translate_address(target, &address); - - return nds32_write_memory(target, address, size, count, buffer); -} - -/** Holds methods for V2 targets. */ -struct target_type nds32_v2_target = { - .name = "nds32_v2", - - .poll = nds32_poll, - .arch_state = nds32_arch_state, - - .target_request_data = nds32_v2_target_request_data, - - .halt = nds32_halt, - .resume = nds32_resume, - .step = nds32_step, - - .assert_reset = nds32_assert_reset, - .deassert_reset = nds32_v2_deassert_reset, - - /* register access */ - .get_gdb_reg_list = nds32_get_gdb_reg_list, - - /* memory access */ - .read_buffer = nds32_v2_read_buffer, - .write_buffer = nds32_v2_write_buffer, - .read_memory = nds32_v2_read_memory, - .write_memory = nds32_v2_write_memory, - - .checksum_memory = nds32_v2_checksum_memory, - - /* breakpoint/watchpoint */ - .add_breakpoint = nds32_v2_add_breakpoint, - .remove_breakpoint = nds32_v2_remove_breakpoint, - .add_watchpoint = nds32_v2_add_watchpoint, - .remove_watchpoint = nds32_v2_remove_watchpoint, - .hit_watchpoint = nds32_v2_hit_watchpoint, - - /* MMU */ - .mmu = nds32_mmu, - .virt2phys = nds32_virtual_to_physical, - .read_phys_memory = nds32_read_phys_memory, - .write_phys_memory = nds32_write_phys_memory, - - .run_algorithm = nds32_v2_run_algorithm, - - .commands = nds32_command_handlers, - .target_create = nds32_v2_target_create, - .init_target = nds32_v2_init_target, - .examine = nds32_v2_examine, -}; diff --git a/src/target/nds32_v2.h b/src/target/nds32_v2.h deleted file mode 100644 index 3c30108690..0000000000 --- a/src/target/nds32_v2.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_V2_H -#define OPENOCD_TARGET_NDS32_V2_H - -#include "nds32.h" - -struct nds32_v2_common { - struct nds32 nds32; - - uint32_t backup_ir0; - - /** number of hardware breakpoints */ - int32_t n_hbr; - - /** next hardware breakpoint index */ - /** increase from low index to high index */ - int32_t next_hbr_index; -}; - -static inline struct nds32_v2_common *target_to_nds32_v2(struct target *target) -{ - return container_of(target->arch_info, struct nds32_v2_common, nds32); -} - -#endif /* OPENOCD_TARGET_NDS32_V2_H */ diff --git a/src/target/nds32_v3.c b/src/target/nds32_v3.c deleted file mode 100644 index a27c1cc3d2..0000000000 --- a/src/target/nds32_v3.c +++ /dev/null @@ -1,510 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "breakpoints.h" -#include "nds32_cmd.h" -#include "nds32_aice.h" -#include "nds32_v3.h" -#include "nds32_v3_common.h" - -static int nds32_v3_activate_hardware_breakpoint(struct target *target) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - int32_t hbr_index = nds32_v3->next_hbr_index; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) { - /* already set at nds32_v3_add_breakpoint() */ - continue; - } else if (bp->type == BKPT_HARD) { - hbr_index--; - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0); - /* set value */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0); - - if (nds32_v3->nds32.memory.address_translation) - /* enable breakpoint (virtual address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2); - else - /* enable breakpoint (physical address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA); - - LOG_DEBUG("Add hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index, - bp->address); - } else { - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int nds32_v3_deactivate_hardware_breakpoint(struct target *target) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - int32_t hbr_index = nds32_v3->next_hbr_index; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) { - continue; - } else if (bp->type == BKPT_HARD) { - hbr_index--; - /* disable breakpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0); - } else { - return ERROR_FAIL; - } - - LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index, - bp->address); - } - - return ERROR_OK; -} - -static int nds32_v3_activate_hardware_watchpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct watchpoint *wp; - int32_t wp_num = 0; - uint32_t wp_config = 0; - bool ld_stop, st_stop; - - if (nds32_v3->nds32.global_stop) - ld_stop = st_stop = false; - - for (wp = target->watchpoints; wp; wp = wp->next) { - - if (wp_num < nds32_v3->used_n_wp) { - wp->mask = wp->length - 1; - if ((wp->address % wp->length) != 0) - wp->mask = (wp->mask << 1) + 1; - - if (wp->rw == WPT_READ) - wp_config = 0x3; - else if (wp->rw == WPT_WRITE) - wp_config = 0x5; - else if (wp->rw == WPT_ACCESS) - wp_config = 0x7; - - /* set/unset physical address bit of BPCn according to PSW.DT */ - if (nds32_v3->nds32.memory.address_translation == false) - wp_config |= 0x8; - - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num, - wp->address - (wp->address % wp->length)); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask); - /* enable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config); - /* set value */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0); - - LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32, - wp_num, wp->address, wp->mask); - - wp_num++; - } else if (nds32_v3->nds32.global_stop) { - if (wp->rw == WPT_READ) - ld_stop = true; - else if (wp->rw == WPT_WRITE) - st_stop = true; - else if (wp->rw == WPT_ACCESS) - ld_stop = st_stop = true; - } - } - - if (nds32_v3->nds32.global_stop) { - uint32_t edm_ctl; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl); - if (ld_stop) - edm_ctl |= 0x10; - if (st_stop) - edm_ctl |= 0x20; - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl); - } - - return ERROR_OK; -} - -static int nds32_v3_deactivate_hardware_watchpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - int32_t wp_num = 0; - struct watchpoint *wp; - bool clean_global_stop = false; - - for (wp = target->watchpoints; wp; wp = wp->next) { - - if (wp_num < nds32_v3->used_n_wp) { - /* disable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0); - - LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR - " mask %08" PRIx32, wp_num, - wp->address, wp->mask); - wp_num++; - } else if (nds32_v3->nds32.global_stop) { - clean_global_stop = true; - } - } - - if (clean_global_stop) { - uint32_t edm_ctl; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl); - edm_ctl = edm_ctl & (~0x30); - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl); - } - - return ERROR_OK; -} - -static int nds32_v3_check_interrupt_stack(struct nds32 *nds32) -{ - uint32_t val_ir0; - uint32_t value; - - /* Save interrupt level */ - nds32_get_mapped_reg(nds32, IR0, &val_ir0); - nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3; - - if (nds32_reach_max_interrupt_level(nds32)) - LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->", - nds32->current_interrupt_level); - - /* backup $ir4 & $ir6 to avoid suppressed exception overwrite */ - nds32_get_mapped_reg(nds32, IR4, &value); - nds32_get_mapped_reg(nds32, IR6, &value); - - return ERROR_OK; -} - -static int nds32_v3_restore_interrupt_stack(struct nds32 *nds32) -{ - uint32_t value; - - /* get backup value from cache */ - /* then set back to make the register dirty */ - nds32_get_mapped_reg(nds32, IR0, &value); - nds32_set_mapped_reg(nds32, IR0, value); - - nds32_get_mapped_reg(nds32, IR4, &value); - nds32_set_mapped_reg(nds32, IR4, value); - - nds32_get_mapped_reg(nds32, IR6, &value); - nds32_set_mapped_reg(nds32, IR6, value); - - return ERROR_OK; -} - -static int nds32_v3_deassert_reset(struct target *target) -{ - int retval; - struct aice_port_s *aice = target_to_aice(target); - bool switch_to_v3_stack = false; - uint32_t value_edm_ctl; - - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl); - if (((value_edm_ctl >> 6) & 0x1) == 0) { /* reset to V2 EDM mode */ - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, value_edm_ctl | (0x1 << 6)); - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl); - if (((value_edm_ctl >> 6) & 0x1) == 1) - switch_to_v3_stack = true; - } else - switch_to_v3_stack = false; - - CHECK_RETVAL(nds32_poll(target)); - - if (target->state != TARGET_HALTED) { - /* reset only */ - LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - retval = target_halt(target); - if (retval != ERROR_OK) - return retval; - - } else { - /* reset-halt */ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct nds32 *nds32 = &(nds32_v3->nds32); - uint32_t value; - uint32_t interrupt_level; - - if (switch_to_v3_stack == true) { - /* PSW.INTL-- */ - nds32_get_mapped_reg(nds32, IR0, &value); - interrupt_level = (value >> 1) & 0x3; - interrupt_level--; - value &= ~(0x6); - value |= (interrupt_level << 1); - value |= 0x400; /* set PSW.DEX */ - nds32_set_mapped_reg(nds32, IR0, value); - - /* copy IPC to OIPC */ - if ((interrupt_level + 1) < nds32->max_interrupt_level) { - nds32_get_mapped_reg(nds32, IR9, &value); - nds32_set_mapped_reg(nds32, IR11, value); - } - } - } - - return ERROR_OK; -} - -static int nds32_v3_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct nds32 *nds32 = &(nds32_v3->nds32); - int result; - - if (breakpoint->type == BKPT_HARD) { - /* check hardware resource */ - if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) { - LOG_WARNING("<-- TARGET WARNING! Insert too many " - "hardware breakpoints/watchpoints! " - "The limit of combined hardware " - "breakpoints/watchpoints is %" PRId32 ". -->", - nds32_v3->n_hbr); - LOG_WARNING("<-- TARGET STATUS: Inserted number of " - "hardware breakpoint: %" PRId32 ", hardware " - "watchpoints: %" PRId32 ". -->", - nds32_v3->next_hbr_index - nds32_v3->used_n_wp, - nds32_v3->used_n_wp); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware breakpoint */ - nds32_v3->next_hbr_index++; - - /* hardware breakpoint insertion occurs before 'continue' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - result = nds32_add_software_breakpoint(target, breakpoint); - if (result != ERROR_OK) { - /* auto convert to hardware breakpoint if failed */ - if (nds32->auto_convert_hw_bp) { - /* convert to hardware breakpoint */ - breakpoint->type = BKPT_HARD; - - return nds32_v3_add_breakpoint(target, breakpoint); - } - } - - return result; - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v3_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - - if (breakpoint->type == BKPT_HARD) { - if (nds32_v3->next_hbr_index <= 0) - return ERROR_FAIL; - - /* update next place to put hardware breakpoint */ - nds32_v3->next_hbr_index--; - - /* hardware breakpoint removal occurs after 'halted' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - return nds32_remove_software_breakpoint(target, breakpoint); - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v3_add_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - - /* check hardware resource */ - if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) { - /* No hardware resource */ - if (nds32_v3->nds32.global_stop) { - LOG_WARNING("<-- TARGET WARNING! The number of " - "watchpoints exceeds the hardware " - "resources. Stop at every load/store " - "instruction to check for watchpoint matches. -->"); - return ERROR_OK; - } - - LOG_WARNING("<-- TARGET WARNING! Insert too many hardware " - "breakpoints/watchpoints! The limit of combined " - "hardware breakpoints/watchpoints is %" PRId32 ". -->", - nds32_v3->n_hbr); - LOG_WARNING("<-- TARGET STATUS: Inserted number of " - "hardware breakpoint: %" PRId32 ", hardware " - "watchpoints: %" PRId32 ". -->", - nds32_v3->next_hbr_index - nds32_v3->used_n_wp, - nds32_v3->used_n_wp); - - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware watchpoint */ - nds32_v3->next_hbr_index++; - nds32_v3->used_n_wp++; - - return ERROR_OK; -} - -static int nds32_v3_remove_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - - if (nds32_v3->next_hbr_index <= 0) { - if (nds32_v3->nds32.global_stop) - return ERROR_OK; - - return ERROR_FAIL; - } - - /* update next place to put hardware breakpoint */ - nds32_v3->next_hbr_index--; - nds32_v3->used_n_wp--; - - return ERROR_OK; -} - -static struct nds32_v3_common_callback nds32_v3_common_callback = { - .check_interrupt_stack = nds32_v3_check_interrupt_stack, - .restore_interrupt_stack = nds32_v3_restore_interrupt_stack, - .activate_hardware_breakpoint = nds32_v3_activate_hardware_breakpoint, - .activate_hardware_watchpoint = nds32_v3_activate_hardware_watchpoint, - .deactivate_hardware_breakpoint = nds32_v3_deactivate_hardware_breakpoint, - .deactivate_hardware_watchpoint = nds32_v3_deactivate_hardware_watchpoint, -}; - -static int nds32_v3_target_create(struct target *target, Jim_Interp *interp) -{ - struct nds32_v3_common *nds32_v3; - - nds32_v3 = calloc(1, sizeof(*nds32_v3)); - if (!nds32_v3) - return ERROR_FAIL; - - nds32_v3_common_register_callback(&nds32_v3_common_callback); - nds32_v3_target_create_common(target, &(nds32_v3->nds32)); - - return ERROR_OK; -} - -/* talk to the target and set things up */ -static int nds32_v3_examine(struct target *target) -{ - struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target); - struct nds32 *nds32 = &(nds32_v3->nds32); - struct aice_port_s *aice = target_to_aice(target); - - if (!target_was_examined(target)) { - CHECK_RETVAL(nds32_edm_config(nds32)); - - if (nds32->reset_halt_as_examine) - CHECK_RETVAL(nds32_reset_halt(nds32)); - } - - uint32_t edm_cfg; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); - - /* get the number of hardware breakpoints */ - nds32_v3->n_hbr = (edm_cfg & 0x7) + 1; - - /* low interference profiling */ - if (edm_cfg & 0x100) - nds32_v3->low_interference_profile = true; - else - nds32_v3->low_interference_profile = false; - - nds32_v3->next_hbr_index = 0; - nds32_v3->used_n_wp = 0; - - LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target), - nds32_v3->n_hbr); - - nds32->target->state = TARGET_RUNNING; - nds32->target->debug_reason = DBG_REASON_NOTHALTED; - - target_set_examined(target); - - return ERROR_OK; -} - -/** Holds methods for Andes1337 targets. */ -struct target_type nds32_v3_target = { - .name = "nds32_v3", - - .poll = nds32_poll, - .arch_state = nds32_arch_state, - - .target_request_data = nds32_v3_target_request_data, - - .halt = nds32_halt, - .resume = nds32_resume, - .step = nds32_step, - - .assert_reset = nds32_assert_reset, - .deassert_reset = nds32_v3_deassert_reset, - - /* register access */ - .get_gdb_reg_list = nds32_get_gdb_reg_list, - - /* memory access */ - .read_buffer = nds32_v3_read_buffer, - .write_buffer = nds32_v3_write_buffer, - .read_memory = nds32_v3_read_memory, - .write_memory = nds32_v3_write_memory, - - .checksum_memory = nds32_v3_checksum_memory, - - /* breakpoint/watchpoint */ - .add_breakpoint = nds32_v3_add_breakpoint, - .remove_breakpoint = nds32_v3_remove_breakpoint, - .add_watchpoint = nds32_v3_add_watchpoint, - .remove_watchpoint = nds32_v3_remove_watchpoint, - .hit_watchpoint = nds32_v3_hit_watchpoint, - - /* MMU */ - .mmu = nds32_mmu, - .virt2phys = nds32_virtual_to_physical, - .read_phys_memory = nds32_read_phys_memory, - .write_phys_memory = nds32_write_phys_memory, - - .run_algorithm = nds32_v3_run_algorithm, - - .commands = nds32_command_handlers, - .target_create = nds32_v3_target_create, - .init_target = nds32_v3_init_target, - .examine = nds32_v3_examine, - - .get_gdb_fileio_info = nds32_get_gdb_fileio_info, - .gdb_fileio_end = nds32_gdb_fileio_end, - - .profiling = nds32_profiling, -}; diff --git a/src/target/nds32_v3.h b/src/target/nds32_v3.h deleted file mode 100644 index 389838d8fb..0000000000 --- a/src/target/nds32_v3.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_V3_H -#define OPENOCD_TARGET_NDS32_V3_H - -#include "nds32.h" - -struct nds32_v3_common { - struct nds32 nds32; - - /** number of hardware breakpoints */ - int32_t n_hbr; - - /** number of used hardware watchpoints */ - int32_t used_n_wp; - - /** next hardware breakpoint index */ - int32_t next_hbr_index; - - /** low interference profiling */ - bool low_interference_profile; -}; - -static inline struct nds32_v3_common *target_to_nds32_v3(struct target *target) -{ - return container_of(target->arch_info, struct nds32_v3_common, nds32); -} - -#endif /* OPENOCD_TARGET_NDS32_V3_H */ diff --git a/src/target/nds32_v3_common.c b/src/target/nds32_v3_common.c deleted file mode 100644 index 50c7582592..0000000000 --- a/src/target/nds32_v3_common.c +++ /dev/null @@ -1,664 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "breakpoints.h" -#include "nds32_reg.h" -#include "nds32_disassembler.h" -#include "nds32.h" -#include "nds32_aice.h" -#include "nds32_v3_common.h" - -static struct nds32_v3_common_callback *v3_common_callback; - -static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no) -{ - if (reg_no == PC) - return IR11; - - return reg_no; -} - -static int nds32_v3_get_debug_reason(struct nds32 *nds32, uint32_t *reason) -{ - uint32_t edmsw; - struct aice_port_s *aice = target_to_aice(nds32->target); - aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw); - - *reason = (edmsw >> 12) & 0x0F; - - return ERROR_OK; -} - -/** - * Save processor state. This is called after a HALT instruction - * succeeds, and on other occasions the processor enters debug mode - * (breakpoint, watchpoint, etc). - */ -static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint) -{ - LOG_DEBUG("nds32_v3_debug_entry"); - - enum target_state backup_state = nds32->target->state; - nds32->target->state = TARGET_HALTED; - - if (nds32->init_arch_info_after_halted == false) { - /* init architecture info according to config registers */ - CHECK_RETVAL(nds32_config(nds32)); - - nds32->init_arch_info_after_halted = true; - } - - /* REVISIT entire cache should already be invalid !!! */ - register_cache_invalidate(nds32->core_cache); - - /* deactivate all hardware breakpoints */ - CHECK_RETVAL(v3_common_callback->deactivate_hardware_breakpoint(nds32->target)); - - if (enable_watchpoint) - CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target)); - - struct breakpoint *syscall_break = &(nds32->syscall_break); - if (nds32->virtual_hosting) { - if (syscall_break->is_set) { - /** disable virtual hosting */ - - /* remove breakpoint at syscall entry */ - target_remove_breakpoint(nds32->target, syscall_break); - syscall_break->is_set = false; - - uint32_t value_pc; - nds32_get_mapped_reg(nds32, PC, &value_pc); - if (value_pc == syscall_break->address) - /** process syscall for virtual hosting */ - nds32->hit_syscall = true; - } - } - - if (nds32_examine_debug_reason(nds32) != ERROR_OK) { - nds32->target->state = backup_state; - - /* re-activate all hardware breakpoints & watchpoints */ - CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(nds32->target)); - - if (enable_watchpoint) - CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(nds32->target)); - - return ERROR_FAIL; - } - - /* Save registers. */ - nds32_full_context(nds32); - - /* check interrupt level */ - v3_common_callback->check_interrupt_stack(nds32); - - return ERROR_OK; -} - -/** - * Restore processor state. - */ -static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint) -{ - LOG_DEBUG("nds32_v3_leave_debug_state"); - - struct target *target = nds32->target; - - /* activate all hardware breakpoints */ - CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(target)); - - if (enable_watchpoint) { - /* activate all watchpoints */ - CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(target)); - } - - /* restore interrupt stack */ - v3_common_callback->restore_interrupt_stack(nds32); - - /* REVISIT once we start caring about MMU and cache state, - * address it here ... - */ - - /* restore PSW, PC, and R0 ... after flushing any modified - * registers. - */ - CHECK_RETVAL(nds32_restore_context(target)); - - if (nds32->virtual_hosting) { - /** enable virtual hosting */ - uint32_t value_ir3; - uint32_t entry_size; - uint32_t syscall_address; - - /* get syscall entry address */ - nds32_get_mapped_reg(nds32, IR3, &value_ir3); - entry_size = 0x4 << (((value_ir3 >> 14) & 0x3) << 1); - syscall_address = (value_ir3 & 0xFFFF0000) + entry_size * 8; /* The index of SYSCALL is 8 */ - - if (nds32->hit_syscall) { - /* single step to skip syscall entry */ - /* use IRET to skip syscall */ - struct aice_port_s *aice = target_to_aice(target); - uint32_t value_ir9; - uint32_t value_ir6; - uint32_t syscall_id; - - nds32_get_mapped_reg(nds32, IR6, &value_ir6); - syscall_id = (value_ir6 >> 16) & 0x7FFF; - - if (syscall_id == NDS32_SYSCALL_EXIT) { - /* If target hits exit syscall, do not use IRET to skip handler. */ - aice_step(aice); - } else { - /* use api->read/write_reg to skip nds32 register cache */ - uint32_t value_dimbr; - aice_read_debug_reg(aice, NDS_EDM_SR_DIMBR, &value_dimbr); - aice_write_register(aice, IR11, value_dimbr + 0xC); - - aice_read_register(aice, IR9, &value_ir9); - value_ir9 += 4; /* syscall is always 4 bytes */ - aice_write_register(aice, IR9, value_ir9); - - /* backup hardware breakpoint 0 */ - uint32_t backup_bpa, backup_bpam, backup_bpc; - aice_read_debug_reg(aice, NDS_EDM_SR_BPA0, &backup_bpa); - aice_read_debug_reg(aice, NDS_EDM_SR_BPAM0, &backup_bpam); - aice_read_debug_reg(aice, NDS_EDM_SR_BPC0, &backup_bpc); - - /* use hardware breakpoint 0 to stop cpu after skipping syscall */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0, value_ir9); - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0, 0); - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0, 0xA); - - /* Execute two IRET. - * First IRET is used to quit debug mode. - * Second IRET is used to quit current syscall. */ - uint32_t dim_inst[4] = {NOP, NOP, IRET, IRET}; - aice_execute(aice, dim_inst, 4); - - /* restore origin hardware breakpoint 0 */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0, backup_bpa); - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0, backup_bpam); - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0, backup_bpc); - } - - nds32->hit_syscall = false; - } - - /* insert breakpoint at syscall entry */ - struct breakpoint *syscall_break = &(nds32->syscall_break); - - syscall_break->address = syscall_address; - syscall_break->type = BKPT_SOFT; - syscall_break->is_set = true; - target_add_breakpoint(target, syscall_break); - } - - return ERROR_OK; -} - -static int nds32_v3_get_exception_address(struct nds32 *nds32, - uint32_t *address, uint32_t reason) -{ - LOG_DEBUG("nds32_v3_get_exception_address"); - - struct aice_port_s *aice = target_to_aice(nds32->target); - struct target *target = nds32->target; - uint32_t edmsw; - uint32_t edm_cfg; - uint32_t match_bits; - uint32_t match_count; - int32_t i; - static int32_t number_of_hard_break; - uint32_t bp_control; - - if (number_of_hard_break == 0) { - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); - number_of_hard_break = (edm_cfg & 0x7) + 1; - } - - aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw); - /* clear matching bits (write-one-clear) */ - aice_write_debug_reg(aice, NDS_EDM_SR_EDMSW, edmsw); - match_bits = (edmsw >> 4) & 0xFF; - match_count = 0; - for (i = 0 ; i < number_of_hard_break ; i++) { - if (match_bits & (1 << i)) { - aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address); - match_count++; - - /* If target hits multiple read/access watchpoint, - * select the first one. */ - aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &bp_control); - if (0x3 == (bp_control & 0x3)) { - match_count = 1; - break; - } - } - } - - if (match_count > 1) { /* multiple hits */ - *address = 0; - return ERROR_OK; - } else if (match_count == 1) { - uint32_t val_pc; - uint32_t opcode; - struct nds32_instruction instruction; - struct watchpoint *wp; - bool hit; - - nds32_get_mapped_reg(nds32, PC, &val_pc); - - if ((reason == NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE) || - (reason == NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE)) { - if (edmsw & 0x4) /* check EDMSW.IS_16BIT */ - val_pc -= 2; - else - val_pc -= 4; - } - - nds32_read_opcode(nds32, val_pc, &opcode); - nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction); - - LOG_DEBUG("PC: 0x%08" PRIx32 ", access start: 0x%08" PRIx32 ", end: 0x%08" PRIx32, - val_pc, instruction.access_start, instruction.access_end); - - /* check if multiple hits in the access range */ - uint32_t in_range_watch_count = 0; - for (wp = target->watchpoints; wp; wp = wp->next) { - if ((instruction.access_start <= wp->address) && - (wp->address < instruction.access_end)) - in_range_watch_count++; - } - if (in_range_watch_count > 1) { - /* Hit LSMW instruction. */ - *address = 0; - return ERROR_OK; - } - - /* dispel false match */ - hit = false; - for (wp = target->watchpoints; wp; wp = wp->next) { - if (((*address ^ wp->address) & (~wp->mask)) == 0) { - uint32_t watch_start; - uint32_t watch_end; - - watch_start = wp->address; - watch_end = wp->address + wp->length; - - if ((watch_end <= instruction.access_start) || - (instruction.access_end <= watch_start)) - continue; - - hit = true; - break; - } - } - - if (hit) - return ERROR_OK; - else - return ERROR_FAIL; - } else if (match_count == 0) { - /* global stop is precise exception */ - if ((reason == NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP) && nds32->global_stop) { - /* parse instruction to get correct access address */ - uint32_t val_pc; - uint32_t opcode; - struct nds32_instruction instruction; - - nds32_get_mapped_reg(nds32, PC, &val_pc); - nds32_read_opcode(nds32, val_pc, &opcode); - nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction); - - *address = instruction.access_start; - - return ERROR_OK; - } - } - - *address = 0xFFFFFFFF; - return ERROR_FAIL; -} - -void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback) -{ - v3_common_callback = callback; -} - -/** target_type functions: */ -/* target request support */ -int nds32_v3_target_request_data(struct target *target, - uint32_t size, uint8_t *buffer) -{ - /* AndesCore could use DTR register to communicate with OpenOCD - * to output messages - * Target data will be put in buffer - * The format of DTR is as follow - * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd - * target_req_cmd has three possible values: - * TARGET_REQ_TRACEMSG - * TARGET_REQ_DEBUGMSG - * TARGET_REQ_DEBUGCHAR - * if size == 0, target will call target_asciimsg(), - * else call target_hexmsg() - */ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_OK; -} - -int nds32_v3_checksum_memory(struct target *target, - target_addr_t address, uint32_t count, uint32_t *checksum) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - -/** - * find out which watchpoint hits - * get exception address and compare the address to watchpoints - */ -int nds32_v3_hit_watchpoint(struct target *target, - struct watchpoint **hit_watchpoint) -{ - static struct watchpoint scan_all_watchpoint; - - uint32_t exception_address; - struct watchpoint *wp; - struct nds32 *nds32 = target_to_nds32(target); - - exception_address = nds32->watched_address; - - if (exception_address == 0xFFFFFFFF) - return ERROR_FAIL; - - if (exception_address == 0) { - scan_all_watchpoint.address = 0; - scan_all_watchpoint.rw = WPT_WRITE; - scan_all_watchpoint.next = 0; - scan_all_watchpoint.unique_id = 0x5CA8; - - *hit_watchpoint = &scan_all_watchpoint; - return ERROR_OK; - } - - for (wp = target->watchpoints; wp; wp = wp->next) { - if (((exception_address ^ wp->address) & (~wp->mask)) == 0) { - *hit_watchpoint = wp; - - return ERROR_OK; - } - } - - return ERROR_FAIL; -} - -int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32) -{ - nds32->register_map = nds32_v3_register_mapping; - nds32->get_debug_reason = nds32_v3_get_debug_reason; - nds32->enter_debug_state = nds32_v3_debug_entry; - nds32->leave_debug_state = nds32_v3_leave_debug_state; - nds32->get_watched_address = nds32_v3_get_exception_address; - - /* Init target->arch_info in nds32_init_arch_info(). - * After this, user could use target_to_nds32() to get nds32 object */ - nds32_init_arch_info(target, nds32); - - return ERROR_OK; -} - -int nds32_v3_run_algorithm(struct target *target, - int num_mem_params, - struct mem_param *mem_params, - int num_reg_params, - struct reg_param *reg_params, - target_addr_t entry_point, - target_addr_t exit_point, - int timeout_ms, - void *arch_info) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - -int nds32_v3_read_buffer(struct target *target, target_addr_t address, - uint32_t size, uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - target_addr_t physical_address; - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - /* When DEX is set to one, hardware will enforce the following behavior without - * modifying the corresponding control bits in PSW. - * - * Disable all interrupts - * Become superuser mode - * Turn off IT/DT - * Use MMU_CFG.DE as the data access endian - * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted - * Disable audio special features - * Disable inline function call - * - * Because hardware will turn off IT/DT by default, it MUST translate virtual address - * to physical address. - */ - if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) - address = physical_address; - else - return ERROR_FAIL; - - int result; - struct aice_port_s *aice = target_to_aice(target); - /* give arbitrary initial value to avoid warning messages */ - enum nds_memory_access origin_access_channel = NDS_MEMORY_ACC_CPU; - - if (nds32->hit_syscall) { - /* Use bus mode to access memory during virtual hosting */ - origin_access_channel = memory->access_channel; - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, NDS_MEMORY_ACC_BUS); - } - - result = nds32_read_buffer(target, address, size, buffer); - - if (nds32->hit_syscall) { - /* Restore access_channel after virtual hosting */ - memory->access_channel = origin_access_channel; - aice_memory_access(aice, origin_access_channel); - } - - return result; -} - -int nds32_v3_write_buffer(struct target *target, target_addr_t address, - uint32_t size, const uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - target_addr_t physical_address; - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - /* When DEX is set to one, hardware will enforce the following behavior without - * modifying the corresponding control bits in PSW. - * - * Disable all interrupts - * Become superuser mode - * Turn off IT/DT - * Use MMU_CFG.DE as the data access endian - * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted - * Disable audio special features - * Disable inline function call - * - * Because hardware will turn off IT/DT by default, it MUST translate virtual address - * to physical address. - */ - if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) - address = physical_address; - else - return ERROR_FAIL; - - if (nds32->hit_syscall) { - struct aice_port_s *aice = target_to_aice(target); - enum nds_memory_access origin_access_channel; - origin_access_channel = memory->access_channel; - - /* If target has no cache, use BUS mode to access memory. */ - if ((memory->dcache.line_size == 0) - || (memory->dcache.enable == false)) { - /* There is no Dcache or Dcache is disabled. */ - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, NDS_MEMORY_ACC_BUS); - } - - int result; - result = nds32_gdb_fileio_write_memory(nds32, address, size, buffer); - - if (origin_access_channel == NDS_MEMORY_ACC_CPU) { - memory->access_channel = NDS_MEMORY_ACC_CPU; - aice_memory_access(aice, NDS_MEMORY_ACC_CPU); - } - - return result; - } - - return nds32_write_buffer(target, address, size, buffer); -} - -int nds32_v3_read_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - target_addr_t physical_address; - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - /* When DEX is set to one, hardware will enforce the following behavior without - * modifying the corresponding control bits in PSW. - * - * Disable all interrupts - * Become superuser mode - * Turn off IT/DT - * Use MMU_CFG.DE as the data access endian - * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted - * Disable audio special features - * Disable inline function call - * - * Because hardware will turn off IT/DT by default, it MUST translate virtual address - * to physical address. - */ - if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) - address = physical_address; - else - return ERROR_FAIL; - - struct aice_port_s *aice = target_to_aice(target); - /* give arbitrary initial value to avoid warning messages */ - enum nds_memory_access origin_access_channel = NDS_MEMORY_ACC_CPU; - int result; - - if (nds32->hit_syscall) { - /* Use bus mode to access memory during virtual hosting */ - origin_access_channel = memory->access_channel; - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, NDS_MEMORY_ACC_BUS); - } - - result = nds32_read_memory(target, address, size, count, buffer); - - if (nds32->hit_syscall) { - /* Restore access_channel after virtual hosting */ - memory->access_channel = origin_access_channel; - aice_memory_access(aice, origin_access_channel); - } - - return result; -} - -int nds32_v3_write_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) -{ - struct nds32 *nds32 = target_to_nds32(target); - struct nds32_memory *memory = &(nds32->memory); - - if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && - (target->state != TARGET_HALTED)) { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - target_addr_t physical_address; - /* BUG: If access range crosses multiple pages, the translation will not correct - * for second page or so. */ - - /* When DEX is set to one, hardware will enforce the following behavior without - * modifying the corresponding control bits in PSW. - * - * Disable all interrupts - * Become superuser mode - * Turn off IT/DT - * Use MMU_CFG.DE as the data access endian - * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted - * Disable audio special features - * Disable inline function call - * - * Because hardware will turn off IT/DT by default, it MUST translate virtual address - * to physical address. - */ - if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) - address = physical_address; - else - return ERROR_FAIL; - - return nds32_write_memory(target, address, size, count, buffer); -} - -int nds32_v3_init_target(struct command_context *cmd_ctx, - struct target *target) -{ - /* Initialize anything we can set up without talking to the target */ - struct nds32 *nds32 = target_to_nds32(target); - - nds32_init(nds32); - - target->fileio_info = malloc(sizeof(struct gdb_fileio_info)); - target->fileio_info->identifier = NULL; - - return ERROR_OK; -} diff --git a/src/target/nds32_v3_common.h b/src/target/nds32_v3_common.h deleted file mode 100644 index a98988e5a9..0000000000 --- a/src/target/nds32_v3_common.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_V3_COMMON_H -#define OPENOCD_TARGET_NDS32_V3_COMMON_H - -#include "target.h" - -struct nds32_v3_common_callback { - int (*check_interrupt_stack)(struct nds32 *nds32); - int (*restore_interrupt_stack)(struct nds32 *nds32); - int (*activate_hardware_breakpoint)(struct target *target); - int (*activate_hardware_watchpoint)(struct target *target); - int (*deactivate_hardware_breakpoint)(struct target *target); - int (*deactivate_hardware_watchpoint)(struct target *target); -}; - -void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback); -int nds32_v3_target_request_data(struct target *target, - uint32_t size, uint8_t *buffer); -int nds32_v3_checksum_memory(struct target *target, - target_addr_t address, uint32_t count, uint32_t *checksum); -int nds32_v3_hit_watchpoint(struct target *target, - struct watchpoint **hit_watchpoint); -int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32); -int nds32_v3_run_algorithm(struct target *target, - int num_mem_params, - struct mem_param *mem_params, - int num_reg_params, - struct reg_param *reg_params, - target_addr_t entry_point, - target_addr_t exit_point, - int timeout_ms, - void *arch_info); -int nds32_v3_read_buffer(struct target *target, target_addr_t address, - uint32_t size, uint8_t *buffer); -int nds32_v3_write_buffer(struct target *target, target_addr_t address, - uint32_t size, const uint8_t *buffer); -int nds32_v3_read_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, uint8_t *buffer); -int nds32_v3_write_memory(struct target *target, target_addr_t address, - uint32_t size, uint32_t count, const uint8_t *buffer); -int nds32_v3_init_target(struct command_context *cmd_ctx, - struct target *target); - -#endif /* OPENOCD_TARGET_NDS32_V3_COMMON_H */ diff --git a/src/target/nds32_v3m.c b/src/target/nds32_v3m.c deleted file mode 100644 index 4ea1d38ac5..0000000000 --- a/src/target/nds32_v3m.c +++ /dev/null @@ -1,495 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "breakpoints.h" -#include "nds32_cmd.h" -#include "nds32_aice.h" -#include "nds32_v3m.h" -#include "nds32_v3_common.h" - -static int nds32_v3m_activate_hardware_breakpoint(struct target *target) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - unsigned brp_num = nds32_v3m->n_hbr - 1; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) { - /* already set at nds32_v3m_add_breakpoint() */ - continue; - } else if (bp->type == BKPT_HARD) { - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + brp_num, bp->address); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + brp_num, 0); - - if (nds32_v3m->nds32.memory.address_translation) - /* enable breakpoint (virtual address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x2); - else - /* enable breakpoint (physical address) */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0xA); - - LOG_DEBUG("Add hardware BP %u at %08" TARGET_PRIxADDR, brp_num, - bp->address); - - brp_num--; - } else { - return ERROR_FAIL; - } - } - - return ERROR_OK; -} - -static int nds32_v3m_deactivate_hardware_breakpoint(struct target *target) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct aice_port_s *aice = target_to_aice(target); - struct breakpoint *bp; - unsigned brp_num = nds32_v3m->n_hbr - 1; - - for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->type == BKPT_SOFT) - continue; - else if (bp->type == BKPT_HARD) - /* disable breakpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x0); - else - return ERROR_FAIL; - - LOG_DEBUG("Remove hardware BP %u at %08" TARGET_PRIxADDR, brp_num, - bp->address); - - brp_num--; - } - - return ERROR_OK; -} - -static int nds32_v3m_activate_hardware_watchpoint(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct watchpoint *wp; - int32_t wp_num = 0; - uint32_t wp_config = 0; - bool ld_stop, st_stop; - - if (nds32_v3m->nds32.global_stop) - ld_stop = st_stop = false; - - for (wp = target->watchpoints; wp; wp = wp->next) { - - if (wp_num < nds32_v3m->used_n_wp) { - wp->mask = wp->length - 1; - if ((wp->address % wp->length) != 0) - wp->mask = (wp->mask << 1) + 1; - - if (wp->rw == WPT_READ) - wp_config = 0x3; - else if (wp->rw == WPT_WRITE) - wp_config = 0x5; - else if (wp->rw == WPT_ACCESS) - wp_config = 0x7; - - /* set/unset physical address bit of BPCn according to PSW.DT */ - if (nds32_v3m->nds32.memory.address_translation == false) - wp_config |= 0x8; - - /* set address */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num, - wp->address - (wp->address % wp->length)); - /* set mask */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask); - /* enable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config); - - LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR - " mask %08" PRIx32, wp_num, wp->address, wp->mask); - - wp_num++; - } else if (nds32_v3m->nds32.global_stop) { - if (wp->rw == WPT_READ) - ld_stop = true; - else if (wp->rw == WPT_WRITE) - st_stop = true; - else if (wp->rw == WPT_ACCESS) - ld_stop = st_stop = true; - } - } - - if (nds32_v3m->nds32.global_stop) { - uint32_t edm_ctl; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl); - if (ld_stop) - edm_ctl |= 0x10; - if (st_stop) - edm_ctl |= 0x20; - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl); - } - - return ERROR_OK; -} - -static int nds32_v3m_deactivate_hardware_watchpoint(struct target *target) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct aice_port_s *aice = target_to_aice(target); - struct watchpoint *wp; - int32_t wp_num = 0; - bool clean_global_stop = false; - - for (wp = target->watchpoints; wp; wp = wp->next) { - - if (wp_num < nds32_v3m->used_n_wp) { - /* disable watchpoint */ - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0); - - LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR - " mask %08" PRIx32, wp_num, wp->address, wp->mask); - wp_num++; - } else if (nds32_v3m->nds32.global_stop) { - clean_global_stop = true; - } - } - - if (clean_global_stop) { - uint32_t edm_ctl; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl); - edm_ctl = edm_ctl & (~0x30); - aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl); - } - - return ERROR_OK; -} - -static int nds32_v3m_check_interrupt_stack(struct nds32 *nds32) -{ - uint32_t val_ir0; - uint32_t value; - - /* Save interrupt level */ - nds32_get_mapped_reg(nds32, IR0, &val_ir0); - nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3; - - if (nds32_reach_max_interrupt_level(nds32)) - LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->", - nds32->current_interrupt_level); - - /* backup $ir6 to avoid suppressed exception overwrite */ - nds32_get_mapped_reg(nds32, IR6, &value); - - return ERROR_OK; -} - -static int nds32_v3m_restore_interrupt_stack(struct nds32 *nds32) -{ - uint32_t value; - - /* get backup value from cache */ - /* then set back to make the register dirty */ - nds32_get_mapped_reg(nds32, IR0, &value); - nds32_set_mapped_reg(nds32, IR0, value); - - nds32_get_mapped_reg(nds32, IR6, &value); - nds32_set_mapped_reg(nds32, IR6, value); - - return ERROR_OK; -} - -static int nds32_v3m_deassert_reset(struct target *target) -{ - int retval; - - CHECK_RETVAL(nds32_poll(target)); - - if (target->state != TARGET_HALTED) { - /* reset only */ - LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - retval = target_halt(target); - if (retval != ERROR_OK) - return retval; - - } - - return ERROR_OK; -} - -static int nds32_v3m_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct nds32 *nds32 = &(nds32_v3m->nds32); - int result; - - if (breakpoint->type == BKPT_HARD) { - /* check hardware resource */ - if (nds32_v3m->next_hbr_index < nds32_v3m->next_hwp_index) { - LOG_WARNING("<-- TARGET WARNING! Insert too many " - "hardware breakpoints/watchpoints! " - "The limit of combined hardware " - "breakpoints/watchpoints is %" PRId32 ". -->", - nds32_v3m->n_hbr); - LOG_WARNING("<-- TARGET STATUS: Inserted number of " - "hardware breakpoint: %" PRId32 ", hardware " - "watchpoints: %" PRId32 ". -->", - nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1, - nds32_v3m->used_n_wp); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware breakpoint */ - nds32_v3m->next_hbr_index--; - - /* hardware breakpoint insertion occurs before 'continue' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - result = nds32_add_software_breakpoint(target, breakpoint); - if (result != ERROR_OK) { - /* auto convert to hardware breakpoint if failed */ - if (nds32->auto_convert_hw_bp) { - /* convert to hardware breakpoint */ - breakpoint->type = BKPT_HARD; - - return nds32_v3m_add_breakpoint(target, breakpoint); - } - } - - return result; - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v3m_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - - if (breakpoint->type == BKPT_HARD) { - if (nds32_v3m->next_hbr_index >= nds32_v3m->n_hbr - 1) - return ERROR_FAIL; - - /* update next place to put hardware breakpoint */ - nds32_v3m->next_hbr_index++; - - /* hardware breakpoint removal occurs after 'halted' actually */ - return ERROR_OK; - } else if (breakpoint->type == BKPT_SOFT) { - return nds32_remove_software_breakpoint(target, breakpoint); - } else /* unrecognized breakpoint type */ - return ERROR_FAIL; - - return ERROR_OK; -} - -static int nds32_v3m_add_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - - /* check hardware resource */ - if (nds32_v3m->next_hwp_index >= nds32_v3m->n_hwp) { - /* No hardware resource */ - if (nds32_v3m->nds32.global_stop) { - LOG_WARNING("<-- TARGET WARNING! The number of " - "watchpoints exceeds the hardware " - "resources. Stop at every load/store " - "instruction to check for watchpoint matches. -->"); - return ERROR_OK; - } - - LOG_WARNING("<-- TARGET WARNING! Insert too many hardware " - "watchpoints! The limit of hardware watchpoints " - "is %" PRId32 ". -->", nds32_v3m->n_hwp); - LOG_WARNING("<-- TARGET STATUS: Inserted number of " - "hardware watchpoint: %" PRId32 ". -->", - nds32_v3m->used_n_wp); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - if (nds32_v3m->next_hwp_index > nds32_v3m->next_hbr_index) { - /* No hardware resource */ - if (nds32_v3m->nds32.global_stop) { - LOG_WARNING("<-- TARGET WARNING! The number of " - "watchpoints exceeds the hardware " - "resources. Stop at every load/store " - "instruction to check for watchpoint matches. -->"); - return ERROR_OK; - } - - LOG_WARNING("<-- TARGET WARNING! Insert too many hardware " - "breakpoints/watchpoints! The limit of combined " - "hardware breakpoints/watchpoints is %" PRId32 ". -->", - nds32_v3m->n_hbr); - LOG_WARNING("<-- TARGET STATUS: Inserted number of " - "hardware breakpoint: %" PRId32 ", hardware " - "watchpoints: %" PRId32 ". -->", - nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1, - nds32_v3m->used_n_wp); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* update next place to put hardware watchpoint */ - nds32_v3m->next_hwp_index++; - nds32_v3m->used_n_wp++; - - return ERROR_OK; -} - -static int nds32_v3m_remove_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - - if (nds32_v3m->next_hwp_index <= 0) { - if (nds32_v3m->nds32.global_stop) - return ERROR_OK; - - return ERROR_FAIL; - } - - /* update next place to put hardware watchpoint */ - nds32_v3m->next_hwp_index--; - nds32_v3m->used_n_wp--; - - return ERROR_OK; -} - -static struct nds32_v3_common_callback nds32_v3m_common_callback = { - .check_interrupt_stack = nds32_v3m_check_interrupt_stack, - .restore_interrupt_stack = nds32_v3m_restore_interrupt_stack, - .activate_hardware_breakpoint = nds32_v3m_activate_hardware_breakpoint, - .activate_hardware_watchpoint = nds32_v3m_activate_hardware_watchpoint, - .deactivate_hardware_breakpoint = nds32_v3m_deactivate_hardware_breakpoint, - .deactivate_hardware_watchpoint = nds32_v3m_deactivate_hardware_watchpoint, -}; - -static int nds32_v3m_target_create(struct target *target, Jim_Interp *interp) -{ - struct nds32_v3m_common *nds32_v3m; - - nds32_v3m = calloc(1, sizeof(*nds32_v3m)); - if (!nds32_v3m) - return ERROR_FAIL; - - nds32_v3_common_register_callback(&nds32_v3m_common_callback); - nds32_v3_target_create_common(target, &(nds32_v3m->nds32)); - - return ERROR_OK; -} - -/* talk to the target and set things up */ -static int nds32_v3m_examine(struct target *target) -{ - struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target); - struct nds32 *nds32 = &(nds32_v3m->nds32); - struct aice_port_s *aice = target_to_aice(target); - - if (!target_was_examined(target)) { - CHECK_RETVAL(nds32_edm_config(nds32)); - - if (nds32->reset_halt_as_examine) - CHECK_RETVAL(nds32_reset_halt(nds32)); - } - - uint32_t edm_cfg; - aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); - - /* get the number of hardware breakpoints */ - nds32_v3m->n_hbr = (edm_cfg & 0x7) + 1; - nds32_v3m->used_n_wp = 0; - - /* get the number of hardware watchpoints */ - /* If the WP field is hardwired to zero, it means this is a - * simple breakpoint. Otherwise, if the WP field is writable - * then it means this is a regular watchpoints. */ - nds32_v3m->n_hwp = 0; - for (int32_t i = 0 ; i < nds32_v3m->n_hbr ; i++) { - /** check the hardware breakpoint is simple or not */ - uint32_t tmp_value; - aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + i, 0x1); - aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &tmp_value); - - if (tmp_value) - nds32_v3m->n_hwp++; - } - /* hardware breakpoint is inserted from high index to low index */ - nds32_v3m->next_hbr_index = nds32_v3m->n_hbr - 1; - /* hardware watchpoint is inserted from low index to high index */ - nds32_v3m->next_hwp_index = 0; - - LOG_INFO("%s: total hardware breakpoint %" PRId32 " (simple breakpoint %" PRId32 ")", - target_name(target), nds32_v3m->n_hbr, nds32_v3m->n_hbr - nds32_v3m->n_hwp); - LOG_INFO("%s: total hardware watchpoint %" PRId32, target_name(target), nds32_v3m->n_hwp); - - nds32->target->state = TARGET_RUNNING; - nds32->target->debug_reason = DBG_REASON_NOTHALTED; - - target_set_examined(target); - - return ERROR_OK; -} - -/** Holds methods for NDS32 V3m targets. */ -struct target_type nds32_v3m_target = { - .name = "nds32_v3m", - - .poll = nds32_poll, - .arch_state = nds32_arch_state, - - .target_request_data = nds32_v3_target_request_data, - - .halt = nds32_halt, - .resume = nds32_resume, - .step = nds32_step, - - .assert_reset = nds32_assert_reset, - .deassert_reset = nds32_v3m_deassert_reset, - - /* register access */ - .get_gdb_reg_list = nds32_get_gdb_reg_list, - - /* memory access */ - .read_buffer = nds32_v3_read_buffer, - .write_buffer = nds32_v3_write_buffer, - .read_memory = nds32_v3_read_memory, - .write_memory = nds32_v3_write_memory, - - .checksum_memory = nds32_v3_checksum_memory, - - /* breakpoint/watchpoint */ - .add_breakpoint = nds32_v3m_add_breakpoint, - .remove_breakpoint = nds32_v3m_remove_breakpoint, - .add_watchpoint = nds32_v3m_add_watchpoint, - .remove_watchpoint = nds32_v3m_remove_watchpoint, - .hit_watchpoint = nds32_v3_hit_watchpoint, - - /* MMU */ - .mmu = nds32_mmu, - .virt2phys = nds32_virtual_to_physical, - .read_phys_memory = nds32_read_phys_memory, - .write_phys_memory = nds32_write_phys_memory, - - .run_algorithm = nds32_v3_run_algorithm, - - .commands = nds32_command_handlers, - .target_create = nds32_v3m_target_create, - .init_target = nds32_v3_init_target, - .examine = nds32_v3m_examine, - - .get_gdb_fileio_info = nds32_get_gdb_fileio_info, - .gdb_fileio_end = nds32_gdb_fileio_end, -}; diff --git a/src/target/nds32_v3m.h b/src/target/nds32_v3m.h deleted file mode 100644 index f21dd62c51..0000000000 --- a/src/target/nds32_v3m.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2013 Andes Technology * - * Hsiangkai Wang <hkwang@andestech.com> * - ***************************************************************************/ - -#ifndef OPENOCD_TARGET_NDS32_V3M_H -#define OPENOCD_TARGET_NDS32_V3M_H - -#include "nds32.h" - -struct nds32_v3m_common { - struct nds32 nds32; - - /** number of hardware breakpoints */ - int32_t n_hbr; - - /** number of hardware watchpoints */ - int32_t n_hwp; - - /** number of used hardware watchpoints */ - int32_t used_n_wp; - - /** next hardware breakpoint index */ - /** for simple breakpoints, hardware breakpoints are inserted - * from high index to low index */ - int32_t next_hbr_index; - - /** next hardware watchpoint index */ - /** increase from low index to high index */ - int32_t next_hwp_index; -}; - -static inline struct nds32_v3m_common *target_to_nds32_v3m(struct target *target) -{ - return container_of(target->arch_info, struct nds32_v3m_common, nds32); -} - -#endif /* OPENOCD_TARGET_NDS32_V3M_H */ diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c index 50bef5e7a2..185a506c45 100644 --- a/src/target/openrisc/jsp_server.c +++ b/src/target/openrisc/jsp_server.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2014 by Franck Jullien * diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c index 06367ffdf1..4aa2bd7347 100644 --- a/src/target/openrisc/or1k.c +++ b/src/target/openrisc/or1k.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2011 by Julius Baxter * @@ -27,8 +27,8 @@ #include "or1k.h" #include "or1k_du.h" -LIST_HEAD(tap_list); -LIST_HEAD(du_list); +OOCD_LIST_HEAD(tap_list); +OOCD_LIST_HEAD(du_list); static int or1k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); @@ -775,9 +775,9 @@ static bool is_any_soft_breakpoint(struct target *target) return false; } -static int or1k_resume_or_step(struct target *target, int current, - uint32_t address, int handle_breakpoints, - int debug_execution, int step) +static int or1k_resume_or_step(struct target *target, bool current, + uint32_t address, bool handle_breakpoints, bool debug_execution, + int step) { struct or1k_common *or1k = target_to_or1k(target); struct or1k_du *du_core = or1k_to_du(or1k); @@ -789,7 +789,7 @@ static int or1k_resume_or_step(struct target *target, int current, address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no"); if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -885,9 +885,8 @@ static int or1k_resume_or_step(struct target *target, int current, return ERROR_OK; } -static int or1k_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, - int debug_execution) +static int or1k_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { return or1k_resume_or_step(target, current, address, handle_breakpoints, @@ -895,12 +894,12 @@ static int or1k_resume(struct target *target, int current, NO_SINGLE_STEP); } -static int or1k_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int or1k_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { return or1k_resume_or_step(target, current, address, handle_breakpoints, - 0, + false, SINGLE_STEP); } @@ -1026,7 +1025,7 @@ static int or1k_read_memory(struct target *target, target_addr_t address, LOG_DEBUG("Read memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1053,7 +1052,7 @@ static int or1k_write_memory(struct target *target, target_addr_t address, LOG_DEBUG("Write memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("Target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1098,7 +1097,7 @@ static int or1k_init_target(struct command_context *cmd_ctx, return ERROR_OK; } -static int or1k_target_create(struct target *target, Jim_Interp *interp) +static int or1k_target_create(struct target *target) { if (!target->tap) return ERROR_FAIL; @@ -1216,7 +1215,7 @@ static int or1k_profiling(struct target *target, uint32_t *samples, /* Make sure the target is running */ target_poll(target); if (target->state == TARGET_HALTED) - retval = target_resume(target, 1, 0, 0, 0); + retval = target_resume(target, true, 0, false, false); if (retval != ERROR_OK) { LOG_ERROR("Error while resuming target"); diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c index 3d20496575..f401ea9fb5 100644 --- a/src/target/openrisc/or1k_du_adv.c +++ b/src/target/openrisc/or1k_du_adv.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013-2014 by Franck Jullien * @@ -22,8 +22,9 @@ #include "or1k_du.h" #include "jsp_server.h" -#include <target/target.h> +#include <helper/crc32.h> #include <jtag/jtag.h> +#include <target/target.h> #define JSP_BANNER "\n\r" \ "******************************\n\r" \ @@ -67,13 +68,6 @@ #define DBG_CPU_CR_STALL 0x01 #define DBG_CPU_CR_RESET 0x02 -/* Polynomial for the CRC calculation - * Yes, it's backwards. Yes, this is on purpose. - * The hardware is designed this way to save on logic and routing, - * and it's really all the same to us here. - */ -#define ADBG_CRC_POLY 0xedb88320 - /* These are for the internal registers in the Wishbone module * The first is the length of the index register, * the indexes of the various registers are defined after that. @@ -133,20 +127,6 @@ static struct or1k_du or1k_du_adv; static const char * const chain_name[] = {"WISHBONE", "CPU0", "CPU1", "JSP"}; -static uint32_t adbg_compute_crc(uint32_t crc, uint32_t data_in, - int length_bits) -{ - for (int i = 0; i < length_bits; i++) { - uint32_t d, c; - d = ((data_in >> i) & 0x1) ? 0xffffffff : 0; - c = (crc & 0x1) ? 0xffffffff : 0; - crc = crc >> 1; - crc = crc ^ ((d ^ c) & ADBG_CRC_POLY); - } - - return crc; -} - static int find_status_bit(void *_buf, int len) { int i = 0; @@ -382,7 +362,7 @@ static int adbg_ctrl_read(struct or1k_jtag *jtag_info, uint32_t regidx, default: LOG_ERROR("Illegal debug chain selected (%i) while doing control read", jtag_info->or1k_jtag_module_selected); - return ERROR_FAIL; + return ERROR_FAIL; } /* Zero MSB = op for module, not top-level debug unit */ @@ -522,9 +502,8 @@ static int adbg_wb_burst_read(struct or1k_jtag *jtag_info, int size, memcpy(data, in_buffer, total_size_bytes); memcpy(&crc_read, &in_buffer[total_size_bytes], 4); - uint32_t crc_calc = 0xffffffff; - for (int i = 0; i < total_size_bytes; i++) - crc_calc = adbg_compute_crc(crc_calc, data[i], 8); + uint32_t crc_calc = crc32_le(CRC32_POLY_LE, 0xffffffff, data, + total_size_bytes); if (crc_calc != crc_read) { LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32 ", read CRC 0x%08" PRIx32, crc_calc, crc_read); @@ -650,9 +629,8 @@ static int adbg_wb_burst_write(struct or1k_jtag *jtag_info, const uint8_t *data, field[0].out_value = &value; field[0].in_value = NULL; - uint32_t crc_calc = 0xffffffff; - for (int i = 0; i < (count * size); i++) - crc_calc = adbg_compute_crc(crc_calc, data[i], 8); + uint32_t crc_calc = crc32_le(CRC32_POLY_LE, 0xffffffff, data, + count * size); field[1].num_bits = count * size * 8; field[1].out_value = data; @@ -934,7 +912,7 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info, void *t = NULL; struct target *target = jtag_info->target; if ((target->endianness == TARGET_BIG_ENDIAN) && (size != 1)) { - t = malloc(count * size * sizeof(uint8_t)); + t = calloc(count * size, sizeof(uint8_t)); if (!t) { LOG_ERROR("Out of memory"); return ERROR_FAIL; @@ -947,6 +925,9 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info, case 2: buf_bswap16(t, buffer, size * count); break; + default: + free(t); + return ERROR_TARGET_FAILURE; } buffer = t; } diff --git a/src/target/openrisc/or1k_tap_mohor.c b/src/target/openrisc/or1k_tap_mohor.c index 4d9e158c72..0dedb3e754 100644 --- a/src/target/openrisc/or1k_tap_mohor.c +++ b/src/target/openrisc/or1k_tap_mohor.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Franck Jullien * diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c index 4b16e97793..783b4dbd1e 100644 --- a/src/target/openrisc/or1k_tap_vjtag.c +++ b/src/target/openrisc/or1k_tap_vjtag.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Franck Jullien * diff --git a/src/target/openrisc/or1k_tap_xilinx_bscan.c b/src/target/openrisc/or1k_tap_xilinx_bscan.c index ec66b77530..6b3df0e1e9 100644 --- a/src/target/openrisc/or1k_tap_xilinx_bscan.c +++ b/src/target/openrisc/or1k_tap_xilinx_bscan.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2013 by Sergio Chico * diff --git a/src/target/quark_d20xx.c b/src/target/quark_d20xx.c index 70d6c61230..931f0dab7d 100644 --- a/src/target/quark_d20xx.c +++ b/src/target/quark_d20xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright(c) 2015-2016 Intel Corporation. @@ -32,7 +32,7 @@ #include "lakemont.h" #include "x86_32_common.h" -static int quark_d20xx_target_create(struct target *t, Jim_Interp *interp) +static int quark_d20xx_target_create(struct target *t) { struct x86_32_common *x86_32 = calloc(1, sizeof(struct x86_32_common)); if (!x86_32) { @@ -65,7 +65,7 @@ static int quark_d20xx_reset_deassert(struct target *t) } /* resume target if reset mode is run */ if (!t->reset_halt) { - retval = lakemont_resume(t, 1, 0, 0, 0); + retval = lakemont_resume(t, true, 0, false, false); if (retval != ERROR_OK) { LOG_ERROR("%s could not resume target", __func__); return retval; diff --git a/src/target/quark_x10xx.c b/src/target/quark_x10xx.c index 5cfdb00716..2abc32ab7b 100644 --- a/src/target/quark_x10xx.c +++ b/src/target/quark_x10xx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright(c) 2013-2016 Intel Corporation. @@ -40,7 +40,7 @@ #include "lakemont.h" #include "x86_32_common.h" -static int quark_x10xx_target_create(struct target *t, Jim_Interp *interp) +static int quark_x10xx_target_create(struct target *t) { struct x86_32_common *x86_32 = calloc(1, sizeof(*x86_32)); diff --git a/src/target/register.c b/src/target/register.c index f05e58a878..e4f22f8e93 100644 --- a/src/target/register.c +++ b/src/target/register.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -93,9 +93,8 @@ void register_unlink_cache(struct reg_cache **cache_p, const struct reg_cache *c /** Marks the contents of the register cache as invalid (and clean). */ void register_cache_invalidate(struct reg_cache *cache) { - struct reg *reg = cache->reg_list; - - for (unsigned int n = cache->num_regs; n != 0; n--, reg++) { + for (unsigned int n = 0; n < cache->num_regs; n++) { + struct reg *reg = &cache->reg_list[n]; if (!reg->exist) continue; reg->valid = false; diff --git a/src/target/register.h b/src/target/register.h index 1e4f2e0889..b9af401b4c 100644 --- a/src/target/register.h +++ b/src/target/register.h @@ -145,7 +145,7 @@ struct reg_cache { const char *name; struct reg_cache *next; struct reg *reg_list; - unsigned num_regs; + unsigned int num_regs; }; struct reg_arch_type { diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c index a3d68a91f3..e3f8ff3d4b 100644 --- a/src/target/riscv/batch.c +++ b/src/target/riscv/batch.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #ifdef HAVE_CONFIG_H #include "config.h" @@ -115,8 +115,10 @@ int riscv_batch_run(struct riscv_batch *batch) if (bscan_tunnel_ir_width != 0) { /* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */ - for (size_t i = 0; i < batch->used_scans; ++i) - buffer_shr((batch->fields + i)->in_value, DMI_SCAN_BUF_SIZE, 1); + for (size_t i = 0; i < batch->used_scans; ++i) { + if ((batch->fields + i)->in_value) + buffer_shr((batch->fields + i)->in_value, DMI_SCAN_BUF_SIZE, 1); + } } for (size_t i = 0; i < batch->used_scans; ++i) @@ -125,7 +127,7 @@ int riscv_batch_run(struct riscv_batch *batch) return ERROR_OK; } -void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data) +void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data) { assert(batch->used_scans < batch->allocated_scans); struct scan_field *field = batch->fields + batch->used_scans; @@ -138,7 +140,7 @@ void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint batch->used_scans++; } -size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address) +size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned int address) { assert(batch->used_scans < batch->allocated_scans); struct scan_field *field = batch->fields + batch->used_scans; @@ -154,14 +156,14 @@ size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address) return batch->read_keys_used++; } -unsigned riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key) +uint32_t riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key) { assert(key < batch->read_keys_used); size_t index = batch->read_keys[key]; assert(index <= batch->used_scans); uint8_t *base = batch->data_in + DMI_SCAN_BUF_SIZE * index; /* extract "op" field from the DMI read result */ - return (unsigned)buf_get_u32(base, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH); + return buf_get_u32(base, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH); } uint32_t riscv_batch_get_dmi_read_data(struct riscv_batch *batch, size_t key) @@ -209,12 +211,12 @@ void dump_field(int idle, const struct scan_field *field) log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, __PRETTY_FUNCTION__, - "%db %s %08x @%02x -> %s %08x @%02x; %di", + "%ub %s %08x @%02x -> %s %08x @%02x; %di", field->num_bits, op_string[out_op], out_data, out_address, status_string[in_op], in_data, in_address, idle); } else { log_printf_lf(LOG_LVL_DEBUG, - __FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?; %di", + __FILE__, __LINE__, __PRETTY_FUNCTION__, "%ub %s %08x @%02x -> ?; %di", field->num_bits, op_string[out_op], out_data, out_address, idle); } } diff --git a/src/target/riscv/batch.h b/src/target/riscv/batch.h index 9c42ba81ea..537fa59233 100644 --- a/src/target/riscv/batch.h +++ b/src/target/riscv/batch.h @@ -59,13 +59,13 @@ bool riscv_batch_full(struct riscv_batch *batch); int riscv_batch_run(struct riscv_batch *batch); /* Adds a DMI write to this batch. */ -void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data); +void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data); /* DMI reads must be handled in two parts: the first one schedules a read and * provides a key, the second one actually obtains the result of the read - * status (op) and the actual data. */ -size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address); -unsigned riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key); +size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned int address); +uint32_t riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key); uint32_t riscv_batch_get_dmi_read_data(struct riscv_batch *batch, size_t key); /* Scans in a NOP. */ diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 5c9eef4eaf..8113d47664 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -1,22 +1,21 @@ /* * This file is auto-generated by running 'make debug_defines.h' in - * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7) - * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0) + * https://github.com/riscv/riscv-debug-spec/ (d749752) */ #define DTM_IDCODE 0x01 /* * Identifies the release version of this part. */ -#define DTM_IDCODE_VERSION_OFFSET 28 +#define DTM_IDCODE_VERSION_OFFSET 0x1c #define DTM_IDCODE_VERSION_LENGTH 4 -#define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET) +#define DTM_IDCODE_VERSION 0xf0000000U /* * Identifies the designer's part number of this part. */ -#define DTM_IDCODE_PARTNUMBER_OFFSET 12 -#define DTM_IDCODE_PARTNUMBER_LENGTH 16 -#define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET) +#define DTM_IDCODE_PARTNUMBER_OFFSET 0xc +#define DTM_IDCODE_PARTNUMBER_LENGTH 0x10 +#define DTM_IDCODE_PARTNUMBER 0xffff000 /* * Identifies the designer/manufacturer of this part. Bits 6:0 must be * bits 6:0 of the designer/manufacturer's Identification Code as @@ -25,11 +24,11 @@ * Identification Code. */ #define DTM_IDCODE_MANUFID_OFFSET 1 -#define DTM_IDCODE_MANUFID_LENGTH 11 -#define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET) +#define DTM_IDCODE_MANUFID_LENGTH 0xb +#define DTM_IDCODE_MANUFID 0xffe #define DTM_IDCODE_1_OFFSET 0 #define DTM_IDCODE_1_LENGTH 1 -#define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET) +#define DTM_IDCODE_1 1 #define DTM_DTMCS 0x10 /* * Writing 1 to this bit does a hard reset of the DTM, @@ -40,16 +39,16 @@ * complete (e.g. a reset condition caused an inflight DMI transaction to * be cancelled). */ -#define DTM_DTMCS_DMIHARDRESET_OFFSET 17 +#define DTM_DTMCS_DMIHARDRESET_OFFSET 0x11 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 -#define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET) +#define DTM_DTMCS_DMIHARDRESET 0x20000 /* * Writing 1 to this bit clears the sticky error state, but does * not affect outstanding DMI transactions. */ -#define DTM_DTMCS_DMIRESET_OFFSET 16 +#define DTM_DTMCS_DMIRESET_OFFSET 0x10 #define DTM_DTMCS_DMIRESET_LENGTH 1 -#define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET) +#define DTM_DTMCS_DMIRESET 0x10000 /* * This is a hint to the debugger of the minimum number of * cycles a debugger should spend in @@ -65,76 +64,89 @@ * * And so on. */ -#define DTM_DTMCS_IDLE_OFFSET 12 +#define DTM_DTMCS_IDLE_OFFSET 0xc #define DTM_DTMCS_IDLE_LENGTH 3 -#define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET) +#define DTM_DTMCS_IDLE 0x7000 /* - * 0: No error. - * - * 1: Reserved. Interpret the same as 2. - * - * 2: An operation failed (resulted in \FdtmDmiOp of 2). - * - * 3: An operation was attempted while a DMI access was still in - * progress (resulted in \FdtmDmiOp of 3). + * Read-only alias of \FdtmDmiOp. */ -#define DTM_DTMCS_DMISTAT_OFFSET 10 +#define DTM_DTMCS_DMISTAT_OFFSET 0xa #define DTM_DTMCS_DMISTAT_LENGTH 2 -#define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET) +#define DTM_DTMCS_DMISTAT 0xc00 /* * The size of \FdmSbaddressZeroAddress in \RdtmDmi. */ #define DTM_DTMCS_ABITS_OFFSET 4 #define DTM_DTMCS_ABITS_LENGTH 6 -#define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET) -/* - * 0: Version described in spec version 0.11. - * - * 1: Version described in spec versions 0.13 and 1.0. - * - * 15: Version not described in any available version of this spec. - */ +#define DTM_DTMCS_ABITS 0x3f0 #define DTM_DTMCS_VERSION_OFFSET 0 #define DTM_DTMCS_VERSION_LENGTH 4 -#define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET) +#define DTM_DTMCS_VERSION 0xf +/* + * 0.11: Version described in spec version 0.11. + */ +#define DTM_DTMCS_VERSION_0_11 0 +/* + * 1.0: Version described in spec versions 0.13 and 1.0. + */ +#define DTM_DTMCS_VERSION_1_0 1 +/* + * custom: Version not described in any available version of this spec. + */ +#define DTM_DTMCS_VERSION_CUSTOM 15 #define DTM_DMI 0x11 /* * Address used for DMI access. In Update-DR this value is used * to access the DM over the DMI. */ -#define DTM_DMI_ADDRESS_OFFSET 34 -#define DTM_DMI_ADDRESS_LENGTH abits -#define DTM_DMI_ADDRESS (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET) +#define DTM_DMI_ADDRESS_OFFSET 0x22 +#define DTM_DMI_ADDRESS_LENGTH(abits) abits +#define DTM_DMI_ADDRESS(abits) ((0x400000000ULL * (1ULL<<abits)) + -0x400000000ULL) /* * The data to send to the DM over the DMI during Update-DR, and * the data returned from the DM as a result of the previous operation. */ #define DTM_DMI_DATA_OFFSET 2 -#define DTM_DMI_DATA_LENGTH 32 -#define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET) +#define DTM_DMI_DATA_LENGTH 0x20 +#define DTM_DMI_DATA 0x3fffffffcULL /* * When the debugger writes this field, it has the following meaning: - * - * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop) + */ +#define DTM_DMI_OP_OFFSET 0 +#define DTM_DMI_OP_LENGTH 2 +#define DTM_DMI_OP 3 +/* + * nop: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. * * Don't send anything over the DMI during Update-DR. * This operation should never result in a busy or error response. * The address and data reported in the following Capture-DR * are undefined. - * - * 1: Read from \FdmSbaddressZeroAddress. (read) - * - * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write) - * - * 3: Reserved. - * + */ +#define DTM_DMI_OP_NOP 0 +/* + * read: Read from \FdmSbaddressZeroAddress. + */ +#define DTM_DMI_OP_READ 1 +/* + * write: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. + */ +#define DTM_DMI_OP_WRITE 2 +/* + * reserved: Reserved. + */ +/* * When the debugger reads this field, it means the following: - * - * 0: The previous operation completed successfully. - * - * 1: Reserved. - * - * 2: A previous operation failed. The data scanned into \RdtmDmi in + */ +/* + * success: The previous operation completed successfully. + */ +#define DTM_DMI_OP_SUCCESS 0 +/* + * reserved: Reserved. + */ +/* + * failed: A previous operation failed. The data scanned into \RdtmDmi in * this access will be ignored. This status is sticky and can be * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs. * @@ -142,8 +154,10 @@ * There are no specified cases in which the DM would * respond with an error, and DMI is not required to support * returning errors. - * - * 3: An operation was attempted while a DMI request is still in + */ +#define DTM_DMI_OP_FAILED 2 +/* + * busy: An operation was attempted while a DMI request is still in * progress. The data scanned into \RdtmDmi in this access will be * ignored. This status is sticky and can be cleared by writing * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it @@ -151,160 +165,212 @@ * Capture-DR. The simplest way to do that is to add extra transitions * in Run-Test/Idle. */ -#define DTM_DMI_OP_OFFSET 0 -#define DTM_DMI_OP_LENGTH 2 -#define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET) +#define DTM_DMI_OP_BUSY 3 #define CSR_DCSR 0x7b0 +#define CSR_DCSR_DEBUGVER_OFFSET 0x1c +#define CSR_DCSR_DEBUGVER_LENGTH 4 +#define CSR_DCSR_DEBUGVER 0xf0000000U /* - * 0: There is no debug support. - * - * 4: Debug support exists as it is described in this document. - * - * 15: There is debug support, but it does not conform to any - * available version of this spec. + * none: There is no debug support. */ -#define CSR_DCSR_DEBUGVER_OFFSET 28 -#define CSR_DCSR_DEBUGVER_LENGTH 4 -#define CSR_DCSR_DEBUGVER (0xfU << CSR_DCSR_DEBUGVER_OFFSET) +#define CSR_DCSR_DEBUGVER_NONE 0 /* - * 0: {\tt ebreak} instructions in VS-mode behave as described in the - * Privileged Spec. - * - * 1: {\tt ebreak} instructions in VS-mode enter Debug Mode. - * - * This bit is hardwired to 0 if the hart does not support virtualization mode. + * 1.0: Debug support exists as it is described in this document. + */ +#define CSR_DCSR_DEBUGVER_1_0 4 +/* + * custom: There is debug support, but it does not conform to any + * available version of this spec. */ -#define CSR_DCSR_EBREAKVS_OFFSET 17 +#define CSR_DCSR_DEBUGVER_CUSTOM 15 +#define CSR_DCSR_EBREAKVS_OFFSET 0x11 #define CSR_DCSR_EBREAKVS_LENGTH 1 -#define CSR_DCSR_EBREAKVS (0x1U << CSR_DCSR_EBREAKVS_OFFSET) +#define CSR_DCSR_EBREAKVS 0x20000 /* - * 0: {\tt ebreak} instructions in VU-mode behave as described in the + * exception: {\tt ebreak} instructions in VS-mode behave as described in the * Privileged Spec. - * - * 1: {\tt ebreak} instructions in VU-mode enter Debug Mode. - * + */ +#define CSR_DCSR_EBREAKVS_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in VS-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKVS_DEBUG_MODE 1 +/* * This bit is hardwired to 0 if the hart does not support virtualization mode. */ -#define CSR_DCSR_EBREAKVU_OFFSET 16 +#define CSR_DCSR_EBREAKVU_OFFSET 0x10 #define CSR_DCSR_EBREAKVU_LENGTH 1 -#define CSR_DCSR_EBREAKVU (0x1U << CSR_DCSR_EBREAKVU_OFFSET) +#define CSR_DCSR_EBREAKVU 0x10000 /* - * 0: {\tt ebreak} instructions in M-mode behave as described in the + * exception: {\tt ebreak} instructions in VU-mode behave as described in the * Privileged Spec. - * - * 1: {\tt ebreak} instructions in M-mode enter Debug Mode. */ -#define CSR_DCSR_EBREAKM_OFFSET 15 +#define CSR_DCSR_EBREAKVU_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in VU-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKVU_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support virtualization mode. + */ +#define CSR_DCSR_EBREAKM_OFFSET 0xf #define CSR_DCSR_EBREAKM_LENGTH 1 -#define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET) +#define CSR_DCSR_EBREAKM 0x8000 /* - * 0: {\tt ebreak} instructions in S-mode behave as described in the + * exception: {\tt ebreak} instructions in M-mode behave as described in the * Privileged Spec. - * - * 1: {\tt ebreak} instructions in S-mode enter Debug Mode. - * - * This bit is hardwired to 0 if the hart does not support S-mode. */ -#define CSR_DCSR_EBREAKS_OFFSET 13 +#define CSR_DCSR_EBREAKM_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in M-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKM_DEBUG_MODE 1 +#define CSR_DCSR_EBREAKS_OFFSET 0xd #define CSR_DCSR_EBREAKS_LENGTH 1 -#define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET) +#define CSR_DCSR_EBREAKS 0x2000 /* - * 0: {\tt ebreak} instructions in U-mode behave as described in the + * exception: {\tt ebreak} instructions in S-mode behave as described in the * Privileged Spec. - * - * 1: {\tt ebreak} instructions in U-mode enter Debug Mode. - * - * This bit is hardwired to 0 if the hart does not support U-mode. */ -#define CSR_DCSR_EBREAKU_OFFSET 12 +#define CSR_DCSR_EBREAKS_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in S-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKS_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support S-mode. + */ +#define CSR_DCSR_EBREAKU_OFFSET 0xc #define CSR_DCSR_EBREAKU_LENGTH 1 -#define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET) +#define CSR_DCSR_EBREAKU 0x1000 +/* + * exception: {\tt ebreak} instructions in U-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKU_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in U-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKU_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support U-mode. + */ +#define CSR_DCSR_STEPIE_OFFSET 0xb +#define CSR_DCSR_STEPIE_LENGTH 1 +#define CSR_DCSR_STEPIE 0x800 +/* + * interrupts disabled: Interrupts (including NMI) are disabled during single stepping. + */ +#define CSR_DCSR_STEPIE_INTERRUPTS_DISABLED 0 +/* + * interrupts enabled: Interrupts (including NMI) are enabled during single stepping. + */ +#define CSR_DCSR_STEPIE_INTERRUPTS_ENABLED 1 /* - * 0: Interrupts (including NMI) are disabled during single stepping. - * - * 1: Interrupts (including NMI) are enabled during single stepping. - * * Implementations may hard wire this bit to 0. * In that case interrupt behavior can be emulated by the debugger. * * The debugger must not change the value of this bit while the hart * is running. */ -#define CSR_DCSR_STEPIE_OFFSET 11 -#define CSR_DCSR_STEPIE_LENGTH 1 -#define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET) +#define CSR_DCSR_STOPCOUNT_OFFSET 0xa +#define CSR_DCSR_STOPCOUNT_LENGTH 1 +#define CSR_DCSR_STOPCOUNT 0x400 /* - * 0: Increment counters as usual. - * - * 1: Don't increment any hart-local counters while in Debug Mode or + * normal: Increment counters as usual. + */ +#define CSR_DCSR_STOPCOUNT_NORMAL 0 +/* + * freeze: Don't increment any hart-local counters while in Debug Mode or * on {\tt ebreak} instructions that cause entry into Debug Mode. * These counters include the {\tt instret} CSR. On single-hart cores * {\tt cycle} should be stopped, but on multi-hart cores it must keep * incrementing. - * - * An implementation may hardwire this bit to 0 or 1. */ -#define CSR_DCSR_STOPCOUNT_OFFSET 10 -#define CSR_DCSR_STOPCOUNT_LENGTH 1 -#define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET) +#define CSR_DCSR_STOPCOUNT_FREEZE 1 /* - * 0: Increment timers as usual. - * - * 1: Don't increment any hart-local timers while in Debug Mode. - * * An implementation may hardwire this bit to 0 or 1. */ #define CSR_DCSR_STOPTIME_OFFSET 9 #define CSR_DCSR_STOPTIME_LENGTH 1 -#define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET) +#define CSR_DCSR_STOPTIME 0x200 +/* + * normal: Increment \Rtime as usual. + */ +#define CSR_DCSR_STOPTIME_NORMAL 0 +/* + * freeze: Don't increment \Rtime while in Debug Mode. If all harts + * have \FcsrDcsrStoptime=1 and are in Debug Mode then \Rmtime + * is also allowed to stop incrementing. + */ +#define CSR_DCSR_STOPTIME_FREEZE 1 +/* + * An implementation may hardwire this bit to 0 or 1. + */ /* * Explains why Debug Mode was entered. * * When there are multiple reasons to enter Debug Mode in a single * cycle, hardware should set \FcsrDcsrCause to the cause with the highest - * priority. - * - * 1: An {\tt ebreak} instruction was executed. (priority 3) - * - * 2: A Trigger Module trigger fired with action=0. (priority 4) - * - * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. - * (priority 1) - * - * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest) - * - * 5: The hart halted directly out of reset due to \Fresethaltreq. It - * is also acceptable to report 3 when this happens. (priority 2) - * - * 6: The hart halted because it's part of a halt group. (priority 5, - * highest) Harts may report 3 for this cause instead. - * - * Other values are reserved for future use. + * priority. See table~\ref{tab:dcsrcausepriority} for priorities. */ #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 -#define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) +#define CSR_DCSR_CAUSE 0x1c0 +/* + * ebreak: An {\tt ebreak} instruction was executed. + */ +#define CSR_DCSR_CAUSE_EBREAK 1 +/* + * trigger: A Trigger Module trigger fired with action=1. + */ +#define CSR_DCSR_CAUSE_TRIGGER 2 +/* + * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. + */ +#define CSR_DCSR_CAUSE_HALTREQ 3 +/* + * step: The hart single stepped because \FcsrDcsrStep was set. + */ +#define CSR_DCSR_CAUSE_STEP 4 +/* + * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It + * is also acceptable to report 3 when this happens. + */ +#define CSR_DCSR_CAUSE_RESETHALTREQ 5 +/* + * group: The hart halted because it's part of a halt group. + * Harts may report 3 for this cause instead. + */ +#define CSR_DCSR_CAUSE_GROUP 6 +/* + * Other values are reserved for future use. + */ /* * Extends the prv field with the virtualization mode the hart was operating * in when Debug Mode was entered. The encoding is described in Table - * \ref{tab:privlevel}. + * \ref{tab:privmode}. * A debugger can change this value to change the hart's virtualization mode * when exiting Debug Mode. * This bit is hardwired to 0 on harts that do not support virtualization mode. */ #define CSR_DCSR_V_OFFSET 5 #define CSR_DCSR_V_LENGTH 1 -#define CSR_DCSR_V (0x1U << CSR_DCSR_V_OFFSET) +#define CSR_DCSR_V 0x20 +#define CSR_DCSR_MPRVEN_OFFSET 4 +#define CSR_DCSR_MPRVEN_LENGTH 1 +#define CSR_DCSR_MPRVEN 0x10 +/* + * disabled: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_DISABLED 0 +/* + * enabled: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_ENABLED 1 /* - * 0: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode. - * - * 1: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode. - * * Implementing this bit is optional. It may be tied to either 0 or 1. */ -#define CSR_DCSR_MPRVEN_OFFSET 4 -#define CSR_DCSR_MPRVEN_LENGTH 1 -#define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET) /* * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. * @@ -314,7 +380,7 @@ */ #define CSR_DCSR_NMIP_OFFSET 3 #define CSR_DCSR_NMIP_LENGTH 1 -#define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET) +#define CSR_DCSR_NMIP 8 /* * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. See Section~\ref{stepBit} @@ -325,101 +391,130 @@ */ #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 -#define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET) +#define CSR_DCSR_STEP 4 /* - * Contains the privilege level the hart was operating in when Debug + * Contains the privilege mode the hart was operating in when Debug * Mode was entered. The encoding is described in Table - * \ref{tab:privlevel}. A debugger can change this value to change - * the hart's privilege level when exiting Debug Mode. + * \ref{tab:privmode}. A debugger can change this value to change + * the hart's privilege mode when exiting Debug Mode. * - * Not all privilege levels are supported on all harts. If the + * Not all privilege modes are supported on all harts. If the * encoding written is not supported or the debugger is not allowed to - * change to it, the hart may change to any supported privilege level. + * change to it, the hart may change to any supported privilege mode. */ #define CSR_DCSR_PRV_OFFSET 0 #define CSR_DCSR_PRV_LENGTH 2 -#define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET) +#define CSR_DCSR_PRV 3 #define CSR_DPC 0x7b1 #define CSR_DPC_DPC_OFFSET 0 -#define CSR_DPC_DPC_LENGTH DXLEN -#define CSR_DPC_DPC (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET) +#define CSR_DPC_DPC_LENGTH(DXLEN) DXLEN +#define CSR_DPC_DPC(DXLEN) ((1ULL<<DXLEN) + -1) #define CSR_DSCRATCH0 0x7b2 #define CSR_DSCRATCH1 0x7b3 #define CSR_TSELECT 0x7a0 #define CSR_TSELECT_INDEX_OFFSET 0 -#define CSR_TSELECT_INDEX_LENGTH XLEN -#define CSR_TSELECT_INDEX (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET) +#define CSR_TSELECT_INDEX_LENGTH(XLEN) XLEN +#define CSR_TSELECT_INDEX(XLEN) ((1ULL<<XLEN) + -1) #define CSR_TDATA1 0x7a1 +#define CSR_TDATA1_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_TDATA1_TYPE_LENGTH 4 +#define CSR_TDATA1_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) /* - * 0: There is no trigger at this \RcsrTselect. - * - * 1: The trigger is a legacy SiFive address match trigger. These + * none: There is no trigger at this \RcsrTselect. + */ +#define CSR_TDATA1_TYPE_NONE 0 +/* + * legacy: The trigger is a legacy SiFive address match trigger. These * should not be implemented and aren't further documented here. - * - * 2: The trigger is an address/data match trigger. The remaining bits + */ +#define CSR_TDATA1_TYPE_LEGACY 1 +/* + * mcontrol: The trigger is an address/data match trigger. The remaining bits * in this register act as described in \RcsrMcontrol. - * - * 3: The trigger is an instruction count trigger. The remaining bits + */ +#define CSR_TDATA1_TYPE_MCONTROL 2 +/* + * icount: The trigger is an instruction count trigger. The remaining bits * in this register act as described in \RcsrIcount. - * - * 4: The trigger is an interrupt trigger. The remaining bits + */ +#define CSR_TDATA1_TYPE_ICOUNT 3 +/* + * itrigger: The trigger is an interrupt trigger. The remaining bits * in this register act as described in \RcsrItrigger. - * - * 5: The trigger is an exception trigger. The remaining bits + */ +#define CSR_TDATA1_TYPE_ITRIGGER 4 +/* + * etrigger: The trigger is an exception trigger. The remaining bits * in this register act as described in \RcsrEtrigger. - * - * 6: The trigger is an address/data match trigger. The remaining bits + */ +#define CSR_TDATA1_TYPE_ETRIGGER 5 +/* + * mcontrol6: The trigger is an address/data match trigger. The remaining bits * in this register act as described in \RcsrMcontrolSix. This is similar * to a type 2 trigger, but provides additional functionality and * should be used instead of type 2 in newer implementations. - * - * 7: The trigger is a trigger source external to the TM. The + */ +#define CSR_TDATA1_TYPE_MCONTROL6 6 +/* + * tmexttrigger: The trigger is a trigger source external to the TM. The * remaining bits in this register act as described in \RcsrTmexttrigger. - * - * 12--14: These trigger types are available for non-standard use. - * - * 15: This trigger exists (so enumeration shouldn't terminate), but - * is not currently available. - * + */ +#define CSR_TDATA1_TYPE_TMEXTTRIGGER 7 +/* + * custom: These trigger types are available for non-standard use. + */ +#define CSR_TDATA1_TYPE_CUSTOM_LOW 12 +#define CSR_TDATA1_TYPE_CUSTOM_HIGH 14 +/* + * disabled: This trigger is disabled. In this state, \RcsrTdataTwo and + * \RcsrTdataThree can be written with any value that is supported for + * any of the types this trigger implements. The remaining bits in this + * register are ignored. + */ +#define CSR_TDATA1_TYPE_DISABLED 15 +/* * Other values are reserved for future use. */ -#define CSR_TDATA1_TYPE_OFFSET (XLEN-4) -#define CSR_TDATA1_TYPE_LENGTH 4 -#define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET) /* * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0. - * - * 0: Both Debug and M-mode can write the {\tt tdata} registers at the + */ +#define CSR_TDATA1_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_TDATA1_DMODE_LENGTH 1 +#define CSR_TDATA1_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * both: Both Debug and M-mode can write the {\tt tdata} registers at the * selected \RcsrTselect. - * - * 1: Only Debug Mode can write the {\tt tdata} registers at the + */ +#define CSR_TDATA1_DMODE_BOTH 0 +/* + * dmode: Only Debug Mode can write the {\tt tdata} registers at the * selected \RcsrTselect. Writes from other modes are ignored. - * + */ +#define CSR_TDATA1_DMODE_DMODE 1 +/* * This bit is only writable from Debug Mode. * In ordinary use, external debuggers will always set this bit when * configuring a trigger. - * When clearing this bit, debuggers should also clear the action field - * (whose location depends on \FcsrTdataOneType). + * When clearing this bit, debuggers should also set the action field + * (whose location depends on \FcsrTdataOneType) to something other + * than 1. */ -#define CSR_TDATA1_DMODE_OFFSET (XLEN-5) -#define CSR_TDATA1_DMODE_LENGTH 1 -#define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET) /* * If \FcsrTdataOneType is 0, then this field is hard-wired to 0. * * Trigger-specific data. */ #define CSR_TDATA1_DATA_OFFSET 0 -#define CSR_TDATA1_DATA_LENGTH (XLEN - 5) -#define CSR_TDATA1_DATA (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET) +#define CSR_TDATA1_DATA_LENGTH(XLEN) (XLEN + -5) +#define CSR_TDATA1_DATA(XLEN) ((1ULL<<(XLEN + -5)) + -1) #define CSR_TDATA2 0x7a2 #define CSR_TDATA2_DATA_OFFSET 0 -#define CSR_TDATA2_DATA_LENGTH XLEN -#define CSR_TDATA2_DATA (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET) +#define CSR_TDATA2_DATA_LENGTH(XLEN) XLEN +#define CSR_TDATA2_DATA(XLEN) ((1ULL<<XLEN) + -1) #define CSR_TDATA3 0x7a3 #define CSR_TDATA3_DATA_OFFSET 0 -#define CSR_TDATA3_DATA_LENGTH XLEN -#define CSR_TDATA3_DATA (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET) +#define CSR_TDATA3_DATA_LENGTH(XLEN) XLEN +#define CSR_TDATA3_DATA(XLEN) ((1ULL<<XLEN) + -1) #define CSR_TINFO 0x7a4 /* * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N @@ -430,32 +525,9 @@ * contains 1. */ #define CSR_TINFO_INFO_OFFSET 0 -#define CSR_TINFO_INFO_LENGTH 16 -#define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET) +#define CSR_TINFO_INFO_LENGTH 0x10 +#define CSR_TINFO_INFO 0xffff #define CSR_TCONTROL 0x7a5 -/* - * \RcsrHcontext enable. - * - * 0: \RcsrHcontext is set to 0 and writes are ignored. - * - * 1: \RcsrHcontext may be written and read. - */ -#define CSR_TCONTROL_HCXE_OFFSET 9 -#define CSR_TCONTROL_HCXE_LENGTH 1 -#define CSR_TCONTROL_HCXE (0x1ULL << CSR_TCONTROL_HCXE_OFFSET) -/* - * \RcsrScontext enable. - * - * 0: \RcsrScontext is set to 0 and writes are ignored. - * - * 1: \RcsrScontext may be written and read. - * - * Enabling \RcsrScontext can be a security risk in a - * virtualized system with a hypervisor that does not swap \RcsrScontext. - */ -#define CSR_TCONTROL_SCXE_OFFSET 8 -#define CSR_TCONTROL_SCXE_LENGTH 1 -#define CSR_TCONTROL_SCXE (0x1ULL << CSR_TCONTROL_SCXE_OFFSET) /* * M-mode previous trigger enable field. * @@ -463,25 +535,30 @@ * regarding triggers with action=0 firing in M-mode trap handlers. See * Section~\ref{sec:nativetrigger} for more details. * - * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of + * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of * \FcsrTcontrolMte. */ #define CSR_TCONTROL_MPTE_OFFSET 7 #define CSR_TCONTROL_MPTE_LENGTH 1 -#define CSR_TCONTROL_MPTE (0x1ULL << CSR_TCONTROL_MPTE_OFFSET) +#define CSR_TCONTROL_MPTE 0x80 /* * M-mode trigger enable field. - * - * 0: Triggers with action=0 do not match/fire while the hart is in M-mode. - * - * 1: Triggers do match/fire while the hart is in M-mode. - * - * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt - * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. */ #define CSR_TCONTROL_MTE_OFFSET 3 #define CSR_TCONTROL_MTE_LENGTH 1 -#define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET) +#define CSR_TCONTROL_MTE 8 +/* + * disabled: Triggers with action=0 do not match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_DISABLED 0 +/* + * enabled: Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_ENABLED 1 +/* + * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt + * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. + */ #define CSR_HCONTEXT 0x6a8 /* * Hypervisor mode software can write a context number to this register, @@ -496,8 +573,8 @@ * and 14 on RV64. */ #define CSR_HCONTEXT_HCONTEXT_OFFSET 0 -#define CSR_HCONTEXT_HCONTEXT_LENGTH XLEN -#define CSR_HCONTEXT_HCONTEXT (((1L << XLEN) - 1) << CSR_HCONTEXT_HCONTEXT_OFFSET) +#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN) XLEN +#define CSR_HCONTEXT_HCONTEXT(XLEN) ((1ULL<<XLEN) + -1) #define CSR_SCONTEXT 0x5a8 /* * Supervisor mode software can write a context number to this @@ -509,17 +586,17 @@ * 34 on RV64. */ #define CSR_SCONTEXT_DATA_OFFSET 0 -#define CSR_SCONTEXT_DATA_LENGTH XLEN -#define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET) +#define CSR_SCONTEXT_DATA_LENGTH(XLEN) XLEN +#define CSR_SCONTEXT_DATA(XLEN) ((1ULL<<XLEN) + -1) #define CSR_MCONTEXT 0x7a8 #define CSR_MSCONTEXT 0x7aa #define CSR_MCONTROL 0x7a1 -#define CSR_MCONTROL_TYPE_OFFSET (XLEN-4) +#define CSR_MCONTROL_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_MCONTROL_TYPE_LENGTH 4 -#define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET) -#define CSR_MCONTROL_DMODE_OFFSET (XLEN-5) +#define CSR_MCONTROL_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_MCONTROL_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_MCONTROL_DMODE_LENGTH 1 -#define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET) +#define CSR_MCONTROL_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * Specifies the largest naturally aligned powers-of-two (NAPOT) range * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the @@ -528,18 +605,18 @@ * A value of 63 corresponds to the maximum NAPOT range, which is * $2^{63}$ bytes in size. */ -#define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11) +#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) (XLEN + -0xb) #define CSR_MCONTROL_MASKMAX_LENGTH 6 -#define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) +#define CSR_MCONTROL_MASKMAX(XLEN) (0x3f * (1ULL<<(XLEN + -0xb))) /* * This field only exists when XLEN is at least 64. * It contains the 2 high bits of the access size. The low bits * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this * is used. */ -#define CSR_MCONTROL_SIZEHI_OFFSET 21 +#define CSR_MCONTROL_SIZEHI_OFFSET 0x15 #define CSR_MCONTROL_SIZEHI_LENGTH 2 -#define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET) +#define CSR_MCONTROL_SIZEHI 0x600000 /* * If this bit is implemented then it must become set when this * trigger fires and may become set when this trigger matches. @@ -548,28 +625,35 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_MCONTROL_HIT_OFFSET 20 +#define CSR_MCONTROL_HIT_OFFSET 0x14 #define CSR_MCONTROL_HIT_LENGTH 1 -#define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET) +#define CSR_MCONTROL_HIT 0x100000 /* * This bit determines the contents of the XLEN-bit compare values. - * - * 0: There is at least one compare value and it contains the lowest + */ +#define CSR_MCONTROL_SELECT_OFFSET 0x13 +#define CSR_MCONTROL_SELECT_LENGTH 1 +#define CSR_MCONTROL_SELECT 0x80000 +/* + * address: There is at least one compare value and it contains the lowest * virtual address of the access. * It is recommended that there are additional compare values for * the other accessed virtual addresses. * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 * and the other addresses are 0x4001, 0x4002, and 0x4003.) - * - * 1: There is exactly one compare value and it contains the data + */ +#define CSR_MCONTROL_SELECT_ADDRESS 0 +/* + * data: There is exactly one compare value and it contains the data * value loaded or stored, or the instruction executed. * Any bits beyond the size of the data access will contain 0. */ -#define CSR_MCONTROL_SELECT_OFFSET 19 -#define CSR_MCONTROL_SELECT_LENGTH 1 -#define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET) +#define CSR_MCONTROL_SELECT_DATA 1 +#define CSR_MCONTROL_TIMING_OFFSET 0x12 +#define CSR_MCONTROL_TIMING_LENGTH 1 +#define CSR_MCONTROL_TIMING 0x40000 /* - * 0: The action for this trigger will be taken just before the + * before: The action for this trigger will be taken just before the * instruction that triggered it is committed, but after all preceding * instructions are committed. \Rxepc or \RcsrDpc (depending * on \FcsrMcontrolAction) must be set to the virtual address of the @@ -581,15 +665,19 @@ * though the load will not update its destination register. Debuggers * should consider this when setting such breakpoints on, for example, * memory-mapped I/O addresses. - * - * 1: The action for this trigger will be taken after the instruction + */ +#define CSR_MCONTROL_TIMING_BEFORE 0 +/* + * after: The action for this trigger will be taken after the instruction * that triggered it is committed. It should be taken before the next * instruction is committed, but it is better to implement triggers imprecisely * than to not implement them at all. \Rxepc or * \RcsrDpc (depending on \FcsrMcontrolAction) must be set to * the virtual address of the next instruction that must be executed to * preserve the program flow. - * + */ +#define CSR_MCONTROL_TIMING_AFTER 1 +/* * Most hardware will only implement one timing or the other, possibly * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute, * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit @@ -606,39 +694,60 @@ * implementation-dependent whether that prevents a trigger with * \FcsrMcontrolTiming of 1 matching as well. */ -#define CSR_MCONTROL_TIMING_OFFSET 18 -#define CSR_MCONTROL_TIMING_LENGTH 1 -#define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET) /* * This field contains the 2 low bits of the access size. The high bits come * from \FcsrMcontrolSizehi. The combined value is interpreted as follows: - * - * 0: The trigger will attempt to match against an access of any size. + */ +#define CSR_MCONTROL_SIZELO_OFFSET 0x10 +#define CSR_MCONTROL_SIZELO_LENGTH 2 +#define CSR_MCONTROL_SIZELO 0x30000 +/* + * any: The trigger will attempt to match against an access of any size. * The behavior is only well-defined if $|select|=0$, or if the access * size is XLEN. - * - * 1: The trigger will only match against 8-bit memory accesses. - * - * 2: The trigger will only match against 16-bit memory accesses or + */ +#define CSR_MCONTROL_SIZELO_ANY 0 +/* + * 8bit: The trigger will only match against 8-bit memory accesses. + */ +#define CSR_MCONTROL_SIZELO_8BIT 1 +/* + * 16bit: The trigger will only match against 16-bit memory accesses or * execution of 16-bit instructions. - * - * 3: The trigger will only match against 32-bit memory accesses or + */ +#define CSR_MCONTROL_SIZELO_16BIT 2 +/* + * 32bit: The trigger will only match against 32-bit memory accesses or * execution of 32-bit instructions. - * - * 4: The trigger will only match against execution of 48-bit instructions. - * - * 5: The trigger will only match against 64-bit memory accesses or + */ +#define CSR_MCONTROL_SIZELO_32BIT 3 +/* + * 48bit: The trigger will only match against execution of 48-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_48BIT 4 +/* + * 64bit: The trigger will only match against 64-bit memory accesses or * execution of 64-bit instructions. - * - * 6: The trigger will only match against execution of 80-bit instructions. - * - * 7: The trigger will only match against execution of 96-bit instructions. - * - * 8: The trigger will only match against execution of 112-bit instructions. - * - * 9: The trigger will only match against 128-bit memory accesses or + */ +#define CSR_MCONTROL_SIZELO_64BIT 5 +/* + * 80bit: The trigger will only match against execution of 80-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_80BIT 6 +/* + * 96bit: The trigger will only match against execution of 96-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_96BIT 7 +/* + * 112bit: The trigger will only match against execution of 112-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_112BIT 8 +/* + * 128bit: The trigger will only match against 128-bit memory accesses or * execution of 128-bit instructions. - * + */ +#define CSR_MCONTROL_SIZELO_128BIT 9 +/* * An implementation must support the value of 0, but all other values * are optional. When an implementation supports address triggers * (\FcsrMcontrolSelect=0), it is recommended that those triggers @@ -656,22 +765,54 @@ * hart supports, as well as for every instruction length up to XLEN * that the hart supports. */ -#define CSR_MCONTROL_SIZELO_OFFSET 16 -#define CSR_MCONTROL_SIZELO_LENGTH 2 -#define CSR_MCONTROL_SIZELO (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_MCONTROL_ACTION_OFFSET 12 +#define CSR_MCONTROL_ACTION_OFFSET 0xc #define CSR_MCONTROL_ACTION_LENGTH 4 -#define CSR_MCONTROL_ACTION (0xfULL << CSR_MCONTROL_ACTION_OFFSET) +#define CSR_MCONTROL_ACTION 0xf000 /* - * 0: When this trigger matches, the configured action is taken. - * - * 1: While this trigger does not match, it prevents the trigger with + * breakpoint: + */ +#define CSR_MCONTROL_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_MCONTROL_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_MCONTROL_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_MCONTROL_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_MCONTROL_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_MCONTROL_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_MCONTROL_ACTION_EXTERNAL1 9 +#define CSR_MCONTROL_CHAIN_OFFSET 0xb +#define CSR_MCONTROL_CHAIN_LENGTH 1 +#define CSR_MCONTROL_CHAIN 0x800 +/* + * disabled: When this trigger matches, the configured action is taken. + */ +#define CSR_MCONTROL_CHAIN_DISABLED 0 +/* + * enabled: While this trigger does not match, it prevents the trigger with * the next index from matching. - * + */ +#define CSR_MCONTROL_CHAIN_ENABLED 1 +/* * A trigger chain starts on the first trigger with $|chain|=1$ after * a trigger with $|chain|=0$, or simply on the first trigger if that * has $|chain|=1$. It ends on the first trigger after that which has @@ -695,44 +836,64 @@ * chain (eg. to meet timing requirements) may do so by zeroing * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long. */ -#define CSR_MCONTROL_CHAIN_OFFSET 11 -#define CSR_MCONTROL_CHAIN_LENGTH 1 -#define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET) +#define CSR_MCONTROL_MATCH_OFFSET 7 +#define CSR_MCONTROL_MATCH_LENGTH 4 +#define CSR_MCONTROL_MATCH 0x780 /* - * 0: Matches when any compare value equals \RcsrTdataTwo. - * - * 1: Matches when the top $M$ bits of any compare value match the top + * equal: Matches when any compare value equals \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_EQUAL 0 +/* + * napot: Matches when the top $M$ bits of any compare value match the top * $M$ bits of \RcsrTdataTwo. * $M$ is $|XLEN|-1$ minus the index of the least-significant * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values * to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$ * and $M\gt0$ , otherwise it's undefined on what conditions the * trigger will match. - * - * 2: Matches when any compare value is greater than (unsigned) or + */ +#define CSR_MCONTROL_MATCH_NAPOT 1 +/* + * ge: Matches when any compare value is greater than (unsigned) or * equal to \RcsrTdataTwo. - * - * 3: Matches when any compare value is less than (unsigned) + */ +#define CSR_MCONTROL_MATCH_GE 2 +/* + * lt: Matches when any compare value is less than (unsigned) * \RcsrTdataTwo. - * - * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value + */ +#define CSR_MCONTROL_MATCH_LT 3 +/* + * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. - * - * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare + */ +#define CSR_MCONTROL_MATCH_MASK_LOW 4 +/* + * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. - * - * 8: Matches when \FcsrMcontrolMatch$=0$ would not match. - * - * 9: Matches when \FcsrMcontrolMatch$=1$ would not match. - * - * 12: Matches when \FcsrMcontrolMatch$=4$ would not match. - * - * 13: Matches when \FcsrMcontrolMatch$=5$ would not match. - * + */ +#define CSR_MCONTROL_MATCH_MASK_HIGH 5 +/* + * not equal: Matches when \FcsrMcontrolMatch$=0$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_EQUAL 8 +/* + * not napot: Matches when \FcsrMcontrolMatch$=1$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_NAPOT 9 +/* + * not mask low: Matches when \FcsrMcontrolMatch$=4$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_MASK_LOW 12 +/* + * not mask high: Matches when \FcsrMcontrolMatch$=5$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_MASK_HIGH 13 +/* * Other values are reserved for future use. * * All comparisons only look at the lower XLEN (in the current mode) @@ -741,15 +902,12 @@ * reduced, and comparisons only look at the lower N bits of the * compare values and of \RcsrTdataTwo. */ -#define CSR_MCONTROL_MATCH_OFFSET 7 -#define CSR_MCONTROL_MATCH_LENGTH 4 -#define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET) /* * When set, enable this trigger in M-mode. */ #define CSR_MCONTROL_M_OFFSET 6 #define CSR_MCONTROL_M_LENGTH 1 -#define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET) +#define CSR_MCONTROL_M 0x40 /* * When set, enable this trigger in S/HS-mode. * This bit is hard-wired to 0 if the hart does not support @@ -757,7 +915,7 @@ */ #define CSR_MCONTROL_S_OFFSET 4 #define CSR_MCONTROL_S_LENGTH 1 -#define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET) +#define CSR_MCONTROL_S 0x10 /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support @@ -765,51 +923,51 @@ */ #define CSR_MCONTROL_U_OFFSET 3 #define CSR_MCONTROL_U_LENGTH 1 -#define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET) +#define CSR_MCONTROL_U 8 /* * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. */ #define CSR_MCONTROL_EXECUTE_OFFSET 2 #define CSR_MCONTROL_EXECUTE_LENGTH 1 -#define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET) +#define CSR_MCONTROL_EXECUTE 4 /* * When set, the trigger fires on the virtual address or data of any * store. */ #define CSR_MCONTROL_STORE_OFFSET 1 #define CSR_MCONTROL_STORE_LENGTH 1 -#define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET) +#define CSR_MCONTROL_STORE 2 /* * When set, the trigger fires on the virtual address or data of any * load. */ #define CSR_MCONTROL_LOAD_OFFSET 0 #define CSR_MCONTROL_LOAD_LENGTH 1 -#define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET) +#define CSR_MCONTROL_LOAD 1 #define CSR_MCONTROL6 0x7a1 -#define CSR_MCONTROL6_TYPE_OFFSET (XLEN-4) +#define CSR_MCONTROL6_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_MCONTROL6_TYPE_LENGTH 4 -#define CSR_MCONTROL6_TYPE (0xfULL << CSR_MCONTROL6_TYPE_OFFSET) -#define CSR_MCONTROL6_DMODE_OFFSET (XLEN-5) +#define CSR_MCONTROL6_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_MCONTROL6_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_MCONTROL6_DMODE_LENGTH 1 -#define CSR_MCONTROL6_DMODE (0x1ULL << CSR_MCONTROL6_DMODE_OFFSET) +#define CSR_MCONTROL6_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * When set, enable this trigger in VS-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_MCONTROL6_VS_OFFSET 24 +#define CSR_MCONTROL6_VS_OFFSET 0x18 #define CSR_MCONTROL6_VS_LENGTH 1 -#define CSR_MCONTROL6_VS (0x1ULL << CSR_MCONTROL6_VS_OFFSET) +#define CSR_MCONTROL6_VS 0x1000000 /* * When set, enable this trigger in VU-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_MCONTROL6_VU_OFFSET 23 +#define CSR_MCONTROL6_VU_OFFSET 0x17 #define CSR_MCONTROL6_VU_LENGTH 1 -#define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET) +#define CSR_MCONTROL6_VU 0x800000 /* * If this bit is implemented then it must become set when this * trigger fires and may become set when this trigger matches. @@ -818,28 +976,35 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_MCONTROL6_HIT_OFFSET 22 +#define CSR_MCONTROL6_HIT_OFFSET 0x16 #define CSR_MCONTROL6_HIT_LENGTH 1 -#define CSR_MCONTROL6_HIT (0x1ULL << CSR_MCONTROL6_HIT_OFFSET) +#define CSR_MCONTROL6_HIT 0x400000 /* * This bit determines the contents of the XLEN-bit compare values. - * - * 0: There is at least one compare value and it contains the lowest + */ +#define CSR_MCONTROL6_SELECT_OFFSET 0x15 +#define CSR_MCONTROL6_SELECT_LENGTH 1 +#define CSR_MCONTROL6_SELECT 0x200000 +/* + * address: There is at least one compare value and it contains the lowest * virtual address of the access. * In addition, it is recommended that there are additional compare * values for the other accessed virtual addresses match. * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 * and the other addresses are 0x4001, 0x4002, and 0x4003.) - * - * 1: There is exactly one compare value and it contains the data + */ +#define CSR_MCONTROL6_SELECT_ADDRESS 0 +/* + * data: There is exactly one compare value and it contains the data * value loaded or stored, or the instruction executed. * Any bits beyond the size of the data access will contain 0. */ -#define CSR_MCONTROL6_SELECT_OFFSET 21 -#define CSR_MCONTROL6_SELECT_LENGTH 1 -#define CSR_MCONTROL6_SELECT (0x1ULL << CSR_MCONTROL6_SELECT_OFFSET) +#define CSR_MCONTROL6_SELECT_DATA 1 +#define CSR_MCONTROL6_TIMING_OFFSET 0x14 +#define CSR_MCONTROL6_TIMING_LENGTH 1 +#define CSR_MCONTROL6_TIMING 0x100000 /* - * 0: The action for this trigger will be taken just before the + * before: The action for this trigger will be taken just before the * instruction that triggered it is committed, but after all preceding * instructions are committed. \Rxepc or \RcsrDpc (depending * on \FcsrMcontrolSixAction) must be set to the virtual address of the @@ -851,15 +1016,19 @@ * though the load will not update its destination register. Debuggers * should consider this when setting such breakpoints on, for example, * memory-mapped I/O addresses. - * - * 1: The action for this trigger will be taken after the instruction + */ +#define CSR_MCONTROL6_TIMING_BEFORE 0 +/* + * after: The action for this trigger will be taken after the instruction * that triggered it is committed. It should be taken before the next * instruction is committed, but it is better to implement triggers imprecisely * than to not implement them at all. \Rxepc or * \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to * the virtual address of the next instruction that must be executed to * preserve the program flow. - * + */ +#define CSR_MCONTROL6_TIMING_AFTER 1 +/* * Most hardware will only implement one timing or the other, possibly * dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute, * \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit @@ -876,36 +1045,56 @@ * implementation-dependent whether that prevents a trigger with * \FcsrMcontrolSixTiming of 1 matching as well. */ -#define CSR_MCONTROL6_TIMING_OFFSET 20 -#define CSR_MCONTROL6_TIMING_LENGTH 1 -#define CSR_MCONTROL6_TIMING (0x1ULL << CSR_MCONTROL6_TIMING_OFFSET) +#define CSR_MCONTROL6_SIZE_OFFSET 0x10 +#define CSR_MCONTROL6_SIZE_LENGTH 4 +#define CSR_MCONTROL6_SIZE 0xf0000 /* - * 0: The trigger will attempt to match against an access of any size. + * any: The trigger will attempt to match against an access of any size. * The behavior is only well-defined if $|select|=0$, or if the access * size is XLEN. - * - * 1: The trigger will only match against 8-bit memory accesses. - * - * 2: The trigger will only match against 16-bit memory accesses or + */ +#define CSR_MCONTROL6_SIZE_ANY 0 +/* + * 8bit: The trigger will only match against 8-bit memory accesses. + */ +#define CSR_MCONTROL6_SIZE_8BIT 1 +/* + * 16bit: The trigger will only match against 16-bit memory accesses or * execution of 16-bit instructions. - * - * 3: The trigger will only match against 32-bit memory accesses or + */ +#define CSR_MCONTROL6_SIZE_16BIT 2 +/* + * 32bit: The trigger will only match against 32-bit memory accesses or * execution of 32-bit instructions. - * - * 4: The trigger will only match against execution of 48-bit instructions. - * - * 5: The trigger will only match against 64-bit memory accesses or + */ +#define CSR_MCONTROL6_SIZE_32BIT 3 +/* + * 48bit: The trigger will only match against execution of 48-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_48BIT 4 +/* + * 64bit: The trigger will only match against 64-bit memory accesses or * execution of 64-bit instructions. - * - * 6: The trigger will only match against execution of 80-bit instructions. - * - * 7: The trigger will only match against execution of 96-bit instructions. - * - * 8: The trigger will only match against execution of 112-bit instructions. - * - * 9: The trigger will only match against 128-bit memory accesses or + */ +#define CSR_MCONTROL6_SIZE_64BIT 5 +/* + * 80bit: The trigger will only match against execution of 80-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_80BIT 6 +/* + * 96bit: The trigger will only match against execution of 96-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_96BIT 7 +/* + * 112bit: The trigger will only match against execution of 112-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_112BIT 8 +/* + * 128bit: The trigger will only match against 128-bit memory accesses or * execution of 128-bit instructions. - * + */ +#define CSR_MCONTROL6_SIZE_128BIT 9 +/* * An implementation must support the value of 0, but all other values * are optional. When an implementation supports address triggers * (\FcsrMcontrolSixSelect=0), it is recommended that those triggers @@ -923,22 +1112,54 @@ * hart supports, as well as for every instruction length up to XLEN * that the hart supports. */ -#define CSR_MCONTROL6_SIZE_OFFSET 16 -#define CSR_MCONTROL6_SIZE_LENGTH 4 -#define CSR_MCONTROL6_SIZE (0xfULL << CSR_MCONTROL6_SIZE_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_MCONTROL6_ACTION_OFFSET 12 +#define CSR_MCONTROL6_ACTION_OFFSET 0xc #define CSR_MCONTROL6_ACTION_LENGTH 4 -#define CSR_MCONTROL6_ACTION (0xfULL << CSR_MCONTROL6_ACTION_OFFSET) +#define CSR_MCONTROL6_ACTION 0xf000 /* - * 0: When this trigger matches, the configured action is taken. - * - * 1: While this trigger does not match, it prevents the trigger with + * breakpoint: + */ +#define CSR_MCONTROL6_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_MCONTROL6_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_MCONTROL6_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_MCONTROL6_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_MCONTROL6_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_MCONTROL6_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_MCONTROL6_ACTION_EXTERNAL1 9 +#define CSR_MCONTROL6_CHAIN_OFFSET 0xb +#define CSR_MCONTROL6_CHAIN_LENGTH 1 +#define CSR_MCONTROL6_CHAIN 0x800 +/* + * disabled: When this trigger matches, the configured action is taken. + */ +#define CSR_MCONTROL6_CHAIN_DISABLED 0 +/* + * enabled: While this trigger does not match, it prevents the trigger with * the next index from matching. - * + */ +#define CSR_MCONTROL6_CHAIN_ENABLED 1 +/* * A trigger chain starts on the first trigger with $|chain|=1$ after * a trigger with $|chain|=0$, or simply on the first trigger if that * has $|chain|=1$. It ends on the first trigger after that which has @@ -962,45 +1183,66 @@ * chain (eg. to meet timing requirements) may do so by zeroing * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long. */ -#define CSR_MCONTROL6_CHAIN_OFFSET 11 -#define CSR_MCONTROL6_CHAIN_LENGTH 1 -#define CSR_MCONTROL6_CHAIN (0x1ULL << CSR_MCONTROL6_CHAIN_OFFSET) +#define CSR_MCONTROL6_MATCH_OFFSET 7 +#define CSR_MCONTROL6_MATCH_LENGTH 4 +#define CSR_MCONTROL6_MATCH 0x780 /* - * 0: Matches when any compare value equals \RcsrTdataTwo. - * - * 1: Matches when the top $M$ bits of any compare value match the top + * equal: Matches when any compare value equals \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_EQUAL 0 +/* + * napot: Matches when the top $M$ bits of any compare value match the top * $M$ bits of \RcsrTdataTwo. * $M$ is $|XLEN|-1$ minus the index of the least-significant bit * containing 0 in \RcsrTdataTwo. - * \RcsrTdataTwo is WARL and bit $|maskmax6|-1$ will be set to 0 if no - * less significant bits are written with 0. + * \RcsrTdataTwo is WARL and if bits $|maskmax6|-1$:0 are written with all + * ones then bit $|maskmax6|-1$ will be set to 0 while the values of bits $|maskmax6|-2$:0 + * are \unspecified. * Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$. * See above for how to determine maskmax6. - * - * 2: Matches when any compare value is greater than (unsigned) or + */ +#define CSR_MCONTROL6_MATCH_NAPOT 1 +/* + * ge: Matches when any compare value is greater than (unsigned) or * equal to \RcsrTdataTwo. - * - * 3: Matches when any compare value is less than (unsigned) + */ +#define CSR_MCONTROL6_MATCH_GE 2 +/* + * lt: Matches when any compare value is less than (unsigned) * \RcsrTdataTwo. - * - * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value + */ +#define CSR_MCONTROL6_MATCH_LT 3 +/* + * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. - * - * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare + */ +#define CSR_MCONTROL6_MATCH_MASK_LOW 4 +/* + * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. - * - * 8: Matches when \FcsrMcontrolSixMatch$=0$ would not match. - * - * 9: Matches when \FcsrMcontrolSixMatch$=1$ would not match. - * - * 12: Matches when \FcsrMcontrolSixMatch$=4$ would not match. - * - * 13: Matches when \FcsrMcontrolSixMatch$=5$ would not match. - * + */ +#define CSR_MCONTROL6_MATCH_MASK_HIGH 5 +/* + * not equal: Matches when \FcsrMcontrolSixMatch$=0$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_EQUAL 8 +/* + * not napot: Matches when \FcsrMcontrolSixMatch$=1$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_NAPOT 9 +/* + * not mask low: Matches when \FcsrMcontrolSixMatch$=4$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_MASK_LOW 12 +/* + * not mask high: Matches when \FcsrMcontrolSixMatch$=5$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_MASK_HIGH 13 +/* * Other values are reserved for future use. * * All comparisons only look at the lower XLEN (in the current mode) @@ -1009,15 +1251,12 @@ * reduced, and comparisons only look at the lower N bits of the * compare values and of \RcsrTdataTwo. */ -#define CSR_MCONTROL6_MATCH_OFFSET 7 -#define CSR_MCONTROL6_MATCH_LENGTH 4 -#define CSR_MCONTROL6_MATCH (0xfULL << CSR_MCONTROL6_MATCH_OFFSET) /* * When set, enable this trigger in M-mode. */ #define CSR_MCONTROL6_M_OFFSET 6 #define CSR_MCONTROL6_M_LENGTH 1 -#define CSR_MCONTROL6_M (0x1ULL << CSR_MCONTROL6_M_OFFSET) +#define CSR_MCONTROL6_M 0x40 /* * When set, enable this trigger in S/HS-mode. * This bit is hard-wired to 0 if the hart does not support @@ -1025,7 +1264,7 @@ */ #define CSR_MCONTROL6_S_OFFSET 4 #define CSR_MCONTROL6_S_LENGTH 1 -#define CSR_MCONTROL6_S (0x1ULL << CSR_MCONTROL6_S_OFFSET) +#define CSR_MCONTROL6_S 0x10 /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support @@ -1033,84 +1272,82 @@ */ #define CSR_MCONTROL6_U_OFFSET 3 #define CSR_MCONTROL6_U_LENGTH 1 -#define CSR_MCONTROL6_U (0x1ULL << CSR_MCONTROL6_U_OFFSET) +#define CSR_MCONTROL6_U 8 /* * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. */ #define CSR_MCONTROL6_EXECUTE_OFFSET 2 #define CSR_MCONTROL6_EXECUTE_LENGTH 1 -#define CSR_MCONTROL6_EXECUTE (0x1ULL << CSR_MCONTROL6_EXECUTE_OFFSET) +#define CSR_MCONTROL6_EXECUTE 4 /* * When set, the trigger fires on the virtual address or data of any * store. */ #define CSR_MCONTROL6_STORE_OFFSET 1 #define CSR_MCONTROL6_STORE_LENGTH 1 -#define CSR_MCONTROL6_STORE (0x1ULL << CSR_MCONTROL6_STORE_OFFSET) +#define CSR_MCONTROL6_STORE 2 /* * When set, the trigger fires on the virtual address or data of any * load. */ #define CSR_MCONTROL6_LOAD_OFFSET 0 #define CSR_MCONTROL6_LOAD_LENGTH 1 -#define CSR_MCONTROL6_LOAD (0x1ULL << CSR_MCONTROL6_LOAD_OFFSET) +#define CSR_MCONTROL6_LOAD 1 #define CSR_ICOUNT 0x7a1 -#define CSR_ICOUNT_TYPE_OFFSET (XLEN-4) +#define CSR_ICOUNT_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_ICOUNT_TYPE_LENGTH 4 -#define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET) -#define CSR_ICOUNT_DMODE_OFFSET (XLEN-5) +#define CSR_ICOUNT_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ICOUNT_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_ICOUNT_DMODE_LENGTH 1 -#define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) +#define CSR_ICOUNT_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * When set, enable this trigger in VS-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ICOUNT_VS_OFFSET 26 +#define CSR_ICOUNT_VS_OFFSET 0x1a #define CSR_ICOUNT_VS_LENGTH 1 -#define CSR_ICOUNT_VS (0x1ULL << CSR_ICOUNT_VS_OFFSET) +#define CSR_ICOUNT_VS 0x4000000 /* * When set, enable this trigger in VU-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ICOUNT_VU_OFFSET 25 +#define CSR_ICOUNT_VU_OFFSET 0x19 #define CSR_ICOUNT_VU_LENGTH 1 -#define CSR_ICOUNT_VU (0x1ULL << CSR_ICOUNT_VU_OFFSET) +#define CSR_ICOUNT_VU 0x2000000 /* * If this bit is implemented, the hardware sets it when this - * trigger matches. The trigger's user can set or clear it at any + * trigger fires. The trigger's user can set or clear it at any * time. It is used to determine which - * trigger(s) matched. If the bit is not implemented, it is always 0 + * trigger(s) fires. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ICOUNT_HIT_OFFSET 24 +#define CSR_ICOUNT_HIT_OFFSET 0x18 #define CSR_ICOUNT_HIT_LENGTH 1 -#define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET) +#define CSR_ICOUNT_HIT 0x1000000 /* - * When count is decremented to 0, the trigger fires. Instead of - * changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to - * clear \FcsrIcountM, \FcsrIcountS, \FcsrIcountU, \FcsrIcountVs, and - * \FcsrIcountVu. This allows \FcsrIcountCount to be hard-wired - * to 1 if this register just exists for single step. + * The trigger will generally fire after \FcsrIcountCount instructions + * in enabled modes have been executed. See above for the precise behavior. */ -#define CSR_ICOUNT_COUNT_OFFSET 10 -#define CSR_ICOUNT_COUNT_LENGTH 14 -#define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET) +#define CSR_ICOUNT_COUNT_OFFSET 0xa +#define CSR_ICOUNT_COUNT_LENGTH 0xe +#define CSR_ICOUNT_COUNT 0xfffc00 /* * When set, enable this trigger in M-mode. */ #define CSR_ICOUNT_M_OFFSET 9 #define CSR_ICOUNT_M_LENGTH 1 -#define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET) +#define CSR_ICOUNT_M 0x200 /* * This bit becomes set when \FcsrIcountCount is decremented from 1 - * to 0. It is cleared when the trigger fires. + * to 0. It is cleared when the trigger fires, which will happen just + * before executing the next instruction in one of the enabled modes. */ #define CSR_ICOUNT_PENDING_OFFSET 8 #define CSR_ICOUNT_PENDING_LENGTH 1 -#define CSR_ICOUNT_PENDING (0x1ULL << CSR_ICOUNT_PENDING_OFFSET) +#define CSR_ICOUNT_PENDING 0x100 /* * When set, enable this trigger in S/HS-mode. * This bit is hard-wired to 0 if the hart does not support @@ -1118,7 +1355,7 @@ */ #define CSR_ICOUNT_S_OFFSET 7 #define CSR_ICOUNT_S_LENGTH 1 -#define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET) +#define CSR_ICOUNT_S 0x80 /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support @@ -1126,21 +1363,49 @@ */ #define CSR_ICOUNT_U_OFFSET 6 #define CSR_ICOUNT_U_LENGTH 1 -#define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET) +#define CSR_ICOUNT_U 0x40 /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ICOUNT_ACTION_OFFSET 0 #define CSR_ICOUNT_ACTION_LENGTH 6 -#define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET) +#define CSR_ICOUNT_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ICOUNT_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ICOUNT_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ICOUNT_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ICOUNT_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ICOUNT_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ICOUNT_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ICOUNT_ACTION_EXTERNAL1 9 #define CSR_ITRIGGER 0x7a1 -#define CSR_ITRIGGER_TYPE_OFFSET (XLEN-4) +#define CSR_ITRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_ITRIGGER_TYPE_LENGTH 4 -#define CSR_ITRIGGER_TYPE (0xfULL << CSR_ITRIGGER_TYPE_OFFSET) -#define CSR_ITRIGGER_DMODE_OFFSET (XLEN-5) +#define CSR_ITRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ITRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_ITRIGGER_DMODE_LENGTH 1 -#define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET) +#define CSR_ITRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1148,34 +1413,41 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ITRIGGER_HIT_OFFSET (XLEN-6) +#define CSR_ITRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) #define CSR_ITRIGGER_HIT_LENGTH 1 -#define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET) +#define CSR_ITRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) /* * When set, enable this trigger for interrupts that are taken from VS * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ITRIGGER_VS_OFFSET 12 +#define CSR_ITRIGGER_VS_OFFSET 0xc #define CSR_ITRIGGER_VS_LENGTH 1 -#define CSR_ITRIGGER_VS (0x1ULL << CSR_ITRIGGER_VS_OFFSET) +#define CSR_ITRIGGER_VS 0x1000 /* * When set, enable this trigger for interrupts that are taken from VU * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ITRIGGER_VU_OFFSET 11 +#define CSR_ITRIGGER_VU_OFFSET 0xb #define CSR_ITRIGGER_VU_LENGTH 1 -#define CSR_ITRIGGER_VU (0x1ULL << CSR_ITRIGGER_VU_OFFSET) +#define CSR_ITRIGGER_VU 0x800 +/* + * When set, non-maskable interrupts cause this + * trigger to fire if the trigger is enabled for the current mode. + */ +#define CSR_ITRIGGER_NMI_OFFSET 0xa +#define CSR_ITRIGGER_NMI_LENGTH 1 +#define CSR_ITRIGGER_NMI 0x400 /* * When set, enable this trigger for interrupts that are taken from M * mode. */ #define CSR_ITRIGGER_M_OFFSET 9 #define CSR_ITRIGGER_M_LENGTH 1 -#define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET) +#define CSR_ITRIGGER_M 0x200 /* * When set, enable this trigger for interrupts that are taken from S/HS * mode. @@ -1184,7 +1456,7 @@ */ #define CSR_ITRIGGER_S_OFFSET 7 #define CSR_ITRIGGER_S_LENGTH 1 -#define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET) +#define CSR_ITRIGGER_S 0x80 /* * When set, enable this trigger for interrupts that are taken from U * mode. @@ -1193,21 +1465,49 @@ */ #define CSR_ITRIGGER_U_OFFSET 6 #define CSR_ITRIGGER_U_LENGTH 1 -#define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET) +#define CSR_ITRIGGER_U 0x40 /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ITRIGGER_ACTION_OFFSET 0 #define CSR_ITRIGGER_ACTION_LENGTH 6 -#define CSR_ITRIGGER_ACTION (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET) +#define CSR_ITRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ITRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ITRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ITRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ITRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ITRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ITRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ITRIGGER_ACTION_EXTERNAL1 9 #define CSR_ETRIGGER 0x7a1 -#define CSR_ETRIGGER_TYPE_OFFSET (XLEN-4) +#define CSR_ETRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_ETRIGGER_TYPE_LENGTH 4 -#define CSR_ETRIGGER_TYPE (0xfULL << CSR_ETRIGGER_TYPE_OFFSET) -#define CSR_ETRIGGER_DMODE_OFFSET (XLEN-5) +#define CSR_ETRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ETRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_ETRIGGER_DMODE_LENGTH 1 -#define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET) +#define CSR_ETRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1215,42 +1515,34 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ETRIGGER_HIT_OFFSET (XLEN-6) +#define CSR_ETRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) #define CSR_ETRIGGER_HIT_LENGTH 1 -#define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET) +#define CSR_ETRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) /* * When set, enable this trigger for exceptions that are taken from VS * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ETRIGGER_VS_OFFSET 12 +#define CSR_ETRIGGER_VS_OFFSET 0xc #define CSR_ETRIGGER_VS_LENGTH 1 -#define CSR_ETRIGGER_VS (0x1ULL << CSR_ETRIGGER_VS_OFFSET) +#define CSR_ETRIGGER_VS 0x1000 /* * When set, enable this trigger for exceptions that are taken from VU * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ETRIGGER_VU_OFFSET 11 +#define CSR_ETRIGGER_VU_OFFSET 0xb #define CSR_ETRIGGER_VU_LENGTH 1 -#define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET) -/* - * When set, non-maskable interrupts cause this - * trigger to fire, regardless of the values of \FcsrEtriggerM, - * \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu. - */ -#define CSR_ETRIGGER_NMI_OFFSET 10 -#define CSR_ETRIGGER_NMI_LENGTH 1 -#define CSR_ETRIGGER_NMI (0x1ULL << CSR_ETRIGGER_NMI_OFFSET) +#define CSR_ETRIGGER_VU 0x800 /* * When set, enable this trigger for exceptions that are taken from M * mode. */ #define CSR_ETRIGGER_M_OFFSET 9 #define CSR_ETRIGGER_M_LENGTH 1 -#define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET) +#define CSR_ETRIGGER_M 0x200 /* * When set, enable this trigger for exceptions that are taken from S/HS * mode. @@ -1259,7 +1551,7 @@ */ #define CSR_ETRIGGER_S_OFFSET 7 #define CSR_ETRIGGER_S_LENGTH 1 -#define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET) +#define CSR_ETRIGGER_S 0x80 /* * When set, enable this trigger for exceptions that are taken from U * mode. @@ -1268,21 +1560,49 @@ */ #define CSR_ETRIGGER_U_OFFSET 6 #define CSR_ETRIGGER_U_LENGTH 1 -#define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET) +#define CSR_ETRIGGER_U 0x40 /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ETRIGGER_ACTION_OFFSET 0 #define CSR_ETRIGGER_ACTION_LENGTH 6 -#define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET) +#define CSR_ETRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ETRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ETRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ETRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ETRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ETRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ETRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ETRIGGER_ACTION_EXTERNAL1 9 #define CSR_TMEXTTRIGGER 0x7a1 -#define CSR_TMEXTTRIGGER_TYPE_OFFSET (XLEN-4) +#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) #define CSR_TMEXTTRIGGER_TYPE_LENGTH 4 -#define CSR_TMEXTTRIGGER_TYPE (0xfULL << CSR_TMEXTTRIGGER_TYPE_OFFSET) -#define CSR_TMEXTTRIGGER_DMODE_OFFSET (XLEN-5) +#define CSR_TMEXTTRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) #define CSR_TMEXTTRIGGER_DMODE_LENGTH 1 -#define CSR_TMEXTTRIGGER_DMODE (0x1ULL << CSR_TMEXTTRIGGER_DMODE_OFFSET) +#define CSR_TMEXTTRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1290,80 +1610,119 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_TMEXTTRIGGER_HIT_OFFSET (XLEN-6) +#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) #define CSR_TMEXTTRIGGER_HIT_LENGTH 1 -#define CSR_TMEXTTRIGGER_HIT (0x1ULL << CSR_TMEXTTRIGGER_HIT_OFFSET) +#define CSR_TMEXTTRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) /* * This optional bit, when set, causes this trigger to fire whenever an attached * interrupt controller signals a trigger. */ -#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 22 +#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 0x16 #define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1 -#define CSR_TMEXTTRIGGER_INTCTL (0x1ULL << CSR_TMEXTTRIGGER_INTCTL_OFFSET) +#define CSR_TMEXTTRIGGER_INTCTL 0x400000 /* * Selects any combination of up to 16 external debug trigger inputs * that cause this trigger to fire. */ #define CSR_TMEXTTRIGGER_SELECT_OFFSET 6 -#define CSR_TMEXTTRIGGER_SELECT_LENGTH 16 -#define CSR_TMEXTTRIGGER_SELECT (0xffffULL << CSR_TMEXTTRIGGER_SELECT_OFFSET) +#define CSR_TMEXTTRIGGER_SELECT_LENGTH 0x10 +#define CSR_TMEXTTRIGGER_SELECT 0x3fffc0 /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_TMEXTTRIGGER_ACTION_OFFSET 0 #define CSR_TMEXTTRIGGER_ACTION_LENGTH 6 -#define CSR_TMEXTTRIGGER_ACTION (0x3fULL << CSR_TMEXTTRIGGER_ACTION_OFFSET) +#define CSR_TMEXTTRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_TMEXTTRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_TMEXTTRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_TMEXTTRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_TMEXTTRIGGER_ACTION_EXTERNAL1 9 #define CSR_TEXTRA32 0x7a3 /* * Data used together with \FcsrTextraThirtytwoMhselect. */ -#define CSR_TEXTRA32_MHVALUE_OFFSET 26 +#define CSR_TEXTRA32_MHVALUE_OFFSET 0x1a #define CSR_TEXTRA32_MHVALUE_LENGTH 6 -#define CSR_TEXTRA32_MHVALUE (0x3fU << CSR_TEXTRA32_MHVALUE_OFFSET) +#define CSR_TEXTRA32_MHVALUE 0xfc000000U +#define CSR_TEXTRA32_MHSELECT_OFFSET 0x17 +#define CSR_TEXTRA32_MHSELECT_LENGTH 3 +#define CSR_TEXTRA32_MHSELECT 0x3800000 /* - * 0: Ignore \FcsrTextraThirtytwoMhvalue. - * - * 4: This trigger will only match if the low bits of + * ignore: Ignore \FcsrTextraThirtytwoMhvalue. + */ +#define CSR_TEXTRA32_MHSELECT_IGNORE 0 +/* + * mcontext: This trigger will only match if the low bits of * \RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue. - * - * 1, 5: This trigger will only match if the low bits of + */ +#define CSR_TEXTRA32_MHSELECT_MCONTEXT 4 +/* + * 1, 5 (mcontext\_select): This trigger will only match if the low bits of * \RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}. * - * 2, 6: This trigger will only match if VMID in hgatp equals the lower VMIDMAX + * 2, 6 (vmid\_select): This trigger will only match if VMID in hgatp equals the lower VMIDMAX * (defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}. * - * 3, 7: Reserved. + * 3, 7 (reserved): Reserved. * * If the H extension is not supported, the only legal values are 0 and 4. */ -#define CSR_TEXTRA32_MHSELECT_OFFSET 23 -#define CSR_TEXTRA32_MHSELECT_LENGTH 3 -#define CSR_TEXTRA32_MHSELECT (0x7U << CSR_TEXTRA32_MHSELECT_OFFSET) /* * When the least significant bit of this field is 1, it causes bits 7:0 * in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1. * When the next most significant bit of this field is 1, it causes bits 15:8 * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1. */ -#define CSR_TEXTRA32_SBYTEMASK_OFFSET 18 +#define CSR_TEXTRA32_SBYTEMASK_OFFSET 0x12 #define CSR_TEXTRA32_SBYTEMASK_LENGTH 2 -#define CSR_TEXTRA32_SBYTEMASK (0x3U << CSR_TEXTRA32_SBYTEMASK_OFFSET) +#define CSR_TEXTRA32_SBYTEMASK 0xc0000 /* * Data used together with \FcsrTextraThirtytwoSselect. * * This field should be tied to 0 when S-mode is not supported. */ #define CSR_TEXTRA32_SVALUE_OFFSET 2 -#define CSR_TEXTRA32_SVALUE_LENGTH 16 -#define CSR_TEXTRA32_SVALUE (0xffffU << CSR_TEXTRA32_SVALUE_OFFSET) +#define CSR_TEXTRA32_SVALUE_LENGTH 0x10 +#define CSR_TEXTRA32_SVALUE 0x3fffc +#define CSR_TEXTRA32_SSELECT_OFFSET 0 +#define CSR_TEXTRA32_SSELECT_LENGTH 2 +#define CSR_TEXTRA32_SSELECT 3 /* - * 0: Ignore \FcsrTextraThirtytwoSvalue. - * - * 1: This trigger will only match if the low bits of + * ignore: Ignore \FcsrTextraThirtytwoSvalue. + */ +#define CSR_TEXTRA32_SSELECT_IGNORE 0 +/* + * scontext: This trigger will only match if the low bits of * \RcsrScontext equal \FcsrTextraThirtytwoSvalue. - * - * 2: This trigger will only match if: + */ +#define CSR_TEXTRA32_SSELECT_SCONTEXT 1 +/* + * asid: This trigger will only match if: * \begin{itemize}[noitemsep,nolistsep] * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp * equals the lower ASIDMAX (defined in the Privileged Spec) bits @@ -1372,19 +1731,18 @@ * ASIDMAX (defined in the Privileged Spec) bits of * \FcsrTextraThirtytwoSvalue. * \end{itemize} - * + */ +#define CSR_TEXTRA32_SSELECT_ASID 2 +/* * This field should be tied to 0 when S-mode is not supported. */ -#define CSR_TEXTRA32_SSELECT_OFFSET 0 -#define CSR_TEXTRA32_SSELECT_LENGTH 2 -#define CSR_TEXTRA32_SSELECT (0x3U << CSR_TEXTRA32_SSELECT_OFFSET) #define CSR_TEXTRA64 0x7a3 -#define CSR_TEXTRA64_MHVALUE_OFFSET 51 -#define CSR_TEXTRA64_MHVALUE_LENGTH 13 -#define CSR_TEXTRA64_MHVALUE (0x1fffULL << CSR_TEXTRA64_MHVALUE_OFFSET) -#define CSR_TEXTRA64_MHSELECT_OFFSET 48 +#define CSR_TEXTRA64_MHVALUE_OFFSET 0x33 +#define CSR_TEXTRA64_MHVALUE_LENGTH 0xd +#define CSR_TEXTRA64_MHVALUE 0xfff8000000000000ULL +#define CSR_TEXTRA64_MHSELECT_OFFSET 0x30 #define CSR_TEXTRA64_MHSELECT_LENGTH 3 -#define CSR_TEXTRA64_MHSELECT (0x7ULL << CSR_TEXTRA64_MHSELECT_OFFSET) +#define CSR_TEXTRA64_MHSELECT 0x7000000000000ULL /* * When the least significant bit of this field is 1, it causes bits 7:0 * in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1. @@ -1393,34 +1751,40 @@ * fourth bit controls the comparison of bits 31:24, and * fifth bit controls the comparison of bits 33:32. */ -#define CSR_TEXTRA64_SBYTEMASK_OFFSET 36 +#define CSR_TEXTRA64_SBYTEMASK_OFFSET 0x24 #define CSR_TEXTRA64_SBYTEMASK_LENGTH 5 -#define CSR_TEXTRA64_SBYTEMASK (0x1fULL << CSR_TEXTRA64_SBYTEMASK_OFFSET) +#define CSR_TEXTRA64_SBYTEMASK 0x1f000000000ULL #define CSR_TEXTRA64_SVALUE_OFFSET 2 -#define CSR_TEXTRA64_SVALUE_LENGTH 34 -#define CSR_TEXTRA64_SVALUE (0x3ffffffffULL << CSR_TEXTRA64_SVALUE_OFFSET) +#define CSR_TEXTRA64_SVALUE_LENGTH 0x22 +#define CSR_TEXTRA64_SVALUE 0xffffffffcULL #define CSR_TEXTRA64_SSELECT_OFFSET 0 #define CSR_TEXTRA64_SSELECT_LENGTH 2 -#define CSR_TEXTRA64_SSELECT (0x3ULL << CSR_TEXTRA64_SSELECT_OFFSET) +#define CSR_TEXTRA64_SSELECT 3 #define DM_DMSTATUS 0x11 +#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 0x18 +#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1 +#define DM_DMSTATUS_NDMRESETPENDING 0x1000000 +/* + * false: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently + * in progress. + */ +#define DM_DMSTATUS_NDMRESETPENDING_FALSE 0 +/* + * true: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress. + */ +#define DM_DMSTATUS_NDMRESETPENDING_TRUE 1 +#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 0x17 +#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_STICKYUNAVAIL 0x800000 /* - * 0: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently - * in progress. - * - * 1: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress. + * current: The per-hart {\tt unavail} bits reflect the current state of the hart. */ -#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 24 -#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1 -#define DM_DMSTATUS_NDMRESETPENDING (0x1U << DM_DMSTATUS_NDMRESETPENDING_OFFSET) +#define DM_DMSTATUS_STICKYUNAVAIL_CURRENT 0 /* - * 0: The per-hart {\tt unavail} bits reflect the current state of the hart. - * - * 1: The per-hart {\tt unavail} bits are sticky. Once they are set, they will + * sticky: The per-hart {\tt unavail} bits are sticky. Once they are set, they will * not clear until the debugger acknowledges them using \FdmDmcontrolAckunavail. */ -#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 23 -#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_STICKYUNAVAIL (0x1U << DM_DMSTATUS_STICKYUNAVAIL_OFFSET) +#define DM_DMSTATUS_STICKYUNAVAIL_STICKY 1 /* * If 1, then there is an implicit {\tt ebreak} instruction at the * non-existent word immediately after the Program Buffer. This saves @@ -1429,115 +1793,123 @@ * * This must be 1 when \FdmAbstractcsProgbufsize is 1. */ -#define DM_DMSTATUS_IMPEBREAK_OFFSET 22 +#define DM_DMSTATUS_IMPEBREAK_OFFSET 0x16 #define DM_DMSTATUS_IMPEBREAK_LENGTH 1 -#define DM_DMSTATUS_IMPEBREAK (0x1U << DM_DMSTATUS_IMPEBREAK_OFFSET) +#define DM_DMSTATUS_IMPEBREAK 0x400000 /* * This field is 1 when all currently selected harts have been reset * and reset has not been acknowledged for any of them. */ -#define DM_DMSTATUS_ALLHAVERESET_OFFSET 19 +#define DM_DMSTATUS_ALLHAVERESET_OFFSET 0x13 #define DM_DMSTATUS_ALLHAVERESET_LENGTH 1 -#define DM_DMSTATUS_ALLHAVERESET (0x1U << DM_DMSTATUS_ALLHAVERESET_OFFSET) +#define DM_DMSTATUS_ALLHAVERESET 0x80000 /* * This field is 1 when at least one currently selected hart has been * reset and reset has not been acknowledged for that hart. */ -#define DM_DMSTATUS_ANYHAVERESET_OFFSET 18 +#define DM_DMSTATUS_ANYHAVERESET_OFFSET 0x12 #define DM_DMSTATUS_ANYHAVERESET_LENGTH 1 -#define DM_DMSTATUS_ANYHAVERESET (0x1U << DM_DMSTATUS_ANYHAVERESET_OFFSET) +#define DM_DMSTATUS_ANYHAVERESET 0x40000 /* - * This field is 1 when all currently selected harts have acknowledged - * their last resume request. + * This field is 1 when all currently selected harts have their + * resume ack bit\index{resume ack bit} set. */ -#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 17 +#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 0x11 #define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1 -#define DM_DMSTATUS_ALLRESUMEACK (0x1U << DM_DMSTATUS_ALLRESUMEACK_OFFSET) +#define DM_DMSTATUS_ALLRESUMEACK 0x20000 /* - * This field is 1 when any currently selected hart has acknowledged - * its last resume request. + * This field is 1 when any currently selected hart has its + * resume ack bit\index{resume ack bit} set. */ -#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 16 +#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 0x10 #define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1 -#define DM_DMSTATUS_ANYRESUMEACK (0x1U << DM_DMSTATUS_ANYRESUMEACK_OFFSET) +#define DM_DMSTATUS_ANYRESUMEACK 0x10000 /* * This field is 1 when all currently selected harts do not exist in * this hardware platform. */ -#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 15 +#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 0xf #define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1 -#define DM_DMSTATUS_ALLNONEXISTENT (0x1U << DM_DMSTATUS_ALLNONEXISTENT_OFFSET) +#define DM_DMSTATUS_ALLNONEXISTENT 0x8000 /* * This field is 1 when any currently selected hart does not exist in * this hardware platform. */ -#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 14 +#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 0xe #define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1 -#define DM_DMSTATUS_ANYNONEXISTENT (0x1U << DM_DMSTATUS_ANYNONEXISTENT_OFFSET) +#define DM_DMSTATUS_ANYNONEXISTENT 0x4000 /* * This field is 1 when all currently selected harts are * unavailable, or (if \FdmDmstatusStickyunavail is 1) were * unavailable without that being acknowledged. */ -#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 13 +#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 0xd #define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_ALLUNAVAIL (0x1U << DM_DMSTATUS_ALLUNAVAIL_OFFSET) +#define DM_DMSTATUS_ALLUNAVAIL 0x2000 /* * This field is 1 when any currently selected hart is unavailable, * or (if \FdmDmstatusStickyunavail is 1) was unavailable without * that being acknowledged. */ -#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 12 +#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 0xc #define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_ANYUNAVAIL (0x1U << DM_DMSTATUS_ANYUNAVAIL_OFFSET) +#define DM_DMSTATUS_ANYUNAVAIL 0x1000 /* * This field is 1 when all currently selected harts are running. */ -#define DM_DMSTATUS_ALLRUNNING_OFFSET 11 +#define DM_DMSTATUS_ALLRUNNING_OFFSET 0xb #define DM_DMSTATUS_ALLRUNNING_LENGTH 1 -#define DM_DMSTATUS_ALLRUNNING (0x1U << DM_DMSTATUS_ALLRUNNING_OFFSET) +#define DM_DMSTATUS_ALLRUNNING 0x800 /* * This field is 1 when any currently selected hart is running. */ -#define DM_DMSTATUS_ANYRUNNING_OFFSET 10 +#define DM_DMSTATUS_ANYRUNNING_OFFSET 0xa #define DM_DMSTATUS_ANYRUNNING_LENGTH 1 -#define DM_DMSTATUS_ANYRUNNING (0x1U << DM_DMSTATUS_ANYRUNNING_OFFSET) +#define DM_DMSTATUS_ANYRUNNING 0x400 /* * This field is 1 when all currently selected harts are halted. */ #define DM_DMSTATUS_ALLHALTED_OFFSET 9 #define DM_DMSTATUS_ALLHALTED_LENGTH 1 -#define DM_DMSTATUS_ALLHALTED (0x1U << DM_DMSTATUS_ALLHALTED_OFFSET) +#define DM_DMSTATUS_ALLHALTED 0x200 /* * This field is 1 when any currently selected hart is halted. */ #define DM_DMSTATUS_ANYHALTED_OFFSET 8 #define DM_DMSTATUS_ANYHALTED_LENGTH 1 -#define DM_DMSTATUS_ANYHALTED (0x1U << DM_DMSTATUS_ANYHALTED_OFFSET) +#define DM_DMSTATUS_ANYHALTED 0x100 +#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7 +#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1 +#define DM_DMSTATUS_AUTHENTICATED 0x80 +/* + * false: Authentication is required before using the DM. + */ +#define DM_DMSTATUS_AUTHENTICATED_FALSE 0 +/* + * true: The authentication check has passed. + */ +#define DM_DMSTATUS_AUTHENTICATED_TRUE 1 /* - * 0: Authentication is required before using the DM. - * - * 1: The authentication check has passed. - * * On components that don't implement authentication, this bit must be * preset as 1. */ -#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7 -#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1 -#define DM_DMSTATUS_AUTHENTICATED (0x1U << DM_DMSTATUS_AUTHENTICATED_OFFSET) +#define DM_DMSTATUS_AUTHBUSY_OFFSET 6 +#define DM_DMSTATUS_AUTHBUSY_LENGTH 1 +#define DM_DMSTATUS_AUTHBUSY 0x40 /* - * 0: The authentication module is ready to process the next + * ready: The authentication module is ready to process the next * read/write to \RdmAuthdata. - * - * 1: The authentication module is busy. Accessing \RdmAuthdata results + */ +#define DM_DMSTATUS_AUTHBUSY_READY 0 +/* + * busy: The authentication module is busy. Accessing \RdmAuthdata results * in unspecified behavior. - * + */ +#define DM_DMSTATUS_AUTHBUSY_BUSY 1 +/* * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to * \RdmAuthdata. */ -#define DM_DMSTATUS_AUTHBUSY_OFFSET 6 -#define DM_DMSTATUS_AUTHBUSY_LENGTH 1 -#define DM_DMSTATUS_AUTHBUSY (0x1U << DM_DMSTATUS_AUTHBUSY_OFFSET) /* * 1 if this Debug Module supports halt-on-reset functionality * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits. @@ -1545,35 +1917,47 @@ */ #define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5 #define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1 -#define DM_DMSTATUS_HASRESETHALTREQ (0x1U << DM_DMSTATUS_HASRESETHALTREQ_OFFSET) -/* - * 0: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which - * is not relevant to the configuration string. - * - * 1: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the - * configuration string. - */ +#define DM_DMSTATUS_HASRESETHALTREQ 0x20 #define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4 #define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1 -#define DM_DMSTATUS_CONFSTRPTRVALID (0x1U << DM_DMSTATUS_CONFSTRPTRVALID_OFFSET) +#define DM_DMSTATUS_CONFSTRPTRVALID 0x10 /* - * 0: There is no Debug Module present. - * - * 1: There is a Debug Module and it conforms to version 0.11 of this + * invalid: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which + * is not relevant to the configuration structure. + */ +#define DM_DMSTATUS_CONFSTRPTRVALID_INVALID 0 +/* + * valid: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the + * configuration structure. + */ +#define DM_DMSTATUS_CONFSTRPTRVALID_VALID 1 +#define DM_DMSTATUS_VERSION_OFFSET 0 +#define DM_DMSTATUS_VERSION_LENGTH 4 +#define DM_DMSTATUS_VERSION 0xf +/* + * none: There is no Debug Module present. + */ +#define DM_DMSTATUS_VERSION_NONE 0 +/* + * 0.11: There is a Debug Module and it conforms to version 0.11 of this * specification. - * - * 2: There is a Debug Module and it conforms to version 0.13 of this + */ +#define DM_DMSTATUS_VERSION_0_11 1 +/* + * 0.13: There is a Debug Module and it conforms to version 0.13 of this * specification. - * - * 3: There is a Debug Module and it conforms to version 1.0 of this + */ +#define DM_DMSTATUS_VERSION_0_13 2 +/* + * 1.0: There is a Debug Module and it conforms to version 1.0 of this * specification. - * - * 15: There is a Debug Module but it does not conform to any + */ +#define DM_DMSTATUS_VERSION_1_0 3 +/* + * custom: There is a Debug Module but it does not conform to any * available version of this spec. */ -#define DM_DMSTATUS_VERSION_OFFSET 0 -#define DM_DMSTATUS_VERSION_LENGTH 4 -#define DM_DMSTATUS_VERSION (0xfU << DM_DMSTATUS_VERSION_OFFSET) +#define DM_DMSTATUS_VERSION_CUSTOM 15 #define DM_DMCONTROL 0x10 /* * Writing 0 clears the halt request bit for all currently selected @@ -1585,9 +1969,9 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_HALTREQ_OFFSET 31 +#define DM_DMCONTROL_HALTREQ_OFFSET 0x1f #define DM_DMCONTROL_HALTREQ_LENGTH 1 -#define DM_DMCONTROL_HALTREQ (0x1U << DM_DMCONTROL_HALTREQ_OFFSET) +#define DM_DMCONTROL_HALTREQ 0x80000000U /* * Writing 1 causes the currently selected harts to resume once, if * they are halted when the write occurs. It also clears the resume @@ -1597,9 +1981,9 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_RESUMEREQ_OFFSET 30 +#define DM_DMCONTROL_RESUMEREQ_OFFSET 0x1e #define DM_DMCONTROL_RESUMEREQ_LENGTH 1 -#define DM_DMCONTROL_RESUMEREQ (0x1U << DM_DMCONTROL_RESUMEREQ_OFFSET) +#define DM_DMCONTROL_RESUMEREQ 0x40000000 /* * This optional field writes the reset bit for all the currently * selected harts. To perform a reset the debugger writes 1, and then @@ -1614,60 +1998,73 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_HARTRESET_OFFSET 29 +#define DM_DMCONTROL_HARTRESET_OFFSET 0x1d #define DM_DMCONTROL_HARTRESET_LENGTH 1 -#define DM_DMCONTROL_HARTRESET (0x1U << DM_DMCONTROL_HARTRESET_OFFSET) +#define DM_DMCONTROL_HARTRESET 0x20000000 +#define DM_DMCONTROL_ACKHAVERESET_OFFSET 0x1c +#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1 +#define DM_DMCONTROL_ACKHAVERESET 0x10000000 /* - * 0: No effect. - * - * 1: Clears {\tt havereset} for any selected harts. - * - * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + * nop: No effect. */ -#define DM_DMCONTROL_ACKHAVERESET_OFFSET 28 -#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1 -#define DM_DMCONTROL_ACKHAVERESET (0x1U << DM_DMCONTROL_ACKHAVERESET_OFFSET) +#define DM_DMCONTROL_ACKHAVERESET_NOP 0 +/* + * ack: Clears {\tt havereset} for any selected harts. + */ +#define DM_DMCONTROL_ACKHAVERESET_ACK 1 /* - * 0: No effect. - * - * 1: Clears {\tt unavail} for any selected harts. - * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 27 +#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 0x1b #define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1 -#define DM_DMCONTROL_ACKUNAVAIL (0x1U << DM_DMCONTROL_ACKUNAVAIL_OFFSET) +#define DM_DMCONTROL_ACKUNAVAIL 0x8000000 +/* + * nop: No effect. + */ +#define DM_DMCONTROL_ACKUNAVAIL_NOP 0 +/* + * ack: Clears {\tt unavail} for any selected harts that are currently available. + */ +#define DM_DMCONTROL_ACKUNAVAIL_ACK 1 +/* + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ /* * Selects the definition of currently selected harts. - * - * 0: There is a single currently selected hart, that is selected by \Fhartsel. - * - * 1: There may be multiple currently selected harts -- the hart + */ +#define DM_DMCONTROL_HASEL_OFFSET 0x1a +#define DM_DMCONTROL_HASEL_LENGTH 1 +#define DM_DMCONTROL_HASEL 0x4000000 +/* + * single: There is a single currently selected hart, that is selected by \Fhartsel. + */ +#define DM_DMCONTROL_HASEL_SINGLE 0 +/* + * multiple: There may be multiple currently selected harts -- the hart * selected by \Fhartsel, plus those selected by the hart array mask * register. - * + */ +#define DM_DMCONTROL_HASEL_MULTIPLE 1 +/* * An implementation which does not implement the hart array mask register * must tie this field to 0. A debugger which wishes to use the hart array * mask register feature should set this bit and read back to see if the functionality * is supported. */ -#define DM_DMCONTROL_HASEL_OFFSET 26 -#define DM_DMCONTROL_HASEL_LENGTH 1 -#define DM_DMCONTROL_HASEL (0x1U << DM_DMCONTROL_HASEL_OFFSET) /* * The low 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ -#define DM_DMCONTROL_HARTSELLO_OFFSET 16 -#define DM_DMCONTROL_HARTSELLO_LENGTH 10 -#define DM_DMCONTROL_HARTSELLO (0x3ffU << DM_DMCONTROL_HARTSELLO_OFFSET) +#define DM_DMCONTROL_HARTSELLO_OFFSET 0x10 +#define DM_DMCONTROL_HARTSELLO_LENGTH 0xa +#define DM_DMCONTROL_HARTSELLO 0x3ff0000 /* * The high 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ #define DM_DMCONTROL_HARTSELHI_OFFSET 6 -#define DM_DMCONTROL_HARTSELHI_LENGTH 10 -#define DM_DMCONTROL_HARTSELHI (0x3ffU << DM_DMCONTROL_HARTSELHI_OFFSET) +#define DM_DMCONTROL_HARTSELHI_LENGTH 0xa +#define DM_DMCONTROL_HARTSELHI 0xffc0 /* * This optional field sets \Fkeepalive for all currently selected * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to @@ -1677,7 +2074,7 @@ */ #define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5 #define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1 -#define DM_DMCONTROL_SETKEEPALIVE (0x1U << DM_DMCONTROL_SETKEEPALIVE_OFFSET) +#define DM_DMCONTROL_SETKEEPALIVE 0x20 /* * This optional field clears \Fkeepalive for all currently selected * harts. @@ -1686,7 +2083,7 @@ */ #define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4 #define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1 -#define DM_DMCONTROL_CLRKEEPALIVE (0x1U << DM_DMCONTROL_CLRKEEPALIVE_OFFSET) +#define DM_DMCONTROL_CLRKEEPALIVE 0x10 /* * This optional field writes the halt-on-reset request bit for all * currently selected harts, unless \FdmDmcontrolClrresethaltreq is @@ -1701,7 +2098,7 @@ */ #define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3 #define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1 -#define DM_DMCONTROL_SETRESETHALTREQ (0x1U << DM_DMCONTROL_SETRESETHALTREQ_OFFSET) +#define DM_DMCONTROL_SETRESETHALTREQ 8 /* * This optional field clears the halt-on-reset request bit for all * currently selected harts. @@ -1710,7 +2107,7 @@ */ #define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 #define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 -#define DM_DMCONTROL_CLRRESETHALTREQ (0x1U << DM_DMCONTROL_CLRRESETHALTREQ_OFFSET) +#define DM_DMCONTROL_CLRRESETHALTREQ 4 /* * This bit controls the reset signal from the DM to the rest of the * hardware platform. The signal should reset every part of the hardware platform, including @@ -1722,7 +2119,7 @@ */ #define DM_DMCONTROL_NDMRESET_OFFSET 1 #define DM_DMCONTROL_NDMRESET_LENGTH 1 -#define DM_DMCONTROL_NDMRESET (0x1U << DM_DMCONTROL_NDMRESET_OFFSET) +#define DM_DMCONTROL_NDMRESET 2 /* * This bit serves as a reset signal for the Debug Module itself. * After changing the value of this bit, the debugger must poll @@ -1731,15 +2128,23 @@ * state change has completed. Hardware may * take an arbitrarily long time to complete activation or deactivation and will * indicate completion by setting \FdmDmcontrolDmactive to the requested value. - * - * 0: The module's state, including authentication mechanism, + */ +#define DM_DMCONTROL_DMACTIVE_OFFSET 0 +#define DM_DMCONTROL_DMACTIVE_LENGTH 1 +#define DM_DMCONTROL_DMACTIVE 1 +/* + * inactive: The module's state, including authentication mechanism, * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can * be written to something other than its reset value). Any accesses * to the module may fail. Specifically, \FdmDmstatusVersion might not return * correct data. - * - * 1: The module functions normally. - * + */ +#define DM_DMCONTROL_DMACTIVE_INACTIVE 0 +/* + * active: The module functions normally. + */ +#define DM_DMCONTROL_DMACTIVE_ACTIVE 1 +/* * No other mechanism should exist that may result in resetting the * Debug Module after power up. * @@ -1751,9 +2156,6 @@ * debugging, for example by preventing the Debug Module from being * power gated while debugging is active. */ -#define DM_DMCONTROL_DMACTIVE_OFFSET 0 -#define DM_DMCONTROL_DMACTIVE_LENGTH 1 -#define DM_DMCONTROL_DMACTIVE (0x1U << DM_DMCONTROL_DMACTIVE_OFFSET) #define DM_HARTINFO 0x12 /* * Number of {\tt dscratch} registers available for the debugger @@ -1761,20 +2163,23 @@ * The debugger can make no assumptions about the contents of these * registers between commands. */ -#define DM_HARTINFO_NSCRATCH_OFFSET 20 +#define DM_HARTINFO_NSCRATCH_OFFSET 0x14 #define DM_HARTINFO_NSCRATCH_LENGTH 4 -#define DM_HARTINFO_NSCRATCH (0xfU << DM_HARTINFO_NSCRATCH_OFFSET) +#define DM_HARTINFO_NSCRATCH 0xf00000 +#define DM_HARTINFO_DATAACCESS_OFFSET 0x10 +#define DM_HARTINFO_DATAACCESS_LENGTH 1 +#define DM_HARTINFO_DATAACCESS 0x10000 /* - * 0: The {\tt data} registers are shadowed in the hart by CSRs. + * csr: The {\tt data} registers are shadowed in the hart by CSRs. * Each CSR is DXLEN bits in size, and corresponds * to a single argument, per Table~\ref{tab:datareg}. - * - * 1: The {\tt data} registers are shadowed in the hart's memory map. + */ +#define DM_HARTINFO_DATAACCESS_CSR 0 +/* + * memory: The {\tt data} registers are shadowed in the hart's memory map. * Each register takes up 4 bytes in the memory map. */ -#define DM_HARTINFO_DATAACCESS_OFFSET 16 -#define DM_HARTINFO_DATAACCESS_LENGTH 1 -#define DM_HARTINFO_DATAACCESS (0x1U << DM_HARTINFO_DATAACCESS_OFFSET) +#define DM_HARTINFO_DATAACCESS_MEMORY 1 /* * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to * shadowing the {\tt data} registers. @@ -1782,12 +2187,16 @@ * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map * dedicated to shadowing the {\tt data} registers. * + * If this value is non-zero, then the {tt data} registers must go + * beyond being MRs and guarantee they each store a single value, that is + * readable/writable by either side. + * * Since there are at most 12 {\tt data} registers, the value in this * register must be 12 or smaller. */ -#define DM_HARTINFO_DATASIZE_OFFSET 12 +#define DM_HARTINFO_DATASIZE_OFFSET 0xc #define DM_HARTINFO_DATASIZE_LENGTH 4 -#define DM_HARTINFO_DATASIZE (0xfU << DM_HARTINFO_DATASIZE_OFFSET) +#define DM_HARTINFO_DATASIZE 0xf000 /* * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to * shadowing the {\tt data} registers. @@ -1798,8 +2207,8 @@ * \Xzero as the address register. */ #define DM_HARTINFO_DATAADDR_OFFSET 0 -#define DM_HARTINFO_DATAADDR_LENGTH 12 -#define DM_HARTINFO_DATAADDR (0xfffU << DM_HARTINFO_DATAADDR_OFFSET) +#define DM_HARTINFO_DATAADDR_LENGTH 0xc +#define DM_HARTINFO_DATAADDR 0xfff #define DM_HAWINDOWSEL 0x14 /* * The high bits of this field may be tied to 0, depending on how large @@ -1807,28 +2216,34 @@ * of this field may actually be writable. */ #define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 -#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15 -#define DM_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET) +#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 0xf +#define DM_HAWINDOWSEL_HAWINDOWSEL 0x7fff #define DM_HAWINDOW 0x15 #define DM_HAWINDOW_MASKDATA_OFFSET 0 -#define DM_HAWINDOW_MASKDATA_LENGTH 32 -#define DM_HAWINDOW_MASKDATA (0xffffffffU << DM_HAWINDOW_MASKDATA_OFFSET) +#define DM_HAWINDOW_MASKDATA_LENGTH 0x20 +#define DM_HAWINDOW_MASKDATA 0xffffffffU #define DM_ABSTRACTCS 0x16 /* * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. */ -#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 24 +#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 0x18 #define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 -#define DM_ABSTRACTCS_PROGBUFSIZE (0x1fU << DM_ABSTRACTCS_PROGBUFSIZE_OFFSET) +#define DM_ABSTRACTCS_PROGBUFSIZE 0x1f000000 +#define DM_ABSTRACTCS_BUSY_OFFSET 0xc +#define DM_ABSTRACTCS_BUSY_LENGTH 1 +#define DM_ABSTRACTCS_BUSY 0x1000 +/* + * ready: There is no abstract command currently being executed. + */ +#define DM_ABSTRACTCS_BUSY_READY 0 +/* + * busy: An abstract command is currently being executed. + */ +#define DM_ABSTRACTCS_BUSY_BUSY 1 /* - * 1: An abstract command is currently being executed. - * * This bit is set as soon as \RdmCommand is written, and is * not cleared until that command has completed. */ -#define DM_ABSTRACTCS_BUSY_OFFSET 12 -#define DM_ABSTRACTCS_BUSY_LENGTH 1 -#define DM_ABSTRACTCS_BUSY (0x1U << DM_ABSTRACTCS_BUSY_OFFSET) /* * This optional bit controls whether program buffer and abstract * memory accesses are performed with the exact and full set of @@ -1838,107 +2253,125 @@ * details of the latter are implementation-specific. When set to 0, * full permissions apply; when set to 1, relaxed permissions apply. */ -#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 11 +#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 0xb #define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1 -#define DM_ABSTRACTCS_RELAXEDPRIV (0x1U << DM_ABSTRACTCS_RELAXEDPRIV_OFFSET) +#define DM_ABSTRACTCS_RELAXEDPRIV 0x800 /* * Gets set if an abstract command fails. The bits in this field remain set until * they are cleared by writing 1 to them. No abstract command is * started until the value is reset to 0. * * This field only contains a valid value if \FdmAbstractcsBusy is 0. - * - * 0 (none): No error. - * - * 1 (busy): An abstract command was executing while \RdmCommand, + */ +#define DM_ABSTRACTCS_CMDERR_OFFSET 8 +#define DM_ABSTRACTCS_CMDERR_LENGTH 3 +#define DM_ABSTRACTCS_CMDERR 0x700 +/* + * none: No error. + */ +#define DM_ABSTRACTCS_CMDERR_NONE 0 +/* + * busy: An abstract command was executing while \RdmCommand, * \RdmAbstractcs, or \RdmAbstractauto was written, or when one * of the {\tt data} or {\tt progbuf} registers was read or written. * This status is only written if \FdmAbstractcsCmderr contains 0. - * - * 2 (not supported): The command in \RdmCommand is not supported. It + */ +#define DM_ABSTRACTCS_CMDERR_BUSY 1 +/* + * not supported: The command in \RdmCommand is not supported. It * may be supported with different options set, but it will not be * supported at a later time when the hart or system state are * different. - * - * 3 (exception): An exception occurred while executing the command + */ +#define DM_ABSTRACTCS_CMDERR_NOT_SUPPORTED 2 +/* + * exception: An exception occurred while executing the command * (e.g.\ while executing the Program Buffer). - * - * 4 (halt/resume): The abstract command couldn't execute because the + */ +#define DM_ABSTRACTCS_CMDERR_EXCEPTION 3 +/* + * halt/resume: The abstract command couldn't execute because the * hart wasn't in the required state (running/halted), or unavailable. - * - * 5 (bus): The abstract command failed due to a bus error (e.g.\ + */ +#define DM_ABSTRACTCS_CMDERR_HALT_RESUME 4 +/* + * bus: The abstract command failed due to a bus error (e.g.\ * alignment, access size, or timeout). - * - * 6: Reserved for future use. - * - * 7 (other): The command failed for another reason. */ -#define DM_ABSTRACTCS_CMDERR_OFFSET 8 -#define DM_ABSTRACTCS_CMDERR_LENGTH 3 -#define DM_ABSTRACTCS_CMDERR (0x7U << DM_ABSTRACTCS_CMDERR_OFFSET) +#define DM_ABSTRACTCS_CMDERR_BUS 5 +/* + * reserved: Reserved for future use. + */ +#define DM_ABSTRACTCS_CMDERR_RESERVED 6 +/* + * other: The command failed for another reason. + */ +#define DM_ABSTRACTCS_CMDERR_OTHER 7 /* * Number of {\tt data} registers that are implemented as part of the * abstract command interface. Valid sizes are 1 -- 12. */ #define DM_ABSTRACTCS_DATACOUNT_OFFSET 0 #define DM_ABSTRACTCS_DATACOUNT_LENGTH 4 -#define DM_ABSTRACTCS_DATACOUNT (0xfU << DM_ABSTRACTCS_DATACOUNT_OFFSET) +#define DM_ABSTRACTCS_DATACOUNT 0xf #define DM_COMMAND 0x17 /* * The type determines the overall functionality of this * abstract command. */ -#define DM_COMMAND_CMDTYPE_OFFSET 24 +#define DM_COMMAND_CMDTYPE_OFFSET 0x18 #define DM_COMMAND_CMDTYPE_LENGTH 8 -#define DM_COMMAND_CMDTYPE (0xffU << DM_COMMAND_CMDTYPE_OFFSET) +#define DM_COMMAND_CMDTYPE 0xff000000U /* * This field is interpreted in a command-specific manner, * described for each abstract command. */ #define DM_COMMAND_CONTROL_OFFSET 0 -#define DM_COMMAND_CONTROL_LENGTH 24 -#define DM_COMMAND_CONTROL (0xffffffU << DM_COMMAND_CONTROL_OFFSET) +#define DM_COMMAND_CONTROL_LENGTH 0x18 +#define DM_COMMAND_CONTROL 0xffffff #define DM_ABSTRACTAUTO 0x18 /* * When a bit in this field is 1, read or write accesses to the - * corresponding {\tt progbuf} word cause the command in \RdmCommand to - * be executed again. + * corresponding {\tt progbuf} word cause the DM to act as if the + * current value in \RdmCommand was written there again after the + * access to {\tt progbuf} completes. */ -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 0x10 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 0x10 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF 0xffff0000U /* * When a bit in this field is 1, read or write accesses to the - * corresponding {\tt data} word cause the command in \RdmCommand to be - * executed again. + * corresponding {\tt data} word cause the DM to act as if the current + * value in \RdmCommand was written there again after the + * access to {\tt data} completes. */ #define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 -#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 -#define DM_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) +#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 0xc +#define DM_ABSTRACTAUTO_AUTOEXECDATA 0xfff #define DM_CONFSTRPTR0 0x19 #define DM_CONFSTRPTR0_ADDR_OFFSET 0 -#define DM_CONFSTRPTR0_ADDR_LENGTH 32 -#define DM_CONFSTRPTR0_ADDR (0xffffffffU << DM_CONFSTRPTR0_ADDR_OFFSET) +#define DM_CONFSTRPTR0_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR0_ADDR 0xffffffffU #define DM_CONFSTRPTR1 0x1a #define DM_CONFSTRPTR1_ADDR_OFFSET 0 -#define DM_CONFSTRPTR1_ADDR_LENGTH 32 -#define DM_CONFSTRPTR1_ADDR (0xffffffffU << DM_CONFSTRPTR1_ADDR_OFFSET) +#define DM_CONFSTRPTR1_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR1_ADDR 0xffffffffU #define DM_CONFSTRPTR2 0x1b #define DM_CONFSTRPTR2_ADDR_OFFSET 0 -#define DM_CONFSTRPTR2_ADDR_LENGTH 32 -#define DM_CONFSTRPTR2_ADDR (0xffffffffU << DM_CONFSTRPTR2_ADDR_OFFSET) +#define DM_CONFSTRPTR2_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR2_ADDR 0xffffffffU #define DM_CONFSTRPTR3 0x1c #define DM_CONFSTRPTR3_ADDR_OFFSET 0 -#define DM_CONFSTRPTR3_ADDR_LENGTH 32 -#define DM_CONFSTRPTR3_ADDR (0xffffffffU << DM_CONFSTRPTR3_ADDR_OFFSET) +#define DM_CONFSTRPTR3_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR3_ADDR 0xffffffffU #define DM_NEXTDM 0x1d #define DM_NEXTDM_ADDR_OFFSET 0 -#define DM_NEXTDM_ADDR_LENGTH 32 -#define DM_NEXTDM_ADDR (0xffffffffU << DM_NEXTDM_ADDR_OFFSET) +#define DM_NEXTDM_ADDR_LENGTH 0x20 +#define DM_NEXTDM_ADDR 0xffffffffU #define DM_DATA0 0x04 #define DM_DATA0_DATA_OFFSET 0 -#define DM_DATA0_DATA_LENGTH 32 -#define DM_DATA0_DATA (0xffffffffU << DM_DATA0_DATA_OFFSET) +#define DM_DATA0_DATA_LENGTH 0x20 +#define DM_DATA0_DATA 0xffffffffU #define DM_DATA1 0x05 #define DM_DATA2 0x06 #define DM_DATA3 0x07 @@ -1952,8 +2385,8 @@ #define DM_DATA11 0x0f #define DM_PROGBUF0 0x20 #define DM_PROGBUF0_DATA_OFFSET 0 -#define DM_PROGBUF0_DATA_LENGTH 32 -#define DM_PROGBUF0_DATA (0xffffffffU << DM_PROGBUF0_DATA_OFFSET) +#define DM_PROGBUF0_DATA_LENGTH 0x20 +#define DM_PROGBUF0_DATA 0xffffffffU #define DM_PROGBUF1 0x21 #define DM_PROGBUF2 0x22 #define DM_PROGBUF3 0x23 @@ -1971,17 +2404,20 @@ #define DM_PROGBUF15 0x2f #define DM_AUTHDATA 0x30 #define DM_AUTHDATA_DATA_OFFSET 0 -#define DM_AUTHDATA_DATA_LENGTH 32 -#define DM_AUTHDATA_DATA (0xffffffffU << DM_AUTHDATA_DATA_OFFSET) +#define DM_AUTHDATA_DATA_LENGTH 0x20 +#define DM_AUTHDATA_DATA 0xffffffffU #define DM_DMCS2 0x32 +#define DM_DMCS2_GROUPTYPE_OFFSET 0xb +#define DM_DMCS2_GROUPTYPE_LENGTH 1 +#define DM_DMCS2_GROUPTYPE 0x800 /* - * 0: The remaining fields in this register configure halt groups. - * - * 1: The remaining fields in this register configure resume groups. + * halt: The remaining fields in this register configure halt groups. */ -#define DM_DMCS2_GROUPTYPE_OFFSET 11 -#define DM_DMCS2_GROUPTYPE_LENGTH 1 -#define DM_DMCS2_GROUPTYPE (0x1U << DM_DMCS2_GROUPTYPE_OFFSET) +#define DM_DMCS2_GROUPTYPE_HALT 0 +/* + * resume: The remaining fields in this register configure resume groups. + */ +#define DM_DMCS2_GROUPTYPE_RESUME 1 /* * This field contains the currently selected DM external trigger. * @@ -1990,7 +2426,7 @@ */ #define DM_DMCS2_DMEXTTRIGGER_OFFSET 7 #define DM_DMCS2_DMEXTTRIGGER_LENGTH 4 -#define DM_DMCS2_DMEXTTRIGGER (0xfU << DM_DMCS2_DMEXTTRIGGER_OFFSET) +#define DM_DMCS2_DMEXTTRIGGER 0x780 /* * When \FdmDmcsTwoHgselect is 0, contains the group of the hart * specified by \Fhartsel. @@ -1998,7 +2434,8 @@ * When \FdmDmcsTwoHgselect is 1, contains the group of the DM external * trigger selected by \FdmDmcsTwoDmexttrigger. * - * Writes only have an effect if \FdmDmcsTwoHgwrite is also written 1. + * The value written to this field is ignored unless \FdmDmcsTwoHgwrite + * is also written 1. * * Group numbers are contiguous starting at 0, with the highest number * being implementation-dependent, and possibly different between @@ -2009,7 +2446,7 @@ */ #define DM_DMCS2_GROUP_OFFSET 2 #define DM_DMCS2_GROUP_LENGTH 5 -#define DM_DMCS2_GROUP (0x1fU << DM_DMCS2_GROUP_OFFSET) +#define DM_DMCS2_GROUP 0x7c /* * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected * hart the DM will change its group to the value written to \FdmDmcsTwoGroup, @@ -2027,45 +2464,53 @@ */ #define DM_DMCS2_HGWRITE_OFFSET 1 #define DM_DMCS2_HGWRITE_LENGTH 1 -#define DM_DMCS2_HGWRITE (0x1U << DM_DMCS2_HGWRITE_OFFSET) +#define DM_DMCS2_HGWRITE 2 +#define DM_DMCS2_HGSELECT_OFFSET 0 +#define DM_DMCS2_HGSELECT_LENGTH 1 +#define DM_DMCS2_HGSELECT 1 +/* + * harts: Operate on harts. + */ +#define DM_DMCS2_HGSELECT_HARTS 0 +/* + * triggers: Operate on DM external triggers. + */ +#define DM_DMCS2_HGSELECT_TRIGGERS 1 /* - * 0: Operate on harts. - * - * 1: Operate on DM external triggers. - * * If there are no DM external triggers, this field must be tied to 0. */ -#define DM_DMCS2_HGSELECT_OFFSET 0 -#define DM_DMCS2_HGSELECT_LENGTH 1 -#define DM_DMCS2_HGSELECT (0x1U << DM_DMCS2_HGSELECT_OFFSET) #define DM_HALTSUM0 0x40 #define DM_HALTSUM0_HALTSUM0_OFFSET 0 -#define DM_HALTSUM0_HALTSUM0_LENGTH 32 -#define DM_HALTSUM0_HALTSUM0 (0xffffffffU << DM_HALTSUM0_HALTSUM0_OFFSET) +#define DM_HALTSUM0_HALTSUM0_LENGTH 0x20 +#define DM_HALTSUM0_HALTSUM0 0xffffffffU #define DM_HALTSUM1 0x13 #define DM_HALTSUM1_HALTSUM1_OFFSET 0 -#define DM_HALTSUM1_HALTSUM1_LENGTH 32 -#define DM_HALTSUM1_HALTSUM1 (0xffffffffU << DM_HALTSUM1_HALTSUM1_OFFSET) +#define DM_HALTSUM1_HALTSUM1_LENGTH 0x20 +#define DM_HALTSUM1_HALTSUM1 0xffffffffU #define DM_HALTSUM2 0x34 #define DM_HALTSUM2_HALTSUM2_OFFSET 0 -#define DM_HALTSUM2_HALTSUM2_LENGTH 32 -#define DM_HALTSUM2_HALTSUM2 (0xffffffffU << DM_HALTSUM2_HALTSUM2_OFFSET) +#define DM_HALTSUM2_HALTSUM2_LENGTH 0x20 +#define DM_HALTSUM2_HALTSUM2 0xffffffffU #define DM_HALTSUM3 0x35 #define DM_HALTSUM3_HALTSUM3_OFFSET 0 -#define DM_HALTSUM3_HALTSUM3_LENGTH 32 -#define DM_HALTSUM3_HALTSUM3 (0xffffffffU << DM_HALTSUM3_HALTSUM3_OFFSET) +#define DM_HALTSUM3_HALTSUM3_LENGTH 0x20 +#define DM_HALTSUM3_HALTSUM3 0xffffffffU #define DM_SBCS 0x38 +#define DM_SBCS_SBVERSION_OFFSET 0x1d +#define DM_SBCS_SBVERSION_LENGTH 3 +#define DM_SBCS_SBVERSION 0xe0000000U /* - * 0: The System Bus interface conforms to mainline drafts of this + * legacy: The System Bus interface conforms to mainline drafts of this * spec older than 1 January, 2018. - * - * 1: The System Bus interface conforms to this version of the spec. - * + */ +#define DM_SBCS_SBVERSION_LEGACY 0 +/* + * 1.0: The System Bus interface conforms to this version of the spec. + */ +#define DM_SBCS_SBVERSION_1_0 1 +/* * Other values are reserved for future versions. */ -#define DM_SBCS_SBVERSION_OFFSET 29 -#define DM_SBCS_SBVERSION_LENGTH 3 -#define DM_SBCS_SBVERSION (0x7U << DM_SBCS_SBVERSION_OFFSET) /* * Set when the debugger attempts to read data while a read is in * progress, or when the debugger initiates a new access while one is @@ -2075,9 +2520,9 @@ * While this field is set, no more system bus accesses can be * initiated by the Debug Module. */ -#define DM_SBCS_SBBUSYERROR_OFFSET 22 +#define DM_SBCS_SBBUSYERROR_OFFSET 0x16 #define DM_SBCS_SBBUSYERROR_LENGTH 1 -#define DM_SBCS_SBBUSYERROR (0x1U << DM_SBCS_SBBUSYERROR_OFFSET) +#define DM_SBCS_SBBUSYERROR 0x400000 /* * When 1, indicates the system bus master is busy. (Whether the * system bus itself is busy is related, but not the same thing.) This @@ -2088,49 +2533,60 @@ * behavior. A debugger must not write to \RdmSbcs until it reads * \FdmSbcsSbbusy as 0. */ -#define DM_SBCS_SBBUSY_OFFSET 21 +#define DM_SBCS_SBBUSY_OFFSET 0x15 #define DM_SBCS_SBBUSY_LENGTH 1 -#define DM_SBCS_SBBUSY (0x1U << DM_SBCS_SBBUSY_OFFSET) +#define DM_SBCS_SBBUSY 0x200000 /* * When 1, every write to \RdmSbaddressZero automatically triggers a * system bus read at the new address. */ -#define DM_SBCS_SBREADONADDR_OFFSET 20 +#define DM_SBCS_SBREADONADDR_OFFSET 0x14 #define DM_SBCS_SBREADONADDR_LENGTH 1 -#define DM_SBCS_SBREADONADDR (0x1U << DM_SBCS_SBREADONADDR_OFFSET) +#define DM_SBCS_SBREADONADDR 0x100000 /* * Select the access size to use for system bus accesses. - * - * 0: 8-bit - * - * 1: 16-bit - * - * 2: 32-bit - * - * 3: 64-bit - * - * 4: 128-bit - * + */ +#define DM_SBCS_SBACCESS_OFFSET 0x11 +#define DM_SBCS_SBACCESS_LENGTH 3 +#define DM_SBCS_SBACCESS 0xe0000 +/* + * 8bit: 8-bit + */ +#define DM_SBCS_SBACCESS_8BIT 0 +/* + * 16bit: 16-bit + */ +#define DM_SBCS_SBACCESS_16BIT 1 +/* + * 32bit: 32-bit + */ +#define DM_SBCS_SBACCESS_32BIT 2 +/* + * 64bit: 64-bit + */ +#define DM_SBCS_SBACCESS_64BIT 3 +/* + * 128bit: 128-bit + */ +#define DM_SBCS_SBACCESS_128BIT 4 +/* * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus * access, the access is not performed and \FdmSbcsSberror is set to 4. */ -#define DM_SBCS_SBACCESS_OFFSET 17 -#define DM_SBCS_SBACCESS_LENGTH 3 -#define DM_SBCS_SBACCESS (0x7U << DM_SBCS_SBACCESS_OFFSET) /* * When 1, {\tt sbaddress} is incremented by the access size (in * bytes) selected in \FdmSbcsSbaccess after every system bus access. */ -#define DM_SBCS_SBAUTOINCREMENT_OFFSET 16 +#define DM_SBCS_SBAUTOINCREMENT_OFFSET 0x10 #define DM_SBCS_SBAUTOINCREMENT_LENGTH 1 -#define DM_SBCS_SBAUTOINCREMENT (0x1U << DM_SBCS_SBAUTOINCREMENT_OFFSET) +#define DM_SBCS_SBAUTOINCREMENT 0x10000 /* * When 1, every read from \RdmSbdataZero automatically triggers a * system bus read at the (possibly auto-incremented) address. */ -#define DM_SBCS_SBREADONDATA_OFFSET 15 +#define DM_SBCS_SBREADONDATA_OFFSET 0xf #define DM_SBCS_SBREADONDATA_LENGTH 1 -#define DM_SBCS_SBREADONDATA (0x1U << DM_SBCS_SBREADONDATA_OFFSET) +#define DM_SBCS_SBREADONDATA 0x8000 /* * When the Debug Module's system bus * master encounters an error, this field gets set. The bits in this @@ -2139,121 +2595,133 @@ * initiated by the Debug Module. * * An implementation may report ``Other'' (7) for any error condition. - * - * 0: There was no bus error. - * - * 1: There was a timeout. - * - * 2: A bad address was accessed. - * - * 3: There was an alignment error. - * - * 4: An access of unsupported size was requested. - * - * 7: Other. */ -#define DM_SBCS_SBERROR_OFFSET 12 +#define DM_SBCS_SBERROR_OFFSET 0xc #define DM_SBCS_SBERROR_LENGTH 3 -#define DM_SBCS_SBERROR (0x7U << DM_SBCS_SBERROR_OFFSET) +#define DM_SBCS_SBERROR 0x7000 +/* + * none: There was no bus error. + */ +#define DM_SBCS_SBERROR_NONE 0 +/* + * timeout: There was a timeout. + */ +#define DM_SBCS_SBERROR_TIMEOUT 1 +/* + * address: A bad address was accessed. + */ +#define DM_SBCS_SBERROR_ADDRESS 2 +/* + * alignment: There was an alignment error. + */ +#define DM_SBCS_SBERROR_ALIGNMENT 3 +/* + * size: An access of unsupported size was requested. + */ +#define DM_SBCS_SBERROR_SIZE 4 +/* + * other: Other. + */ +#define DM_SBCS_SBERROR_OTHER 7 /* * Width of system bus addresses in bits. (0 indicates there is no bus * access support.) */ #define DM_SBCS_SBASIZE_OFFSET 5 #define DM_SBCS_SBASIZE_LENGTH 7 -#define DM_SBCS_SBASIZE (0x7fU << DM_SBCS_SBASIZE_OFFSET) +#define DM_SBCS_SBASIZE 0xfe0 /* * 1 when 128-bit system bus accesses are supported. */ #define DM_SBCS_SBACCESS128_OFFSET 4 #define DM_SBCS_SBACCESS128_LENGTH 1 -#define DM_SBCS_SBACCESS128 (0x1U << DM_SBCS_SBACCESS128_OFFSET) +#define DM_SBCS_SBACCESS128 0x10 /* * 1 when 64-bit system bus accesses are supported. */ #define DM_SBCS_SBACCESS64_OFFSET 3 #define DM_SBCS_SBACCESS64_LENGTH 1 -#define DM_SBCS_SBACCESS64 (0x1U << DM_SBCS_SBACCESS64_OFFSET) +#define DM_SBCS_SBACCESS64 8 /* * 1 when 32-bit system bus accesses are supported. */ #define DM_SBCS_SBACCESS32_OFFSET 2 #define DM_SBCS_SBACCESS32_LENGTH 1 -#define DM_SBCS_SBACCESS32 (0x1U << DM_SBCS_SBACCESS32_OFFSET) +#define DM_SBCS_SBACCESS32 4 /* * 1 when 16-bit system bus accesses are supported. */ #define DM_SBCS_SBACCESS16_OFFSET 1 #define DM_SBCS_SBACCESS16_LENGTH 1 -#define DM_SBCS_SBACCESS16 (0x1U << DM_SBCS_SBACCESS16_OFFSET) +#define DM_SBCS_SBACCESS16 2 /* * 1 when 8-bit system bus accesses are supported. */ #define DM_SBCS_SBACCESS8_OFFSET 0 #define DM_SBCS_SBACCESS8_LENGTH 1 -#define DM_SBCS_SBACCESS8 (0x1U << DM_SBCS_SBACCESS8_OFFSET) +#define DM_SBCS_SBACCESS8 1 #define DM_SBADDRESS0 0x39 /* * Accesses bits 31:0 of the physical address in {\tt sbaddress}. */ #define DM_SBADDRESS0_ADDRESS_OFFSET 0 -#define DM_SBADDRESS0_ADDRESS_LENGTH 32 -#define DM_SBADDRESS0_ADDRESS (0xffffffffU << DM_SBADDRESS0_ADDRESS_OFFSET) +#define DM_SBADDRESS0_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS0_ADDRESS 0xffffffffU #define DM_SBADDRESS1 0x3a /* * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DM_SBADDRESS1_ADDRESS_OFFSET 0 -#define DM_SBADDRESS1_ADDRESS_LENGTH 32 -#define DM_SBADDRESS1_ADDRESS (0xffffffffU << DM_SBADDRESS1_ADDRESS_OFFSET) +#define DM_SBADDRESS1_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS1_ADDRESS 0xffffffffU #define DM_SBADDRESS2 0x3b /* * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DM_SBADDRESS2_ADDRESS_OFFSET 0 -#define DM_SBADDRESS2_ADDRESS_LENGTH 32 -#define DM_SBADDRESS2_ADDRESS (0xffffffffU << DM_SBADDRESS2_ADDRESS_OFFSET) +#define DM_SBADDRESS2_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS2_ADDRESS 0xffffffffU #define DM_SBADDRESS3 0x37 /* * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DM_SBADDRESS3_ADDRESS_OFFSET 0 -#define DM_SBADDRESS3_ADDRESS_LENGTH 32 -#define DM_SBADDRESS3_ADDRESS (0xffffffffU << DM_SBADDRESS3_ADDRESS_OFFSET) +#define DM_SBADDRESS3_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS3_ADDRESS 0xffffffffU #define DM_SBDATA0 0x3c /* * Accesses bits 31:0 of {\tt sbdata}. */ #define DM_SBDATA0_DATA_OFFSET 0 -#define DM_SBDATA0_DATA_LENGTH 32 -#define DM_SBDATA0_DATA (0xffffffffU << DM_SBDATA0_DATA_OFFSET) +#define DM_SBDATA0_DATA_LENGTH 0x20 +#define DM_SBDATA0_DATA 0xffffffffU #define DM_SBDATA1 0x3d /* * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that * wide). */ #define DM_SBDATA1_DATA_OFFSET 0 -#define DM_SBDATA1_DATA_LENGTH 32 -#define DM_SBDATA1_DATA (0xffffffffU << DM_SBDATA1_DATA_OFFSET) +#define DM_SBDATA1_DATA_LENGTH 0x20 +#define DM_SBDATA1_DATA 0xffffffffU #define DM_SBDATA2 0x3e /* * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that * wide). */ #define DM_SBDATA2_DATA_OFFSET 0 -#define DM_SBDATA2_DATA_LENGTH 32 -#define DM_SBDATA2_DATA (0xffffffffU << DM_SBDATA2_DATA_OFFSET) +#define DM_SBDATA2_DATA_LENGTH 0x20 +#define DM_SBDATA2_DATA 0xffffffffU #define DM_SBDATA3 0x3f /* * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that * wide). */ #define DM_SBDATA3_DATA_OFFSET 0 -#define DM_SBDATA3_DATA_LENGTH 32 -#define DM_SBDATA3_DATA (0xffffffffU << DM_SBDATA3_DATA_OFFSET) +#define DM_SBDATA3_DATA_LENGTH 0x20 +#define DM_SBDATA3_DATA 0xffffffffU #define DM_CUSTOM 0x1f #define DM_CUSTOM0 0x70 #define DM_CUSTOM1 0x71 @@ -2277,75 +2745,98 @@ */ #define SHORTNAME_FIELD_OFFSET 0 #define SHORTNAME_FIELD_LENGTH 8 -#define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET) +#define SHORTNAME_FIELD 0xff /* * This is 0 to indicate Access Register Command. */ -#define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24 +#define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 0x18 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 -#define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET) +#define AC_ACCESS_REGISTER_CMDTYPE 0xff000000U +#define AC_ACCESS_REGISTER_AARSIZE_OFFSET 0x14 +#define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3 +#define AC_ACCESS_REGISTER_AARSIZE 0x700000 +/* + * 32bit: Access the lowest 32 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_32BIT 2 +/* + * 64bit: Access the lowest 64 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_64BIT 3 +/* + * 128bit: Access the lowest 128 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_128BIT 4 /* - * 2: Access the lowest 32 bits of the register. - * - * 3: Access the lowest 64 bits of the register. - * - * 4: Access the lowest 128 bits of the register. - * * If \FacAccessregisterAarsize specifies a size larger than the register's actual size, * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize * less than or equal to the register's actual size must be supported. + * Writing less than the full register may be supported, but what + * happens to the high bits in that case is \unspecified. * * This field controls the Argument Width as referenced in * Table~\ref{tab:datareg}. */ -#define AC_ACCESS_REGISTER_AARSIZE_OFFSET 20 -#define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3 -#define AC_ACCESS_REGISTER_AARSIZE (0x7U << AC_ACCESS_REGISTER_AARSIZE_OFFSET) +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 0x13 +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1 +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT 0x80000 /* - * 0: No effect. This variant must be supported. - * - * 1: After a successful register access, \FacAccessregisterRegno is + * disabled: No effect. This variant must be supported. + */ +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_DISABLED 0 +/* + * enabled: After a successful register access, \FacAccessregisterRegno is * incremented. Incrementing past the highest supported value * causes \FacAccessregisterRegno to become \unspecified. Supporting * this variant is optional. It is undefined whether the increment * happens when \FacAccessregisterTransfer is 0. */ -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 19 -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1 -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT (0x1U << AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET) +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_ENABLED 1 +#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 0x12 +#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 +#define AC_ACCESS_REGISTER_POSTEXEC 0x40000 /* - * 0: No effect. This variant must be supported, and is the only + * disabled: No effect. This variant must be supported, and is the only * supported one if \FdmAbstractcsProgbufsize is 0. - * - * 1: Execute the program in the Program Buffer exactly once after + */ +#define AC_ACCESS_REGISTER_POSTEXEC_DISABLED 0 +/* + * enabled: Execute the program in the Program Buffer exactly once after * performing the transfer, if any. Supporting this variant is * optional. */ -#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18 -#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 -#define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET) +#define AC_ACCESS_REGISTER_POSTEXEC_ENABLED 1 +#define AC_ACCESS_REGISTER_TRANSFER_OFFSET 0x11 +#define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 +#define AC_ACCESS_REGISTER_TRANSFER 0x20000 +/* + * disabled: Don't do the operation specified by \FacAccessregisterWrite. + */ +#define AC_ACCESS_REGISTER_TRANSFER_DISABLED 0 +/* + * enabled: Do the operation specified by \FacAccessregisterWrite. + */ +#define AC_ACCESS_REGISTER_TRANSFER_ENABLED 1 /* - * 0: Don't do the operation specified by \FacAccessregisterWrite. - * - * 1: Do the operation specified by \FacAccessregisterWrite. - * * This bit can be used to just execute the Program Buffer without * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno. */ -#define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17 -#define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 -#define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET) /* * When \FacAccessregisterTransfer is set: - * 0: Copy data from the specified register into {\tt arg0} portion + */ +#define AC_ACCESS_REGISTER_WRITE_OFFSET 0x10 +#define AC_ACCESS_REGISTER_WRITE_LENGTH 1 +#define AC_ACCESS_REGISTER_WRITE 0x10000 +/* + * arg0: Copy data from the specified register into {\tt arg0} portion * of {\tt data}. - * - * 1: Copy data from {\tt arg0} portion of {\tt data} into the + */ +#define AC_ACCESS_REGISTER_WRITE_ARG0 0 +/* + * register: Copy data from {\tt arg0} portion of {\tt data} into the * specified register. */ -#define AC_ACCESS_REGISTER_WRITE_OFFSET 16 -#define AC_ACCESS_REGISTER_WRITE_LENGTH 1 -#define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET) +#define AC_ACCESS_REGISTER_WRITE_REGISTER 1 /* * Number of the register to access, as described in * Table~\ref{tab:regno}. @@ -2353,51 +2844,65 @@ * supported on a non-halted hart. */ #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 -#define AC_ACCESS_REGISTER_REGNO_LENGTH 16 -#define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET) +#define AC_ACCESS_REGISTER_REGNO_LENGTH 0x10 +#define AC_ACCESS_REGISTER_REGNO 0xffff /* * This is 1 to indicate Quick Access command. */ -#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24 +#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 0x18 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 -#define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET) +#define AC_QUICK_ACCESS_CMDTYPE 0xff000000U /* * This is 2 to indicate Access Memory Command. */ -#define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 24 +#define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 0x18 #define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8 -#define AC_ACCESS_MEMORY_CMDTYPE (0xffU << AC_ACCESS_MEMORY_CMDTYPE_OFFSET) +#define AC_ACCESS_MEMORY_CMDTYPE 0xff000000U /* * An implementation does not have to implement both virtual and * physical accesses, but it must fail accesses that it doesn't * support. - * - * 0: Addresses are physical (to the hart they are performed on). - * - * 1: Addresses are virtual, and translated the way they would be from + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 0x17 +#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1 +#define AC_ACCESS_MEMORY_AAMVIRTUAL 0x800000 +/* + * physical: Addresses are physical (to the hart they are performed on). + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_PHYSICAL 0 +/* + * virtual: Addresses are virtual, and translated the way they would be from * M-mode, with \FcsrMstatusMprv set. - * + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_VIRTUAL 1 +/* * Debug Modules on systems without address translation (i.e. virtual addresses equal physical) * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as * that same abstract command with \FacAccessmemoryAamvirtual cleared. */ -#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 23 -#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1 -#define AC_ACCESS_MEMORY_AAMVIRTUAL (0x1U << AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET) +#define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 0x14 +#define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3 +#define AC_ACCESS_MEMORY_AAMSIZE 0x700000 /* - * 0: Access the lowest 8 bits of the memory location. - * - * 1: Access the lowest 16 bits of the memory location. - * - * 2: Access the lowest 32 bits of the memory location. - * - * 3: Access the lowest 64 bits of the memory location. - * - * 4: Access the lowest 128 bits of the memory location. + * 8bit: Access the lowest 8 bits of the memory location. */ -#define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 20 -#define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3 -#define AC_ACCESS_MEMORY_AAMSIZE (0x7U << AC_ACCESS_MEMORY_AAMSIZE_OFFSET) +#define AC_ACCESS_MEMORY_AAMSIZE_8BIT 0 +/* + * 16bit: Access the lowest 16 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_16BIT 1 +/* + * 32bit: Access the lowest 32 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_32BIT 2 +/* + * 64bit: Access the lowest 64 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_64BIT 3 +/* + * 128bit: Access the lowest 128 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_128BIT 4 /* * After a memory access has completed, if this bit is 1, increment * {\tt arg1} (which contains the address used) by the number of bytes @@ -2406,123 +2911,126 @@ * Supporting this variant is optional, but highly recommended for * performance reasons. */ -#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 19 +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 0x13 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1 -#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT (0x1U << AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET) +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT 0x80000 +#define AC_ACCESS_MEMORY_WRITE_OFFSET 0x10 +#define AC_ACCESS_MEMORY_WRITE_LENGTH 1 +#define AC_ACCESS_MEMORY_WRITE 0x10000 /* - * 0: Copy data from the memory location specified in {\tt arg1} into - * the low bits of {\tt arg0}. Any remaining bits of {\tt arg0} now - * have an undefined value. - * - * 1: Copy data from the low bits of {\tt arg0} into the memory + * arg0: Copy data from the memory location specified in {\tt arg1} into + * the low bits of {\tt arg0}. The value of the remaining bits of + * {\tt arg0} are \unspecified. + */ +#define AC_ACCESS_MEMORY_WRITE_ARG0 0 +/* + * memory: Copy data from the low bits of {\tt arg0} into the memory * location specified in {\tt arg1}. */ -#define AC_ACCESS_MEMORY_WRITE_OFFSET 16 -#define AC_ACCESS_MEMORY_WRITE_LENGTH 1 -#define AC_ACCESS_MEMORY_WRITE (0x1U << AC_ACCESS_MEMORY_WRITE_OFFSET) +#define AC_ACCESS_MEMORY_WRITE_MEMORY 1 /* * These bits are reserved for target-specific uses. */ -#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 14 +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 0xe #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2 -#define AC_ACCESS_MEMORY_TARGET_SPECIFIC (0x3U << AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET) +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC 0xc000 #define VIRT_PRIV virtual /* * Contains the virtualization mode the hart was operating in when Debug - * Mode was entered. The encoding is described in Table \ref{tab:privlevel}, + * Mode was entered. The encoding is described in Table \ref{tab:privmode}, * and matches the virtualization mode encoding from the Privileged Spec. * A user can write this value to change the hart's virtualization mode * when exiting Debug Mode. */ #define VIRT_PRIV_V_OFFSET 2 #define VIRT_PRIV_V_LENGTH 1 -#define VIRT_PRIV_V (0x1U << VIRT_PRIV_V_OFFSET) +#define VIRT_PRIV_V 4 /* - * Contains the privilege level the hart was operating in when Debug + * Contains the privilege mode the hart was operating in when Debug * Mode was entered. The encoding is described in Table - * \ref{tab:privlevel}, and matches the privilege level encoding from + * \ref{tab:privmode}, and matches the privilege mode encoding from * the Privileged Spec. A user can write this - * value to change the hart's privilege level when exiting Debug Mode. + * value to change the hart's privilege mode when exiting Debug Mode. */ #define VIRT_PRIV_PRV_OFFSET 0 #define VIRT_PRIV_PRV_LENGTH 2 -#define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET) +#define VIRT_PRIV_PRV 3 #define DMI_SERCS 0x34 /* * Number of supported serial ports. */ -#define DMI_SERCS_SERIALCOUNT_OFFSET 28 +#define DMI_SERCS_SERIALCOUNT_OFFSET 0x1c #define DMI_SERCS_SERIALCOUNT_LENGTH 4 -#define DMI_SERCS_SERIALCOUNT (0xfU << DMI_SERCS_SERIALCOUNT_OFFSET) +#define DMI_SERCS_SERIALCOUNT 0xf0000000U /* * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx. */ -#define DMI_SERCS_SERIAL_OFFSET 24 +#define DMI_SERCS_SERIAL_OFFSET 0x18 #define DMI_SERCS_SERIAL_LENGTH 3 -#define DMI_SERCS_SERIAL (0x7U << DMI_SERCS_SERIAL_OFFSET) -#define DMI_SERCS_ERROR7_OFFSET 23 +#define DMI_SERCS_SERIAL 0x7000000 +#define DMI_SERCS_ERROR7_OFFSET 0x17 #define DMI_SERCS_ERROR7_LENGTH 1 -#define DMI_SERCS_ERROR7 (0x1U << DMI_SERCS_ERROR7_OFFSET) -#define DMI_SERCS_VALID7_OFFSET 22 +#define DMI_SERCS_ERROR7 0x800000 +#define DMI_SERCS_VALID7_OFFSET 0x16 #define DMI_SERCS_VALID7_LENGTH 1 -#define DMI_SERCS_VALID7 (0x1U << DMI_SERCS_VALID7_OFFSET) -#define DMI_SERCS_FULL7_OFFSET 21 +#define DMI_SERCS_VALID7 0x400000 +#define DMI_SERCS_FULL7_OFFSET 0x15 #define DMI_SERCS_FULL7_LENGTH 1 -#define DMI_SERCS_FULL7 (0x1U << DMI_SERCS_FULL7_OFFSET) -#define DMI_SERCS_ERROR6_OFFSET 20 +#define DMI_SERCS_FULL7 0x200000 +#define DMI_SERCS_ERROR6_OFFSET 0x14 #define DMI_SERCS_ERROR6_LENGTH 1 -#define DMI_SERCS_ERROR6 (0x1U << DMI_SERCS_ERROR6_OFFSET) -#define DMI_SERCS_VALID6_OFFSET 19 +#define DMI_SERCS_ERROR6 0x100000 +#define DMI_SERCS_VALID6_OFFSET 0x13 #define DMI_SERCS_VALID6_LENGTH 1 -#define DMI_SERCS_VALID6 (0x1U << DMI_SERCS_VALID6_OFFSET) -#define DMI_SERCS_FULL6_OFFSET 18 +#define DMI_SERCS_VALID6 0x80000 +#define DMI_SERCS_FULL6_OFFSET 0x12 #define DMI_SERCS_FULL6_LENGTH 1 -#define DMI_SERCS_FULL6 (0x1U << DMI_SERCS_FULL6_OFFSET) -#define DMI_SERCS_ERROR5_OFFSET 17 +#define DMI_SERCS_FULL6 0x40000 +#define DMI_SERCS_ERROR5_OFFSET 0x11 #define DMI_SERCS_ERROR5_LENGTH 1 -#define DMI_SERCS_ERROR5 (0x1U << DMI_SERCS_ERROR5_OFFSET) -#define DMI_SERCS_VALID5_OFFSET 16 +#define DMI_SERCS_ERROR5 0x20000 +#define DMI_SERCS_VALID5_OFFSET 0x10 #define DMI_SERCS_VALID5_LENGTH 1 -#define DMI_SERCS_VALID5 (0x1U << DMI_SERCS_VALID5_OFFSET) -#define DMI_SERCS_FULL5_OFFSET 15 +#define DMI_SERCS_VALID5 0x10000 +#define DMI_SERCS_FULL5_OFFSET 0xf #define DMI_SERCS_FULL5_LENGTH 1 -#define DMI_SERCS_FULL5 (0x1U << DMI_SERCS_FULL5_OFFSET) -#define DMI_SERCS_ERROR4_OFFSET 14 +#define DMI_SERCS_FULL5 0x8000 +#define DMI_SERCS_ERROR4_OFFSET 0xe #define DMI_SERCS_ERROR4_LENGTH 1 -#define DMI_SERCS_ERROR4 (0x1U << DMI_SERCS_ERROR4_OFFSET) -#define DMI_SERCS_VALID4_OFFSET 13 +#define DMI_SERCS_ERROR4 0x4000 +#define DMI_SERCS_VALID4_OFFSET 0xd #define DMI_SERCS_VALID4_LENGTH 1 -#define DMI_SERCS_VALID4 (0x1U << DMI_SERCS_VALID4_OFFSET) -#define DMI_SERCS_FULL4_OFFSET 12 +#define DMI_SERCS_VALID4 0x2000 +#define DMI_SERCS_FULL4_OFFSET 0xc #define DMI_SERCS_FULL4_LENGTH 1 -#define DMI_SERCS_FULL4 (0x1U << DMI_SERCS_FULL4_OFFSET) -#define DMI_SERCS_ERROR3_OFFSET 11 +#define DMI_SERCS_FULL4 0x1000 +#define DMI_SERCS_ERROR3_OFFSET 0xb #define DMI_SERCS_ERROR3_LENGTH 1 -#define DMI_SERCS_ERROR3 (0x1U << DMI_SERCS_ERROR3_OFFSET) -#define DMI_SERCS_VALID3_OFFSET 10 +#define DMI_SERCS_ERROR3 0x800 +#define DMI_SERCS_VALID3_OFFSET 0xa #define DMI_SERCS_VALID3_LENGTH 1 -#define DMI_SERCS_VALID3 (0x1U << DMI_SERCS_VALID3_OFFSET) +#define DMI_SERCS_VALID3 0x400 #define DMI_SERCS_FULL3_OFFSET 9 #define DMI_SERCS_FULL3_LENGTH 1 -#define DMI_SERCS_FULL3 (0x1U << DMI_SERCS_FULL3_OFFSET) +#define DMI_SERCS_FULL3 0x200 #define DMI_SERCS_ERROR2_OFFSET 8 #define DMI_SERCS_ERROR2_LENGTH 1 -#define DMI_SERCS_ERROR2 (0x1U << DMI_SERCS_ERROR2_OFFSET) +#define DMI_SERCS_ERROR2 0x100 #define DMI_SERCS_VALID2_OFFSET 7 #define DMI_SERCS_VALID2_LENGTH 1 -#define DMI_SERCS_VALID2 (0x1U << DMI_SERCS_VALID2_OFFSET) +#define DMI_SERCS_VALID2 0x80 #define DMI_SERCS_FULL2_OFFSET 6 #define DMI_SERCS_FULL2_LENGTH 1 -#define DMI_SERCS_FULL2 (0x1U << DMI_SERCS_FULL2_OFFSET) +#define DMI_SERCS_FULL2 0x40 #define DMI_SERCS_ERROR1_OFFSET 5 #define DMI_SERCS_ERROR1_LENGTH 1 -#define DMI_SERCS_ERROR1 (0x1U << DMI_SERCS_ERROR1_OFFSET) +#define DMI_SERCS_ERROR1 0x20 #define DMI_SERCS_VALID1_OFFSET 4 #define DMI_SERCS_VALID1_LENGTH 1 -#define DMI_SERCS_VALID1 (0x1U << DMI_SERCS_VALID1_OFFSET) +#define DMI_SERCS_VALID1 0x10 #define DMI_SERCS_FULL1_OFFSET 3 #define DMI_SERCS_FULL1_LENGTH 1 -#define DMI_SERCS_FULL1 (0x1U << DMI_SERCS_FULL1_OFFSET) +#define DMI_SERCS_FULL1 8 /* * 1 when the debugger-to-core queue for serial port 0 has * over or underflowed. This bit will remain set until it is reset by @@ -2530,24 +3038,24 @@ */ #define DMI_SERCS_ERROR0_OFFSET 2 #define DMI_SERCS_ERROR0_LENGTH 1 -#define DMI_SERCS_ERROR0 (0x1U << DMI_SERCS_ERROR0_OFFSET) +#define DMI_SERCS_ERROR0 4 /* * 1 when the core-to-debugger queue for serial port 0 is not empty. */ #define DMI_SERCS_VALID0_OFFSET 1 #define DMI_SERCS_VALID0_LENGTH 1 -#define DMI_SERCS_VALID0 (0x1U << DMI_SERCS_VALID0_OFFSET) +#define DMI_SERCS_VALID0 2 /* * 1 when the debugger-to-core queue for serial port 0 is full. */ #define DMI_SERCS_FULL0_OFFSET 0 #define DMI_SERCS_FULL0_LENGTH 1 -#define DMI_SERCS_FULL0 (0x1U << DMI_SERCS_FULL0_OFFSET) +#define DMI_SERCS_FULL0 1 #define DMI_SERTX 0x35 #define DMI_SERTX_DATA_OFFSET 0 -#define DMI_SERTX_DATA_LENGTH 32 -#define DMI_SERTX_DATA (0xffffffffU << DMI_SERTX_DATA_OFFSET) +#define DMI_SERTX_DATA_LENGTH 0x20 +#define DMI_SERTX_DATA 0xffffffffU #define DMI_SERRX 0x36 #define DMI_SERRX_DATA_OFFSET 0 -#define DMI_SERRX_DATA_LENGTH 32 -#define DMI_SERRX_DATA (0xffffffffU << DMI_SERRX_DATA_OFFSET) +#define DMI_SERRX_DATA_LENGTH 0x20 +#define DMI_SERRX_DATA 0xffffffffU diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h index 4445f0bd2e..c2da4e6767 100644 --- a/src/target/riscv/encoding.h +++ b/src/target/riscv/encoding.h @@ -1,10 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2022 RISC-V International */ + /* - * This file is auto-generated by running 'make ../riscv-openocd/src/target/riscv/encoding.h' in - * https://github.com/riscv/riscv-opcodes (6c34f60) + * This file is auto-generated by running 'make' in + * https://github.com/riscv/riscv-opcodes (dcdf8d3) */ -/* See LICENSE for license details. */ - #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H @@ -139,6 +141,7 @@ #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_LCOF) #define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) #define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) @@ -149,6 +152,74 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define MSTATEEN0_CS 0x00000001 +#define MSTATEEN0_FCSR 0x00000002 +#define MSTATEEN0_HCONTEXT 0x0200000000000000 +#define MSTATEEN0_HENVCFG 0x4000000000000000 +#define MSTATEEN_HSTATEEN 0x8000000000000000 + +#define MSTATEEN0H_HCONTEXT 0x02000000 +#define MSTATEEN0H_HENVCFG 0x40000000 +#define MSTATEENH_HSTATEEN 0x80000000 + +#define MHPMEVENT_VUINH 0x0400000000000000 +#define MHPMEVENT_VSINH 0x0800000000000000 +#define MHPMEVENT_UINH 0x1000000000000000 +#define MHPMEVENT_SINH 0x2000000000000000 +#define MHPMEVENT_MINH 0x4000000000000000 +#define MHPMEVENT_OF 0x8000000000000000 + +#define MHPMEVENTH_VUINH 0x04000000 +#define MHPMEVENTH_VSINH 0x08000000 +#define MHPMEVENTH_UINH 0x10000000 +#define MHPMEVENTH_SINH 0x20000000 +#define MHPMEVENTH_MINH 0x40000000 +#define MHPMEVENTH_OF 0x80000000 + +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define HSTATEEN0_CS 0x00000001 +#define HSTATEEN0_FCSR 0x00000002 +#define HSTATEEN0_SCONTEXT 0x0200000000000000 +#define HSTATEEN0_SENVCFG 0x4000000000000000 +#define HSTATEEN_SSTATEEN 0x8000000000000000 + +#define HSTATEEN0H_SCONTEXT 0x02000000 +#define HSTATEEN0H_SENVCFG 0x40000000 +#define HSTATEENH_SSTATEEN 0x80000000 + +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 + +#define SSTATEEN0_CS 0x00000001 +#define SSTATEEN0_FCSR 0x00000002 + +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 + #define PRV_U 0 #define PRV_S 1 #define PRV_M 3 @@ -181,6 +252,7 @@ #define HGATP_MODE_SV32X4 1 #define HGATP_MODE_SV39X4 8 #define HGATP_MODE_SV48X4 9 +#define HGATP_MODE_SV57X4 10 #define PMP_R 0x01 #define PMP_W 0x02 @@ -207,7 +279,7 @@ #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_COP 12 -#define IRQ_HOST 13 +#define IRQ_LCOF 13 /* page table entry (PTE) fields */ #define PTE_V 0x001 /* Valid */ @@ -278,3797 +350,3344 @@ #endif #endif -/* Automatically generated by parse_opcodes. */ + +/* Automatically generated by parse_opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f -#define MATCH_FRFLAGS 0x102073 -#define MASK_FRFLAGS 0xfffff07f -#define MATCH_FSFLAGS 0x101073 -#define MASK_FSFLAGS 0xfff0707f -#define MATCH_FSFLAGSI 0x105073 -#define MASK_FSFLAGSI 0xfff0707f -#define MATCH_FRRM 0x202073 -#define MASK_FRRM 0xfffff07f -#define MATCH_FSRM 0x201073 -#define MASK_FSRM 0xfff0707f -#define MATCH_FSRMI 0x205073 -#define MASK_FSRMI 0xfff0707f -#define MATCH_FSCSR 0x301073 -#define MASK_FSCSR 0xfff0707f -#define MATCH_FRCSR 0x302073 -#define MASK_FRCSR 0xfffff07f -#define MATCH_RDCYCLE 0xc0002073 -#define MASK_RDCYCLE 0xfffff07f -#define MATCH_RDTIME 0xc0102073 -#define MASK_RDTIME 0xfffff07f -#define MATCH_RDINSTRET 0xc0202073 -#define MASK_RDINSTRET 0xfffff07f -#define MATCH_RDCYCLEH 0xc8002073 -#define MASK_RDCYCLEH 0xfffff07f -#define MATCH_RDTIMEH 0xc8102073 -#define MASK_RDTIMEH 0xfffff07f -#define MATCH_RDINSTRETH 0xc8202073 -#define MASK_RDINSTRETH 0xfffff07f -#define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff -#define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FENCE_TSO 0x8330000f -#define MASK_FENCE_TSO 0xfff0707f -#define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f #define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f +#define MASK_ADD 0xfe00707f +#define MATCH_ADD16 0x40000077 +#define MASK_ADD16 0xfe00707f +#define MATCH_ADD32 0x40002077 +#define MASK_ADD32 0xfe00707f +#define MATCH_ADD64 0xc0001077 +#define MASK_ADD64 0xfe00707f +#define MATCH_ADD8 0x48000077 +#define MASK_ADD8 0xfe00707f +#define MATCH_ADD_UW 0x800003b +#define MASK_ADD_UW 0xfe00707f +#define MATCH_ADDD 0x7b +#define MASK_ADDD 0xfe00707f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_ADDID 0x5b +#define MASK_ADDID 0x707f #define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f +#define MASK_ADDIW 0x707f #define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f +#define MASK_ADDW 0xfe00707f +#define MATCH_AES32DSI 0x2a000033 +#define MASK_AES32DSI 0x3e00707f +#define MATCH_AES32DSMI 0x2e000033 +#define MASK_AES32DSMI 0x3e00707f +#define MATCH_AES32ESI 0x22000033 +#define MASK_AES32ESI 0x3e00707f +#define MATCH_AES32ESMI 0x26000033 +#define MASK_AES32ESMI 0x3e00707f +#define MATCH_AES64DS 0x3a000033 +#define MASK_AES64DS 0xfe00707f +#define MATCH_AES64DSM 0x3e000033 +#define MASK_AES64DSM 0xfe00707f +#define MATCH_AES64ES 0x32000033 +#define MASK_AES64ES 0xfe00707f +#define MATCH_AES64ESM 0x36000033 +#define MASK_AES64ESM 0xfe00707f +#define MATCH_AES64IM 0x30001013 +#define MASK_AES64IM 0xfff0707f +#define MATCH_AES64KS1I 0x31001013 +#define MASK_AES64KS1I 0xff00707f +#define MATCH_AES64KS2 0x7e000033 +#define MASK_AES64KS2 0xfe00707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f #define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f #define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f #define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f +#define MASK_AMOMAXU_W 0xf800707f #define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f #define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f #define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff -#define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff -#define MATCH_HLV_B 0x60004073 -#define MASK_HLV_B 0xfff0707f -#define MATCH_HLV_BU 0x60104073 -#define MASK_HLV_BU 0xfff0707f -#define MATCH_HLV_H 0x64004073 -#define MASK_HLV_H 0xfff0707f -#define MATCH_HLV_HU 0x64104073 -#define MASK_HLV_HU 0xfff0707f -#define MATCH_HLVX_HU 0x64304073 -#define MASK_HLVX_HU 0xfff0707f -#define MATCH_HLV_W 0x68004073 -#define MASK_HLV_W 0xfff0707f -#define MATCH_HLVX_WU 0x68304073 -#define MASK_HLVX_WU 0xfff0707f -#define MATCH_HSV_B 0x62004073 -#define MASK_HSV_B 0xfe007fff -#define MATCH_HSV_H 0x66004073 -#define MASK_HSV_H 0xfe007fff -#define MATCH_HSV_W 0x6a004073 -#define MASK_HSV_W 0xfe007fff -#define MATCH_HLV_WU 0x68104073 -#define MASK_HLV_WU 0xfff0707f -#define MATCH_HLV_D 0x6c004073 -#define MASK_HLV_D 0xfff0707f -#define MATCH_HSV_D 0x6e004073 -#define MASK_HSV_D 0xfe007fff -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f #define MATCH_ANDN 0x40007033 -#define MASK_ANDN 0xfe00707f -#define MATCH_ORN 0x40006033 -#define MASK_ORN 0xfe00707f -#define MATCH_XNOR 0x40004033 -#define MASK_XNOR 0xfe00707f -#define MATCH_SLO 0x20001033 -#define MASK_SLO 0xfe00707f -#define MATCH_SRO 0x20005033 -#define MASK_SRO 0xfe00707f -#define MATCH_ROL 0x60001033 -#define MASK_ROL 0xfe00707f -#define MATCH_ROR 0x60005033 -#define MASK_ROR 0xfe00707f +#define MASK_ANDN 0xfe00707f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_AVE 0xe0000077 +#define MASK_AVE 0xfe00707f #define MATCH_BCLR 0x48001033 -#define MASK_BCLR 0xfe00707f -#define MATCH_BSET 0x28001033 -#define MASK_BSET 0xfe00707f -#define MATCH_BINV 0x68001033 -#define MASK_BINV 0xfe00707f -#define MATCH_BEXT 0x48005033 -#define MASK_BEXT 0xfe00707f -#define MATCH_GORC 0x28005033 -#define MASK_GORC 0xfe00707f -#define MATCH_GREV 0x68005033 -#define MASK_GREV 0xfe00707f -#define MATCH_SLOI 0x20001013 -#define MASK_SLOI 0xfc00707f -#define MATCH_SROI 0x20005013 -#define MASK_SROI 0xfc00707f -#define MATCH_RORI 0x60005013 -#define MASK_RORI 0xfc00707f +#define MASK_BCLR 0xfe00707f #define MATCH_BCLRI 0x48001013 -#define MASK_BCLRI 0xfc00707f -#define MATCH_BSETI 0x28001013 -#define MASK_BSETI 0xfc00707f -#define MATCH_BINVI 0x68001013 -#define MASK_BINVI 0xfc00707f -#define MATCH_BEXTI 0x48005013 -#define MASK_BEXTI 0xfc00707f -#define MATCH_GORCI 0x28005013 -#define MASK_GORCI 0xfc00707f -#define MATCH_GREVI 0x68005013 -#define MASK_GREVI 0xfc00707f -#define MATCH_CMIX 0x6001033 -#define MASK_CMIX 0x600707f -#define MATCH_CMOV 0x6005033 -#define MASK_CMOV 0x600707f -#define MATCH_FSL 0x4001033 -#define MASK_FSL 0x600707f -#define MATCH_FSR 0x4005033 -#define MASK_FSR 0x600707f -#define MATCH_FSRI 0x4005013 -#define MASK_FSRI 0x400707f -#define MATCH_CLZ 0x60001013 -#define MASK_CLZ 0xfff0707f -#define MATCH_CTZ 0x60101013 -#define MASK_CTZ 0xfff0707f -#define MATCH_CPOP 0x60201013 -#define MASK_CPOP 0xfff0707f -#define MATCH_SEXT_B 0x60401013 -#define MASK_SEXT_B 0xfff0707f -#define MATCH_SEXT_H 0x60501013 -#define MASK_SEXT_H 0xfff0707f -#define MATCH_CRC32_B 0x61001013 -#define MASK_CRC32_B 0xfff0707f -#define MATCH_CRC32_H 0x61101013 -#define MASK_CRC32_H 0xfff0707f -#define MATCH_CRC32_W 0x61201013 -#define MASK_CRC32_W 0xfff0707f -#define MATCH_CRC32C_B 0x61801013 -#define MASK_CRC32C_B 0xfff0707f -#define MATCH_CRC32C_H 0x61901013 -#define MASK_CRC32C_H 0xfff0707f -#define MATCH_CRC32C_W 0x61a01013 -#define MASK_CRC32C_W 0xfff0707f -#define MATCH_SH1ADD 0x20002033 -#define MASK_SH1ADD 0xfe00707f -#define MATCH_SH2ADD 0x20004033 -#define MASK_SH2ADD 0xfe00707f -#define MATCH_SH3ADD 0x20006033 -#define MASK_SH3ADD 0xfe00707f -#define MATCH_CLMUL 0xa001033 -#define MASK_CLMUL 0xfe00707f -#define MATCH_CLMULR 0xa002033 -#define MASK_CLMULR 0xfe00707f -#define MATCH_CLMULH 0xa003033 -#define MASK_CLMULH 0xfe00707f -#define MATCH_MIN 0xa004033 -#define MASK_MIN 0xfe00707f -#define MATCH_MINU 0xa005033 -#define MASK_MINU 0xfe00707f -#define MATCH_MAX 0xa006033 -#define MASK_MAX 0xfe00707f -#define MATCH_MAXU 0xa007033 -#define MASK_MAXU 0xfe00707f -#define MATCH_SHFL 0x8001033 -#define MASK_SHFL 0xfe00707f -#define MATCH_UNSHFL 0x8005033 -#define MASK_UNSHFL 0xfe00707f +#define MASK_BCLRI 0xfc00707f #define MATCH_BCOMPRESS 0x8006033 -#define MASK_BCOMPRESS 0xfe00707f +#define MASK_BCOMPRESS 0xfe00707f +#define MATCH_BCOMPRESSW 0x800603b +#define MASK_BCOMPRESSW 0xfe00707f #define MATCH_BDECOMPRESS 0x48006033 -#define MASK_BDECOMPRESS 0xfe00707f -#define MATCH_PACK 0x8004033 -#define MASK_PACK 0xfe00707f -#define MATCH_PACKU 0x48004033 -#define MASK_PACKU 0xfe00707f -#define MATCH_PACKH 0x8007033 -#define MASK_PACKH 0xfe00707f +#define MASK_BDECOMPRESS 0xfe00707f +#define MATCH_BDECOMPRESSW 0x4800603b +#define MASK_BDECOMPRESSW 0xfe00707f +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BEXT 0x48005033 +#define MASK_BEXT 0xfe00707f +#define MATCH_BEXTI 0x48005013 +#define MASK_BEXTI 0xfc00707f #define MATCH_BFP 0x48007033 -#define MASK_BFP 0xfe00707f -#define MATCH_SHFLI 0x8001013 -#define MASK_SHFLI 0xfe00707f -#define MATCH_UNSHFLI 0x8005013 -#define MASK_UNSHFLI 0xfe00707f -#define MATCH_XPERM4 0x28002033 -#define MASK_XPERM4 0xfe00707f -#define MATCH_XPERM8 0x28004033 -#define MASK_XPERM8 0xfe00707f -#define MATCH_XPERM16 0x28006033 -#define MASK_XPERM16 0xfe00707f +#define MASK_BFP 0xfe00707f +#define MATCH_BFPW 0x4800703b +#define MASK_BFPW 0xfe00707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_BINV 0x68001033 +#define MASK_BINV 0xfe00707f +#define MATCH_BINVI 0x68001013 +#define MASK_BINVI 0xfc00707f +#define MATCH_BITREV 0xe6000077 +#define MASK_BITREV 0xfe00707f +#define MATCH_BITREVI 0xe8000077 +#define MASK_BITREVI 0xfc00707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f #define MATCH_BMATFLIP 0x60301013 -#define MASK_BMATFLIP 0xfff0707f -#define MATCH_CRC32_D 0x61301013 -#define MASK_CRC32_D 0xfff0707f -#define MATCH_CRC32C_D 0x61b01013 -#define MASK_CRC32C_D 0xfff0707f +#define MASK_BMATFLIP 0xfff0707f #define MATCH_BMATOR 0x8003033 -#define MASK_BMATOR 0xfe00707f +#define MASK_BMATOR 0xfe00707f #define MATCH_BMATXOR 0x48003033 -#define MASK_BMATXOR 0xfe00707f -#define MATCH_SLLI_UW 0x800101b -#define MASK_SLLI_UW 0xfc00707f -#define MATCH_ADD_UW 0x800003b -#define MASK_ADD_UW 0xfe00707f -#define MATCH_SLOW 0x2000103b -#define MASK_SLOW 0xfe00707f -#define MATCH_SROW 0x2000503b -#define MASK_SROW 0xfe00707f -#define MATCH_ROLW 0x6000103b -#define MASK_ROLW 0xfe00707f -#define MATCH_RORW 0x6000503b -#define MASK_RORW 0xfe00707f -#define MATCH_SBCLRW 0x4800103b -#define MASK_SBCLRW 0xfe00707f -#define MATCH_SBSETW 0x2800103b -#define MASK_SBSETW 0xfe00707f -#define MATCH_SBINVW 0x6800103b -#define MASK_SBINVW 0xfe00707f -#define MATCH_SBEXTW 0x4800503b -#define MASK_SBEXTW 0xfe00707f -#define MATCH_GORCW 0x2800503b -#define MASK_GORCW 0xfe00707f -#define MATCH_GREVW 0x6800503b -#define MASK_GREVW 0xfe00707f -#define MATCH_SLOIW 0x2000101b -#define MASK_SLOIW 0xfe00707f -#define MATCH_SROIW 0x2000501b -#define MASK_SROIW 0xfe00707f -#define MATCH_RORIW 0x6000501b -#define MASK_RORIW 0xfe00707f -#define MATCH_SBCLRIW 0x4800101b -#define MASK_SBCLRIW 0xfe00707f -#define MATCH_SBSETIW 0x2800101b -#define MASK_SBSETIW 0xfe00707f -#define MATCH_SBINVIW 0x6800101b -#define MASK_SBINVIW 0xfe00707f -#define MATCH_GORCIW 0x2800501b -#define MASK_GORCIW 0xfe00707f -#define MATCH_GREVIW 0x6800501b -#define MASK_GREVIW 0xfe00707f -#define MATCH_FSLW 0x400103b -#define MASK_FSLW 0x600707f -#define MATCH_FSRW 0x400503b -#define MASK_FSRW 0x600707f -#define MATCH_FSRIW 0x400501b -#define MASK_FSRIW 0x600707f -#define MATCH_CLZW 0x6000101b -#define MASK_CLZW 0xfff0707f -#define MATCH_CTZW 0x6010101b -#define MASK_CTZW 0xfff0707f -#define MATCH_CPOPW 0x6020101b -#define MASK_CPOPW 0xfff0707f -#define MATCH_SH1ADD_UW 0x2000203b -#define MASK_SH1ADD_UW 0xfe00707f -#define MATCH_SH2ADD_UW 0x2000403b -#define MASK_SH2ADD_UW 0xfe00707f -#define MATCH_SH3ADD_UW 0x2000603b -#define MASK_SH3ADD_UW 0xfe00707f -#define MATCH_SHFLW 0x800103b -#define MASK_SHFLW 0xfe00707f -#define MATCH_UNSHFLW 0x800503b -#define MASK_UNSHFLW 0xfe00707f -#define MATCH_BCOMPRESSW 0x800603b -#define MASK_BCOMPRESSW 0xfe00707f -#define MATCH_BDECOMPRESSW 0x4800603b -#define MASK_BDECOMPRESSW 0xfe00707f -#define MATCH_PACKW 0x800403b -#define MASK_PACKW 0xfe00707f -#define MATCH_PACKUW 0x4800403b -#define MASK_PACKUW 0xfe00707f -#define MATCH_BFPW 0x4800703b -#define MASK_BFPW 0xfe00707f -#define MATCH_XPERM32 0x28000033 -#define MASK_XPERM32 0xfe00707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_SINVAL_VMA 0x16000073 -#define MASK_SINVAL_VMA 0xfe007fff -#define MATCH_SFENCE_W_INVAL 0x18000073 -#define MASK_SFENCE_W_INVAL 0xffffffff -#define MATCH_SFENCE_INVAL_IR 0x18100073 -#define MASK_SFENCE_INVAL_IR 0xffffffff -#define MATCH_HINVAL_VVMA 0x36000073 -#define MASK_HINVAL_VVMA 0xfe007fff -#define MATCH_HINVAL_GVMA 0x76000073 -#define MASK_HINVAL_GVMA 0xfe007fff -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f -#define MATCH_SM4ED 0x30000033 -#define MASK_SM4ED 0x3e00707f -#define MATCH_SM4KS 0x34000033 -#define MASK_SM4KS 0x3e00707f -#define MATCH_SM3P0 0x10801013 -#define MASK_SM3P0 0xfff0707f -#define MATCH_SM3P1 0x10901013 -#define MASK_SM3P1 0xfff0707f -#define MATCH_SHA256SUM0 0x10001013 -#define MASK_SHA256SUM0 0xfff0707f -#define MATCH_SHA256SUM1 0x10101013 -#define MASK_SHA256SUM1 0xfff0707f -#define MATCH_SHA256SIG0 0x10201013 -#define MASK_SHA256SIG0 0xfff0707f -#define MATCH_SHA256SIG1 0x10301013 -#define MASK_SHA256SIG1 0xfff0707f -#define MATCH_AES32ESMI 0x26000033 -#define MASK_AES32ESMI 0x3e00707f -#define MATCH_AES32ESI 0x22000033 -#define MASK_AES32ESI 0x3e00707f -#define MATCH_AES32DSMI 0x2e000033 -#define MASK_AES32DSMI 0x3e00707f -#define MATCH_AES32DSI 0x2a000033 -#define MASK_AES32DSI 0x3e00707f -#define MATCH_SHA512SUM0R 0x50000033 -#define MASK_SHA512SUM0R 0xfe00707f -#define MATCH_SHA512SUM1R 0x52000033 -#define MASK_SHA512SUM1R 0xfe00707f -#define MATCH_SHA512SIG0L 0x54000033 -#define MASK_SHA512SIG0L 0xfe00707f -#define MATCH_SHA512SIG0H 0x5c000033 -#define MASK_SHA512SIG0H 0xfe00707f -#define MATCH_SHA512SIG1L 0x56000033 -#define MASK_SHA512SIG1L 0xfe00707f -#define MATCH_SHA512SIG1H 0x5e000033 -#define MASK_SHA512SIG1H 0xfe00707f -#define MATCH_AES64KS1I 0x31001013 -#define MASK_AES64KS1I 0xff00707f -#define MATCH_AES64IM 0x30001013 -#define MASK_AES64IM 0xfff0707f -#define MATCH_AES64KS2 0x7e000033 -#define MASK_AES64KS2 0xfe00707f -#define MATCH_AES64ESM 0x36000033 -#define MASK_AES64ESM 0xfe00707f -#define MATCH_AES64ES 0x32000033 -#define MASK_AES64ES 0xfe00707f -#define MATCH_AES64DSM 0x3e000033 -#define MASK_AES64DSM 0xfe00707f -#define MATCH_AES64DS 0x3a000033 -#define MASK_AES64DS 0xfe00707f -#define MATCH_SHA512SUM0 0x10401013 -#define MASK_SHA512SUM0 0xfff0707f -#define MATCH_SHA512SUM1 0x10501013 -#define MASK_SHA512SUM1 0xfff0707f -#define MATCH_SHA512SIG0 0x10601013 -#define MASK_SHA512SIG0 0xfff0707f -#define MATCH_SHA512SIG1 0x10701013 -#define MASK_SHA512SIG1 0xfff0707f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff +#define MASK_BMATXOR 0xfe00707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BPICK 0x3077 +#define MASK_BPICK 0x600707f +#define MATCH_BSET 0x28001033 +#define MASK_BSET 0xfe00707f +#define MATCH_BSETI 0x28001013 +#define MASK_BSETI 0xfc00707f +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 #define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff +#define MASK_C_ADDI16SP 0xef83 #define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff #define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 +#define MASK_C_FLD 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 #define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 #define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 +#define MASK_C_FSD 0xe003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 #define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 +#define MASK_C_FSW 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 #define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 +#define MASK_C_JAL 0xe003 +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 #define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 +#define MASK_C_LI 0xe003 +#define MATCH_C_LQ 0x2000 +#define MASK_C_LQ 0xe003 +#define MATCH_C_LQSP 0x2002 +#define MASK_C_LQSP 0xe003 #define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 +#define MASK_C_LUI 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 #define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 +#define MASK_C_LWSP 0xe003 #define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_C_SRLI_RV32 0x8001 -#define MASK_C_SRLI_RV32 0xfc03 -#define MATCH_C_SRAI_RV32 0x8401 -#define MASK_C_SRAI_RV32 0xfc03 -#define MATCH_C_SLLI_RV32 0x2 -#define MASK_C_SLLI_RV32 0xf003 -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 +#define MASK_C_MV 0xf003 +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xef83 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 #define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 +#define MASK_C_SD 0xe003 #define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define MATCH_VSETIVLI 0xc0007057 -#define MASK_VSETIVLI 0xc000707f -#define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f -#define MATCH_VSETVL 0x80007057 -#define MASK_VSETVL 0xfe00707f -#define MATCH_VLM_V 0x2b00007 -#define MASK_VLM_V 0xfff0707f -#define MATCH_VSM_V 0x2b00027 -#define MASK_VSM_V 0xfff0707f -#define MATCH_VLE8_V 0x7 -#define MASK_VLE8_V 0x1df0707f -#define MATCH_VLE16_V 0x5007 -#define MASK_VLE16_V 0x1df0707f -#define MATCH_VLE32_V 0x6007 -#define MASK_VLE32_V 0x1df0707f -#define MATCH_VLE64_V 0x7007 -#define MASK_VLE64_V 0x1df0707f -#define MATCH_VLE128_V 0x10000007 -#define MASK_VLE128_V 0x1df0707f -#define MATCH_VLE256_V 0x10005007 -#define MASK_VLE256_V 0x1df0707f -#define MATCH_VLE512_V 0x10006007 -#define MASK_VLE512_V 0x1df0707f -#define MATCH_VLE1024_V 0x10007007 -#define MASK_VLE1024_V 0x1df0707f -#define MATCH_VSE8_V 0x27 -#define MASK_VSE8_V 0x1df0707f -#define MATCH_VSE16_V 0x5027 -#define MASK_VSE16_V 0x1df0707f -#define MATCH_VSE32_V 0x6027 -#define MASK_VSE32_V 0x1df0707f -#define MATCH_VSE64_V 0x7027 -#define MASK_VSE64_V 0x1df0707f -#define MATCH_VSE128_V 0x10000027 -#define MASK_VSE128_V 0x1df0707f -#define MATCH_VSE256_V 0x10005027 -#define MASK_VSE256_V 0x1df0707f -#define MATCH_VSE512_V 0x10006027 -#define MASK_VSE512_V 0x1df0707f -#define MATCH_VSE1024_V 0x10007027 -#define MASK_VSE1024_V 0x1df0707f -#define MATCH_VLUXEI8_V 0x4000007 -#define MASK_VLUXEI8_V 0x1c00707f -#define MATCH_VLUXEI16_V 0x4005007 -#define MASK_VLUXEI16_V 0x1c00707f -#define MATCH_VLUXEI32_V 0x4006007 -#define MASK_VLUXEI32_V 0x1c00707f -#define MATCH_VLUXEI64_V 0x4007007 -#define MASK_VLUXEI64_V 0x1c00707f -#define MATCH_VLUXEI128_V 0x14000007 -#define MASK_VLUXEI128_V 0x1c00707f -#define MATCH_VLUXEI256_V 0x14005007 -#define MASK_VLUXEI256_V 0x1c00707f -#define MATCH_VLUXEI512_V 0x14006007 -#define MASK_VLUXEI512_V 0x1c00707f -#define MATCH_VLUXEI1024_V 0x14007007 -#define MASK_VLUXEI1024_V 0x1c00707f -#define MATCH_VSUXEI8_V 0x4000027 -#define MASK_VSUXEI8_V 0x1c00707f -#define MATCH_VSUXEI16_V 0x4005027 -#define MASK_VSUXEI16_V 0x1c00707f -#define MATCH_VSUXEI32_V 0x4006027 -#define MASK_VSUXEI32_V 0x1c00707f -#define MATCH_VSUXEI64_V 0x4007027 -#define MASK_VSUXEI64_V 0x1c00707f -#define MATCH_VSUXEI128_V 0x14000027 -#define MASK_VSUXEI128_V 0x1c00707f -#define MATCH_VSUXEI256_V 0x14005027 -#define MASK_VSUXEI256_V 0x1c00707f -#define MATCH_VSUXEI512_V 0x14006027 -#define MASK_VSUXEI512_V 0x1c00707f -#define MATCH_VSUXEI1024_V 0x14007027 -#define MASK_VSUXEI1024_V 0x1c00707f -#define MATCH_VLSE8_V 0x8000007 -#define MASK_VLSE8_V 0x1c00707f -#define MATCH_VLSE16_V 0x8005007 -#define MASK_VLSE16_V 0x1c00707f -#define MATCH_VLSE32_V 0x8006007 -#define MASK_VLSE32_V 0x1c00707f -#define MATCH_VLSE64_V 0x8007007 -#define MASK_VLSE64_V 0x1c00707f -#define MATCH_VLSE128_V 0x18000007 -#define MASK_VLSE128_V 0x1c00707f -#define MATCH_VLSE256_V 0x18005007 -#define MASK_VLSE256_V 0x1c00707f -#define MATCH_VLSE512_V 0x18006007 -#define MASK_VLSE512_V 0x1c00707f -#define MATCH_VLSE1024_V 0x18007007 -#define MASK_VLSE1024_V 0x1c00707f -#define MATCH_VSSE8_V 0x8000027 -#define MASK_VSSE8_V 0x1c00707f -#define MATCH_VSSE16_V 0x8005027 -#define MASK_VSSE16_V 0x1c00707f -#define MATCH_VSSE32_V 0x8006027 -#define MASK_VSSE32_V 0x1c00707f -#define MATCH_VSSE64_V 0x8007027 -#define MASK_VSSE64_V 0x1c00707f -#define MATCH_VSSE128_V 0x18000027 -#define MASK_VSSE128_V 0x1c00707f -#define MATCH_VSSE256_V 0x18005027 -#define MASK_VSSE256_V 0x1c00707f -#define MATCH_VSSE512_V 0x18006027 -#define MASK_VSSE512_V 0x1c00707f -#define MATCH_VSSE1024_V 0x18007027 -#define MASK_VSSE1024_V 0x1c00707f -#define MATCH_VLOXEI8_V 0xc000007 -#define MASK_VLOXEI8_V 0x1c00707f -#define MATCH_VLOXEI16_V 0xc005007 -#define MASK_VLOXEI16_V 0x1c00707f -#define MATCH_VLOXEI32_V 0xc006007 -#define MASK_VLOXEI32_V 0x1c00707f -#define MATCH_VLOXEI64_V 0xc007007 -#define MASK_VLOXEI64_V 0x1c00707f -#define MATCH_VLOXEI128_V 0x1c000007 -#define MASK_VLOXEI128_V 0x1c00707f -#define MATCH_VLOXEI256_V 0x1c005007 -#define MASK_VLOXEI256_V 0x1c00707f -#define MATCH_VLOXEI512_V 0x1c006007 -#define MASK_VLOXEI512_V 0x1c00707f -#define MATCH_VLOXEI1024_V 0x1c007007 -#define MASK_VLOXEI1024_V 0x1c00707f -#define MATCH_VSOXEI8_V 0xc000027 -#define MASK_VSOXEI8_V 0x1c00707f -#define MATCH_VSOXEI16_V 0xc005027 -#define MASK_VSOXEI16_V 0x1c00707f -#define MATCH_VSOXEI32_V 0xc006027 -#define MASK_VSOXEI32_V 0x1c00707f -#define MATCH_VSOXEI64_V 0xc007027 -#define MASK_VSOXEI64_V 0x1c00707f -#define MATCH_VSOXEI128_V 0x1c000027 -#define MASK_VSOXEI128_V 0x1c00707f -#define MATCH_VSOXEI256_V 0x1c005027 -#define MASK_VSOXEI256_V 0x1c00707f -#define MATCH_VSOXEI512_V 0x1c006027 -#define MASK_VSOXEI512_V 0x1c00707f -#define MATCH_VSOXEI1024_V 0x1c007027 -#define MASK_VSOXEI1024_V 0x1c00707f -#define MATCH_VLE8FF_V 0x1000007 -#define MASK_VLE8FF_V 0x1df0707f -#define MATCH_VLE16FF_V 0x1005007 -#define MASK_VLE16FF_V 0x1df0707f -#define MATCH_VLE32FF_V 0x1006007 -#define MASK_VLE32FF_V 0x1df0707f -#define MATCH_VLE64FF_V 0x1007007 -#define MASK_VLE64FF_V 0x1df0707f -#define MATCH_VLE128FF_V 0x11000007 -#define MASK_VLE128FF_V 0x1df0707f -#define MATCH_VLE256FF_V 0x11005007 -#define MASK_VLE256FF_V 0x1df0707f -#define MATCH_VLE512FF_V 0x11006007 -#define MASK_VLE512FF_V 0x1df0707f -#define MATCH_VLE1024FF_V 0x11007007 -#define MASK_VLE1024FF_V 0x1df0707f -#define MATCH_VL1RE8_V 0x2800007 -#define MASK_VL1RE8_V 0xfff0707f -#define MATCH_VL1RE16_V 0x2805007 -#define MASK_VL1RE16_V 0xfff0707f -#define MATCH_VL1RE32_V 0x2806007 -#define MASK_VL1RE32_V 0xfff0707f -#define MATCH_VL1RE64_V 0x2807007 -#define MASK_VL1RE64_V 0xfff0707f -#define MATCH_VL2RE8_V 0x22800007 -#define MASK_VL2RE8_V 0xfff0707f -#define MATCH_VL2RE16_V 0x22805007 -#define MASK_VL2RE16_V 0xfff0707f -#define MATCH_VL2RE32_V 0x22806007 -#define MASK_VL2RE32_V 0xfff0707f -#define MATCH_VL2RE64_V 0x22807007 -#define MASK_VL2RE64_V 0xfff0707f -#define MATCH_VL4RE8_V 0x62800007 -#define MASK_VL4RE8_V 0xfff0707f -#define MATCH_VL4RE16_V 0x62805007 -#define MASK_VL4RE16_V 0xfff0707f -#define MATCH_VL4RE32_V 0x62806007 -#define MASK_VL4RE32_V 0xfff0707f -#define MATCH_VL4RE64_V 0x62807007 -#define MASK_VL4RE64_V 0xfff0707f -#define MATCH_VL8RE8_V 0xe2800007 -#define MASK_VL8RE8_V 0xfff0707f -#define MATCH_VL8RE16_V 0xe2805007 -#define MASK_VL8RE16_V 0xfff0707f -#define MATCH_VL8RE32_V 0xe2806007 -#define MASK_VL8RE32_V 0xfff0707f -#define MATCH_VL8RE64_V 0xe2807007 -#define MASK_VL8RE64_V 0xfff0707f -#define MATCH_VS1R_V 0x2800027 -#define MASK_VS1R_V 0xfff0707f -#define MATCH_VS2R_V 0x22800027 -#define MASK_VS2R_V 0xfff0707f -#define MATCH_VS4R_V 0x62800027 -#define MASK_VS4R_V 0xfff0707f -#define MATCH_VS8R_V 0xe2800027 -#define MASK_VS8R_V 0xfff0707f -#define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f -#define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f -#define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f -#define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f -#define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f -#define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f -#define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f -#define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f -#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f -#define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f -#define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f -#define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f -#define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f -#define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f -#define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f -#define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f -#define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f -#define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f -#define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f -#define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f -#define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f -#define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f -#define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f -#define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f -#define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f -#define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f -#define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f -#define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f -#define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f -#define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f -#define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f -#define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f -#define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f -#define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f -#define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f -#define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f -#define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f -#define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f -#define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f -#define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f -#define MATCH_VFREDUSUM_VS 0x4001057 -#define MASK_VFREDUSUM_VS 0xfc00707f -#define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f -#define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f -#define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f -#define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f -#define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f -#define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f -#define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f -#define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f -#define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f -#define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f -#define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f -#define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f -#define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f -#define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f -#define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f -#define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f -#define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f -#define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f -#define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f -#define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f -#define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f -#define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f -#define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f -#define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f -#define MATCH_VFCVT_XU_F_V 0x48001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_X_F_V 0x48009057 -#define MASK_VFCVT_X_F_V 0xfc0ff07f -#define MATCH_VFCVT_F_XU_V 0x48011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFCVT_F_X_V 0x48019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_XU_F_V 0x48041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_X_F_V 0x48049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_F_XU_V 0x48051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFWCVT_F_X_V 0x48059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f -#define MATCH_VFWCVT_F_F_V 0x48061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFNCVT_XU_F_W 0x48081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_X_F_W 0x48089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_F_XU_W 0x48091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f -#define MATCH_VFNCVT_F_X_W 0x48099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f -#define MATCH_VFNCVT_F_F_W 0x480a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f -#define MATCH_VFSQRT_V 0x4c001057 -#define MASK_VFSQRT_V 0xfc0ff07f -#define MATCH_VFRSQRT7_V 0x4c021057 -#define MASK_VFRSQRT7_V 0xfc0ff07f -#define MATCH_VFREC7_V 0x4c029057 -#define MASK_VFREC7_V 0xfc0ff07f -#define MATCH_VFCLASS_V 0x4c081057 -#define MASK_VFCLASS_V 0xfc0ff07f -#define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f -#define MATCH_VFWREDUSUM_VS 0xc4001057 -#define MASK_VFWREDUSUM_VS 0xfc00707f -#define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f -#define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f -#define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f -#define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f -#define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f -#define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f -#define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f -#define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f -#define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f -#define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f -#define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f -#define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f -#define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f -#define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f -#define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f -#define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f -#define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f -#define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f -#define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f -#define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f -#define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f -#define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f -#define MATCH_VADC_VXM 0x40004057 -#define MASK_VADC_VXM 0xfe00707f -#define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfe00707f -#define MATCH_VMADC_VX 0x46004057 -#define MASK_VMADC_VX 0xfe00707f -#define MATCH_VSBC_VXM 0x48004057 -#define MASK_VSBC_VXM 0xfe00707f -#define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfe00707f -#define MATCH_VMSBC_VX 0x4e004057 -#define MASK_VMSBC_VX 0xfe00707f -#define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f -#define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f -#define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f -#define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f -#define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f -#define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f -#define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f -#define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f -#define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f -#define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f -#define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f -#define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f -#define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f -#define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f -#define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f -#define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f -#define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f -#define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f -#define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f -#define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f -#define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f -#define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f -#define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f -#define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f -#define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f -#define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f -#define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f -#define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f -#define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f -#define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f -#define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f -#define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f -#define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f -#define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f -#define MATCH_VRGATHEREI16_VV 0x38000057 -#define MASK_VRGATHEREI16_VV 0xfc00707f -#define MATCH_VADC_VVM 0x40000057 -#define MASK_VADC_VVM 0xfe00707f -#define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfe00707f -#define MATCH_VMADC_VV 0x46000057 -#define MASK_VMADC_VV 0xfe00707f -#define MATCH_VSBC_VVM 0x48000057 -#define MASK_VSBC_VVM 0xfe00707f -#define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfe00707f -#define MATCH_VMSBC_VV 0x4e000057 -#define MASK_VMSBC_VV 0xfe00707f -#define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f -#define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f -#define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f -#define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f -#define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f -#define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f -#define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f -#define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f -#define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f -#define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f -#define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f -#define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f -#define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f -#define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f -#define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f -#define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f -#define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f -#define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f -#define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f -#define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f -#define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f -#define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f -#define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f -#define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f -#define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f -#define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f -#define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f -#define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f -#define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f -#define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f -#define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f -#define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f -#define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f -#define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfe00707f -#define MATCH_VMADC_VI 0x46003057 -#define MASK_VMADC_VI 0xfe00707f -#define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f -#define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f -#define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f -#define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f -#define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f -#define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f -#define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f -#define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f -#define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f -#define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f -#define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f -#define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f -#define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f -#define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f -#define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f -#define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f -#define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f -#define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f -#define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f -#define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f -#define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f -#define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f -#define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f -#define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f -#define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f -#define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f -#define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f -#define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f -#define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f -#define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f -#define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f -#define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f -#define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f -#define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f -#define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f -#define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f -#define MATCH_VZEXT_VF8 0x48012057 -#define MASK_VZEXT_VF8 0xfc0ff07f -#define MATCH_VSEXT_VF8 0x4801a057 -#define MASK_VSEXT_VF8 0xfc0ff07f -#define MATCH_VZEXT_VF4 0x48022057 -#define MASK_VZEXT_VF4 0xfc0ff07f -#define MATCH_VSEXT_VF4 0x4802a057 -#define MASK_VSEXT_VF4 0xfc0ff07f -#define MATCH_VZEXT_VF2 0x48032057 -#define MASK_VZEXT_VF2 0xfc0ff07f -#define MATCH_VSEXT_VF2 0x4803a057 -#define MASK_VSEXT_VF2 0xfc0ff07f -#define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f -#define MATCH_VMANDNOT_MM 0x60002057 -#define MASK_VMANDNOT_MM 0xfc00707f -#define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f -#define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f -#define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f -#define MATCH_VMORNOT_MM 0x70002057 -#define MASK_VMORNOT_MM 0xfc00707f -#define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f -#define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f -#define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f -#define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f -#define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f -#define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f -#define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f -#define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f -#define MATCH_VCPOP_M 0x40082057 -#define MASK_VCPOP_M 0xfc0ff07f -#define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f -#define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f -#define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f -#define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f -#define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f -#define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f -#define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f -#define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f -#define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f -#define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f -#define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f -#define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f -#define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f -#define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f -#define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f -#define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f -#define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f -#define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f -#define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f -#define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f -#define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f -#define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f -#define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f -#define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f -#define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f -#define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f -#define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f -#define MATCH_VAADDU_VX 0x20006057 -#define MASK_VAADDU_VX 0xfc00707f -#define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f -#define MATCH_VASUBU_VX 0x28006057 -#define MASK_VASUBU_VX 0xfc00707f -#define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f -#define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f -#define MATCH_VSLIDE1UP_VX 0x38006057 -#define MASK_VSLIDE1UP_VX 0xfc00707f -#define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f -#define MATCH_VDIVU_VX 0x80006057 -#define MASK_VDIVU_VX 0xfc00707f -#define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f -#define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f -#define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f -#define MATCH_VMULHU_VX 0x90006057 -#define MASK_VMULHU_VX 0xfc00707f -#define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f -#define MATCH_VMULHSU_VX 0x98006057 -#define MASK_VMULHSU_VX 0xfc00707f -#define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f -#define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f -#define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f -#define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f -#define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f -#define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f -#define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f -#define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f -#define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f -#define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f -#define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f -#define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f -#define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f -#define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f -#define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f -#define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f -#define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f -#define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f -#define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f -#define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f -#define MATCH_VAMOSWAPEI8_V 0x800002f -#define MASK_VAMOSWAPEI8_V 0xf800707f -#define MATCH_VAMOADDEI8_V 0x2f -#define MASK_VAMOADDEI8_V 0xf800707f -#define MATCH_VAMOXOREI8_V 0x2000002f -#define MASK_VAMOXOREI8_V 0xf800707f -#define MATCH_VAMOANDEI8_V 0x6000002f -#define MASK_VAMOANDEI8_V 0xf800707f -#define MATCH_VAMOOREI8_V 0x4000002f -#define MASK_VAMOOREI8_V 0xf800707f -#define MATCH_VAMOMINEI8_V 0x8000002f -#define MASK_VAMOMINEI8_V 0xf800707f -#define MATCH_VAMOMAXEI8_V 0xa000002f -#define MASK_VAMOMAXEI8_V 0xf800707f -#define MATCH_VAMOMINUEI8_V 0xc000002f -#define MASK_VAMOMINUEI8_V 0xf800707f -#define MATCH_VAMOMAXUEI8_V 0xe000002f -#define MASK_VAMOMAXUEI8_V 0xf800707f -#define MATCH_VAMOSWAPEI16_V 0x800502f -#define MASK_VAMOSWAPEI16_V 0xf800707f -#define MATCH_VAMOADDEI16_V 0x502f -#define MASK_VAMOADDEI16_V 0xf800707f -#define MATCH_VAMOXOREI16_V 0x2000502f -#define MASK_VAMOXOREI16_V 0xf800707f -#define MATCH_VAMOANDEI16_V 0x6000502f -#define MASK_VAMOANDEI16_V 0xf800707f -#define MATCH_VAMOOREI16_V 0x4000502f -#define MASK_VAMOOREI16_V 0xf800707f -#define MATCH_VAMOMINEI16_V 0x8000502f -#define MASK_VAMOMINEI16_V 0xf800707f -#define MATCH_VAMOMAXEI16_V 0xa000502f -#define MASK_VAMOMAXEI16_V 0xf800707f -#define MATCH_VAMOMINUEI16_V 0xc000502f -#define MASK_VAMOMINUEI16_V 0xf800707f -#define MATCH_VAMOMAXUEI16_V 0xe000502f -#define MASK_VAMOMAXUEI16_V 0xf800707f -#define MATCH_VAMOSWAPEI32_V 0x800602f -#define MASK_VAMOSWAPEI32_V 0xf800707f -#define MATCH_VAMOADDEI32_V 0x602f -#define MASK_VAMOADDEI32_V 0xf800707f -#define MATCH_VAMOXOREI32_V 0x2000602f -#define MASK_VAMOXOREI32_V 0xf800707f -#define MATCH_VAMOANDEI32_V 0x6000602f -#define MASK_VAMOANDEI32_V 0xf800707f -#define MATCH_VAMOOREI32_V 0x4000602f -#define MASK_VAMOOREI32_V 0xf800707f -#define MATCH_VAMOMINEI32_V 0x8000602f -#define MASK_VAMOMINEI32_V 0xf800707f -#define MATCH_VAMOMAXEI32_V 0xa000602f -#define MASK_VAMOMAXEI32_V 0xf800707f -#define MATCH_VAMOMINUEI32_V 0xc000602f -#define MASK_VAMOMINUEI32_V 0xf800707f -#define MATCH_VAMOMAXUEI32_V 0xe000602f -#define MASK_VAMOMAXUEI32_V 0xf800707f -#define MATCH_VAMOSWAPEI64_V 0x800702f -#define MASK_VAMOSWAPEI64_V 0xf800707f -#define MATCH_VAMOADDEI64_V 0x702f -#define MASK_VAMOADDEI64_V 0xf800707f -#define MATCH_VAMOXOREI64_V 0x2000702f -#define MASK_VAMOXOREI64_V 0xf800707f -#define MATCH_VAMOANDEI64_V 0x6000702f -#define MASK_VAMOANDEI64_V 0xf800707f -#define MATCH_VAMOOREI64_V 0x4000702f -#define MASK_VAMOOREI64_V 0xf800707f -#define MATCH_VAMOMINEI64_V 0x8000702f -#define MASK_VAMOMINEI64_V 0xf800707f -#define MATCH_VAMOMAXEI64_V 0xa000702f -#define MASK_VAMOMAXEI64_V 0xf800707f -#define MATCH_VAMOMINUEI64_V 0xc000702f -#define MASK_VAMOMINUEI64_V 0xf800707f -#define MATCH_VAMOMAXUEI64_V 0xe000702f -#define MASK_VAMOMAXUEI64_V 0xf800707f -#define MATCH_ADD8 0x48000077 -#define MASK_ADD8 0xfe00707f -#define MATCH_ADD16 0x40000077 -#define MASK_ADD16 0xfe00707f -#define MATCH_ADD64 0xc0001077 -#define MASK_ADD64 0xfe00707f -#define MATCH_AVE 0xe0000077 -#define MASK_AVE 0xfe00707f -#define MATCH_BITREV 0xe6000077 -#define MASK_BITREV 0xfe00707f -#define MATCH_BITREVI 0xe8000077 -#define MASK_BITREVI 0xfc00707f -#define MATCH_BPICK 0x3077 -#define MASK_BPICK 0x600707f -#define MATCH_CLRS8 0xae000077 -#define MASK_CLRS8 0xfff0707f -#define MATCH_CLRS16 0xae800077 -#define MASK_CLRS16 0xfff0707f -#define MATCH_CLRS32 0xaf800077 -#define MASK_CLRS32 0xfff0707f -#define MATCH_CLO8 0xae300077 -#define MASK_CLO8 0xfff0707f -#define MATCH_CLO16 0xaeb00077 -#define MASK_CLO16 0xfff0707f -#define MATCH_CLO32 0xafb00077 -#define MASK_CLO32 0xfff0707f -#define MATCH_CLZ8 0xae100077 -#define MASK_CLZ8 0xfff0707f -#define MATCH_CLZ16 0xae900077 -#define MASK_CLZ16 0xfff0707f -#define MATCH_CLZ32 0xaf900077 -#define MASK_CLZ32 0xfff0707f -#define MATCH_CMPEQ8 0x4e000077 -#define MASK_CMPEQ8 0xfe00707f -#define MATCH_CMPEQ16 0x4c000077 -#define MASK_CMPEQ16 0xfe00707f -#define MATCH_CRAS16 0x44000077 -#define MASK_CRAS16 0xfe00707f -#define MATCH_CRSA16 0x46000077 -#define MASK_CRSA16 0xfe00707f -#define MATCH_INSB 0xac000077 -#define MASK_INSB 0xff80707f -#define MATCH_KABS8 0xad000077 -#define MASK_KABS8 0xfff0707f -#define MATCH_KABS16 0xad100077 -#define MASK_KABS16 0xfff0707f -#define MATCH_KABSW 0xad400077 -#define MASK_KABSW 0xfff0707f -#define MATCH_KADD8 0x18000077 -#define MASK_KADD8 0xfe00707f -#define MATCH_KADD16 0x10000077 -#define MASK_KADD16 0xfe00707f -#define MATCH_KADD64 0x90001077 -#define MASK_KADD64 0xfe00707f -#define MATCH_KADDH 0x4001077 -#define MASK_KADDH 0xfe00707f -#define MATCH_KADDW 0x1077 -#define MASK_KADDW 0xfe00707f -#define MATCH_KCRAS16 0x14000077 -#define MASK_KCRAS16 0xfe00707f -#define MATCH_KCRSA16 0x16000077 -#define MASK_KCRSA16 0xfe00707f -#define MATCH_KDMBB 0xa001077 -#define MASK_KDMBB 0xfe00707f -#define MATCH_KDMBT 0x1a001077 -#define MASK_KDMBT 0xfe00707f -#define MATCH_KDMTT 0x2a001077 -#define MASK_KDMTT 0xfe00707f -#define MATCH_KDMABB 0xd2001077 -#define MASK_KDMABB 0xfe00707f -#define MATCH_KDMABT 0xe2001077 -#define MASK_KDMABT 0xfe00707f -#define MATCH_KDMATT 0xf2001077 -#define MASK_KDMATT 0xfe00707f -#define MATCH_KHM8 0x8e000077 -#define MASK_KHM8 0xfe00707f -#define MATCH_KHMX8 0x9e000077 -#define MASK_KHMX8 0xfe00707f -#define MATCH_KHM16 0x86000077 -#define MASK_KHM16 0xfe00707f -#define MATCH_KHMX16 0x96000077 -#define MASK_KHMX16 0xfe00707f -#define MATCH_KHMBB 0xc001077 -#define MASK_KHMBB 0xfe00707f -#define MATCH_KHMBT 0x1c001077 -#define MASK_KHMBT 0xfe00707f -#define MATCH_KHMTT 0x2c001077 -#define MASK_KHMTT 0xfe00707f -#define MATCH_KMABB 0x5a001077 -#define MASK_KMABB 0xfe00707f -#define MATCH_KMABT 0x6a001077 -#define MASK_KMABT 0xfe00707f -#define MATCH_KMATT 0x7a001077 -#define MASK_KMATT 0xfe00707f -#define MATCH_KMADA 0x48001077 -#define MASK_KMADA 0xfe00707f -#define MATCH_KMAXDA 0x4a001077 -#define MASK_KMAXDA 0xfe00707f -#define MATCH_KMADS 0x5c001077 -#define MASK_KMADS 0xfe00707f -#define MATCH_KMADRS 0x6c001077 -#define MASK_KMADRS 0xfe00707f -#define MATCH_KMAXDS 0x7c001077 -#define MASK_KMAXDS 0xfe00707f -#define MATCH_KMAR64 0x94001077 -#define MASK_KMAR64 0xfe00707f -#define MATCH_KMDA 0x38001077 -#define MASK_KMDA 0xfe00707f -#define MATCH_KMXDA 0x3a001077 -#define MASK_KMXDA 0xfe00707f -#define MATCH_KMMAC 0x60001077 -#define MASK_KMMAC 0xfe00707f -#define MATCH_KMMAC_U 0x70001077 -#define MASK_KMMAC_U 0xfe00707f -#define MATCH_KMMAWB 0x46001077 -#define MASK_KMMAWB 0xfe00707f -#define MATCH_KMMAWB_U 0x56001077 -#define MASK_KMMAWB_U 0xfe00707f -#define MATCH_KMMAWB2 0xce001077 -#define MASK_KMMAWB2 0xfe00707f -#define MATCH_KMMAWB2_U 0xde001077 -#define MASK_KMMAWB2_U 0xfe00707f -#define MATCH_KMMAWT 0x66001077 -#define MASK_KMMAWT 0xfe00707f -#define MATCH_KMMAWT_U 0x76001077 -#define MASK_KMMAWT_U 0xfe00707f -#define MATCH_KMMAWT2 0xee001077 -#define MASK_KMMAWT2 0xfe00707f -#define MATCH_KMMAWT2_U 0xfe001077 -#define MASK_KMMAWT2_U 0xfe00707f -#define MATCH_KMMSB 0x42001077 -#define MASK_KMMSB 0xfe00707f -#define MATCH_KMMSB_U 0x52001077 -#define MASK_KMMSB_U 0xfe00707f -#define MATCH_KMMWB2 0x8e001077 -#define MASK_KMMWB2 0xfe00707f -#define MATCH_KMMWB2_U 0x9e001077 -#define MASK_KMMWB2_U 0xfe00707f -#define MATCH_KMMWT2 0xae001077 -#define MASK_KMMWT2 0xfe00707f -#define MATCH_KMMWT2_U 0xbe001077 -#define MASK_KMMWT2_U 0xfe00707f -#define MATCH_KMSDA 0x4c001077 -#define MASK_KMSDA 0xfe00707f -#define MATCH_KMSXDA 0x4e001077 -#define MASK_KMSXDA 0xfe00707f -#define MATCH_KMSR64 0x96001077 -#define MASK_KMSR64 0xfe00707f -#define MATCH_KSLLW 0x26001077 -#define MASK_KSLLW 0xfe00707f -#define MATCH_KSLLIW 0x36001077 -#define MASK_KSLLIW 0xfe00707f -#define MATCH_KSLL8 0x6c000077 -#define MASK_KSLL8 0xfe00707f -#define MATCH_KSLLI8 0x7c800077 -#define MASK_KSLLI8 0xff80707f -#define MATCH_KSLL16 0x64000077 -#define MASK_KSLL16 0xfe00707f -#define MATCH_KSLLI16 0x75000077 -#define MASK_KSLLI16 0xff00707f -#define MATCH_KSLRA8 0x5e000077 -#define MASK_KSLRA8 0xfe00707f -#define MATCH_KSLRA8_U 0x6e000077 -#define MASK_KSLRA8_U 0xfe00707f -#define MATCH_KSLRA16 0x56000077 -#define MASK_KSLRA16 0xfe00707f -#define MATCH_KSLRA16_U 0x66000077 -#define MASK_KSLRA16_U 0xfe00707f -#define MATCH_KSLRAW 0x6e001077 -#define MASK_KSLRAW 0xfe00707f -#define MATCH_KSLRAW_U 0x7e001077 -#define MASK_KSLRAW_U 0xfe00707f -#define MATCH_KSTAS16 0xc4002077 -#define MASK_KSTAS16 0xfe00707f -#define MATCH_KSTSA16 0xc6002077 -#define MASK_KSTSA16 0xfe00707f -#define MATCH_KSUB8 0x1a000077 -#define MASK_KSUB8 0xfe00707f -#define MATCH_KSUB16 0x12000077 -#define MASK_KSUB16 0xfe00707f -#define MATCH_KSUB64 0x92001077 -#define MASK_KSUB64 0xfe00707f -#define MATCH_KSUBH 0x6001077 -#define MASK_KSUBH 0xfe00707f -#define MATCH_KSUBW 0x2001077 -#define MASK_KSUBW 0xfe00707f -#define MATCH_KWMMUL 0x62001077 -#define MASK_KWMMUL 0xfe00707f -#define MATCH_KWMMUL_U 0x72001077 -#define MASK_KWMMUL_U 0xfe00707f -#define MATCH_MADDR32 0xc4001077 -#define MASK_MADDR32 0xfe00707f -#define MATCH_MAXW 0xf2000077 -#define MASK_MAXW 0xfe00707f -#define MATCH_MINW 0xf0000077 -#define MASK_MINW 0xfe00707f -#define MATCH_MSUBR32 0xc6001077 -#define MASK_MSUBR32 0xfe00707f -#define MATCH_MULR64 0xf0001077 -#define MASK_MULR64 0xfe00707f -#define MATCH_MULSR64 0xe0001077 -#define MASK_MULSR64 0xfe00707f -#define MATCH_PBSAD 0xfc000077 -#define MASK_PBSAD 0xfe00707f -#define MATCH_PBSADA 0xfe000077 -#define MASK_PBSADA 0xfe00707f -#define MATCH_PKBB16 0xe001077 -#define MASK_PKBB16 0xfe00707f -#define MATCH_PKBT16 0x1e001077 -#define MASK_PKBT16 0xfe00707f -#define MATCH_PKTT16 0x2e001077 -#define MASK_PKTT16 0xfe00707f -#define MATCH_PKTB16 0x3e001077 -#define MASK_PKTB16 0xfe00707f -#define MATCH_RADD8 0x8000077 -#define MASK_RADD8 0xfe00707f -#define MATCH_RADD16 0x77 -#define MASK_RADD16 0xfe00707f -#define MATCH_RADD64 0x80001077 -#define MASK_RADD64 0xfe00707f -#define MATCH_RADDW 0x20001077 -#define MASK_RADDW 0xfe00707f -#define MATCH_RCRAS16 0x4000077 -#define MASK_RCRAS16 0xfe00707f -#define MATCH_RCRSA16 0x6000077 -#define MASK_RCRSA16 0xfe00707f -#define MATCH_RSTAS16 0xb4002077 -#define MASK_RSTAS16 0xfe00707f -#define MATCH_RSTSA16 0xb6002077 -#define MASK_RSTSA16 0xfe00707f -#define MATCH_RSUB8 0xa000077 -#define MASK_RSUB8 0xfe00707f -#define MATCH_RSUB16 0x2000077 -#define MASK_RSUB16 0xfe00707f -#define MATCH_RSUB64 0x82001077 -#define MASK_RSUB64 0xfe00707f -#define MATCH_RSUBW 0x22001077 -#define MASK_RSUBW 0xfe00707f -#define MATCH_SCLIP8 0x8c000077 -#define MASK_SCLIP8 0xff80707f -#define MATCH_SCLIP16 0x84000077 -#define MASK_SCLIP16 0xff00707f -#define MATCH_SCLIP32 0xe4000077 -#define MASK_SCLIP32 0xfe00707f -#define MATCH_SCMPLE8 0x1e000077 -#define MASK_SCMPLE8 0xfe00707f -#define MATCH_SCMPLE16 0x1c000077 -#define MASK_SCMPLE16 0xfe00707f -#define MATCH_SCMPLT8 0xe000077 -#define MASK_SCMPLT8 0xfe00707f -#define MATCH_SCMPLT16 0xc000077 -#define MASK_SCMPLT16 0xfe00707f -#define MATCH_SLL8 0x5c000077 -#define MASK_SLL8 0xfe00707f -#define MATCH_SLLI8 0x7c000077 -#define MASK_SLLI8 0xff80707f -#define MATCH_SLL16 0x54000077 -#define MASK_SLL16 0xfe00707f -#define MATCH_SLLI16 0x74000077 -#define MASK_SLLI16 0xff00707f -#define MATCH_SMAL 0x5e001077 -#define MASK_SMAL 0xfe00707f -#define MATCH_SMALBB 0x88001077 -#define MASK_SMALBB 0xfe00707f -#define MATCH_SMALBT 0x98001077 -#define MASK_SMALBT 0xfe00707f -#define MATCH_SMALTT 0xa8001077 -#define MASK_SMALTT 0xfe00707f -#define MATCH_SMALDA 0x8c001077 -#define MASK_SMALDA 0xfe00707f -#define MATCH_SMALXDA 0x9c001077 -#define MASK_SMALXDA 0xfe00707f -#define MATCH_SMALDS 0x8a001077 -#define MASK_SMALDS 0xfe00707f -#define MATCH_SMALDRS 0x9a001077 -#define MASK_SMALDRS 0xfe00707f -#define MATCH_SMALXDS 0xaa001077 -#define MASK_SMALXDS 0xfe00707f -#define MATCH_SMAR64 0x84001077 -#define MASK_SMAR64 0xfe00707f -#define MATCH_SMAQA 0xc8000077 -#define MASK_SMAQA 0xfe00707f -#define MATCH_SMAQA_SU 0xca000077 -#define MASK_SMAQA_SU 0xfe00707f -#define MATCH_SMAX8 0x8a000077 -#define MASK_SMAX8 0xfe00707f -#define MATCH_SMAX16 0x82000077 -#define MASK_SMAX16 0xfe00707f -#define MATCH_SMBB16 0x8001077 -#define MASK_SMBB16 0xfe00707f -#define MATCH_SMBT16 0x18001077 -#define MASK_SMBT16 0xfe00707f -#define MATCH_SMTT16 0x28001077 -#define MASK_SMTT16 0xfe00707f -#define MATCH_SMDS 0x58001077 -#define MASK_SMDS 0xfe00707f -#define MATCH_SMDRS 0x68001077 -#define MASK_SMDRS 0xfe00707f -#define MATCH_SMXDS 0x78001077 -#define MASK_SMXDS 0xfe00707f -#define MATCH_SMIN8 0x88000077 -#define MASK_SMIN8 0xfe00707f -#define MATCH_SMIN16 0x80000077 -#define MASK_SMIN16 0xfe00707f -#define MATCH_SMMUL 0x40001077 -#define MASK_SMMUL 0xfe00707f -#define MATCH_SMMUL_U 0x50001077 -#define MASK_SMMUL_U 0xfe00707f -#define MATCH_SMMWB 0x44001077 -#define MASK_SMMWB 0xfe00707f -#define MATCH_SMMWB_U 0x54001077 -#define MASK_SMMWB_U 0xfe00707f -#define MATCH_SMMWT 0x64001077 -#define MASK_SMMWT 0xfe00707f -#define MATCH_SMMWT_U 0x74001077 -#define MASK_SMMWT_U 0xfe00707f -#define MATCH_SMSLDA 0xac001077 -#define MASK_SMSLDA 0xfe00707f -#define MATCH_SMSLXDA 0xbc001077 -#define MASK_SMSLXDA 0xfe00707f -#define MATCH_SMSR64 0x86001077 -#define MASK_SMSR64 0xfe00707f -#define MATCH_SMUL8 0xa8000077 -#define MASK_SMUL8 0xfe00707f -#define MATCH_SMULX8 0xaa000077 -#define MASK_SMULX8 0xfe00707f -#define MATCH_SMUL16 0xa0000077 -#define MASK_SMUL16 0xfe00707f -#define MATCH_SMULX16 0xa2000077 -#define MASK_SMULX16 0xfe00707f -#define MATCH_SRA_U 0x24001077 -#define MASK_SRA_U 0xfe00707f -#define MATCH_SRAI_U 0xd4001077 -#define MASK_SRAI_U 0xfc00707f -#define MATCH_SRA8 0x58000077 -#define MASK_SRA8 0xfe00707f -#define MATCH_SRA8_U 0x68000077 -#define MASK_SRA8_U 0xfe00707f -#define MATCH_SRAI8 0x78000077 -#define MASK_SRAI8 0xff80707f -#define MATCH_SRAI8_U 0x78800077 -#define MASK_SRAI8_U 0xff80707f -#define MATCH_SRA16 0x50000077 -#define MASK_SRA16 0xfe00707f -#define MATCH_SRA16_U 0x60000077 -#define MASK_SRA16_U 0xfe00707f -#define MATCH_SRAI16 0x70000077 -#define MASK_SRAI16 0xff00707f -#define MATCH_SRAI16_U 0x71000077 -#define MASK_SRAI16_U 0xff00707f -#define MATCH_SRL8 0x5a000077 -#define MASK_SRL8 0xfe00707f -#define MATCH_SRL8_U 0x6a000077 -#define MASK_SRL8_U 0xfe00707f -#define MATCH_SRLI8 0x7a000077 -#define MASK_SRLI8 0xff80707f -#define MATCH_SRLI8_U 0x7a800077 -#define MASK_SRLI8_U 0xff80707f -#define MATCH_SRL16 0x52000077 -#define MASK_SRL16 0xfe00707f -#define MATCH_SRL16_U 0x62000077 -#define MASK_SRL16_U 0xfe00707f -#define MATCH_SRLI16 0x72000077 -#define MASK_SRLI16 0xff00707f -#define MATCH_SRLI16_U 0x73000077 -#define MASK_SRLI16_U 0xff00707f -#define MATCH_STAS16 0xf4002077 -#define MASK_STAS16 0xfe00707f -#define MATCH_STSA16 0xf6002077 -#define MASK_STSA16 0xfe00707f -#define MATCH_SUB8 0x4a000077 -#define MASK_SUB8 0xfe00707f -#define MATCH_SUB16 0x42000077 -#define MASK_SUB16 0xfe00707f -#define MATCH_SUB64 0xc2001077 -#define MASK_SUB64 0xfe00707f -#define MATCH_SUNPKD810 0xac800077 -#define MASK_SUNPKD810 0xfff0707f -#define MATCH_SUNPKD820 0xac900077 -#define MASK_SUNPKD820 0xfff0707f -#define MATCH_SUNPKD830 0xaca00077 -#define MASK_SUNPKD830 0xfff0707f -#define MATCH_SUNPKD831 0xacb00077 -#define MASK_SUNPKD831 0xfff0707f -#define MATCH_SUNPKD832 0xad300077 -#define MASK_SUNPKD832 0xfff0707f -#define MATCH_SWAP8 0xad800077 -#define MASK_SWAP8 0xfff0707f -#define MATCH_UCLIP8 0x8d000077 -#define MASK_UCLIP8 0xff80707f -#define MATCH_UCLIP16 0x85000077 -#define MASK_UCLIP16 0xff00707f -#define MATCH_UCLIP32 0xf4000077 -#define MASK_UCLIP32 0xfe00707f -#define MATCH_UCMPLE8 0x3e000077 -#define MASK_UCMPLE8 0xfe00707f -#define MATCH_UCMPLE16 0x3c000077 -#define MASK_UCMPLE16 0xfe00707f -#define MATCH_UCMPLT8 0x2e000077 -#define MASK_UCMPLT8 0xfe00707f -#define MATCH_UCMPLT16 0x2c000077 -#define MASK_UCMPLT16 0xfe00707f -#define MATCH_UKADD8 0x38000077 -#define MASK_UKADD8 0xfe00707f -#define MATCH_UKADD16 0x30000077 -#define MASK_UKADD16 0xfe00707f -#define MATCH_UKADD64 0xb0001077 -#define MASK_UKADD64 0xfe00707f -#define MATCH_UKADDH 0x14001077 -#define MASK_UKADDH 0xfe00707f -#define MATCH_UKADDW 0x10001077 -#define MASK_UKADDW 0xfe00707f -#define MATCH_UKCRAS16 0x34000077 -#define MASK_UKCRAS16 0xfe00707f -#define MATCH_UKCRSA16 0x36000077 -#define MASK_UKCRSA16 0xfe00707f -#define MATCH_UKMAR64 0xb4001077 -#define MASK_UKMAR64 0xfe00707f -#define MATCH_UKMSR64 0xb6001077 -#define MASK_UKMSR64 0xfe00707f -#define MATCH_UKSTAS16 0xe4002077 -#define MASK_UKSTAS16 0xfe00707f -#define MATCH_UKSTSA16 0xe6002077 -#define MASK_UKSTSA16 0xfe00707f -#define MATCH_UKSUB8 0x3a000077 -#define MASK_UKSUB8 0xfe00707f -#define MATCH_UKSUB16 0x32000077 -#define MASK_UKSUB16 0xfe00707f -#define MATCH_UKSUB64 0xb2001077 -#define MASK_UKSUB64 0xfe00707f -#define MATCH_UKSUBH 0x16001077 -#define MASK_UKSUBH 0xfe00707f -#define MATCH_UKSUBW 0x12001077 -#define MASK_UKSUBW 0xfe00707f -#define MATCH_UMAR64 0xa4001077 -#define MASK_UMAR64 0xfe00707f -#define MATCH_UMAQA 0xcc000077 -#define MASK_UMAQA 0xfe00707f -#define MATCH_UMAX8 0x9a000077 -#define MASK_UMAX8 0xfe00707f -#define MATCH_UMAX16 0x92000077 -#define MASK_UMAX16 0xfe00707f -#define MATCH_UMIN8 0x98000077 -#define MASK_UMIN8 0xfe00707f -#define MATCH_UMIN16 0x90000077 -#define MASK_UMIN16 0xfe00707f -#define MATCH_UMSR64 0xa6001077 -#define MASK_UMSR64 0xfe00707f -#define MATCH_UMUL8 0xb8000077 -#define MASK_UMUL8 0xfe00707f -#define MATCH_UMULX8 0xba000077 -#define MASK_UMULX8 0xfe00707f -#define MATCH_UMUL16 0xb0000077 -#define MASK_UMUL16 0xfe00707f -#define MATCH_UMULX16 0xb2000077 -#define MASK_UMULX16 0xfe00707f -#define MATCH_URADD8 0x28000077 -#define MASK_URADD8 0xfe00707f -#define MATCH_URADD16 0x20000077 -#define MASK_URADD16 0xfe00707f -#define MATCH_URADD64 0xa0001077 -#define MASK_URADD64 0xfe00707f -#define MATCH_URADDW 0x30001077 -#define MASK_URADDW 0xfe00707f -#define MATCH_URCRAS16 0x24000077 -#define MASK_URCRAS16 0xfe00707f -#define MATCH_URCRSA16 0x26000077 -#define MASK_URCRSA16 0xfe00707f -#define MATCH_URSTAS16 0xd4002077 -#define MASK_URSTAS16 0xfe00707f -#define MATCH_URSTSA16 0xd6002077 -#define MASK_URSTSA16 0xfe00707f -#define MATCH_URSUB8 0x2a000077 -#define MASK_URSUB8 0xfe00707f -#define MATCH_URSUB16 0x22000077 -#define MASK_URSUB16 0xfe00707f -#define MATCH_URSUB64 0xa2001077 -#define MASK_URSUB64 0xfe00707f -#define MATCH_URSUBW 0x32001077 -#define MASK_URSUBW 0xfe00707f -#define MATCH_WEXTI 0xde000077 -#define MASK_WEXTI 0xfe00707f -#define MATCH_WEXT 0xce000077 -#define MASK_WEXT 0xfe00707f -#define MATCH_ZUNPKD810 0xacc00077 -#define MASK_ZUNPKD810 0xfff0707f -#define MATCH_ZUNPKD820 0xacd00077 -#define MASK_ZUNPKD820 0xfff0707f -#define MATCH_ZUNPKD830 0xace00077 -#define MASK_ZUNPKD830 0xfff0707f -#define MATCH_ZUNPKD831 0xacf00077 -#define MASK_ZUNPKD831 0xfff0707f -#define MATCH_ZUNPKD832 0xad700077 -#define MASK_ZUNPKD832 0xfff0707f -#define MATCH_ADD32 0x40002077 -#define MASK_ADD32 0xfe00707f -#define MATCH_CRAS32 0x44002077 -#define MASK_CRAS32 0xfe00707f -#define MATCH_CRSA32 0x46002077 -#define MASK_CRSA32 0xfe00707f -#define MATCH_KABS32 0xad200077 -#define MASK_KABS32 0xfff0707f -#define MATCH_KADD32 0x10002077 -#define MASK_KADD32 0xfe00707f -#define MATCH_KCRAS32 0x14002077 -#define MASK_KCRAS32 0xfe00707f -#define MATCH_KCRSA32 0x16002077 -#define MASK_KCRSA32 0xfe00707f -#define MATCH_KDMBB16 0xda001077 -#define MASK_KDMBB16 0xfe00707f -#define MATCH_KDMBT16 0xea001077 -#define MASK_KDMBT16 0xfe00707f -#define MATCH_KDMTT16 0xfa001077 -#define MASK_KDMTT16 0xfe00707f -#define MATCH_KDMABB16 0xd8001077 -#define MASK_KDMABB16 0xfe00707f -#define MATCH_KDMABT16 0xe8001077 -#define MASK_KDMABT16 0xfe00707f -#define MATCH_KDMATT16 0xf8001077 -#define MASK_KDMATT16 0xfe00707f -#define MATCH_KHMBB16 0xdc001077 -#define MASK_KHMBB16 0xfe00707f -#define MATCH_KHMBT16 0xec001077 -#define MASK_KHMBT16 0xfe00707f -#define MATCH_KHMTT16 0xfc001077 -#define MASK_KHMTT16 0xfe00707f -#define MATCH_KMABB32 0x5a002077 -#define MASK_KMABB32 0xfe00707f -#define MATCH_KMABT32 0x6a002077 -#define MASK_KMABT32 0xfe00707f -#define MATCH_KMATT32 0x7a002077 -#define MASK_KMATT32 0xfe00707f -#define MATCH_KMAXDA32 0x4a002077 -#define MASK_KMAXDA32 0xfe00707f -#define MATCH_KMDA32 0x38002077 -#define MASK_KMDA32 0xfe00707f -#define MATCH_KMXDA32 0x3a002077 -#define MASK_KMXDA32 0xfe00707f -#define MATCH_KMADS32 0x5c002077 -#define MASK_KMADS32 0xfe00707f -#define MATCH_KMADRS32 0x6c002077 -#define MASK_KMADRS32 0xfe00707f -#define MATCH_KMAXDS32 0x7c002077 -#define MASK_KMAXDS32 0xfe00707f -#define MATCH_KMSDA32 0x4c002077 -#define MASK_KMSDA32 0xfe00707f -#define MATCH_KMSXDA32 0x4e002077 -#define MASK_KMSXDA32 0xfe00707f -#define MATCH_KSLL32 0x64002077 -#define MASK_KSLL32 0xfe00707f -#define MATCH_KSLLI32 0x84002077 -#define MASK_KSLLI32 0xfe00707f -#define MATCH_KSLRA32 0x56002077 -#define MASK_KSLRA32 0xfe00707f -#define MATCH_KSLRA32_U 0x66002077 -#define MASK_KSLRA32_U 0xfe00707f -#define MATCH_KSTAS32 0xc0002077 -#define MASK_KSTAS32 0xfe00707f -#define MATCH_KSTSA32 0xc2002077 -#define MASK_KSTSA32 0xfe00707f -#define MATCH_KSUB32 0x12002077 -#define MASK_KSUB32 0xfe00707f -#define MATCH_PKBB32 0xe002077 -#define MASK_PKBB32 0xfe00707f -#define MATCH_PKBT32 0x1e002077 -#define MASK_PKBT32 0xfe00707f -#define MATCH_PKTT32 0x2e002077 -#define MASK_PKTT32 0xfe00707f -#define MATCH_PKTB32 0x3e002077 -#define MASK_PKTB32 0xfe00707f -#define MATCH_RADD32 0x2077 -#define MASK_RADD32 0xfe00707f -#define MATCH_RCRAS32 0x4002077 -#define MASK_RCRAS32 0xfe00707f -#define MATCH_RCRSA32 0x6002077 -#define MASK_RCRSA32 0xfe00707f -#define MATCH_RSTAS32 0xb0002077 -#define MASK_RSTAS32 0xfe00707f -#define MATCH_RSTSA32 0xb2002077 -#define MASK_RSTSA32 0xfe00707f -#define MATCH_RSUB32 0x2002077 -#define MASK_RSUB32 0xfe00707f -#define MATCH_SLL32 0x54002077 -#define MASK_SLL32 0xfe00707f -#define MATCH_SLLI32 0x74002077 -#define MASK_SLLI32 0xfe00707f -#define MATCH_SMAX32 0x92002077 -#define MASK_SMAX32 0xfe00707f -#define MATCH_SMBT32 0x18002077 -#define MASK_SMBT32 0xfe00707f -#define MATCH_SMTT32 0x28002077 -#define MASK_SMTT32 0xfe00707f -#define MATCH_SMDS32 0x58002077 -#define MASK_SMDS32 0xfe00707f -#define MATCH_SMDRS32 0x68002077 -#define MASK_SMDRS32 0xfe00707f -#define MATCH_SMXDS32 0x78002077 -#define MASK_SMXDS32 0xfe00707f -#define MATCH_SMIN32 0x90002077 -#define MASK_SMIN32 0xfe00707f -#define MATCH_SRA32 0x50002077 -#define MASK_SRA32 0xfe00707f -#define MATCH_SRA32_U 0x60002077 -#define MASK_SRA32_U 0xfe00707f -#define MATCH_SRAI32 0x70002077 -#define MASK_SRAI32 0xfe00707f -#define MATCH_SRAI32_U 0x80002077 -#define MASK_SRAI32_U 0xfe00707f -#define MATCH_SRAIW_U 0x34001077 -#define MASK_SRAIW_U 0xfe00707f -#define MATCH_SRL32 0x52002077 -#define MASK_SRL32 0xfe00707f -#define MATCH_SRL32_U 0x62002077 -#define MASK_SRL32_U 0xfe00707f -#define MATCH_SRLI32 0x72002077 -#define MASK_SRLI32 0xfe00707f -#define MATCH_SRLI32_U 0x82002077 -#define MASK_SRLI32_U 0xfe00707f -#define MATCH_STAS32 0xf0002077 -#define MASK_STAS32 0xfe00707f -#define MATCH_STSA32 0xf2002077 -#define MASK_STSA32 0xfe00707f -#define MATCH_SUB32 0x42002077 -#define MASK_SUB32 0xfe00707f -#define MATCH_UKADD32 0x30002077 -#define MASK_UKADD32 0xfe00707f -#define MATCH_UKCRAS32 0x34002077 -#define MASK_UKCRAS32 0xfe00707f -#define MATCH_UKCRSA32 0x36002077 -#define MASK_UKCRSA32 0xfe00707f -#define MATCH_UKSTAS32 0xe0002077 -#define MASK_UKSTAS32 0xfe00707f -#define MATCH_UKSTSA32 0xe2002077 -#define MASK_UKSTSA32 0xfe00707f -#define MATCH_UKSUB32 0x32002077 -#define MASK_UKSUB32 0xfe00707f -#define MATCH_UMAX32 0xa2002077 -#define MASK_UMAX32 0xfe00707f -#define MATCH_UMIN32 0xa0002077 -#define MASK_UMIN32 0xfe00707f -#define MATCH_URADD32 0x20002077 -#define MASK_URADD32 0xfe00707f -#define MATCH_URCRAS32 0x24002077 -#define MASK_URCRAS32 0xfe00707f -#define MATCH_URCRSA32 0x26002077 -#define MASK_URCRSA32 0xfe00707f -#define MATCH_URSTAS32 0xd0002077 -#define MASK_URSTAS32 0xfe00707f -#define MATCH_URSTSA32 0xd2002077 -#define MASK_URSTSA32 0xfe00707f -#define MATCH_URSUB32 0x22002077 -#define MASK_URSUB32 0xfe00707f -#define MATCH_VMVNFR_V 0x9e003057 -#define MASK_VMVNFR_V 0xfe00707f -#define MATCH_VL1R_V 0x2800007 -#define MASK_VL1R_V 0xfff0707f -#define MATCH_VL2R_V 0x6805007 -#define MASK_VL2R_V 0xfff0707f -#define MATCH_VL4R_V 0xe806007 -#define MASK_VL4R_V 0xfff0707f -#define MATCH_VL8R_V 0x1e807007 -#define MASK_VL8R_V 0xfff0707f -#define MATCH_VLE1_V 0x2b00007 -#define MASK_VLE1_V 0xfff0707f -#define MATCH_VSE1_V 0x2b00027 -#define MASK_VSE1_V 0xfff0707f -#define MATCH_VFREDSUM_VS 0x4001057 -#define MASK_VFREDSUM_VS 0xfc00707f -#define MATCH_VFWREDSUM_VS 0xc4001057 -#define MASK_VFWREDSUM_VS 0xfc00707f -#define MATCH_VPOPC_M 0x40082057 -#define MASK_VPOPC_M 0xfc0ff07f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_VSTART 0x8 -#define CSR_VXSAT 0x9 -#define CSR_VXRM 0xa -#define CSR_VCSR 0xf -#define CSR_SEED 0x15 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_VL 0xc20 -#define CSR_VTYPE 0xc21 -#define CSR_VLENB 0xc22 -#define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 -#define CSR_SATP 0x180 -#define CSR_SCONTEXT 0x5a8 -#define CSR_VSSTATUS 0x200 -#define CSR_VSIE 0x204 -#define CSR_VSTVEC 0x205 -#define CSR_VSSCRATCH 0x240 -#define CSR_VSEPC 0x241 -#define CSR_VSCAUSE 0x242 -#define CSR_VSTVAL 0x243 -#define CSR_VSIP 0x244 -#define CSR_VSATP 0x280 -#define CSR_HSTATUS 0x600 -#define CSR_HEDELEG 0x602 -#define CSR_HIDELEG 0x603 -#define CSR_HIE 0x604 -#define CSR_HTIMEDELTA 0x605 -#define CSR_HCOUNTEREN 0x606 -#define CSR_HGEIE 0x607 -#define CSR_HTVAL 0x643 -#define CSR_HIP 0x644 -#define CSR_HVIP 0x645 -#define CSR_HTINST 0x64a -#define CSR_HGATP 0x680 -#define CSR_HCONTEXT 0x6a8 -#define CSR_HGEIP 0xe12 -#define CSR_UTVT 0x7 -#define CSR_UNXTI 0x45 -#define CSR_UINTSTATUS 0x46 -#define CSR_USCRATCHCSW 0x48 -#define CSR_USCRATCHCSWL 0x49 -#define CSR_STVT 0x107 -#define CSR_SNXTI 0x145 -#define CSR_SINTSTATUS 0x146 -#define CSR_SSCRATCHCSW 0x148 -#define CSR_SSCRATCHCSWL 0x149 -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 -#define CSR_MINTSTATUS 0x346 -#define CSR_MSCRATCHCSW 0x348 -#define CSR_MSCRATCHCSWL 0x349 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MCOUNTINHIBIT 0x320 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MTINST 0x34a -#define CSR_MTVAL2 0x34b -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_TINFO 0x7a4 -#define CSR_TCONTROL 0x7a5 -#define CSR_MCONTEXT 0x7a8 -#define CSR_MSCONTEXT 0x7aa -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH0 0x7b2 -#define CSR_DSCRATCH1 0x7b3 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_HTIMEDELTAH 0x615 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MSTATUSH 0x310 -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 -#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 -#define CAUSE_VIRTUAL_INSTRUCTION 0x16 -#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) -DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) -DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) -DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) -DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) -DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) -DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) -DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) -DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) -DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) -DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) -DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) -DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) -DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) -DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) -DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) -DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) -DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) -DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) -DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) -DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) -DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) -DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) -DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) -DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) -DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) -DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) -DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) -DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) -DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) -DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) -DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) -DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) -DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) -DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) -DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) -DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) -DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) -DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) -DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) -DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) -DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) -DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) -DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) -DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) -DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) -DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) -DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) -DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) -DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) -DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) -DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) -DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) -DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) -DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) -DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) -DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) -DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) -DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) -DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) -DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) -DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) -DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) -DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) -DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) -DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) -DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) -DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) -DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) -DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) -DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) -DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) -DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) -DECLARE_INSN(min, MATCH_MIN, MASK_MIN) -DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) -DECLARE_INSN(max, MATCH_MAX, MASK_MAX) -DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) -DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) -DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) -DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) -DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) -DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) -DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) -DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) -DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) -DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) -DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) -DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) -DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) -DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) -DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) -DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) -DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) -DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) -DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) -DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) -DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) -DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) -DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) -DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) -DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) -DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW) -DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW) -DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW) -DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW) -DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) -DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) -DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) -DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) -DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) -DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW) -DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW) -DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW) -DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) -DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) -DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) -DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) -DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) -DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) -DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) -DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) -DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) -DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) -DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) -DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) -DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) -DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) -DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) -DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) -DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) -DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) -DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) -DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) -DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) -DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) -DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) -DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) -DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) -DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) -DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) -DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) -DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) -DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) -DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) -DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) -DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) -DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) -DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) -DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) -DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) -DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) -DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) -DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) -DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) -DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) -DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) -DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) -DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) -DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) -DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) -DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) -DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) -DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) -DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) -DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) -DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) -DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) -DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) -DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32) -DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32) -DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) -DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) -DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) -DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) -DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) -DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) -DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) -DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) -DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) -DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) -DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) -DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) -DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) -DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) -DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) -DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) -DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) -DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) -DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) -DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) -DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) -DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) -DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) -DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) -DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) -DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) -DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) -DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) -DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) -DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) -DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) -DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) -DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) -DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) -DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) -DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) -DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) -DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) -DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) -DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) -DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) -DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) -DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) -DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) -DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) -DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) -DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) -DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) -DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) -DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) -DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) -DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) -DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) -DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) -DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) -DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) -DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) -DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) -DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) -DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) -DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) -DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) -DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) -DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) -DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) -DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) -DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) -DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) -DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) -DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) -DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) -DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) -DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) -DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) -DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) -DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) -DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) -DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) -DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) -DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) -DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) -DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) -DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) -DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) -DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) -DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) -DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) -DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) -DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) -DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) -DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) -DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) -DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) -DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) -DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) -DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) -DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) -DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) -DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) -DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) -DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) -DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) -DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) -DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) -DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) -DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) -DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) -DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) -DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) -DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) -DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) -DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) -DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) -DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) -DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) -DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) -DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) -DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) -DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) -DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) -DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) -DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) -DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) -DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) -DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) -DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) -DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) -DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) -DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) -DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) -DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) -DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) -DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) -DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) -DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) -DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) -DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) -DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) -DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) -DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) -DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) -DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) -DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) -DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) -DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) -DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) -DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) -DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) -DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) -DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) -DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) -DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) -DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) -DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) -DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) -DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) -DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) -DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) -DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) -DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) -DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) -DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) -DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) -DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) -DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) -DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) -DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) -DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) -DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) -DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) -DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) -DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) -DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) -DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) -DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) -DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) -DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) -DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) -DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) -DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) -DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) -DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) -DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) -DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) -DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) -DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) -DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) -DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) -DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) -DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) -DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) -DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) -DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) -DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) -DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) -DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) -DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) -DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) -DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) -DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) -DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) -DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) -DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) -DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) -DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) -DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) -DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) -DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) -DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) -DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) -DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) -DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) -DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) -DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) -DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) -DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) -DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) -DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) -DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) -DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) -DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) -DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) -DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) -DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) -DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) -DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) -DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) -DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) -DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) -DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) -DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) -DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) -DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) -DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) -DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) -DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) -DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) -DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) -DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) -DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) -DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) -DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) -DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) -DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) -DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) -DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) -DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) -DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) -DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) -DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) -DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) -DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) -DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) -DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) -DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) -DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) -DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) -DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) -DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) -DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) -DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) -DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) -DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) -DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) -DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) -DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) -DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) -DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) -DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) -DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) -DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) -DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) -DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) -DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) -DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) -DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) -DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) -DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) -DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) -DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) -DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) -DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) -DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) -DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) -DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) -DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) -DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) -DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) -DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) -DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) -DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) -DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) -DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) -DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) -DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) -DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) -DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) -DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) -DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) -DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) -DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) -DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) -DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) -DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) -DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) -DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) -DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) -DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) -DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) -DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) -DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) -DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) -DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) -DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) -DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) -DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) -DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) -DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) -DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) -DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) -DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) -DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) -DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) -DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) -DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) -DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) -DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) -DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) -DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) -DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) -DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) -DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) -DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) -DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) -DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) -DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) -DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM) -DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) -DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) -DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) -DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM) -DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) -DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) -DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) -DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) -DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) -DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) -DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) -DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) -DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) -DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) -DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) -DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) -DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) -DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) -DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) -DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) -DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) -DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) -DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) -DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) -DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) -DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) -DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) -DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) -DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) -DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) -DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) -DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) -DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) -DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) -DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) -DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) -DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) -DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) -DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) -DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) -DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) -DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) -DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) -DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) -DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) -DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) -DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) -DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) -DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) -DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) -DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) -DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) -DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) -DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) -DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) -DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) -DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) -DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) -DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) -DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) -DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) -DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) -DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) -DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) -DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) -DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) -DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) -DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) -DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) -DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) -DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) -DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) -DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) -DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) -DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) -DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) -DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) -DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) -DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) -DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) -DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) -DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) -DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) -DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) -DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) -DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) -DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) -DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) -DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) -DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) -DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) -DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) -DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) -DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) -DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) -DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) -DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) -DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) -DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) -DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) -DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) -DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) -DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) -DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) -DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) -DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) -DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) -DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) -DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) -DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) -DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) +#define MASK_C_SDSP 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_SQ 0xa000 +#define MASK_C_SQ 0xe003 +#define MATCH_C_SQSP 0xa002 +#define MASK_C_SQSP 0xe003 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_CBO_CLEAN 0x10200f +#define MASK_CBO_CLEAN 0xfff07fff +#define MATCH_CBO_FLUSH 0x20200f +#define MASK_CBO_FLUSH 0xfff07fff +#define MATCH_CBO_INVAL 0x200f +#define MASK_CBO_INVAL 0xfff07fff +#define MATCH_CBO_ZERO 0x40200f +#define MASK_CBO_ZERO 0xfff07fff +#define MATCH_CLMUL 0xa001033 +#define MASK_CLMUL 0xfe00707f +#define MATCH_CLMULH 0xa003033 +#define MASK_CLMULH 0xfe00707f +#define MATCH_CLMULR 0xa002033 +#define MASK_CLMULR 0xfe00707f +#define MATCH_CLO16 0xaeb00077 +#define MASK_CLO16 0xfff0707f +#define MATCH_CLO32 0xafb00077 +#define MASK_CLO32 0xfff0707f +#define MATCH_CLO8 0xae300077 +#define MASK_CLO8 0xfff0707f +#define MATCH_CLRS16 0xae800077 +#define MASK_CLRS16 0xfff0707f +#define MATCH_CLRS32 0xaf800077 +#define MASK_CLRS32 0xfff0707f +#define MATCH_CLRS8 0xae000077 +#define MASK_CLRS8 0xfff0707f +#define MATCH_CLZ 0x60001013 +#define MASK_CLZ 0xfff0707f +#define MATCH_CLZ16 0xae900077 +#define MASK_CLZ16 0xfff0707f +#define MATCH_CLZ32 0xaf900077 +#define MASK_CLZ32 0xfff0707f +#define MATCH_CLZ8 0xae100077 +#define MASK_CLZ8 0xfff0707f +#define MATCH_CLZW 0x6000101b +#define MASK_CLZW 0xfff0707f +#define MATCH_CMIX 0x6001033 +#define MASK_CMIX 0x600707f +#define MATCH_CMOV 0x6005033 +#define MASK_CMOV 0x600707f +#define MATCH_CMPEQ16 0x4c000077 +#define MASK_CMPEQ16 0xfe00707f +#define MATCH_CMPEQ8 0x4e000077 +#define MASK_CMPEQ8 0xfe00707f +#define MATCH_CPOP 0x60201013 +#define MASK_CPOP 0xfff0707f +#define MATCH_CPOPW 0x6020101b +#define MASK_CPOPW 0xfff0707f +#define MATCH_CRAS16 0x44000077 +#define MASK_CRAS16 0xfe00707f +#define MATCH_CRAS32 0x44002077 +#define MASK_CRAS32 0xfe00707f +#define MATCH_CRC32_B 0x61001013 +#define MASK_CRC32_B 0xfff0707f +#define MATCH_CRC32_D 0x61301013 +#define MASK_CRC32_D 0xfff0707f +#define MATCH_CRC32_H 0x61101013 +#define MASK_CRC32_H 0xfff0707f +#define MATCH_CRC32_W 0x61201013 +#define MASK_CRC32_W 0xfff0707f +#define MATCH_CRC32C_B 0x61801013 +#define MASK_CRC32C_B 0xfff0707f +#define MATCH_CRC32C_D 0x61b01013 +#define MASK_CRC32C_D 0xfff0707f +#define MATCH_CRC32C_H 0x61901013 +#define MASK_CRC32C_H 0xfff0707f +#define MATCH_CRC32C_W 0x61a01013 +#define MASK_CRC32C_W 0xfff0707f +#define MATCH_CRSA16 0x46000077 +#define MASK_CRSA16 0xfe00707f +#define MATCH_CRSA32 0x46002077 +#define MASK_CRSA32 0xfe00707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CTZ 0x60101013 +#define MASK_CTZ 0xfff0707f +#define MATCH_CTZW 0x6010101b +#define MASK_CTZW 0xfff0707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FADD_H 0x4000053 +#define MASK_FADD_H 0xfe00007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCLASS_H 0xe4001053 +#define MASK_FCLASS_H 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_D_H 0x42200053 +#define MASK_FCVT_D_H 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_H_D 0x44100053 +#define MASK_FCVT_H_D 0xfff0007f +#define MATCH_FCVT_H_L 0xd4200053 +#define MASK_FCVT_H_L 0xfff0007f +#define MATCH_FCVT_H_LU 0xd4300053 +#define MASK_FCVT_H_LU 0xfff0007f +#define MATCH_FCVT_H_Q 0x44300053 +#define MASK_FCVT_H_Q 0xfff0007f +#define MATCH_FCVT_H_S 0x44000053 +#define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_H_W 0xd4000053 +#define MASK_FCVT_H_W 0xfff0007f +#define MATCH_FCVT_H_WU 0xd4100053 +#define MASK_FCVT_H_WU 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_L_H 0xc4200053 +#define MASK_FCVT_L_H 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FCVT_LU_H 0xc4300053 +#define MASK_FCVT_LU_H 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FCVT_Q_H 0x46200053 +#define MASK_FCVT_Q_H 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_S_H 0x40200053 +#define MASK_FCVT_S_H 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_W_H 0xc4000053 +#define MASK_FCVT_W_H 0xfff0007f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_WU_H 0xc4100053 +#define MASK_FCVT_WU_H 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FDIV_H 0x1c000053 +#define MASK_FDIV_H 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FEQ_H 0xa4002053 +#define MASK_FEQ_H 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLE_H 0xa4000053 +#define MASK_FLE_H 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLH 0x1007 +#define MASK_FLH 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FLT_H 0xa4001053 +#define MASK_FLT_H 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMADD_H 0x4000043 +#define MASK_FMADD_H 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FMAX_H 0x2c001053 +#define MASK_FMAX_H 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMIN_H 0x2c000053 +#define MASK_FMIN_H 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FMSUB_H 0x4000047 +#define MASK_FMSUB_H 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FMUL_H 0x14000053 +#define MASK_FMUL_H 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FMV_H_X 0xf4000053 +#define MASK_FMV_H_X 0xfff0707f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FMV_X_H 0xe4000053 +#define MASK_FMV_X_H 0xfff0707f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FNMADD_H 0x400004f +#define MASK_FNMADD_H 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMSUB_H 0x400004b +#define MASK_FNMSUB_H 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJ_H 0x24000053 +#define MASK_FSGNJ_H 0xfe00707f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJN_H 0x24001053 +#define MASK_FSGNJN_H 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FSGNJX_H 0x24002053 +#define MASK_FSGNJX_H 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FSH 0x1027 +#define MASK_FSH 0x707f +#define MATCH_FSL 0x4001033 +#define MASK_FSL 0x600707f +#define MATCH_FSLW 0x400103b +#define MASK_FSLW 0x600707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FSQRT_H 0x5c000053 +#define MASK_FSQRT_H 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FSR 0x4005033 +#define MASK_FSR 0x600707f +#define MATCH_FSRI 0x4005013 +#define MASK_FSRI 0x400707f +#define MATCH_FSRIW 0x400501b +#define MASK_FSRIW 0x600707f +#define MATCH_FSRW 0x400503b +#define MASK_FSRW 0x600707f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FSUB_H 0xc000053 +#define MASK_FSUB_H 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_GORC 0x28005033 +#define MASK_GORC 0xfe00707f +#define MATCH_GORCI 0x28005013 +#define MASK_GORCI 0xfc00707f +#define MATCH_GORCIW 0x2800501b +#define MASK_GORCIW 0xfe00707f +#define MATCH_GORCW 0x2800503b +#define MASK_GORCW 0xfe00707f +#define MATCH_GREV 0x68005033 +#define MASK_GREV 0xfe00707f +#define MATCH_GREVI 0x68005013 +#define MASK_GREVI 0xfc00707f +#define MATCH_GREVIW 0x6800501b +#define MASK_GREVIW 0xfe00707f +#define MATCH_GREVW 0x6800503b +#define MASK_GREVW 0xfe00707f +#define MATCH_HFENCE_GVMA 0x62000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HINVAL_GVMA 0x66000073 +#define MASK_HINVAL_GVMA 0xfe007fff +#define MATCH_HINVAL_VVMA 0x26000073 +#define MASK_HINVAL_VVMA 0xfe007fff +#define MATCH_HLV_B 0x60004073 +#define MASK_HLV_B 0xfff0707f +#define MATCH_HLV_BU 0x60104073 +#define MASK_HLV_BU 0xfff0707f +#define MATCH_HLV_D 0x6c004073 +#define MASK_HLV_D 0xfff0707f +#define MATCH_HLV_H 0x64004073 +#define MASK_HLV_H 0xfff0707f +#define MATCH_HLV_HU 0x64104073 +#define MASK_HLV_HU 0xfff0707f +#define MATCH_HLV_W 0x68004073 +#define MASK_HLV_W 0xfff0707f +#define MATCH_HLV_WU 0x68104073 +#define MASK_HLV_WU 0xfff0707f +#define MATCH_HLVX_HU 0x64304073 +#define MASK_HLVX_HU 0xfff0707f +#define MATCH_HLVX_WU 0x68304073 +#define MASK_HLVX_WU 0xfff0707f +#define MATCH_HSV_B 0x62004073 +#define MASK_HSV_B 0xfe007fff +#define MATCH_HSV_D 0x6e004073 +#define MASK_HSV_D 0xfe007fff +#define MATCH_HSV_H 0x66004073 +#define MASK_HSV_H 0xfe007fff +#define MATCH_HSV_W 0x6a004073 +#define MASK_HSV_W 0xfe007fff +#define MATCH_INSB 0xac000077 +#define MASK_INSB 0xff80707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_KABS16 0xad100077 +#define MASK_KABS16 0xfff0707f +#define MATCH_KABS32 0xad200077 +#define MASK_KABS32 0xfff0707f +#define MATCH_KABS8 0xad000077 +#define MASK_KABS8 0xfff0707f +#define MATCH_KABSW 0xad400077 +#define MASK_KABSW 0xfff0707f +#define MATCH_KADD16 0x10000077 +#define MASK_KADD16 0xfe00707f +#define MATCH_KADD32 0x10002077 +#define MASK_KADD32 0xfe00707f +#define MATCH_KADD64 0x90001077 +#define MASK_KADD64 0xfe00707f +#define MATCH_KADD8 0x18000077 +#define MASK_KADD8 0xfe00707f +#define MATCH_KADDH 0x4001077 +#define MASK_KADDH 0xfe00707f +#define MATCH_KADDW 0x1077 +#define MASK_KADDW 0xfe00707f +#define MATCH_KCRAS16 0x14000077 +#define MASK_KCRAS16 0xfe00707f +#define MATCH_KCRAS32 0x14002077 +#define MASK_KCRAS32 0xfe00707f +#define MATCH_KCRSA16 0x16000077 +#define MASK_KCRSA16 0xfe00707f +#define MATCH_KCRSA32 0x16002077 +#define MASK_KCRSA32 0xfe00707f +#define MATCH_KDMABB 0xd2001077 +#define MASK_KDMABB 0xfe00707f +#define MATCH_KDMABB16 0xd8001077 +#define MASK_KDMABB16 0xfe00707f +#define MATCH_KDMABT 0xe2001077 +#define MASK_KDMABT 0xfe00707f +#define MATCH_KDMABT16 0xe8001077 +#define MASK_KDMABT16 0xfe00707f +#define MATCH_KDMATT 0xf2001077 +#define MASK_KDMATT 0xfe00707f +#define MATCH_KDMATT16 0xf8001077 +#define MASK_KDMATT16 0xfe00707f +#define MATCH_KDMBB 0xa001077 +#define MASK_KDMBB 0xfe00707f +#define MATCH_KDMBB16 0xda001077 +#define MASK_KDMBB16 0xfe00707f +#define MATCH_KDMBT 0x1a001077 +#define MASK_KDMBT 0xfe00707f +#define MATCH_KDMBT16 0xea001077 +#define MASK_KDMBT16 0xfe00707f +#define MATCH_KDMTT 0x2a001077 +#define MASK_KDMTT 0xfe00707f +#define MATCH_KDMTT16 0xfa001077 +#define MASK_KDMTT16 0xfe00707f +#define MATCH_KHM16 0x86000077 +#define MASK_KHM16 0xfe00707f +#define MATCH_KHM8 0x8e000077 +#define MASK_KHM8 0xfe00707f +#define MATCH_KHMBB 0xc001077 +#define MASK_KHMBB 0xfe00707f +#define MATCH_KHMBB16 0xdc001077 +#define MASK_KHMBB16 0xfe00707f +#define MATCH_KHMBT 0x1c001077 +#define MASK_KHMBT 0xfe00707f +#define MATCH_KHMBT16 0xec001077 +#define MASK_KHMBT16 0xfe00707f +#define MATCH_KHMTT 0x2c001077 +#define MASK_KHMTT 0xfe00707f +#define MATCH_KHMTT16 0xfc001077 +#define MASK_KHMTT16 0xfe00707f +#define MATCH_KHMX16 0x96000077 +#define MASK_KHMX16 0xfe00707f +#define MATCH_KHMX8 0x9e000077 +#define MASK_KHMX8 0xfe00707f +#define MATCH_KMABB 0x5a001077 +#define MASK_KMABB 0xfe00707f +#define MATCH_KMABB32 0x5a002077 +#define MASK_KMABB32 0xfe00707f +#define MATCH_KMABT 0x6a001077 +#define MASK_KMABT 0xfe00707f +#define MATCH_KMABT32 0x6a002077 +#define MASK_KMABT32 0xfe00707f +#define MATCH_KMADA 0x48001077 +#define MASK_KMADA 0xfe00707f +#define MATCH_KMADRS 0x6c001077 +#define MASK_KMADRS 0xfe00707f +#define MATCH_KMADRS32 0x6c002077 +#define MASK_KMADRS32 0xfe00707f +#define MATCH_KMADS 0x5c001077 +#define MASK_KMADS 0xfe00707f +#define MATCH_KMADS32 0x5c002077 +#define MASK_KMADS32 0xfe00707f +#define MATCH_KMAR64 0x94001077 +#define MASK_KMAR64 0xfe00707f +#define MATCH_KMATT 0x7a001077 +#define MASK_KMATT 0xfe00707f +#define MATCH_KMATT32 0x7a002077 +#define MASK_KMATT32 0xfe00707f +#define MATCH_KMAXDA 0x4a001077 +#define MASK_KMAXDA 0xfe00707f +#define MATCH_KMAXDA32 0x4a002077 +#define MASK_KMAXDA32 0xfe00707f +#define MATCH_KMAXDS 0x7c001077 +#define MASK_KMAXDS 0xfe00707f +#define MATCH_KMAXDS32 0x7c002077 +#define MASK_KMAXDS32 0xfe00707f +#define MATCH_KMDA 0x38001077 +#define MASK_KMDA 0xfe00707f +#define MATCH_KMDA32 0x38002077 +#define MASK_KMDA32 0xfe00707f +#define MATCH_KMMAC 0x60001077 +#define MASK_KMMAC 0xfe00707f +#define MATCH_KMMAC_U 0x70001077 +#define MASK_KMMAC_U 0xfe00707f +#define MATCH_KMMAWB 0x46001077 +#define MASK_KMMAWB 0xfe00707f +#define MATCH_KMMAWB2 0xce001077 +#define MASK_KMMAWB2 0xfe00707f +#define MATCH_KMMAWB2_U 0xde001077 +#define MASK_KMMAWB2_U 0xfe00707f +#define MATCH_KMMAWB_U 0x56001077 +#define MASK_KMMAWB_U 0xfe00707f +#define MATCH_KMMAWT 0x66001077 +#define MASK_KMMAWT 0xfe00707f +#define MATCH_KMMAWT2 0xee001077 +#define MASK_KMMAWT2 0xfe00707f +#define MATCH_KMMAWT2_U 0xfe001077 +#define MASK_KMMAWT2_U 0xfe00707f +#define MATCH_KMMAWT_U 0x76001077 +#define MASK_KMMAWT_U 0xfe00707f +#define MATCH_KMMSB 0x42001077 +#define MASK_KMMSB 0xfe00707f +#define MATCH_KMMSB_U 0x52001077 +#define MASK_KMMSB_U 0xfe00707f +#define MATCH_KMMWB2 0x8e001077 +#define MASK_KMMWB2 0xfe00707f +#define MATCH_KMMWB2_U 0x9e001077 +#define MASK_KMMWB2_U 0xfe00707f +#define MATCH_KMMWT2 0xae001077 +#define MASK_KMMWT2 0xfe00707f +#define MATCH_KMMWT2_U 0xbe001077 +#define MASK_KMMWT2_U 0xfe00707f +#define MATCH_KMSDA 0x4c001077 +#define MASK_KMSDA 0xfe00707f +#define MATCH_KMSDA32 0x4c002077 +#define MASK_KMSDA32 0xfe00707f +#define MATCH_KMSR64 0x96001077 +#define MASK_KMSR64 0xfe00707f +#define MATCH_KMSXDA 0x4e001077 +#define MASK_KMSXDA 0xfe00707f +#define MATCH_KMSXDA32 0x4e002077 +#define MASK_KMSXDA32 0xfe00707f +#define MATCH_KMXDA 0x3a001077 +#define MASK_KMXDA 0xfe00707f +#define MATCH_KMXDA32 0x3a002077 +#define MASK_KMXDA32 0xfe00707f +#define MATCH_KSLL16 0x64000077 +#define MASK_KSLL16 0xfe00707f +#define MATCH_KSLL32 0x64002077 +#define MASK_KSLL32 0xfe00707f +#define MATCH_KSLL8 0x6c000077 +#define MASK_KSLL8 0xfe00707f +#define MATCH_KSLLI16 0x75000077 +#define MASK_KSLLI16 0xff00707f +#define MATCH_KSLLI32 0x84002077 +#define MASK_KSLLI32 0xfe00707f +#define MATCH_KSLLI8 0x7c800077 +#define MASK_KSLLI8 0xff80707f +#define MATCH_KSLLIW 0x36001077 +#define MASK_KSLLIW 0xfe00707f +#define MATCH_KSLLW 0x26001077 +#define MASK_KSLLW 0xfe00707f +#define MATCH_KSLRA16 0x56000077 +#define MASK_KSLRA16 0xfe00707f +#define MATCH_KSLRA16_U 0x66000077 +#define MASK_KSLRA16_U 0xfe00707f +#define MATCH_KSLRA32 0x56002077 +#define MASK_KSLRA32 0xfe00707f +#define MATCH_KSLRA32_U 0x66002077 +#define MASK_KSLRA32_U 0xfe00707f +#define MATCH_KSLRA8 0x5e000077 +#define MASK_KSLRA8 0xfe00707f +#define MATCH_KSLRA8_U 0x6e000077 +#define MASK_KSLRA8_U 0xfe00707f +#define MATCH_KSLRAW 0x6e001077 +#define MASK_KSLRAW 0xfe00707f +#define MATCH_KSLRAW_U 0x7e001077 +#define MASK_KSLRAW_U 0xfe00707f +#define MATCH_KSTAS16 0xc4002077 +#define MASK_KSTAS16 0xfe00707f +#define MATCH_KSTAS32 0xc0002077 +#define MASK_KSTAS32 0xfe00707f +#define MATCH_KSTSA16 0xc6002077 +#define MASK_KSTSA16 0xfe00707f +#define MATCH_KSTSA32 0xc2002077 +#define MASK_KSTSA32 0xfe00707f +#define MATCH_KSUB16 0x12000077 +#define MASK_KSUB16 0xfe00707f +#define MATCH_KSUB32 0x12002077 +#define MASK_KSUB32 0xfe00707f +#define MATCH_KSUB64 0x92001077 +#define MASK_KSUB64 0xfe00707f +#define MATCH_KSUB8 0x1a000077 +#define MASK_KSUB8 0xfe00707f +#define MATCH_KSUBH 0x6001077 +#define MASK_KSUBH 0xfe00707f +#define MATCH_KSUBW 0x2001077 +#define MASK_KSUBW 0xfe00707f +#define MATCH_KWMMUL 0x62001077 +#define MASK_KWMMUL 0xfe00707f +#define MATCH_KWMMUL_U 0x72001077 +#define MASK_KWMMUL_U 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LDU 0x7003 +#define MASK_LDU 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LQ 0x300f +#define MASK_LQ 0x707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_MADDR32 0xc4001077 +#define MASK_MADDR32 0xfe00707f +#define MATCH_MAX 0xa006033 +#define MASK_MAX 0xfe00707f +#define MATCH_MAXU 0xa007033 +#define MASK_MAXU 0xfe00707f +#define MATCH_MAXW 0xf2000077 +#define MASK_MAXW 0xfe00707f +#define MATCH_MIN 0xa004033 +#define MASK_MIN 0xfe00707f +#define MATCH_MINU 0xa005033 +#define MASK_MINU 0xfe00707f +#define MATCH_MINW 0xf0000077 +#define MASK_MINW 0xfe00707f +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_MSUBR32 0xc6001077 +#define MASK_MSUBR32 0xfe00707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_MULR64 0xf0001077 +#define MASK_MULR64 0xfe00707f +#define MATCH_MULSR64 0xe0001077 +#define MASK_MULSR64 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ORN 0x40006033 +#define MASK_ORN 0xfe00707f +#define MATCH_PACK 0x8004033 +#define MASK_PACK 0xfe00707f +#define MATCH_PACKH 0x8007033 +#define MASK_PACKH 0xfe00707f +#define MATCH_PACKU 0x48004033 +#define MASK_PACKU 0xfe00707f +#define MATCH_PACKUW 0x4800403b +#define MASK_PACKUW 0xfe00707f +#define MATCH_PACKW 0x800403b +#define MASK_PACKW 0xfe00707f +#define MATCH_PAUSE 0x100000f +#define MASK_PAUSE 0xffffffff +#define MATCH_PBSAD 0xfc000077 +#define MASK_PBSAD 0xfe00707f +#define MATCH_PBSADA 0xfe000077 +#define MASK_PBSADA 0xfe00707f +#define MATCH_PKBB16 0xe001077 +#define MASK_PKBB16 0xfe00707f +#define MATCH_PKBB32 0xe002077 +#define MASK_PKBB32 0xfe00707f +#define MATCH_PKBT16 0x1e001077 +#define MASK_PKBT16 0xfe00707f +#define MATCH_PKBT32 0x1e002077 +#define MASK_PKBT32 0xfe00707f +#define MATCH_PKTB16 0x3e001077 +#define MASK_PKTB16 0xfe00707f +#define MATCH_PKTB32 0x3e002077 +#define MASK_PKTB32 0xfe00707f +#define MATCH_PKTT16 0x2e001077 +#define MASK_PKTT16 0xfe00707f +#define MATCH_PKTT32 0x2e002077 +#define MASK_PKTT32 0xfe00707f +#define MATCH_PREFETCH_I 0x6013 +#define MASK_PREFETCH_I 0x1f07fff +#define MATCH_PREFETCH_R 0x106013 +#define MASK_PREFETCH_R 0x1f07fff +#define MATCH_PREFETCH_W 0x306013 +#define MASK_PREFETCH_W 0x1f07fff +#define MATCH_RADD16 0x77 +#define MASK_RADD16 0xfe00707f +#define MATCH_RADD32 0x2077 +#define MASK_RADD32 0xfe00707f +#define MATCH_RADD64 0x80001077 +#define MASK_RADD64 0xfe00707f +#define MATCH_RADD8 0x8000077 +#define MASK_RADD8 0xfe00707f +#define MATCH_RADDW 0x20001077 +#define MASK_RADDW 0xfe00707f +#define MATCH_RCRAS16 0x4000077 +#define MASK_RCRAS16 0xfe00707f +#define MATCH_RCRAS32 0x4002077 +#define MASK_RCRAS32 0xfe00707f +#define MATCH_RCRSA16 0x6000077 +#define MASK_RCRSA16 0xfe00707f +#define MATCH_RCRSA32 0x6002077 +#define MASK_RCRSA32 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_ROL 0x60001033 +#define MASK_ROL 0xfe00707f +#define MATCH_ROLW 0x6000103b +#define MASK_ROLW 0xfe00707f +#define MATCH_ROR 0x60005033 +#define MASK_ROR 0xfe00707f +#define MATCH_RORI 0x60005013 +#define MASK_RORI 0xfc00707f +#define MATCH_RORIW 0x6000501b +#define MASK_RORIW 0xfe00707f +#define MATCH_RORW 0x6000503b +#define MASK_RORW 0xfe00707f +#define MATCH_RSTAS16 0xb4002077 +#define MASK_RSTAS16 0xfe00707f +#define MATCH_RSTAS32 0xb0002077 +#define MASK_RSTAS32 0xfe00707f +#define MATCH_RSTSA16 0xb6002077 +#define MASK_RSTSA16 0xfe00707f +#define MATCH_RSTSA32 0xb2002077 +#define MASK_RSTSA32 0xfe00707f +#define MATCH_RSUB16 0x2000077 +#define MASK_RSUB16 0xfe00707f +#define MATCH_RSUB32 0x2002077 +#define MASK_RSUB32 0xfe00707f +#define MATCH_RSUB64 0x82001077 +#define MASK_RSUB64 0xfe00707f +#define MATCH_RSUB8 0xa000077 +#define MASK_RSUB8 0xfe00707f +#define MATCH_RSUBW 0x22001077 +#define MASK_RSUBW 0xfe00707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_SCLIP16 0x84000077 +#define MASK_SCLIP16 0xff00707f +#define MATCH_SCLIP32 0xe4000077 +#define MASK_SCLIP32 0xfe00707f +#define MATCH_SCLIP8 0x8c000077 +#define MASK_SCLIP8 0xff80707f +#define MATCH_SCMPLE16 0x1c000077 +#define MASK_SCMPLE16 0xfe00707f +#define MATCH_SCMPLE8 0x1e000077 +#define MASK_SCMPLE8 0xfe00707f +#define MATCH_SCMPLT16 0xc000077 +#define MASK_SCMPLT16 0xfe00707f +#define MATCH_SCMPLT8 0xe000077 +#define MASK_SCMPLT8 0xfe00707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_SEXT_B 0x60401013 +#define MASK_SEXT_B 0xfff0707f +#define MATCH_SEXT_H 0x60501013 +#define MASK_SEXT_H 0xfff0707f +#define MATCH_SFENCE_INVAL_IR 0x18100073 +#define MASK_SFENCE_INVAL_IR 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_SFENCE_W_INVAL 0x18000073 +#define MASK_SFENCE_W_INVAL 0xffffffff +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SH1ADD 0x20002033 +#define MASK_SH1ADD 0xfe00707f +#define MATCH_SH1ADD_UW 0x2000203b +#define MASK_SH1ADD_UW 0xfe00707f +#define MATCH_SH2ADD 0x20004033 +#define MASK_SH2ADD 0xfe00707f +#define MATCH_SH2ADD_UW 0x2000403b +#define MASK_SH2ADD_UW 0xfe00707f +#define MATCH_SH3ADD 0x20006033 +#define MASK_SH3ADD 0xfe00707f +#define MATCH_SH3ADD_UW 0x2000603b +#define MASK_SH3ADD_UW 0xfe00707f +#define MATCH_SHA256SIG0 0x10201013 +#define MASK_SHA256SIG0 0xfff0707f +#define MATCH_SHA256SIG1 0x10301013 +#define MASK_SHA256SIG1 0xfff0707f +#define MATCH_SHA256SUM0 0x10001013 +#define MASK_SHA256SUM0 0xfff0707f +#define MATCH_SHA256SUM1 0x10101013 +#define MASK_SHA256SUM1 0xfff0707f +#define MATCH_SHA512SIG0 0x10601013 +#define MASK_SHA512SIG0 0xfff0707f +#define MATCH_SHA512SIG0H 0x5c000033 +#define MASK_SHA512SIG0H 0xfe00707f +#define MATCH_SHA512SIG0L 0x54000033 +#define MASK_SHA512SIG0L 0xfe00707f +#define MATCH_SHA512SIG1 0x10701013 +#define MASK_SHA512SIG1 0xfff0707f +#define MATCH_SHA512SIG1H 0x5e000033 +#define MASK_SHA512SIG1H 0xfe00707f +#define MATCH_SHA512SIG1L 0x56000033 +#define MASK_SHA512SIG1L 0xfe00707f +#define MATCH_SHA512SUM0 0x10401013 +#define MASK_SHA512SUM0 0xfff0707f +#define MATCH_SHA512SUM0R 0x50000033 +#define MASK_SHA512SUM0R 0xfe00707f +#define MATCH_SHA512SUM1 0x10501013 +#define MASK_SHA512SUM1 0xfff0707f +#define MATCH_SHA512SUM1R 0x52000033 +#define MASK_SHA512SUM1R 0xfe00707f +#define MATCH_SHFL 0x8001033 +#define MASK_SHFL 0xfe00707f +#define MATCH_SHFLI 0x8001013 +#define MASK_SHFLI 0xfe00707f +#define MATCH_SHFLW 0x800103b +#define MASK_SHFLW 0xfe00707f +#define MATCH_SINVAL_VMA 0x16000073 +#define MASK_SINVAL_VMA 0xfe007fff +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLL16 0x54000077 +#define MASK_SLL16 0xfe00707f +#define MATCH_SLL32 0x54002077 +#define MASK_SLL32 0xfe00707f +#define MATCH_SLL8 0x5c000077 +#define MASK_SLL8 0xfe00707f +#define MATCH_SLLD 0x107b +#define MASK_SLLD 0xfe00707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xf800707f +#define MATCH_SLLI16 0x74000077 +#define MASK_SLLI16 0xff00707f +#define MATCH_SLLI32 0x74002077 +#define MASK_SLLI32 0xfe00707f +#define MATCH_SLLI8 0x7c000077 +#define MASK_SLLI8 0xff80707f +#define MATCH_SLLI_UW 0x800101b +#define MASK_SLLI_UW 0xfc00707f +#define MATCH_SLLID 0x105b +#define MASK_SLLID 0xfc00707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SLO 0x20001033 +#define MASK_SLO 0xfe00707f +#define MATCH_SLOI 0x20001013 +#define MASK_SLOI 0xfc00707f +#define MATCH_SLOIW 0x2000101b +#define MASK_SLOIW 0xfe00707f +#define MATCH_SLOW 0x2000103b +#define MASK_SLOW 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_SM3P0 0x10801013 +#define MASK_SM3P0 0xfff0707f +#define MATCH_SM3P1 0x10901013 +#define MASK_SM3P1 0xfff0707f +#define MATCH_SM4ED 0x30000033 +#define MASK_SM4ED 0x3e00707f +#define MATCH_SM4KS 0x34000033 +#define MASK_SM4KS 0x3e00707f +#define MATCH_SMAL 0x5e001077 +#define MASK_SMAL 0xfe00707f +#define MATCH_SMALBB 0x88001077 +#define MASK_SMALBB 0xfe00707f +#define MATCH_SMALBT 0x98001077 +#define MASK_SMALBT 0xfe00707f +#define MATCH_SMALDA 0x8c001077 +#define MASK_SMALDA 0xfe00707f +#define MATCH_SMALDRS 0x9a001077 +#define MASK_SMALDRS 0xfe00707f +#define MATCH_SMALDS 0x8a001077 +#define MASK_SMALDS 0xfe00707f +#define MATCH_SMALTT 0xa8001077 +#define MASK_SMALTT 0xfe00707f +#define MATCH_SMALXDA 0x9c001077 +#define MASK_SMALXDA 0xfe00707f +#define MATCH_SMALXDS 0xaa001077 +#define MASK_SMALXDS 0xfe00707f +#define MATCH_SMAQA 0xc8000077 +#define MASK_SMAQA 0xfe00707f +#define MATCH_SMAQA_SU 0xca000077 +#define MASK_SMAQA_SU 0xfe00707f +#define MATCH_SMAR64 0x84001077 +#define MASK_SMAR64 0xfe00707f +#define MATCH_SMAX16 0x82000077 +#define MASK_SMAX16 0xfe00707f +#define MATCH_SMAX32 0x92002077 +#define MASK_SMAX32 0xfe00707f +#define MATCH_SMAX8 0x8a000077 +#define MASK_SMAX8 0xfe00707f +#define MATCH_SMBB16 0x8001077 +#define MASK_SMBB16 0xfe00707f +#define MATCH_SMBT16 0x18001077 +#define MASK_SMBT16 0xfe00707f +#define MATCH_SMBT32 0x18002077 +#define MASK_SMBT32 0xfe00707f +#define MATCH_SMDRS 0x68001077 +#define MASK_SMDRS 0xfe00707f +#define MATCH_SMDRS32 0x68002077 +#define MASK_SMDRS32 0xfe00707f +#define MATCH_SMDS 0x58001077 +#define MASK_SMDS 0xfe00707f +#define MATCH_SMDS32 0x58002077 +#define MASK_SMDS32 0xfe00707f +#define MATCH_SMIN16 0x80000077 +#define MASK_SMIN16 0xfe00707f +#define MATCH_SMIN32 0x90002077 +#define MASK_SMIN32 0xfe00707f +#define MATCH_SMIN8 0x88000077 +#define MASK_SMIN8 0xfe00707f +#define MATCH_SMMUL 0x40001077 +#define MASK_SMMUL 0xfe00707f +#define MATCH_SMMUL_U 0x50001077 +#define MASK_SMMUL_U 0xfe00707f +#define MATCH_SMMWB 0x44001077 +#define MASK_SMMWB 0xfe00707f +#define MATCH_SMMWB_U 0x54001077 +#define MASK_SMMWB_U 0xfe00707f +#define MATCH_SMMWT 0x64001077 +#define MASK_SMMWT 0xfe00707f +#define MATCH_SMMWT_U 0x74001077 +#define MASK_SMMWT_U 0xfe00707f +#define MATCH_SMSLDA 0xac001077 +#define MASK_SMSLDA 0xfe00707f +#define MATCH_SMSLXDA 0xbc001077 +#define MASK_SMSLXDA 0xfe00707f +#define MATCH_SMSR64 0x86001077 +#define MASK_SMSR64 0xfe00707f +#define MATCH_SMTT16 0x28001077 +#define MASK_SMTT16 0xfe00707f +#define MATCH_SMTT32 0x28002077 +#define MASK_SMTT32 0xfe00707f +#define MATCH_SMUL16 0xa0000077 +#define MASK_SMUL16 0xfe00707f +#define MATCH_SMUL8 0xa8000077 +#define MASK_SMUL8 0xfe00707f +#define MATCH_SMULX16 0xa2000077 +#define MASK_SMULX16 0xfe00707f +#define MATCH_SMULX8 0xaa000077 +#define MASK_SMULX8 0xfe00707f +#define MATCH_SMXDS 0x78001077 +#define MASK_SMXDS 0xfe00707f +#define MATCH_SMXDS32 0x78002077 +#define MASK_SMXDS32 0xfe00707f +#define MATCH_SQ 0x4023 +#define MASK_SQ 0x707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_SRA16 0x50000077 +#define MASK_SRA16 0xfe00707f +#define MATCH_SRA16_U 0x60000077 +#define MASK_SRA16_U 0xfe00707f +#define MATCH_SRA32 0x50002077 +#define MASK_SRA32 0xfe00707f +#define MATCH_SRA32_U 0x60002077 +#define MASK_SRA32_U 0xfe00707f +#define MATCH_SRA8 0x58000077 +#define MASK_SRA8 0xfe00707f +#define MATCH_SRA8_U 0x68000077 +#define MASK_SRA8_U 0xfe00707f +#define MATCH_SRA_U 0x24001077 +#define MASK_SRA_U 0xfe00707f +#define MATCH_SRAD 0x4000507b +#define MASK_SRAD 0xfe00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xf800707f +#define MATCH_SRAI16 0x70000077 +#define MASK_SRAI16 0xff00707f +#define MATCH_SRAI16_U 0x71000077 +#define MASK_SRAI16_U 0xff00707f +#define MATCH_SRAI32 0x70002077 +#define MASK_SRAI32 0xfe00707f +#define MATCH_SRAI32_U 0x80002077 +#define MASK_SRAI32_U 0xfe00707f +#define MATCH_SRAI8 0x78000077 +#define MASK_SRAI8 0xff80707f +#define MATCH_SRAI8_U 0x78800077 +#define MASK_SRAI8_U 0xff80707f +#define MATCH_SRAI_U 0xd4001077 +#define MASK_SRAI_U 0xfc00707f +#define MATCH_SRAID 0x4000505b +#define MASK_SRAID 0xfc00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_SRAIW_U 0x34001077 +#define MASK_SRAIW_U 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRL16 0x52000077 +#define MASK_SRL16 0xfe00707f +#define MATCH_SRL16_U 0x62000077 +#define MASK_SRL16_U 0xfe00707f +#define MATCH_SRL32 0x52002077 +#define MASK_SRL32 0xfe00707f +#define MATCH_SRL32_U 0x62002077 +#define MASK_SRL32_U 0xfe00707f +#define MATCH_SRL8 0x5a000077 +#define MASK_SRL8 0xfe00707f +#define MATCH_SRL8_U 0x6a000077 +#define MASK_SRL8_U 0xfe00707f +#define MATCH_SRLD 0x507b +#define MASK_SRLD 0xfe00707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xf800707f +#define MATCH_SRLI16 0x72000077 +#define MASK_SRLI16 0xff00707f +#define MATCH_SRLI16_U 0x73000077 +#define MASK_SRLI16_U 0xff00707f +#define MATCH_SRLI32 0x72002077 +#define MASK_SRLI32 0xfe00707f +#define MATCH_SRLI32_U 0x82002077 +#define MASK_SRLI32_U 0xfe00707f +#define MATCH_SRLI8 0x7a000077 +#define MASK_SRLI8 0xff80707f +#define MATCH_SRLI8_U 0x7a800077 +#define MASK_SRLI8_U 0xff80707f +#define MATCH_SRLID 0x505b +#define MASK_SRLID 0xfc00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRO 0x20005033 +#define MASK_SRO 0xfe00707f +#define MATCH_SROI 0x20005013 +#define MASK_SROI 0xfc00707f +#define MATCH_SROIW 0x2000501b +#define MASK_SROIW 0xfe00707f +#define MATCH_SROW 0x2000503b +#define MASK_SROW 0xfe00707f +#define MATCH_STAS16 0xf4002077 +#define MASK_STAS16 0xfe00707f +#define MATCH_STAS32 0xf0002077 +#define MASK_STAS32 0xfe00707f +#define MATCH_STSA16 0xf6002077 +#define MASK_STSA16 0xfe00707f +#define MATCH_STSA32 0xf2002077 +#define MASK_STSA32 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SUB16 0x42000077 +#define MASK_SUB16 0xfe00707f +#define MATCH_SUB32 0x42002077 +#define MASK_SUB32 0xfe00707f +#define MATCH_SUB64 0xc2001077 +#define MASK_SUB64 0xfe00707f +#define MATCH_SUB8 0x4a000077 +#define MASK_SUB8 0xfe00707f +#define MATCH_SUBD 0x4000007b +#define MASK_SUBD 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SUNPKD810 0xac800077 +#define MASK_SUNPKD810 0xfff0707f +#define MATCH_SUNPKD820 0xac900077 +#define MASK_SUNPKD820 0xfff0707f +#define MATCH_SUNPKD830 0xaca00077 +#define MASK_SUNPKD830 0xfff0707f +#define MATCH_SUNPKD831 0xacb00077 +#define MASK_SUNPKD831 0xfff0707f +#define MATCH_SUNPKD832 0xad300077 +#define MASK_SUNPKD832 0xfff0707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SWAP8 0xad800077 +#define MASK_SWAP8 0xfff0707f +#define MATCH_UCLIP16 0x85000077 +#define MASK_UCLIP16 0xff00707f +#define MATCH_UCLIP32 0xf4000077 +#define MASK_UCLIP32 0xfe00707f +#define MATCH_UCLIP8 0x8d000077 +#define MASK_UCLIP8 0xff80707f +#define MATCH_UCMPLE16 0x3c000077 +#define MASK_UCMPLE16 0xfe00707f +#define MATCH_UCMPLE8 0x3e000077 +#define MASK_UCMPLE8 0xfe00707f +#define MATCH_UCMPLT16 0x2c000077 +#define MASK_UCMPLT16 0xfe00707f +#define MATCH_UCMPLT8 0x2e000077 +#define MASK_UCMPLT8 0xfe00707f +#define MATCH_UKADD16 0x30000077 +#define MASK_UKADD16 0xfe00707f +#define MATCH_UKADD32 0x30002077 +#define MASK_UKADD32 0xfe00707f +#define MATCH_UKADD64 0xb0001077 +#define MASK_UKADD64 0xfe00707f +#define MATCH_UKADD8 0x38000077 +#define MASK_UKADD8 0xfe00707f +#define MATCH_UKADDH 0x14001077 +#define MASK_UKADDH 0xfe00707f +#define MATCH_UKADDW 0x10001077 +#define MASK_UKADDW 0xfe00707f +#define MATCH_UKCRAS16 0x34000077 +#define MASK_UKCRAS16 0xfe00707f +#define MATCH_UKCRAS32 0x34002077 +#define MASK_UKCRAS32 0xfe00707f +#define MATCH_UKCRSA16 0x36000077 +#define MASK_UKCRSA16 0xfe00707f +#define MATCH_UKCRSA32 0x36002077 +#define MASK_UKCRSA32 0xfe00707f +#define MATCH_UKMAR64 0xb4001077 +#define MASK_UKMAR64 0xfe00707f +#define MATCH_UKMSR64 0xb6001077 +#define MASK_UKMSR64 0xfe00707f +#define MATCH_UKSTAS16 0xe4002077 +#define MASK_UKSTAS16 0xfe00707f +#define MATCH_UKSTAS32 0xe0002077 +#define MASK_UKSTAS32 0xfe00707f +#define MATCH_UKSTSA16 0xe6002077 +#define MASK_UKSTSA16 0xfe00707f +#define MATCH_UKSTSA32 0xe2002077 +#define MASK_UKSTSA32 0xfe00707f +#define MATCH_UKSUB16 0x32000077 +#define MASK_UKSUB16 0xfe00707f +#define MATCH_UKSUB32 0x32002077 +#define MASK_UKSUB32 0xfe00707f +#define MATCH_UKSUB64 0xb2001077 +#define MASK_UKSUB64 0xfe00707f +#define MATCH_UKSUB8 0x3a000077 +#define MASK_UKSUB8 0xfe00707f +#define MATCH_UKSUBH 0x16001077 +#define MASK_UKSUBH 0xfe00707f +#define MATCH_UKSUBW 0x12001077 +#define MASK_UKSUBW 0xfe00707f +#define MATCH_UMAQA 0xcc000077 +#define MASK_UMAQA 0xfe00707f +#define MATCH_UMAR64 0xa4001077 +#define MASK_UMAR64 0xfe00707f +#define MATCH_UMAX16 0x92000077 +#define MASK_UMAX16 0xfe00707f +#define MATCH_UMAX32 0xa2002077 +#define MASK_UMAX32 0xfe00707f +#define MATCH_UMAX8 0x9a000077 +#define MASK_UMAX8 0xfe00707f +#define MATCH_UMIN16 0x90000077 +#define MASK_UMIN16 0xfe00707f +#define MATCH_UMIN32 0xa0002077 +#define MASK_UMIN32 0xfe00707f +#define MATCH_UMIN8 0x98000077 +#define MASK_UMIN8 0xfe00707f +#define MATCH_UMSR64 0xa6001077 +#define MASK_UMSR64 0xfe00707f +#define MATCH_UMUL16 0xb0000077 +#define MASK_UMUL16 0xfe00707f +#define MATCH_UMUL8 0xb8000077 +#define MASK_UMUL8 0xfe00707f +#define MATCH_UMULX16 0xb2000077 +#define MASK_UMULX16 0xfe00707f +#define MATCH_UMULX8 0xba000077 +#define MASK_UMULX8 0xfe00707f +#define MATCH_UNSHFL 0x8005033 +#define MASK_UNSHFL 0xfe00707f +#define MATCH_UNSHFLI 0x8005013 +#define MASK_UNSHFLI 0xfe00707f +#define MATCH_UNSHFLW 0x800503b +#define MASK_UNSHFLW 0xfe00707f +#define MATCH_URADD16 0x20000077 +#define MASK_URADD16 0xfe00707f +#define MATCH_URADD32 0x20002077 +#define MASK_URADD32 0xfe00707f +#define MATCH_URADD64 0xa0001077 +#define MASK_URADD64 0xfe00707f +#define MATCH_URADD8 0x28000077 +#define MASK_URADD8 0xfe00707f +#define MATCH_URADDW 0x30001077 +#define MASK_URADDW 0xfe00707f +#define MATCH_URCRAS16 0x24000077 +#define MASK_URCRAS16 0xfe00707f +#define MATCH_URCRAS32 0x24002077 +#define MASK_URCRAS32 0xfe00707f +#define MATCH_URCRSA16 0x26000077 +#define MASK_URCRSA16 0xfe00707f +#define MATCH_URCRSA32 0x26002077 +#define MASK_URCRSA32 0xfe00707f +#define MATCH_URSTAS16 0xd4002077 +#define MASK_URSTAS16 0xfe00707f +#define MATCH_URSTAS32 0xd0002077 +#define MASK_URSTAS32 0xfe00707f +#define MATCH_URSTSA16 0xd6002077 +#define MASK_URSTSA16 0xfe00707f +#define MATCH_URSTSA32 0xd2002077 +#define MASK_URSTSA32 0xfe00707f +#define MATCH_URSUB16 0x22000077 +#define MASK_URSUB16 0xfe00707f +#define MATCH_URSUB32 0x22002077 +#define MASK_URSUB32 0xfe00707f +#define MATCH_URSUB64 0xa2001077 +#define MASK_URSUB64 0xfe00707f +#define MATCH_URSUB8 0x2a000077 +#define MASK_URSUB8 0xfe00707f +#define MATCH_URSUBW 0x32001077 +#define MASK_URSUBW 0xfe00707f +#define MATCH_VAADD_VV 0x24002057 +#define MASK_VAADD_VV 0xfc00707f +#define MATCH_VAADD_VX 0x24006057 +#define MASK_VAADD_VX 0xfc00707f +#define MATCH_VAADDU_VV 0x20002057 +#define MASK_VAADDU_VV 0xfc00707f +#define MATCH_VAADDU_VX 0x20006057 +#define MASK_VAADDU_VX 0xfc00707f +#define MATCH_VADC_VIM 0x40003057 +#define MASK_VADC_VIM 0xfe00707f +#define MATCH_VADC_VVM 0x40000057 +#define MASK_VADC_VVM 0xfe00707f +#define MATCH_VADC_VXM 0x40004057 +#define MASK_VADC_VXM 0xfe00707f +#define MATCH_VADD_VI 0x3057 +#define MASK_VADD_VI 0xfc00707f +#define MATCH_VADD_VV 0x57 +#define MASK_VADD_VV 0xfc00707f +#define MATCH_VADD_VX 0x4057 +#define MASK_VADD_VX 0xfc00707f +#define MATCH_VAMOADDEI16_V 0x502f +#define MASK_VAMOADDEI16_V 0xf800707f +#define MATCH_VAMOADDEI32_V 0x602f +#define MASK_VAMOADDEI32_V 0xf800707f +#define MATCH_VAMOADDEI64_V 0x702f +#define MASK_VAMOADDEI64_V 0xf800707f +#define MATCH_VAMOADDEI8_V 0x2f +#define MASK_VAMOADDEI8_V 0xf800707f +#define MATCH_VAMOANDEI16_V 0x6000502f +#define MASK_VAMOANDEI16_V 0xf800707f +#define MATCH_VAMOANDEI32_V 0x6000602f +#define MASK_VAMOANDEI32_V 0xf800707f +#define MATCH_VAMOANDEI64_V 0x6000702f +#define MASK_VAMOANDEI64_V 0xf800707f +#define MATCH_VAMOANDEI8_V 0x6000002f +#define MASK_VAMOANDEI8_V 0xf800707f +#define MATCH_VAMOMAXEI16_V 0xa000502f +#define MASK_VAMOMAXEI16_V 0xf800707f +#define MATCH_VAMOMAXEI32_V 0xa000602f +#define MASK_VAMOMAXEI32_V 0xf800707f +#define MATCH_VAMOMAXEI64_V 0xa000702f +#define MASK_VAMOMAXEI64_V 0xf800707f +#define MATCH_VAMOMAXEI8_V 0xa000002f +#define MASK_VAMOMAXEI8_V 0xf800707f +#define MATCH_VAMOMAXUEI16_V 0xe000502f +#define MASK_VAMOMAXUEI16_V 0xf800707f +#define MATCH_VAMOMAXUEI32_V 0xe000602f +#define MASK_VAMOMAXUEI32_V 0xf800707f +#define MATCH_VAMOMAXUEI64_V 0xe000702f +#define MASK_VAMOMAXUEI64_V 0xf800707f +#define MATCH_VAMOMAXUEI8_V 0xe000002f +#define MASK_VAMOMAXUEI8_V 0xf800707f +#define MATCH_VAMOMINEI16_V 0x8000502f +#define MASK_VAMOMINEI16_V 0xf800707f +#define MATCH_VAMOMINEI32_V 0x8000602f +#define MASK_VAMOMINEI32_V 0xf800707f +#define MATCH_VAMOMINEI64_V 0x8000702f +#define MASK_VAMOMINEI64_V 0xf800707f +#define MATCH_VAMOMINEI8_V 0x8000002f +#define MASK_VAMOMINEI8_V 0xf800707f +#define MATCH_VAMOMINUEI16_V 0xc000502f +#define MASK_VAMOMINUEI16_V 0xf800707f +#define MATCH_VAMOMINUEI32_V 0xc000602f +#define MASK_VAMOMINUEI32_V 0xf800707f +#define MATCH_VAMOMINUEI64_V 0xc000702f +#define MASK_VAMOMINUEI64_V 0xf800707f +#define MATCH_VAMOMINUEI8_V 0xc000002f +#define MASK_VAMOMINUEI8_V 0xf800707f +#define MATCH_VAMOOREI16_V 0x4000502f +#define MASK_VAMOOREI16_V 0xf800707f +#define MATCH_VAMOOREI32_V 0x4000602f +#define MASK_VAMOOREI32_V 0xf800707f +#define MATCH_VAMOOREI64_V 0x4000702f +#define MASK_VAMOOREI64_V 0xf800707f +#define MATCH_VAMOOREI8_V 0x4000002f +#define MASK_VAMOOREI8_V 0xf800707f +#define MATCH_VAMOSWAPEI16_V 0x800502f +#define MASK_VAMOSWAPEI16_V 0xf800707f +#define MATCH_VAMOSWAPEI32_V 0x800602f +#define MASK_VAMOSWAPEI32_V 0xf800707f +#define MATCH_VAMOSWAPEI64_V 0x800702f +#define MASK_VAMOSWAPEI64_V 0xf800707f +#define MATCH_VAMOSWAPEI8_V 0x800002f +#define MASK_VAMOSWAPEI8_V 0xf800707f +#define MATCH_VAMOXOREI16_V 0x2000502f +#define MASK_VAMOXOREI16_V 0xf800707f +#define MATCH_VAMOXOREI32_V 0x2000602f +#define MASK_VAMOXOREI32_V 0xf800707f +#define MATCH_VAMOXOREI64_V 0x2000702f +#define MASK_VAMOXOREI64_V 0xf800707f +#define MATCH_VAMOXOREI8_V 0x2000002f +#define MASK_VAMOXOREI8_V 0xf800707f +#define MATCH_VAND_VI 0x24003057 +#define MASK_VAND_VI 0xfc00707f +#define MATCH_VAND_VV 0x24000057 +#define MASK_VAND_VV 0xfc00707f +#define MATCH_VAND_VX 0x24004057 +#define MASK_VAND_VX 0xfc00707f +#define MATCH_VASUB_VV 0x2c002057 +#define MASK_VASUB_VV 0xfc00707f +#define MATCH_VASUB_VX 0x2c006057 +#define MASK_VASUB_VX 0xfc00707f +#define MATCH_VASUBU_VV 0x28002057 +#define MASK_VASUBU_VV 0xfc00707f +#define MATCH_VASUBU_VX 0x28006057 +#define MASK_VASUBU_VX 0xfc00707f +#define MATCH_VCOMPRESS_VM 0x5e002057 +#define MASK_VCOMPRESS_VM 0xfe00707f +#define MATCH_VCPOP_M 0x40082057 +#define MASK_VCPOP_M 0xfc0ff07f +#define MATCH_VDIV_VV 0x84002057 +#define MASK_VDIV_VV 0xfc00707f +#define MATCH_VDIV_VX 0x84006057 +#define MASK_VDIV_VX 0xfc00707f +#define MATCH_VDIVU_VV 0x80002057 +#define MASK_VDIVU_VV 0xfc00707f +#define MATCH_VDIVU_VX 0x80006057 +#define MASK_VDIVU_VX 0xfc00707f +#define MATCH_VFADD_VF 0x5057 +#define MASK_VFADD_VF 0xfc00707f +#define MATCH_VFADD_VV 0x1057 +#define MASK_VFADD_VV 0xfc00707f +#define MATCH_VFCLASS_V 0x4c081057 +#define MASK_VFCLASS_V 0xfc0ff07f +#define MATCH_VFCVT_F_X_V 0x48019057 +#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_F_XU_V 0x48011057 +#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_X_F_V 0x48009057 +#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_XU_F_V 0x48001057 +#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFDIV_VF 0x80005057 +#define MASK_VFDIV_VF 0xfc00707f +#define MATCH_VFDIV_VV 0x80001057 +#define MASK_VFDIV_VV 0xfc00707f +#define MATCH_VFIRST_M 0x4008a057 +#define MASK_VFIRST_M 0xfc0ff07f +#define MATCH_VFMACC_VF 0xb0005057 +#define MASK_VFMACC_VF 0xfc00707f +#define MATCH_VFMACC_VV 0xb0001057 +#define MASK_VFMACC_VV 0xfc00707f +#define MATCH_VFMADD_VF 0xa0005057 +#define MASK_VFMADD_VF 0xfc00707f +#define MATCH_VFMADD_VV 0xa0001057 +#define MASK_VFMADD_VV 0xfc00707f +#define MATCH_VFMAX_VF 0x18005057 +#define MASK_VFMAX_VF 0xfc00707f +#define MATCH_VFMAX_VV 0x18001057 +#define MASK_VFMAX_VV 0xfc00707f +#define MATCH_VFMERGE_VFM 0x5c005057 +#define MASK_VFMERGE_VFM 0xfe00707f +#define MATCH_VFMIN_VF 0x10005057 +#define MASK_VFMIN_VF 0xfc00707f +#define MATCH_VFMIN_VV 0x10001057 +#define MASK_VFMIN_VV 0xfc00707f +#define MATCH_VFMSAC_VF 0xb8005057 +#define MASK_VFMSAC_VF 0xfc00707f +#define MATCH_VFMSAC_VV 0xb8001057 +#define MASK_VFMSAC_VV 0xfc00707f +#define MATCH_VFMSUB_VF 0xa8005057 +#define MASK_VFMSUB_VF 0xfc00707f +#define MATCH_VFMSUB_VV 0xa8001057 +#define MASK_VFMSUB_VV 0xfc00707f +#define MATCH_VFMUL_VF 0x90005057 +#define MASK_VFMUL_VF 0xfc00707f +#define MATCH_VFMUL_VV 0x90001057 +#define MASK_VFMUL_VV 0xfc00707f +#define MATCH_VFMV_F_S 0x42001057 +#define MASK_VFMV_F_S 0xfe0ff07f +#define MATCH_VFMV_S_F 0x42005057 +#define MASK_VFMV_S_F 0xfff0707f +#define MATCH_VFMV_V_F 0x5e005057 +#define MASK_VFMV_V_F 0xfff0707f +#define MATCH_VFNCVT_F_F_W 0x480a1057 +#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_F_X_W 0x48099057 +#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MATCH_VFNCVT_F_XU_W 0x48091057 +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_X_F_W 0x48089057 +#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_XU_F_W 0x48081057 +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MATCH_VFNMACC_VF 0xb4005057 +#define MASK_VFNMACC_VF 0xfc00707f +#define MATCH_VFNMACC_VV 0xb4001057 +#define MASK_VFNMACC_VV 0xfc00707f +#define MATCH_VFNMADD_VF 0xa4005057 +#define MASK_VFNMADD_VF 0xfc00707f +#define MATCH_VFNMADD_VV 0xa4001057 +#define MASK_VFNMADD_VV 0xfc00707f +#define MATCH_VFNMSAC_VF 0xbc005057 +#define MASK_VFNMSAC_VF 0xfc00707f +#define MATCH_VFNMSAC_VV 0xbc001057 +#define MASK_VFNMSAC_VV 0xfc00707f +#define MATCH_VFNMSUB_VF 0xac005057 +#define MASK_VFNMSUB_VF 0xfc00707f +#define MATCH_VFNMSUB_VV 0xac001057 +#define MASK_VFNMSUB_VV 0xfc00707f +#define MATCH_VFRDIV_VF 0x84005057 +#define MASK_VFRDIV_VF 0xfc00707f +#define MATCH_VFREC7_V 0x4c029057 +#define MASK_VFREC7_V 0xfc0ff07f +#define MATCH_VFREDMAX_VS 0x1c001057 +#define MASK_VFREDMAX_VS 0xfc00707f +#define MATCH_VFREDMIN_VS 0x14001057 +#define MASK_VFREDMIN_VS 0xfc00707f +#define MATCH_VFREDOSUM_VS 0xc001057 +#define MASK_VFREDOSUM_VS 0xfc00707f +#define MATCH_VFREDUSUM_VS 0x4001057 +#define MASK_VFREDUSUM_VS 0xfc00707f +#define MATCH_VFRSQRT7_V 0x4c021057 +#define MASK_VFRSQRT7_V 0xfc0ff07f +#define MATCH_VFRSUB_VF 0x9c005057 +#define MASK_VFRSUB_VF 0xfc00707f +#define MATCH_VFSGNJ_VF 0x20005057 +#define MASK_VFSGNJ_VF 0xfc00707f +#define MATCH_VFSGNJ_VV 0x20001057 +#define MASK_VFSGNJ_VV 0xfc00707f +#define MATCH_VFSGNJN_VF 0x24005057 +#define MASK_VFSGNJN_VF 0xfc00707f +#define MATCH_VFSGNJN_VV 0x24001057 +#define MASK_VFSGNJN_VV 0xfc00707f +#define MATCH_VFSGNJX_VF 0x28005057 +#define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSGNJX_VV 0x28001057 +#define MASK_VFSGNJX_VV 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSQRT_V 0x4c001057 +#define MASK_VFSQRT_V 0xfc0ff07f +#define MATCH_VFSUB_VF 0x8005057 +#define MASK_VFSUB_VF 0xfc00707f +#define MATCH_VFSUB_VV 0x8001057 +#define MASK_VFSUB_VV 0xfc00707f +#define MATCH_VFWADD_VF 0xc0005057 +#define MASK_VFWADD_VF 0xfc00707f +#define MATCH_VFWADD_VV 0xc0001057 +#define MASK_VFWADD_VV 0xfc00707f +#define MATCH_VFWADD_WF 0xd0005057 +#define MASK_VFWADD_WF 0xfc00707f +#define MATCH_VFWADD_WV 0xd0001057 +#define MASK_VFWADD_WV 0xfc00707f +#define MATCH_VFWCVT_F_F_V 0x48061057 +#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_F_X_V 0x48059057 +#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MATCH_VFWCVT_F_XU_V 0x48051057 +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_X_F_V 0x48049057 +#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_XU_F_V 0x48041057 +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFWMACC_VF 0xf0005057 +#define MASK_VFWMACC_VF 0xfc00707f +#define MATCH_VFWMACC_VV 0xf0001057 +#define MASK_VFWMACC_VV 0xfc00707f +#define MATCH_VFWMSAC_VF 0xf8005057 +#define MASK_VFWMSAC_VF 0xfc00707f +#define MATCH_VFWMSAC_VV 0xf8001057 +#define MASK_VFWMSAC_VV 0xfc00707f +#define MATCH_VFWMUL_VF 0xe0005057 +#define MASK_VFWMUL_VF 0xfc00707f +#define MATCH_VFWMUL_VV 0xe0001057 +#define MASK_VFWMUL_VV 0xfc00707f +#define MATCH_VFWNMACC_VF 0xf4005057 +#define MASK_VFWNMACC_VF 0xfc00707f +#define MATCH_VFWNMACC_VV 0xf4001057 +#define MASK_VFWNMACC_VV 0xfc00707f +#define MATCH_VFWNMSAC_VF 0xfc005057 +#define MASK_VFWNMSAC_VF 0xfc00707f +#define MATCH_VFWNMSAC_VV 0xfc001057 +#define MASK_VFWNMSAC_VV 0xfc00707f +#define MATCH_VFWREDOSUM_VS 0xcc001057 +#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MATCH_VFWREDUSUM_VS 0xc4001057 +#define MASK_VFWREDUSUM_VS 0xfc00707f +#define MATCH_VFWSUB_VF 0xc8005057 +#define MASK_VFWSUB_VF 0xfc00707f +#define MATCH_VFWSUB_VV 0xc8001057 +#define MASK_VFWSUB_VV 0xfc00707f +#define MATCH_VFWSUB_WF 0xd8005057 +#define MASK_VFWSUB_WF 0xfc00707f +#define MATCH_VFWSUB_WV 0xd8001057 +#define MASK_VFWSUB_WV 0xfc00707f +#define MATCH_VID_V 0x5008a057 +#define MASK_VID_V 0xfdfff07f +#define MATCH_VIOTA_M 0x50082057 +#define MASK_VIOTA_M 0xfc0ff07f +#define MATCH_VL1RE16_V 0x2805007 +#define MASK_VL1RE16_V 0xfff0707f +#define MATCH_VL1RE32_V 0x2806007 +#define MASK_VL1RE32_V 0xfff0707f +#define MATCH_VL1RE64_V 0x2807007 +#define MASK_VL1RE64_V 0xfff0707f +#define MATCH_VL1RE8_V 0x2800007 +#define MASK_VL1RE8_V 0xfff0707f +#define MATCH_VL2RE16_V 0x22805007 +#define MASK_VL2RE16_V 0xfff0707f +#define MATCH_VL2RE32_V 0x22806007 +#define MASK_VL2RE32_V 0xfff0707f +#define MATCH_VL2RE64_V 0x22807007 +#define MASK_VL2RE64_V 0xfff0707f +#define MATCH_VL2RE8_V 0x22800007 +#define MASK_VL2RE8_V 0xfff0707f +#define MATCH_VL4RE16_V 0x62805007 +#define MASK_VL4RE16_V 0xfff0707f +#define MATCH_VL4RE32_V 0x62806007 +#define MASK_VL4RE32_V 0xfff0707f +#define MATCH_VL4RE64_V 0x62807007 +#define MASK_VL4RE64_V 0xfff0707f +#define MATCH_VL4RE8_V 0x62800007 +#define MASK_VL4RE8_V 0xfff0707f +#define MATCH_VL8RE16_V 0xe2805007 +#define MASK_VL8RE16_V 0xfff0707f +#define MATCH_VL8RE32_V 0xe2806007 +#define MASK_VL8RE32_V 0xfff0707f +#define MATCH_VL8RE64_V 0xe2807007 +#define MASK_VL8RE64_V 0xfff0707f +#define MATCH_VL8RE8_V 0xe2800007 +#define MASK_VL8RE8_V 0xfff0707f +#define MATCH_VLE1024_V 0x10007007 +#define MASK_VLE1024_V 0x1df0707f +#define MATCH_VLE1024FF_V 0x11007007 +#define MASK_VLE1024FF_V 0x1df0707f +#define MATCH_VLE128_V 0x10000007 +#define MASK_VLE128_V 0x1df0707f +#define MATCH_VLE128FF_V 0x11000007 +#define MASK_VLE128FF_V 0x1df0707f +#define MATCH_VLE16_V 0x5007 +#define MASK_VLE16_V 0x1df0707f +#define MATCH_VLE16FF_V 0x1005007 +#define MASK_VLE16FF_V 0x1df0707f +#define MATCH_VLE256_V 0x10005007 +#define MASK_VLE256_V 0x1df0707f +#define MATCH_VLE256FF_V 0x11005007 +#define MASK_VLE256FF_V 0x1df0707f +#define MATCH_VLE32_V 0x6007 +#define MASK_VLE32_V 0x1df0707f +#define MATCH_VLE32FF_V 0x1006007 +#define MASK_VLE32FF_V 0x1df0707f +#define MATCH_VLE512_V 0x10006007 +#define MASK_VLE512_V 0x1df0707f +#define MATCH_VLE512FF_V 0x11006007 +#define MASK_VLE512FF_V 0x1df0707f +#define MATCH_VLE64_V 0x7007 +#define MASK_VLE64_V 0x1df0707f +#define MATCH_VLE64FF_V 0x1007007 +#define MASK_VLE64FF_V 0x1df0707f +#define MATCH_VLE8_V 0x7 +#define MASK_VLE8_V 0x1df0707f +#define MATCH_VLE8FF_V 0x1000007 +#define MASK_VLE8FF_V 0x1df0707f +#define MATCH_VLM_V 0x2b00007 +#define MASK_VLM_V 0xfff0707f +#define MATCH_VLOXEI1024_V 0x1c007007 +#define MASK_VLOXEI1024_V 0x1c00707f +#define MATCH_VLOXEI128_V 0x1c000007 +#define MASK_VLOXEI128_V 0x1c00707f +#define MATCH_VLOXEI16_V 0xc005007 +#define MASK_VLOXEI16_V 0x1c00707f +#define MATCH_VLOXEI256_V 0x1c005007 +#define MASK_VLOXEI256_V 0x1c00707f +#define MATCH_VLOXEI32_V 0xc006007 +#define MASK_VLOXEI32_V 0x1c00707f +#define MATCH_VLOXEI512_V 0x1c006007 +#define MASK_VLOXEI512_V 0x1c00707f +#define MATCH_VLOXEI64_V 0xc007007 +#define MASK_VLOXEI64_V 0x1c00707f +#define MATCH_VLOXEI8_V 0xc000007 +#define MASK_VLOXEI8_V 0x1c00707f +#define MATCH_VLSE1024_V 0x18007007 +#define MASK_VLSE1024_V 0x1c00707f +#define MATCH_VLSE128_V 0x18000007 +#define MASK_VLSE128_V 0x1c00707f +#define MATCH_VLSE16_V 0x8005007 +#define MASK_VLSE16_V 0x1c00707f +#define MATCH_VLSE256_V 0x18005007 +#define MASK_VLSE256_V 0x1c00707f +#define MATCH_VLSE32_V 0x8006007 +#define MASK_VLSE32_V 0x1c00707f +#define MATCH_VLSE512_V 0x18006007 +#define MASK_VLSE512_V 0x1c00707f +#define MATCH_VLSE64_V 0x8007007 +#define MASK_VLSE64_V 0x1c00707f +#define MATCH_VLSE8_V 0x8000007 +#define MASK_VLSE8_V 0x1c00707f +#define MATCH_VLUXEI1024_V 0x14007007 +#define MASK_VLUXEI1024_V 0x1c00707f +#define MATCH_VLUXEI128_V 0x14000007 +#define MASK_VLUXEI128_V 0x1c00707f +#define MATCH_VLUXEI16_V 0x4005007 +#define MASK_VLUXEI16_V 0x1c00707f +#define MATCH_VLUXEI256_V 0x14005007 +#define MASK_VLUXEI256_V 0x1c00707f +#define MATCH_VLUXEI32_V 0x4006007 +#define MASK_VLUXEI32_V 0x1c00707f +#define MATCH_VLUXEI512_V 0x14006007 +#define MASK_VLUXEI512_V 0x1c00707f +#define MATCH_VLUXEI64_V 0x4007007 +#define MASK_VLUXEI64_V 0x1c00707f +#define MATCH_VLUXEI8_V 0x4000007 +#define MASK_VLUXEI8_V 0x1c00707f +#define MATCH_VMACC_VV 0xb4002057 +#define MASK_VMACC_VV 0xfc00707f +#define MATCH_VMACC_VX 0xb4006057 +#define MASK_VMACC_VX 0xfc00707f +#define MATCH_VMADC_VI 0x46003057 +#define MASK_VMADC_VI 0xfe00707f +#define MATCH_VMADC_VIM 0x44003057 +#define MASK_VMADC_VIM 0xfe00707f +#define MATCH_VMADC_VV 0x46000057 +#define MASK_VMADC_VV 0xfe00707f +#define MATCH_VMADC_VVM 0x44000057 +#define MASK_VMADC_VVM 0xfe00707f +#define MATCH_VMADC_VX 0x46004057 +#define MASK_VMADC_VX 0xfe00707f +#define MATCH_VMADC_VXM 0x44004057 +#define MASK_VMADC_VXM 0xfe00707f +#define MATCH_VMADD_VV 0xa4002057 +#define MASK_VMADD_VV 0xfc00707f +#define MATCH_VMADD_VX 0xa4006057 +#define MASK_VMADD_VX 0xfc00707f +#define MATCH_VMAND_MM 0x64002057 +#define MASK_VMAND_MM 0xfc00707f +#define MATCH_VMANDN_MM 0x60002057 +#define MASK_VMANDN_MM 0xfc00707f +#define MATCH_VMAX_VV 0x1c000057 +#define MASK_VMAX_VV 0xfc00707f +#define MATCH_VMAX_VX 0x1c004057 +#define MASK_VMAX_VX 0xfc00707f +#define MATCH_VMAXU_VV 0x18000057 +#define MASK_VMAXU_VV 0xfc00707f +#define MATCH_VMAXU_VX 0x18004057 +#define MASK_VMAXU_VX 0xfc00707f +#define MATCH_VMERGE_VIM 0x5c003057 +#define MASK_VMERGE_VIM 0xfe00707f +#define MATCH_VMERGE_VVM 0x5c000057 +#define MASK_VMERGE_VVM 0xfe00707f +#define MATCH_VMERGE_VXM 0x5c004057 +#define MASK_VMERGE_VXM 0xfe00707f +#define MATCH_VMFEQ_VF 0x60005057 +#define MASK_VMFEQ_VF 0xfc00707f +#define MATCH_VMFEQ_VV 0x60001057 +#define MASK_VMFEQ_VV 0xfc00707f +#define MATCH_VMFGE_VF 0x7c005057 +#define MASK_VMFGE_VF 0xfc00707f +#define MATCH_VMFGT_VF 0x74005057 +#define MASK_VMFGT_VF 0xfc00707f +#define MATCH_VMFLE_VF 0x64005057 +#define MASK_VMFLE_VF 0xfc00707f +#define MATCH_VMFLE_VV 0x64001057 +#define MASK_VMFLE_VV 0xfc00707f +#define MATCH_VMFLT_VF 0x6c005057 +#define MASK_VMFLT_VF 0xfc00707f +#define MATCH_VMFLT_VV 0x6c001057 +#define MASK_VMFLT_VV 0xfc00707f +#define MATCH_VMFNE_VF 0x70005057 +#define MASK_VMFNE_VF 0xfc00707f +#define MATCH_VMFNE_VV 0x70001057 +#define MASK_VMFNE_VV 0xfc00707f +#define MATCH_VMIN_VV 0x14000057 +#define MASK_VMIN_VV 0xfc00707f +#define MATCH_VMIN_VX 0x14004057 +#define MASK_VMIN_VX 0xfc00707f +#define MATCH_VMINU_VV 0x10000057 +#define MASK_VMINU_VV 0xfc00707f +#define MATCH_VMINU_VX 0x10004057 +#define MASK_VMINU_VX 0xfc00707f +#define MATCH_VMNAND_MM 0x74002057 +#define MASK_VMNAND_MM 0xfc00707f +#define MATCH_VMNOR_MM 0x78002057 +#define MASK_VMNOR_MM 0xfc00707f +#define MATCH_VMOR_MM 0x68002057 +#define MASK_VMOR_MM 0xfc00707f +#define MATCH_VMORN_MM 0x70002057 +#define MASK_VMORN_MM 0xfc00707f +#define MATCH_VMSBC_VV 0x4e000057 +#define MASK_VMSBC_VV 0xfe00707f +#define MATCH_VMSBC_VVM 0x4c000057 +#define MASK_VMSBC_VVM 0xfe00707f +#define MATCH_VMSBC_VX 0x4e004057 +#define MASK_VMSBC_VX 0xfe00707f +#define MATCH_VMSBC_VXM 0x4c004057 +#define MASK_VMSBC_VXM 0xfe00707f +#define MATCH_VMSBF_M 0x5000a057 +#define MASK_VMSBF_M 0xfc0ff07f +#define MATCH_VMSEQ_VI 0x60003057 +#define MASK_VMSEQ_VI 0xfc00707f +#define MATCH_VMSEQ_VV 0x60000057 +#define MASK_VMSEQ_VV 0xfc00707f +#define MATCH_VMSEQ_VX 0x60004057 +#define MASK_VMSEQ_VX 0xfc00707f +#define MATCH_VMSGT_VI 0x7c003057 +#define MASK_VMSGT_VI 0xfc00707f +#define MATCH_VMSGT_VX 0x7c004057 +#define MASK_VMSGT_VX 0xfc00707f +#define MATCH_VMSGTU_VI 0x78003057 +#define MASK_VMSGTU_VI 0xfc00707f +#define MATCH_VMSGTU_VX 0x78004057 +#define MASK_VMSGTU_VX 0xfc00707f +#define MATCH_VMSIF_M 0x5001a057 +#define MASK_VMSIF_M 0xfc0ff07f +#define MATCH_VMSLE_VI 0x74003057 +#define MASK_VMSLE_VI 0xfc00707f +#define MATCH_VMSLE_VV 0x74000057 +#define MASK_VMSLE_VV 0xfc00707f +#define MATCH_VMSLE_VX 0x74004057 +#define MASK_VMSLE_VX 0xfc00707f +#define MATCH_VMSLEU_VI 0x70003057 +#define MASK_VMSLEU_VI 0xfc00707f +#define MATCH_VMSLEU_VV 0x70000057 +#define MASK_VMSLEU_VV 0xfc00707f +#define MATCH_VMSLEU_VX 0x70004057 +#define MASK_VMSLEU_VX 0xfc00707f +#define MATCH_VMSLT_VV 0x6c000057 +#define MASK_VMSLT_VV 0xfc00707f +#define MATCH_VMSLT_VX 0x6c004057 +#define MASK_VMSLT_VX 0xfc00707f +#define MATCH_VMSLTU_VV 0x68000057 +#define MASK_VMSLTU_VV 0xfc00707f +#define MATCH_VMSLTU_VX 0x68004057 +#define MASK_VMSLTU_VX 0xfc00707f +#define MATCH_VMSNE_VI 0x64003057 +#define MASK_VMSNE_VI 0xfc00707f +#define MATCH_VMSNE_VV 0x64000057 +#define MASK_VMSNE_VV 0xfc00707f +#define MATCH_VMSNE_VX 0x64004057 +#define MASK_VMSNE_VX 0xfc00707f +#define MATCH_VMSOF_M 0x50012057 +#define MASK_VMSOF_M 0xfc0ff07f +#define MATCH_VMUL_VV 0x94002057 +#define MASK_VMUL_VV 0xfc00707f +#define MATCH_VMUL_VX 0x94006057 +#define MASK_VMUL_VX 0xfc00707f +#define MATCH_VMULH_VV 0x9c002057 +#define MASK_VMULH_VV 0xfc00707f +#define MATCH_VMULH_VX 0x9c006057 +#define MASK_VMULH_VX 0xfc00707f +#define MATCH_VMULHSU_VV 0x98002057 +#define MASK_VMULHSU_VV 0xfc00707f +#define MATCH_VMULHSU_VX 0x98006057 +#define MASK_VMULHSU_VX 0xfc00707f +#define MATCH_VMULHU_VV 0x90002057 +#define MASK_VMULHU_VV 0xfc00707f +#define MATCH_VMULHU_VX 0x90006057 +#define MASK_VMULHU_VX 0xfc00707f +#define MATCH_VMV1R_V 0x9e003057 +#define MASK_VMV1R_V 0xfe0ff07f +#define MATCH_VMV2R_V 0x9e00b057 +#define MASK_VMV2R_V 0xfe0ff07f +#define MATCH_VMV4R_V 0x9e01b057 +#define MASK_VMV4R_V 0xfe0ff07f +#define MATCH_VMV8R_V 0x9e03b057 +#define MASK_VMV8R_V 0xfe0ff07f +#define MATCH_VMV_S_X 0x42006057 +#define MASK_VMV_S_X 0xfff0707f +#define MATCH_VMV_V_I 0x5e003057 +#define MASK_VMV_V_I 0xfff0707f +#define MATCH_VMV_V_V 0x5e000057 +#define MASK_VMV_V_V 0xfff0707f +#define MATCH_VMV_V_X 0x5e004057 +#define MASK_VMV_V_X 0xfff0707f +#define MATCH_VMV_X_S 0x42002057 +#define MASK_VMV_X_S 0xfe0ff07f +#define MATCH_VMXNOR_MM 0x7c002057 +#define MASK_VMXNOR_MM 0xfc00707f +#define MATCH_VMXOR_MM 0x6c002057 +#define MASK_VMXOR_MM 0xfc00707f +#define MATCH_VNCLIP_WI 0xbc003057 +#define MASK_VNCLIP_WI 0xfc00707f +#define MATCH_VNCLIP_WV 0xbc000057 +#define MASK_VNCLIP_WV 0xfc00707f +#define MATCH_VNCLIP_WX 0xbc004057 +#define MASK_VNCLIP_WX 0xfc00707f +#define MATCH_VNCLIPU_WI 0xb8003057 +#define MASK_VNCLIPU_WI 0xfc00707f +#define MATCH_VNCLIPU_WV 0xb8000057 +#define MASK_VNCLIPU_WV 0xfc00707f +#define MATCH_VNCLIPU_WX 0xb8004057 +#define MASK_VNCLIPU_WX 0xfc00707f +#define MATCH_VNMSAC_VV 0xbc002057 +#define MASK_VNMSAC_VV 0xfc00707f +#define MATCH_VNMSAC_VX 0xbc006057 +#define MASK_VNMSAC_VX 0xfc00707f +#define MATCH_VNMSUB_VV 0xac002057 +#define MASK_VNMSUB_VV 0xfc00707f +#define MATCH_VNMSUB_VX 0xac006057 +#define MASK_VNMSUB_VX 0xfc00707f +#define MATCH_VNSRA_WI 0xb4003057 +#define MASK_VNSRA_WI 0xfc00707f +#define MATCH_VNSRA_WV 0xb4000057 +#define MASK_VNSRA_WV 0xfc00707f +#define MATCH_VNSRA_WX 0xb4004057 +#define MASK_VNSRA_WX 0xfc00707f +#define MATCH_VNSRL_WI 0xb0003057 +#define MASK_VNSRL_WI 0xfc00707f +#define MATCH_VNSRL_WV 0xb0000057 +#define MASK_VNSRL_WV 0xfc00707f +#define MATCH_VNSRL_WX 0xb0004057 +#define MASK_VNSRL_WX 0xfc00707f +#define MATCH_VOR_VI 0x28003057 +#define MASK_VOR_VI 0xfc00707f +#define MATCH_VOR_VV 0x28000057 +#define MASK_VOR_VV 0xfc00707f +#define MATCH_VOR_VX 0x28004057 +#define MASK_VOR_VX 0xfc00707f +#define MATCH_VREDAND_VS 0x4002057 +#define MASK_VREDAND_VS 0xfc00707f +#define MATCH_VREDMAX_VS 0x1c002057 +#define MASK_VREDMAX_VS 0xfc00707f +#define MATCH_VREDMAXU_VS 0x18002057 +#define MASK_VREDMAXU_VS 0xfc00707f +#define MATCH_VREDMIN_VS 0x14002057 +#define MASK_VREDMIN_VS 0xfc00707f +#define MATCH_VREDMINU_VS 0x10002057 +#define MASK_VREDMINU_VS 0xfc00707f +#define MATCH_VREDOR_VS 0x8002057 +#define MASK_VREDOR_VS 0xfc00707f +#define MATCH_VREDSUM_VS 0x2057 +#define MASK_VREDSUM_VS 0xfc00707f +#define MATCH_VREDXOR_VS 0xc002057 +#define MASK_VREDXOR_VS 0xfc00707f +#define MATCH_VREM_VV 0x8c002057 +#define MASK_VREM_VV 0xfc00707f +#define MATCH_VREM_VX 0x8c006057 +#define MASK_VREM_VX 0xfc00707f +#define MATCH_VREMU_VV 0x88002057 +#define MASK_VREMU_VV 0xfc00707f +#define MATCH_VREMU_VX 0x88006057 +#define MASK_VREMU_VX 0xfc00707f +#define MATCH_VRGATHER_VI 0x30003057 +#define MASK_VRGATHER_VI 0xfc00707f +#define MATCH_VRGATHER_VV 0x30000057 +#define MASK_VRGATHER_VV 0xfc00707f +#define MATCH_VRGATHER_VX 0x30004057 +#define MASK_VRGATHER_VX 0xfc00707f +#define MATCH_VRGATHEREI16_VV 0x38000057 +#define MASK_VRGATHEREI16_VV 0xfc00707f +#define MATCH_VRSUB_VI 0xc003057 +#define MASK_VRSUB_VI 0xfc00707f +#define MATCH_VRSUB_VX 0xc004057 +#define MASK_VRSUB_VX 0xfc00707f +#define MATCH_VS1R_V 0x2800027 +#define MASK_VS1R_V 0xfff0707f +#define MATCH_VS2R_V 0x22800027 +#define MASK_VS2R_V 0xfff0707f +#define MATCH_VS4R_V 0x62800027 +#define MASK_VS4R_V 0xfff0707f +#define MATCH_VS8R_V 0xe2800027 +#define MASK_VS8R_V 0xfff0707f +#define MATCH_VSADD_VI 0x84003057 +#define MASK_VSADD_VI 0xfc00707f +#define MATCH_VSADD_VV 0x84000057 +#define MASK_VSADD_VV 0xfc00707f +#define MATCH_VSADD_VX 0x84004057 +#define MASK_VSADD_VX 0xfc00707f +#define MATCH_VSADDU_VI 0x80003057 +#define MASK_VSADDU_VI 0xfc00707f +#define MATCH_VSADDU_VV 0x80000057 +#define MASK_VSADDU_VV 0xfc00707f +#define MATCH_VSADDU_VX 0x80004057 +#define MASK_VSADDU_VX 0xfc00707f +#define MATCH_VSBC_VVM 0x48000057 +#define MASK_VSBC_VVM 0xfe00707f +#define MATCH_VSBC_VXM 0x48004057 +#define MASK_VSBC_VXM 0xfe00707f +#define MATCH_VSE1024_V 0x10007027 +#define MASK_VSE1024_V 0x1df0707f +#define MATCH_VSE128_V 0x10000027 +#define MASK_VSE128_V 0x1df0707f +#define MATCH_VSE16_V 0x5027 +#define MASK_VSE16_V 0x1df0707f +#define MATCH_VSE256_V 0x10005027 +#define MASK_VSE256_V 0x1df0707f +#define MATCH_VSE32_V 0x6027 +#define MASK_VSE32_V 0x1df0707f +#define MATCH_VSE512_V 0x10006027 +#define MASK_VSE512_V 0x1df0707f +#define MATCH_VSE64_V 0x7027 +#define MASK_VSE64_V 0x1df0707f +#define MATCH_VSE8_V 0x27 +#define MASK_VSE8_V 0x1df0707f +#define MATCH_VSETIVLI 0xc0007057 +#define MASK_VSETIVLI 0xc000707f +#define MATCH_VSETVL 0x80007057 +#define MASK_VSETVL 0xfe00707f +#define MATCH_VSETVLI 0x7057 +#define MASK_VSETVLI 0x8000707f +#define MATCH_VSEXT_VF2 0x4803a057 +#define MASK_VSEXT_VF2 0xfc0ff07f +#define MATCH_VSEXT_VF4 0x4802a057 +#define MASK_VSEXT_VF4 0xfc0ff07f +#define MATCH_VSEXT_VF8 0x4801a057 +#define MASK_VSEXT_VF8 0xfc0ff07f +#define MATCH_VSLIDE1DOWN_VX 0x3c006057 +#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MATCH_VSLIDE1UP_VX 0x38006057 +#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MATCH_VSLIDEDOWN_VI 0x3c003057 +#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MATCH_VSLIDEDOWN_VX 0x3c004057 +#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MATCH_VSLIDEUP_VI 0x38003057 +#define MASK_VSLIDEUP_VI 0xfc00707f +#define MATCH_VSLIDEUP_VX 0x38004057 +#define MASK_VSLIDEUP_VX 0xfc00707f +#define MATCH_VSLL_VI 0x94003057 +#define MASK_VSLL_VI 0xfc00707f +#define MATCH_VSLL_VV 0x94000057 +#define MASK_VSLL_VV 0xfc00707f +#define MATCH_VSLL_VX 0x94004057 +#define MASK_VSLL_VX 0xfc00707f +#define MATCH_VSM_V 0x2b00027 +#define MASK_VSM_V 0xfff0707f +#define MATCH_VSMUL_VV 0x9c000057 +#define MASK_VSMUL_VV 0xfc00707f +#define MATCH_VSMUL_VX 0x9c004057 +#define MASK_VSMUL_VX 0xfc00707f +#define MATCH_VSOXEI1024_V 0x1c007027 +#define MASK_VSOXEI1024_V 0x1c00707f +#define MATCH_VSOXEI128_V 0x1c000027 +#define MASK_VSOXEI128_V 0x1c00707f +#define MATCH_VSOXEI16_V 0xc005027 +#define MASK_VSOXEI16_V 0x1c00707f +#define MATCH_VSOXEI256_V 0x1c005027 +#define MASK_VSOXEI256_V 0x1c00707f +#define MATCH_VSOXEI32_V 0xc006027 +#define MASK_VSOXEI32_V 0x1c00707f +#define MATCH_VSOXEI512_V 0x1c006027 +#define MASK_VSOXEI512_V 0x1c00707f +#define MATCH_VSOXEI64_V 0xc007027 +#define MASK_VSOXEI64_V 0x1c00707f +#define MATCH_VSOXEI8_V 0xc000027 +#define MASK_VSOXEI8_V 0x1c00707f +#define MATCH_VSRA_VI 0xa4003057 +#define MASK_VSRA_VI 0xfc00707f +#define MATCH_VSRA_VV 0xa4000057 +#define MASK_VSRA_VV 0xfc00707f +#define MATCH_VSRA_VX 0xa4004057 +#define MASK_VSRA_VX 0xfc00707f +#define MATCH_VSRL_VI 0xa0003057 +#define MASK_VSRL_VI 0xfc00707f +#define MATCH_VSRL_VV 0xa0000057 +#define MASK_VSRL_VV 0xfc00707f +#define MATCH_VSRL_VX 0xa0004057 +#define MASK_VSRL_VX 0xfc00707f +#define MATCH_VSSE1024_V 0x18007027 +#define MASK_VSSE1024_V 0x1c00707f +#define MATCH_VSSE128_V 0x18000027 +#define MASK_VSSE128_V 0x1c00707f +#define MATCH_VSSE16_V 0x8005027 +#define MASK_VSSE16_V 0x1c00707f +#define MATCH_VSSE256_V 0x18005027 +#define MASK_VSSE256_V 0x1c00707f +#define MATCH_VSSE32_V 0x8006027 +#define MASK_VSSE32_V 0x1c00707f +#define MATCH_VSSE512_V 0x18006027 +#define MASK_VSSE512_V 0x1c00707f +#define MATCH_VSSE64_V 0x8007027 +#define MASK_VSSE64_V 0x1c00707f +#define MATCH_VSSE8_V 0x8000027 +#define MASK_VSSE8_V 0x1c00707f +#define MATCH_VSSRA_VI 0xac003057 +#define MASK_VSSRA_VI 0xfc00707f +#define MATCH_VSSRA_VV 0xac000057 +#define MASK_VSSRA_VV 0xfc00707f +#define MATCH_VSSRA_VX 0xac004057 +#define MASK_VSSRA_VX 0xfc00707f +#define MATCH_VSSRL_VI 0xa8003057 +#define MASK_VSSRL_VI 0xfc00707f +#define MATCH_VSSRL_VV 0xa8000057 +#define MASK_VSSRL_VV 0xfc00707f +#define MATCH_VSSRL_VX 0xa8004057 +#define MASK_VSSRL_VX 0xfc00707f +#define MATCH_VSSUB_VV 0x8c000057 +#define MASK_VSSUB_VV 0xfc00707f +#define MATCH_VSSUB_VX 0x8c004057 +#define MASK_VSSUB_VX 0xfc00707f +#define MATCH_VSSUBU_VV 0x88000057 +#define MASK_VSSUBU_VV 0xfc00707f +#define MATCH_VSSUBU_VX 0x88004057 +#define MASK_VSSUBU_VX 0xfc00707f +#define MATCH_VSUB_VV 0x8000057 +#define MASK_VSUB_VV 0xfc00707f +#define MATCH_VSUB_VX 0x8004057 +#define MASK_VSUB_VX 0xfc00707f +#define MATCH_VSUXEI1024_V 0x14007027 +#define MASK_VSUXEI1024_V 0x1c00707f +#define MATCH_VSUXEI128_V 0x14000027 +#define MASK_VSUXEI128_V 0x1c00707f +#define MATCH_VSUXEI16_V 0x4005027 +#define MASK_VSUXEI16_V 0x1c00707f +#define MATCH_VSUXEI256_V 0x14005027 +#define MASK_VSUXEI256_V 0x1c00707f +#define MATCH_VSUXEI32_V 0x4006027 +#define MASK_VSUXEI32_V 0x1c00707f +#define MATCH_VSUXEI512_V 0x14006027 +#define MASK_VSUXEI512_V 0x1c00707f +#define MATCH_VSUXEI64_V 0x4007027 +#define MASK_VSUXEI64_V 0x1c00707f +#define MATCH_VSUXEI8_V 0x4000027 +#define MASK_VSUXEI8_V 0x1c00707f +#define MATCH_VWADD_VV 0xc4002057 +#define MASK_VWADD_VV 0xfc00707f +#define MATCH_VWADD_VX 0xc4006057 +#define MASK_VWADD_VX 0xfc00707f +#define MATCH_VWADD_WV 0xd4002057 +#define MASK_VWADD_WV 0xfc00707f +#define MATCH_VWADD_WX 0xd4006057 +#define MASK_VWADD_WX 0xfc00707f +#define MATCH_VWADDU_VV 0xc0002057 +#define MASK_VWADDU_VV 0xfc00707f +#define MATCH_VWADDU_VX 0xc0006057 +#define MASK_VWADDU_VX 0xfc00707f +#define MATCH_VWADDU_WV 0xd0002057 +#define MASK_VWADDU_WV 0xfc00707f +#define MATCH_VWADDU_WX 0xd0006057 +#define MASK_VWADDU_WX 0xfc00707f +#define MATCH_VWMACC_VV 0xf4002057 +#define MASK_VWMACC_VV 0xfc00707f +#define MATCH_VWMACC_VX 0xf4006057 +#define MASK_VWMACC_VX 0xfc00707f +#define MATCH_VWMACCSU_VV 0xfc002057 +#define MASK_VWMACCSU_VV 0xfc00707f +#define MATCH_VWMACCSU_VX 0xfc006057 +#define MASK_VWMACCSU_VX 0xfc00707f +#define MATCH_VWMACCU_VV 0xf0002057 +#define MASK_VWMACCU_VV 0xfc00707f +#define MATCH_VWMACCU_VX 0xf0006057 +#define MASK_VWMACCU_VX 0xfc00707f +#define MATCH_VWMACCUS_VX 0xf8006057 +#define MASK_VWMACCUS_VX 0xfc00707f +#define MATCH_VWMUL_VV 0xec002057 +#define MASK_VWMUL_VV 0xfc00707f +#define MATCH_VWMUL_VX 0xec006057 +#define MASK_VWMUL_VX 0xfc00707f +#define MATCH_VWMULSU_VV 0xe8002057 +#define MASK_VWMULSU_VV 0xfc00707f +#define MATCH_VWMULSU_VX 0xe8006057 +#define MASK_VWMULSU_VX 0xfc00707f +#define MATCH_VWMULU_VV 0xe0002057 +#define MASK_VWMULU_VV 0xfc00707f +#define MATCH_VWMULU_VX 0xe0006057 +#define MASK_VWMULU_VX 0xfc00707f +#define MATCH_VWREDSUM_VS 0xc4000057 +#define MASK_VWREDSUM_VS 0xfc00707f +#define MATCH_VWREDSUMU_VS 0xc0000057 +#define MASK_VWREDSUMU_VS 0xfc00707f +#define MATCH_VWSUB_VV 0xcc002057 +#define MASK_VWSUB_VV 0xfc00707f +#define MATCH_VWSUB_VX 0xcc006057 +#define MASK_VWSUB_VX 0xfc00707f +#define MATCH_VWSUB_WV 0xdc002057 +#define MASK_VWSUB_WV 0xfc00707f +#define MATCH_VWSUB_WX 0xdc006057 +#define MASK_VWSUB_WX 0xfc00707f +#define MATCH_VWSUBU_VV 0xc8002057 +#define MASK_VWSUBU_VV 0xfc00707f +#define MATCH_VWSUBU_VX 0xc8006057 +#define MASK_VWSUBU_VX 0xfc00707f +#define MATCH_VWSUBU_WV 0xd8002057 +#define MASK_VWSUBU_WV 0xfc00707f +#define MATCH_VWSUBU_WX 0xd8006057 +#define MASK_VWSUBU_WX 0xfc00707f +#define MATCH_VXOR_VI 0x2c003057 +#define MASK_VXOR_VI 0xfc00707f +#define MATCH_VXOR_VV 0x2c000057 +#define MASK_VXOR_VV 0xfc00707f +#define MATCH_VXOR_VX 0x2c004057 +#define MASK_VXOR_VX 0xfc00707f +#define MATCH_VZEXT_VF2 0x48032057 +#define MASK_VZEXT_VF2 0xfc0ff07f +#define MATCH_VZEXT_VF4 0x48022057 +#define MASK_VZEXT_VF4 0xfc0ff07f +#define MATCH_VZEXT_VF8 0x48012057 +#define MASK_VZEXT_VF8 0xfc0ff07f +#define MATCH_WEXT 0xce000077 +#define MASK_WEXT 0xfe00707f +#define MATCH_WEXTI 0xde000077 +#define MASK_WEXTI 0xfe00707f +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_WRS_NTO 0xd00073 +#define MASK_WRS_NTO 0xffffffff +#define MATCH_WRS_STO 0x1d00073 +#define MASK_WRS_STO 0xffffffff +#define MATCH_XNOR 0x40004033 +#define MASK_XNOR 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_XPERM16 0x28006033 +#define MASK_XPERM16 0xfe00707f +#define MATCH_XPERM32 0x28000033 +#define MASK_XPERM32 0xfe00707f +#define MATCH_XPERM4 0x28002033 +#define MASK_XPERM4 0xfe00707f +#define MATCH_XPERM8 0x28004033 +#define MASK_XPERM8 0xfe00707f +#define MATCH_ZUNPKD810 0xacc00077 +#define MASK_ZUNPKD810 0xfff0707f +#define MATCH_ZUNPKD820 0xacd00077 +#define MASK_ZUNPKD820 0xfff0707f +#define MATCH_ZUNPKD830 0xace00077 +#define MASK_ZUNPKD830 0xfff0707f +#define MATCH_ZUNPKD831 0xacf00077 +#define MASK_ZUNPKD831 0xfff0707f +#define MATCH_ZUNPKD832 0xad700077 +#define MASK_ZUNPKD832 0xfff0707f + +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_VSTART 0x8 +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa +#define CSR_VCSR 0xf +#define CSR_SEED 0x15 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a +#define CSR_SSTATEEN0 0x10c +#define CSR_SSTATEEN1 0x10d +#define CSR_SSTATEEN2 0x10e +#define CSR_SSTATEEN3 0x10f +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_STIMECMP 0x14d +#define CSR_SATP 0x180 +#define CSR_SCONTEXT 0x5a8 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSATP 0x280 +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HENVCFG 0x60a +#define CSR_HSTATEEN0 0x60c +#define CSR_HSTATEEN1 0x60d +#define CSR_HSTATEEN2 0x60e +#define CSR_HSTATEEN3 0x60f +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HGEIP 0xe12 +#define CSR_SCOUNTOVF 0xda0 +#define CSR_UTVT 0x7 +#define CSR_UNXTI 0x45 +#define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0x146 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MENVCFG 0x30a +#define CSR_MSTATEEN0 0x30c +#define CSR_MSTATEEN1 0x30d +#define CSR_MSTATEEN2 0x30e +#define CSR_MSTATEEN3 0x30f +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef +#define CSR_MSECCFG 0x747 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 +#define CSR_MSCONTEXT 0x7aa +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 +#define CSR_STIMECMPH 0x15d +#define CSR_VSTIMECMPH 0x25d +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HENVCFGH 0x61a +#define CSR_HSTATEEN0H 0x61c +#define CSR_HSTATEEN1H 0x61d +#define CSR_HSTATEEN2H 0x61e +#define CSR_HSTATEEN3H 0x61f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MSTATUSH 0x310 +#define CSR_MENVCFGH 0x31a +#define CSR_MSTATEEN0H 0x31c +#define CSR_MSTATEEN1H 0x31d +#define CSR_MSTATEEN2H 0x31e +#define CSR_MSTATEEN3H 0x31f +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f +#define CSR_MSECCFGH 0x757 +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INSTRUCTION 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#define INSN_FIELD_RD 0xf80 +#define INSN_FIELD_RT 0xf8000 +#define INSN_FIELD_RS1 0xf8000 +#define INSN_FIELD_RS2 0x1f00000 +#define INSN_FIELD_RS3 0xf8000000 +#define INSN_FIELD_AQRL 0x6000000 +#define INSN_FIELD_AQ 0x4000000 +#define INSN_FIELD_RL 0x2000000 +#define INSN_FIELD_FM 0xf0000000 +#define INSN_FIELD_PRED 0xf000000 +#define INSN_FIELD_SUCC 0xf00000 +#define INSN_FIELD_RM 0x7000 +#define INSN_FIELD_FUNCT3 0x7000 +#define INSN_FIELD_FUNCT2 0x6000000 +#define INSN_FIELD_IMM20 0xfffff000 +#define INSN_FIELD_JIMM20 0xfffff000 +#define INSN_FIELD_IMM12 0xfff00000 +#define INSN_FIELD_CSR 0xfff00000 +#define INSN_FIELD_IMM12HI 0xfe000000 +#define INSN_FIELD_BIMM12HI 0xfe000000 +#define INSN_FIELD_IMM12LO 0xf80 +#define INSN_FIELD_BIMM12LO 0xf80 +#define INSN_FIELD_ZIMM 0xf8000 +#define INSN_FIELD_SHAMT 0x7f00000 +#define INSN_FIELD_SHAMTW 0x1f00000 +#define INSN_FIELD_SHAMTW4 0xf00000 +#define INSN_FIELD_SHAMTD 0x3f00000 +#define INSN_FIELD_BS 0xc0000000 +#define INSN_FIELD_RNUM 0xf00000 +#define INSN_FIELD_RC 0x3e000000 +#define INSN_FIELD_IMM2 0x300000 +#define INSN_FIELD_IMM3 0x700000 +#define INSN_FIELD_IMM4 0xf00000 +#define INSN_FIELD_IMM5 0x1f00000 +#define INSN_FIELD_IMM6 0x3f00000 +#define INSN_FIELD_OPCODE 0x7f +#define INSN_FIELD_FUNCT7 0xfe000000 +#define INSN_FIELD_VD 0xf80 +#define INSN_FIELD_VS3 0xf80 +#define INSN_FIELD_VS1 0xf8000 +#define INSN_FIELD_VS2 0x1f00000 +#define INSN_FIELD_VM 0x2000000 +#define INSN_FIELD_WD 0x4000000 +#define INSN_FIELD_AMOOP 0xf8000000 +#define INSN_FIELD_NF 0xe0000000 +#define INSN_FIELD_SIMM5 0xf8000 +#define INSN_FIELD_ZIMM10 0x3ff00000 +#define INSN_FIELD_ZIMM11 0x7ff00000 +#define INSN_FIELD_C_NZUIMM10 0x1fe0 +#define INSN_FIELD_C_UIMM7LO 0x60 +#define INSN_FIELD_C_UIMM7HI 0x1c00 +#define INSN_FIELD_C_UIMM8LO 0x60 +#define INSN_FIELD_C_UIMM8HI 0x1c00 +#define INSN_FIELD_C_UIMM9LO 0x60 +#define INSN_FIELD_C_UIMM9HI 0x1c00 +#define INSN_FIELD_C_NZIMM6LO 0x7c +#define INSN_FIELD_C_NZIMM6HI 0x1000 +#define INSN_FIELD_C_IMM6LO 0x7c +#define INSN_FIELD_C_IMM6HI 0x1000 +#define INSN_FIELD_C_NZIMM10HI 0x1000 +#define INSN_FIELD_C_NZIMM10LO 0x7c +#define INSN_FIELD_C_NZIMM18HI 0x1000 +#define INSN_FIELD_C_NZIMM18LO 0x7c +#define INSN_FIELD_C_IMM12 0x1ffc +#define INSN_FIELD_C_BIMM9LO 0x7c +#define INSN_FIELD_C_BIMM9HI 0x1c00 +#define INSN_FIELD_C_NZUIMM5 0x7c +#define INSN_FIELD_C_NZUIMM6LO 0x7c +#define INSN_FIELD_C_NZUIMM6HI 0x1000 +#define INSN_FIELD_C_UIMM8SPLO 0x7c +#define INSN_FIELD_C_UIMM8SPHI 0x1000 +#define INSN_FIELD_C_UIMM8SP_S 0x1f80 +#define INSN_FIELD_C_UIMM10SPLO 0x7c +#define INSN_FIELD_C_UIMM10SPHI 0x1000 +#define INSN_FIELD_C_UIMM9SPLO 0x7c +#define INSN_FIELD_C_UIMM9SPHI 0x1000 +#define INSN_FIELD_C_UIMM10SP_S 0x1f80 +#define INSN_FIELD_C_UIMM9SP_S 0x1f80 +#define INSN_FIELD_RS1_P 0x380 +#define INSN_FIELD_RS2_P 0x1c +#define INSN_FIELD_RD_P 0x1c +#define INSN_FIELD_RD_RS1_N0 0xf80 +#define INSN_FIELD_RD_RS1_P 0x380 +#define INSN_FIELD_RD_RS1 0xf80 +#define INSN_FIELD_RD_N2 0xf80 +#define INSN_FIELD_RD_N0 0xf80 +#define INSN_FIELD_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2_N0 0x7c +#define INSN_FIELD_C_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2 0x7c +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) +DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) +DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) +DECLARE_INSN(addd, MATCH_ADDD, MASK_ADDD) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(addid, MATCH_ADDID, MASK_ADDID) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) +DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) +DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) +DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) +DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) +DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) +DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) +DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) +DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) +DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) +DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) +DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) +DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) +DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) +DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV) DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK) -DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) -DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) -DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) -DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8) +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ) +DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ) +DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) +DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) +DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) +DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16) DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32) -DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) +DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8) +DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) +DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) +DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) -DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) +DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) +DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) +DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) +DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) +DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) +DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) +DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) +DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) +DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) +DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) +DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) +DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) +DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) +DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) +DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) +DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) +DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) +DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) +DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) +DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) +DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) +DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) +DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) +DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) +DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) -DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) +DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) +DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) -DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) +DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) +DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) +DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) -DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) -DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) -DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) +DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) +DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) +DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) -DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) -DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) +DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) +DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) +DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) +DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) +DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) +DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) +DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) -DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) +DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) +DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) +DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) +DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) +DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) +DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) +DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) -DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) +DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) -DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) -DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) -DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) +DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) +DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) +DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) +DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) +DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) +DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) +DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) +DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) +DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) -DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) +DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) -DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) +DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) -DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) +DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) @@ -4076,86 +3695,209 @@ DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) -DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) +DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) -DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) -DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) -DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) -DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) +DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) +DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) +DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) +DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) +DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) +DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) -DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) -DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) +DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) +DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) +DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) +DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) +DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) +DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) +DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) +DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) +DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) -DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) +DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) +DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) +DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lq, MATCH_LQ, MASK_LQ) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) +DECLARE_INSN(max, MATCH_MAX, MASK_MAX) +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW) +DECLARE_INSN(min, MATCH_MIN, MASK_MIN) +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) DECLARE_INSN(minw, MATCH_MINW, MASK_MINW) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) +DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) +DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32) DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) -DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) +DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) -DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) +DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) +DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) +DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32) +DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) +DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) +DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) +DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) +DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) +DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) +DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) +DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) -DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) +DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) +DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) +DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) -DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) -DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) +DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) -DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) +DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) -DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) -DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) +DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) +DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) +DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) +DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) +DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) +DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) +DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) +DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) +DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) +DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) +DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) +DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) +DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) +DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) +DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) +DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) +DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) +DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) +DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) +DECLARE_INSN(slld, MATCH_SLLD, MASK_SLLD) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) +DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) +DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) +DECLARE_INSN(sllid, MATCH_SLLID, MASK_SLLID) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) +DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) +DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) +DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) -DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) -DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) -DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) +DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) +DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) +DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) -DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) -DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) +DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) +DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) +DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) -DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) -DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) +DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) -DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) -DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) +DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) +DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) +DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) +DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) +DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) @@ -4165,181 +3907,604 @@ DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) -DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) -DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) +DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) +DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) +DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) -DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) -DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) -DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) -DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) -DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) -DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) +DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) +DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) +DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) +DECLARE_INSN(sq, MATCH_SQ, MASK_SQ) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) +DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) +DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) +DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) +DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) +DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) +DECLARE_INSN(srad, MATCH_SRAD, MASK_SRAD) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) -DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) -DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) -DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) -DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) +DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) +DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) +DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) +DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) +DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) +DECLARE_INSN(sraid, MATCH_SRAID, MASK_SRAID) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) +DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) +DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) +DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) +DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) +DECLARE_INSN(srld, MATCH_SRLD, MASK_SRLD) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) +DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) +DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) +DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) +DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) +DECLARE_INSN(srlid, MATCH_SRLID, MASK_SRLID) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) +DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) -DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) +DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) +DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) +DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) +DECLARE_INSN(subd, MATCH_SUBD, MASK_SUBD) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8) -DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) -DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) +DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) -DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) +DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) -DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) +DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) +DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) +DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) +DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) +DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) +DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) -DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) +DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) +DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) +DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) -DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) -DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) +DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) -DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) +DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) +DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) +DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) +DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) -DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) -DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) +DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) -DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) +DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) +DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) +DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) +DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) +DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) +DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) -DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) +DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) +DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) +DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) -DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI) +DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) +DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) +DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) +DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) +DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) +DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) +DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) +DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) +DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) +DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) +DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) +DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) +DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) +DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) +DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) +DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) +DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) +DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) +DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) +DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) +DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) +DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) +DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) +DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) +DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) +DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) +DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) +DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) +DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) +DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) +DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) +DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) +DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) +DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) +DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) +DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) +DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) +DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) +DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) +DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) +DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) +DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) +DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) +DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) +DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) +DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) +DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) +DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) +DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) +DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) +DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) +DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) +DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) +DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) +DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) +DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) +DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) +DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) +DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) +DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) +DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) +DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) +DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) +DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) +DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) +DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) +DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) +DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) +DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) +DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) +DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) +DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) +DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) +DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) +DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) +DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) +DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) +DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) +DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) +DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) +DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) +DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) +DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) +DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) +DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) +DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) +DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) +DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) +DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) +DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) +DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) +DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) +DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) +DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) +DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) +DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) +DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) +DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) +DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) +DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) +DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) +DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) +DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) +DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) +DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) +DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) +DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) +DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) +DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) +DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) +DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) +DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) +DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) +DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) +DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) +DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) +DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) +DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) +DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) +DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) +DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) +DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) +DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) +DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) +DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) +DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) +DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) +DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) +DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) +DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) +DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) +DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) +DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) +DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) +DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) +DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) +DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) +DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) +DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) +DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) +DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) +DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) +DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) +DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) +DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) +DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) +DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) +DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) +DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) +DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) +DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) +DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) +DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) +DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) +DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) +DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) +DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) +DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) +DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) +DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) +DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) +DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) +DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) +DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) +DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) +DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) +DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) +DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) +DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) +DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) +DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) +DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) +DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) +DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) +DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) +DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) +DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) +DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) +DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) +DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) +DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) +DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) +DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) +DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) +DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) +DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) +DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) +DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) +DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) +DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) +DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) +DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) +DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) +DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) +DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) +DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) +DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) +DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) +DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) +DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) +DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) +DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) +DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) +DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) +DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) +DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) +DECLARE_INSN(vmandn_mm, MATCH_VMANDN_MM, MASK_VMANDN_MM) +DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) +DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) +DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) +DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) +DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) +DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) +DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) +DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) +DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) +DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) +DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) +DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) +DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) +DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) +DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) +DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) +DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) +DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) +DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) +DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) +DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) +DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) +DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) +DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) +DECLARE_INSN(vmorn_mm, MATCH_VMORN_MM, MASK_VMORN_MM) +DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) +DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) +DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) +DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) +DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) +DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) +DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) +DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) +DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) +DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) +DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) +DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) +DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) +DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) +DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) +DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) +DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) +DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) +DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) +DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) +DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) +DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) +DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) +DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) +DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) +DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) +DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) +DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) +DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) +DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) +DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) +DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) +DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) +DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) +DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) +DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) +DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) +DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) +DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) +DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) +DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) +DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) +DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) +DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) +DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) +DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) +DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) +DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) +DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) +DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) +DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) +DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) +DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) +DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) +DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) +DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) +DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) +DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) +DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) +DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) +DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) +DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) +DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) +DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) +DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) +DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) +DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) +DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) +DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) +DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) +DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) +DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) +DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) +DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) +DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) +DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) +DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) +DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) +DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) +DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) +DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) +DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) +DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) +DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) +DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) +DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) +DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) +DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) +DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) +DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) +DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) +DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) +DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) +DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) +DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) +DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) +DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) +DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) +DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) +DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) +DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) +DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) +DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) +DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) +DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) +DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) +DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) +DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) +DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) +DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) +DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) +DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) +DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) +DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) +DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) +DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) +DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) +DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) +DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) +DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) +DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) +DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) +DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) +DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) +DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) +DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) +DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) +DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) +DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) +DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) +DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) +DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) +DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) +DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) +DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) +DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) +DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) +DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) +DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) +DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) +DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) +DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) +DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) +DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) +DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) +DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) +DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) +DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) +DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) +DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) +DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) +DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) +DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) +DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) +DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) +DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) +DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) +DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) +DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) +DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) +DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) +DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) +DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) +DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) +DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) +DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) +DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) +DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) +DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) +DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) +DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) +DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) +DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) +DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) +DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) +DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) +DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) +DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) +DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) +DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) +DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) +DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) +DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) +DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) +DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) +DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) +DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) +DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) +DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) +DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) +DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) +DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) +DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) +DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) +DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) +DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) +DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) +DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) +DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) +DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT) +DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) +DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) +DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) -DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) -DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) -DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) -DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) -DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) -DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) -DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) -DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) -DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) -DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) -DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) -DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) -DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) -DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) -DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) -DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) -DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) -DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) -DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) -DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) -DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) -DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) -DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) -DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) -DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) -DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) -DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) -DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) -DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) -DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) -DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) -DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) -DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) -DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) -DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32) -DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) -DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32) -DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) -DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) -DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) -DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) -DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) -DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) -DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) -DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) -DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) -DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) -DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) -DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) -DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) -DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) -DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) -DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) -DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) -DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) -DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) -DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) -DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) -DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) -DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) -DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) -DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) -DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) -DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) -DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) -DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) -DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) -DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) -DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) -DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) -DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) -DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) -DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) -DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) -DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) -DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) -DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) -DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) -DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) -DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) -DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V) -DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V) -DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V) -DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V) -DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V) -DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V) -DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS) -DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) -DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M) #endif #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) @@ -4391,11 +4556,17 @@ DECLARE_CSR(sideleg, CSR_SIDELEG) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(senvcfg, CSR_SENVCFG) +DECLARE_CSR(sstateen0, CSR_SSTATEEN0) +DECLARE_CSR(sstateen1, CSR_SSTATEEN1) +DECLARE_CSR(sstateen2, CSR_SSTATEEN2) +DECLARE_CSR(sstateen3, CSR_SSTATEEN3) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(stimecmp, CSR_STIMECMP) DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(scontext, CSR_SCONTEXT) DECLARE_CSR(vsstatus, CSR_VSSTATUS) @@ -4406,6 +4577,7 @@ DECLARE_CSR(vsepc, CSR_VSEPC) DECLARE_CSR(vscause, CSR_VSCAUSE) DECLARE_CSR(vstval, CSR_VSTVAL) DECLARE_CSR(vsip, CSR_VSIP) +DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) DECLARE_CSR(vsatp, CSR_VSATP) DECLARE_CSR(hstatus, CSR_HSTATUS) DECLARE_CSR(hedeleg, CSR_HEDELEG) @@ -4414,6 +4586,11 @@ DECLARE_CSR(hie, CSR_HIE) DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) DECLARE_CSR(hgeie, CSR_HGEIE) +DECLARE_CSR(henvcfg, CSR_HENVCFG) +DECLARE_CSR(hstateen0, CSR_HSTATEEN0) +DECLARE_CSR(hstateen1, CSR_HSTATEEN1) +DECLARE_CSR(hstateen2, CSR_HSTATEEN2) +DECLARE_CSR(hstateen3, CSR_HSTATEEN3) DECLARE_CSR(htval, CSR_HTVAL) DECLARE_CSR(hip, CSR_HIP) DECLARE_CSR(hvip, CSR_HVIP) @@ -4421,6 +4598,7 @@ DECLARE_CSR(htinst, CSR_HTINST) DECLARE_CSR(hgatp, CSR_HGATP) DECLARE_CSR(hcontext, CSR_HCONTEXT) DECLARE_CSR(hgeip, CSR_HGEIP) +DECLARE_CSR(scountovf, CSR_SCOUNTOVF) DECLARE_CSR(utvt, CSR_UTVT) DECLARE_CSR(unxti, CSR_UNXTI) DECLARE_CSR(uintstatus, CSR_UINTSTATUS) @@ -4443,6 +4621,11 @@ DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(menvcfg, CSR_MENVCFG) +DECLARE_CSR(mstateen0, CSR_MSTATEEN0) +DECLARE_CSR(mstateen1, CSR_MSTATEEN1) +DECLARE_CSR(mstateen2, CSR_MSTATEEN2) +DECLARE_CSR(mstateen3, CSR_MSTATEEN3) DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) @@ -4455,6 +4638,18 @@ DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpcfg4, CSR_PMPCFG4) +DECLARE_CSR(pmpcfg5, CSR_PMPCFG5) +DECLARE_CSR(pmpcfg6, CSR_PMPCFG6) +DECLARE_CSR(pmpcfg7, CSR_PMPCFG7) +DECLARE_CSR(pmpcfg8, CSR_PMPCFG8) +DECLARE_CSR(pmpcfg9, CSR_PMPCFG9) +DECLARE_CSR(pmpcfg10, CSR_PMPCFG10) +DECLARE_CSR(pmpcfg11, CSR_PMPCFG11) +DECLARE_CSR(pmpcfg12, CSR_PMPCFG12) +DECLARE_CSR(pmpcfg13, CSR_PMPCFG13) +DECLARE_CSR(pmpcfg14, CSR_PMPCFG14) +DECLARE_CSR(pmpcfg15, CSR_PMPCFG15) DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) @@ -4471,6 +4666,55 @@ DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(pmpaddr16, CSR_PMPADDR16) +DECLARE_CSR(pmpaddr17, CSR_PMPADDR17) +DECLARE_CSR(pmpaddr18, CSR_PMPADDR18) +DECLARE_CSR(pmpaddr19, CSR_PMPADDR19) +DECLARE_CSR(pmpaddr20, CSR_PMPADDR20) +DECLARE_CSR(pmpaddr21, CSR_PMPADDR21) +DECLARE_CSR(pmpaddr22, CSR_PMPADDR22) +DECLARE_CSR(pmpaddr23, CSR_PMPADDR23) +DECLARE_CSR(pmpaddr24, CSR_PMPADDR24) +DECLARE_CSR(pmpaddr25, CSR_PMPADDR25) +DECLARE_CSR(pmpaddr26, CSR_PMPADDR26) +DECLARE_CSR(pmpaddr27, CSR_PMPADDR27) +DECLARE_CSR(pmpaddr28, CSR_PMPADDR28) +DECLARE_CSR(pmpaddr29, CSR_PMPADDR29) +DECLARE_CSR(pmpaddr30, CSR_PMPADDR30) +DECLARE_CSR(pmpaddr31, CSR_PMPADDR31) +DECLARE_CSR(pmpaddr32, CSR_PMPADDR32) +DECLARE_CSR(pmpaddr33, CSR_PMPADDR33) +DECLARE_CSR(pmpaddr34, CSR_PMPADDR34) +DECLARE_CSR(pmpaddr35, CSR_PMPADDR35) +DECLARE_CSR(pmpaddr36, CSR_PMPADDR36) +DECLARE_CSR(pmpaddr37, CSR_PMPADDR37) +DECLARE_CSR(pmpaddr38, CSR_PMPADDR38) +DECLARE_CSR(pmpaddr39, CSR_PMPADDR39) +DECLARE_CSR(pmpaddr40, CSR_PMPADDR40) +DECLARE_CSR(pmpaddr41, CSR_PMPADDR41) +DECLARE_CSR(pmpaddr42, CSR_PMPADDR42) +DECLARE_CSR(pmpaddr43, CSR_PMPADDR43) +DECLARE_CSR(pmpaddr44, CSR_PMPADDR44) +DECLARE_CSR(pmpaddr45, CSR_PMPADDR45) +DECLARE_CSR(pmpaddr46, CSR_PMPADDR46) +DECLARE_CSR(pmpaddr47, CSR_PMPADDR47) +DECLARE_CSR(pmpaddr48, CSR_PMPADDR48) +DECLARE_CSR(pmpaddr49, CSR_PMPADDR49) +DECLARE_CSR(pmpaddr50, CSR_PMPADDR50) +DECLARE_CSR(pmpaddr51, CSR_PMPADDR51) +DECLARE_CSR(pmpaddr52, CSR_PMPADDR52) +DECLARE_CSR(pmpaddr53, CSR_PMPADDR53) +DECLARE_CSR(pmpaddr54, CSR_PMPADDR54) +DECLARE_CSR(pmpaddr55, CSR_PMPADDR55) +DECLARE_CSR(pmpaddr56, CSR_PMPADDR56) +DECLARE_CSR(pmpaddr57, CSR_PMPADDR57) +DECLARE_CSR(pmpaddr58, CSR_PMPADDR58) +DECLARE_CSR(pmpaddr59, CSR_PMPADDR59) +DECLARE_CSR(pmpaddr60, CSR_PMPADDR60) +DECLARE_CSR(pmpaddr61, CSR_PMPADDR61) +DECLARE_CSR(pmpaddr62, CSR_PMPADDR62) +DECLARE_CSR(pmpaddr63, CSR_PMPADDR63) +DECLARE_CSR(mseccfg, CSR_MSECCFG) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) @@ -4547,7 +4791,15 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR) +DECLARE_CSR(stimecmph, CSR_STIMECMPH) +DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH) DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH) +DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H) +DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H) +DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H) +DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) @@ -4581,6 +4833,41 @@ DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) DECLARE_CSR(mstatush, CSR_MSTATUSH) +DECLARE_CSR(menvcfgh, CSR_MENVCFGH) +DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H) +DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H) +DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H) +DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H) +DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H) +DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H) +DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H) +DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H) +DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H) +DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H) +DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H) +DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H) +DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H) +DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H) +DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H) +DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H) +DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H) +DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H) +DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H) +DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H) +DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H) +DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H) +DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H) +DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H) +DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H) +DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H) +DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H) +DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H) +DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H) +DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) +DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) +DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) +DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) +DECLARE_CSR(mseccfgh, CSR_MSECCFGH) DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(minstreth, CSR_MINSTRETH) DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) diff --git a/src/target/riscv/opcodes.h b/src/target/riscv/opcodes.h index 8faa154bae..7d17e6eea0 100644 --- a/src/target/riscv/opcodes.h +++ b/src/target/riscv/opcodes.h @@ -191,26 +191,26 @@ static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) return imm_i(offset) | inst_rs1(base) | inst_rd(dest) | MATCH_FLD; } -static uint32_t fmv_x_w(unsigned dest, unsigned src) __attribute__ ((unused)); -static uint32_t fmv_x_w(unsigned dest, unsigned src) +static uint32_t fmv_x_w(unsigned int dest, unsigned int src) __attribute__ ((unused)); +static uint32_t fmv_x_w(unsigned int dest, unsigned int src) { return inst_rs1(src) | inst_rd(dest) | MATCH_FMV_X_W; } -static uint32_t fmv_x_d(unsigned dest, unsigned src) __attribute__ ((unused)); -static uint32_t fmv_x_d(unsigned dest, unsigned src) +static uint32_t fmv_x_d(unsigned int dest, unsigned int src) __attribute__ ((unused)); +static uint32_t fmv_x_d(unsigned int dest, unsigned int src) { return inst_rs1(src) | inst_rd(dest) | MATCH_FMV_X_D; } -static uint32_t fmv_w_x(unsigned dest, unsigned src) __attribute__ ((unused)); -static uint32_t fmv_w_x(unsigned dest, unsigned src) +static uint32_t fmv_w_x(unsigned int dest, unsigned int src) __attribute__ ((unused)); +static uint32_t fmv_w_x(unsigned int dest, unsigned int src) { return inst_rs1(src) | inst_rd(dest) | MATCH_FMV_W_X; } -static uint32_t fmv_d_x(unsigned dest, unsigned src) __attribute__ ((unused)); -static uint32_t fmv_d_x(unsigned dest, unsigned src) +static uint32_t fmv_d_x(unsigned int dest, unsigned int src) __attribute__ ((unused)); +static uint32_t fmv_d_x(unsigned int dest, unsigned int src) { return inst_rs1(src) | inst_rd(dest) | MATCH_FMV_D_X; } diff --git a/src/target/riscv/program.c b/src/target/riscv/program.c index 8e2ce5dbd5..1014137f4f 100644 --- a/src/target/riscv/program.c +++ b/src/target/riscv/program.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #ifdef HAVE_CONFIG_H #include "config.h" @@ -31,7 +31,7 @@ int riscv_program_init(struct riscv_program *p, struct target *target) int riscv_program_write(struct riscv_program *program) { - for (unsigned i = 0; i < program->instruction_count; ++i) { + for (unsigned int i = 0; i < program->instruction_count; ++i) { LOG_DEBUG("debug_buffer[%02x] = DASM(0x%08x)", i, program->debug_buffer[i]); if (riscv_write_debug_buffer(program->target, i, program->debug_buffer[i]) != ERROR_OK) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index ae0b6e481b..f4a7d0e5ca 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Support for RISC-V, debug version 0.11. This was never an officially adopted @@ -227,10 +227,10 @@ static int get_register(struct target *target, riscv_reg_t *value, int regid); static riscv011_info_t *get_info(const struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; assert(info); assert(info->version_specific); - return (riscv011_info_t *) info->version_specific; + return info->version_specific; } static unsigned int slot_offset(const struct target *target, slot_t slot) @@ -412,7 +412,7 @@ static void dump_field(const struct scan_field *field) log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", - "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x", + "%ub %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x", field->num_bits, op_string[out_op], out_interrupt, out_haltnot, out_data, out_address, @@ -474,7 +474,7 @@ static uint64_t dbus_read(struct target *target, uint16_t address) * While somewhat nonintuitive, this is an efficient way to get the data. */ - unsigned i = 0; + unsigned int i = 0; do { status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0); if (status == DBUS_STATUS_BUSY) @@ -495,7 +495,7 @@ static uint64_t dbus_read(struct target *target, uint16_t address) static void dbus_write(struct target *target, uint16_t address, uint64_t value) { dbus_status_t status = DBUS_STATUS_BUSY; - unsigned i = 0; + unsigned int i = 0; while (status == DBUS_STATUS_BUSY && i++ < 256) { status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value); if (status == DBUS_STATUS_BUSY) @@ -656,13 +656,13 @@ static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt) } static uint32_t scans_get_u32(scans_t *scans, unsigned int index, - unsigned first, unsigned num) + unsigned int first, unsigned int num) { return buf_get_u32(scans->in + scans->scan_size * index, first, num); } static uint64_t scans_get_u64(scans_t *scans, unsigned int index, - unsigned first, unsigned num) + unsigned int first, unsigned int num) { return buf_get_u64(scans->in + scans->scan_size * index, first, num); } @@ -699,7 +699,7 @@ static bits_t read_bits(struct target *target) }; do { - unsigned i = 0; + unsigned int i = 0; do { status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0); if (status == DBUS_STATUS_BUSY) { @@ -1192,7 +1192,7 @@ static int full_step(struct target *target, bool announce) return ERROR_OK; } -static int resume(struct target *target, int debug_execution, bool step) +static int resume(struct target *target, bool debug_execution, bool step) { if (debug_execution) { LOG_ERROR("TODO: debug_execution is true"); @@ -1296,7 +1296,7 @@ static int register_write(struct target *target, unsigned int number, int result = update_mstatus_actual(target); if (result != ERROR_OK) return result; - unsigned i = 0; + unsigned int i = 0; if ((info->mstatus_actual & MSTATUS_FS) == 0) { info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1); cache_set_load(target, i++, S0, SLOT1); @@ -1352,7 +1352,7 @@ static int get_register(struct target *target, riscv_reg_t *value, int regid) int result = update_mstatus_actual(target); if (result != ERROR_OK) return result; - unsigned i = 0; + unsigned int i = 0; if ((info->mstatus_actual & MSTATUS_FS) == 0) { info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1); cache_set_load(target, i++, S0, SLOT1); @@ -1408,7 +1408,10 @@ static int halt(struct target *target) static void deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; + if (!info) + return; + free(info->version_specific); info->version_specific = NULL; } @@ -1436,8 +1439,8 @@ static int strict_step(struct target *target, bool announce) return ERROR_OK; } -static int step(struct target *target, int current, target_addr_t address, - int handle_breakpoints) +static int step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE); @@ -1535,7 +1538,7 @@ static int examine(struct target *target) /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */ cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4)); cache_set_jump(target, 5); - for (unsigned i = 6; i < info->dramsize; i++) + for (unsigned int i = 6; i < info->dramsize; i++) cache_set32(target, i, i * 0x01020304); cache_write(target, 0, false); @@ -1549,7 +1552,7 @@ static int examine(struct target *target) uint32_t word0 = cache_get32(target, 0); uint32_t word1 = cache_get32(target, 1); - riscv_info_t *generic_info = (riscv_info_t *) target->arch_info; + struct riscv_info *generic_info = riscv_info(target); if (word0 == 1 && word1 == 0) { generic_info->xlen = 32; } else if (word0 == 0xffffffff && word1 == 3) { @@ -1566,7 +1569,7 @@ static int examine(struct target *target) LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target)); if (read_remote_csr(target, &r->misa, CSR_MISA) != ERROR_OK) { - const unsigned old_csr_misa = 0xf10; + const unsigned int old_csr_misa = 0xf10; LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA, old_csr_misa); if (read_remote_csr(target, &r->misa, old_csr_misa) != ERROR_OK) { @@ -1648,7 +1651,7 @@ static riscv_error_t handle_halt_routine(struct target *target) unsigned int dbus_busy = 0; unsigned int interrupt_set = 0; - unsigned result = 0; + unsigned int result = 0; uint64_t value = 0; reg_cache_set(target, 0, 0); /* The first scan result is the result from something old we don't care @@ -1926,8 +1929,9 @@ static int riscv011_poll(struct target *target) return poll_target(target, true); } -static int riscv011_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int riscv011_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution) { RISCV_INFO(r); jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE); @@ -2013,7 +2017,7 @@ static int read_memory(struct target *target, target_addr_t address, cache_write(target, CACHE_NO_READ, false); riscv011_info_t *info = get_info(target); - const unsigned max_batch_size = 256; + const unsigned int max_batch_size = 256; scans_t *scans = scans_new(target, max_batch_size); if (!scans) return ERROR_FAIL; @@ -2171,7 +2175,7 @@ static int write_memory(struct target *target, target_addr_t address, if (setup_write_memory(target, size) != ERROR_OK) return ERROR_FAIL; - const unsigned max_batch_size = 256; + const unsigned int max_batch_size = 256; scans_t *scans = scans_new(target, max_batch_size); if (!scans) return ERROR_FAIL; @@ -2294,7 +2298,7 @@ static int arch_state(struct target *target) return ERROR_OK; } -COMMAND_HELPER(riscv011_print_info, struct target *target) +static COMMAND_HELPER(riscv011_print_info, struct target *target) { /* Abstract description. */ riscv_print_info_line(CMD, "target", "memory.read_while_running8", 0); diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1b1450a7dc..bb450ce623 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Support for RISC-V, debug version 0.13, which is currently (2/4/17) the @@ -34,7 +34,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step, bool use_hasel); static void riscv013_clear_abstract_error(struct target *target); -/* Implementations of the functions in riscv_info_t. */ +/* Implementations of the functions in struct riscv_info. */ static int riscv013_get_register(struct target *target, riscv_reg_t *value, int rid); static int riscv013_set_register(struct target *target, int regid, uint64_t value); @@ -48,10 +48,9 @@ static int riscv013_on_step(struct target *target); static int riscv013_resume_prep(struct target *target); static bool riscv013_is_halted(struct target *target); static enum riscv_halt_reason riscv013_halt_reason(struct target *target); -static int riscv013_write_debug_buffer(struct target *target, unsigned index, +static int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t d); -static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned - index); +static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index); static int riscv013_execute_debug_buffer(struct target *target); static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d); static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); @@ -59,18 +58,12 @@ static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); static int register_read(struct target *target, uint64_t *value, uint32_t number); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); -static int register_write_direct(struct target *target, unsigned number, +static int register_write_direct(struct target *target, unsigned int number, uint64_t value); static int read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment); static int write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer); -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, - uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); -void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t *write_data, - uint32_t write_size, uint32_t sbcs); -void read_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs); /** * Since almost everything can be accomplish by scanning the dbus register, all @@ -138,7 +131,7 @@ typedef enum { typedef struct { struct list_head list; - int abs_chain_position; + unsigned int abs_chain_position; /* The number of harts connected to this DM. */ int hart_count; @@ -162,13 +155,13 @@ typedef struct { typedef struct { /* The indexed used to address this hart in its DM. */ - unsigned index; + unsigned int index; /* Number of address bits in the dbus register. */ - unsigned abits; + unsigned int abits; /* Number of abstract command data registers. */ - unsigned datacount; + unsigned int datacount; /* Number of words in the Program Buffer. */ - unsigned progbufsize; + unsigned int progbufsize; /* We cache the read-only bits of sbcs here. */ uint32_t sbcs; @@ -215,20 +208,20 @@ typedef struct { int16_t dataaddr; /* The width of the hartsel field. */ - unsigned hartsellen; + unsigned int hartsellen; /* DM that provides access to this target. */ dm013_info_t *dm; } riscv013_info_t; -LIST_HEAD(dm_list); +static OOCD_LIST_HEAD(dm_list); static riscv013_info_t *get_info(const struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; assert(info); assert(info->version_specific); - return (riscv013_info_t *) info->version_specific; + return info->version_specific; } /** @@ -236,13 +229,13 @@ static riscv013_info_t *get_info(const struct target *target) * global list of DMs. If it's not in there, then create one and initialize it * to 0. */ -dm013_info_t *get_dm(struct target *target) +static dm013_info_t *get_dm(struct target *target) { RISCV013_INFO(info); if (info->dm) return info->dm; - int abs_chain_position = target->tap->abs_chain_position; + unsigned int abs_chain_position = target->tap->abs_chain_position; dm013_info_t *entry; dm013_info_t *dm = NULL; @@ -296,10 +289,10 @@ static uint32_t set_hartsel(uint32_t initial, uint32_t index) return initial; } -static void decode_dmi(char *text, unsigned address, unsigned data) +static void decode_dmi(char *text, unsigned int address, unsigned int data) { static const struct { - unsigned address; + unsigned int address; uint64_t mask; const char *name; } description[] = { @@ -356,10 +349,10 @@ static void decode_dmi(char *text, unsigned address, unsigned data) }; text[0] = 0; - for (unsigned i = 0; i < ARRAY_SIZE(description); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) { if (description[i].address == address) { uint64_t mask = description[i].mask; - unsigned value = get_field(data, mask); + unsigned int value = get_field(data, mask); if (value) { if (i > 0) *(text++) = ' '; @@ -395,7 +388,7 @@ static void dump_field(int idle, const struct scan_field *field) log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", - "%db %s %08x @%02x -> %s %08x @%02x; %di", + "%ub %s %08x @%02x -> %s %08x @%02x; %di", field->num_bits, op_string[out_op], out_data, out_address, status_string[in_op], in_data, in_address, idle); @@ -474,7 +467,7 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in, { riscv013_info_t *info = get_info(target); RISCV_INFO(r); - unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH; + unsigned int num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH; size_t num_bytes = (num_bits + 7) / 8; uint8_t in[num_bytes]; uint8_t out[num_bytes]; @@ -604,6 +597,7 @@ static int dmi_op_timeout(struct target *target, uint32_t *data_in, break; } else { LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status); + dtmcontrol_scan(target, DTM_DTMCS_DMIRESET); return ERROR_FAIL; } if (time(NULL) - start > timeout_sec) @@ -636,6 +630,7 @@ static int dmi_op_timeout(struct target *target, uint32_t *data_in, LOG_ERROR("Failed %s (NOP) at 0x%x; status=%d", op_name, address, status); } + dtmcontrol_scan(target, DTM_DTMCS_DMIRESET); return ERROR_FAIL; } if (time(NULL) - start > timeout_sec) @@ -683,8 +678,8 @@ static int dmi_write_exec(struct target *target, uint32_t address, return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, true, ensure_success); } -int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus, - bool authenticated, unsigned timeout_sec) +static int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus, + bool authenticated, unsigned int timeout_sec) { int result = dmi_op_timeout(target, dmstatus, NULL, DMI_OP_READ, DM_DMSTATUS, 0, timeout_sec, false, true); @@ -705,7 +700,7 @@ int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus, return ERROR_OK; } -int dmstatus_read(struct target *target, uint32_t *dmstatus, +static int dmstatus_read(struct target *target, uint32_t *dmstatus, bool authenticated) { return dmstatus_read_timeout(target, dmstatus, authenticated, @@ -721,7 +716,7 @@ static void increase_ac_busy_delay(struct target *target) info->ac_busy_delay); } -uint32_t abstract_register_size(unsigned width) +static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width) { switch (width) { case 32: @@ -811,12 +806,12 @@ static int execute_abstract_command(struct target *target, uint32_t command) return ERROR_OK; } -static riscv_reg_t read_abstract_arg(struct target *target, unsigned index, - unsigned size_bits) +static riscv_reg_t read_abstract_arg(struct target *target, unsigned int index, + unsigned int size_bits) { riscv_reg_t value = 0; uint32_t v; - unsigned offset = index * size_bits / 32; + unsigned int offset = index * size_bits / 32; switch (size_bits) { default: LOG_ERROR("Unsupported size: %d bits", size_bits); @@ -832,10 +827,10 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index, return value; } -static int write_abstract_arg(struct target *target, unsigned index, - riscv_reg_t value, unsigned size_bits) +static int write_abstract_arg(struct target *target, unsigned int index, + riscv_reg_t value, unsigned int size_bits) { - unsigned offset = index * size_bits / 32; + unsigned int offset = index * size_bits / 32; switch (size_bits) { default: LOG_ERROR("Unsupported size: %d bits", size_bits); @@ -853,7 +848,7 @@ static int write_abstract_arg(struct target *target, unsigned index, * @par size in bits */ static uint32_t access_register_command(struct target *target, uint32_t number, - unsigned size, uint32_t flags) + unsigned int size, uint32_t flags) { uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0); switch (size) { @@ -895,7 +890,7 @@ static uint32_t access_register_command(struct target *target, uint32_t number, } static int register_read_abstract(struct target *target, uint64_t *value, - uint32_t number, unsigned size) + uint32_t number, unsigned int size) { RISCV013_INFO(info); @@ -933,7 +928,7 @@ static int register_read_abstract(struct target *target, uint64_t *value, } static int register_write_abstract(struct target *target, uint32_t number, - uint64_t value, unsigned size) + uint64_t value, unsigned int size) { RISCV013_INFO(info); @@ -972,7 +967,7 @@ static int register_write_abstract(struct target *target, uint32_t number, * Sets the AAMSIZE field of a memory access abstract command based on * the width (bits). */ -static uint32_t abstract_memory_size(unsigned width) +static uint32_t abstract_memory_size(unsigned int width) { switch (width) { case 8: @@ -995,7 +990,7 @@ static uint32_t abstract_memory_size(unsigned width) * Creates a memory access abstract command. */ static uint32_t access_memory_command(struct target *target, bool virtual, - unsigned width, bool postincrement, bool write) + unsigned int width, bool postincrement, bool write) { uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2); command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual); @@ -1138,7 +1133,7 @@ typedef struct { static int scratch_reserve(struct target *target, scratch_mem_t *scratch, struct riscv_program *program, - unsigned size_bytes) + unsigned int size_bytes) { riscv_addr_t alignment = 1; while (alignment < size_bytes) @@ -1170,7 +1165,7 @@ static int scratch_reserve(struct target *target, return ERROR_FAIL; /* Allow for ebreak at the end of the program. */ - unsigned program_size = (program->instruction_count + 1) * 4; + unsigned int program_size = (program->instruction_count + 1) * 4; scratch->hart_address = (info->progbuf_address + program_size + alignment - 1) & ~(alignment - 1); if ((info->progbuf_writable == YNM_YES) && @@ -1275,7 +1270,7 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch, } /** Return register size in bits. */ -static unsigned register_size(struct target *target, unsigned number) +static unsigned int register_size(struct target *target, unsigned int number) { /* If reg_cache hasn't been initialized yet, make a guess. We need this for * when this function is called during examine(). */ @@ -1285,7 +1280,7 @@ static unsigned register_size(struct target *target, unsigned number) return riscv_xlen(target); } -static bool has_sufficient_progbuf(struct target *target, unsigned size) +static bool has_sufficient_progbuf(struct target *target, unsigned int size) { RISCV013_INFO(info); RISCV_INFO(r); @@ -1297,7 +1292,7 @@ static bool has_sufficient_progbuf(struct target *target, unsigned size) * Immediately write the new value to the requested register. This mechanism * bypasses any caches. */ -static int register_write_direct(struct target *target, unsigned number, +static int register_write_direct(struct target *target, unsigned int number, uint64_t value) { LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target), @@ -1524,7 +1519,10 @@ static int wait_for_authbusy(struct target *target, uint32_t *dmstatus) static void deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; + if (!info) + return; + free(info->version_specific); /* TODO: free register arch_info */ info->version_specific = NULL; @@ -1538,7 +1536,7 @@ static int set_haltgroup(struct target *target, bool *supported) uint32_t read; if (dmi_read(target, &read, DM_DMCS2) != ERROR_OK) return ERROR_FAIL; - *supported = get_field(read, DM_DMCS2_GROUP) == (unsigned)target->smp; + *supported = get_field(read, DM_DMCS2_GROUP) == target->smp; return ERROR_OK; } @@ -1835,7 +1833,7 @@ static int riscv013_hart_count(struct target *target) } /* Try to find out the widest memory access size depending on the selected memory access methods. */ -static unsigned riscv013_data_bits(struct target *target) +static unsigned int riscv013_data_bits(struct target *target) { RISCV013_INFO(info); RISCV_INFO(r); @@ -1870,7 +1868,7 @@ static unsigned riscv013_data_bits(struct target *target) return 32; } -COMMAND_HELPER(riscv013_print_info, struct target *target) +static COMMAND_HELPER(riscv013_print_info, struct target *target) { RISCV013_INFO(info); @@ -1905,12 +1903,12 @@ COMMAND_HELPER(riscv013_print_info, struct target *target) } static int prep_for_vector_access(struct target *target, uint64_t *vtype, - uint64_t *vl, unsigned *debug_vl) + uint64_t *vl, unsigned int *debug_vl) { RISCV_INFO(r); /* TODO: this continuous save/restore is terrible for performance. */ /* Write vtype and vl. */ - unsigned encoded_vsew; + unsigned int encoded_vsew; switch (riscv_xlen(target)) { case 32: encoded_vsew = 2; @@ -1966,12 +1964,12 @@ static int riscv013_get_register_buf(struct target *target, return ERROR_FAIL; uint64_t vtype, vl; - unsigned debug_vl; + unsigned int debug_vl; if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK) return ERROR_FAIL; - unsigned vnum = regno - GDB_REGNO_V0; - unsigned xlen = riscv_xlen(target); + unsigned int vnum = regno - GDB_REGNO_V0; + unsigned int xlen = riscv_xlen(target); struct riscv_program program; riscv_program_init(&program, target); @@ -1979,7 +1977,7 @@ static int riscv013_get_register_buf(struct target *target, riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true)); int result = ERROR_OK; - for (unsigned i = 0; i < debug_vl; i++) { + for (unsigned int i = 0; i < debug_vl; i++) { /* Executing the program might result in an exception if there is some * issue with the vector implementation/instructions we're using. If that * happens, attempt to restore as usual. We may have clobbered the @@ -2025,18 +2023,18 @@ static int riscv013_set_register_buf(struct target *target, return ERROR_FAIL; uint64_t vtype, vl; - unsigned debug_vl; + unsigned int debug_vl; if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK) return ERROR_FAIL; - unsigned vnum = regno - GDB_REGNO_V0; - unsigned xlen = riscv_xlen(target); + unsigned int vnum = regno - GDB_REGNO_V0; + unsigned int xlen = riscv_xlen(target); struct riscv_program program; riscv_program_init(&program, target); riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true)); int result = ERROR_OK; - for (unsigned i = 0; i < debug_vl; i++) { + for (unsigned int i = 0; i < debug_vl; i++) { if (register_write_direct(target, GDB_REGNO_S0, buf_get_u64(value, xlen * i, xlen)) != ERROR_OK) return ERROR_FAIL; @@ -2304,7 +2302,6 @@ static int init_target(struct command_context *cmd_ctx, generic_info->dmi_read = &dmi_read; generic_info->dmi_write = &dmi_write; generic_info->read_memory = read_memory; - generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->hart_count = &riscv013_hart_count; generic_info->data_bits = &riscv013_data_bits; generic_info->print_info = &riscv013_print_info; @@ -2356,9 +2353,7 @@ static int assert_reset(struct target *target) /* TODO: Try to use hasel in dmcontrol */ /* Set haltreq for each hart. */ - uint32_t control = control_base; - - control = set_hartsel(control_base, target->coreid); + uint32_t control = set_hartsel(control_base, target->coreid); control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); dmi_write(target, DM_DMCONTROL, control); @@ -2480,7 +2475,7 @@ static int execute_fence(struct target *target) } static void log_memory_access(target_addr_t address, uint64_t value, - unsigned size_bytes, bool read) + unsigned int size_bytes, bool read) { if (debug_level < LOG_LVL_DEBUG) return; @@ -2528,7 +2523,7 @@ static int read_memory_bus_word(struct target *target, target_addr_t address, static target_addr_t sb_read_address(struct target *target) { RISCV013_INFO(info); - unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); + unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); target_addr_t address = 0; uint32_t v; if (sbasize > 32) { @@ -2721,7 +2716,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, for (uint32_t i = (next_address - address) / size; i < count - 1; i++) { for (int j = (size - 1) / 4; j >= 0; j--) { uint32_t value; - unsigned attempt = 0; + unsigned int attempt = 0; while (1) { if (attempt++ > 100) { LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT, @@ -2749,7 +2744,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, uint32_t sbcs_read = 0; if (count > 1) { uint32_t value; - unsigned attempt = 0; + unsigned int attempt = 0; while (1) { if (attempt++ > 100) { LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT, @@ -2797,7 +2792,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, continue; } - unsigned error = get_field(sbcs_read, DM_SBCS_SBERROR); + unsigned int error = get_field(sbcs_read, DM_SBCS_SBERROR); if (error == 0) { next_address = end_address; } else { @@ -2963,7 +2958,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address, memset(buffer, 0, count * size); /* Convert the size (bytes) to width (bits) */ - unsigned width = size << 3; + unsigned int width = size << 3; /* Create the command (physical address, postincrement, read) */ uint32_t command = access_memory_command(target, false, width, use_aampostincrement, false); @@ -3039,7 +3034,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address, size, address); /* Convert the size (bytes) to width (bits) */ - unsigned width = size << 3; + unsigned int width = size << 3; /* Create the command (physical address, postincrement, write) */ uint32_t command = access_memory_command(target, false, width, use_aampostincrement, true); @@ -3149,7 +3144,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres /* read_addr is the next address that the hart will read from, which is the * value in s0. */ - unsigned index = 2; + unsigned int index = 2; while (index < count) { riscv_addr_t read_addr = address + index * increment; LOG_DEBUG("i=%d, count=%d, read_addr=0x%" PRIx64, index, count, read_addr); @@ -3166,8 +3161,8 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres if (!batch) return ERROR_FAIL; - unsigned reads = 0; - for (unsigned j = index; j < count; j++) { + unsigned int reads = 0; + for (unsigned int j = index; j < count; j++) { if (size > 4) riscv_batch_add_dmi_read(batch, DM_DATA1); riscv_batch_add_dmi_read(batch, DM_DATA0); @@ -3190,8 +3185,8 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres return ERROR_FAIL; info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); - unsigned next_index; - unsigned ignore_last = 0; + unsigned int next_index; + unsigned int ignore_last = 0; switch (info->cmderr) { case CMDERR_NONE: LOG_DEBUG("successful (partial?) memory read"); @@ -3260,9 +3255,9 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres /* Now read whatever we got out of the batch. */ dmi_status_t status = DMI_STATUS_SUCCESS; - unsigned read = 0; + unsigned int read = 0; assert(index >= 2); - for (unsigned j = index - 2; j < index + reads; j++) { + for (unsigned int j = index - 2; j < index + reads; j++) { assert(j < count); LOG_DEBUG("index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d", index, reads, next_index, ignore_last, j); @@ -3871,9 +3866,9 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, goto error; /* To write another word, we put it in S1 and execute the program. */ - unsigned start = (cur_addr - address) / size; - for (unsigned i = start; i < count; ++i) { - unsigned offset = size*i; + unsigned int start = (cur_addr - address) / size; + for (unsigned int i = start; i < count; ++i) { + unsigned int offset = size * i; const uint8_t *t_buffer = buffer + offset; uint64_t value = buf_get_u64(t_buffer, 0, 8 * size); @@ -4164,18 +4159,18 @@ static int select_prepped_harts(struct target *target, bool *use_hasel) } assert(dm->hart_count); - unsigned hawindow_count = (dm->hart_count + 31) / 32; + unsigned int hawindow_count = (dm->hart_count + 31) / 32; uint32_t hawindow[hawindow_count]; memset(hawindow, 0, sizeof(uint32_t) * hawindow_count); target_list_t *entry; - unsigned total_selected = 0; + unsigned int total_selected = 0; list_for_each_entry(entry, &dm->target_list, list) { struct target *t = entry->target; - riscv_info_t *r = riscv_info(t); + struct riscv_info *r = riscv_info(t); riscv013_info_t *info = get_info(t); - unsigned index = info->index; + unsigned int index = info->index; LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped); r->selected = r->prepped; if (r->prepped) { @@ -4192,7 +4187,7 @@ static int select_prepped_harts(struct target *target, bool *use_hasel) return ERROR_OK; } - for (unsigned i = 0; i < hawindow_count; i++) { + for (unsigned int i = 0; i < hawindow_count; i++) { if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK) return ERROR_FAIL; if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK) @@ -4350,7 +4345,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target) return RISCV_HALT_UNKNOWN; } -int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data) +int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data) { dm013_info_t *dm = get_dm(target); if (!dm) @@ -4365,7 +4360,7 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins return ERROR_OK; } -riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index) +riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index) { uint32_t value; dmi_read(target, &value, DM_PROGBUF0 + index); @@ -4407,358 +4402,6 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } -/* Helper function for riscv013_test_sba_config_reg */ -static int get_max_sbaccess(struct target *target) -{ - RISCV013_INFO(info); - - uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32); - uint32_t sbaccess16 = get_field(info->sbcs, DM_SBCS_SBACCESS16); - uint32_t sbaccess8 = get_field(info->sbcs, DM_SBCS_SBACCESS8); - - if (sbaccess128) - return 4; - else if (sbaccess64) - return 3; - else if (sbaccess32) - return 2; - else if (sbaccess16) - return 1; - else if (sbaccess8) - return 0; - else - return -1; -} - -static uint32_t get_num_sbdata_regs(struct target *target) -{ - RISCV013_INFO(info); - - uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32); - - if (sbaccess128) - return 4; - else if (sbaccess64) - return 2; - else if (sbaccess32) - return 1; - else - return 0; -} - -static int riscv013_test_sba_config_reg(struct target *target, - target_addr_t legal_address, uint32_t num_words, - target_addr_t illegal_address, bool run_sbbusyerror_test) -{ - LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); - - uint32_t tests_failed = 0; - - uint32_t rd_val; - uint32_t sbcs_orig; - dmi_read(target, &sbcs_orig, DM_SBCS); - - uint32_t sbcs = sbcs_orig; - bool test_passed; - - int max_sbaccess = get_max_sbaccess(target); - - if (max_sbaccess == -1) { - LOG_ERROR("System Bus Access not supported in this config."); - return ERROR_FAIL; - } - - if (get_field(sbcs, DM_SBCS_SBVERSION) != 1) { - LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", - get_field(sbcs, DM_SBCS_SBVERSION)); - return ERROR_FAIL; - } - - uint32_t num_sbdata_regs = get_num_sbdata_regs(target); - assert(num_sbdata_regs); - - uint32_t rd_buf[num_sbdata_regs]; - - /* Test 1: Simple write/read test */ - test_passed = true; - sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 0); - dmi_write(target, DM_SBCS, sbcs); - - uint32_t test_patterns[4] = {0xdeadbeef, 0xfeedbabe, 0x12345678, 0x08675309}; - for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { - sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess); - dmi_write(target, DM_SBCS, sbcs); - - uint32_t compare_mask = (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff; - - for (uint32_t i = 0; i < num_words; i++) { - uint32_t addr = legal_address + (i << sbaccess); - uint32_t wr_data[num_sbdata_regs]; - for (uint32_t j = 0; j < num_sbdata_regs; j++) - wr_data[j] = test_patterns[j] + i; - write_memory_sba_simple(target, addr, wr_data, num_sbdata_regs, sbcs); - } - - for (uint32_t i = 0; i < num_words; i++) { - uint32_t addr = legal_address + (i << sbaccess); - read_memory_sba_simple(target, addr, rd_buf, num_sbdata_regs, sbcs); - for (uint32_t j = 0; j < num_sbdata_regs; j++) { - if (((test_patterns[j]+i)&compare_mask) != (rd_buf[j]&compare_mask)) { - LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x," - "expected val = %x, read val = %x", addr, test_patterns[j]+i, rd_buf[j]); - test_passed = false; - tests_failed++; - } - } - } - } - if (test_passed) - LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED."); - - /* Test 2: Address autoincrement test */ - target_addr_t curr_addr; - target_addr_t prev_addr; - test_passed = true; - sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 1); - dmi_write(target, DM_SBCS, sbcs); - - for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { - sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess); - dmi_write(target, DM_SBCS, sbcs); - - dmi_write(target, DM_SBADDRESS0, legal_address); - read_sbcs_nonbusy(target, &sbcs); - curr_addr = legal_address; - for (uint32_t i = 0; i < num_words; i++) { - prev_addr = curr_addr; - read_sbcs_nonbusy(target, &sbcs); - curr_addr = sb_read_address(target); - if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { - LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess); - test_passed = false; - tests_failed++; - } - dmi_write(target, DM_SBDATA0, i); - } - - read_sbcs_nonbusy(target, &sbcs); - - dmi_write(target, DM_SBADDRESS0, legal_address); - - uint32_t val; - sbcs = set_field(sbcs, DM_SBCS_SBREADONDATA, 1); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &val, DM_SBDATA0); /* Dummy read to trigger first system bus read */ - curr_addr = legal_address; - for (uint32_t i = 0; i < num_words; i++) { - prev_addr = curr_addr; - read_sbcs_nonbusy(target, &sbcs); - curr_addr = sb_read_address(target); - if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { - LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); - test_passed = false; - tests_failed++; - } - dmi_read(target, &val, DM_SBDATA0); - read_sbcs_nonbusy(target, &sbcs); - if (i != val) { - LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," - "expected val = %x, read val = %x.", i, val); - test_passed = false; - tests_failed++; - } - } - } - if (test_passed) - LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED."); - - /* Test 3: Read from illegal address */ - read_memory_sba_simple(target, illegal_address, rd_buf, 1, sbcs_orig); - - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 2) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 0) - LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED."); - else - LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to clear to 0."); - } else { - LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to set error code."); - } - - /* Test 4: Write to illegal address */ - write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig); - - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 2) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 0) - LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); - else { - LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0."); - tests_failed++; - } - } else { - LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to set error code."); - tests_failed++; - } - - /* Test 5: Write with unsupported sbaccess size */ - uint32_t sbaccess128 = get_field(sbcs_orig, DM_SBCS_SBACCESS128); - - if (sbaccess128) { - LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported."); - } else { - sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 4); - - write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs); - - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 4) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 4); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 0) - LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED."); - else { - LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0."); - tests_failed++; - } - } else { - LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code."); - tests_failed++; - } - } - - /* Test 6: Write to misaligned address */ - sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 1); - - write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs); - - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 3) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 3); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBERROR) == 0) - LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED"); - else { - LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0."); - tests_failed++; - } - } else { - LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code."); - tests_failed++; - } - - /* Test 7: Set sbbusyerror, only run this case in simulation as it is likely - * impossible to hit otherwise */ - if (run_sbbusyerror_test) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBREADONADDR, 1); - dmi_write(target, DM_SBCS, sbcs); - - for (int i = 0; i < 16; i++) - dmi_write(target, DM_SBDATA0, 0xdeadbeef); - - for (int i = 0; i < 16; i++) - dmi_write(target, DM_SBADDRESS0, legal_address); - - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBBUSYERROR)) { - sbcs = set_field(sbcs_orig, DM_SBCS_SBBUSYERROR, 1); - dmi_write(target, DM_SBCS, sbcs); - dmi_read(target, &rd_val, DM_SBCS); - if (get_field(rd_val, DM_SBCS_SBBUSYERROR) == 0) - LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED."); - else { - LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0."); - tests_failed++; - } - } else { - LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code."); - tests_failed++; - } - } - - if (tests_failed == 0) { - LOG_INFO("ALL TESTS PASSED"); - return ERROR_OK; - } else { - LOG_ERROR("%d TESTS FAILED", tests_failed); - return ERROR_FAIL; - } - -} - -void write_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t *write_data, uint32_t write_size, uint32_t sbcs) -{ - RISCV013_INFO(info); - - uint32_t rd_sbcs; - uint32_t masked_addr; - - uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE); - - read_sbcs_nonbusy(target, &rd_sbcs); - - uint32_t sbcs_no_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 0); - dmi_write(target, DM_SBCS, sbcs_no_readonaddr); - - for (uint32_t i = 0; i < sba_size/32; i++) { - masked_addr = (addr >> 32*i) & 0xffffffff; - - if (i != 3) - dmi_write(target, DM_SBADDRESS0+i, masked_addr); - else - dmi_write(target, DM_SBADDRESS3, masked_addr); - } - - /* Write SBDATA registers starting with highest address, since write to - * SBDATA0 triggers write */ - for (int i = write_size-1; i >= 0; i--) - dmi_write(target, DM_SBDATA0+i, write_data[i]); -} - -void read_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs) -{ - RISCV013_INFO(info); - - uint32_t rd_sbcs; - uint32_t masked_addr; - - uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE); - - read_sbcs_nonbusy(target, &rd_sbcs); - - uint32_t sbcs_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 1); - dmi_write(target, DM_SBCS, sbcs_readonaddr); - - /* Write addresses starting with highest address register */ - for (int i = sba_size/32-1; i >= 0; i--) { - masked_addr = (addr >> 32*i) & 0xffffffff; - - if (i != 3) - dmi_write(target, DM_SBADDRESS0+i, masked_addr); - else - dmi_write(target, DM_SBADDRESS3, masked_addr); - } - - read_sbcs_nonbusy(target, &rd_sbcs); - - for (uint32_t i = 0; i < read_size; i++) - dmi_read(target, &(rd_buf[i]), DM_SBDATA0+i); -} - int riscv013_dmi_write_u64_bits(struct target *target) { RISCV013_INFO(info); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index f79239a9d4..11ef8f9b92 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <assert.h> #include <stdlib.h> @@ -109,37 +109,37 @@ typedef enum slot { #define MAX_HWBPS 16 #define DRAM_CACHE_SIZE 16 -uint8_t ir_dtmcontrol[4] = {DTMCONTROL}; +static uint8_t ir_dtmcontrol[4] = {DTMCONTROL}; struct scan_field select_dtmcontrol = { .in_value = NULL, .out_value = ir_dtmcontrol }; -uint8_t ir_dbus[4] = {DBUS}; +static uint8_t ir_dbus[4] = {DBUS}; struct scan_field select_dbus = { .in_value = NULL, .out_value = ir_dbus }; -uint8_t ir_idcode[4] = {0x1}; +static uint8_t ir_idcode[4] = {0x1}; struct scan_field select_idcode = { .in_value = NULL, .out_value = ir_idcode }; -bscan_tunnel_type_t bscan_tunnel_type; +static bscan_tunnel_type_t bscan_tunnel_type; int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */ static const uint8_t bscan_zero[4] = {0}; static const uint8_t bscan_one[4] = {1}; -uint8_t ir_user4[4]; -struct scan_field select_user4 = { +static uint8_t ir_user4[4]; +static struct scan_field select_user4 = { .in_value = NULL, .out_value = ir_user4 }; -uint8_t bscan_tunneled_ir_width[4] = {5}; /* overridden by assignment in riscv_init_target */ -struct scan_field _bscan_tunnel_data_register_select_dmi[] = { +static uint8_t bscan_tunneled_ir_width[4] = {5}; /* overridden by assignment in riscv_init_target */ +static struct scan_field _bscan_tunnel_data_register_select_dmi[] = { { .num_bits = 3, .out_value = bscan_zero, @@ -162,7 +162,7 @@ struct scan_field _bscan_tunnel_data_register_select_dmi[] = { } }; -struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { +static struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { { .num_bits = 1, .out_value = bscan_zero, @@ -184,11 +184,11 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { .in_value = NULL, } }; -struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi; -uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi); +static struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi; +static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi); -struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi; -uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi); +static struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi; +static uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi); struct trigger { uint64_t address; @@ -205,7 +205,7 @@ int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC; /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/ int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC; -bool riscv_enable_virt2phys = true; +static bool riscv_enable_virt2phys = true; bool riscv_ebreakm = true; bool riscv_ebreaks = true; bool riscv_ebreaku = true; @@ -217,7 +217,7 @@ static enum { RO_REVERSED } resume_order; -const virt2phys_info_t sv32 = { +static const virt2phys_info_t sv32 = { .name = "Sv32", .va_bits = 32, .level = 2, @@ -230,7 +230,7 @@ const virt2phys_info_t sv32 = { .pa_ppn_mask = {0x3ff, 0xfff}, }; -const virt2phys_info_t sv39 = { +static const virt2phys_info_t sv39 = { .name = "Sv39", .va_bits = 39, .level = 3, @@ -243,7 +243,7 @@ const virt2phys_info_t sv39 = { .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff}, }; -const virt2phys_info_t sv48 = { +static const virt2phys_info_t sv48 = { .name = "Sv48", .va_bits = 48, .level = 4, @@ -256,7 +256,12 @@ const virt2phys_info_t sv48 = { .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff}, }; -void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before) +static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid); +static void riscv_info_init(struct target *target, struct riscv_info *r); +static void riscv_invalidate_register_cache(struct target *target); +static int riscv_step_rtos_hart(struct target *target); + +static void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before) { RISCV_INFO(r); uint32_t now = timeval_ms() & 0xffffffff; @@ -405,13 +410,12 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out) static struct target_type *get_target_type(struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; - - if (!info) { + if (!target->arch_info) { LOG_ERROR("Target has not been initialized"); return NULL; } + RISCV_INFO(info); switch (info->dtm_version) { case 0: return &riscv011_target; @@ -423,10 +427,10 @@ static struct target_type *get_target_type(struct target *target) } } -static int riscv_create_target(struct target *target, Jim_Interp *interp) +static int riscv_create_target(struct target *target) { LOG_DEBUG("riscv_create_target()"); - target->arch_info = calloc(1, sizeof(riscv_info_t)); + target->arch_info = calloc(1, sizeof(struct riscv_info)); if (!target->arch_info) { LOG_ERROR("Failed to allocate RISC-V target structure."); return ERROR_FAIL; @@ -449,10 +453,7 @@ static int riscv_init_target(struct command_context *cmd_ctx, if (bscan_tunnel_ir_width != 0) { assert(target->tap->ir_length >= 6); uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6); - ir_user4[0] = (uint8_t)ir_user4_raw; - ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8); - ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8); - ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8); + h_u32_to_le(ir_user4, ir_user4_raw); select_user4.num_bits = target->tap->ir_length; bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width; if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) @@ -475,7 +476,7 @@ static void riscv_free_registers(struct target *target) if (target->reg_cache->reg_list) { free(target->reg_cache->reg_list[0].arch_info); /* Free the ones we allocated separately. */ - for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++) + for (unsigned int i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++) free(target->reg_cache->reg_list[i].arch_info); for (unsigned int i = 0; i < target->reg_cache->num_regs; i++) free(target->reg_cache->reg_list[i].value); @@ -489,14 +490,17 @@ static void riscv_deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = target->arch_info; + struct riscv_info *info = target->arch_info; struct target_type *tt = get_target_type(target); - if (tt && info->version_specific) + if (tt && info && info->version_specific) tt->deinit_target(target); riscv_free_registers(target); + if (!info) + return; + range_list_t *entry, *tmp; list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) { free(entry->name); @@ -706,7 +710,6 @@ static int add_trigger(struct target *target, struct trigger *trigger) return result; int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target))); - result = ERROR_OK; switch (type) { case 1: result = maybe_add_trigger_t1(target, trigger, tdata1); @@ -859,7 +862,7 @@ int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_ return ERROR_FAIL; } -int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint) +static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address); assert(breakpoint); @@ -939,7 +942,7 @@ static int remove_trigger(struct target *target, struct trigger *trigger) return ERROR_OK; } -int riscv_remove_breakpoint(struct target *target, +static int riscv_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { if (breakpoint->type == BKPT_SOFT) { @@ -1017,7 +1020,7 @@ int riscv_remove_watchpoint(struct target *target, * The GDB server uses this information to tell GDB what data address has * been hit, which enables GDB to print the hit variable along with its old * and new value. */ -int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) +static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) { struct watchpoint *wp = target->watchpoints; @@ -1093,16 +1096,15 @@ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoi return ERROR_FAIL; } - -static int oldriscv_step(struct target *target, int current, uint32_t address, - int handle_breakpoints) +static int oldriscv_step(struct target *target, bool current, uint32_t address, + bool handle_breakpoints) { struct target_type *tt = get_target_type(target); return tt->step(target, current, address, handle_breakpoints); } -static int old_or_new_riscv_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int old_or_new_riscv_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { RISCV_INFO(r); LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints); @@ -1112,7 +1114,6 @@ static int old_or_new_riscv_step(struct target *target, int current, return riscv_openocd_step(target, current, address, handle_breakpoints); } - static int riscv_examine(struct target *target) { LOG_DEBUG("riscv_examine()"); @@ -1160,7 +1161,7 @@ int riscv_select_current_hart(struct target *target) return riscv_set_current_hartid(target, target->coreid); } -int halt_prep(struct target *target) +static int halt_prep(struct target *target) { RISCV_INFO(r); @@ -1180,7 +1181,7 @@ int halt_prep(struct target *target) return ERROR_OK; } -int riscv_halt_go_all_harts(struct target *target) +static int riscv_halt_go_all_harts(struct target *target) { RISCV_INFO(r); @@ -1198,9 +1199,9 @@ int riscv_halt_go_all_harts(struct target *target) return ERROR_OK; } -int halt_go(struct target *target) +static int halt_go(struct target *target) { - riscv_info_t *r = riscv_info(target); + RISCV_INFO(r); int result; if (!r->is_halted) { struct target_type *tt = get_target_type(target); @@ -1242,7 +1243,7 @@ int riscv_halt(struct target *target) foreach_smp_target(tlist, target->smp_targets) { struct target *t = tlist->target; - riscv_info_t *i = riscv_info(t); + struct riscv_info *i = riscv_info(t); if (i->prepped) { if (halt_go(t) != ERROR_OK) result = ERROR_FAIL; @@ -1282,7 +1283,7 @@ static int riscv_deassert_reset(struct target *target) return tt->deassert_reset(target); } -int riscv_resume_prep_all_harts(struct target *target) +static int riscv_resume_prep_all_harts(struct target *target) { RISCV_INFO(r); @@ -1392,8 +1393,8 @@ static int enable_triggers(struct target *target, riscv_reg_t *state) /** * Get everything ready to resume. */ -static int resume_prep(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int resume_prep(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { RISCV_INFO(r); LOG_DEBUG("[%d]", target->coreid); @@ -1431,10 +1432,10 @@ static int resume_prep(struct target *target, int current, * Resume all the harts that have been prepped, as close to instantaneous as * possible. */ -static int resume_go(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int resume_go(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { - riscv_info_t *r = riscv_info(target); + RISCV_INFO(r); int result; if (!r->is_halted) { struct target_type *tt = get_target_type(target); @@ -1460,12 +1461,12 @@ static int resume_finish(struct target *target) * @par single_hart When true, only resume a single hart even if SMP is * configured. This is used to run algorithms on just one hart. */ -int riscv_resume( +static int riscv_resume( struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution, + bool handle_breakpoints, + bool debug_execution, bool single_hart) { LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints); @@ -1483,7 +1484,7 @@ int riscv_resume( foreach_smp_target_direction(resume_order == RO_NORMAL, tlist, target->smp_targets) { struct target *t = tlist->target; - riscv_info_t *i = riscv_info(t); + struct riscv_info *i = riscv_info(t); if (i->prepped) { if (resume_go(t, current, address, handle_breakpoints, debug_execution) != ERROR_OK) @@ -1512,8 +1513,8 @@ int riscv_resume( return result; } -static int riscv_target_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +static int riscv_target_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { return riscv_resume(target, current, address, handle_breakpoints, debug_execution, false); @@ -1580,7 +1581,7 @@ static int riscv_address_translate(struct target *target, if (result != ERROR_OK) return result; - unsigned xlen = riscv_xlen(target); + unsigned int xlen = riscv_xlen(target); mode = get_field(satp_value, RISCV_SATP_MODE(xlen)); switch (mode) { case SATP_MODE_SV32: @@ -1604,6 +1605,7 @@ static int riscv_address_translate(struct target *target, LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name); /* verify bits xlen-1:va_bits-1 are all equal */ + assert(xlen >= info->va_bits); target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1; target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask; if (masked_msbs != 0 && masked_msbs != mask) { @@ -1740,7 +1742,7 @@ static int riscv_write_memory(struct target *target, target_addr_t address, return tt->write_memory(target, address, size, count, buffer); } -const char *riscv_get_gdb_arch(struct target *target) +static const char *riscv_get_gdb_arch(const struct target *target) { switch (riscv_xlen(target)) { case 32: @@ -1826,7 +1828,7 @@ static int riscv_arch_state(struct target *target) static int riscv_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, - target_addr_t exit_point, int timeout_ms, void *arch_info) + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { RISCV_INFO(info); @@ -1836,7 +1838,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, } if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted (run target algo)"); return ERROR_TARGET_NOT_HALTED; } @@ -1900,7 +1902,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, /* Run algorithm */ LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point); - if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK) + if (riscv_resume(target, false, entry_point, false, false, true) != ERROR_OK) return ERROR_FAIL; int64_t start = timeval_ms(); @@ -1923,7 +1925,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, GDB_REGNO_PC, GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE, }; - for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(regnums); i++) { enum gdb_regno regno = regnums[i]; riscv_reg_t reg_value; if (riscv_get_register(target, ®_value, regno) != ERROR_OK) @@ -2003,8 +2005,8 @@ static int riscv_checksum_memory(struct target *target, static const uint8_t *crc_code; - unsigned xlen = riscv_xlen(target); - unsigned crc_code_size; + unsigned int xlen = riscv_xlen(target); + unsigned int crc_code_size; if (xlen == 32) { crc_code = riscv32_crc_code; crc_code_size = sizeof(riscv32_crc_code); @@ -2048,7 +2050,7 @@ static int riscv_checksum_memory(struct target *target, buf_set_u64(reg_params[1].value, 0, xlen, count); /* 20 second timeout/megabyte */ - int timeout = 20000 * (1 + (count / (1024 * 1024))); + unsigned int timeout = 20000 * (1 + (count / (1024 * 1024))); retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, @@ -2103,7 +2105,7 @@ static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid) return RPH_NO_CHANGE; } -int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) +static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) { switch (halt_reason) { case RISCV_HALT_BREAKPOINT: @@ -2129,7 +2131,7 @@ int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) return ERROR_OK; } -int sample_memory(struct target *target) +static int sample_memory(struct target *target) { RISCV_INFO(r); @@ -2183,13 +2185,12 @@ int riscv_openocd_poll(struct target *target) int halted_hart = -1; if (target->smp) { - unsigned halts_discovered = 0; - unsigned should_remain_halted = 0; - unsigned should_resume = 0; + unsigned int should_remain_halted = 0; + unsigned int should_resume = 0; struct target_list *list; foreach_smp_target(list, target->smp_targets) { struct target *t = list->target; - riscv_info_t *r = riscv_info(t); + struct riscv_info *r = riscv_info(t); enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid); switch (out) { case RPH_NO_CHANGE: @@ -2199,7 +2200,6 @@ int riscv_openocd_poll(struct target *target) t->debug_reason = DBG_REASON_NOTHALTED; break; case RPH_DISCOVERED_HALTED: - halts_discovered++; t->state = TARGET_HALTED; enum riscv_halt_reason halt_reason = riscv_halt_reason(t, r->current_hartid); @@ -2243,7 +2243,7 @@ int riscv_openocd_poll(struct target *target) riscv_halt(target); } else if (should_resume) { LOG_DEBUG("resume all"); - riscv_resume(target, true, 0, 0, 0, false); + riscv_resume(target, true, 0, false, false, false); } /* Sample memory if any target is running. */ @@ -2285,7 +2285,7 @@ int riscv_openocd_poll(struct target *target) target_call_event_callbacks(target, TARGET_EVENT_HALTED); break; case SEMIHOSTING_HANDLED: - if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK) + if (riscv_resume(target, true, 0, false, false, false) != ERROR_OK) return ERROR_FAIL; break; case SEMIHOSTING_ERROR: @@ -2298,8 +2298,8 @@ int riscv_openocd_poll(struct target *target) return ERROR_OK; } -int riscv_openocd_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +int riscv_openocd_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { LOG_DEBUG("stepping rtos hart"); @@ -2363,37 +2363,6 @@ COMMAND_HANDLER(riscv_set_reset_timeout_sec) return ERROR_OK; } -COMMAND_HANDLER(riscv_set_prefer_sba) -{ - struct target *target = get_current_target(CMD_CTX); - RISCV_INFO(r); - bool prefer_sba; - LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead."); - if (CMD_ARGC != 1) { - LOG_ERROR("Command takes exactly 1 parameter"); - return ERROR_COMMAND_SYNTAX_ERROR; - } - COMMAND_PARSE_ON_OFF(CMD_ARGV[0], prefer_sba); - if (prefer_sba) { - /* Use system bus with highest priority */ - r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS; - r->mem_access_methods[1] = RISCV_MEM_ACCESS_PROGBUF; - r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT; - } else { - /* Use progbuf with highest priority */ - r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF; - r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS; - r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT; - } - - /* Reset warning flags */ - r->mem_access_progbuf_warn = true; - r->mem_access_sysbus_warn = true; - r->mem_access_abstract_warn = true; - - return ERROR_OK; -} - COMMAND_HANDLER(riscv_set_mem_access) { struct target *target = get_current_target(CMD_CTX); @@ -2456,7 +2425,7 @@ COMMAND_HANDLER(riscv_set_enable_virtual) return ERROR_OK; } -int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val) +static int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val) { char *args = strdup(tcl_arg); if (!args) @@ -2465,8 +2434,8 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_ /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */ char *arg = strtok(args, ","); while (arg) { - unsigned low = 0; - unsigned high = 0; + unsigned int low = 0; + unsigned int high = 0; char *name = NULL; char *dash = strchr(arg, '-'); @@ -2662,27 +2631,25 @@ COMMAND_HANDLER(riscv_authdata_write) uint32_t value; unsigned int index = 0; - if (CMD_ARGC == 0) { - /* nop */ - } else if (CMD_ARGC == 1) { + if (CMD_ARGC == 0 || CMD_ARGC > 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 1) { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value); - } else if (CMD_ARGC == 2) { + } else { COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); - } else { - LOG_ERROR("Command takes at most 2 arguments"); - return ERROR_COMMAND_SYNTAX_ERROR; } struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); - if (r->authdata_write) { - return r->authdata_write(target, value, index); - } else { + if (!r->authdata_write) { LOG_ERROR("authdata_write is not implemented for this target."); return ERROR_FAIL; } + + return r->authdata_write(target, value, index); } COMMAND_HANDLER(riscv_dmi_read) @@ -2740,35 +2707,6 @@ COMMAND_HANDLER(riscv_dmi_write) } } -COMMAND_HANDLER(riscv_test_sba_config_reg) -{ - if (CMD_ARGC != 4) { - LOG_ERROR("Command takes exactly 4 arguments"); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - struct target *target = get_current_target(CMD_CTX); - RISCV_INFO(r); - - target_addr_t legal_address; - uint32_t num_words; - target_addr_t illegal_address; - bool run_sbbusyerror_test; - - COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words); - COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address); - COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test); - - if (r->test_sba_config_reg) { - return r->test_sba_config_reg(target, legal_address, num_words, - illegal_address, run_sbbusyerror_test); - } else { - LOG_ERROR("test_sba_config_reg is not implemented for this target."); - return ERROR_FAIL; - } -} - COMMAND_HANDLER(riscv_reset_delays) { int wait = 0; @@ -2943,14 +2881,6 @@ static const struct command_registration riscv_exec_command_handlers[] = { .usage = "[sec]", .help = "Set the wall-clock timeout (in seconds) after reset is deasserted" }, - { - .name = "set_prefer_sba", - .handler = riscv_set_prefer_sba, - .mode = COMMAND_ANY, - .usage = "on|off", - .help = "When on, prefer to use System Bus Access to access memory. " - "When off (default), prefer to use the Program Buffer to access memory." - }, { .name = "set_mem_access", .handler = riscv_set_mem_access, @@ -3016,19 +2946,6 @@ static const struct command_registration riscv_exec_command_handlers[] = { .usage = "address value", .help = "Perform a 32-bit DMI write of value at address." }, - { - .name = "test_sba_config_reg", - .handler = riscv_test_sba_config_reg, - .mode = COMMAND_ANY, - .usage = "legal_address num_words " - "illegal_address run_sbbusyerror_test[on/off]", - .help = "Perform a series of tests on the SBCS register. " - "Inputs are a legal, 128-byte aligned address and a number of words to " - "read/write starting at that address (i.e., address range [legal address, " - "legal_address+word_size*num_words) must be legally readable/writable), " - "an illegal, 128-byte aligned address for error flag/handling cases, " - "and whether sbbusyerror test should be run." - }, { .name = "reset_delays", .handler = riscv_reset_delays, @@ -3115,7 +3032,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { * sense, but for now all semihosting commands are prefixed with `arm`. */ -const struct command_registration riscv_command_handlers[] = { +static const struct command_registration riscv_command_handlers[] = { { .name = "riscv", .mode = COMMAND_ANY, @@ -3130,10 +3047,13 @@ const struct command_registration riscv_command_handlers[] = { .usage = "", .chain = semihosting_common_handlers }, + { + .chain = smp_command_handlers + }, COMMAND_REGISTRATION_DONE }; -static unsigned riscv_xlen_nonconst(struct target *target) +static unsigned int riscv_xlen_nonconst(struct target *target) { return riscv_xlen(target); } @@ -3197,9 +3117,13 @@ struct target_type riscv_target = { /*** RISC-V Interface ***/ -void riscv_info_init(struct target *target, riscv_info_t *r) +/* Initializes the shared RISC-V structure. */ +static void riscv_info_init(struct target *target, struct riscv_info *r) { memset(r, 0, sizeof(*r)); + + r->common_magic = RISCV_COMMON_MAGIC; + r->dtm_version = 1; r->current_hartid = target->coreid; r->version_specific = NULL; @@ -3239,7 +3163,9 @@ static int riscv_resume_go_all_harts(struct target *target) return ERROR_OK; } -int riscv_step_rtos_hart(struct target *target) +/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS + * then the only hart. */ +static int riscv_step_rtos_hart(struct target *target) { RISCV_INFO(r); if (riscv_select_current_hart(target) != ERROR_OK) @@ -3266,7 +3192,7 @@ int riscv_step_rtos_hart(struct target *target) bool riscv_supports_extension(struct target *target, char letter) { RISCV_INFO(r); - unsigned num; + unsigned int num; if (letter >= 'a' && letter <= 'z') num = letter - 'a'; else if (letter >= 'A' && letter <= 'Z') @@ -3276,7 +3202,7 @@ bool riscv_supports_extension(struct target *target, char letter) return r->misa & BIT(num); } -unsigned riscv_xlen(const struct target *target) +unsigned int riscv_xlen(const struct target *target) { RISCV_INFO(r); return r->xlen; @@ -3297,7 +3223,8 @@ int riscv_set_current_hartid(struct target *target, int hartid) return ERROR_OK; } -void riscv_invalidate_register_cache(struct target *target) +/* Invalidates the register cache. */ +static void riscv_invalidate_register_cache(struct target *target) { LOG_DEBUG("[%d]", target->coreid); register_cache_invalidate(target->reg_cache); @@ -3447,7 +3374,7 @@ bool riscv_is_halted(struct target *target) return r->is_halted(target); } -enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid) +static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid) { RISCV_INFO(r); if (riscv_set_current_hartid(target, hartid) != ERROR_OK) @@ -3849,7 +3776,7 @@ static struct reg_arch_type riscv_reg_arch_type = { }; struct csr_info { - unsigned number; + unsigned int number; const char *name; }; @@ -3925,7 +3852,7 @@ int riscv_init_registers(struct target *target) .type = REG_TYPE_ARCH_DEFINED, .id = "FPU_FD", .type_class = REG_TYPE_CLASS_UNION, - .reg_type_union = &single_double_union + { .reg_type_union = &single_double_union } }; static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" }; static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" }; @@ -4029,7 +3956,7 @@ int riscv_init_registers(struct target *target) }; /* encoding.h does not contain the registers in sorted order. */ qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info); - unsigned csr_info_index = 0; + unsigned int csr_info_index = 0; int custom_within_range = 0; @@ -4284,7 +4211,7 @@ int riscv_init_registers(struct target *target) } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { r->group = "csr"; r->feature = &feature_csr; - unsigned csr_number = number - GDB_REGNO_CSR0; + unsigned int csr_number = number - GDB_REGNO_CSR0; while (csr_info[csr_info_index].number < csr_number && csr_info_index < ARRAY_SIZE(csr_info) - 1) { @@ -4447,7 +4374,7 @@ int riscv_init_registers(struct target *target) range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list); - unsigned custom_number = range->low + custom_within_range; + unsigned int custom_number = range->low + custom_within_range; r->group = "custom"; r->feature = &feature_custom; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index a6d27f79b9..f06b5f516d 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -13,6 +13,8 @@ struct riscv_program; #include "target/semihosting_common.h" #include <helper/command.h> +#define RISCV_COMMON_MAGIC 0x52495356U + /* The register cache is statically allocated. */ #define RISCV_MAX_HARTS 1024 #define RISCV_MAX_REGISTERS 5000 @@ -59,7 +61,7 @@ enum riscv_halt_reason { typedef struct { struct target *target; - unsigned custom_number; + unsigned int custom_number; } riscv_reg_info_t; #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80 @@ -85,8 +87,10 @@ typedef struct { char *name; } range_list_t; -typedef struct { - unsigned dtm_version; +struct riscv_info { + unsigned int common_magic; + + unsigned int dtm_version; struct command_context *cmd_ctx; void *version_specific; @@ -155,9 +159,9 @@ typedef struct { int (*halt_go)(struct target *target); int (*on_step)(struct target *target); enum riscv_halt_reason (*halt_reason)(struct target *target); - int (*write_debug_buffer)(struct target *target, unsigned index, + int (*write_debug_buffer)(struct target *target, unsigned int index, riscv_insn_t d); - riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index); + riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned int index); int (*execute_debug_buffer)(struct target *target); int (*dmi_write_u64_bits)(struct target *target); void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d); @@ -170,9 +174,6 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); - int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, - uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); - int (*sample_memory)(struct target *target, struct riscv_sample_buf *buf, riscv_sample_config_t *config, @@ -183,7 +184,7 @@ typedef struct { /* How many harts are attached to the DM that this target is attached to? */ int (*hart_count)(struct target *target); - unsigned (*data_bits)(struct target *target); + unsigned int (*data_bits)(struct target *target); COMMAND_HELPER((*print_info), struct target *target); @@ -225,7 +226,7 @@ typedef struct { riscv_sample_config_t sample_config; struct riscv_sample_buf sample_buf; -} riscv_info_t; +}; COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key, unsigned int value); @@ -238,14 +239,14 @@ typedef struct { typedef struct { const char *name; int level; - unsigned va_bits; - unsigned pte_shift; - unsigned vpn_shift[PG_MAX_LEVEL]; - unsigned vpn_mask[PG_MAX_LEVEL]; - unsigned pte_ppn_shift[PG_MAX_LEVEL]; - unsigned pte_ppn_mask[PG_MAX_LEVEL]; - unsigned pa_ppn_shift[PG_MAX_LEVEL]; - unsigned pa_ppn_mask[PG_MAX_LEVEL]; + unsigned int va_bits; + unsigned int pte_shift; + unsigned int vpn_shift[PG_MAX_LEVEL]; + unsigned int vpn_mask[PG_MAX_LEVEL]; + unsigned int pte_ppn_shift[PG_MAX_LEVEL]; + unsigned int pte_ppn_mask[PG_MAX_LEVEL]; + unsigned int pa_ppn_shift[PG_MAX_LEVEL]; + unsigned int pa_ppn_mask[PG_MAX_LEVEL]; } virt2phys_info_t; /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/ @@ -261,27 +262,27 @@ extern bool riscv_ebreaku; /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ -static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused)); -static inline riscv_info_t *riscv_info(const struct target *target) +static inline struct riscv_info *riscv_info(const struct target *target) __attribute__((unused)); +static inline struct riscv_info *riscv_info(const struct target *target) { assert(target->arch_info); return target->arch_info; } -#define RISCV_INFO(R) riscv_info_t *R = riscv_info(target); +#define RISCV_INFO(R) struct riscv_info *R = riscv_info(target); + +static inline bool is_riscv(const struct riscv_info *riscv_info) +{ + return riscv_info->common_magic == RISCV_COMMON_MAGIC; +} -extern uint8_t ir_dtmcontrol[4]; extern struct scan_field select_dtmcontrol; -extern uint8_t ir_dbus[4]; extern struct scan_field select_dbus; -extern uint8_t ir_idcode[4]; extern struct scan_field select_idcode; -extern struct scan_field select_user4; extern struct scan_field *bscan_tunneled_select_dmi; extern uint32_t bscan_tunneled_select_dmi_num_fields; typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t; extern int bscan_tunnel_ir_width; -extern bscan_tunnel_type_t bscan_tunnel_type; uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out); void select_dmi_via_bscan(struct target *target); @@ -291,20 +292,11 @@ int riscv_openocd_poll(struct target *target); int riscv_halt(struct target *target); -int riscv_resume( - struct target *target, - int current, - target_addr_t address, - int handle_breakpoints, - int debug_execution, - bool single_hart -); - int riscv_openocd_step( struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints + bool handle_breakpoints ); int riscv_openocd_assert_reset(struct target *target); @@ -312,17 +304,10 @@ int riscv_openocd_deassert_reset(struct target *target); /*** RISC-V Interface ***/ -/* Initializes the shared RISC-V structure. */ -void riscv_info_init(struct target *target, riscv_info_t *r); - -/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS - * then the only hart. */ -int riscv_step_rtos_hart(struct target *target); - bool riscv_supports_extension(struct target *target, char letter); /* Returns XLEN for the given (or current) hart. */ -unsigned riscv_xlen(const struct target *target); +unsigned int riscv_xlen(const struct target *target); int riscv_xlen_of_hart(const struct target *target); /* Sets the current hart, which is the hart that will actually be used when @@ -347,7 +332,6 @@ int riscv_get_register(struct target *target, riscv_reg_t *value, /* Checks the state of the current hart -- "is_halted" checks the actual * on-device register. */ bool riscv_is_halted(struct target *target); -enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid); /* These helper functions let the generic program interface get target-specific * information. */ @@ -362,18 +346,11 @@ void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a); int riscv_dmi_write_u64_bits(struct target *target); -/* Invalidates the register cache. */ -void riscv_invalidate_register_cache(struct target *target); - int riscv_enumerate_triggers(struct target *target); -int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint); -int riscv_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint); int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint); int riscv_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); -int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address); int riscv_init_registers(struct target *target); diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c index 03de97c457..da237ef337 100644 --- a/src/target/riscv/riscv_semihosting.c +++ b/src/target/riscv/riscv_semihosting.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Liviu Ionescu * @@ -141,16 +141,16 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval) } } + /* Resume right after the EBREAK 4 bytes instruction. */ + *retval = riscv_set_register(target, GDB_REGNO_PC, pc + 4); + if (*retval != ERROR_OK) + return SEMIHOSTING_ERROR; + /* * Resume target if we are not waiting on a fileio * operation to complete. */ if (semihosting->is_resumable && !semihosting->hit_fileio) { - /* Resume right after the EBREAK 4 bytes instruction. */ - *retval = riscv_set_register(target, GDB_REGNO_PC, pc + 4); - if (*retval != ERROR_OK) - return SEMIHOSTING_ERROR; - LOG_DEBUG(" -> HANDLED"); return SEMIHOSTING_HANDLED; } diff --git a/src/target/rtt.c b/src/target/rtt.c index 671650cf86..5ce049ae18 100644 --- a/src/target/rtt.c +++ b/src/target/rtt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016-2020 by Marc Schink <dev@zapb.de> @@ -14,6 +14,7 @@ #include <helper/binarybuffer.h> #include <helper/command.h> #include <rtt/rtt.h> +#include <target/rtt.h> #include "target.h" @@ -241,43 +242,37 @@ int target_rtt_find_control_block(struct target *target, target_addr_t *address, size_t size, const char *id, bool *found, void *user_data) { + target_addr_t address_end = *address + size; uint8_t buf[1024]; *found = false; - size_t j = 0; - size_t cb_offset = 0; + size_t id_matched_length = 0; const size_t id_length = strlen(id); LOG_INFO("rtt: Searching for control block '%s'", id); - for (target_addr_t addr = 0; addr < size; addr = addr + sizeof(buf)) { + for (target_addr_t addr = *address; addr < address_end; addr += sizeof(buf)) { int ret; - const size_t buf_size = MIN(sizeof(buf), size - addr); - ret = target_read_buffer(target, *address + addr, buf_size, buf); + const size_t buf_size = MIN(sizeof(buf), address_end - addr); + ret = target_read_buffer(target, addr, buf_size, buf); if (ret != ERROR_OK) return ret; - size_t start = 0; - size_t i = 0; - - while (i < buf_size) { - if (buf[i] != id[j]) { - start++; - cb_offset++; - i = start; - j = 0; - - continue; + for (size_t buf_off = 0; buf_off < buf_size; buf_off++) { + if (id_matched_length > 0 && + buf[buf_off] != id[id_matched_length]) { + /* Start from beginning */ + id_matched_length = 0; } - i++; - j++; + if (buf[buf_off] == id[id_matched_length]) + id_matched_length++; - if (j == id_length) { - *address = *address + cb_offset; + if (id_matched_length == id_length) { + *address = addr + buf_off + 1 - id_length; *found = true; return ERROR_OK; } diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c index e31ff6fd4a..ffcd3aafde 100644 --- a/src/target/semihosting_common.c +++ b/src/target/semihosting_common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2018 by Liviu Ionescu * @@ -39,6 +39,7 @@ #include <helper/binarybuffer.h> #include <helper/log.h> +#include <server/gdb_server.h> #include <sys/stat.h> /** @@ -91,9 +92,8 @@ static int semihosting_common_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info); static int semihosting_common_fileio_end(struct target *target, int result, int fileio_errno, bool ctrl_c); - -/* Attempts to include gdb_server.h failed. */ -extern int gdb_actual_connections; +static void semihosting_set_field(struct target *target, uint64_t value, size_t index, uint8_t *fields); +static int semihosting_write_fields(struct target *target, size_t number, uint8_t *fields); /** * Initialize common semihosting support. @@ -225,7 +225,10 @@ static ssize_t semihosting_write(struct semihosting *semihosting, int fd, void * return semihosting_redirect_write(semihosting, buf, size); /* default write */ - return write(fd, buf, size); + int result = write(fd, buf, size); + if (result == -1) + semihosting->sys_errno = errno; + return result; } static ssize_t semihosting_redirect_read(struct semihosting *semihosting, void *buf, int size) @@ -270,7 +273,8 @@ static inline ssize_t semihosting_read(struct semihosting *semihosting, int fd, /* default read */ ssize_t result = read(fd, buf, size); - semihosting->sys_errno = errno; + if (result == -1) + semihosting->sys_errno = errno; return result; } @@ -296,6 +300,71 @@ static inline int semihosting_getchar(struct semihosting *semihosting, int fd) */ static char *semihosting_user_op_params; +/** + * @brief Convert the syscall opcode to a human-readable string + * @param[in] opcode Syscall opcode + * @return String representation of syscall opcode + */ +static const char *semihosting_opcode_to_str(const uint64_t opcode) +{ + switch (opcode) { + case SEMIHOSTING_SYS_CLOSE: + return "CLOSE"; + case SEMIHOSTING_SYS_CLOCK: + return "CLOCK"; + case SEMIHOSTING_SYS_ELAPSED: + return "ELAPSED"; + case SEMIHOSTING_SYS_ERRNO: + return "ERRNO"; + case SEMIHOSTING_SYS_EXIT: + return "EXIT"; + case SEMIHOSTING_SYS_EXIT_EXTENDED: + return "EXIT_EXTENDED"; + case SEMIHOSTING_SYS_FLEN: + return "FLEN"; + case SEMIHOSTING_SYS_GET_CMDLINE: + return "GET_CMDLINE"; + case SEMIHOSTING_SYS_HEAPINFO: + return "HEAPINFO"; + case SEMIHOSTING_SYS_ISERROR: + return "ISERROR"; + case SEMIHOSTING_SYS_ISTTY: + return "ISTTY"; + case SEMIHOSTING_SYS_OPEN: + return "OPEN"; + case SEMIHOSTING_SYS_READ: + return "READ"; + case SEMIHOSTING_SYS_READC: + return "READC"; + case SEMIHOSTING_SYS_REMOVE: + return "REMOVE"; + case SEMIHOSTING_SYS_RENAME: + return "RENAME"; + case SEMIHOSTING_SYS_SEEK: + return "SEEK"; + case SEMIHOSTING_SYS_SYSTEM: + return "SYSTEM"; + case SEMIHOSTING_SYS_TICKFREQ: + return "TICKFREQ"; + case SEMIHOSTING_SYS_TIME: + return "TIME"; + case SEMIHOSTING_SYS_TMPNAM: + return "TMPNAM"; + case SEMIHOSTING_SYS_WRITE: + return "WRITE"; + case SEMIHOSTING_SYS_WRITEC: + return "WRITEC"; + case SEMIHOSTING_SYS_WRITE0: + return "WRITE0"; + case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X1FF: + return "USER_CMD"; + case SEMIHOSTING_ARM_RESERVED_START ... SEMIHOSTING_ARM_RESERVED_END: + return "ARM_RESERVED_CMD"; + default: + return "<unknown>"; + } +} + /** * Portable implementation of ARM semihosting calls. * Performs the currently pending semihosting operation @@ -325,8 +394,9 @@ int semihosting_common(struct target *target) /* Enough space to hold 4 long words. */ uint8_t fields[4*8]; - LOG_DEBUG("op=0x%x, param=0x%" PRIx64, semihosting->op, - semihosting->param); + LOG_DEBUG("op=0x%x (%s), param=0x%" PRIx64, semihosting->op, + semihosting_opcode_to_str(semihosting->op), + semihosting->param); switch (semihosting->op) { @@ -390,12 +460,7 @@ int semihosting_common(struct target *target) (fd == 0) ? "stdin" : (fd == 1) ? "stdout" : "stderr"); /* Just pretend success */ - if (semihosting->is_fileio) { - semihosting->result = 0; - } else { - semihosting->result = 0; - semihosting->sys_errno = 0; - } + semihosting->result = 0; break; } /* Close the descriptor */ @@ -405,8 +470,9 @@ int semihosting_common(struct target *target) fileio_info->param_1 = fd; } else { semihosting->result = close(fd); - semihosting->sys_errno = errno; - LOG_DEBUG("close(%d)=%d", fd, (int)semihosting->result); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result); } } break; @@ -493,7 +559,7 @@ int semihosting_common(struct target *target) int code = semihosting_get_field(target, 1, fields); if (type == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_actual_connections) + if (!gdb_get_actual_connections()) exit(code); else { fprintf(stderr, @@ -508,7 +574,7 @@ int semihosting_common(struct target *target) } } else { if (semihosting->param == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_actual_connections) + if (!gdb_get_actual_connections()) exit(0); else { fprintf(stderr, @@ -517,14 +583,14 @@ int semihosting_common(struct target *target) } else if (semihosting->param == ADP_STOPPED_RUN_TIME_ERROR) { /* Chosen more or less arbitrarily to have a nicer message, * otherwise all other return the same exit code 1. */ - if (!gdb_actual_connections) + if (!gdb_get_actual_connections()) exit(1); else { fprintf(stderr, "semihosting: *** application exited with error ***\n"); } } else { - if (!gdb_actual_connections) + if (!gdb_get_actual_connections()) exit(1); else { fprintf(stderr, @@ -584,7 +650,7 @@ int semihosting_common(struct target *target) int code = semihosting_get_field(target, 1, fields); if (type == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_actual_connections) + if (!gdb_get_actual_connections()) exit(code); else { fprintf(stderr, @@ -631,10 +697,10 @@ int semihosting_common(struct target *target) semihosting->result = fstat(fd, &buf); if (semihosting->result == -1) { semihosting->sys_errno = errno; - LOG_DEBUG("fstat(%d)=%d", fd, (int)semihosting->result); + LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result); break; } - LOG_DEBUG("fstat(%d)=%d", fd, (int)semihosting->result); + LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result); semihosting->result = buf.st_size; } break; @@ -691,8 +757,7 @@ int semihosting_common(struct target *target) if (retval != ERROR_OK) return retval; } - LOG_DEBUG("SYS_GET_CMDLINE=[%s],%d", arg, - (int)semihosting->result); + LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result); } break; @@ -782,9 +847,11 @@ int semihosting_common(struct target *target) if (retval != ERROR_OK) return retval; int fd = semihosting_get_field(target, 0, fields); - semihosting->result = isatty(fd); - semihosting->sys_errno = errno; - LOG_DEBUG("isatty(%d)=%d", fd, (int)semihosting->result); + // isatty() on Windows may return any non-zero value if fd is a terminal + semihosting->result = isatty(fd) ? 1 : 0; + if (semihosting->result == 0) + semihosting->sys_errno = errno; + LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result); } break; @@ -875,14 +942,16 @@ int semihosting_common(struct target *target) semihosting->result = -1; semihosting->sys_errno = EINVAL; } else if (strcmp((char *)fn, ":tt") == 0) { - if (mode == 0) + if (mode == 0) { semihosting->result = 0; - else if (mode == 4) + } else if (mode == 4) { semihosting->result = 1; - else if (mode == 8) + } else if (mode == 8) { semihosting->result = 2; - else + } else { semihosting->result = -1; + semihosting->sys_errno = EINVAL; + } } else { semihosting->hit_fileio = true; fileio_info->identifier = "open"; @@ -897,28 +966,23 @@ int semihosting_common(struct target *target) * - 0-3 ("r") for stdin, * - 4-7 ("w") for stdout, * - 8-11 ("a") for stderr */ + int fd; if (mode < 4) { - int fd = dup(STDIN_FILENO); - semihosting->result = fd; + fd = dup(STDIN_FILENO); semihosting->stdin_fd = fd; - semihosting->sys_errno = errno; - LOG_DEBUG("dup(STDIN)=%d", - (int)semihosting->result); + LOG_DEBUG("dup(STDIN)=%d", fd); } else if (mode < 8) { - int fd = dup(STDOUT_FILENO); - semihosting->result = fd; + fd = dup(STDOUT_FILENO); semihosting->stdout_fd = fd; - semihosting->sys_errno = errno; - LOG_DEBUG("dup(STDOUT)=%d", - (int)semihosting->result); + LOG_DEBUG("dup(STDOUT)=%d", fd); } else { - int fd = dup(STDERR_FILENO); - semihosting->result = fd; + fd = dup(STDERR_FILENO); semihosting->stderr_fd = fd; - semihosting->sys_errno = errno; - LOG_DEBUG("dup(STDERR)=%d", - (int)semihosting->result); + LOG_DEBUG("dup(STDERR)=%d", fd); } + semihosting->result = fd; + if (fd == -1) + semihosting->sys_errno = errno; } else { /* cygwin requires the permission setting * otherwise it will fail to reopen a previously @@ -926,9 +990,9 @@ int semihosting_common(struct target *target) semihosting->result = open((char *)fn, open_host_modeflags[mode], 0644); - semihosting->sys_errno = errno; - LOG_DEBUG("open('%s')=%d", fn, - (int)semihosting->result); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result); } } free(fn); @@ -991,11 +1055,11 @@ int semihosting_common(struct target *target) semihosting->sys_errno = ENOMEM; } else { semihosting->result = semihosting_read(semihosting, fd, buf, len); - LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%d", + LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64, fd, addr, len, - (int)semihosting->result); + semihosting->result); if (semihosting->result >= 0) { retval = target_write_buffer(target, addr, semihosting->result, @@ -1031,7 +1095,7 @@ int semihosting_common(struct target *target) return ERROR_FAIL; } semihosting->result = semihosting_getchar(semihosting, semihosting->stdin_fd); - LOG_DEBUG("getchar()=%d", (int)semihosting->result); + LOG_DEBUG("getchar()=%" PRId64, semihosting->result); break; case SEMIHOSTING_SYS_REMOVE: /* 0x0E */ @@ -1076,9 +1140,9 @@ int semihosting_common(struct target *target) } fn[len] = 0; semihosting->result = remove((char *)fn); - semihosting->sys_errno = errno; - LOG_DEBUG("remove('%s')=%d", fn, - (int)semihosting->result); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result); free(fn); } @@ -1146,10 +1210,10 @@ int semihosting_common(struct target *target) fn2[len2] = 0; semihosting->result = rename((char *)fn1, (char *)fn2); - semihosting->sys_errno = errno; - LOG_DEBUG("rename('%s', '%s')=%d", fn1, fn2, - (int)semihosting->result); - + // rename() on Windows returns nonzero on error + if (semihosting->result != 0) + semihosting->sys_errno = errno; + LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno); free(fn1); free(fn2); } @@ -1193,9 +1257,9 @@ int semihosting_common(struct target *target) fileio_info->param_3 = SEEK_SET; } else { semihosting->result = lseek(fd, pos, SEEK_SET); - semihosting->sys_errno = errno; - LOG_DEBUG("lseek(%d, %d)=%d", fd, (int)pos, - (int)semihosting->result); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result); if (semihosting->result == pos) semihosting->result = 0; } @@ -1254,9 +1318,7 @@ int semihosting_common(struct target *target) cmd[len] = 0; semihosting->result = system( (const char *)cmd); - LOG_DEBUG("system('%s')=%d", - cmd, - (int)semihosting->result); + LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result); } free(cmd); @@ -1334,12 +1396,11 @@ int semihosting_common(struct target *target) return retval; } semihosting->result = semihosting_write(semihosting, fd, buf, len); - semihosting->sys_errno = errno; - LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%d", + LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64, fd, addr, len, - (int)semihosting->result); + semihosting->result); if (semihosting->result >= 0) { /* The number of bytes that are NOT written. * */ @@ -1428,7 +1489,7 @@ int semihosting_common(struct target *target) } break; - case SEMIHOSTING_USER_CMD_0x100 ... SEMIHOSTING_USER_CMD_0x107: + case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X107: /** * This is a user defined operation (while user cmds 0x100-0x1ff * are possible, only 0x100-0x107 are currently implemented). @@ -1482,8 +1543,9 @@ int semihosting_common(struct target *target) retval = target_read_buffer(target, addr, len, (uint8_t *)(semihosting_user_op_params)); if (retval != ERROR_OK) { - LOG_ERROR("Failed to read from target, semihosting op=0x%x", - semihosting->op); + LOG_ERROR("Failed to read from target, semihosting op=0x%x (%s)", + semihosting->op, + semihosting_opcode_to_str(semihosting->op)); free(semihosting_user_op_params); semihosting_user_op_params = NULL; return retval; @@ -1621,7 +1683,6 @@ static int semihosting_common_fileio_end(struct target *target, int result, semihosting->hit_fileio = false; semihosting->result = result; - semihosting->sys_errno = fileio_errno; /* * Some fileio results do not match up with what the semihosting @@ -1643,6 +1704,17 @@ static int semihosting_common_fileio_end(struct target *target, int result, break; } + bool fileio_failed = false; + if (semihosting->op == SEMIHOSTING_SYS_ISTTY) + fileio_failed = (semihosting->result == 0); + else if (semihosting->op == SEMIHOSTING_SYS_RENAME) + fileio_failed = (semihosting->result != 0); + else + fileio_failed = (semihosting->result == -1); + + if (fileio_failed) + semihosting->sys_errno = fileio_errno; + return semihosting->post_result(target); } @@ -1664,8 +1736,7 @@ int semihosting_read_fields(struct target *target, size_t number, /** * Write all fields of a command from buffer to target. */ -int semihosting_write_fields(struct target *target, size_t number, - uint8_t *fields) +static int semihosting_write_fields(struct target *target, size_t number, uint8_t *fields) { struct semihosting *semihosting = target->semihosting; /* Use 4-byte multiples to trigger fast memory access. */ @@ -1689,9 +1760,7 @@ uint64_t semihosting_get_field(struct target *target, size_t index, /** * Store a field in the buffer, considering register size and endianness. */ -void semihosting_set_field(struct target *target, uint64_t value, - size_t index, - uint8_t *fields) +static void semihosting_set_field(struct target *target, uint64_t value, size_t index, uint8_t *fields) { struct semihosting *semihosting = target->semihosting; if (semihosting->word_size_bytes == 8) @@ -1737,10 +1806,8 @@ static int semihosting_service_input_handler(struct connection *connection) static int semihosting_service_connection_closed_handler(struct connection *connection) { struct semihosting_tcp_service *service = connection->service->priv; - if (service) { + if (service) free(service->name); - free(service); - } return ERROR_OK; } diff --git a/src/target/semihosting_common.h b/src/target/semihosting_common.h index 8ecf2e5263..1821ca4e2e 100644 --- a/src/target/semihosting_common.h +++ b/src/target/semihosting_common.h @@ -65,9 +65,11 @@ enum semihosting_operation_numbers { SEMIHOSTING_SYS_WRITE = 0x05, SEMIHOSTING_SYS_WRITEC = 0x03, SEMIHOSTING_SYS_WRITE0 = 0x04, - SEMIHOSTING_USER_CMD_0x100 = 0x100, /* First user cmd op code */ - SEMIHOSTING_USER_CMD_0x107 = 0x107, /* Last supported user cmd op code */ - SEMIHOSTING_USER_CMD_0x1FF = 0x1FF, /* Last user cmd op code */ + SEMIHOSTING_ARM_RESERVED_START = 0x32, + SEMIHOSTING_ARM_RESERVED_END = 0xFF, + SEMIHOSTING_USER_CMD_0X100 = 0x100, /* First user cmd op code */ + SEMIHOSTING_USER_CMD_0X107 = 0x107, /* Last supported user cmd op code */ + SEMIHOSTING_USER_CMD_0X1FF = 0x1FF, /* Last user cmd op code */ }; /** Maximum allowed Tcl command segment length in bytes*/ @@ -193,13 +195,8 @@ int semihosting_common(struct target *target); /* utility functions which may also be used by semihosting extensions (custom vendor-defined syscalls) */ int semihosting_read_fields(struct target *target, size_t number, uint8_t *fields); -int semihosting_write_fields(struct target *target, size_t number, - uint8_t *fields); uint64_t semihosting_get_field(struct target *target, size_t index, uint8_t *fields); -void semihosting_set_field(struct target *target, uint64_t value, - size_t index, - uint8_t *fields); extern const struct command_registration semihosting_common_handlers[]; diff --git a/src/target/smp.c b/src/target/smp.c index b28d546be7..41ca880d43 100644 --- a/src/target/smp.c +++ b/src/target/smp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * * @@ -119,7 +119,7 @@ COMMAND_HANDLER(default_handle_smp_command) head->target->smp = 0; /* fixes the target display to the debugger */ - if (!list_empty(target->smp_targets)) + if (!list_empty(target->smp_targets) && target->gdb_service) target->gdb_service->target = target; return ERROR_OK; @@ -132,6 +132,9 @@ COMMAND_HANDLER(handle_smp_gdb_command) { struct target *target = get_current_target(CMD_CTX); int retval = ERROR_OK; + + LOG_WARNING(DEPRECATED_MSG); + if (!list_empty(target->smp_targets)) { if (CMD_ARGC == 1) { int coreid = 0; diff --git a/src/target/startup.tcl b/src/target/startup.tcl index 290e79d1ee..1cc9bb7fda 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -114,10 +114,21 @@ proc ocd_process_reset_inner { MODE } { continue } - # don't wait for targets where examination is deferred - # they can not be halted anyway at this point - if { ![$t was_examined] && [$t examine_deferred] } { - continue + if { ![$t was_examined] } { + # don't wait for targets where examination is deferred + # they can not be halted anyway at this point + if { [$t examine_deferred] } { + continue + } + # try to re-examine or target state will be unknown + $t invoke-event examine-start + set err [catch "$t arp_examine allow-defer"] + if { $err } { + $t invoke-event examine-fail + return -code error [format "TARGET: %s - Not examined" $t] + } else { + $t invoke-event examine-end + } } # Wait up to 1 second for target to halt. Why 1sec? Cause @@ -208,31 +219,44 @@ proc init_target_events {} { proc init_board {} { } -proc mem2array {arrayname bitwidth address count {phys ""}} { - echo "DEPRECATED! use 'read_memory' not 'mem2array'" - - upvar $arrayname $arrayname - set $arrayname "" - set i 0 - - foreach elem [read_memory $address $bitwidth $count {*}$phys] { - set ${arrayname}($i) $elem - incr i - } -} - -proc array2mem {arrayname bitwidth address count {phys ""}} { - echo "DEPRECATED! use 'write_memory' not 'array2mem'" - - upvar $arrayname $arrayname - set data "" +lappend _telnet_autocomplete_skip _post_init_target_array_mem +proc _post_init_target_array_mem {} { + set targets [target names] + lappend targets "" - for {set i 0} {$i < $count} {incr i} { - lappend data [expr $${arrayname}($i)] + foreach t $targets { + if {$t != ""} { + set t "$t " + } + eval [format {lappend ::_telnet_autocomplete_skip "%smem2array"} $t] + eval [format {proc {%smem2array} {arrayname bitwidth address count {phys ""}} { + echo "DEPRECATED! use 'read_memory' not 'mem2array'" + + upvar $arrayname $arrayname + set $arrayname "" + set i 0 + + foreach elem [%sread_memory $address $bitwidth $count {*}$phys] { + set ${arrayname}($i) $elem + incr i + } + }} $t $t] + eval [format {lappend ::_telnet_autocomplete_skip "%sarray2mem"} $t] + eval [format {proc {%sarray2mem} {arrayname bitwidth address count {phys ""}} { + echo "DEPRECATED! use 'write_memory' not 'array2mem'" + + upvar $arrayname $arrayname + set data "" + + for {set i 0} {$i < $count} {incr i} { + lappend data [expr $${arrayname}($i)] + } + + %swrite_memory $address $bitwidth $data {*}$phys + }} $t $t] } - - write_memory $address $bitwidth $data {*}$phys } +lappend post_init_commands _post_init_target_array_mem # smp_on/smp_off were already DEPRECATED in v0.11.0 through http://openocd.zylin.com/4615 lappend _telnet_autocomplete_skip "aarch64 smp_on" @@ -270,3 +294,31 @@ proc "mips_m4k smp_off" {args} { echo "DEPRECATED! use 'mips_m4k smp off' not 'mips_m4k smp_off'" eval mips_m4k smp off $args } + +lappend _telnet_autocomplete_skip _post_init_target_cortex_a_cache_auto +proc _post_init_target_cortex_a_cache_auto {} { + set cortex_a_found 0 + + foreach t [target names] { + if { [$t cget -type] != "cortex_a" } { continue } + set cortex_a_found 1 + lappend ::_telnet_autocomplete_skip "$t cache auto" + proc "$t cache auto" { enable } { + echo "DEPRECATED! Don't use anymore '[dict get [info frame 0] proc] $enable' as it's always enabled" + } + } + + if { $cortex_a_found } { + lappend ::_telnet_autocomplete_skip "cache auto" + proc "cache auto" { enable } { + echo "DEPRECATED! Don't use anymore 'cache auto $enable' as it's always enabled" + } + } +} +lappend post_init_commands _post_init_target_cortex_a_cache_auto + +lappend _telnet_autocomplete_skip "cache_config l2x" +proc "cache_config l2x" {args} { + echo "DEPRECATED! use 'cache l2x conf' not 'cache_config l2x'" + eval cache_config l2x $args +} diff --git a/src/target/stm8.c b/src/target/stm8.c index d5731a214a..7785d40ef0 100644 --- a/src/target/stm8.c +++ b/src/target/stm8.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * OpenOCD STM8 target driver @@ -13,14 +13,12 @@ #include <helper/log.h> #include "target.h" #include "target_type.h" -#include "hello.h" #include "jtag/interface.h" #include "jtag/jtag.h" #include "jtag/swim.h" #include "register.h" #include "breakpoints.h" #include "algorithm.h" -#include "stm8.h" static struct reg_cache *stm8_build_reg_cache(struct target *target); static int stm8_read_core_reg(struct target *target, unsigned int num); @@ -38,7 +36,7 @@ static int (*adapter_speed)(int speed); extern struct adapter_driver *adapter_driver; static const struct { - unsigned id; + unsigned int id; const char *name; const uint8_t bits; enum reg_type type; @@ -54,6 +52,8 @@ static const struct { { 5, "cc", 8, REG_TYPE_UINT8, "general", "org.gnu.gdb.stm8.core", 0 }, }; +#define STM8_COMMON_MAGIC 0x53544D38U + #define STM8_NUM_REGS ARRAY_SIZE(stm8_regs) #define STM8_PC 0 #define STM8_A 1 @@ -168,6 +168,51 @@ struct stm8_comparator { enum hw_break_type type; }; +struct stm8_common { + unsigned int common_magic; + + void *arch_info; + struct reg_cache *core_cache; + uint32_t core_regs[STM8_NUM_REGS]; + + /* working area for fastdata access */ + struct working_area *fast_data_area; + + bool swim_configured; + bool bp_scanned; + uint8_t num_hw_bpoints; + uint8_t num_hw_bpoints_avail; + struct stm8_comparator *hw_break_list; + uint32_t blocksize; + uint32_t flashstart; + uint32_t flashend; + uint32_t eepromstart; + uint32_t eepromend; + uint32_t optionstart; + uint32_t optionend; + bool enable_step_irq; + + bool enable_stm8l; + uint32_t flash_cr2; + uint32_t flash_ncr2; + uint32_t flash_iapsr; + uint32_t flash_dukr; + uint32_t flash_pukr; + + /* cc value used for interrupt flags restore */ + uint32_t cc; + bool cc_valid; + + /* register cache to processor synchronization */ + int (*read_core_reg)(struct target *target, unsigned int num); + int (*write_core_reg)(struct target *target, unsigned int num); +}; + +static struct stm8_common *target_to_stm8(struct target *target) +{ + return target->arch_info; +} + static int stm8_adapter_read_memory(struct target *target, uint32_t addr, int size, int count, void *buf) { @@ -542,12 +587,12 @@ static int stm8_get_core_reg(struct reg *reg) int retval; struct stm8_core_reg *stm8_reg = reg->arch_info; struct target *target = stm8_reg->target; - struct stm8_common *stm8_target = target_to_stm8(target); + struct stm8_common *stm8 = target_to_stm8(target); if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; - retval = stm8_target->read_core_reg(target, stm8_reg->num); + retval = stm8->read_core_reg(target, stm8_reg->num); return retval; } @@ -689,15 +734,13 @@ static int stm8_write_flash(struct target *target, enum mem_type type, if (stm8->flash_ncr2) stm8_write_u8(target, stm8->flash_ncr2, ~(PRG + opt)); blocksize = blocksize_param; - } else - if ((bytecnt >= 4) && ((address & 0x3) == 0)) { + } else if ((bytecnt >= 4) && ((address & 0x3) == 0)) { if (stm8->flash_cr2) stm8_write_u8(target, stm8->flash_cr2, WPRG + opt); if (stm8->flash_ncr2) stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG + opt)); blocksize = 4; - } else - if (blocksize != 1) { + } else if (blocksize != 1) { if (stm8->flash_cr2) stm8_write_u8(target, stm8->flash_cr2, opt); if (stm8->flash_ncr2) @@ -827,7 +870,7 @@ static int stm8_poll(struct target *target) uint8_t csr1, csr2; #ifdef LOG_STM8 - LOG_DEBUG("target->state=%d", target->state); + LOG_DEBUG("target->state %s", target_state_name(target)); #endif /* read dm_csrx control regs */ @@ -982,9 +1025,9 @@ static int stm8_single_step_core(struct target *target) return ERROR_OK; } -static int stm8_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, - int debug_execution) +static int stm8_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, + bool debug_execution) { struct stm8_common *stm8 = target_to_stm8(target); struct breakpoint *breakpoint = NULL; @@ -994,7 +1037,7 @@ static int stm8_resume(struct target *target, int current, handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1006,7 +1049,7 @@ static int stm8_resume(struct target *target, int current, stm8_set_hwbreak(target, comparator_list); } - /* current = 1: continue on current pc, + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value, @@ -1108,8 +1151,7 @@ static int stm8_init_arch_info(struct target *target, return ERROR_OK; } -static int stm8_target_create(struct target *target, - Jim_Interp *interp) +static int stm8_target_create(struct target *target) { struct stm8_common *stm8 = calloc(1, sizeof(struct stm8_common)); @@ -1158,7 +1200,7 @@ static int stm8_write_core_reg(struct target *target, unsigned int num) return ERROR_OK; } -static const char *stm8_get_gdb_arch(struct target *target) +static const char *stm8_get_gdb_arch(const struct target *target) { return "stm8"; } @@ -1292,8 +1334,8 @@ static int stm8_arch_state(struct target *target) return ERROR_OK; } -static int stm8_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int stm8_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { LOG_DEBUG("%x " TARGET_ADDR_FMT " %x", current, address, handle_breakpoints); @@ -1303,11 +1345,11 @@ static int stm8_step(struct target *target, int current, struct breakpoint *breakpoint = NULL; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) { buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32, address); stm8->core_cache->reg_list[STM8_PC].dirty = true; @@ -1518,7 +1560,7 @@ static int stm8_remove_breakpoint(struct target *target, struct stm8_common *stm8 = target_to_stm8(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1552,8 +1594,8 @@ static int stm8_set_watchpoint(struct target *target, } if (watchpoint->length != 1) { - LOG_ERROR("Only watchpoints of length 1 are supported"); - return ERROR_TARGET_UNALIGNED_ACCESS; + LOG_ERROR("Only watchpoints of length 1 are supported"); + return ERROR_TARGET_UNALIGNED_ACCESS; } enum hw_break_type enable = 0; @@ -1654,7 +1696,7 @@ static int stm8_remove_watchpoint(struct target *target, struct stm8_common *stm8 = target_to_stm8(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1784,14 +1826,14 @@ static int stm8_checksum_memory(struct target *target, target_addr_t address, /* run to exit point. return error if exit point was not reached. */ static int stm8_run_and_wait(struct target *target, uint32_t entry_point, - int timeout_ms, uint32_t exit_point, struct stm8_common *stm8) + unsigned int timeout_ms, uint32_t exit_point, struct stm8_common *stm8) { uint32_t pc; int retval; /* This code relies on the target specific resume() and poll()->debug_entry() sequence to write register values to the processor and the read them back */ - retval = target_resume(target, 0, entry_point, 0, 1); + retval = target_resume(target, false, entry_point, false, true); if (retval != ERROR_OK) return retval; @@ -1819,7 +1861,7 @@ static int stm8_run_and_wait(struct target *target, uint32_t entry_point, static int stm8_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, - target_addr_t exit_point, int timeout_ms, void *arch_info) + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { struct stm8_common *stm8 = target_to_stm8(target); diff --git a/src/target/stm8.h b/src/target/stm8.h deleted file mode 100644 index bbda4feb68..0000000000 --- a/src/target/stm8.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* -* OpenOCD STM8 target driver -* Copyright (C) 2017 Ake Rehnman -* ake.rehnman(at)gmail.com -*/ - -#ifndef OPENOCD_TARGET_STM8_H -#define OPENOCD_TARGET_STM8_H - -struct target; - -#define STM8_COMMON_MAGIC 0x53544D38 -#define STM8_NUM_CORE_REGS 6 - -struct stm8_common { - uint32_t common_magic; - void *arch_info; - struct reg_cache *core_cache; - uint32_t core_regs[STM8_NUM_CORE_REGS]; - - /* working area for fastdata access */ - struct working_area *fast_data_area; - - bool swim_configured; - bool bp_scanned; - uint8_t num_hw_bpoints; - uint8_t num_hw_bpoints_avail; - struct stm8_comparator *hw_break_list; - uint32_t blocksize; - uint32_t flashstart; - uint32_t flashend; - uint32_t eepromstart; - uint32_t eepromend; - uint32_t optionstart; - uint32_t optionend; - bool enable_step_irq; - - bool enable_stm8l; - uint32_t flash_cr2; - uint32_t flash_ncr2; - uint32_t flash_iapsr; - uint32_t flash_dukr; - uint32_t flash_pukr; - - /* cc value used for interrupt flags restore */ - uint32_t cc; - bool cc_valid; - - /* register cache to processor synchronization */ - int (*read_core_reg)(struct target *target, unsigned int num); - int (*write_core_reg)(struct target *target, unsigned int num); -}; - -static inline struct stm8_common * -target_to_stm8(struct target *target) -{ - return target->arch_info; -} - -#endif /* OPENOCD_TARGET_STM8_H */ diff --git a/src/target/target.c b/src/target/target.c index 78073f6807..995adbc9d3 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -31,6 +31,8 @@ #endif #include <helper/align.h> +#include <helper/list.h> +#include <helper/nvp.h> #include <helper/time_support.h> #include <jtag/jtag.h> #include <flash/nor/core.h> @@ -51,114 +53,80 @@ /* default halt wait timeout (ms) */ #define DEFAULT_HALT_TIMEOUT 5000 +struct target_event_action { + enum target_event event; + Jim_Interp *interp; + Jim_Obj *body; + struct list_head list; +}; + static int target_read_buffer_default(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer); static int target_write_buffer_default(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer); -static int target_array2mem(Jim_Interp *interp, struct target *target, - int argc, Jim_Obj * const *argv); -static int target_mem2array(Jim_Interp *interp, struct target *target, - int argc, Jim_Obj * const *argv); static int target_register_user_commands(struct command_context *cmd_ctx); static int target_get_gdb_fileio_info_default(struct target *target, struct gdb_fileio_info *fileio_info); static int target_gdb_fileio_end_default(struct target *target, int retcode, int fileio_errno, bool ctrl_c); -/* targets */ -extern struct target_type arm7tdmi_target; -extern struct target_type arm720t_target; -extern struct target_type arm9tdmi_target; -extern struct target_type arm920t_target; -extern struct target_type arm966e_target; -extern struct target_type arm946e_target; -extern struct target_type arm926ejs_target; -extern struct target_type fa526_target; -extern struct target_type feroceon_target; -extern struct target_type dragonite_target; -extern struct target_type xscale_target; -extern struct target_type cortexm_target; -extern struct target_type cortexa_target; -extern struct target_type aarch64_target; -extern struct target_type cortexr4_target; -extern struct target_type arm11_target; -extern struct target_type ls1_sap_target; -extern struct target_type mips_m4k_target; -extern struct target_type mips_mips64_target; -extern struct target_type avr_target; -extern struct target_type dsp563xx_target; -extern struct target_type dsp5680xx_target; -extern struct target_type testee_target; -extern struct target_type avr32_ap7k_target; -extern struct target_type hla_target; -extern struct target_type nds32_v2_target; -extern struct target_type nds32_v3_target; -extern struct target_type nds32_v3m_target; -extern struct target_type esp32_target; -extern struct target_type esp32s2_target; -extern struct target_type esp32s3_target; -extern struct target_type or1k_target; -extern struct target_type quark_x10xx_target; -extern struct target_type quark_d20xx_target; -extern struct target_type stm8_target; -extern struct target_type riscv_target; -extern struct target_type mem_ap_target; -extern struct target_type esirisc_target; -extern struct target_type arcv2_target; - static struct target_type *target_types[] = { + // Keep in alphabetic order this list of targets + &aarch64_target, + &arcv2_target, + &arm11_target, + &arm720t_target, &arm7tdmi_target, - &arm9tdmi_target, &arm920t_target, - &arm720t_target, - &arm966e_target, - &arm946e_target, &arm926ejs_target, - &fa526_target, - &feroceon_target, - &dragonite_target, - &xscale_target, - &cortexm_target, + &arm946e_target, + &arm966e_target, + &arm9tdmi_target, + &armv8r_target, + &avr32_ap7k_target, + &avr_target, &cortexa_target, + &cortexm_target, &cortexr4_target, - &arm11_target, - &ls1_sap_target, - &mips_m4k_target, - &avr_target, + &dragonite_target, &dsp563xx_target, &dsp5680xx_target, - &testee_target, - &avr32_ap7k_target, - &hla_target, - &nds32_v2_target, - &nds32_v3_target, - &nds32_v3m_target, - &esp32_target, + &esirisc_target, &esp32s2_target, &esp32s3_target, + &esp32_target, + &fa526_target, + &feroceon_target, + &hla_target, + &ls1_sap_target, + &mem_ap_target, + &mips_m4k_target, + &mips_mips64_target, &or1k_target, - &quark_x10xx_target, &quark_d20xx_target, - &stm8_target, + &quark_x10xx_target, &riscv_target, - &mem_ap_target, - &esirisc_target, - &arcv2_target, - &aarch64_target, - &mips_mips64_target, - NULL, + &stm8_target, + &testee_target, + &xscale_target, + &xtensa_chip_target, }; struct target *all_targets; static struct target_event_callback *target_event_callbacks; static struct target_timer_callback *target_timer_callbacks; static int64_t target_timer_next_event_value; -static LIST_HEAD(target_reset_callback_list); -static LIST_HEAD(target_trace_callback_list); +static OOCD_LIST_HEAD(target_reset_callback_list); +static OOCD_LIST_HEAD(target_trace_callback_list); static const int polling_interval = TARGET_DEFAULT_POLLING_INTERVAL; -static LIST_HEAD(empty_smp_targets); +static OOCD_LIST_HEAD(empty_smp_targets); + +enum nvp_assert { + NVP_DEASSERT, + NVP_ASSERT, +}; -static const struct jim_nvp nvp_assert[] = { +static const struct nvp nvp_assert[] = { { .name = "assert", NVP_ASSERT }, { .name = "deassert", NVP_DEASSERT }, { .name = "T", NVP_ASSERT }, @@ -168,7 +136,7 @@ static const struct jim_nvp nvp_assert[] = { { .name = NULL, .value = -1 } }; -static const struct jim_nvp nvp_error_target[] = { +static const struct nvp nvp_error_target[] = { { .value = ERROR_TARGET_INVALID, .name = "err-invalid" }, { .value = ERROR_TARGET_INIT_FAILED, .name = "err-init-failed" }, { .value = ERROR_TARGET_TIMEOUT, .name = "err-timeout" }, @@ -185,16 +153,16 @@ static const struct jim_nvp nvp_error_target[] = { static const char *target_strerror_safe(int err) { - const struct jim_nvp *n; + const struct nvp *n; - n = jim_nvp_value2name_simple(nvp_error_target, err); + n = nvp_value2name(nvp_error_target, err); if (!n->name) return "unknown"; else return n->name; } -static const struct jim_nvp nvp_target_event[] = { +static const struct nvp nvp_target_event[] = { { .value = TARGET_EVENT_GDB_HALT, .name = "gdb-halt" }, { .value = TARGET_EVENT_HALTED, .name = "halted" }, @@ -234,28 +202,29 @@ static const struct jim_nvp nvp_target_event[] = { { .value = TARGET_EVENT_TRACE_CONFIG, .name = "trace-config" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x100, .name = "semihosting-user-cmd-0x100" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x101, .name = "semihosting-user-cmd-0x101" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x102, .name = "semihosting-user-cmd-0x102" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x103, .name = "semihosting-user-cmd-0x103" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x104, .name = "semihosting-user-cmd-0x104" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x105, .name = "semihosting-user-cmd-0x105" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x106, .name = "semihosting-user-cmd-0x106" }, - { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x107, .name = "semihosting-user-cmd-0x107" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X100, .name = "semihosting-user-cmd-0x100" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X101, .name = "semihosting-user-cmd-0x101" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X102, .name = "semihosting-user-cmd-0x102" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X103, .name = "semihosting-user-cmd-0x103" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X104, .name = "semihosting-user-cmd-0x104" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X105, .name = "semihosting-user-cmd-0x105" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X106, .name = "semihosting-user-cmd-0x106" }, + { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X107, .name = "semihosting-user-cmd-0x107" }, { .name = NULL, .value = -1 } }; -static const struct jim_nvp nvp_target_state[] = { +static const struct nvp nvp_target_state[] = { { .name = "unknown", .value = TARGET_UNKNOWN }, { .name = "running", .value = TARGET_RUNNING }, { .name = "halted", .value = TARGET_HALTED }, { .name = "reset", .value = TARGET_RESET }, { .name = "debug-running", .value = TARGET_DEBUG_RUNNING }, + { .name = "unavailable", .value = TARGET_UNAVAILABLE }, { .name = NULL, .value = -1 }, }; -static const struct jim_nvp nvp_target_debug_reason[] = { +static const struct nvp nvp_target_debug_reason[] = { { .name = "debug-request", .value = DBG_REASON_DBGRQ }, { .name = "breakpoint", .value = DBG_REASON_BREAKPOINT }, { .name = "watchpoint", .value = DBG_REASON_WATCHPOINT }, @@ -268,7 +237,7 @@ static const struct jim_nvp nvp_target_debug_reason[] = { { .name = NULL, .value = -1 }, }; -static const struct jim_nvp nvp_target_endian[] = { +static const struct nvp nvp_target_endian[] = { { .name = "big", .value = TARGET_BIG_ENDIAN }, { .name = "little", .value = TARGET_LITTLE_ENDIAN }, { .name = "be", .value = TARGET_BIG_ENDIAN }, @@ -276,7 +245,7 @@ static const struct jim_nvp nvp_target_endian[] = { { .name = NULL, .value = -1 }, }; -static const struct jim_nvp nvp_reset_modes[] = { +static const struct nvp nvp_reset_modes[] = { { .name = "unknown", .value = RESET_UNKNOWN }, { .name = "run", .value = RESET_RUN }, { .name = "halt", .value = RESET_HALT }, @@ -284,11 +253,11 @@ static const struct jim_nvp nvp_reset_modes[] = { { .name = NULL, .value = -1 }, }; -const char *debug_reason_name(struct target *t) +const char *debug_reason_name(const struct target *t) { const char *cp; - cp = jim_nvp_value2name_simple(nvp_target_debug_reason, + cp = nvp_value2name(nvp_target_debug_reason, t->debug_reason)->name; if (!cp) { LOG_ERROR("Invalid debug reason: %d", (int)(t->debug_reason)); @@ -297,10 +266,10 @@ const char *debug_reason_name(struct target *t) return cp; } -const char *target_state_name(struct target *t) +const char *target_state_name(const struct target *t) { const char *cp; - cp = jim_nvp_value2name_simple(nvp_target_state, t->state)->name; + cp = nvp_value2name(nvp_target_state, t->state)->name; if (!cp) { LOG_ERROR("Invalid target state: %d", (int)(t->state)); cp = "(*BUG*unknown*BUG*)"; @@ -315,7 +284,7 @@ const char *target_state_name(struct target *t) const char *target_event_name(enum target_event event) { const char *cp; - cp = jim_nvp_value2name_simple(nvp_target_event, event)->name; + cp = nvp_value2name(nvp_target_event, event)->name; if (!cp) { LOG_ERROR("Invalid target event: %d", (int)(event)); cp = "(*BUG*unknown*BUG*)"; @@ -326,7 +295,7 @@ const char *target_event_name(enum target_event event) const char *target_reset_mode_name(enum target_reset_mode reset_mode) { const char *cp; - cp = jim_nvp_value2name_simple(nvp_reset_modes, reset_mode)->name; + cp = nvp_value2name(nvp_reset_modes, reset_mode)->name; if (!cp) { LOG_ERROR("Invalid target reset mode: %d", (int)(reset_mode)); cp = "(*BUG*unknown*BUG*)"; @@ -334,23 +303,6 @@ const char *target_reset_mode_name(enum target_reset_mode reset_mode) return cp; } -/* determine the number of the new target */ -static int new_target_number(void) -{ - struct target *t; - int x; - - /* number is 0 based */ - x = -1; - t = all_targets; - while (t) { - if (x < t->target_number) - x = t->target_number; - t = t->next; - } - return x + 1; -} - static void append_to_list_all_targets(struct target *target) { struct target **t = &all_targets; @@ -486,7 +438,7 @@ void target_buffer_set_u16_array(struct target *target, uint8_t *buffer, uint32_ target_buffer_set_u16(target, &buffer[i * 2], srcbuf[i]); } -/* return a pointer to a configured target; id is name or number */ +/* return a pointer to a configured target; id is name or index in all_targets */ struct target *get_target(const char *id) { struct target *target; @@ -499,36 +451,17 @@ struct target *get_target(const char *id) return target; } - /* It's OK to remove this fallback sometime after August 2010 or so */ - - /* no match, try as number */ - unsigned num; - if (parse_uint(id, &num) != ERROR_OK) + /* try as index */ + unsigned int index, counter; + if (parse_uint(id, &index) != ERROR_OK) return NULL; - for (target = all_targets; target; target = target->next) { - if (target->target_number == (int)num) { - LOG_WARNING("use '%s' as target identifier, not '%u'", - target_name(target), num); - return target; - } - } - - return NULL; -} - -/* returns a pointer to the n-th configured target */ -struct target *get_target_by_num(int num) -{ - struct target *target = all_targets; - - while (target) { - if (target->target_number == num) - return target; - target = target->next; - } + for (target = all_targets, counter = index; + target && counter; + target = target->next, --counter) + ; - return NULL; + return target; } struct target *get_current_target(struct command_context *cmd_ctx) @@ -629,8 +562,8 @@ int target_halt(struct target *target) * hand the infrastructure for running such helpers might use this * procedure but rely on hardware breakpoint to detect termination.) */ -int target_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution) +int target_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution) { int retval; @@ -654,10 +587,11 @@ int target_resume(struct target *target, int current, target_addr_t address, * Disable polling during resume() to guarantee the execution of handlers * in the correct order. */ - bool save_poll = jtag_poll_get_enabled(); - jtag_poll_set_enabled(false); - retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution); - jtag_poll_set_enabled(save_poll); + bool save_poll_mask = jtag_poll_mask(); + retval = target->type->resume(target, current, address, handle_breakpoints, + debug_execution); + jtag_poll_unmask(save_poll_mask); + if (retval != ERROR_OK) return retval; @@ -670,8 +604,8 @@ static int target_process_reset(struct command_invocation *cmd, enum target_rese { char buf[100]; int retval; - struct jim_nvp *n; - n = jim_nvp_value2name_simple(nvp_reset_modes, reset_mode); + const struct nvp *n; + n = nvp_value2name(nvp_reset_modes, reset_mode); if (!n->name) { LOG_ERROR("invalid reset mode"); return ERROR_FAIL; @@ -685,14 +619,12 @@ static int target_process_reset(struct command_invocation *cmd, enum target_rese * more predictable, i.e. dr/irscan & pathmove in events will * not have JTAG operations injected into the middle of a sequence. */ - bool save_poll = jtag_poll_get_enabled(); - - jtag_poll_set_enabled(false); + bool save_poll_mask = jtag_poll_mask(); sprintf(buf, "ocd_process_reset %s", n->name); retval = Jim_Eval(cmd->ctx->interp, buf); - jtag_poll_set_enabled(save_poll); + jtag_poll_unmask(save_poll_mask); if (retval != JIM_OK) { Jim_MakeErrorMessage(cmd->ctx->interp); @@ -749,10 +681,14 @@ static int default_check_reset(struct target *target) * Keep in sync */ int target_examine_one(struct target *target) { + LOG_TARGET_DEBUG(target, "Examination started"); + target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_START); int retval = target->type->examine(target); if (retval != ERROR_OK) { + LOG_TARGET_ERROR(target, "Examination failed"); + LOG_TARGET_DEBUG(target, "examine() returned error code %d", retval); target_reset_examined(target); target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_FAIL); return retval; @@ -761,6 +697,7 @@ int target_examine_one(struct target *target) target_set_examined(target); target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_END); + LOG_TARGET_INFO(target, "Examination succeed"); return ERROR_OK; } @@ -806,7 +743,7 @@ int target_examine(void) return retval; } -const char *target_type_name(struct target *target) +const char *target_type_name(const struct target *target) { return target->type->name; } @@ -847,7 +784,7 @@ int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info) + unsigned int timeout_ms, void *arch_info) { int retval = ERROR_FAIL; @@ -931,7 +868,7 @@ int target_start_algorithm(struct target *target, int target_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - target_addr_t exit_point, int timeout_ms, + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) { int retval = ERROR_FAIL; @@ -1273,6 +1210,10 @@ int target_run_read_async_algorithm(struct target *target, /* Avoid GDB timeouts */ keep_alive(); + if (openocd_is_shutdown_pending()) { + retval = ERROR_SERVER_INTERRUPTED; + break; + } } if (retval != ERROR_OK) { @@ -1363,7 +1304,7 @@ int target_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { if ((target->state != TARGET_HALTED) && (breakpoint->type != BKPT_HARD)) { - LOG_WARNING("target %s is not halted (add breakpoint)", target_name(target)); + LOG_TARGET_ERROR(target, "not halted (add breakpoint)"); return ERROR_TARGET_NOT_HALTED; } return target->type->add_breakpoint(target, breakpoint); @@ -1373,7 +1314,7 @@ int target_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (add context breakpoint)", target_name(target)); + LOG_TARGET_ERROR(target, "not halted (add context breakpoint)"); return ERROR_TARGET_NOT_HALTED; } return target->type->add_context_breakpoint(target, breakpoint); @@ -1383,7 +1324,7 @@ int target_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (add hybrid breakpoint)", target_name(target)); + LOG_TARGET_ERROR(target, "not halted (add hybrid breakpoint)"); return ERROR_TARGET_NOT_HALTED; } return target->type->add_hybrid_breakpoint(target, breakpoint); @@ -1399,7 +1340,7 @@ int target_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (add watchpoint)", target_name(target)); + LOG_TARGET_ERROR(target, "not halted (add watchpoint)"); return ERROR_TARGET_NOT_HALTED; } return target->type->add_watchpoint(target, watchpoint); @@ -1413,7 +1354,7 @@ int target_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (hit watchpoint)", target->cmd_name); + LOG_TARGET_ERROR(target, "not halted (hit watchpoint)"); return ERROR_TARGET_NOT_HALTED; } @@ -1427,7 +1368,7 @@ int target_hit_watchpoint(struct target *target, return target->type->hit_watchpoint(target, hit_watchpoint); } -const char *target_get_gdb_arch(struct target *target) +const char *target_get_gdb_arch(const struct target *target) { if (!target->type->get_gdb_arch) return NULL; @@ -1467,7 +1408,7 @@ int target_get_gdb_reg_list_noread(struct target *target, return target_get_gdb_reg_list(target, reg_list, reg_list_size, reg_class); } -bool target_supports_gdb_connection(struct target *target) +bool target_supports_gdb_connection(const struct target *target) { /* * exclude all the targets that don't provide get_gdb_reg_list @@ -1477,7 +1418,7 @@ bool target_supports_gdb_connection(struct target *target) } int target_step(struct target *target, - int current, target_addr_t address, int handle_breakpoints) + bool current, target_addr_t address, bool handle_breakpoints) { int retval; @@ -1495,7 +1436,7 @@ int target_step(struct target *target, int target_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (gdb fileio)", target->cmd_name); + LOG_TARGET_ERROR(target, "not halted (gdb fileio)"); return ERROR_TARGET_NOT_HALTED; } return target->type->get_gdb_fileio_info(target, fileio_info); @@ -1504,7 +1445,7 @@ int target_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fi int target_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c) { if (target->state != TARGET_HALTED) { - LOG_WARNING("target %s is not halted (gdb fileio end)", target->cmd_name); + LOG_TARGET_ERROR(target, "not halted (gdb fileio end)"); return ERROR_TARGET_NOT_HALTED; } return target->type->gdb_fileio_end(target, retcode, fileio_errno, ctrl_c); @@ -1512,14 +1453,14 @@ int target_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, target_addr_t target_address_max(struct target *target) { - unsigned bits = target_address_bits(target); + unsigned int bits = target_address_bits(target); if (sizeof(target_addr_t) * 8 == bits) return (target_addr_t) -1; else return (((target_addr_t) 1) << bits) - 1; } -unsigned target_address_bits(struct target *target) +unsigned int target_address_bits(struct target *target) { if (target->type->address_bits) return target->type->address_bits(target); @@ -1567,7 +1508,7 @@ static int target_init_one(struct command_context *cmd_ctx, */ if (type->mmu) { if (!type->virt2phys) { - LOG_ERROR("type '%s' is missing virt2phys", type->name); + LOG_ERROR("type '%s' is missing virt2phys", target_name(target)); type->virt2phys = identity_virt2phys; } } else { @@ -1576,7 +1517,7 @@ static int target_init_one(struct command_context *cmd_ctx, * ensure that virt2phys() is always an identity mapping. */ if (type->write_phys_memory || type->read_phys_memory || type->virt2phys) - LOG_WARNING("type '%s' has bad MMU hooks", type->name); + LOG_WARNING("type '%s' has bad MMU hooks", target_name(target)); type->mmu = no_mmu; type->write_phys_memory = type->write_memory; @@ -1860,7 +1801,7 @@ int target_call_reset_callbacks(struct target *target, enum target_reset_mode re struct target_reset_callback *callback; LOG_DEBUG("target reset %i (%s)", reset_mode, - jim_nvp_value2name_simple(nvp_reset_modes, reset_mode)->name); + nvp_value2name(nvp_reset_modes, reset_mode)->name); list_for_each_entry(callback, &target_reset_callback_list, list) callback->callback(target, reset_mode, callback->priv); @@ -1944,13 +1885,13 @@ static int target_call_timer_callbacks_check_time(int checktime) return ERROR_OK; } -int target_call_timer_callbacks() +int target_call_timer_callbacks(void) { return target_call_timer_callbacks_check_time(1); } /* invoke periodic callbacks immediately */ -int target_call_timer_callbacks_now() +int target_call_timer_callbacks_now(void) { return target_call_timer_callbacks_check_time(0); } @@ -2071,7 +2012,7 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w struct working_area *new_wa = malloc(sizeof(*new_wa)); if (new_wa) { new_wa->next = NULL; - new_wa->size = target->working_area_size & ~3UL; /* 4-byte align */ + new_wa->size = ALIGN_DOWN(target->working_area_size, 4); /* 4-byte align */ new_wa->address = target->working_area; new_wa->backup = NULL; new_wa->user = NULL; @@ -2082,8 +2023,7 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w } /* only allocate multiples of 4 byte */ - if (size % 4) - size = (size + 3) & (~3UL); + size = ALIGN_UP(size, 4); struct working_area *c = target->working_areas; @@ -2237,7 +2177,7 @@ uint32_t target_get_working_area_avail(struct target *target) uint32_t max_size = 0; if (!c) - return target->working_area_size; + return ALIGN_DOWN(target->working_area_size, 4); while (c) { if (c->free && max_size < c->size) @@ -2251,6 +2191,9 @@ uint32_t target_get_working_area_avail(struct target *target) static void target_destroy(struct target *target) { + breakpoint_remove_all(target); + watchpoint_remove_all(target); + if (target->type->deinit_target) target->type->deinit_target(target); @@ -2260,12 +2203,11 @@ static void target_destroy(struct target *target) jtag_unregister_event_callback(jtag_enable_callback, target); - struct target_event_action *teap = target->event_action; - while (teap) { - struct target_event_action *next = teap->next; + struct target_event_action *teap, *temp; + list_for_each_entry_safe(teap, temp, &target->events_action, list) { + list_del(&teap->list); Jim_DecrRefCount(teap->interp, teap->body); free(teap); - teap = next; } target_free_all_working_areas(target); @@ -2376,7 +2318,7 @@ int target_profiling_default(struct target *target, uint32_t *samples, uint32_t t = buf_get_u32(reg->value, 0, 32); samples[sample_count++] = t; /* current pc, addr = 0, do not handle breakpoints, not debugging */ - retval = target_resume(target, 1, 0, 0, 0); + retval = target_resume(target, true, 0, false, false); target_poll(target); alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */ } else if (target->state == TARGET_RUNNING) { @@ -2879,10 +2821,10 @@ COMMAND_HANDLER(handle_targets_command) } } - struct target *target = all_targets; + unsigned int index = 0; command_print(CMD, " TargetName Type Endian TapName State "); command_print(CMD, "-- ------------------ ---------- ------ ------------------ ------------"); - while (target) { + for (struct target *target = all_targets; target; target = target->next, ++index) { const char *state; char marker = ' '; @@ -2897,15 +2839,13 @@ COMMAND_HANDLER(handle_targets_command) /* keep columns lined up to match the headers above */ command_print(CMD, "%2d%c %-18s %-10s %-6s %-18s %s", - target->target_number, + index, marker, target_name(target), target_type_name(target), - jim_nvp_value2name_simple(nvp_target_endian, - target->endianness)->name, + nvp_value2name(nvp_target_endian, target->endianness)->name, target->tap->dotted_name, state); - target = target->next; } return retval; @@ -3065,14 +3005,14 @@ static int handle_target(void *priv) target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); } if (target->backoff.times > 0) { - LOG_USER("Polling target %s failed, trying to reexamine", target_name(target)); + LOG_TARGET_ERROR(target, "Polling failed, trying to reexamine"); target_reset_examined(target); retval = target_examine_one(target); /* Target examination could have failed due to unstable connection, * but we set the examined flag anyway to repoll it later */ if (retval != ERROR_OK) { target_set_examined(target); - LOG_USER("Examination failed, GDB will be halted. Polling again in %dms", + LOG_TARGET_ERROR(target, "Examination failed, GDB will be halted. Polling again in %dms", target->backoff.times * polling_interval); return retval; } @@ -3091,6 +3031,10 @@ COMMAND_HANDLER(handle_reg_command) LOG_DEBUG("-"); struct target *target = get_current_target(CMD_CTX); + if (!target_was_examined(target)) { + LOG_ERROR("Target not examined yet"); + return ERROR_TARGET_NOT_EXAMINED; + } struct reg *reg = NULL; /* list all available registers for the current target */ @@ -3099,14 +3043,14 @@ COMMAND_HANDLER(handle_reg_command) unsigned int count = 0; while (cache) { - unsigned i; + unsigned int i; command_print(CMD, "===== %s", cache->name); for (i = 0, reg = cache->reg_list; i < cache->num_regs; i++, reg++, count++) { - if (reg->exist == false || reg->hidden) + if (!reg->exist || reg->hidden) continue; /* only print cached values if they are valid */ if (reg->valid) { @@ -3134,13 +3078,13 @@ COMMAND_HANDLER(handle_reg_command) /* access a single register by its ordinal number */ if ((CMD_ARGV[0][0] >= '0') && (CMD_ARGV[0][0] <= '9')) { - unsigned num; + unsigned int num; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct reg_cache *cache = target->reg_cache; unsigned int count = 0; while (cache) { - unsigned i; + unsigned int i; for (i = 0; i < cache->num_regs; i++) { if (count++ == num) { reg = &cache->reg_list[i]; @@ -3155,7 +3099,7 @@ COMMAND_HANDLER(handle_reg_command) if (!reg) { command_print(CMD, "%i is out of bounds, the current target " "has only %i registers (0 - %i)", num, count, count - 1); - return ERROR_OK; + return ERROR_FAIL; } } else { /* access a single register by its name */ @@ -3174,9 +3118,9 @@ COMMAND_HANDLER(handle_reg_command) if ((CMD_ARGC == 1) || ((CMD_ARGC == 2) && !((CMD_ARGV[1][0] >= '0') && (CMD_ARGV[1][0] <= '9')))) { if ((CMD_ARGC == 2) && (strcmp(CMD_ARGV[1], "force") == 0)) - reg->valid = 0; + reg->valid = false; - if (reg->valid == 0) { + if (!reg->valid) { int retval = reg->type->get(reg); if (retval != ERROR_OK) { LOG_ERROR("Could not read register '%s'", reg->name); @@ -3192,11 +3136,18 @@ COMMAND_HANDLER(handle_reg_command) /* set register value */ if (CMD_ARGC == 2) { uint8_t *buf = malloc(DIV_ROUND_UP(reg->size, 8)); - if (!buf) + if (!buf) { + LOG_ERROR("Failed to allocate memory"); return ERROR_FAIL; - str_to_buf(CMD_ARGV[1], strlen(CMD_ARGV[1]), buf, reg->size, 0); + } + + int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[1], buf, reg->size); + if (retval != ERROR_OK) { + free(buf); + return retval; + } - int retval = reg->type->set(reg, buf); + retval = reg->type->set(reg, buf); if (retval != ERROR_OK) { LOG_ERROR("Could not write to register '%s'", reg->name); } else { @@ -3214,7 +3165,7 @@ COMMAND_HANDLER(handle_reg_command) not_found: command_print(CMD, "register %s not found in current target", CMD_ARGV[0]); - return ERROR_OK; + return ERROR_FAIL; } COMMAND_HANDLER(handle_poll_command) @@ -3251,7 +3202,7 @@ COMMAND_HANDLER(handle_wait_halt_command) if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned ms = DEFAULT_HALT_TIMEOUT; + unsigned int ms = DEFAULT_HALT_TIMEOUT; if (1 == CMD_ARGC) { int retval = parse_uint(CMD_ARGV[0], &ms); if (retval != ERROR_OK) @@ -3268,7 +3219,7 @@ COMMAND_HANDLER(handle_wait_halt_command) * * After 500ms, keep_alive() is invoked */ -int target_wait_state(struct target *target, enum target_state state, int ms) +int target_wait_state(struct target *target, enum target_state state, unsigned int ms) { int retval; int64_t then = 0, cur; @@ -3285,15 +3236,18 @@ int target_wait_state(struct target *target, enum target_state state, int ms) once = false; then = timeval_ms(); LOG_DEBUG("waiting for target %s...", - jim_nvp_value2name_simple(nvp_target_state, state)->name); + nvp_value2name(nvp_target_state, state)->name); } - if (cur-then > 500) + if (cur - then > 500) { keep_alive(); + if (openocd_is_shutdown_pending()) + return ERROR_SERVER_INTERRUPTED; + } if ((cur-then) > ms) { LOG_ERROR("timed out while waiting for target %s", - jim_nvp_value2name_simple(nvp_target_state, state)->name); + nvp_value2name(nvp_target_state, state)->name); return ERROR_FAIL; } } @@ -3314,7 +3268,7 @@ COMMAND_HANDLER(handle_halt_command) return retval; if (CMD_ARGC == 1) { - unsigned wait_local; + unsigned int wait_local; retval = parse_uint(CMD_ARGV[0], &wait_local); if (retval != ERROR_OK) return ERROR_COMMAND_SYNTAX_ERROR; @@ -3343,8 +3297,8 @@ COMMAND_HANDLER(handle_reset_command) enum target_reset_mode reset_mode = RESET_RUN; if (CMD_ARGC == 1) { - const struct jim_nvp *n; - n = jim_nvp_name2value_simple(nvp_reset_modes, CMD_ARGV[0]); + const struct nvp *n; + n = nvp_name2value(nvp_reset_modes, CMD_ARGV[0]); if ((!n->name) || (n->value == RESET_UNKNOWN)) return ERROR_COMMAND_SYNTAX_ERROR; reset_mode = n->value; @@ -3357,7 +3311,7 @@ COMMAND_HANDLER(handle_reset_command) COMMAND_HANDLER(handle_resume_command) { - int current = 1; + bool current = true; if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; @@ -3369,10 +3323,10 @@ COMMAND_HANDLER(handle_resume_command) target_addr_t addr = 0; if (CMD_ARGC == 1) { COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - current = 0; + current = false; } - return target_resume(target, current, addr, 1, 0); + return target_resume(target, current, addr, true, false); } COMMAND_HANDLER(handle_step_command) @@ -3394,18 +3348,18 @@ COMMAND_HANDLER(handle_step_command) struct target *target = get_current_target(CMD_CTX); - return target_step(target, current_pc, addr, 1); + return target_step(target, current_pc, addr, true); } void target_handle_md_output(struct command_invocation *cmd, - struct target *target, target_addr_t address, unsigned size, - unsigned count, const uint8_t *buffer) + struct target *target, target_addr_t address, unsigned int size, + unsigned int count, const uint8_t *buffer) { - const unsigned line_bytecnt = 32; - unsigned line_modulo = line_bytecnt / size; + const unsigned int line_bytecnt = 32; + unsigned int line_modulo = line_bytecnt / size; char output[line_bytecnt * 4 + 1]; - unsigned output_len = 0; + unsigned int output_len = 0; const char *value_fmt; switch (size) { @@ -3427,7 +3381,7 @@ void target_handle_md_output(struct command_invocation *cmd, return; } - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { if (i % line_modulo == 0) { output_len += snprintf(output + output_len, sizeof(output) - output_len, @@ -3466,7 +3420,7 @@ COMMAND_HANDLER(handle_md_command) if (CMD_ARGC < 1) return ERROR_COMMAND_SYNTAX_ERROR; - unsigned size = 0; + unsigned int size = 0; switch (CMD_NAME[2]) { case 'd': size = 8; @@ -3499,7 +3453,7 @@ COMMAND_HANDLER(handle_md_command) target_addr_t address; COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); - unsigned count = 1; + unsigned int count = 1; if (CMD_ARGC == 2) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count); @@ -3525,22 +3479,22 @@ typedef int (*target_write_fn)(struct target *target, static int target_fill_mem(struct target *target, target_addr_t address, target_write_fn fn, - unsigned data_size, + unsigned int data_size, /* value */ uint64_t b, /* count */ - unsigned c) + unsigned int c) { /* We have to write in reasonably large chunks to be able * to fill large memory areas with any sane speed */ - const unsigned chunk_size = 16384; + const unsigned int chunk_size = 16384; uint8_t *target_buf = malloc(chunk_size * data_size); if (!target_buf) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - for (unsigned i = 0; i < chunk_size; i++) { + for (unsigned int i = 0; i < chunk_size; i++) { switch (data_size) { case 8: target_buffer_set_u64(target, target_buf + i * data_size, b); @@ -3561,8 +3515,8 @@ static int target_fill_mem(struct target *target, int retval = ERROR_OK; - for (unsigned x = 0; x < c; x += chunk_size) { - unsigned current; + for (unsigned int x = 0; x < c; x += chunk_size) { + unsigned int current; current = c - x; if (current > chunk_size) current = chunk_size; @@ -3571,6 +3525,11 @@ static int target_fill_mem(struct target *target, break; /* avoid GDB timeouts */ keep_alive(); + + if (openocd_is_shutdown_pending()) { + retval = ERROR_SERVER_INTERRUPTED; + break; + } } free(target_buf); @@ -3599,12 +3558,12 @@ COMMAND_HANDLER(handle_mw_command) uint64_t value; COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], value); - unsigned count = 1; + unsigned int count = 1; if (CMD_ARGC == 3) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], count); struct target *target = get_current_target(CMD_CTX); - unsigned wordsize; + unsigned int wordsize; switch (CMD_NAME[2]) { case 'd': wordsize = 8; @@ -3900,11 +3859,11 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver for (t = 0; t < buf_cnt; t++) { if (data[t] != buffer[t]) { command_print(CMD, - "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x", - diffs, - (unsigned)(t + image.sections[i].base_address), - data[t], - buffer[t]); + "diff %d address " TARGET_ADDR_FMT ". Was 0x%02" PRIx8 " instead of 0x%02" PRIx8, + diffs, + t + image.sections[i].base_address, + data[t], + buffer[t]); if (diffs++ >= 127) { command_print(CMD, "More than 128 errors, the rest are not printed."); free(data); @@ -3913,6 +3872,12 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver } } keep_alive(); + if (openocd_is_shutdown_pending()) { + retval = ERROR_SERVER_INTERRUPTED; + free(data); + free(buffer); + goto done; + } } } free(data); @@ -3964,25 +3929,25 @@ static int handle_bp_command_list(struct command_invocation *cmd) while (breakpoint) { if (breakpoint->type == BKPT_SOFT) { char *buf = buf_to_hex_str(breakpoint->orig_instr, - breakpoint->length); - command_print(cmd, "IVA breakpoint: " TARGET_ADDR_FMT ", 0x%x, 0x%s", + breakpoint->length * 8); + command_print(cmd, "Software breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, orig_instr=0x%s", breakpoint->address, breakpoint->length, buf); free(buf); } else { if ((breakpoint->address == 0) && (breakpoint->asid != 0)) - command_print(cmd, "Context breakpoint: 0x%8.8" PRIx32 ", 0x%x, %u", + command_print(cmd, "Context breakpoint: asid=0x%8.8" PRIx32 ", len=0x%x, num=%u", breakpoint->asid, breakpoint->length, breakpoint->number); else if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { - command_print(cmd, "Hybrid breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %u", + command_print(cmd, "Hybrid breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, num=%u", breakpoint->address, breakpoint->length, breakpoint->number); command_print(cmd, "\t|--->linked with ContextID: 0x%8.8" PRIx32, breakpoint->asid); } else - command_print(cmd, "Breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %u", + command_print(cmd, "Hardware breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, num=%u", breakpoint->address, breakpoint->length, breakpoint->number); } @@ -3993,7 +3958,7 @@ static int handle_bp_command_list(struct command_invocation *cmd) } static int handle_bp_command_set(struct command_invocation *cmd, - target_addr_t addr, uint32_t asid, uint32_t length, int hw) + target_addr_t addr, uint32_t asid, unsigned int length, int hw) { struct target *target = get_current_target(cmd->ctx); int retval; @@ -4006,7 +3971,7 @@ static int handle_bp_command_set(struct command_invocation *cmd, } else if (addr == 0) { if (!target->type->add_context_breakpoint) { - LOG_ERROR("Context breakpoint not available"); + LOG_TARGET_ERROR(target, "Context breakpoint not available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } retval = context_breakpoint_add(target, asid, length, hw); @@ -4016,7 +3981,7 @@ static int handle_bp_command_set(struct command_invocation *cmd, } else { if (!target->type->add_hybrid_breakpoint) { - LOG_ERROR("Hybrid breakpoint not available"); + LOG_TARGET_ERROR(target, "Hybrid breakpoint not available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } retval = hybrid_breakpoint_add(target, addr, asid, length, hw); @@ -4073,21 +4038,31 @@ COMMAND_HANDLER(handle_bp_command) COMMAND_HANDLER(handle_rbp_command) { + int retval; + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; struct target *target = get_current_target(CMD_CTX); if (!strcmp(CMD_ARGV[0], "all")) { - breakpoint_remove_all(target); + retval = breakpoint_remove_all(target); + + if (retval != ERROR_OK) { + command_print(CMD, "Error encountered during removal of all breakpoints."); + command_print(CMD, "Some breakpoints may have remained set."); + } } else { target_addr_t addr; COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - breakpoint_remove(target, addr); + retval = breakpoint_remove(target, addr); + + if (retval != ERROR_OK) + command_print(CMD, "Error during removal of breakpoint at address " TARGET_ADDR_FMT, addr); } - return ERROR_OK; + return retval; } COMMAND_HANDLER(handle_wp_command) @@ -4098,13 +4073,14 @@ COMMAND_HANDLER(handle_wp_command) struct watchpoint *watchpoint = target->watchpoints; while (watchpoint) { + char wp_type = (watchpoint->rw == WPT_READ ? 'r' : (watchpoint->rw == WPT_WRITE ? 'w' : 'a')); command_print(CMD, "address: " TARGET_ADDR_FMT - ", len: 0x%8.8" PRIx32 - ", r/w/a: %i, value: 0x%8.8" PRIx32 - ", mask: 0x%8.8" PRIx32, + ", len: 0x%8.8x" + ", r/w/a: %c, value: 0x%8.8" PRIx64 + ", mask: 0x%8.8" PRIx64, watchpoint->address, watchpoint->length, - (int)watchpoint->rw, + wp_type, watchpoint->value, watchpoint->mask); watchpoint = watchpoint->next; @@ -4115,15 +4091,20 @@ COMMAND_HANDLER(handle_wp_command) enum watchpoint_rw type = WPT_ACCESS; target_addr_t addr = 0; uint32_t length = 0; - uint32_t data_value = 0x0; - uint32_t data_mask = 0xffffffff; + uint64_t data_value = 0x0; + uint64_t data_mask = WATCHPOINT_IGNORE_DATA_VALUE_MASK; + bool mask_specified = false; switch (CMD_ARGC) { case 5: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], data_mask); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[4], data_mask); + mask_specified = true; /* fall through */ case 4: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], data_value); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], data_value); + // if user specified only data value without mask - the mask should be 0 + if (!mask_specified) + data_mask = 0; /* fall through */ case 3: switch (CMD_ARGV[2][0]) { @@ -4137,7 +4118,7 @@ COMMAND_HANDLER(handle_wp_command) type = WPT_ACCESS; break; default: - LOG_ERROR("invalid watchpoint mode ('%c')", CMD_ARGV[2][0]); + LOG_TARGET_ERROR(target, "invalid watchpoint mode ('%c')", CMD_ARGV[2][0]); return ERROR_COMMAND_SYNTAX_ERROR; } /* fall through */ @@ -4153,23 +4134,37 @@ COMMAND_HANDLER(handle_wp_command) int retval = watchpoint_add(target, addr, length, type, data_value, data_mask); if (retval != ERROR_OK) - LOG_ERROR("Failure setting watchpoints"); + LOG_TARGET_ERROR(target, "Failure setting watchpoints"); return retval; } COMMAND_HANDLER(handle_rwp_command) { + int retval; + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - target_addr_t addr; - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - struct target *target = get_current_target(CMD_CTX); - watchpoint_remove(target, addr); + if (!strcmp(CMD_ARGV[0], "all")) { + retval = watchpoint_remove_all(target); - return ERROR_OK; + if (retval != ERROR_OK) { + command_print(CMD, "Error encountered during removal of all watchpoints."); + command_print(CMD, "Some watchpoints may have remained set."); + } + } else { + target_addr_t addr; + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); + + retval = watchpoint_remove(target, addr); + + if (retval != ERROR_OK) + command_print(CMD, "Error during removal of watchpoint at address " TARGET_ADDR_FMT, addr); + } + + return retval; } /** @@ -4222,7 +4217,7 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen uint32_t start_address, uint32_t end_address, struct target *target, uint32_t duration_ms) { uint32_t i; - FILE *f = fopen(filename, "w"); + FILE *f = fopen(filename, "wb"); if (!f) return; write_string(f, "gmon"); @@ -4252,11 +4247,19 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen /* max should be (largest sample + 1) * Refer to binutils/gprof/hist.c (find_histogram_for_pc) */ - max++; + if (max < UINT32_MAX) + max++; + + /* gprof requires (max - min) >= 2 */ + while ((max - min) < 2) { + if (max < UINT32_MAX) + max++; + else + min--; + } } - int address_space = max - min; - assert(address_space >= 2); + uint32_t address_space = max - min; /* FIXME: What is the reasonable number of buckets? * The profiling result will be more accurate if there are enough buckets. */ @@ -4324,7 +4327,7 @@ COMMAND_HANDLER(handle_profile_command) if ((CMD_ARGC != 2) && (CMD_ARGC != 4)) return ERROR_COMMAND_SYNTAX_ERROR; - const uint32_t MAX_PROFILE_SAMPLE_NUM = 10000; + const uint32_t MAX_PROFILE_SAMPLE_NUM = 1000000; uint32_t offset; uint32_t num_of_samples; int retval = ERROR_OK; @@ -4332,6 +4335,19 @@ COMMAND_HANDLER(handle_profile_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], offset); + uint32_t start_address = 0; + uint32_t end_address = 0; + bool with_range = false; + if (CMD_ARGC == 4) { + with_range = true; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address); + if (start_address > end_address || (end_address - start_address) < 2) { + command_print(CMD, "Error: end - start < 2"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + } + uint32_t *samples = malloc(sizeof(uint32_t) * MAX_PROFILE_SAMPLE_NUM); if (!samples) { LOG_ERROR("No memory to store samples."); @@ -4371,7 +4387,7 @@ COMMAND_HANDLER(handle_profile_command) } else if (target->state == TARGET_HALTED && !halted_before_profiling) { /* The target was running before we started and is halted now. Resume * it, for consistency. */ - retval = target_resume(target, 1, 0, 0, 0); + retval = target_resume(target, true, 0, false, false); if (retval != ERROR_OK) { free(samples); return retval; @@ -4384,15 +4400,6 @@ COMMAND_HANDLER(handle_profile_command) return retval; } - uint32_t start_address = 0; - uint32_t end_address = 0; - bool with_range = false; - if (CMD_ARGC == 4) { - with_range = true; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address); - } - write_gmon(samples, num_of_samples, CMD_ARGV[1], with_range, start_address, end_address, target, duration_ms); command_print(CMD, "Wrote %s", CMD_ARGV[1]); @@ -4401,243 +4408,36 @@ COMMAND_HANDLER(handle_profile_command) return retval; } -static int new_u64_array_element(Jim_Interp *interp, const char *varname, int idx, uint64_t val) -{ - char *namebuf; - Jim_Obj *obj_name, *obj_val; - int result; - - namebuf = alloc_printf("%s(%d)", varname, idx); - if (!namebuf) - return JIM_ERR; - - obj_name = Jim_NewStringObj(interp, namebuf, -1); - jim_wide wide_val = val; - obj_val = Jim_NewWideObj(interp, wide_val); - if (!obj_name || !obj_val) { - free(namebuf); - return JIM_ERR; - } - - Jim_IncrRefCount(obj_name); - Jim_IncrRefCount(obj_val); - result = Jim_SetVariable(interp, obj_name, obj_val); - Jim_DecrRefCount(interp, obj_name); - Jim_DecrRefCount(interp, obj_val); - free(namebuf); - /* printf("%s(%d) <= 0%08x\n", varname, idx, val); */ - return result; -} - -static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) -{ - int e; - - LOG_WARNING("DEPRECATED! use 'read_memory' not 'mem2array'"); - - /* argv[0] = name of array to receive the data - * argv[1] = desired element width in bits - * argv[2] = memory address - * argv[3] = count of times to read - * argv[4] = optional "phys" - */ - if (argc < 4 || argc > 5) { - Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]"); - return JIM_ERR; - } - - /* Arg 0: Name of the array variable */ - const char *varname = Jim_GetString(argv[0], NULL); - - /* Arg 1: Bit width of one element */ - long l; - e = Jim_GetLong(interp, argv[1], &l); - if (e != JIM_OK) - return e; - const unsigned int width_bits = l; - - if (width_bits != 8 && - width_bits != 16 && - width_bits != 32 && - width_bits != 64) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL); - return JIM_ERR; - } - const unsigned int width = width_bits / 8; - - /* Arg 2: Memory address */ - jim_wide wide_addr; - e = Jim_GetWide(interp, argv[2], &wide_addr); - if (e != JIM_OK) - return e; - target_addr_t addr = (target_addr_t)wide_addr; - - /* Arg 3: Number of elements to read */ - e = Jim_GetLong(interp, argv[3], &l); - if (e != JIM_OK) - return e; - size_t len = l; - - /* Arg 4: phys */ - bool is_phys = false; - if (argc > 4) { - int str_len = 0; - const char *phys = Jim_GetString(argv[4], &str_len); - if (!strncmp(phys, "phys", str_len)) - is_phys = true; - else - return JIM_ERR; - } - - /* Argument checks */ - if (len == 0) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: zero width read?", NULL); - return JIM_ERR; - } - if ((addr + (len * width)) < addr) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: addr + len - wraps to zero?", NULL); - return JIM_ERR; - } - if (len > 65536) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "mem2array: too large read request, exceeds 64K items", NULL); - return JIM_ERR; - } - - if ((width == 1) || - ((width == 2) && ((addr & 1) == 0)) || - ((width == 4) && ((addr & 3) == 0)) || - ((width == 8) && ((addr & 7) == 0))) { - /* alignment correct */ - } else { - char buf[100]; - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - sprintf(buf, "mem2array address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads", - addr, - width); - Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL); - return JIM_ERR; - } - - /* Transfer loop */ - - /* index counter */ - size_t idx = 0; - - const size_t buffersize = 4096; - uint8_t *buffer = malloc(buffersize); - if (!buffer) - return JIM_ERR; - - /* assume ok */ - e = JIM_OK; - while (len) { - /* Slurp... in buffer size chunks */ - const unsigned int max_chunk_len = buffersize / width; - const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */ - - int retval; - if (is_phys) - retval = target_read_phys_memory(target, addr, width, chunk_len, buffer); - else - retval = target_read_memory(target, addr, width, chunk_len, buffer); - if (retval != ERROR_OK) { - /* BOO !*/ - LOG_ERROR("mem2array: Read @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed", - addr, - width, - chunk_len); - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: cannot read memory", NULL); - e = JIM_ERR; - break; - } else { - for (size_t i = 0; i < chunk_len ; i++, idx++) { - uint64_t v = 0; - switch (width) { - case 8: - v = target_buffer_get_u64(target, &buffer[i*width]); - break; - case 4: - v = target_buffer_get_u32(target, &buffer[i*width]); - break; - case 2: - v = target_buffer_get_u16(target, &buffer[i*width]); - break; - case 1: - v = buffer[i] & 0x0ff; - break; - } - new_u64_array_element(interp, varname, idx, v); - } - len -= chunk_len; - addr += chunk_len * width; - } - } - - free(buffer); - - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - - return e; -} - -static int target_jim_read_memory(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handle_target_read_memory) { /* - * argv[1] = memory address - * argv[2] = desired element width in bits - * argv[3] = number of elements to read - * argv[4] = optional "phys" + * CMD_ARGV[0] = memory address + * CMD_ARGV[1] = desired element width in bits + * CMD_ARGV[2] = number of elements to read + * CMD_ARGV[3] = optional "phys" */ - if (argc < 4 || argc > 5) { - Jim_WrongNumArgs(interp, 1, argv, "address width count ['phys']"); - return JIM_ERR; - } + if (CMD_ARGC < 3 || CMD_ARGC > 4) + return ERROR_COMMAND_SYNTAX_ERROR; /* Arg 1: Memory address. */ - jim_wide wide_addr; - int e; - e = Jim_GetWide(interp, argv[1], &wide_addr); - - if (e != JIM_OK) - return e; - - target_addr_t addr = (target_addr_t)wide_addr; + target_addr_t addr; + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], addr); /* Arg 2: Bit width of one element. */ - long l; - e = Jim_GetLong(interp, argv[2], &l); - - if (e != JIM_OK) - return e; - - const unsigned int width_bits = l; + unsigned int width_bits; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], width_bits); /* Arg 3: Number of elements to read. */ - e = Jim_GetLong(interp, argv[3], &l); - - if (e != JIM_OK) - return e; - - size_t count = l; + unsigned int count; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], count); /* Arg 4: Optional 'phys'. */ bool is_phys = false; - - if (argc > 4) { - const char *phys = Jim_GetString(argv[4], NULL); - - if (strcmp(phys, "phys")) { - Jim_SetResultFormatted(interp, "invalid argument '%s', must be 'phys'", phys); - return JIM_ERR; + if (CMD_ARGC == 4) { + if (strcmp(CMD_ARGV[3], "phys")) { + command_print(CMD, "invalid argument '%s', must be 'phys'", CMD_ARGV[3]); + return ERROR_COMMAND_ARGUMENT_INVALID; } is_phys = true; @@ -4650,37 +4450,35 @@ static int target_jim_read_memory(Jim_Interp *interp, int argc, case 64: break; default: - Jim_SetResultString(interp, "invalid width, must be 8, 16, 32 or 64", -1); - return JIM_ERR; + command_print(CMD, "invalid width, must be 8, 16, 32 or 64"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - const unsigned int width = width_bits / 8; - - if ((addr + (count * width)) < addr) { - Jim_SetResultString(interp, "read_memory: addr + count wraps to zero", -1); - return JIM_ERR; + if (count > 65536) { + command_print(CMD, "too large read request, exceeds 64K elements"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - if (count > 65536) { - Jim_SetResultString(interp, "read_memory: too large read request, exeeds 64K elements", -1); - return JIM_ERR; + const unsigned int width = width_bits / 8; + /* -1 is needed to handle cases when (addr + count * width) results in zero + * due to overflow. + */ + if ((addr + count * width - 1) < addr) { + command_print(CMD, "memory region wraps over address zero"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx != NULL); - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); const size_t buffersize = 4096; uint8_t *buffer = malloc(buffersize); if (!buffer) { LOG_ERROR("Failed to allocate memory"); - return JIM_ERR; + return ERROR_FAIL; } - Jim_Obj *result_list = Jim_NewListObj(interp, NULL, 0); - Jim_IncrRefCount(result_list); - + char *separator = ""; while (count > 0) { const unsigned int max_chunk_len = buffersize / width; const size_t chunk_len = MIN(count, max_chunk_len); @@ -4693,11 +4491,15 @@ static int target_jim_read_memory(Jim_Interp *interp, int argc, retval = target_read_memory(target, addr, width, chunk_len, buffer); if (retval != ERROR_OK) { - LOG_ERROR("read_memory: read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed", + LOG_DEBUG("read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed", addr, width_bits, chunk_len); - Jim_SetResultString(interp, "read_memory: failed to read memory", -1); - e = JIM_ERR; - break; + /* + * FIXME: we append the errmsg to the list of value already read. + * Add a way to flush and replace old output, but LOG_DEBUG() it + */ + command_print(CMD, "failed to read memory"); + free(buffer); + return retval; } for (size_t i = 0; i < chunk_len ; i++) { @@ -4718,11 +4520,8 @@ static int target_jim_read_memory(Jim_Interp *interp, int argc, break; } - char value_buf[11]; - snprintf(value_buf, sizeof(value_buf), "0x%" PRIx64, v); - - Jim_ListAppendElement(interp, result_list, - Jim_NewStringObj(interp, value_buf, -1)); + command_print_sameline(CMD, "%s0x%" PRIx64, separator, v); + separator = " "; } count -= chunk_len; @@ -4731,260 +4530,43 @@ static int target_jim_read_memory(Jim_Interp *interp, int argc, free(buffer); - if (e != JIM_OK) { - Jim_DecrRefCount(interp, result_list); - return e; - } - - Jim_SetResult(interp, result_list); - Jim_DecrRefCount(interp, result_list); - - return JIM_OK; + return ERROR_OK; } -static int get_u64_array_element(Jim_Interp *interp, const char *varname, size_t idx, uint64_t *val) +COMMAND_HANDLER(handle_target_write_memory) { - char *namebuf = alloc_printf("%s(%zu)", varname, idx); - if (!namebuf) - return JIM_ERR; - - Jim_Obj *obj_name = Jim_NewStringObj(interp, namebuf, -1); - if (!obj_name) { - free(namebuf); - return JIM_ERR; - } + /* + * CMD_ARGV[0] = memory address + * CMD_ARGV[1] = desired element width in bits + * CMD_ARGV[2] = list of data to write + * CMD_ARGV[3] = optional "phys" + */ - Jim_IncrRefCount(obj_name); - Jim_Obj *obj_val = Jim_GetVariable(interp, obj_name, JIM_ERRMSG); - Jim_DecrRefCount(interp, obj_name); - free(namebuf); - if (!obj_val) - return JIM_ERR; + if (CMD_ARGC < 3 || CMD_ARGC > 4) + return ERROR_COMMAND_SYNTAX_ERROR; - jim_wide wide_val; - int result = Jim_GetWide(interp, obj_val, &wide_val); - *val = wide_val; - return result; -} + /* Arg 1: Memory address. */ + target_addr_t addr; + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], addr); -static int target_array2mem(Jim_Interp *interp, struct target *target, - int argc, Jim_Obj *const *argv) -{ - int e; + /* Arg 2: Bit width of one element. */ + unsigned int width_bits; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], width_bits); - LOG_WARNING("DEPRECATED! use 'write_memory' not 'array2mem'"); + /* Arg 3: Elements to write. */ + size_t count = Jim_ListLength(CMD_CTX->interp, CMD_JIMTCL_ARGV[2]); - /* argv[0] = name of array from which to read the data - * argv[1] = desired element width in bits - * argv[2] = memory address - * argv[3] = number of elements to write - * argv[4] = optional "phys" - */ - if (argc < 4 || argc > 5) { - Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]"); - return JIM_ERR; - } - - /* Arg 0: Name of the array variable */ - const char *varname = Jim_GetString(argv[0], NULL); - - /* Arg 1: Bit width of one element */ - long l; - e = Jim_GetLong(interp, argv[1], &l); - if (e != JIM_OK) - return e; - const unsigned int width_bits = l; - - if (width_bits != 8 && - width_bits != 16 && - width_bits != 32 && - width_bits != 64) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL); - return JIM_ERR; - } - const unsigned int width = width_bits / 8; + /* Arg 4: Optional 'phys'. */ + bool is_phys = false; - /* Arg 2: Memory address */ - jim_wide wide_addr; - e = Jim_GetWide(interp, argv[2], &wide_addr); - if (e != JIM_OK) - return e; - target_addr_t addr = (target_addr_t)wide_addr; + if (CMD_ARGC == 4) { + if (strcmp(CMD_ARGV[3], "phys")) { + command_print(CMD, "invalid argument '%s', must be 'phys'", CMD_ARGV[3]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } - /* Arg 3: Number of elements to write */ - e = Jim_GetLong(interp, argv[3], &l); - if (e != JIM_OK) - return e; - size_t len = l; - - /* Arg 4: Phys */ - bool is_phys = false; - if (argc > 4) { - int str_len = 0; - const char *phys = Jim_GetString(argv[4], &str_len); - if (!strncmp(phys, "phys", str_len)) - is_phys = true; - else - return JIM_ERR; - } - - /* Argument checks */ - if (len == 0) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "array2mem: zero width read?", NULL); - return JIM_ERR; - } - - if ((addr + (len * width)) < addr) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "array2mem: addr + len - wraps to zero?", NULL); - return JIM_ERR; - } - - if (len > 65536) { - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "array2mem: too large memory write request, exceeds 64K items", NULL); - return JIM_ERR; - } - - if ((width == 1) || - ((width == 2) && ((addr & 1) == 0)) || - ((width == 4) && ((addr & 3) == 0)) || - ((width == 8) && ((addr & 7) == 0))) { - /* alignment correct */ - } else { - char buf[100]; - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - sprintf(buf, "array2mem address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads", - addr, - width); - Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL); - return JIM_ERR; - } - - /* Transfer loop */ - - /* assume ok */ - e = JIM_OK; - - const size_t buffersize = 4096; - uint8_t *buffer = malloc(buffersize); - if (!buffer) - return JIM_ERR; - - /* index counter */ - size_t idx = 0; - - while (len) { - /* Slurp... in buffer size chunks */ - const unsigned int max_chunk_len = buffersize / width; - - const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */ - - /* Fill the buffer */ - for (size_t i = 0; i < chunk_len; i++, idx++) { - uint64_t v = 0; - if (get_u64_array_element(interp, varname, idx, &v) != JIM_OK) { - free(buffer); - return JIM_ERR; - } - switch (width) { - case 8: - target_buffer_set_u64(target, &buffer[i * width], v); - break; - case 4: - target_buffer_set_u32(target, &buffer[i * width], v); - break; - case 2: - target_buffer_set_u16(target, &buffer[i * width], v); - break; - case 1: - buffer[i] = v & 0x0ff; - break; - } - } - len -= chunk_len; - - /* Write the buffer to memory */ - int retval; - if (is_phys) - retval = target_write_phys_memory(target, addr, width, chunk_len, buffer); - else - retval = target_write_memory(target, addr, width, chunk_len, buffer); - if (retval != ERROR_OK) { - /* BOO !*/ - LOG_ERROR("array2mem: Write @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed", - addr, - width, - chunk_len); - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: cannot read memory", NULL); - e = JIM_ERR; - break; - } - addr += chunk_len * width; - } - - free(buffer); - - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - - return e; -} - -static int target_jim_write_memory(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) -{ - /* - * argv[1] = memory address - * argv[2] = desired element width in bits - * argv[3] = list of data to write - * argv[4] = optional "phys" - */ - - if (argc < 4 || argc > 5) { - Jim_WrongNumArgs(interp, 1, argv, "address width data ['phys']"); - return JIM_ERR; - } - - /* Arg 1: Memory address. */ - int e; - jim_wide wide_addr; - e = Jim_GetWide(interp, argv[1], &wide_addr); - - if (e != JIM_OK) - return e; - - target_addr_t addr = (target_addr_t)wide_addr; - - /* Arg 2: Bit width of one element. */ - long l; - e = Jim_GetLong(interp, argv[2], &l); - - if (e != JIM_OK) - return e; - - const unsigned int width_bits = l; - size_t count = Jim_ListLength(interp, argv[3]); - - /* Arg 4: Optional 'phys'. */ - bool is_phys = false; - - if (argc > 4) { - const char *phys = Jim_GetString(argv[4], NULL); - - if (strcmp(phys, "phys")) { - Jim_SetResultFormatted(interp, "invalid argument '%s', must be 'phys'", phys); - return JIM_ERR; - } - - is_phys = true; - } + is_phys = true; + } switch (width_bits) { case 8: @@ -4993,32 +4575,32 @@ static int target_jim_write_memory(Jim_Interp *interp, int argc, case 64: break; default: - Jim_SetResultString(interp, "invalid width, must be 8, 16, 32 or 64", -1); - return JIM_ERR; + command_print(CMD, "invalid width, must be 8, 16, 32 or 64"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - const unsigned int width = width_bits / 8; - - if ((addr + (count * width)) < addr) { - Jim_SetResultString(interp, "write_memory: addr + len wraps to zero", -1); - return JIM_ERR; + if (count > 65536) { + command_print(CMD, "too large memory write request, exceeds 64K elements"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - if (count > 65536) { - Jim_SetResultString(interp, "write_memory: too large memory write request, exceeds 64K elements", -1); - return JIM_ERR; + const unsigned int width = width_bits / 8; + /* -1 is needed to handle cases when (addr + count * width) results in zero + * due to overflow. + */ + if ((addr + count * width - 1) < addr) { + command_print(CMD, "memory region wraps over address zero"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx != NULL); - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); const size_t buffersize = 4096; uint8_t *buffer = malloc(buffersize); if (!buffer) { LOG_ERROR("Failed to allocate memory"); - return JIM_ERR; + return ERROR_FAIL; } size_t j = 0; @@ -5028,9 +4610,14 @@ static int target_jim_write_memory(Jim_Interp *interp, int argc, const size_t chunk_len = MIN(count, max_chunk_len); for (size_t i = 0; i < chunk_len; i++, j++) { - Jim_Obj *tmp = Jim_ListGetIndex(interp, argv[3], j); + Jim_Obj *tmp = Jim_ListGetIndex(CMD_CTX->interp, CMD_JIMTCL_ARGV[2], j); jim_wide element_wide; - Jim_GetWide(interp, tmp, &element_wide); + int jimretval = Jim_GetWide(CMD_CTX->interp, tmp, &element_wide); + if (jimretval != JIM_OK) { + command_print(CMD, "invalid value \"%s\"", Jim_GetString(tmp, NULL)); + free(buffer); + return ERROR_COMMAND_ARGUMENT_INVALID; + } const uint64_t v = element_wide; @@ -5060,11 +4647,11 @@ static int target_jim_write_memory(Jim_Interp *interp, int argc, retval = target_write_memory(target, addr, width, chunk_len, buffer); if (retval != ERROR_OK) { - LOG_ERROR("write_memory: write at " TARGET_ADDR_FMT " with width=%u and count=%zu failed", + LOG_DEBUG("write at " TARGET_ADDR_FMT " with width=%u and count=%zu failed", addr, width_bits, chunk_len); - Jim_SetResultString(interp, "write_memory: failed to write memory", -1); - e = JIM_ERR; - break; + command_print(CMD, "failed to write memory"); + free(buffer); + return retval; } addr += chunk_len * width; @@ -5072,7 +4659,7 @@ static int target_jim_write_memory(Jim_Interp *interp, int argc, free(buffer); - return e; + return ERROR_OK; } /* FIX? should we propagate errors here rather than printing them @@ -5083,10 +4670,9 @@ void target_handle_event(struct target *target, enum target_event e) struct target_event_action *teap; int retval; - for (teap = target->event_action; teap; teap = teap->next) { + list_for_each_entry(teap, &target->events_action, list) { if (teap->event == e) { - LOG_DEBUG("target(%d): %s (%s) event: %d (%s) action: %s", - target->target_number, + LOG_DEBUG("target: %s (%s) event: %d (%s) action: %s", target_name(target), target_type_name(target), e, @@ -5113,9 +4699,8 @@ void target_handle_event(struct target *target, enum target_event e) if (retval != JIM_OK) { Jim_MakeErrorMessage(teap->interp); - LOG_USER("Error executing event %s on target %s:\n%s", + LOG_TARGET_ERROR(target, "Execution of event %s failed:\n%s", target_event_name(e), - target_name(target), Jim_GetString(Jim_GetResult(teap->interp), NULL)); /* clean both error code and stacktrace before return */ Jim_Eval(teap->interp, "error \"\" \"\""); @@ -5124,63 +4709,46 @@ void target_handle_event(struct target *target, enum target_event e) } } -static int target_jim_get_reg(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handle_target_get_reg) { - bool force = false; + if (CMD_ARGC < 1 || CMD_ARGC > 2) + return ERROR_COMMAND_SYNTAX_ERROR; - if (argc == 3) { - const char *option = Jim_GetString(argv[1], NULL); + bool force = false; + Jim_Obj *next_argv = CMD_JIMTCL_ARGV[0]; - if (!strcmp(option, "-force")) { - argc--; - argv++; - force = true; - } else { - Jim_SetResultFormatted(interp, "invalid option '%s'", option); - return JIM_ERR; + if (CMD_ARGC == 2) { + if (strcmp(CMD_ARGV[0], "-force")) { + command_print(CMD, "invalid argument '%s', must be '-force'", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - } - if (argc != 2) { - Jim_WrongNumArgs(interp, 1, argv, "[-force] list"); - return JIM_ERR; + force = true; + next_argv = CMD_JIMTCL_ARGV[1]; } - const int length = Jim_ListLength(interp, argv[1]); - - Jim_Obj *result_dict = Jim_NewDictObj(interp, NULL, 0); - - if (!result_dict) - return JIM_ERR; + const int length = Jim_ListLength(CMD_CTX->interp, next_argv); - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx != NULL); - const struct target *target = get_current_target(cmd_ctx); + const struct target *target = get_current_target(CMD_CTX); for (int i = 0; i < length; i++) { - Jim_Obj *elem = Jim_ListGetIndex(interp, argv[1], i); - - if (!elem) - return JIM_ERR; + Jim_Obj *elem = Jim_ListGetIndex(CMD_CTX->interp, next_argv, i); const char *reg_name = Jim_String(elem); - struct reg *reg = register_get_by_name(target->reg_cache, reg_name, - false); + struct reg *reg = register_get_by_name(target->reg_cache, reg_name, false); if (!reg || !reg->exist) { - Jim_SetResultFormatted(interp, "unknown register '%s'", reg_name); - return JIM_ERR; + command_print(CMD, "unknown register '%s'", reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; } - if (force) { + if (force || !reg->valid) { int retval = reg->type->get(reg); if (retval != ERROR_OK) { - Jim_SetResultFormatted(interp, "failed to read register '%s'", - reg_name); - return JIM_ERR; + command_print(CMD, "failed to read register '%s'", reg_name); + return retval; } } @@ -5188,96 +4756,84 @@ static int target_jim_get_reg(Jim_Interp *interp, int argc, if (!reg_value) { LOG_ERROR("Failed to allocate memory"); - return JIM_ERR; + return ERROR_FAIL; } - char *tmp = alloc_printf("0x%s", reg_value); + command_print(CMD, "%s 0x%s", reg_name, reg_value); free(reg_value); - - if (!tmp) { - LOG_ERROR("Failed to allocate memory"); - return JIM_ERR; - } - - Jim_DictAddElement(interp, result_dict, elem, - Jim_NewStringObj(interp, tmp, -1)); - - free(tmp); } - Jim_SetResult(interp, result_dict); - - return JIM_OK; + return ERROR_OK; } -static int target_jim_set_reg(Jim_Interp *interp, int argc, - Jim_Obj * const *argv) +COMMAND_HANDLER(handle_set_reg_command) { - if (argc != 2) { - Jim_WrongNumArgs(interp, 1, argv, "dict"); - return JIM_ERR; - } + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; int tmp; #if JIM_VERSION >= 80 - Jim_Obj **dict = Jim_DictPairs(interp, argv[1], &tmp); + Jim_Obj **dict = Jim_DictPairs(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], &tmp); if (!dict) - return JIM_ERR; + return ERROR_FAIL; #else Jim_Obj **dict; - int ret = Jim_DictPairs(interp, argv[1], &dict, &tmp); + int ret = Jim_DictPairs(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], &dict, &tmp); if (ret != JIM_OK) - return ret; + return ERROR_FAIL; #endif const unsigned int length = tmp; - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - const struct target *target = get_current_target(cmd_ctx); + + const struct target *target = get_current_target(CMD_CTX); + assert(target); for (unsigned int i = 0; i < length; i += 2) { const char *reg_name = Jim_String(dict[i]); const char *reg_value = Jim_String(dict[i + 1]); - struct reg *reg = register_get_by_name(target->reg_cache, reg_name, - false); + struct reg *reg = register_get_by_name(target->reg_cache, reg_name, false); if (!reg || !reg->exist) { - Jim_SetResultFormatted(interp, "unknown register '%s'", reg_name); - return JIM_ERR; + command_print(CMD, "unknown register '%s'", reg_name); + return ERROR_FAIL; } uint8_t *buf = malloc(DIV_ROUND_UP(reg->size, 8)); - if (!buf) { LOG_ERROR("Failed to allocate memory"); - return JIM_ERR; + return ERROR_FAIL; + } + + int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf, reg_value, buf, reg->size); + if (retval != ERROR_OK) { + free(buf); + return retval; } - str_to_buf(reg_value, strlen(reg_value), buf, reg->size, 0); - int retval = reg->type->set(reg, buf); + retval = reg->type->set(reg, buf); free(buf); if (retval != ERROR_OK) { - Jim_SetResultFormatted(interp, "failed to set '%s' to register '%s'", + command_print(CMD, "failed to set '%s' to register '%s'", reg_value, reg_name); - return JIM_ERR; + return retval; } } - return JIM_OK; + return ERROR_OK; } /** * Returns true only if the target has a handler for the specified event. */ -bool target_has_event_action(struct target *target, enum target_event event) +bool target_has_event_action(const struct target *target, enum target_event event) { struct target_event_action *teap; - for (teap = target->event_action; teap; teap = teap->next) { + list_for_each_entry(teap, &target->events_action, list) { if (teap->event == event) return true; } @@ -5301,7 +4857,7 @@ enum target_cfg_param { TCFG_GDB_MAX_CONNECTIONS, }; -static struct jim_nvp nvp_config_opts[] = { +static struct nvp nvp_config_opts[] = { { .name = "-type", .value = TCFG_TYPE }, { .name = "-event", .value = TCFG_EVENT }, { .name = "-work-area-virt", .value = TCFG_WORK_AREA_VIRT }, @@ -5319,98 +4875,107 @@ static struct jim_nvp nvp_config_opts[] = { { .name = NULL, .value = -1 } }; -static int target_configure(struct jim_getopt_info *goi, struct target *target) +static COMMAND_HELPER(target_configure, struct target *target, unsigned int index, bool is_configure) { - struct jim_nvp *n; - Jim_Obj *o; - jim_wide w; - int e; + const struct nvp *n; + int retval; /* parse config or cget options ... */ - while (goi->argc > 0) { - Jim_SetEmptyResult(goi->interp); - /* jim_getopt_debug(goi); */ - + while (index < CMD_ARGC) { if (target->type->target_jim_configure) { /* target defines a configure function */ /* target gets first dibs on parameters */ - e = (*(target->type->target_jim_configure))(target, goi); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, CMD_CTX->interp, CMD_ARGC - index, CMD_JIMTCL_ARGV + index); + goi.is_configure = is_configure; + int e = (*target->type->target_jim_configure)(target, &goi); + index = CMD_ARGC - goi.argc; + + int reslen; + const char *result = Jim_GetString(Jim_GetResult(CMD_CTX->interp), &reslen); + if (reslen > 0) + command_print(CMD, "%s", result); + if (e == JIM_OK) { /* more? */ continue; } if (e == JIM_ERR) { /* An error */ - return e; + return ERROR_FAIL; } /* otherwise we 'continue' below */ } - e = jim_getopt_nvp(goi, nvp_config_opts, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, nvp_config_opts, 0); - return e; + n = nvp_name2value(nvp_config_opts, CMD_ARGV[index]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_config_opts, NULL, CMD_ARGV[index]); + return ERROR_COMMAND_ARGUMENT_INVALID; } + index++; switch (n->value) { case TCFG_TYPE: /* not settable */ - if (goi->isconfigure) { - Jim_SetResultFormatted(goi->interp, - "not settable: %s", n->name); - return JIM_ERR; - } else { -no_params: - if (goi->argc != 0) { - Jim_WrongNumArgs(goi->interp, - goi->argc, goi->argv, - "NO PARAMS"); - return JIM_ERR; - } + if (is_configure) { + command_print(CMD, "not settable: %s", n->name); + return ERROR_COMMAND_ARGUMENT_INVALID; } - Jim_SetResultString(goi->interp, - target_type_name(target), -1); + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "%s", target_type_name(target)); /* loop for more */ break; + case TCFG_EVENT: - if (goi->argc == 0) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event ?event-name? ..."); - return JIM_ERR; + if (index == CMD_ARGC) { + command_print(CMD, "expecting %s event-name event-body", + CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - e = jim_getopt_nvp(goi, nvp_target_event, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, nvp_target_event, 1); - return e; + n = nvp_name2value(nvp_target_event, CMD_ARGV[index]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_target_event, CMD_ARGV[index - 1], CMD_ARGV[index]); + return ERROR_COMMAND_ARGUMENT_INVALID; } + index++; - if (goi->isconfigure) { - if (goi->argc != 1) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event ?event-name? ?EVENT-BODY?"); - return JIM_ERR; - } - } else { - if (goi->argc != 0) { - Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event ?event-name?"); - return JIM_ERR; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "expecting %s %s event-body", + CMD_ARGV[index - 2], CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } } { struct target_event_action *teap; - teap = target->event_action; /* replace existing? */ - while (teap) { + list_for_each_entry(teap, &target->events_action, list) if (teap->event == (enum target_event)n->value) break; - teap = teap->next; - } - if (goi->isconfigure) { + /* not found! */ + if (&teap->list == &target->events_action) + teap = NULL; + + if (is_configure) { /* START_DEPRECATED_TPIU */ if (n->value == TARGET_EVENT_TRACE_CONFIG) LOG_INFO("DEPRECATED target event %s; use TPIU events {pre,post}-{enable,disable}", n->name); /* END_DEPRECATED_TPIU */ + if (strlen(CMD_ARGV[index]) == 0) { + /* empty action, drop existing one */ + if (teap) { + list_del(&teap->list); + Jim_DecrRefCount(teap->interp, teap->body); + free(teap); + } + index++; + break; + } + bool replace = true; if (!teap) { /* create new */ @@ -5418,11 +4983,12 @@ static int target_configure(struct jim_getopt_info *goi, struct target *target) replace = false; } teap->event = n->value; - teap->interp = goi->interp; - jim_getopt_obj(goi, &o); + teap->interp = CMD_CTX->interp; if (teap->body) Jim_DecrRefCount(teap->interp, teap->body); - teap->body = Jim_DuplicateObj(goi->interp, o); + /* use jim object to keep its reference on tcl file and line */ + /* TODO: need duplicate? isn't IncrRefCount enough? */ + teap->body = Jim_DuplicateObj(teap->interp, CMD_JIMTCL_ARGV[index++]); /* * FIXME: * Tcl/TK - "tk events" have a nice feature. @@ -5437,476 +5003,447 @@ static int target_configure(struct jim_getopt_info *goi, struct target *target) if (!replace) { /* add to head of event list */ - teap->next = target->event_action; - target->event_action = teap; + list_add(&teap->list, &target->events_action); } - Jim_SetEmptyResult(goi->interp); } else { - /* get */ - if (!teap) - Jim_SetEmptyResult(goi->interp); - else - Jim_SetResult(goi->interp, Jim_DuplicateObj(goi->interp, teap->body)); + /* cget */ + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (teap) + command_print(CMD, "%s", Jim_GetString(teap->body, NULL)); } } /* loop for more */ break; case TCFG_WORK_AREA_VIRT: - if (goi->isconfigure) { - target_free_all_working_areas(target); - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->working_area_virt = w; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[index], target->working_area_virt); + index++; target->working_area_virt_spec = true; + target_free_all_working_areas(target); } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, TARGET_ADDR_FMT, target->working_area_virt); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_virt)); /* loop for more */ break; case TCFG_WORK_AREA_PHYS: - if (goi->isconfigure) { - target_free_all_working_areas(target); - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->working_area_phys = w; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[index], target->working_area_phys); + index++; target->working_area_phys_spec = true; + target_free_all_working_areas(target); } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, TARGET_ADDR_FMT, target->working_area_phys); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_phys)); /* loop for more */ break; case TCFG_WORK_AREA_SIZE: - if (goi->isconfigure) { + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index], target->working_area_size); + index++; target_free_all_working_areas(target); - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->working_area_size = w; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "0x%08" PRIx32, target->working_area_size); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_size)); /* loop for more */ break; case TCFG_WORK_AREA_BACKUP: - if (goi->isconfigure) { + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + retval = command_parse_bool_arg(CMD_ARGV[index], &target->backup_working_area); + if (retval != ERROR_OK) + return retval; + index++; target_free_all_working_areas(target); - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - /* make this exactly 1 or 0 */ - target->backup_working_area = (!!w); } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, target->backup_working_area ? "1" : "0"); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->backup_working_area)); - /* loop for more e*/ + /* loop for more */ break; - case TCFG_ENDIAN: - if (goi->isconfigure) { - e = jim_getopt_nvp(goi, nvp_target_endian, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(goi, nvp_target_endian, 1); - return e; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } + n = nvp_name2value(nvp_target_endian, CMD_ARGV[index]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_target_endian, CMD_ARGV[index - 1], CMD_ARGV[index]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + index++; target->endianness = n->value; } else { - if (goi->argc != 0) - goto no_params; - } - n = jim_nvp_value2name_simple(nvp_target_endian, target->endianness); - if (!n->name) { - target->endianness = TARGET_LITTLE_ENDIAN; - n = jim_nvp_value2name_simple(nvp_target_endian, target->endianness); + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + n = nvp_value2name(nvp_target_endian, target->endianness); + if (!n->name) { + target->endianness = TARGET_LITTLE_ENDIAN; + n = nvp_value2name(nvp_target_endian, target->endianness); + } + command_print(CMD, "%s", n->name); } - Jim_SetResultString(goi->interp, n->name, -1); /* loop for more */ break; case TCFG_COREID: - if (goi->isconfigure) { - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->coreid = (int32_t)w; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + COMMAND_PARSE_NUMBER(s32, CMD_ARGV[index], target->coreid); + index++; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "%" PRIi32, target->coreid); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->coreid)); /* loop for more */ break; case TCFG_CHAIN_POSITION: - if (goi->isconfigure) { - Jim_Obj *o_t; - struct jtag_tap *tap; - + if (is_configure) { if (target->has_dap) { - Jim_SetResultString(goi->interp, - "target requires -dap parameter instead of -chain-position!", -1); - return JIM_ERR; + command_print(CMD, "target requires -dap parameter instead of -chain-position!"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - target_free_all_working_areas(target); - e = jim_getopt_obj(goi, &o_t); - if (e != JIM_OK) - return e; - tap = jtag_tap_by_jim_obj(goi->interp, o_t); - if (!tap) - return JIM_ERR; + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + struct jtag_tap *tap = jtag_tap_by_string(CMD_ARGV[index]); + if (!tap) { + command_print(CMD, "Tap '%s' could not be found", CMD_ARGV[index]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + index++; target->tap = tap; target->tap_configured = true; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "%s", target->tap->dotted_name); } - Jim_SetResultString(goi->interp, target->tap->dotted_name, -1); - /* loop for more e*/ + /* loop for more */ break; + case TCFG_DBGBASE: - if (goi->isconfigure) { - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->dbgbase = (uint32_t)w; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index], target->dbgbase); + index++; target->dbgbase_set = true; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "0x%08" PRIx32, target->dbgbase); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->dbgbase)); /* loop for more */ break; + case TCFG_RTOS: - /* RTOS */ - { - int result = rtos_create(goi, target); - if (result != JIM_OK) - return result; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + retval = rtos_create(CMD, target, CMD_ARGV[index]); + if (retval != ERROR_OK) + return retval; + index++; + } else { + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + if (target->rtos) + command_print(CMD, "%s", target->rtos->type->name); } /* loop for more */ break; case TCFG_DEFER_EXAMINE: - /* DEFER_EXAMINE */ - target->defer_examine = true; + if (is_configure) + target->defer_examine = true; + else + command_print(CMD, "%s", target->defer_examine ? "true" : "false"); /* loop for more */ break; case TCFG_GDB_PORT: - if (goi->isconfigure) { - struct command_context *cmd_ctx = current_command_context(goi->interp); - if (cmd_ctx->mode != COMMAND_CONFIG) { - Jim_SetResultString(goi->interp, "-gdb-port must be configured before 'init'", -1); - return JIM_ERR; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - const char *s; - e = jim_getopt_string(goi, &s, NULL); - if (e != JIM_OK) - return e; + /* TODO: generalize test of COMMAND_CONFIG */ + if (CMD_CTX->mode != COMMAND_CONFIG) { + command_print(CMD, "-gdb-port must be configured before 'init'"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + char *s = strdup(CMD_ARGV[index]); + if (!s) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } free(target->gdb_port_override); - target->gdb_port_override = strdup(s); + target->gdb_port_override = s; + index++; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "%s", target->gdb_port_override ? target->gdb_port_override : "undefined"); } - Jim_SetResultString(goi->interp, target->gdb_port_override ? target->gdb_port_override : "undefined", -1); /* loop for more */ break; case TCFG_GDB_MAX_CONNECTIONS: - if (goi->isconfigure) { - struct command_context *cmd_ctx = current_command_context(goi->interp); - if (cmd_ctx->mode != COMMAND_CONFIG) { - Jim_SetResultString(goi->interp, "-gdb-max-connections must be configured before 'init'", -1); - return JIM_ERR; + if (is_configure) { + if (index == CMD_ARGC) { + command_print(CMD, "missing argument to %s", CMD_ARGV[index - 1]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - e = jim_getopt_wide(goi, &w); - if (e != JIM_OK) - return e; - target->gdb_max_connections = (w < 0) ? CONNECTION_LIMIT_UNLIMITED : (int)w; + if (CMD_CTX->mode != COMMAND_CONFIG) { + command_print(CMD, "-gdb-max-connections must be configured before 'init'"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + COMMAND_PARSE_NUMBER(int, CMD_ARGV[index], target->gdb_max_connections); + index++; + if (target->gdb_max_connections < 0) + target->gdb_max_connections = CONNECTION_LIMIT_UNLIMITED; } else { - if (goi->argc != 0) - goto no_params; + if (index != CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "%d", target->gdb_max_connections); } - Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->gdb_max_connections)); + /* loop for more */ break; } - } /* while (goi->argc) */ - + } - /* done - we return */ - return JIM_OK; + return ERROR_OK; } -static int jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_target_configure) { - struct command *c = jim_to_command(interp); - struct jim_getopt_info goi; - - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - goi.isconfigure = !strcmp(c->name, "configure"); - if (goi.argc < 1) { - Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, - "missing: -option ..."); - return JIM_ERR; - } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - return target_configure(&goi, target); -} + if (!CMD_ARGC) + return ERROR_COMMAND_SYNTAX_ERROR; -static int jim_target_mem2array(Jim_Interp *interp, - int argc, Jim_Obj *const *argv) -{ - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - return target_mem2array(interp, target, argc - 1, argv + 1); -} + bool is_configure = !strcmp(CMD_NAME, "configure"); -static int jim_target_array2mem(Jim_Interp *interp, - int argc, Jim_Obj *const *argv) -{ - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - return target_array2mem(interp, target, argc - 1, argv + 1); -} + struct target *target = get_current_target(CMD_CTX); -static int jim_target_tap_disabled(Jim_Interp *interp) -{ - Jim_SetResultFormatted(interp, "[TAP is disabled]"); - return JIM_ERR; + return CALL_COMMAND_HANDLER(target_configure, target, 0, is_configure); } -static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_examine) { bool allow_defer = false; - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc > 1) { - const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_SetResultFormatted(goi.interp, - "usage: %s ['allow-defer']", cmd_name); - return JIM_ERR; - } - if (goi.argc > 0 && - strcmp(Jim_GetString(argv[1], NULL), "allow-defer") == 0) { - /* consume it */ - Jim_Obj *obj; - int e = jim_getopt_obj(&goi, &obj); - if (e != JIM_OK) - return e; + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 1) { + if (strcmp(CMD_ARGV[0], "allow-defer")) + return ERROR_COMMAND_ARGUMENT_INVALID; allow_defer = true; } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - if (!target->tap->enabled) - return jim_target_tap_disabled(interp); + struct target *target = get_current_target(CMD_CTX); + if (!target->tap->enabled) { + command_print(CMD, "[TAP is disabled]"); + return ERROR_FAIL; + } if (allow_defer && target->defer_examine) { LOG_INFO("Deferring arp_examine of %s", target_name(target)); LOG_INFO("Use arp_examine command to examine it manually!"); - return JIM_OK; + return ERROR_OK; } - int e = target->type->examine(target); - if (e != ERROR_OK) { + int retval = target->type->examine(target); + if (retval != ERROR_OK) { target_reset_examined(target); - return JIM_ERR; + return retval; } target_set_examined(target); - return JIM_OK; + return ERROR_OK; } -static int jim_target_was_examined(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_target_was_examined) { - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + command_print(CMD, "%d", target_was_examined(target) ? 1 : 0); - Jim_SetResultBool(interp, target_was_examined(target)); - return JIM_OK; + return ERROR_OK; } -static int jim_target_examine_deferred(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_target_examine_deferred) { - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + command_print(CMD, "%d", target->defer_examine ? 1 : 0); - Jim_SetResultBool(interp, target->defer_examine); - return JIM_OK; + return ERROR_OK; } -static int jim_target_halt_gdb(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_halt_gdb) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); - return JIM_ERR; - } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - if (target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT) != ERROR_OK) - return JIM_ERR; + struct target *target = get_current_target(CMD_CTX); - return JIM_OK; + return target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); } -static int jim_target_poll(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_poll) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); - return JIM_ERR; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + if (!target->tap->enabled) { + command_print(CMD, "[TAP is disabled]"); + return ERROR_FAIL; } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - if (!target->tap->enabled) - return jim_target_tap_disabled(interp); - int e; if (!(target_was_examined(target))) - e = ERROR_TARGET_NOT_EXAMINED; - else - e = target->type->poll(target); - if (e != ERROR_OK) - return JIM_ERR; - return JIM_OK; + return ERROR_TARGET_NOT_EXAMINED; + + return target->type->poll(target); } -static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_reset) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; - if (goi.argc != 2) { - Jim_WrongNumArgs(interp, 0, argv, - "([tT]|[fF]|assert|deassert) BOOL"); - return JIM_ERR; + const struct nvp *n = nvp_name2value(nvp_assert, CMD_ARGV[0]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_assert, NULL, CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - struct jim_nvp *n; - int e = jim_getopt_nvp(&goi, nvp_assert, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, nvp_assert, 1); - return e; - } /* the halt or not param */ - jim_wide a; - e = jim_getopt_wide(&goi, &a); - if (e != JIM_OK) - return e; + int a; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], a); - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - if (!target->tap->enabled) - return jim_target_tap_disabled(interp); + struct target *target = get_current_target(CMD_CTX); + if (!target->tap->enabled) { + command_print(CMD, "[TAP is disabled]"); + return ERROR_FAIL; + } if (!target->type->assert_reset || !target->type->deassert_reset) { - Jim_SetResultFormatted(interp, - "No target-specific reset for %s", - target_name(target)); - return JIM_ERR; + command_print(CMD, "No target-specific reset for %s", target_name(target)); + return ERROR_FAIL; } - if (target->defer_examine) - target_reset_examined(target); - /* determine if we should halt or not. */ target->reset_halt = (a != 0); /* When this happens - all workareas are invalid. */ target_free_all_working_areas_restore(target, 0); /* do the assert */ - if (n->value == NVP_ASSERT) - e = target->type->assert_reset(target); - else - e = target->type->deassert_reset(target); - return (e == ERROR_OK) ? JIM_OK : JIM_ERR; -} - -static int jim_target_halt(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); - return JIM_ERR; - } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - if (!target->tap->enabled) - return jim_target_tap_disabled(interp); - int e = target->type->halt(target); - return (e == ERROR_OK) ? JIM_OK : JIM_ERR; -} - -static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - - /* params: <name> statename timeoutmsecs */ - if (goi.argc != 2) { - const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_SetResultFormatted(goi.interp, - "%s <state_name> <timeout_in_msec>", cmd_name); - return JIM_ERR; - } - - struct jim_nvp *n; - int e = jim_getopt_nvp(&goi, nvp_target_state, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, nvp_target_state, 1); - return e; - } - jim_wide a; - e = jim_getopt_wide(&goi, &a); - if (e != JIM_OK) - return e; - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - if (!target->tap->enabled) - return jim_target_tap_disabled(interp); - - e = target_wait_state(target, n->value, a); - if (e != ERROR_OK) { - Jim_Obj *obj = Jim_NewIntObj(interp, e); - Jim_SetResultFormatted(goi.interp, - "target: %s wait %s fails (%#s) %s", + if (n->value == NVP_ASSERT) { + int retval = target->type->assert_reset(target); + if (target->defer_examine) + target_reset_examined(target); + return retval; + } + + return target->type->deassert_reset(target); +} + +COMMAND_HANDLER(handle_target_halt) +{ + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + if (!target->tap->enabled) { + command_print(CMD, "[TAP is disabled]"); + return ERROR_FAIL; + } + + return target->type->halt(target); +} + +COMMAND_HANDLER(handle_target_wait_state) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + const struct nvp *n = nvp_name2value(nvp_target_state, CMD_ARGV[0]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_target_state, NULL, CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + unsigned int a; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], a); + + struct target *target = get_current_target(CMD_CTX); + if (!target->tap->enabled) { + command_print(CMD, "[TAP is disabled]"); + return ERROR_FAIL; + } + + int retval = target_wait_state(target, n->value, a); + if (retval != ERROR_OK) { + command_print(CMD, + "target: %s wait %s fails (%d) %s", target_name(target), n->name, - obj, target_strerror_safe(e)); - return JIM_ERR; + retval, target_strerror_safe(retval)); + return retval; } - return JIM_OK; + return ERROR_OK; } /* List for human, Events defined for this target. * scripts/programs should use 'name cget -event NAME' @@ -5914,69 +5451,85 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a COMMAND_HANDLER(handle_target_event_list) { struct target *target = get_current_target(CMD_CTX); - struct target_event_action *teap = target->event_action; + struct target_event_action *teap; - command_print(CMD, "Event actions for target (%d) %s\n", - target->target_number, + command_print(CMD, "Event actions for target %s\n", target_name(target)); command_print(CMD, "%-25s | Body", "Event"); command_print(CMD, "------------------------- | " "----------------------------------------"); - while (teap) { + + list_for_each_entry(teap, &target->events_action, list) command_print(CMD, "%-25s | %s", target_event_name(teap->event), Jim_GetString(teap->body, NULL)); - teap = teap->next; - } + command_print(CMD, "***END***"); return ERROR_OK; } -static int jim_target_current_state(Jim_Interp *interp, int argc, Jim_Obj *const *argv) + +COMMAND_HANDLER(handle_target_current_state) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); - return JIM_ERR; - } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); - Jim_SetResultString(interp, target_state_name(target), -1); - return JIM_OK; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + command_print(CMD, "%s", target_state_name(target)); + + return ERROR_OK; } -static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const *argv) + +COMMAND_HANDLER(handle_target_debug_reason) { - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc != 1) { - const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_SetResultFormatted(goi.interp, "%s <eventname>", cmd_name); - return JIM_ERR; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + + const char *debug_reason = nvp_value2name(nvp_target_debug_reason, + target->debug_reason)->name; + + if (!debug_reason) { + command_print(CMD, "bug: invalid debug reason (%d)", + target->debug_reason); + return ERROR_FAIL; } - struct jim_nvp *n; - int e = jim_getopt_nvp(&goi, nvp_target_event, &n); - if (e != JIM_OK) { - jim_getopt_nvp_unknown(&goi, nvp_target_event, 1); - return e; + + command_print(CMD, "%s", debug_reason); + + return ERROR_OK; +} + +COMMAND_HANDLER(handle_target_invoke_event) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + const struct nvp *n = nvp_name2value(nvp_target_event, CMD_ARGV[0]); + if (!n->name) { + nvp_unknown_command_print(CMD, nvp_target_event, NULL, CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); - struct target *target = get_current_target(cmd_ctx); + + struct target *target = get_current_target(CMD_CTX); target_handle_event(target, n->value); - return JIM_OK; + return ERROR_OK; } static const struct command_registration target_instance_command_handlers[] = { { .name = "configure", .mode = COMMAND_ANY, - .jim_handler = jim_target_configure, + .handler = handle_target_configure, .help = "configure a new target for use", .usage = "[target_attribute ...]", }, { .name = "cget", .mode = COMMAND_ANY, - .jim_handler = jim_target_configure, + .handler = handle_target_configure, .help = "returns the specified target attribute", .usage = "target_attribute", }, @@ -6036,47 +5589,31 @@ static const struct command_registration target_instance_command_handlers[] = { .help = "Display target memory as 8-bit bytes", .usage = "address [count]", }, - { - .name = "array2mem", - .mode = COMMAND_EXEC, - .jim_handler = jim_target_array2mem, - .help = "Writes Tcl array of 8/16/32 bit numbers " - "to target memory", - .usage = "arrayname bitwidth address count", - }, - { - .name = "mem2array", - .mode = COMMAND_EXEC, - .jim_handler = jim_target_mem2array, - .help = "Loads Tcl array of 8/16/32 bit numbers " - "from target memory", - .usage = "arrayname bitwidth address count", - }, { .name = "get_reg", .mode = COMMAND_EXEC, - .jim_handler = target_jim_get_reg, + .handler = handle_target_get_reg, .help = "Get register values from the target", - .usage = "list", + .usage = "[-force] list", }, { .name = "set_reg", .mode = COMMAND_EXEC, - .jim_handler = target_jim_set_reg, + .handler = handle_set_reg_command, .help = "Set target register values", .usage = "dict", }, { .name = "read_memory", .mode = COMMAND_EXEC, - .jim_handler = target_jim_read_memory, + .handler = handle_target_read_memory, .help = "Read Tcl list of 8/16/32/64 bit numbers from target memory", .usage = "address width count ['phys']", }, { .name = "write_memory", .mode = COMMAND_EXEC, - .jim_handler = target_jim_write_memory, + .handler = handle_target_write_memory, .help = "Write Tcl list of 8/16/32/64 bit numbers to target memory", .usage = "address width data ['phys']", }, @@ -6090,153 +5627,151 @@ static const struct command_registration target_instance_command_handlers[] = { { .name = "curstate", .mode = COMMAND_EXEC, - .jim_handler = jim_target_current_state, + .handler = handle_target_current_state, .help = "displays the current state of this target", + .usage = "", + }, + { + .name = "debug_reason", + .mode = COMMAND_EXEC, + .handler = handle_target_debug_reason, + .help = "displays the debug reason of this target", + .usage = "", }, { .name = "arp_examine", .mode = COMMAND_EXEC, - .jim_handler = jim_target_examine, + .handler = handle_target_examine, .help = "used internally for reset processing", .usage = "['allow-defer']", }, { .name = "was_examined", .mode = COMMAND_EXEC, - .jim_handler = jim_target_was_examined, + .handler = handle_target_was_examined, .help = "used internally for reset processing", + .usage = "", }, { .name = "examine_deferred", .mode = COMMAND_EXEC, - .jim_handler = jim_target_examine_deferred, + .handler = handle_target_examine_deferred, .help = "used internally for reset processing", + .usage = "", }, { .name = "arp_halt_gdb", .mode = COMMAND_EXEC, - .jim_handler = jim_target_halt_gdb, + .handler = handle_target_halt_gdb, .help = "used internally for reset processing to halt GDB", + .usage = "", }, { .name = "arp_poll", .mode = COMMAND_EXEC, - .jim_handler = jim_target_poll, + .handler = handle_target_poll, .help = "used internally for reset processing", + .usage = "", }, { .name = "arp_reset", .mode = COMMAND_EXEC, - .jim_handler = jim_target_reset, + .handler = handle_target_reset, .help = "used internally for reset processing", + .usage = "'assert'|'deassert' halt", }, { .name = "arp_halt", .mode = COMMAND_EXEC, - .jim_handler = jim_target_halt, + .handler = handle_target_halt, .help = "used internally for reset processing", + .usage = "", }, { .name = "arp_waitstate", .mode = COMMAND_EXEC, - .jim_handler = jim_target_wait_state, + .handler = handle_target_wait_state, .help = "used internally for reset processing", + .usage = "statename timeoutmsecs", }, { .name = "invoke-event", .mode = COMMAND_EXEC, - .jim_handler = jim_target_invoke_event, + .handler = handle_target_invoke_event, .help = "invoke handler for specified event", .usage = "event_name", }, COMMAND_REGISTRATION_DONE }; -static int target_create(struct jim_getopt_info *goi) +COMMAND_HANDLER(handle_target_create) { - Jim_Obj *new_cmd; - Jim_Cmd *cmd; - const char *cp; - int e; - int x; - struct target *target; - struct command_context *cmd_ctx; - - cmd_ctx = current_command_context(goi->interp); - assert(cmd_ctx); + int retval = ERROR_OK; - if (goi->argc < 3) { - Jim_WrongNumArgs(goi->interp, 1, goi->argv, "?name? ?type? ..options..."); - return JIM_ERR; - } + if (CMD_ARGC < 2) + return ERROR_COMMAND_SYNTAX_ERROR; - /* COMMAND */ - jim_getopt_obj(goi, &new_cmd); - /* does this command exist? */ - cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE); - if (cmd) { - cp = Jim_GetString(new_cmd, NULL); - Jim_SetResultFormatted(goi->interp, "Command/target: %s Exists", cp); - return JIM_ERR; + /* check if the target name clashes with an existing command name */ + Jim_Cmd *jimcmd = Jim_GetCommand(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], JIM_NONE); + if (jimcmd) { + command_print(CMD, "Command/target: %s Exists", CMD_ARGV[0]); + return ERROR_FAIL; } /* TYPE */ - e = jim_getopt_string(goi, &cp, NULL); - if (e != JIM_OK) - return e; + const char *cp = CMD_ARGV[1]; struct transport *tr = get_current_transport(); - if (tr->override_target) { - e = tr->override_target(&cp); - if (e != ERROR_OK) { - LOG_ERROR("The selected transport doesn't support this target"); - return JIM_ERR; + if (tr && tr->override_target) { + retval = tr->override_target(&cp); + if (retval != ERROR_OK) { + command_print(CMD, "The selected transport doesn't support this target"); + return retval; } LOG_INFO("The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD"); } /* now does target type exist */ - for (x = 0 ; target_types[x] ; x++) { + size_t x; + for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) { if (strcmp(cp, target_types[x]->name) == 0) { /* found */ break; } } - if (!target_types[x]) { - Jim_SetResultFormatted(goi->interp, "Unknown target type %s, try one of ", cp); - for (x = 0 ; target_types[x] ; x++) { - if (target_types[x + 1]) { - Jim_AppendStrings(goi->interp, - Jim_GetResult(goi->interp), - target_types[x]->name, - ", ", NULL); - } else { - Jim_AppendStrings(goi->interp, - Jim_GetResult(goi->interp), - " or ", - target_types[x]->name, NULL); + if (x == ARRAY_SIZE(target_types)) { + char *all = NULL; + for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) { + char *prev = all; + if (all) + all = alloc_printf("%s, %s", all, target_types[x]->name); + else + all = alloc_printf("%s", target_types[x]->name); + free(prev); + if (!all) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } } - return JIM_ERR; + command_print(CMD, "Unknown target type %s, try one of %s", cp, all); + free(all); + return ERROR_FAIL; } /* Create it */ - target = calloc(1, sizeof(struct target)); + struct target *target = calloc(1, sizeof(struct target)); if (!target) { LOG_ERROR("Out of memory"); - return JIM_ERR; + return ERROR_FAIL; } /* set empty smp cluster */ target->smp_targets = &empty_smp_targets; - /* set target number */ - target->target_number = new_target_number(); - /* allocate memory for each unique target type */ target->type = malloc(sizeof(struct target_type)); if (!target->type) { LOG_ERROR("Out of memory"); free(target); - return JIM_ERR; + return ERROR_FAIL; } memcpy(target->type, target_types[x], sizeof(struct target_type)); @@ -6247,7 +5782,7 @@ static int target_create(struct jim_getopt_info *goi) target->working_area = 0x0; target->working_area_size = 0x0; target->working_areas = NULL; - target->backup_working_area = 0; + target->backup_working_area = false; target->state = TARGET_UNKNOWN; target->debug_reason = DBG_REASON_UNDEFINED; @@ -6261,17 +5796,19 @@ static int target_create(struct jim_getopt_info *goi) target->halt_issued = false; + INIT_LIST_HEAD(&target->events_action); + /* initialize trace information */ target->trace_info = calloc(1, sizeof(struct trace)); if (!target->trace_info) { LOG_ERROR("Out of memory"); free(target->type); free(target); - return JIM_ERR; + return ERROR_FAIL; } target->dbgmsg = NULL; - target->dbg_msg_enabled = 0; + target->dbg_msg_enabled = false; target->endianness = TARGET_ENDIAN_UNKNOWN; @@ -6281,34 +5818,43 @@ static int target_create(struct jim_getopt_info *goi) target->gdb_port_override = NULL; target->gdb_max_connections = 1; - /* Do the rest as "configure" options */ - goi->isconfigure = 1; - e = target_configure(goi, target); + target->cmd_name = strdup(CMD_ARGV[0]); + if (!target->cmd_name) { + LOG_ERROR("Out of memory"); + free(target->trace_info); + free(target->type); + free(target); + return ERROR_FAIL; + } - if (e == JIM_OK) { + /* Do the rest as "configure" options */ + bool is_configure = true; + retval = CALL_COMMAND_HANDLER(target_configure, target, 2, is_configure); + if (retval == ERROR_OK) { if (target->has_dap) { if (!target->dap_configured) { - Jim_SetResultString(goi->interp, "-dap ?name? required when creating target", -1); - e = JIM_ERR; + command_print(CMD, "-dap ?name? required when creating target"); + retval = ERROR_COMMAND_ARGUMENT_INVALID; } } else { if (!target->tap_configured) { - Jim_SetResultString(goi->interp, "-chain-position ?name? required when creating target", -1); - e = JIM_ERR; + command_print(CMD, "-chain-position ?name? required when creating target"); + retval = ERROR_COMMAND_ARGUMENT_INVALID; } } /* tap must be set after target was configured */ if (!target->tap) - e = JIM_ERR; + retval = ERROR_COMMAND_ARGUMENT_INVALID; } - if (e != JIM_OK) { + if (retval != ERROR_OK) { rtos_destroy(target); free(target->gdb_port_override); free(target->trace_info); free(target->type); + free(target->private_config); free(target); - return e; + return retval; } if (target->endianness == TARGET_ENDIAN_UNKNOWN) { @@ -6316,37 +5862,26 @@ static int target_create(struct jim_getopt_info *goi) target->endianness = TARGET_LITTLE_ENDIAN; } - cp = Jim_GetString(new_cmd, NULL); - target->cmd_name = strdup(cp); - if (!target->cmd_name) { - LOG_ERROR("Out of memory"); - rtos_destroy(target); - free(target->gdb_port_override); - free(target->trace_info); - free(target->type); - free(target); - return JIM_ERR; - } - if (target->type->target_create) { - e = (*(target->type->target_create))(target, goi->interp); - if (e != ERROR_OK) { + retval = (*target->type->target_create)(target); + if (retval != ERROR_OK) { LOG_DEBUG("target_create failed"); free(target->cmd_name); rtos_destroy(target); free(target->gdb_port_override); free(target->trace_info); free(target->type); + free(target->private_config); free(target); - return JIM_ERR; + return retval; } } /* create the target specific commands */ if (target->type->commands) { - e = register_commands(cmd_ctx, NULL, target->type->commands); - if (e != ERROR_OK) - LOG_ERROR("unable to register '%s' commands", cp); + retval = register_commands(CMD_CTX, NULL, target->type->commands); + if (retval != ERROR_OK) + LOG_ERROR("unable to register '%s' commands", CMD_ARGV[0]); } /* now - create the new target name command */ @@ -6361,7 +5896,7 @@ static int target_create(struct jim_getopt_info *goi) }; const struct command_registration target_commands[] = { { - .name = cp, + .name = CMD_ARGV[0], .mode = COMMAND_ANY, .help = "target command group", .usage = "", @@ -6369,8 +5904,8 @@ static int target_create(struct jim_getopt_info *goi) }, COMMAND_REGISTRATION_DONE }; - e = register_commands_override_target(cmd_ctx, NULL, target_commands, target); - if (e != ERROR_OK) { + retval = register_commands_override_target(CMD_CTX, NULL, target_commands, target); + if (retval != ERROR_OK) { if (target->type->deinit_target) target->type->deinit_target(target); free(target->cmd_name); @@ -6379,122 +5914,134 @@ static int target_create(struct jim_getopt_info *goi) free(target->trace_info); free(target->type); free(target); - return JIM_ERR; + return retval; } /* append to end of list */ append_to_list_all_targets(target); - cmd_ctx->current_target = target; - return JIM_OK; + CMD_CTX->current_target = target; + return ERROR_OK; } -static int jim_target_current(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_current) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - struct command_context *cmd_ctx = current_command_context(interp); - assert(cmd_ctx); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; - struct target *target = get_current_target_or_null(cmd_ctx); + struct target *target = get_current_target_or_null(CMD_CTX); if (target) - Jim_SetResultString(interp, target_name(target), -1); - return JIM_OK; + command_print(CMD, "%s", target_name(target)); + + return ERROR_OK; } -static int jim_target_types(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_types) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); - for (unsigned x = 0; target_types[x]; x++) { - Jim_ListAppendElement(interp, Jim_GetResult(interp), - Jim_NewStringObj(interp, target_types[x]->name, -1)); - } - return JIM_OK; + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (size_t x = 0; x < ARRAY_SIZE(target_types); x++) + command_print(CMD, "%s", target_types[x]->name); + + return ERROR_OK; } -static int jim_target_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +COMMAND_HANDLER(handle_target_names) { - if (argc != 1) { - Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); - return JIM_ERR; - } - Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + struct target *target = all_targets; while (target) { - Jim_ListAppendElement(interp, Jim_GetResult(interp), - Jim_NewStringObj(interp, target_name(target), -1)); + command_print(CMD, "%s", target_name(target)); target = target->next; } - return JIM_OK; + + return ERROR_OK; } -static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +static struct target_list * +__attribute__((warn_unused_result)) +create_target_list_node(const char *targetname) +{ + struct target *target = get_target(targetname); + LOG_DEBUG("%s ", targetname); + if (!target) + return NULL; + + struct target_list *new = malloc(sizeof(struct target_list)); + if (!new) { + LOG_ERROR("Out of memory"); + return new; + } + + new->target = target; + return new; +} + +static int get_target_with_common_rtos_type(struct command_invocation *cmd, + struct list_head *lh, struct target **result) { - int i; - const char *targetname; - int retval, len; - static int smp_group = 1; struct target *target = NULL; - struct target_list *head, *new; + struct target_list *curr; + foreach_smp_target(curr, lh) { + struct rtos *curr_rtos = curr->target->rtos; + if (curr_rtos) { + if (target && target->rtos && target->rtos->type != curr_rtos->type) { + command_print(cmd, "Different rtos types in members of one smp target!"); + return ERROR_FAIL; + } + target = curr->target; + } + } + *result = target; + return ERROR_OK; +} + +COMMAND_HANDLER(handle_target_smp) +{ + static unsigned int smp_group = 1; - retval = 0; - LOG_DEBUG("%d", argc); - /* argv[1] = target to associate in smp - * argv[2] = target to associate in smp - * argv[3] ... + if (CMD_ARGC == 0) { + LOG_DEBUG("Empty SMP target"); + return ERROR_OK; + } + LOG_DEBUG("%d", CMD_ARGC); + /* CMD_ARGC[0] = target to associate in smp + * CMD_ARGC[1] = target to associate in smp + * CMD_ARGC[2] ... */ struct list_head *lh = malloc(sizeof(*lh)); if (!lh) { LOG_ERROR("Out of memory"); - return JIM_ERR; + return ERROR_FAIL; } INIT_LIST_HEAD(lh); - for (i = 1; i < argc; i++) { - - targetname = Jim_GetString(argv[i], &len); - target = get_target(targetname); - LOG_DEBUG("%s ", targetname); - if (target) { - new = malloc(sizeof(struct target_list)); - new->target = target; + for (unsigned int i = 0; i < CMD_ARGC; i++) { + struct target_list *new = create_target_list_node(CMD_ARGV[i]); + if (new) list_add_tail(&new->lh, lh); - } } /* now parse the list of cpu and put the target in smp mode*/ - foreach_smp_target(head, lh) { - target = head->target; + struct target_list *curr; + foreach_smp_target(curr, lh) { + struct target *target = curr->target; target->smp = smp_group; target->smp_targets = lh; } smp_group++; - if (target && target->rtos) - retval = rtos_smp_init(target); + struct target *rtos_target; + int retval = get_target_with_common_rtos_type(CMD, lh, &rtos_target); + if (retval == ERROR_OK && rtos_target) + retval = rtos_smp_init(rtos_target); return retval; } - -static int jim_target_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) -{ - struct jim_getopt_info goi; - jim_getopt_setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 3) { - Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, - "<name> <target_type> [<target_options> ...]"); - return JIM_ERR; - } - return target_create(&goi); -} - static const struct command_registration target_subcommand_handlers[] = { { .name = "init", @@ -6506,33 +6053,36 @@ static const struct command_registration target_subcommand_handlers[] = { { .name = "create", .mode = COMMAND_CONFIG, - .jim_handler = jim_target_create, - .usage = "name type '-chain-position' name [options ...]", + .handler = handle_target_create, + .usage = "name type [options ...]", .help = "Creates and selects a new target", }, { .name = "current", .mode = COMMAND_ANY, - .jim_handler = jim_target_current, + .handler = handle_target_current, .help = "Returns the currently selected target", + .usage = "", }, { .name = "types", .mode = COMMAND_ANY, - .jim_handler = jim_target_types, + .handler = handle_target_types, .help = "Returns the available target types as " "a list of strings", + .usage = "", }, { .name = "names", .mode = COMMAND_ANY, - .jim_handler = jim_target_names, + .handler = handle_target_names, .help = "Returns the names of all targets as a list of strings", + .usage = "", }, { .name = "smp", .mode = COMMAND_ANY, - .jim_handler = jim_target_smp, + .handler = handle_target_smp, .usage = "targetname1 targetname2 ...", .help = "gather several target in a smp list" }, @@ -6734,8 +6284,8 @@ COMMAND_HANDLER(handle_ps_command) struct target *target = get_current_target(CMD_CTX); char *display; if (target->state != TARGET_HALTED) { - LOG_INFO("target not halted !!"); - return ERROR_OK; + command_print(CMD, "Error: [%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; } if ((target->rtos) && (target->rtos->type) @@ -6766,8 +6316,8 @@ COMMAND_HANDLER(handle_test_mem_access_command) int retval = ERROR_OK; if (target->state != TARGET_HALTED) { - LOG_INFO("target not halted !!"); - return ERROR_FAIL; + command_print(CMD, "Error: [%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; } if (CMD_ARGC != 1) @@ -6947,8 +6497,8 @@ static const struct command_registration target_exec_command_handlers[] = { .mode = COMMAND_ANY, .help = "Load image into server memory for later use by " "fast_load; primarily for profiling", - .usage = "filename address ['bin'|'ihex'|'elf'|'s19'] " - "[min_address [max_length]]", + .usage = "filename [address ['bin'|'ihex'|'elf'|'s19' " + "[min_address [max_length]]]]", }, { .name = "fast_load", @@ -7108,21 +6658,21 @@ static const struct command_registration target_exec_command_handlers[] = { .handler = handle_wp_command, .mode = COMMAND_EXEC, .help = "list (no params) or create watchpoints", - .usage = "[address length [('r'|'w'|'a') value [mask]]]", + .usage = "[address length [('r'|'w'|'a') [value [mask]]]]", }, { .name = "rwp", .handler = handle_rwp_command, .mode = COMMAND_EXEC, .help = "remove watchpoint", - .usage = "address", + .usage = "'all' | address", }, { .name = "load_image", .handler = handle_load_image_command, .mode = COMMAND_EXEC, - .usage = "filename address ['bin'|'ihex'|'elf'|'s19'] " - "[min_address] [max_length]", + .usage = "filename [address ['bin'|'ihex'|'elf'|'s19' " + "[min_address [max_length]]]]", }, { .name = "dump_image", @@ -7151,31 +6701,38 @@ static const struct command_registration target_exec_command_handlers[] = { { .name = "get_reg", .mode = COMMAND_EXEC, - .jim_handler = target_jim_get_reg, + .handler = handle_target_get_reg, .help = "Get register values from the target", - .usage = "list", + .usage = "[-force] list", }, { .name = "set_reg", .mode = COMMAND_EXEC, - .jim_handler = target_jim_set_reg, + .handler = handle_set_reg_command, .help = "Set target register values", .usage = "dict", }, { .name = "read_memory", .mode = COMMAND_EXEC, - .jim_handler = target_jim_read_memory, + .handler = handle_target_read_memory, .help = "Read Tcl list of 8/16/32/64 bit numbers from target memory", .usage = "address width count ['phys']", }, { .name = "write_memory", .mode = COMMAND_EXEC, - .jim_handler = target_jim_write_memory, + .handler = handle_target_write_memory, .help = "Write Tcl list of 8/16/32/64 bit numbers to target memory", .usage = "address width data ['phys']", }, + { + .name = "debug_reason", + .mode = COMMAND_EXEC, + .handler = handle_target_debug_reason, + .help = "displays the debug reason of this target", + .usage = "", + }, { .name = "reset_nag", .handler = handle_target_reset_nag, @@ -7215,3 +6772,29 @@ static int target_register_user_commands(struct command_context *cmd_ctx) return register_commands(cmd_ctx, NULL, target_exec_command_handlers); } + +const char *target_debug_reason_str(enum target_debug_reason reason) +{ + switch (reason) { + case DBG_REASON_DBGRQ: + return "DBGRQ"; + case DBG_REASON_BREAKPOINT: + return "BREAKPOINT"; + case DBG_REASON_WATCHPOINT: + return "WATCHPOINT"; + case DBG_REASON_WPTANDBKPT: + return "WPTANDBKPT"; + case DBG_REASON_SINGLESTEP: + return "SINGLESTEP"; + case DBG_REASON_NOTHALTED: + return "NOTHALTED"; + case DBG_REASON_EXIT: + return "EXIT"; + case DBG_REASON_EXC_CATCH: + return "EXC_CATCH"; + case DBG_REASON_UNDEFINED: + return "UNDEFINED"; + default: + return "UNKNOWN!"; + } +} diff --git a/src/target/target.h b/src/target/target.h index e221351a83..b850b49cf3 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -23,6 +23,7 @@ #include <helper/list.h> #include "helper/replacements.h" #include "helper/system.h" +#include <helper/types.h> #include <jim.h> struct reg; @@ -45,6 +46,8 @@ struct gdb_fileio_info; * not sure how this is used with all the recent changes) * TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on * behalf of the debugger (e.g. algorithm for flashing) + * TARGET_UNAVAILABLE = 5: The target is unavailable for some reason. It might + * be powered down, for instance. * * also see: target_state_name(); */ @@ -55,11 +58,7 @@ enum target_state { TARGET_HALTED = 2, TARGET_RESET = 3, TARGET_DEBUG_RUNNING = 4, -}; - -enum nvp_assert { - NVP_DEASSERT, - NVP_ASSERT, + TARGET_UNAVAILABLE = 5 }; enum target_reset_mode { @@ -120,7 +119,6 @@ enum target_register_class { struct target { struct target_type *type; /* target type definition (name, access functions) */ char *cmd_name; /* tcl Name of target */ - int target_number; /* DO NOT USE! field to be removed in 2010 */ struct jtag_tap *tap; /* where on the jtag chain is this */ int32_t coreid; /* which device on the TAP? */ @@ -144,7 +142,7 @@ struct target { */ bool running_alg; - struct target_event_action *event_action; + struct list_head events_action; bool reset_halt; /* attempt resetting the CPU into the halted mode? */ target_addr_t working_area; /* working area (initialised RAM). Evaluated @@ -154,7 +152,7 @@ struct target { bool working_area_phys_spec; /* physical address specified? */ target_addr_t working_area_phys; /* physical address */ uint32_t working_area_size; /* size in bytes */ - uint32_t backup_working_area; /* whether the content of the working area has to be preserved */ + bool backup_working_area; /* whether the content of the working area has to be preserved */ struct working_area *working_areas;/* list of allocated working areas */ enum target_debug_reason debug_reason;/* reason why the target entered debug state */ enum target_endianness endianness; /* target endianness */ @@ -165,7 +163,7 @@ struct target { struct watchpoint *watchpoints; /* list of watchpoints */ struct trace *trace_info; /* generic trace information */ struct debug_msg_receiver *dbgmsg; /* list of debug message receivers */ - uint32_t dbg_msg_enabled; /* debug message status */ + bool dbg_msg_enabled; /* debug message status */ void *arch_info; /* architecture specific information */ void *private_config; /* pointer to target specific config data (for jim_configure hook) */ struct target *next; /* next target in list */ @@ -189,10 +187,14 @@ struct target { bool rtos_auto_detect; /* A flag that indicates that the RTOS has been specified as "auto" * and must be detected when symbols are offered */ struct backoff_timer backoff; - int smp; /* Unique non-zero number for each SMP group */ + unsigned int smp; /* Unique non-zero number for each SMP group */ struct list_head *smp_targets; /* list all targets in this smp group/cluster * The head of the list is shared between the * cluster, thus here there is a pointer */ + bool smp_halt_event_postponed; /* Some SMP implementations (currently Cortex-M) stores + * 'halted' events and emits them after all targets of + * the SMP group has been polled */ + /* the gdb service is there in case of smp, we have only one gdb server * for all smp target * the target attached to the gdb is changing dynamically by changing @@ -224,19 +226,19 @@ struct gdb_fileio_info { }; /** Returns a description of the endianness for the specified target. */ -static inline const char *target_endianness(struct target *target) +static inline const char *target_endianness(const struct target *target) { return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" : (target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian"; } /** Returns the instance-specific name of the specified target. */ -static inline const char *target_name(struct target *target) +static inline const char *target_name(const struct target *target) { return target->cmd_name; } -const char *debug_reason_name(struct target *t); +const char *debug_reason_name(const struct target *t); enum target_event { @@ -286,24 +288,17 @@ enum target_event { TARGET_EVENT_TRACE_CONFIG, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x100 = 0x100, /* semihosting allows user cmds from 0x100 to 0x1ff */ - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x101 = 0x101, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x102 = 0x102, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x103 = 0x103, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x104 = 0x104, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x105 = 0x105, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x106 = 0x106, - TARGET_EVENT_SEMIHOSTING_USER_CMD_0x107 = 0x107, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X100 = 0x100, /* semihosting allows user cmds from 0x100 to 0x1ff */ + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X101 = 0x101, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X102 = 0x102, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X103 = 0x103, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X104 = 0x104, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X105 = 0x105, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X106 = 0x106, + TARGET_EVENT_SEMIHOSTING_USER_CMD_0X107 = 0x107, }; -struct target_event_action { - enum target_event event; - Jim_Interp *interp; - Jim_Obj *body; - struct target_event_action *next; -}; - -bool target_has_event_action(struct target *target, enum target_event event); +bool target_has_event_action(const struct target *target, enum target_event event); struct target_event_callback { int (*callback)(struct target *target, enum target_event event, void *priv); @@ -387,8 +382,8 @@ int target_unregister_trace_callback( * yet it is possible to detect error conditions. */ int target_poll(struct target *target); -int target_resume(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution); +int target_resume(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution); int target_halt(struct target *target); int target_call_event_callbacks(struct target *target, enum target_event event); int target_call_reset_callbacks(struct target *target, enum target_reset_mode reset_mode); @@ -413,7 +408,6 @@ int target_call_timer_callbacks_now(void); */ int64_t target_timer_next_event(void); -struct target *get_target_by_num(int num); struct target *get_current_target(struct command_context *cmd_ctx); struct target *get_current_target_or_null(struct command_context *cmd_ctx); struct target *get_target(const char *id); @@ -424,7 +418,7 @@ struct target *get_target(const char *id); * This routine is a wrapper for the target->type->name field. * Note that this is not an instance-specific name for his target. */ -const char *target_type_name(struct target *target); +const char *target_type_name(const struct target *target); /** * Examine the specified @a target, letting it perform any @@ -435,7 +429,7 @@ const char *target_type_name(struct target *target); int target_examine_one(struct target *target); /** @returns @c true if target_set_examined() has been called. */ -static inline bool target_was_examined(struct target *target) +static inline bool target_was_examined(const struct target *target) { return target->examined; } @@ -504,7 +498,7 @@ int target_hit_watchpoint(struct target *target, * * This routine is a wrapper for target->type->get_gdb_arch. */ -const char *target_get_gdb_arch(struct target *target); +const char *target_get_gdb_arch(const struct target *target); /** * Obtain the registers for GDB. @@ -530,7 +524,7 @@ int target_get_gdb_reg_list_noread(struct target *target, * * Some target do not implement the necessary code required by GDB. */ -bool target_supports_gdb_connection(struct target *target); +bool target_supports_gdb_connection(const struct target *target); /** * Step the target. @@ -538,7 +532,7 @@ bool target_supports_gdb_connection(struct target *target); * This routine is a wrapper for target->type->step. */ int target_step(struct target *target, - int current, target_addr_t address, int handle_breakpoints); + bool current, target_addr_t address, bool handle_breakpoints); /** * Run an algorithm on the @a target given. * @@ -548,7 +542,7 @@ int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); /** * Starts an algorithm in the background on the @a target given. @@ -569,7 +563,7 @@ int target_start_algorithm(struct target *target, int target_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - target_addr_t exit_point, int timeout_ms, + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info); /** @@ -661,7 +655,7 @@ int target_checksum_memory(struct target *target, int target_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); -int target_wait_state(struct target *target, enum target_state state, int ms); +int target_wait_state(struct target *target, enum target_state state, unsigned int ms); /** * Obtain file-I/O information from target for GDB to do syscall. @@ -687,7 +681,7 @@ target_addr_t target_address_max(struct target *target); * * This routine is a wrapper for target->type->address_bits. */ -unsigned target_address_bits(struct target *target); +unsigned int target_address_bits(struct target *target); /** * Return the number of data bits this target supports. @@ -697,7 +691,7 @@ unsigned target_address_bits(struct target *target); unsigned int target_data_bits(struct target *target); /** Return the *name* of this targets current state */ -const char *target_state_name(struct target *target); +const char *target_state_name(const struct target *target); /** Return the *name* of a target event enumeration value */ const char *target_event_name(enum target_event event); @@ -780,8 +774,8 @@ int target_arch_state(struct target *target); void target_handle_event(struct target *t, enum target_event e); void target_handle_md_output(struct command_invocation *cmd, - struct target *target, target_addr_t address, unsigned size, - unsigned count, const uint8_t *buffer); + struct target *target, target_addr_t address, unsigned int size, + unsigned int count, const uint8_t *buffer); int target_profiling_default(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); @@ -799,9 +793,14 @@ int target_profiling_default(struct target *target, uint32_t *samples, uint32_t #define ERROR_TARGET_NOT_EXAMINED (-311) #define ERROR_TARGET_DUPLICATE_BREAKPOINT (-312) #define ERROR_TARGET_ALGO_EXIT (-313) +#define ERROR_TARGET_SIZE_NOT_SUPPORTED (-314) +#define ERROR_TARGET_PACKING_NOT_SUPPORTED (-315) +#define ERROR_TARGET_HALTED_DO_RESUME (-316) /* used to workaround incorrect debug halt */ extern bool get_target_reset_nag(void); #define TARGET_DEFAULT_POLLING_INTERVAL 100 +const char *target_debug_reason_str(enum target_debug_reason reason); + #endif /* OPENOCD_TARGET_TARGET_H */ diff --git a/src/target/target_request.c b/src/target/target_request.c index f3bcd2e1d2..8d51dc3d60 100644 --- a/src/target/target_request.c +++ b/src/target/target_request.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2007 by Dominic Rath * @@ -107,7 +107,7 @@ static int target_hexmsg(struct target *target, int size, uint32_t length) */ int target_request(struct target *target, uint32_t request) { - target_req_cmd_t target_req_cmd = request & 0xff; + enum target_req_cmd target_req_cmd = request & 0xff; assert(target->type->target_request_data); @@ -164,7 +164,7 @@ static int add_debug_msg_receiver(struct command_context *cmd_ctx, struct target (*p)->next = NULL; /* enable callback */ - target->dbg_msg_enabled = 1; + target->dbg_msg_enabled = true; return ERROR_OK; } @@ -225,7 +225,7 @@ int delete_debug_msg_receiver(struct command_context *cmd_ctx, struct target *ta free(c); if (!*p) { /* disable callback */ - target->dbg_msg_enabled = 0; + target->dbg_msg_enabled = false; } return ERROR_OK; } else diff --git a/src/target/target_request.h b/src/target/target_request.h index 62d5c74b1e..97edd9ede2 100644 --- a/src/target/target_request.h +++ b/src/target/target_request.h @@ -17,12 +17,12 @@ struct target; struct command_context; -typedef enum target_req_cmd { +enum target_req_cmd { TARGET_REQ_TRACEMSG, TARGET_REQ_DEBUGMSG, TARGET_REQ_DEBUGCHAR, /* TARGET_REQ_SEMIHOSTING, */ -} target_req_cmd_t; +}; struct debug_msg_receiver { struct command_context *cmd_ctx; diff --git a/src/target/target_type.h b/src/target/target_type.h index 1933e1cc7c..a146fab763 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -42,10 +42,10 @@ struct target_type { /* halt will log a warning, but return ERROR_OK if the target is already halted. */ int (*halt)(struct target *target); /* See target.c target_resume() for documentation. */ - int (*resume)(struct target *target, int current, target_addr_t address, - int handle_breakpoints, int debug_execution); - int (*step)(struct target *target, int current, target_addr_t address, - int handle_breakpoints); + int (*resume)(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints, bool debug_execution); + int (*step)(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints); /* target reset control. assert reset can be invoked when OpenOCD and * the target is out of sync. * @@ -83,7 +83,7 @@ struct target_type { * if dynamic allocation is used for this value, it must be managed by * the target, ideally by caching the result for subsequent calls. */ - const char *(*get_gdb_arch)(struct target *target); + const char *(*get_gdb_arch)(const struct target *target); /** * Target register access for GDB. Do @b not call this function @@ -181,7 +181,7 @@ struct target_type { int (*run_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, - target_addr_t exit_point, int timeout_ms, void *arch_info); + target_addr_t exit_point, unsigned int timeout_ms, void *arch_info); int (*start_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, @@ -189,22 +189,18 @@ struct target_type { int (*wait_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); const struct command_registration *commands; /* called when target is created */ - int (*target_create)(struct target *target, Jim_Interp *interp); + int (*target_create)(struct target *target); /* called for various config parameters */ /* returns JIM_CONTINUE - if option not understood */ /* otherwise: JIM_OK, or JIM_ERR, */ int (*target_jim_configure)(struct target *target, struct jim_getopt_info *goi); - /* target commands specifically handled by the target */ - /* returns JIM_OK, or JIM_ERR, or JIM_CONTINUE - if option not understood */ - int (*target_jim_commands)(struct target *target, struct jim_getopt_info *goi); - /** * This method is used to perform target setup that requires * JTAG access. @@ -286,6 +282,15 @@ struct target_type { */ int (*gdb_fileio_end)(struct target *target, int retcode, int fileio_errno, bool ctrl_c); + /* Parse target-specific GDB query commands. + * The string pointer "response_p" is always assigned by the called function + * to a pointer to a NULL-terminated string, even when the function returns + * an error. The string memory is not freed by the caller, so this function + * must pay attention for possible memory leaks if the string memory is + * dynamically allocated. + */ + int (*gdb_query_custom)(struct target *target, const char *packet, char **response_p); + /* do target profiling */ int (*profiling)(struct target *target, uint32_t *samples, @@ -294,7 +299,7 @@ struct target_type { /* Return the number of address bits this target supports. This will * typically be 32 for 32-bit targets, and 64 for 64-bit targets. If not * implemented, it's assumed to be 32. */ - unsigned (*address_bits)(struct target *target); + unsigned int (*address_bits)(struct target *target); /* Return the number of system bus data bits this target supports. This * will typically be 32 for 32-bit targets, and 64 for 64-bit targets. If @@ -302,4 +307,44 @@ struct target_type { unsigned int (*data_bits)(struct target *target); }; +// Keep in alphabetic order this list of targets +extern struct target_type aarch64_target; +extern struct target_type arcv2_target; +extern struct target_type arm11_target; +extern struct target_type arm720t_target; +extern struct target_type arm7tdmi_target; +extern struct target_type arm920t_target; +extern struct target_type arm926ejs_target; +extern struct target_type arm946e_target; +extern struct target_type arm966e_target; +extern struct target_type arm9tdmi_target; +extern struct target_type armv8r_target; +extern struct target_type avr32_ap7k_target; +extern struct target_type avr_target; +extern struct target_type cortexa_target; +extern struct target_type cortexm_target; +extern struct target_type cortexr4_target; +extern struct target_type dragonite_target; +extern struct target_type dsp563xx_target; +extern struct target_type dsp5680xx_target; +extern struct target_type esirisc_target; +extern struct target_type esp32s2_target; +extern struct target_type esp32s3_target; +extern struct target_type esp32_target; +extern struct target_type fa526_target; +extern struct target_type feroceon_target; +extern struct target_type hla_target; +extern struct target_type ls1_sap_target; +extern struct target_type mem_ap_target; +extern struct target_type mips_m4k_target; +extern struct target_type mips_mips64_target; +extern struct target_type or1k_target; +extern struct target_type quark_d20xx_target; +extern struct target_type quark_x10xx_target; +extern struct target_type riscv_target; +extern struct target_type stm8_target; +extern struct target_type testee_target; +extern struct target_type xscale_target; +extern struct target_type xtensa_chip_target; + #endif /* OPENOCD_TARGET_TARGET_TYPE_H */ diff --git a/src/target/testee.c b/src/target/testee.c index b94240fd53..687565271d 100644 --- a/src/target/testee.c +++ b/src/target/testee.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> * diff --git a/src/target/trace.c b/src/target/trace.c index c325dcc15d..333a787f92 100644 --- a/src/target/trace.c +++ b/src/target/trace.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005, 2007 by Dominic Rath * diff --git a/src/target/trace.h b/src/target/trace.h index e3d787eddf..dc3ab57124 100644 --- a/src/target/trace.h +++ b/src/target/trace.h @@ -33,13 +33,13 @@ struct trace { * to *hardware* tracing ... split such "real" tracing out from * the contrib/libdcc support. */ -typedef enum trace_status { +enum trace_status { TRACE_IDLE = 0x0, TRACE_RUNNING = 0x1, TRACE_TRIGGERED = 0x2, TRACE_COMPLETED = 0x4, TRACE_OVERFLOWED = 0x8, -} trace_status_t; +}; int trace_point(struct target *target, uint32_t number); int trace_register_commands(struct command_context *cmd_ctx); diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c index 6d3909c6bd..8cca9a5e91 100644 --- a/src/target/x86_32_common.c +++ b/src/target/x86_32_common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright(c) 2013 Intel Corporation. @@ -677,7 +677,7 @@ int x86_32_common_write_memory(struct target *t, target_addr_t addr, return retval; } -int x86_32_common_read_io(struct target *t, uint32_t addr, +static int x86_32_common_read_io(struct target *t, uint32_t addr, uint32_t size, uint8_t *buf) { struct x86_32_common *x86_32 = target_to_x86_32(t); @@ -1330,14 +1330,14 @@ static int write_hw_reg_from_cache(struct target *t, int num) /* x86 32 commands */ static void handle_iod_output(struct command_invocation *cmd, - struct target *target, uint32_t address, unsigned size, - unsigned count, const uint8_t *buffer) + struct target *target, uint32_t address, unsigned int size, + unsigned int count, const uint8_t *buffer) { - const unsigned line_bytecnt = 32; - unsigned line_modulo = line_bytecnt / size; + const unsigned int line_bytecnt = 32; + unsigned int line_modulo = line_bytecnt / size; char output[line_bytecnt * 4 + 1]; - unsigned output_len = 0; + unsigned int output_len = 0; const char *value_fmt; switch (size) { @@ -1356,12 +1356,12 @@ static void handle_iod_output(struct command_invocation *cmd, return; } - for (unsigned i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { if (i % line_modulo == 0) { output_len += snprintf(output + output_len, sizeof(output) - output_len, - "0x%8.8x: ", - (unsigned)(address + (i*size))); + "0x%8.8" PRIx32 ": ", + address + (i * size)); } uint32_t value = 0; @@ -1399,7 +1399,7 @@ COMMAND_HANDLER(handle_iod_command) return ERROR_COMMAND_SYNTAX_ERROR; } - unsigned size = 0; + unsigned int size = 0; switch (CMD_NAME[2]) { case 'w': size = 4; @@ -1413,7 +1413,7 @@ COMMAND_HANDLER(handle_iod_command) default: return ERROR_COMMAND_SYNTAX_ERROR; } - unsigned count = 1; + unsigned int count = 1; uint8_t *buffer = calloc(count, size); struct target *target = get_current_target(CMD_CTX); int retval = x86_32_common_read_io(target, address, size, buffer); @@ -1425,7 +1425,7 @@ COMMAND_HANDLER(handle_iod_command) static int target_fill_io(struct target *target, uint32_t address, - unsigned data_size, + unsigned int data_size, /* value */ uint32_t b) { @@ -1458,7 +1458,7 @@ COMMAND_HANDLER(handle_iow_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); struct target *target = get_current_target(CMD_CTX); - unsigned wordsize; + unsigned int wordsize; switch (CMD_NAME[2]) { case 'w': wordsize = 4; diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h index 4f90ab4e67..e232747697 100644 --- a/src/target/x86_32_common.h +++ b/src/target/x86_32_common.h @@ -148,7 +148,7 @@ enum { PMCR, }; -#define X86_32_COMMON_MAGIC 0x86328632 +#define X86_32_COMMON_MAGIC 0x86328632U enum { /* memory read/write */ @@ -200,7 +200,8 @@ struct swbp_mem_patch { #define NUM_PM_REGS 18 /* regs used in save/restore */ struct x86_32_common { - uint32_t common_magic; + unsigned int common_magic; + void *arch_info; enum x86_core_type core_type; struct reg_cache *cache; @@ -308,8 +309,6 @@ int x86_32_common_read_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, uint8_t *buf); int x86_32_common_write_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, const uint8_t *buf); -int x86_32_common_read_io(struct target *t, uint32_t addr, - uint32_t size, uint8_t *buf); int x86_32_common_write_io(struct target *t, uint32_t addr, uint32_t size, const uint8_t *buf); int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp); diff --git a/src/target/xscale.c b/src/target/xscale.c index 4927d00917..84318a905f 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2006, 2007 by Dominic Rath * @@ -47,8 +47,8 @@ */ /* forward declarations */ -static int xscale_resume(struct target *, int current, - target_addr_t address, int handle_breakpoints, int debug_execution); +static int xscale_resume(struct target *, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution); static int xscale_debug_entry(struct target *); static int xscale_restore_banked(struct target *); static int xscale_get_reg(struct reg *reg); @@ -137,7 +137,7 @@ static int xscale_verify_pointer(struct command_invocation *cmd, return ERROR_OK; } -static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state) +static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, enum tap_state end_state) { assert(tap); @@ -232,7 +232,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words struct xscale_common *xscale = target_to_xscale(target); int retval = ERROR_OK; - tap_state_t path[3]; + enum tap_state path[3]; struct scan_field fields[3]; uint8_t *field0 = malloc(num_words * 1); uint8_t field0_check_value = 0x2; @@ -330,8 +330,8 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words static int xscale_read_tx(struct target *target, int consume) { struct xscale_common *xscale = target_to_xscale(target); - tap_state_t path[3]; - tap_state_t noconsume_path[6]; + enum tap_state path[3]; + enum tap_state noconsume_path[6]; int retval; struct timeval timeout, now; struct scan_field fields[3]; @@ -840,7 +840,7 @@ static int xscale_debug_entry(struct target *target) struct arm *arm = &xscale->arm; uint32_t pc; uint32_t buffer[10]; - unsigned i; + unsigned int i; int retval; uint32_t moe; @@ -997,7 +997,7 @@ static int xscale_debug_entry(struct target *target) * can only happen in fill mode. */ if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) { if (--xscale->trace.fill_counter > 0) - xscale_resume(target, 1, 0x0, 1, 0); + xscale_resume(target, true, 0x0, true, false); } else /* entered debug for other reason; reset counter */ xscale->trace.fill_counter = 0; } @@ -1106,8 +1106,8 @@ static void xscale_free_trace_data(struct xscale_common *xscale) xscale->trace.data = NULL; } -static int xscale_resume(struct target *target, int current, - target_addr_t address, int handle_breakpoints, int debug_execution) +static int xscale_resume(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints, bool debug_execution) { struct xscale_common *xscale = target_to_xscale(target); struct arm *arm = &xscale->arm; @@ -1118,7 +1118,7 @@ static int xscale_resume(struct target *target, int current, LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1130,7 +1130,7 @@ static int xscale_resume(struct target *target, int current, if (retval != ERROR_OK) return retval; - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) buf_set_u32(arm->pc->value, 0, 32, address); @@ -1277,8 +1277,8 @@ static int xscale_resume(struct target *target, int current, return ERROR_OK; } -static int xscale_step_inner(struct target *target, int current, - uint32_t address, int handle_breakpoints) +static int xscale_step_inner(struct target *target, bool current, + uint32_t address, bool handle_breakpoints) { struct xscale_common *xscale = target_to_xscale(target); struct arm *arm = &xscale->arm; @@ -1372,8 +1372,8 @@ static int xscale_step_inner(struct target *target, int current, return ERROR_OK; } -static int xscale_step(struct target *target, int current, - target_addr_t address, int handle_breakpoints) +static int xscale_step(struct target *target, bool current, + target_addr_t address, bool handle_breakpoints) { struct arm *arm = target_to_arm(target); struct breakpoint *breakpoint = NULL; @@ -1382,11 +1382,11 @@ static int xscale_step(struct target *target, int current, int retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - /* current = 1: continue on current pc, otherwise continue at <address> */ + /* current = true: continue on current pc, otherwise continue at <address> */ if (!current) buf_set_u32(arm->pc->value, 0, 32, address); @@ -1515,7 +1515,7 @@ static int xscale_deassert_reset(struct target *target) */ { uint32_t address; - unsigned buf_cnt; + unsigned int buf_cnt; const uint8_t *buffer = xscale_debug_handler; int retval; @@ -1539,11 +1539,11 @@ static int xscale_deassert_reset(struct target *target) * coprocessors, trace data, etc. */ address = xscale->handler_address; - for (unsigned binary_size = sizeof(xscale_debug_handler); + for (unsigned int binary_size = sizeof(xscale_debug_handler); binary_size > 0; binary_size -= buf_cnt, buffer += buf_cnt) { uint32_t cache_line[8]; - unsigned i; + unsigned int i; buf_cnt = binary_size; if (buf_cnt > 32) @@ -1598,7 +1598,7 @@ static int xscale_deassert_reset(struct target *target) target->state = TARGET_HALTED; /* resume the target */ - xscale_resume(target, 1, 0x0, 1, 0); + xscale_resume(target, true, 0x0, true, false); } } @@ -1632,7 +1632,7 @@ static int xscale_full_context(struct target *target) LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1705,7 +1705,7 @@ static int xscale_restore_banked(struct target *target) int i, j; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1781,7 +1781,7 @@ static int xscale_read_memory(struct target *target, target_addr_t address, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1880,7 +1880,7 @@ static int xscale_write_memory(struct target *target, target_addr_t address, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2073,7 +2073,7 @@ static int xscale_set_breakpoint(struct target *target, struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2163,7 +2163,7 @@ static int xscale_unset_breakpoint(struct target *target, struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2210,7 +2210,7 @@ static int xscale_remove_breakpoint(struct target *target, struct breakpoint *br struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2232,7 +2232,7 @@ static int xscale_set_watchpoint(struct target *target, uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { - LOG_ERROR("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2296,7 +2296,7 @@ static int xscale_add_watchpoint(struct target *target, return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (watchpoint->value) + if (watchpoint->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) LOG_WARNING("xscale does not support value, mask arguments; ignoring"); /* check that length is a power of two */ @@ -2336,7 +2336,7 @@ static int xscale_unset_watchpoint(struct target *target, uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2369,7 +2369,7 @@ static int xscale_remove_watchpoint(struct target *target, struct watchpoint *wa struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2490,7 +2490,7 @@ static int xscale_read_trace(struct target *target) unsigned int num_checkpoints = 0; if (target->state != TARGET_HALTED) { - LOG_WARNING("target must be stopped to read trace data"); + LOG_TARGET_ERROR(target, "must be stopped to read trace data"); return ERROR_TARGET_NOT_HALTED; } @@ -3012,7 +3012,7 @@ static int xscale_init_arch_info(struct target *target, return ERROR_OK; } -static int xscale_target_create(struct target *target, Jim_Interp *interp) +static int xscale_target_create(struct target *target) { struct xscale_common *xscale; @@ -3131,8 +3131,8 @@ static int xscale_mmu(struct target *target, int *enabled) struct xscale_common *xscale = target_to_xscale(target); if (target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_INVALID; + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; } *enabled = xscale->armv4_5_mmu.mmu_enabled; return ERROR_OK; @@ -3149,8 +3149,8 @@ COMMAND_HANDLER(xscale_handle_mmu_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } if (CMD_ARGC >= 1) { @@ -3179,8 +3179,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } bool icache = false; @@ -3215,7 +3215,7 @@ COMMAND_HANDLER(xscale_handle_idcache_command) static const struct { char name[15]; - unsigned mask; + unsigned int mask; } vec_ids[] = { { "fiq", DCSR_TF, }, { "irq", DCSR_TI, }, @@ -3250,7 +3250,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command) } } while (CMD_ARGC-- > 0) { - unsigned i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name)) continue; @@ -3268,7 +3268,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command) } dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32); - for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(vec_ids); i++) { command_print(CMD, "%15s: %s", vec_ids[i].name, (dcsr_value & vec_ids[i].mask) ? "catch" : "ignore"); } @@ -3347,8 +3347,8 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } if (CMD_ARGC >= 1) { @@ -3451,8 +3451,8 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } if (CMD_ARGC < 1) @@ -3514,8 +3514,8 @@ COMMAND_HANDLER(xscale_handle_cp15) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; + command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; } uint32_t reg_no = 0; struct reg *reg = NULL; diff --git a/src/target/xscale.h b/src/target/xscale.h index 0087b8a43b..36a69bca39 100644 --- a/src/target/xscale.h +++ b/src/target/xscale.h @@ -15,7 +15,7 @@ #include "armv4_5_mmu.h" #include "trace.h" -#define XSCALE_COMMON_MAGIC 0x58534341 +#define XSCALE_COMMON_MAGIC 0x58534341U /* These four JTAG instructions are architecturally defined. * Lengths are core-specific; originally 5 bits, later 7. @@ -71,11 +71,11 @@ struct xscale_trace { }; struct xscale_common { + unsigned int common_magic; + /* armv4/5 common stuff */ struct arm arm; - int common_magic; - /* XScale registers (CP15, DBG) */ struct reg_cache *reg_cache; diff --git a/src/target/xtensa/Makefile.am b/src/target/xtensa/Makefile.am index a11e58530c..22504e78b2 100644 --- a/src/target/xtensa/Makefile.am +++ b/src/target/xtensa/Makefile.am @@ -4,6 +4,10 @@ noinst_LTLIBRARIES += %D%/libxtensa.la %C%_libxtensa_la_SOURCES = \ %D%/xtensa.c \ %D%/xtensa.h \ + %D%/xtensa_chip.c \ + %D%/xtensa_chip.h \ %D%/xtensa_debug_module.c \ %D%/xtensa_debug_module.h \ + %D%/xtensa_fileio.c \ + %D%/xtensa_fileio.h \ %D%/xtensa_regs.h diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index f04132e68c..3366623d64 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -1,13 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Generic Xtensa target API for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * * Copyright (C) 2016-2019 Espressif Systems Ltd. * * Derived from esp108.c * * Author: Angus Gratton gus@projectgus.com * - * Author: Jeroen Domburg <jeroen@espressif.com> * - * Author: Alexey Gerenkov <alexey@espressif.com> * - * Author: Andrey Gramakov <andrei.gramakov@espressif.com> * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -18,326 +16,281 @@ #include <helper/time_support.h> #include <helper/align.h> #include <target/register.h> +#include <target/algorithm.h> +#include "xtensa_chip.h" #include "xtensa.h" - -#define _XT_INS_FORMAT_RSR(OPCODE, SR, T) ((OPCODE) \ - | (((SR) & 0xFF) << 8) \ +/* Swap 4-bit Xtensa opcodes and fields */ +#define XT_NIBSWAP8(V) \ + ((((V) & 0x0F) << 4) \ + | (((V) & 0xF0) >> 4)) + +#define XT_NIBSWAP16(V) \ + ((((V) & 0x000F) << 12) \ + | (((V) & 0x00F0) << 4) \ + | (((V) & 0x0F00) >> 4) \ + | (((V) & 0xF000) >> 12)) + +#define XT_NIBSWAP24(V) \ + ((((V) & 0x00000F) << 20) \ + | (((V) & 0x0000F0) << 12) \ + | (((V) & 0x000F00) << 4) \ + | (((V) & 0x00F000) >> 4) \ + | (((V) & 0x0F0000) >> 12) \ + | (((V) & 0xF00000) >> 20)) + +/* _XT_INS_FORMAT_*() + * Instruction formatting converted from little-endian inputs + * and shifted to the MSB-side of DIR for BE systems. + */ +#define _XT_INS_FORMAT_RSR(X, OPCODE, SR, T) \ + (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \ + | (((T) & 0x0F) << 16) \ + | (((SR) & 0xFF) << 8)) << 8 \ + : (OPCODE) \ + | (((SR) & 0xFF) << 8) \ | (((T) & 0x0F) << 4)) -#define _XT_INS_FORMAT_RRR(OPCODE, ST, R) ((OPCODE) \ - | (((ST) & 0xFF) << 4) \ +#define _XT_INS_FORMAT_RRR(X, OPCODE, ST, R) \ + (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \ + | ((XT_NIBSWAP8((ST) & 0xFF)) << 12) \ + | (((R) & 0x0F) << 8)) << 8 \ + : (OPCODE) \ + | (((ST) & 0xFF) << 4) \ | (((R) & 0x0F) << 12)) -#define _XT_INS_FORMAT_RRRN(OPCODE, S, T, IMM4) ((OPCODE) \ - | (((T) & 0x0F) << 4) \ - | (((S) & 0x0F) << 8) \ +#define _XT_INS_FORMAT_RRRN(X, OPCODE, S, T, IMM4) \ + (XT_ISBE(X) ? (XT_NIBSWAP16(OPCODE) \ + | (((T) & 0x0F) << 8) \ + | (((S) & 0x0F) << 4) \ + | ((IMM4) & 0x0F)) << 16 \ + : (OPCODE) \ + | (((T) & 0x0F) << 4) \ + | (((S) & 0x0F) << 8) \ | (((IMM4) & 0x0F) << 12)) -#define _XT_INS_FORMAT_RRI8(OPCODE, R, S, T, IMM8) ((OPCODE) \ - | (((IMM8) & 0xFF) << 16) \ - | (((R) & 0x0F) << 12) \ - | (((S) & 0x0F) << 8) \ +#define _XT_INS_FORMAT_RRI8(X, OPCODE, R, S, T, IMM8) \ + (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \ + | (((T) & 0x0F) << 16) \ + | (((S) & 0x0F) << 12) \ + | (((R) & 0x0F) << 8) \ + | ((IMM8) & 0xFF)) << 8 \ + : (OPCODE) \ + | (((IMM8) & 0xFF) << 16) \ + | (((R) & 0x0F) << 12) \ + | (((S) & 0x0F) << 8) \ | (((T) & 0x0F) << 4)) -#define _XT_INS_FORMAT_RRI4(OPCODE, IMM4, R, S, T) ((OPCODE) \ - | (((IMM4) & 0x0F) << 20) \ - | (((R) & 0x0F) << 12) \ - | (((S) & 0x0F) << 8) \ +#define _XT_INS_FORMAT_RRI4(X, OPCODE, IMM4, R, S, T) \ + (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \ + | (((T) & 0x0F) << 16) \ + | (((S) & 0x0F) << 12) \ + | (((R) & 0x0F) << 8)) << 8 \ + | ((IMM4) & 0x0F) \ + : (OPCODE) \ + | (((IMM4) & 0x0F) << 20) \ + | (((R) & 0x0F) << 12) \ + | (((S) & 0x0F) << 8) \ | (((T) & 0x0F) << 4)) /* Xtensa processor instruction opcodes - * "Return From Debug Operation" to Normal */ -#define XT_INS_RFDO 0xf1e000 +*/ +/* "Return From Debug Operation" to Normal */ +#define XT_INS_RFDO(X) (XT_ISBE(X) ? 0x000e1f << 8 : 0xf1e000) /* "Return From Debug and Dispatch" - allow sw debugging stuff to take over */ -#define XT_INS_RFDD 0xf1e010 +#define XT_INS_RFDD(X) (XT_ISBE(X) ? 0x010e1f << 8 : 0xf1e010) /* Load to DDR register, increase addr register */ -#define XT_INS_LDDR32P(S) (0x0070E0 | ((S) << 8)) +#define XT_INS_LDDR32P(X, S) (XT_ISBE(X) ? (0x0E0700 | ((S) << 12)) << 8 : (0x0070E0 | ((S) << 8))) /* Store from DDR register, increase addr register */ -#define XT_INS_SDDR32P(S) (0x0070F0 | ((S) << 8)) - -/* Load 32-bit Indirect from A(S) + 4 * IMM8 to A(T) */ -#define XT_INS_L32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x002002, 0, S, T, IMM8) -/* Load 16-bit Unsigned from A(S) + 2 * IMM8 to A(T) */ -#define XT_INS_L16UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x001002, 0, S, T, IMM8) -/* Load 8-bit Unsigned from A(S) + IMM8 to A(T) */ -#define XT_INS_L8UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x000002, 0, S, T, IMM8) - -/* Store 32-bit Indirect to A(S) + 4 * IMM8 from A(T) */ -#define XT_INS_S32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x006002, 0, S, T, IMM8) -/* Store 16-bit to A(S) + 2 * IMM8 from A(T) */ -#define XT_INS_S16I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x005002, 0, S, T, IMM8) -/* Store 8-bit to A(S) + IMM8 from A(T) */ -#define XT_INS_S8I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x004002, 0, S, T, IMM8) +#define XT_INS_SDDR32P(X, S) (XT_ISBE(X) ? (0x0F0700 | ((S) << 12)) << 8 : (0x0070F0 | ((S) << 8))) + +/* Load 32-bit Indirect from A(S)+4*IMM8 to A(T) */ +#define XT_INS_L32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x002002, 0, S, T, IMM8) +/* Load 16-bit Unsigned from A(S)+2*IMM8 to A(T) */ +#define XT_INS_L16UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x001002, 0, S, T, IMM8) +/* Load 8-bit Unsigned from A(S)+IMM8 to A(T) */ +#define XT_INS_L8UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x000002, 0, S, T, IMM8) + +/* Store 32-bit Indirect to A(S)+4*IMM8 from A(T) */ +#define XT_INS_S32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x006002, 0, S, T, IMM8) +/* Store 16-bit to A(S)+2*IMM8 from A(T) */ +#define XT_INS_S16I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x005002, 0, S, T, IMM8) +/* Store 8-bit to A(S)+IMM8 from A(T) */ +#define XT_INS_S8I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x004002, 0, S, T, IMM8) + +/* Cache Instructions */ +#define XT_INS_IHI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x0070E2, 0, S, 0, IMM8) +#define XT_INS_DHWBI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007052, 0, S, 0, IMM8) +#define XT_INS_DHWB(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007042, 0, S, 0, IMM8) +#define XT_INS_ISYNC(X) (XT_ISBE(X) ? 0x000200 << 8 : 0x002000) + +/* Control Instructions */ +#define XT_INS_JX(X, S) (XT_ISBE(X) ? (0x050000 | ((S) << 12)) : (0x0000a0 | ((S) << 8))) +#define XT_INS_CALL0(X, IMM18) (XT_ISBE(X) ? (0x500000 | ((IMM18) & 0x3ffff)) : (0x000005 | (((IMM18) & 0x3ffff) << 6))) /* Read Special Register */ -#define XT_INS_RSR(SR, T) _XT_INS_FORMAT_RSR(0x030000, SR, T) +#define XT_INS_RSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x030000, SR, T) /* Write Special Register */ -#define XT_INS_WSR(SR, T) _XT_INS_FORMAT_RSR(0x130000, SR, T) +#define XT_INS_WSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x130000, SR, T) /* Swap Special Register */ -#define XT_INS_XSR(SR, T) _XT_INS_FORMAT_RSR(0x610000, SR, T) +#define XT_INS_XSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x610000, SR, T) /* Rotate Window by (-8..7) */ -#define XT_INS_ROTW(N) ((0x408000) | (((N) & 15) << 4)) +#define XT_INS_ROTW(X, N) (XT_ISBE(X) ? ((0x000804) | (((N) & 15) << 16)) << 8 : ((0x408000) | (((N) & 15) << 4))) /* Read User Register */ -#define XT_INS_RUR(UR, T) _XT_INS_FORMAT_RRR(0xE30000, UR, T) +#define XT_INS_RUR(X, UR, T) _XT_INS_FORMAT_RRR(X, 0xE30000, UR, T) /* Write User Register */ -#define XT_INS_WUR(UR, T) _XT_INS_FORMAT_RSR(0xF30000, UR, T) +#define XT_INS_WUR(X, UR, T) _XT_INS_FORMAT_RSR(X, 0xF30000, UR, T) /* Read Floating-Point Register */ -#define XT_INS_RFR(FR, T) _XT_INS_FORMAT_RRR(0xFA0000, (((FR) << 4) | 0x4), T) +#define XT_INS_RFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((FR << 4) | 0x4), T) /* Write Floating-Point Register */ -#define XT_INS_WFR(FR, T) _XT_INS_FORMAT_RRR(0xFA0000, (((FR) << 4) | 0x5), T) +#define XT_INS_WFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((T << 4) | 0x5), FR) -/* 32-bit break */ -#define XT_INS_BREAK(IMM1, IMM2) _XT_INS_FORMAT_RRR(0x000000, \ - (((IMM1) & 0x0F) << 4) | ((IMM2) & 0x0F), 0x4) -/* 16-bit break */ -#define XT_INS_BREAKN(IMM4) _XT_INS_FORMAT_RRRN(0x00000D, IMM4, 0x2, 0xF) +#define XT_INS_L32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x090000, 0, R, S, T) +#define XT_INS_S32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x490000, 0, R, S, T) +#define XT_INS_L32E_S32E_MASK(X) (XT_ISBE(X) ? 0xF000FF << 8 : 0xFF000F) -#define XT_INS_L32E(R, S, T) _XT_INS_FORMAT_RRI4(0x90000, 0, R, S, T) -#define XT_INS_S32E(R, S, T) _XT_INS_FORMAT_RRI4(0x490000, 0, R, S, T) -#define XT_INS_L32E_S32E_MASK 0xFF000F +#define XT_INS_RFWO(X) (XT_ISBE(X) ? 0x004300 << 8 : 0x003400) +#define XT_INS_RFWU(X) (XT_ISBE(X) ? 0x005300 << 8 : 0x003500) +#define XT_INS_RFWO_RFWU_MASK(X) (XT_ISBE(X) ? 0xFFFFFF << 8 : 0xFFFFFF) -#define XT_INS_RFWO 0x3400 -#define XT_INS_RFWU 0x3500 -#define XT_INS_RFWO_RFWU_MASK 0xFFFFFF +/* Read Protection TLB Entry Info */ +#define XT_INS_PPTLB(X, S, T) _XT_INS_FORMAT_RRR(X, 0x500000, ((S) << 4) | (T), 0xD) -#define XT_WATCHPOINTS_NUM_MAX 2 +#define XT_TLB1_ACC_SHIFT 8 +#define XT_TLB1_ACC_MSK 0xF -/* Special register number macro for DDR register. -* this gets used a lot so making a shortcut to it is -* useful. -*/ -#define XT_SR_DDR (xtensa_regs[XT_REG_IDX_OCD_DDR].reg_num) +#define XT_WATCHPOINTS_NUM_MAX 2 -/*Same thing for A3/A4 */ +/* Special register number macro for DDR, PS, WB, A3, A4 registers. + * These get used a lot so making a shortcut is useful. + */ +#define XT_SR_DDR (xtensa_regs[XT_REG_IDX_DDR].reg_num) +#define XT_SR_PS (xtensa_regs[XT_REG_IDX_PS].reg_num) +#define XT_SR_WB (xtensa_regs[XT_REG_IDX_WINDOWBASE].reg_num) +#define XT_REG_A0 (xtensa_regs[XT_REG_IDX_AR0].reg_num) #define XT_REG_A3 (xtensa_regs[XT_REG_IDX_AR3].reg_num) #define XT_REG_A4 (xtensa_regs[XT_REG_IDX_AR4].reg_num) -#define XT_PC_REG_NUM_BASE (176) -#define XT_SW_BREAKPOINTS_MAX_NUM 32 - -const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = { - { "pc", XT_PC_REG_NUM_BASE /*+XT_DEBUGLEVEL*/, XT_REG_SPECIAL, 0 }, /* actually epc[debuglevel] */ - { "ar0", 0x00, XT_REG_GENERAL, 0 }, - { "ar1", 0x01, XT_REG_GENERAL, 0 }, - { "ar2", 0x02, XT_REG_GENERAL, 0 }, - { "ar3", 0x03, XT_REG_GENERAL, 0 }, - { "ar4", 0x04, XT_REG_GENERAL, 0 }, - { "ar5", 0x05, XT_REG_GENERAL, 0 }, - { "ar6", 0x06, XT_REG_GENERAL, 0 }, - { "ar7", 0x07, XT_REG_GENERAL, 0 }, - { "ar8", 0x08, XT_REG_GENERAL, 0 }, - { "ar9", 0x09, XT_REG_GENERAL, 0 }, - { "ar10", 0x0A, XT_REG_GENERAL, 0 }, - { "ar11", 0x0B, XT_REG_GENERAL, 0 }, - { "ar12", 0x0C, XT_REG_GENERAL, 0 }, - { "ar13", 0x0D, XT_REG_GENERAL, 0 }, - { "ar14", 0x0E, XT_REG_GENERAL, 0 }, - { "ar15", 0x0F, XT_REG_GENERAL, 0 }, - { "ar16", 0x10, XT_REG_GENERAL, 0 }, - { "ar17", 0x11, XT_REG_GENERAL, 0 }, - { "ar18", 0x12, XT_REG_GENERAL, 0 }, - { "ar19", 0x13, XT_REG_GENERAL, 0 }, - { "ar20", 0x14, XT_REG_GENERAL, 0 }, - { "ar21", 0x15, XT_REG_GENERAL, 0 }, - { "ar22", 0x16, XT_REG_GENERAL, 0 }, - { "ar23", 0x17, XT_REG_GENERAL, 0 }, - { "ar24", 0x18, XT_REG_GENERAL, 0 }, - { "ar25", 0x19, XT_REG_GENERAL, 0 }, - { "ar26", 0x1A, XT_REG_GENERAL, 0 }, - { "ar27", 0x1B, XT_REG_GENERAL, 0 }, - { "ar28", 0x1C, XT_REG_GENERAL, 0 }, - { "ar29", 0x1D, XT_REG_GENERAL, 0 }, - { "ar30", 0x1E, XT_REG_GENERAL, 0 }, - { "ar31", 0x1F, XT_REG_GENERAL, 0 }, - { "ar32", 0x20, XT_REG_GENERAL, 0 }, - { "ar33", 0x21, XT_REG_GENERAL, 0 }, - { "ar34", 0x22, XT_REG_GENERAL, 0 }, - { "ar35", 0x23, XT_REG_GENERAL, 0 }, - { "ar36", 0x24, XT_REG_GENERAL, 0 }, - { "ar37", 0x25, XT_REG_GENERAL, 0 }, - { "ar38", 0x26, XT_REG_GENERAL, 0 }, - { "ar39", 0x27, XT_REG_GENERAL, 0 }, - { "ar40", 0x28, XT_REG_GENERAL, 0 }, - { "ar41", 0x29, XT_REG_GENERAL, 0 }, - { "ar42", 0x2A, XT_REG_GENERAL, 0 }, - { "ar43", 0x2B, XT_REG_GENERAL, 0 }, - { "ar44", 0x2C, XT_REG_GENERAL, 0 }, - { "ar45", 0x2D, XT_REG_GENERAL, 0 }, - { "ar46", 0x2E, XT_REG_GENERAL, 0 }, - { "ar47", 0x2F, XT_REG_GENERAL, 0 }, - { "ar48", 0x30, XT_REG_GENERAL, 0 }, - { "ar49", 0x31, XT_REG_GENERAL, 0 }, - { "ar50", 0x32, XT_REG_GENERAL, 0 }, - { "ar51", 0x33, XT_REG_GENERAL, 0 }, - { "ar52", 0x34, XT_REG_GENERAL, 0 }, - { "ar53", 0x35, XT_REG_GENERAL, 0 }, - { "ar54", 0x36, XT_REG_GENERAL, 0 }, - { "ar55", 0x37, XT_REG_GENERAL, 0 }, - { "ar56", 0x38, XT_REG_GENERAL, 0 }, - { "ar57", 0x39, XT_REG_GENERAL, 0 }, - { "ar58", 0x3A, XT_REG_GENERAL, 0 }, - { "ar59", 0x3B, XT_REG_GENERAL, 0 }, - { "ar60", 0x3C, XT_REG_GENERAL, 0 }, - { "ar61", 0x3D, XT_REG_GENERAL, 0 }, - { "ar62", 0x3E, XT_REG_GENERAL, 0 }, - { "ar63", 0x3F, XT_REG_GENERAL, 0 }, - { "lbeg", 0x00, XT_REG_SPECIAL, 0 }, - { "lend", 0x01, XT_REG_SPECIAL, 0 }, - { "lcount", 0x02, XT_REG_SPECIAL, 0 }, - { "sar", 0x03, XT_REG_SPECIAL, 0 }, - { "windowbase", 0x48, XT_REG_SPECIAL, 0 }, - { "windowstart", 0x49, XT_REG_SPECIAL, 0 }, - { "configid0", 0xB0, XT_REG_SPECIAL, 0 }, - { "configid1", 0xD0, XT_REG_SPECIAL, 0 }, - { "ps", 0xC6, XT_REG_SPECIAL, 0 }, /* actually EPS[debuglevel] */ - { "threadptr", 0xE7, XT_REG_USER, 0 }, - { "br", 0x04, XT_REG_SPECIAL, 0 }, - { "scompare1", 0x0C, XT_REG_SPECIAL, 0 }, - { "acclo", 0x10, XT_REG_SPECIAL, 0 }, - { "acchi", 0x11, XT_REG_SPECIAL, 0 }, - { "m0", 0x20, XT_REG_SPECIAL, 0 }, - { "m1", 0x21, XT_REG_SPECIAL, 0 }, - { "m2", 0x22, XT_REG_SPECIAL, 0 }, - { "m3", 0x23, XT_REG_SPECIAL, 0 }, - { "f0", 0x00, XT_REG_FR, XT_REGF_COPROC0 }, - { "f1", 0x01, XT_REG_FR, XT_REGF_COPROC0 }, - { "f2", 0x02, XT_REG_FR, XT_REGF_COPROC0 }, - { "f3", 0x03, XT_REG_FR, XT_REGF_COPROC0 }, - { "f4", 0x04, XT_REG_FR, XT_REGF_COPROC0 }, - { "f5", 0x05, XT_REG_FR, XT_REGF_COPROC0 }, - { "f6", 0x06, XT_REG_FR, XT_REGF_COPROC0 }, - { "f7", 0x07, XT_REG_FR, XT_REGF_COPROC0 }, - { "f8", 0x08, XT_REG_FR, XT_REGF_COPROC0 }, - { "f9", 0x09, XT_REG_FR, XT_REGF_COPROC0 }, - { "f10", 0x0A, XT_REG_FR, XT_REGF_COPROC0 }, - { "f11", 0x0B, XT_REG_FR, XT_REGF_COPROC0 }, - { "f12", 0x0C, XT_REG_FR, XT_REGF_COPROC0 }, - { "f13", 0x0D, XT_REG_FR, XT_REGF_COPROC0 }, - { "f14", 0x0E, XT_REG_FR, XT_REGF_COPROC0 }, - { "f15", 0x0F, XT_REG_FR, XT_REGF_COPROC0 }, - { "fcr", 0xE8, XT_REG_USER, XT_REGF_COPROC0 }, - { "fsr", 0xE9, XT_REG_USER, XT_REGF_COPROC0 }, - { "mmid", 0x59, XT_REG_SPECIAL, XT_REGF_NOREAD }, - { "ibreakenable", 0x60, XT_REG_SPECIAL, 0 }, - { "memctl", 0x61, XT_REG_SPECIAL, 0 }, - { "atomctl", 0x63, XT_REG_SPECIAL, 0 }, - { "ibreaka0", 0x80, XT_REG_SPECIAL, 0 }, - { "ibreaka1", 0x81, XT_REG_SPECIAL, 0 }, - { "dbreaka0", 0x90, XT_REG_SPECIAL, 0 }, - { "dbreaka1", 0x91, XT_REG_SPECIAL, 0 }, - { "dbreakc0", 0xA0, XT_REG_SPECIAL, 0 }, - { "dbreakc1", 0xA1, XT_REG_SPECIAL, 0 }, - { "epc1", 0xB1, XT_REG_SPECIAL, 0 }, - { "epc2", 0xB2, XT_REG_SPECIAL, 0 }, - { "epc3", 0xB3, XT_REG_SPECIAL, 0 }, - { "epc4", 0xB4, XT_REG_SPECIAL, 0 }, - { "epc5", 0xB5, XT_REG_SPECIAL, 0 }, - { "epc6", 0xB6, XT_REG_SPECIAL, 0 }, - { "epc7", 0xB7, XT_REG_SPECIAL, 0 }, - { "depc", 0xC0, XT_REG_SPECIAL, 0 }, - { "eps2", 0xC2, XT_REG_SPECIAL, 0 }, - { "eps3", 0xC3, XT_REG_SPECIAL, 0 }, - { "eps4", 0xC4, XT_REG_SPECIAL, 0 }, - { "eps5", 0xC5, XT_REG_SPECIAL, 0 }, - { "eps6", 0xC6, XT_REG_SPECIAL, 0 }, - { "eps7", 0xC7, XT_REG_SPECIAL, 0 }, - { "excsave1", 0xD1, XT_REG_SPECIAL, 0 }, - { "excsave2", 0xD2, XT_REG_SPECIAL, 0 }, - { "excsave3", 0xD3, XT_REG_SPECIAL, 0 }, - { "excsave4", 0xD4, XT_REG_SPECIAL, 0 }, - { "excsave5", 0xD5, XT_REG_SPECIAL, 0 }, - { "excsave6", 0xD6, XT_REG_SPECIAL, 0 }, - { "excsave7", 0xD7, XT_REG_SPECIAL, 0 }, - { "cpenable", 0xE0, XT_REG_SPECIAL, 0 }, - { "interrupt", 0xE2, XT_REG_SPECIAL, 0 }, - { "intset", 0xE2, XT_REG_SPECIAL, XT_REGF_NOREAD }, - { "intclear", 0xE3, XT_REG_SPECIAL, XT_REGF_NOREAD }, - { "intenable", 0xE4, XT_REG_SPECIAL, 0 }, - { "vecbase", 0xE7, XT_REG_SPECIAL, 0 }, - { "exccause", 0xE8, XT_REG_SPECIAL, 0 }, - { "debugcause", 0xE9, XT_REG_SPECIAL, 0 }, - { "ccount", 0xEA, XT_REG_SPECIAL, 0 }, - { "prid", 0xEB, XT_REG_SPECIAL, 0 }, - { "icount", 0xEC, XT_REG_SPECIAL, 0 }, - { "icountlevel", 0xED, XT_REG_SPECIAL, 0 }, - { "excvaddr", 0xEE, XT_REG_SPECIAL, 0 }, - { "ccompare0", 0xF0, XT_REG_SPECIAL, 0 }, - { "ccompare1", 0xF1, XT_REG_SPECIAL, 0 }, - { "ccompare2", 0xF2, XT_REG_SPECIAL, 0 }, - { "misc0", 0xF4, XT_REG_SPECIAL, 0 }, - { "misc1", 0xF5, XT_REG_SPECIAL, 0 }, - { "misc2", 0xF6, XT_REG_SPECIAL, 0 }, - { "misc3", 0xF7, XT_REG_SPECIAL, 0 }, - { "litbase", 0x05, XT_REG_SPECIAL, 0 }, - { "ptevaddr", 0x53, XT_REG_SPECIAL, 0 }, - { "rasid", 0x5A, XT_REG_SPECIAL, 0 }, - { "itlbcfg", 0x5B, XT_REG_SPECIAL, 0 }, - { "dtlbcfg", 0x5C, XT_REG_SPECIAL, 0 }, - { "mepc", 0x6A, XT_REG_SPECIAL, 0 }, - { "meps", 0x6B, XT_REG_SPECIAL, 0 }, - { "mesave", 0x6C, XT_REG_SPECIAL, 0 }, - { "mesr", 0x6D, XT_REG_SPECIAL, 0 }, - { "mecr", 0x6E, XT_REG_SPECIAL, 0 }, - { "mevaddr", 0x6F, XT_REG_SPECIAL, 0 }, - { "a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0 }, /* WARNING: For these registers, regnum points to the */ - { "a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0 }, /* index of the corresponding ARxregisters, NOT to */ - { "a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0 }, /* the processor register number! */ - { "a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0 }, - { "a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0 }, - { "a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0 }, - { "a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0 }, - { "a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0 }, - { "a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0 }, - { "a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0 }, - { "a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0 }, - { "a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0 }, - { "a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0 }, - { "a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0 }, - { "a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0 }, - { "a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0 }, - - { "pwrctl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pwrstat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "eristat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_itctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_claimset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_claimclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_lockaccess", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_lockstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "cs_authstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "fault_info", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_ctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_stat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_data", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_addr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_pctrigger", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_pcmatch", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_delay", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_memstart", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "trax_memend", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmg", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmoc", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pm0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pm1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmctrl0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmctrl1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmstat0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "pmstat1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "ocd_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "ocd_dcrclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "ocd_dcrset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "ocd_dsr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, - { "ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD }, +#define XT_PS_REG_NUM (0xe6U) +#define XT_EPS_REG_NUM_BASE (0xc0U) /* (EPS2 - 2), for adding DBGLEVEL */ +#define XT_EPC_REG_NUM_BASE (0xb0U) /* (EPC1 - 1), for adding DBGLEVEL */ +#define XT_PC_REG_NUM_VIRTUAL (0xffU) /* Marker for computing PC (EPC[DBGLEVEL) */ +#define XT_PC_DBREG_NUM_BASE (0x20U) /* External (i.e., GDB) access */ +#define XT_NX_IBREAKC_BASE (0xc0U) /* (IBREAKC0..IBREAKC1) for NX */ + +#define XT_SW_BREAKPOINTS_MAX_NUM 32 +#define XT_HW_IBREAK_MAX_NUM 2 +#define XT_HW_DBREAK_MAX_NUM 2 + +struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = { + XT_MK_REG_DESC("pc", XT_PC_REG_NUM_VIRTUAL, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("ar0", 0x00, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar1", 0x01, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar2", 0x02, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar3", 0x03, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar4", 0x04, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar5", 0x05, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar6", 0x06, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar7", 0x07, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar8", 0x08, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar9", 0x09, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar10", 0x0A, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar11", 0x0B, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar12", 0x0C, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar13", 0x0D, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar14", 0x0E, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar15", 0x0F, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar16", 0x10, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar17", 0x11, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar18", 0x12, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar19", 0x13, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar20", 0x14, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar21", 0x15, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar22", 0x16, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar23", 0x17, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar24", 0x18, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar25", 0x19, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar26", 0x1A, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar27", 0x1B, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar28", 0x1C, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar29", 0x1D, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar30", 0x1E, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar31", 0x1F, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar32", 0x20, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar33", 0x21, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar34", 0x22, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar35", 0x23, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar36", 0x24, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar37", 0x25, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar38", 0x26, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar39", 0x27, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar40", 0x28, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar41", 0x29, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar42", 0x2A, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar43", 0x2B, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar44", 0x2C, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar45", 0x2D, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar46", 0x2E, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar47", 0x2F, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar48", 0x30, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar49", 0x31, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar50", 0x32, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar51", 0x33, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar52", 0x34, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar53", 0x35, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar54", 0x36, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar55", 0x37, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar56", 0x38, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar57", 0x39, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar58", 0x3A, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar59", 0x3B, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar60", 0x3C, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar61", 0x3D, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar62", 0x3E, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0), + XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("ps", XT_PS_REG_NUM, XT_REG_SPECIAL, 0), /* PS (not mapped through EPS[]) */ + XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD), + XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("ibreaka1", 0x81, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("dbreaka0", 0x90, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("dbreaka1", 0x91, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("dbreakc0", 0xA0, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("dbreakc1", 0xA1, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("cpenable", 0xE0, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("exccause", 0xE8, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("debugcause", 0xE9, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("icount", 0xEC, XT_REG_SPECIAL, 0), + XT_MK_REG_DESC("icountlevel", 0xED, XT_REG_SPECIAL, 0), + + /* WARNING: For these registers, regnum points to the + * index of the corresponding ARx registers, NOT to + * the processor register number! */ + XT_MK_REG_DESC("a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0), + XT_MK_REG_DESC("a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0), }; - /** * Types of memory used at xtensa target */ @@ -346,11 +299,48 @@ enum xtensa_mem_region_type { XTENSA_MEM_REG_IRAM, XTENSA_MEM_REG_DROM, XTENSA_MEM_REG_DRAM, - XTENSA_MEM_REG_URAM, - XTENSA_MEM_REG_XLMI, + XTENSA_MEM_REG_SRAM, + XTENSA_MEM_REG_SROM, XTENSA_MEM_REGS_NUM }; +/** + * Types of access rights for MPU option + * The first block is kernel RWX ARs; the second block is user rwx ARs. + */ +enum xtensa_mpu_access_type { + XTENSA_ACC_00X_000 = 0x2, + XTENSA_ACC_000_00X, + XTENSA_ACC_R00_000, + XTENSA_ACC_R0X_000, + XTENSA_ACC_RW0_000, + XTENSA_ACC_RWX_000, + XTENSA_ACC_0W0_0W0, + XTENSA_ACC_RW0_RWX, + XTENSA_ACC_RW0_R00, + XTENSA_ACC_RWX_R0X, + XTENSA_ACC_R00_R00, + XTENSA_ACC_R0X_R0X, + XTENSA_ACC_RW0_RW0, + XTENSA_ACC_RWX_RWX +}; + +/* Register definition as union for list allocation */ +union xtensa_reg_val_u { + xtensa_reg_val_t val; + uint8_t buf[4]; +}; + +static const struct xtensa_keyval_info xt_qerr[XT_QERR_NUM] = { + { .chrval = "E00", .intval = ERROR_FAIL }, + { .chrval = "E01", .intval = ERROR_FAIL }, + { .chrval = "E02", .intval = ERROR_COMMAND_ARGUMENT_INVALID }, + { .chrval = "E03", .intval = ERROR_FAIL }, +}; + +/* Set to true for extra debug logging */ +static const bool xtensa_extra_debug_log; + /** * Gets a config for the specific mem type */ @@ -367,10 +357,10 @@ static inline const struct xtensa_local_mem_config *xtensa_get_mem_config( return &xtensa->core_config->drom; case XTENSA_MEM_REG_DRAM: return &xtensa->core_config->dram; - case XTENSA_MEM_REG_URAM: - return &xtensa->core_config->uram; - case XTENSA_MEM_REG_XLMI: - return &xtensa->core_config->xlmi; + case XTENSA_MEM_REG_SRAM: + return &xtensa->core_config->sram; + case XTENSA_MEM_REG_SROM: + return &xtensa->core_config->srom; default: return NULL; } @@ -413,14 +403,47 @@ static inline const struct xtensa_local_mem_region_config *xtensa_target_memory_ return NULL; } +static inline bool xtensa_is_cacheable(const struct xtensa_cache_config *cache, + const struct xtensa_local_mem_config *mem, + target_addr_t address) +{ + if (!cache->size) + return false; + return xtensa_memory_region_find(mem, address); +} + +static inline bool xtensa_is_icacheable(struct xtensa *xtensa, target_addr_t address) +{ + return xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->iram, address) || + xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->irom, address) || + xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->sram, address) || + xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->srom, address); +} + +static inline bool xtensa_is_dcacheable(struct xtensa *xtensa, target_addr_t address) +{ + return xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->dram, address) || + xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->drom, address) || + xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->sram, address) || + xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->srom, address); +} + static int xtensa_core_reg_get(struct reg *reg) { - /*We don't need this because we read all registers on halt anyway. */ + /* We don't need this because we read all registers on halt anyway. */ struct xtensa *xtensa = (struct xtensa *)reg->arch_info; struct target *target = xtensa->target; if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; + if (!reg->exist) { + if (strncmp(reg->name, "?0x", 3) == 0) { + unsigned int regnum = strtoul(reg->name + 1, NULL, 0); + LOG_WARNING("Read unknown register 0x%04x ignored", regnum); + return ERROR_OK; + } + return ERROR_COMMAND_ARGUMENT_INVALID; + } return ERROR_OK; } @@ -433,7 +456,31 @@ static int xtensa_core_reg_set(struct reg *reg, uint8_t *buf) if (target->state != TARGET_HALTED) return ERROR_TARGET_NOT_HALTED; + if (!reg->exist) { + if (strncmp(reg->name, "?0x", 3) == 0) { + unsigned int regnum = strtoul(reg->name + 1, NULL, 0); + LOG_WARNING("Write unknown register 0x%04x ignored", regnum); + return ERROR_OK; + } + return ERROR_COMMAND_ARGUMENT_INVALID; + } + buf_cpy(buf, reg->value, reg->size); + + if (xtensa->core_config->windowed) { + /* If the user updates a potential scratch register, track for conflicts */ + for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) { + if (strcmp(reg->name, xtensa->scratch_ars[s].chrval) == 0) { + LOG_DEBUG("Scratch reg %s [0x%08" PRIx32 "] set from gdb", reg->name, + buf_get_u32(reg->value, 0, 32)); + LOG_DEBUG("scratch_ars mapping: a3/%s, a4/%s", + xtensa->scratch_ars[XT_AR_SCRATCH_AR3].chrval, + xtensa->scratch_ars[XT_AR_SCRATCH_AR4].chrval); + xtensa->scratch_ars[s].intval = true; + break; + } + } + } reg->dirty = true; reg->valid = true; @@ -445,39 +492,30 @@ static const struct reg_arch_type xtensa_reg_type = { .set = xtensa_core_reg_set, }; -const struct reg_arch_type xtensa_user_reg_u32_type = { - .get = xtensa_core_reg_get, - .set = xtensa_core_reg_set, -}; - -const struct reg_arch_type xtensa_user_reg_u128_type = { - .get = xtensa_core_reg_get, - .set = xtensa_core_reg_set, -}; - -static inline size_t xtensa_insn_size_get(uint32_t insn) -{ - return insn & BIT(3) ? 2 : XT_ISNS_SZ_MAX; -} - /* Convert a register index that's indexed relative to windowbase, to the real address. */ -static enum xtensa_reg_id xtensa_windowbase_offset_to_canonical(enum xtensa_reg_id reg_idx, int windowbase) +static enum xtensa_reg_id xtensa_windowbase_offset_to_canonical(struct xtensa *xtensa, + enum xtensa_reg_id reg_idx, + int windowbase) { unsigned int idx; - if (reg_idx >= XT_REG_IDX_AR0 && reg_idx <= XT_REG_IDX_AR63) { + if (reg_idx >= XT_REG_IDX_AR0 && reg_idx <= XT_REG_IDX_ARLAST) { idx = reg_idx - XT_REG_IDX_AR0; } else if (reg_idx >= XT_REG_IDX_A0 && reg_idx <= XT_REG_IDX_A15) { idx = reg_idx - XT_REG_IDX_A0; } else { - LOG_ERROR("Error: can't convert register %d to non-windowbased register!", reg_idx); + LOG_ERROR("Can't convert register %d to non-windowbased register", reg_idx); return -1; } - return ((idx + windowbase * 4) & 63) + XT_REG_IDX_AR0; + /* Each windowbase value represents 4 registers on LX and 8 on NX */ + int base_inc = (xtensa->core_config->core_type == XT_LX) ? 4 : 8; + return ((idx + windowbase * base_inc) & (xtensa->core_config->aregs_num - 1)) + XT_REG_IDX_AR0; } -static enum xtensa_reg_id xtensa_canonical_to_windowbase_offset(enum xtensa_reg_id reg_idx, int windowbase) +static enum xtensa_reg_id xtensa_canonical_to_windowbase_offset(struct xtensa *xtensa, + enum xtensa_reg_id reg_idx, + int windowbase) { - return xtensa_windowbase_offset_to_canonical(reg_idx, -windowbase); + return xtensa_windowbase_offset_to_canonical(xtensa, reg_idx, -windowbase); } static void xtensa_mark_register_dirty(struct xtensa *xtensa, enum xtensa_reg_id reg_idx) @@ -486,41 +524,65 @@ static void xtensa_mark_register_dirty(struct xtensa *xtensa, enum xtensa_reg_id reg_list[reg_idx].dirty = true; } -static int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, unsigned int reg, uint8_t *data) +static void xtensa_queue_exec_ins(struct xtensa *xtensa, uint32_t ins) { - struct xtensa_debug_module *dm = &xtensa->dbg_mod; - - if (!xtensa->core_config->trace.enabled && - (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) { - LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg); - return ERROR_FAIL; - } - return dm->dbg_ops->queue_reg_read(dm, reg, data); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0EXEC, ins); } -static int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data) +static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint8_t oplen) { - struct xtensa_debug_module *dm = &xtensa->dbg_mod; - - if (!xtensa->core_config->trace.enabled && - (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) { - LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg); - return ERROR_FAIL; + const int max_oplen = 64; /* 8 DIRx regs: max width 64B */ + if ((oplen > 0) && (oplen <= max_oplen)) { + uint8_t ops_padded[max_oplen]; + memcpy(ops_padded, ops, oplen); + memset(ops_padded + oplen, 0, max_oplen - oplen); + unsigned int oplenw = DIV_ROUND_UP(oplen, sizeof(uint32_t)); + for (int32_t i = oplenw - 1; i > 0; i--) + xtensa_queue_dbg_reg_write(xtensa, + XDMREG_DIR0 + i, + target_buffer_get_u32(xtensa->target, &ops_padded[sizeof(uint32_t) * i])); + /* Write DIR0EXEC last */ + xtensa_queue_dbg_reg_write(xtensa, + XDMREG_DIR0EXEC, + target_buffer_get_u32(xtensa->target, &ops_padded[0])); } - return dm->dbg_ops->queue_reg_write(dm, reg, data); -} - -static void xtensa_queue_exec_ins(struct xtensa *xtensa, uint32_t ins) -{ - xtensa_queue_dbg_reg_write(xtensa, NARADR_DIR0EXEC, ins); } -static bool xtensa_reg_is_readable(enum xtensa_reg_flags flags, xtensa_reg_val_t cpenable) +/* NOTE: Assumes A3 has already been saved and marked dirty; A3 will be clobbered */ +static inline bool xtensa_region_ar_exec(struct target *target, target_addr_t start, target_addr_t end) { - if (flags & XT_REGF_NOREAD) - return false; - if ((flags & XT_REGF_COPROC0) && (cpenable & BIT(0)) == 0) - return false; + struct xtensa *xtensa = target_to_xtensa(target); + if (xtensa->core_config->mpu.enabled) { + /* For cores with the MPU option, issue PPTLB on start and end addresses. + * Parse access rights field, and confirm both have execute permissions. + */ + for (int i = 0; i <= 1; i++) { + uint32_t at, acc; + uint8_t at_buf[4]; + bool exec_acc; + target_addr_t addr = i ? end : start; + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addr); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_PPTLB(xtensa, XT_REG_A3, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, at_buf); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) + LOG_TARGET_ERROR(target, "Error queuing PPTLB: %d", res); + res = xtensa_core_status_check(target); + if (res != ERROR_OK) + LOG_TARGET_ERROR(target, "Error issuing PPTLB: %d", res); + at = buf_get_u32(at_buf, 0, 32); + acc = (at >> XT_TLB1_ACC_SHIFT) & XT_TLB1_ACC_MSK; + exec_acc = ((acc == XTENSA_ACC_00X_000) || (acc == XTENSA_ACC_R0X_000) || + (acc == XTENSA_ACC_RWX_000) || (acc == XTENSA_ACC_RWX_R0X) || + (acc == XTENSA_ACC_R0X_R0X) || (acc == XTENSA_ACC_RWX_RWX)); + LOG_TARGET_DEBUG(target, "PPTLB(" TARGET_ADDR_FMT ") -> 0x%08" PRIx32 " exec_acc %d", + addr, at, exec_acc); + if (!exec_acc) + return false; + } + } return true; } @@ -530,63 +592,72 @@ static int xtensa_queue_pwr_reg_write(struct xtensa *xtensa, unsigned int reg, u return dm->pwr_ops->queue_reg_write(dm, reg, data); } -static bool xtensa_special_reg_exists(struct xtensa *xtensa, enum xtensa_reg_id reg_idx) -{ - /* TODO: array of size XT_NUM_REGS can be used here to map special register ID to - * corresponding config option 'enabled' flag */ - if (reg_idx >= XT_REG_IDX_LBEG && reg_idx <= XT_REG_IDX_LCOUNT) - return xtensa->core_config->loop; - else if (reg_idx == XT_REG_IDX_BR) - return xtensa->core_config->boolean; - else if (reg_idx == XT_REG_IDX_LITBASE) - return xtensa->core_config->ext_l32r; - else if (reg_idx == XT_REG_IDX_SCOMPARE1 || reg_idx == XT_REG_IDX_ATOMCTL) - return xtensa->core_config->cond_store; - else if (reg_idx >= XT_REG_IDX_ACCLO && reg_idx <= XT_REG_IDX_M3) - return xtensa->core_config->mac16; - else if (reg_idx == XT_REG_IDX_WINDOWBASE || reg_idx == XT_REG_IDX_WINDOWSTART) - return xtensa->core_config->windowed; - else if (reg_idx >= XT_REG_IDX_PTEVADDR && reg_idx <= XT_REG_IDX_DTLBCFG) - return xtensa->core_config->mmu.enabled; - else if (reg_idx == XT_REG_IDX_MMID) - return xtensa->core_config->trace.enabled; - else if (reg_idx >= XT_REG_IDX_MEPC && reg_idx <= XT_REG_IDX_MEVADDR) - return xtensa->core_config->mem_err_check; - else if (reg_idx == XT_REG_IDX_CPENABLE) - return xtensa->core_config->coproc; - else if (reg_idx == XT_REG_IDX_VECBASE) - return xtensa->core_config->reloc_vec; - else if (reg_idx == XT_REG_IDX_CCOUNT) - return xtensa->core_config->tim_irq.enabled; - else if (reg_idx >= XT_REG_IDX_CCOMPARE0 && reg_idx <= XT_REG_IDX_CCOMPARE2) - return xtensa->core_config->tim_irq.enabled && - (reg_idx - XT_REG_IDX_CCOMPARE0 < xtensa->core_config->tim_irq.comp_num); - else if (reg_idx == XT_REG_IDX_PRID) - return xtensa->core_config->proc_id; - else if (reg_idx >= XT_REG_IDX_MISC0 && reg_idx <= XT_REG_IDX_MISC3) - return reg_idx - XT_REG_IDX_MISC0 < xtensa->core_config->miscregs_num; - return true; +/* NOTE: Assumes A3 has already been saved */ +static int xtensa_window_state_save(struct target *target, uint32_t *woe) +{ + struct xtensa *xtensa = target_to_xtensa(target); + unsigned int woe_sr = (xtensa->core_config->core_type == XT_LX) ? XT_SR_PS : XT_SR_WB; + uint32_t woe_dis; + uint8_t woe_buf[4]; + + if (xtensa->core_config->windowed) { + /* Save PS (LX) or WB (NX) and disable window overflow exceptions prior to AR save */ + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, woe_sr, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, woe_buf); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_TARGET_ERROR(target, "Failed to read %s (%d)!", + (woe_sr == XT_SR_PS) ? "PS" : "WB", res); + return res; + } + xtensa_core_status_check(target); + *woe = buf_get_u32(woe_buf, 0, 32); + woe_dis = *woe & ~((woe_sr == XT_SR_PS) ? XT_PS_WOE_MSK : XT_WB_S_MSK); + LOG_TARGET_DEBUG(target, "Clearing %s (0x%08" PRIx32 " -> 0x%08" PRIx32 ")", + (woe_sr == XT_SR_PS) ? "PS.WOE" : "WB.S", *woe, woe_dis); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe_dis); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, woe_sr, XT_REG_A3)); + } + return ERROR_OK; } -static bool xtensa_user_reg_exists(struct xtensa *xtensa, enum xtensa_reg_id reg_idx) +/* NOTE: Assumes A3 has already been saved */ +static void xtensa_window_state_restore(struct target *target, uint32_t woe) { - if (reg_idx == XT_REG_IDX_THREADPTR) - return xtensa->core_config->threadptr; - if (reg_idx == XT_REG_IDX_FCR || reg_idx == XT_REG_IDX_FSR) - return xtensa->core_config->fp_coproc; - return false; + struct xtensa *xtensa = target_to_xtensa(target); + unsigned int woe_sr = (xtensa->core_config->core_type == XT_LX) ? XT_SR_PS : XT_SR_WB; + if (xtensa->core_config->windowed) { + /* Restore window overflow exception state */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, woe_sr, XT_REG_A3)); + LOG_TARGET_DEBUG(target, "Restored %s (0x%08" PRIx32 ")", + (woe_sr == XT_SR_PS) ? "PS.WOE" : "WB", woe); + } } -static inline bool xtensa_fp_reg_exists(struct xtensa *xtensa, enum xtensa_reg_id reg_idx) +static bool xtensa_reg_is_readable(int flags, int cpenable) { - return xtensa->core_config->fp_coproc; + if (flags & XT_REGF_NOREAD) + return false; + if ((flags & XT_REGF_COPROC0) && (cpenable & BIT(0)) == 0) + return false; + return true; } -static inline bool xtensa_regular_reg_exists(struct xtensa *xtensa, enum xtensa_reg_id reg_idx) +static bool xtensa_scratch_regs_fixup(struct xtensa *xtensa, struct reg *reg_list, int i, int j, int a_idx, int ar_idx) { - if (reg_idx >= XT_REG_IDX_AR0 && reg_idx <= XT_REG_IDX_AR63) - return reg_idx - XT_REG_IDX_AR0 < xtensa->core_config->aregs_num; - return true; + int a_name = (a_idx == XT_AR_SCRATCH_A3) ? 3 : 4; + if (xtensa->scratch_ars[a_idx].intval && !xtensa->scratch_ars[ar_idx].intval) { + LOG_DEBUG("AR conflict: a%d -> ar%d", a_name, j - XT_REG_IDX_AR0); + memcpy(reg_list[j].value, reg_list[i].value, sizeof(xtensa_reg_val_t)); + } else { + LOG_DEBUG("AR conflict: ar%d -> a%d", j - XT_REG_IDX_AR0, a_name); + memcpy(reg_list[i].value, reg_list[j].value, sizeof(xtensa_reg_val_t)); + } + return xtensa->scratch_ars[a_idx].intval && xtensa->scratch_ars[ar_idx].intval; } static int xtensa_write_dirty_registers(struct target *target) @@ -594,45 +665,66 @@ static int xtensa_write_dirty_registers(struct target *target) struct xtensa *xtensa = target_to_xtensa(target); int res; xtensa_reg_val_t regval, windowbase = 0; - bool scratch_reg_dirty = false; + bool scratch_reg_dirty = false, delay_cpenable = false; struct reg *reg_list = xtensa->core_cache->reg_list; + unsigned int reg_list_size = xtensa->core_cache->num_regs; + bool preserve_a3 = false; + uint8_t a3_buf[4]; + xtensa_reg_val_t a3 = 0, woe; + unsigned int ms_idx = (xtensa->core_config->core_type == XT_NX) ? + xtensa->nx_reg_idx[XT_NX_REG_IDX_MS] : reg_list_size; + xtensa_reg_val_t ms = 0; + bool restore_ms = false; LOG_TARGET_DEBUG(target, "start"); - /*We need to write the dirty registers in the cache list back to the processor. - *Start by writing the SFR/user registers. */ - for (unsigned int i = 0; i < XT_NUM_REGS; i++) { + /* We need to write the dirty registers in the cache list back to the processor. + * Start by writing the SFR/user registers. */ + for (unsigned int i = 0; i < reg_list_size; i++) { + struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs; + unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS; if (reg_list[i].dirty) { - if (xtensa_regs[i].type == XT_REG_SPECIAL || - xtensa_regs[i].type == XT_REG_USER || - xtensa_regs[i].type == XT_REG_FR) { + if (rlist[ridx].type == XT_REG_SPECIAL || + rlist[ridx].type == XT_REG_USER || + rlist[ridx].type == XT_REG_FR) { scratch_reg_dirty = true; + if (i == XT_REG_IDX_CPENABLE) { + delay_cpenable = true; + continue; + } regval = xtensa_reg_get(target, i); - LOG_TARGET_DEBUG(target, "Writing back reg %s val %08" PRIX32, - xtensa_regs[i].name, + LOG_TARGET_DEBUG(target, "Writing back reg %s (%d) val %08" PRIX32, + reg_list[i].name, + rlist[ridx].reg_num, regval); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); - if (xtensa_regs[i].type == XT_REG_USER) { - if (reg_list[i].exist) - xtensa_queue_exec_ins(xtensa, - XT_INS_WUR(xtensa_regs[i].reg_num, - XT_REG_A3)); - } else if (xtensa_regs[i].type == XT_REG_FR) { - if (reg_list[i].exist) - xtensa_queue_exec_ins(xtensa, - XT_INS_WFR(xtensa_regs[i].reg_num, - XT_REG_A3)); - } else {/*SFR */ - if (reg_list[i].exist) { - unsigned int reg_num = xtensa_regs[i].reg_num; - if (reg_num == XT_PC_REG_NUM_BASE) - /* reg number of PC for debug interrupt - * depends on NDEBUGLEVEL */ - reg_num += xtensa->core_config->debug.irq_level; - - xtensa_queue_exec_ins(xtensa, - XT_INS_WSR(reg_num, XT_REG_A3)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + if (reg_list[i].exist) { + unsigned int reg_num = rlist[ridx].reg_num; + if (rlist[ridx].type == XT_REG_USER) { + xtensa_queue_exec_ins(xtensa, XT_INS_WUR(xtensa, reg_num, XT_REG_A3)); + } else if (rlist[ridx].type == XT_REG_FR) { + xtensa_queue_exec_ins(xtensa, XT_INS_WFR(xtensa, reg_num, XT_REG_A3)); + } else {/*SFR */ + if (reg_num == XT_PC_REG_NUM_VIRTUAL) { + if (xtensa->core_config->core_type == XT_LX) { + /* reg number of PC for debug interrupt depends on NDEBUGLEVEL */ + reg_num = (XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3)); + } else { + /* NX PC set through issuing a jump instruction */ + xtensa_queue_exec_ins(xtensa, XT_INS_JX(xtensa, XT_REG_A3)); + } + } else if (i == ms_idx) { + /* MS must be restored after ARs. This ensures ARs remain in correct + * order even for reversed register groups (overflow/underflow). + */ + ms = regval; + restore_ms = true; + LOG_TARGET_DEBUG(target, "Delaying MS write: 0x%x", ms); + } else { + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3)); + } } } reg_list[i].dirty = false; @@ -641,31 +733,71 @@ static int xtensa_write_dirty_registers(struct target *target) } if (scratch_reg_dirty) xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); + if (delay_cpenable) { + regval = xtensa_reg_get(target, XT_REG_IDX_CPENABLE); + LOG_TARGET_DEBUG(target, "Writing back reg cpenable (224) val %08" PRIX32, regval); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, + xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, + XT_REG_A3)); + reg_list[XT_REG_IDX_CPENABLE].dirty = false; + } - if (xtensa->core_config->user_regs_num > 0 && - xtensa->core_config->queue_write_dirty_user_regs) - xtensa->core_config->queue_write_dirty_user_regs(target); + preserve_a3 = (xtensa->core_config->windowed) || (xtensa->core_config->core_type == XT_NX); + if (preserve_a3) { + /* Save (windowed) A3 for scratch use */ + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a3_buf); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) + return res; + xtensa_core_status_check(target); + a3 = buf_get_u32(a3_buf, 0, 32); + } if (xtensa->core_config->windowed) { - /*Grab the windowbase, we need it. */ - windowbase = xtensa_reg_get(target, XT_REG_IDX_WINDOWBASE); - /*Check if there are problems with both the ARx as well as the corresponding Rx - * registers set and dirty. */ - /*Warn the user if this happens, not much else we can do... */ + res = xtensa_window_state_save(target, &woe); + if (res != ERROR_OK) + return res; + /* Grab the windowbase, we need it. */ + uint32_t wb_idx = (xtensa->core_config->core_type == XT_LX) ? + XT_REG_IDX_WINDOWBASE : xtensa->nx_reg_idx[XT_NX_REG_IDX_WB]; + windowbase = xtensa_reg_get(target, wb_idx); + if (xtensa->core_config->core_type == XT_NX) + windowbase = (windowbase & XT_WB_P_MSK) >> XT_WB_P_SHIFT; + + /* Check if there are mismatches between the ARx and corresponding Ax registers. + * When the user sets a register on a windowed config, xt-gdb may set the ARx + * register directly. Thus we take ARx as priority over Ax if both are dirty + * and it's unclear if the user set one over the other explicitly. + */ for (unsigned int i = XT_REG_IDX_A0; i <= XT_REG_IDX_A15; i++) { - unsigned int j = xtensa_windowbase_offset_to_canonical(i, windowbase); + unsigned int j = xtensa_windowbase_offset_to_canonical(xtensa, i, windowbase); if (reg_list[i].dirty && reg_list[j].dirty) { - if (memcmp(reg_list[i].value, reg_list[j].value, - sizeof(xtensa_reg_val_t)) != 0) - LOG_WARNING( - "Warning: Both A%d as well as the physical register it points to (AR%d) are dirty and differs in value. Results are undefined!", - i - XT_REG_IDX_A0, - j - XT_REG_IDX_AR0); + if (memcmp(reg_list[i].value, reg_list[j].value, sizeof(xtensa_reg_val_t)) != 0) { + bool show_warning = true; + if (i == XT_REG_IDX_A3) + show_warning = xtensa_scratch_regs_fixup(xtensa, + reg_list, i, j, XT_AR_SCRATCH_A3, XT_AR_SCRATCH_AR3); + else if (i == XT_REG_IDX_A4) + show_warning = xtensa_scratch_regs_fixup(xtensa, + reg_list, i, j, XT_AR_SCRATCH_A4, XT_AR_SCRATCH_AR4); + if (show_warning) + LOG_WARNING( + "Warning: Both A%d [0x%08" PRIx32 + "] as well as its underlying physical register " + "(AR%d) [0x%08" PRIx32 "] are dirty and differ in value", + i - XT_REG_IDX_A0, + buf_get_u32(reg_list[i].value, 0, 32), + j - XT_REG_IDX_AR0, + buf_get_u32(reg_list[j].value, 0, 32)); + } } } } - /*Write A0-A16 */ + /* Write A0-A16. */ for (unsigned int i = 0; i < 16; i++) { if (reg_list[XT_REG_IDX_A0 + i].dirty) { regval = xtensa_reg_get(target, XT_REG_IDX_A0 + i); @@ -673,22 +805,26 @@ static int xtensa_write_dirty_registers(struct target *target) xtensa_regs[XT_REG_IDX_A0 + i].name, regval, xtensa_regs[XT_REG_IDX_A0 + i].reg_num); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, i)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, i)); reg_list[XT_REG_IDX_A0 + i].dirty = false; + if (i == 3) { + /* Avoid stomping A3 during restore at end of function */ + a3 = regval; + } } } if (xtensa->core_config->windowed) { - /*Now write AR0-AR63. */ - for (unsigned int j = 0; j < 64; j += 16) { - /*Write the 16 registers we can see */ + /* Now write AR registers */ + for (unsigned int j = 0; j < XT_REG_IDX_ARLAST; j += 16) { + /* Write the 16 registers we can see */ for (unsigned int i = 0; i < 16; i++) { if (i + j < xtensa->core_config->aregs_num) { enum xtensa_reg_id realadr = - xtensa_windowbase_offset_to_canonical(XT_REG_IDX_AR0 + i + j, + xtensa_windowbase_offset_to_canonical(xtensa, XT_REG_IDX_AR0 + i + j, windowbase); - /*Write back any dirty un-windowed registers */ + /* Write back any dirty un-windowed registers */ if (reg_list[realadr].dirty) { regval = xtensa_reg_get(target, realadr); LOG_TARGET_DEBUG( @@ -697,55 +833,48 @@ static int xtensa_write_dirty_registers(struct target *target) xtensa_regs[realadr].name, regval, xtensa_regs[realadr].reg_num); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval); xtensa_queue_exec_ins(xtensa, - XT_INS_RSR(XT_SR_DDR, xtensa_regs[XT_REG_IDX_AR0 + i].reg_num)); + XT_INS_RSR(xtensa, XT_SR_DDR, + xtensa_regs[XT_REG_IDX_AR0 + i].reg_num)); reg_list[realadr].dirty = false; + if ((i + j) == 3) + /* Avoid stomping AR during A3 restore at end of function */ + a3 = regval; } } } - /*Now rotate the window so we'll see the next 16 registers. The final rotate - * will wraparound, */ - /*leaving us in the state we were. */ - xtensa_queue_exec_ins(xtensa, XT_INS_ROTW(4)); + + /* Now rotate the window so we'll see the next 16 registers. The final rotate + * will wraparound, leaving us in the state we were. + * Each ROTW rotates 4 registers on LX and 8 on NX */ + int rotw_arg = (xtensa->core_config->core_type == XT_LX) ? 4 : 2; + xtensa_queue_exec_ins(xtensa, XT_INS_ROTW(xtensa, rotw_arg)); } - } - res = jtag_execute_queue(); - xtensa_core_status_check(target); - return res; -} + xtensa_window_state_restore(target, woe); -int xtensa_queue_write_dirty_user_regs_u32(struct target *target) -{ - struct xtensa *xtensa = target_to_xtensa(target); - struct reg *reg_list = xtensa->core_cache->reg_list; - xtensa_reg_val_t reg_val; - bool scratch_reg_dirty = false; + for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) + xtensa->scratch_ars[s].intval = false; + } - LOG_TARGET_DEBUG(target, "start"); + if (restore_ms) { + uint32_t ms_regno = xtensa->optregs[ms_idx - XT_NUM_REGS].reg_num; + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, ms); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, ms_regno, XT_REG_A3)); + LOG_TARGET_DEBUG(target, "Delayed MS (0x%x) write complete: 0x%x", ms_regno, ms); + } - /* We need to write the dirty registers in the cache list back to the processor. - * Start by writing the SFR/user registers. */ - for (unsigned int i = 0; i < xtensa->core_config->user_regs_num; i++) { - if (!reg_list[XT_USR_REG_START + i].dirty) - continue; - scratch_reg_dirty = true; - reg_val = xtensa_reg_get(target, XT_USR_REG_START + i); - LOG_TARGET_DEBUG(target, "Writing back reg %s val %08" PRIX32, - xtensa->core_config->user_regs[i].name, - reg_val); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, reg_val); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_exec_ins(xtensa, - XT_INS_WUR(xtensa->core_config->user_regs[i].reg_num, - XT_REG_A3)); - reg_list[XT_USR_REG_START + i].dirty = false; + if (preserve_a3) { + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, a3); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); } - if (scratch_reg_dirty) - xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); - return ERROR_OK; + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + xtensa_core_status_check(target); + + return res; } static inline bool xtensa_is_stopped(struct target *target) @@ -757,14 +886,20 @@ static inline bool xtensa_is_stopped(struct target *target) int xtensa_examine(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); - unsigned int cmd = PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP; + unsigned int cmd = PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_COREWAKEUP(xtensa); + + LOG_TARGET_DEBUG(target, ""); + + if (xtensa->core_config->core_type == XT_UNDEF) { + LOG_ERROR("XTensa core not configured; is xtensa-core-openocd.cfg missing?"); + return ERROR_FAIL; + } - LOG_DEBUG("coreid = %d", target->coreid); - xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd); - xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE); + xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd); + xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE(xtensa)); xtensa_dm_queue_enable(&xtensa->dbg_mod); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) return res; if (!xtensa_dm_is_online(&xtensa->dbg_mod)) { @@ -772,8 +907,7 @@ int xtensa_examine(struct target *target) return ERROR_TARGET_FAILURE; } LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id); - if (!target_was_examined(target)) - target_set_examined(target); + target_set_examined(target); xtensa_smpbreak_write(xtensa, xtensa->smp_break); return ERROR_OK; } @@ -781,15 +915,15 @@ int xtensa_examine(struct target *target) int xtensa_wakeup(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); - unsigned int cmd = PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP; + unsigned int cmd = PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_COREWAKEUP(xtensa); if (xtensa->reset_asserted) - cmd |= PWRCTL_CORERESET; - xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd); + cmd |= PWRCTL_CORERESET(xtensa); + xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd); /* TODO: can we join this with the write above? */ - xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE); + xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE(xtensa)); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(&xtensa->dbg_mod); } int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set) @@ -800,11 +934,11 @@ int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set) OCDDCR_DEBUGMODEOUTEN | OCDDCR_ENABLEOCD); LOG_TARGET_DEBUG(xtensa->target, "write smpbreak set=0x%" PRIx32 " clear=0x%" PRIx32, set, clear); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRSET, set | OCDDCR_ENABLEOCD); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRCLR, clear); - xtensa_queue_dbg_reg_write(xtensa, NARADR_DSR, dsr_data); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, set | OCDDCR_ENABLEOCD); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRCLR, clear); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DSR, dsr_data); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(&xtensa->dbg_mod); } int xtensa_smpbreak_set(struct target *target, uint32_t set) @@ -815,7 +949,8 @@ int xtensa_smpbreak_set(struct target *target, uint32_t set) xtensa->smp_break = set; if (target_was_examined(target)) res = xtensa_smpbreak_write(xtensa, xtensa->smp_break); - LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set, target->state); + LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state %s", set, + target_state_name(target)); return res; } @@ -823,9 +958,9 @@ int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val) { uint8_t dcr_buf[sizeof(uint32_t)]; - xtensa_queue_dbg_reg_read(xtensa, NARADR_DCRSET, dcr_buf); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DCRSET, dcr_buf); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); *val = buf_get_u32(dcr_buf, 0, 32); return res; @@ -849,10 +984,41 @@ static inline void xtensa_reg_set_value(struct reg *reg, xtensa_reg_val_t value) reg->dirty = true; } +static int xtensa_imprecise_exception_occurred(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + for (enum xtensa_nx_reg_idx idx = XT_NX_REG_IDX_IEVEC; idx <= XT_NX_REG_IDX_MESR; idx++) { + enum xtensa_reg_id ridx = xtensa->nx_reg_idx[idx]; + if (xtensa->nx_reg_idx[idx]) { + xtensa_reg_val_t reg = xtensa_reg_get(target, xtensa->nx_reg_idx[idx]); + if (reg & XT_IMPR_EXC_MSK) { + LOG_TARGET_DEBUG(target, "Imprecise exception: %s: 0x%x", + xtensa->core_cache->reg_list[ridx].name, reg); + return true; + } + } + } + return false; +} + +static void xtensa_imprecise_exception_clear(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + for (enum xtensa_nx_reg_idx idx = XT_NX_REG_IDX_IEVEC; idx <= XT_NX_REG_IDX_MESRCLR; idx++) { + enum xtensa_reg_id ridx = xtensa->nx_reg_idx[idx]; + if (ridx && idx != XT_NX_REG_IDX_MESR) { + xtensa_reg_val_t value = (idx == XT_NX_REG_IDX_MESRCLR) ? XT_MESRCLR_IMPR_EXC_MSK : 0; + xtensa_reg_set(target, ridx, value); + LOG_TARGET_DEBUG(target, "Imprecise exception: clearing %s (0x%x)", + xtensa->core_cache->reg_list[ridx].name, value); + } + } +} + int xtensa_core_status_check(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); - int res, needclear = 0; + int res, needclear = 0, needimprclear = 0; xtensa_dm_core_status_read(&xtensa->dbg_mod); xtensa_dsr_t dsr = xtensa_dm_core_status_get(&xtensa->dbg_mod); @@ -876,12 +1042,21 @@ int xtensa_core_status_check(struct target *target) dsr); needclear = 1; } + if (xtensa->core_config->core_type == XT_NX && (xtensa_imprecise_exception_occurred(target))) { + if (!xtensa->suppress_dsr_errors) + LOG_TARGET_ERROR(target, + "%s: Imprecise exception occurred!", target_name(target)); + needclear = 1; + needimprclear = 1; + } if (needclear) { res = xtensa_dm_core_status_clear(&xtensa->dbg_mod, OCDDSR_EXECEXCEPTION | OCDDSR_EXECOVERRUN); if (res != ERROR_OK && !xtensa->suppress_dsr_errors) LOG_TARGET_ERROR(target, "clearing DSR failed!"); - return xtensa->suppress_dsr_errors ? ERROR_OK : ERROR_FAIL; + if (xtensa->core_config->core_type == XT_NX && needimprclear) + xtensa_imprecise_exception_clear(target); + return ERROR_FAIL; } return ERROR_OK; } @@ -890,7 +1065,6 @@ xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id { struct xtensa *xtensa = target_to_xtensa(target); struct reg *reg = &xtensa->core_cache->reg_list[reg_id]; - assert(reg_id < xtensa->core_cache->num_regs && "Attempt to access non-existing reg!"); return xtensa_reg_get_value(reg); } @@ -898,28 +1072,112 @@ void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg { struct xtensa *xtensa = target_to_xtensa(target); struct reg *reg = &xtensa->core_cache->reg_list[reg_id]; - assert(reg_id < xtensa->core_cache->num_regs && "Attempt to access non-existing reg!"); if (xtensa_reg_get_value(reg) == value) return; xtensa_reg_set_value(reg, value); } +/* Set Ax (XT_REG_RELGEN) register along with its underlying ARx (XT_REG_GENERAL) */ +void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value) +{ + struct xtensa *xtensa = target_to_xtensa(target); + uint32_t wb_idx = (xtensa->core_config->core_type == XT_LX) ? + XT_REG_IDX_WINDOWBASE : xtensa->nx_reg_idx[XT_NX_REG_IDX_WB]; + uint32_t windowbase = (xtensa->core_config->windowed ? + xtensa_reg_get(target, wb_idx) : 0); + if (xtensa->core_config->core_type == XT_NX) + windowbase = (windowbase & XT_WB_P_MSK) >> XT_WB_P_SHIFT; + int ar_idx = xtensa_windowbase_offset_to_canonical(xtensa, a_idx, windowbase); + xtensa_reg_set(target, a_idx, value); + xtensa_reg_set(target, ar_idx, value); +} + +/* Read cause for entering halted state; return bitmask in DEBUGCAUSE_* format */ +uint32_t xtensa_cause_get(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + if (xtensa->core_config->core_type == XT_LX) { + /* LX cause in DEBUGCAUSE */ + return xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE); + } + if (xtensa->nx_stop_cause & DEBUGCAUSE_VALID) + return xtensa->nx_stop_cause; + + /* NX cause determined from DSR.StopCause */ + if (xtensa_dm_core_status_read(&xtensa->dbg_mod) != ERROR_OK) { + LOG_TARGET_ERROR(target, "Read DSR error"); + } else { + uint32_t dsr = xtensa_dm_core_status_get(&xtensa->dbg_mod); + /* NX causes are prioritized; only 1 bit can be set */ + switch ((dsr & OCDDSR_STOPCAUSE) >> OCDDSR_STOPCAUSE_SHIFT) { + case OCDDSR_STOPCAUSE_DI: + xtensa->nx_stop_cause = DEBUGCAUSE_DI; + break; + case OCDDSR_STOPCAUSE_SS: + xtensa->nx_stop_cause = DEBUGCAUSE_IC; + break; + case OCDDSR_STOPCAUSE_IB: + xtensa->nx_stop_cause = DEBUGCAUSE_IB; + break; + case OCDDSR_STOPCAUSE_B: + case OCDDSR_STOPCAUSE_B1: + xtensa->nx_stop_cause = DEBUGCAUSE_BI; + break; + case OCDDSR_STOPCAUSE_BN: + xtensa->nx_stop_cause = DEBUGCAUSE_BN; + break; + case OCDDSR_STOPCAUSE_DB0: + case OCDDSR_STOPCAUSE_DB1: + xtensa->nx_stop_cause = DEBUGCAUSE_DB; + break; + default: + LOG_TARGET_ERROR(target, "Unknown stop cause (DSR: 0x%08x)", dsr); + break; + } + if (xtensa->nx_stop_cause) + xtensa->nx_stop_cause |= DEBUGCAUSE_VALID; + } + return xtensa->nx_stop_cause; +} + +void xtensa_cause_clear(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + if (xtensa->core_config->core_type == XT_LX) { + xtensa_reg_set(target, XT_REG_IDX_DEBUGCAUSE, 0); + xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false; + } else { + /* NX DSR.STOPCAUSE is not writeable; clear cached copy but leave it valid */ + xtensa->nx_stop_cause = DEBUGCAUSE_VALID; + } +} + +void xtensa_cause_reset(struct target *target) +{ + /* Clear DEBUGCAUSE_VALID to trigger re-read (on NX) */ + struct xtensa *xtensa = target_to_xtensa(target); + xtensa->nx_stop_cause = 0; +} + int xtensa_assert_reset(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); - LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number); - target->state = TARGET_RESET; + LOG_TARGET_DEBUG(target, " begin"); xtensa_queue_pwr_reg_write(xtensa, - DMREG_PWRCTL, - PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP | - PWRCTL_CORERESET); + XDMREG_PWRCTL, + PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | + PWRCTL_COREWAKEUP(xtensa) | PWRCTL_CORERESET(xtensa)); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) return res; + + /* registers are now invalid */ xtensa->reset_asserted = true; - return res; + register_cache_invalidate(xtensa->core_cache); + target->state = TARGET_RESET; + return ERROR_OK; } int xtensa_deassert_reset(struct target *target) @@ -929,13 +1187,14 @@ int xtensa_deassert_reset(struct target *target) LOG_TARGET_DEBUG(target, "halt=%d", target->reset_halt); if (target->reset_halt) xtensa_queue_dbg_reg_write(xtensa, - NARADR_DCRSET, + XDMREG_DCRSET, OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT); xtensa_queue_pwr_reg_write(xtensa, - DMREG_PWRCTL, - PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP); + XDMREG_PWRCTL, + PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | + PWRCTL_COREWAKEUP(xtensa)); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) return res; target->state = TARGET_RUNNING; @@ -943,17 +1202,64 @@ int xtensa_deassert_reset(struct target *target) return res; } +int xtensa_soft_reset_halt(struct target *target) +{ + LOG_TARGET_DEBUG(target, "begin"); + return xtensa_assert_reset(target); +} + int xtensa_fetch_all_regs(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); struct reg *reg_list = xtensa->core_cache->reg_list; - xtensa_reg_val_t cpenable = 0, windowbase = 0; - uint8_t regvals[XT_NUM_REGS][sizeof(xtensa_reg_val_t)]; - uint8_t dsrs[XT_NUM_REGS][sizeof(xtensa_dsr_t)]; + unsigned int reg_list_size = xtensa->core_cache->num_regs; + xtensa_reg_val_t cpenable = 0, windowbase = 0, a0 = 0, a3; + unsigned int ms_idx = reg_list_size; + uint32_t ms = 0; + uint32_t woe; + uint8_t a0_buf[4], a3_buf[4], ms_buf[4]; bool debug_dsrs = !xtensa->regs_fetched || LOG_LEVEL_IS(LOG_LVL_DEBUG); + union xtensa_reg_val_u *regvals = calloc(reg_list_size, sizeof(*regvals)); + if (!regvals) { + LOG_TARGET_ERROR(target, "unable to allocate memory for regvals!"); + return ERROR_FAIL; + } + union xtensa_reg_val_u *dsrs = calloc(reg_list_size, sizeof(*dsrs)); + if (!dsrs) { + LOG_TARGET_ERROR(target, "unable to allocate memory for dsrs!"); + free(regvals); + return ERROR_FAIL; + } + LOG_TARGET_DEBUG(target, "start"); + /* Save (windowed) A3 so cache matches physical AR3; A3 usable as scratch */ + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a3_buf); + if (xtensa->core_config->core_type == XT_NX) { + /* Save (windowed) A0 as well--it will be required for reading PC */ + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A0)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a0_buf); + + /* Set MS.DispSt, clear MS.DE prior to accessing ARs. This ensures ARs remain + * in correct order even for reversed register groups (overflow/underflow). + */ + ms_idx = xtensa->nx_reg_idx[XT_NX_REG_IDX_MS]; + uint32_t ms_regno = xtensa->optregs[ms_idx - XT_NUM_REGS].reg_num; + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, ms_regno, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, ms_buf); + LOG_TARGET_DEBUG(target, "Overriding MS (0x%x): 0x%x", ms_regno, XT_MS_DISPST_DBG); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, XT_MS_DISPST_DBG); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, ms_regno, XT_REG_A3)); + } + + int res = xtensa_window_state_save(target, &woe); + if (res != ERROR_OK) + goto xtensa_fetch_all_regs_done; + /* Assume the CPU has just halted. We now want to fill the register cache with all the * register contents GDB needs. For speed, we pipeline all the read operations, execute them * in one go, then sort everything out from the regvals variable. */ @@ -964,176 +1270,221 @@ int xtensa_fetch_all_regs(struct target *target) for (unsigned int i = 0; i < 16; i++) { if (i + j < xtensa->core_config->aregs_num) { xtensa_queue_exec_ins(xtensa, - XT_INS_WSR(XT_SR_DDR, xtensa_regs[XT_REG_IDX_AR0 + i].reg_num)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[XT_REG_IDX_AR0 + i + j]); + XT_INS_WSR(xtensa, XT_SR_DDR, xtensa_regs[XT_REG_IDX_AR0 + i].reg_num)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, + regvals[XT_REG_IDX_AR0 + i + j].buf); if (debug_dsrs) - xtensa_queue_dbg_reg_read(xtensa, NARADR_DSR, dsrs[XT_REG_IDX_AR0 + i + j]); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DSR, + dsrs[XT_REG_IDX_AR0 + i + j].buf); } } if (xtensa->core_config->windowed) { /* Now rotate the window so we'll see the next 16 registers. The final rotate - * will wraparound, */ - /* leaving us in the state we were. */ - xtensa_queue_exec_ins(xtensa, XT_INS_ROTW(4)); + * will wraparound, leaving us in the state we were. + * Each ROTW rotates 4 registers on LX and 8 on NX */ + int rotw_arg = (xtensa->core_config->core_type == XT_LX) ? 4 : 2; + xtensa_queue_exec_ins(xtensa, XT_INS_ROTW(xtensa, rotw_arg)); } } + xtensa_window_state_restore(target, woe); + if (xtensa->core_config->coproc) { - /* As the very first thing after AREGS, go grab the CPENABLE registers. It indicates - * if we can also grab the FP */ - /* (and theoretically other coprocessor) registers, or if this is a bad thing to do.*/ - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3)); - xtensa_queue_exec_ins(xtensa, XT_INS_WSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[XT_REG_IDX_CPENABLE]); - } - int res = jtag_execute_queue(); + /* As the very first thing after AREGS, go grab CPENABLE */ + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, regvals[XT_REG_IDX_CPENABLE].buf); + } + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) { LOG_ERROR("Failed to read ARs (%d)!", res); - return res; + goto xtensa_fetch_all_regs_done; } xtensa_core_status_check(target); - if (xtensa->core_config->coproc) - cpenable = buf_get_u32(regvals[XT_REG_IDX_CPENABLE], 0, 32); + a3 = buf_get_u32(a3_buf, 0, 32); + if (xtensa->core_config->core_type == XT_NX) { + a0 = buf_get_u32(a0_buf, 0, 32); + ms = buf_get_u32(ms_buf, 0, 32); + } + + if (xtensa->core_config->coproc) { + cpenable = buf_get_u32(regvals[XT_REG_IDX_CPENABLE].buf, 0, 32); + + /* Enable all coprocessors (by setting all bits in CPENABLE) so we can read FP and user registers. */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, 0xffffffff); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3)); + + /* Save CPENABLE; flag dirty later (when regcache updated) so original value is always restored */ + LOG_TARGET_DEBUG(target, "CPENABLE: was 0x%" PRIx32 ", all enabled", cpenable); + xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable); + } /* We're now free to use any of A0-A15 as scratch registers * Grab the SFRs and user registers first. We use A3 as a scratch register. */ - for (unsigned int i = 0; i < XT_NUM_REGS; i++) { - if (xtensa_reg_is_readable(xtensa_regs[i].flags, cpenable) && reg_list[i].exist && - (xtensa_regs[i].type == XT_REG_SPECIAL || - xtensa_regs[i].type == XT_REG_USER || xtensa_regs[i].type == XT_REG_FR)) { - if (xtensa_regs[i].type == XT_REG_USER) { - xtensa_queue_exec_ins(xtensa, XT_INS_RUR(xtensa_regs[i].reg_num, XT_REG_A3)); - } else if (xtensa_regs[i].type == XT_REG_FR) { - xtensa_queue_exec_ins(xtensa, XT_INS_RFR(xtensa_regs[i].reg_num, XT_REG_A3)); - } else { /*SFR */ - unsigned int reg_num = xtensa_regs[i].reg_num; - if (reg_num == XT_PC_REG_NUM_BASE) { - /* reg number of PC for debug interrupt depends on NDEBUGLEVEL */ - reg_num += xtensa->core_config->debug.irq_level; + for (unsigned int i = 0; i < reg_list_size; i++) { + struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs; + unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS; + if (xtensa_reg_is_readable(rlist[ridx].flags, cpenable) && rlist[ridx].exist) { + bool reg_fetched = true; + unsigned int reg_num = rlist[ridx].reg_num; + switch (rlist[ridx].type) { + case XT_REG_USER: + xtensa_queue_exec_ins(xtensa, XT_INS_RUR(xtensa, reg_num, XT_REG_A3)); + break; + case XT_REG_FR: + xtensa_queue_exec_ins(xtensa, XT_INS_RFR(xtensa, reg_num, XT_REG_A3)); + break; + case XT_REG_SPECIAL: + if (reg_num == XT_PC_REG_NUM_VIRTUAL) { + if (xtensa->core_config->core_type == XT_LX) { + /* reg number of PC for debug interrupt depends on NDEBUGLEVEL */ + reg_num = XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level; + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, reg_num, XT_REG_A3)); + } else { + /* NX PC read through CALL0(0) and reading A0 */ + xtensa_queue_exec_ins(xtensa, XT_INS_CALL0(xtensa, 0)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A0)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, regvals[i].buf); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DSR, dsrs[i].buf); + reg_fetched = false; + } + } else if ((xtensa->core_config->core_type == XT_LX) + && (reg_num == xtensa_regs[XT_REG_IDX_PS].reg_num)) { + /* reg number of PS for debug interrupt depends on NDEBUGLEVEL */ + reg_num = XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level; + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, reg_num, XT_REG_A3)); + } else if (reg_num == xtensa_regs[XT_REG_IDX_CPENABLE].reg_num) { + /* CPENABLE already read/updated; don't re-read */ + reg_fetched = false; + break; + } else { + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, reg_num, XT_REG_A3)); } - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(reg_num, XT_REG_A3)); + break; + default: + reg_fetched = false; + } + if (reg_fetched) { + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, regvals[i].buf); + if (debug_dsrs) + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DSR, dsrs[i].buf); } - xtensa_queue_exec_ins(xtensa, XT_INS_WSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[i]); - if (debug_dsrs) - xtensa_queue_dbg_reg_read(xtensa, NARADR_DSR, dsrs[i]); } } /* Ok, send the whole mess to the CPU. */ - res = jtag_execute_queue(); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) { LOG_ERROR("Failed to fetch AR regs!"); - return res; + goto xtensa_fetch_all_regs_done; } xtensa_core_status_check(target); if (debug_dsrs) { /* DSR checking: follows order in which registers are requested. */ - for (unsigned int i = 0; i < XT_NUM_REGS; i++) { - if (xtensa_reg_is_readable(xtensa_regs[i].flags, cpenable) && reg_list[i].exist && - (xtensa_regs[i].type == XT_REG_SPECIAL || xtensa_regs[i].type == XT_REG_USER || - xtensa_regs[i].type == XT_REG_FR)) { - if (buf_get_u32(dsrs[i], 0, 32) & OCDDSR_EXECEXCEPTION) { - LOG_ERROR("Exception reading %s!", xtensa_regs[i].name); - return ERROR_FAIL; + for (unsigned int i = 0; i < reg_list_size; i++) { + struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs; + unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS; + if (xtensa_reg_is_readable(rlist[ridx].flags, cpenable) && rlist[ridx].exist && + (rlist[ridx].type != XT_REG_DEBUG) && + (rlist[ridx].type != XT_REG_RELGEN) && + (rlist[ridx].type != XT_REG_TIE) && + (rlist[ridx].type != XT_REG_OTHER)) { + if (buf_get_u32(dsrs[i].buf, 0, 32) & OCDDSR_EXECEXCEPTION) { + LOG_ERROR("Exception reading %s!", reg_list[i].name); + res = ERROR_FAIL; + goto xtensa_fetch_all_regs_done; } } } } - if (xtensa->core_config->user_regs_num > 0 && xtensa->core_config->fetch_user_regs) { - res = xtensa->core_config->fetch_user_regs(target); - if (res != ERROR_OK) - return res; - } - if (xtensa->core_config->windowed) { /* We need the windowbase to decode the general addresses. */ - windowbase = buf_get_u32(regvals[XT_REG_IDX_WINDOWBASE], 0, 32); + uint32_t wb_idx = (xtensa->core_config->core_type == XT_LX) ? + XT_REG_IDX_WINDOWBASE : xtensa->nx_reg_idx[XT_NX_REG_IDX_WB]; + windowbase = buf_get_u32(regvals[wb_idx].buf, 0, 32); + if (xtensa->core_config->core_type == XT_NX) + windowbase = (windowbase & XT_WB_P_MSK) >> XT_WB_P_SHIFT; } + /* Decode the result and update the cache. */ - for (unsigned int i = 0; i < XT_NUM_REGS; i++) { - if (xtensa_reg_is_readable(xtensa_regs[i].flags, cpenable) && reg_list[i].exist) { - if (xtensa_regs[i].type == XT_REG_GENERAL) { - /* TODO: add support for non-windowed configs */ - assert( - xtensa->core_config->windowed && - "Regs fetch is not supported for non-windowed configs!"); + for (unsigned int i = 0; i < reg_list_size; i++) { + struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs; + unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS; + if (xtensa_reg_is_readable(rlist[ridx].flags, cpenable) && rlist[ridx].exist) { + if ((xtensa->core_config->windowed) && (rlist[ridx].type == XT_REG_GENERAL)) { /* The 64-value general register set is read from (windowbase) on down. * We need to get the real register address by subtracting windowbase and * wrapping around. */ - int realadr = xtensa_canonical_to_windowbase_offset(i, windowbase); - buf_cpy(regvals[realadr], reg_list[i].value, reg_list[i].size); - } else if (xtensa_regs[i].type == XT_REG_RELGEN) { - buf_cpy(regvals[xtensa_regs[i].reg_num], reg_list[i].value, reg_list[i].size); + enum xtensa_reg_id realadr = xtensa_canonical_to_windowbase_offset(xtensa, i, + windowbase); + buf_cpy(regvals[realadr].buf, reg_list[i].value, reg_list[i].size); + } else if (rlist[ridx].type == XT_REG_RELGEN) { + buf_cpy(regvals[rlist[ridx].reg_num].buf, reg_list[i].value, reg_list[i].size); + if (xtensa_extra_debug_log) { + xtensa_reg_val_t regval = buf_get_u32(regvals[rlist[ridx].reg_num].buf, 0, 32); + LOG_DEBUG("%s = 0x%x", rlist[ridx].name, regval); + } } else { - buf_cpy(regvals[i], reg_list[i].value, reg_list[i].size); + xtensa_reg_val_t regval = buf_get_u32(regvals[i].buf, 0, 32); + bool is_dirty = (i == XT_REG_IDX_CPENABLE); + if (xtensa_extra_debug_log) + LOG_INFO("Register %s: 0x%X", reg_list[i].name, regval); + if (rlist[ridx].reg_num == XT_PC_REG_NUM_VIRTUAL && + xtensa->core_config->core_type == XT_NX) { + /* A0 from prior CALL0 points to next instruction; decrement it */ + regval -= 3; + is_dirty = 1; + } else if (i == ms_idx) { + LOG_TARGET_DEBUG(target, "Caching MS: 0x%x", ms); + regval = ms; + is_dirty = 1; + } + xtensa_reg_set(target, i, regval); + reg_list[i].dirty = is_dirty; /*always do this _after_ xtensa_reg_set! */ } reg_list[i].valid = true; } else { - reg_list[i].valid = false; - } - } - /* We have used A3 as a scratch register and we will need to write that back. */ - xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); - xtensa->regs_fetched = true; - - return ERROR_OK; -} - -int xtensa_fetch_user_regs_u32(struct target *target) -{ - struct xtensa *xtensa = target_to_xtensa(target); - struct reg *reg_list = xtensa->core_cache->reg_list; - xtensa_reg_val_t cpenable = 0; - uint8_t regvals[XT_USER_REGS_NUM_MAX][sizeof(xtensa_reg_val_t)]; - uint8_t dsrs[XT_USER_REGS_NUM_MAX][sizeof(xtensa_dsr_t)]; - bool debug_dsrs = !xtensa->regs_fetched || LOG_LEVEL_IS(LOG_LVL_DEBUG); - - assert(xtensa->core_config->user_regs_num < XT_USER_REGS_NUM_MAX && "Too many user regs configured!"); - if (xtensa->core_config->coproc) - cpenable = xtensa_reg_get(target, XT_REG_IDX_CPENABLE); - - for (unsigned int i = 0; i < xtensa->core_config->user_regs_num; i++) { - if (!xtensa_reg_is_readable(xtensa->core_config->user_regs[i].flags, cpenable)) - continue; - xtensa_queue_exec_ins(xtensa, XT_INS_RUR(xtensa->core_config->user_regs[i].reg_num, XT_REG_A3)); - xtensa_queue_exec_ins(xtensa, XT_INS_WSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[i]); - if (debug_dsrs) - xtensa_queue_dbg_reg_read(xtensa, NARADR_DSR, dsrs[i]); - } - /* Ok, send the whole mess to the CPU. */ - int res = jtag_execute_queue(); - if (res != ERROR_OK) { - LOG_ERROR("Failed to fetch AR regs!"); - return res; - } - xtensa_core_status_check(target); - - if (debug_dsrs) { - /* DSR checking: follows order in which registers are requested. */ - for (unsigned int i = 0; i < xtensa->core_config->user_regs_num; i++) { - if (!xtensa_reg_is_readable(xtensa->core_config->user_regs[i].flags, cpenable)) - continue; - if (buf_get_u32(dsrs[i], 0, 32) & OCDDSR_EXECEXCEPTION) { - LOG_ERROR("Exception reading %s!", xtensa->core_config->user_regs[i].name); - return ERROR_FAIL; + if ((rlist[ridx].flags & XT_REGF_MASK) == XT_REGF_NOREAD) { + /* Report read-only registers all-zero but valid */ + reg_list[i].valid = true; + xtensa_reg_set(target, i, 0); + } else { + reg_list[i].valid = false; } } } - for (unsigned int i = 0; i < xtensa->core_config->user_regs_num; i++) { - if (xtensa_reg_is_readable(xtensa->core_config->user_regs[i].flags, cpenable)) { - buf_cpy(regvals[i], reg_list[XT_USR_REG_START + i].value, reg_list[XT_USR_REG_START + i].size); - reg_list[XT_USR_REG_START + i].valid = true; - } else { - reg_list[XT_USR_REG_START + i].valid = false; - } + if (xtensa->core_config->windowed) { + /* We have used A3 as a scratch register. + * Windowed configs: restore A3's AR (XT_REG_GENERAL) and and flag for write-back. + */ + enum xtensa_reg_id ar3_idx = xtensa_windowbase_offset_to_canonical(xtensa, XT_REG_IDX_A3, windowbase); + xtensa_reg_set(target, ar3_idx, a3); + xtensa_mark_register_dirty(xtensa, ar3_idx); + + /* Reset scratch_ars[] on fetch. .chrval tracks AR mapping and changes w/ window */ + sprintf(xtensa->scratch_ars[XT_AR_SCRATCH_AR3].chrval, "ar%d", ar3_idx - XT_REG_IDX_AR0); + enum xtensa_reg_id ar4_idx = xtensa_windowbase_offset_to_canonical(xtensa, XT_REG_IDX_A4, windowbase); + sprintf(xtensa->scratch_ars[XT_AR_SCRATCH_AR4].chrval, "ar%d", ar4_idx - XT_REG_IDX_AR0); + for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) + xtensa->scratch_ars[s].intval = false; } - /* We have used A3 as a scratch register and we will need to write that back. */ + /* We have used A3 (XT_REG_RELGEN) as a scratch register. Restore and flag for write-back. */ + xtensa_reg_set(target, XT_REG_IDX_A3, a3); xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); - return ERROR_OK; + if (xtensa->core_config->core_type == XT_NX) { + xtensa_reg_set(target, XT_REG_IDX_A0, a0); + xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A0); + } + + xtensa->regs_fetched = true; +xtensa_fetch_all_regs_done: + free(regvals); + free(dsrs); + return res; } int xtensa_get_gdb_reg_list(struct target *target, @@ -1142,23 +1493,65 @@ int xtensa_get_gdb_reg_list(struct target *target, enum target_register_class reg_class) { struct xtensa *xtensa = target_to_xtensa(target); - unsigned int num_regs = xtensa->core_config->gdb_general_regs_num; + unsigned int num_regs; - if (reg_class == REG_CLASS_ALL) - num_regs = xtensa->regs_num; + if (reg_class == REG_CLASS_GENERAL) { + if ((xtensa->genpkt_regs_num == 0) || !xtensa->contiguous_regs_list) { + LOG_ERROR("reg_class %d unhandled; 'xtgregs' not found", reg_class); + return ERROR_FAIL; + } + num_regs = xtensa->genpkt_regs_num; + } else { + /* Determine whether to return a contiguous or sparse register map */ + num_regs = xtensa->regmap_contiguous ? xtensa->total_regs_num : xtensa->dbregs_num; + } - LOG_DEBUG("reg_class=%i, num_regs=%d", reg_class, num_regs); + LOG_DEBUG("reg_class=%i, num_regs=%d", (int)reg_class, num_regs); - *reg_list = malloc(num_regs * sizeof(struct reg *)); + *reg_list = calloc(num_regs, sizeof(struct reg *)); if (!*reg_list) return ERROR_FAIL; - for (unsigned int k = 0; k < num_regs; k++) { - unsigned int reg_id = xtensa->core_config->gdb_regs_mapping[k]; - (*reg_list)[k] = &xtensa->core_cache->reg_list[reg_id]; + *reg_list_size = num_regs; + if (xtensa->regmap_contiguous) { + assert((num_regs <= xtensa->total_regs_num) && "contiguous regmap size internal error!"); + for (unsigned int i = 0; i < num_regs; i++) + (*reg_list)[i] = xtensa->contiguous_regs_list[i]; + return ERROR_OK; } - *reg_list_size = num_regs; + for (unsigned int i = 0; i < num_regs; i++) + (*reg_list)[i] = (struct reg *)&xtensa->empty_regs[i]; + unsigned int k = 0; + for (unsigned int i = 0; i < xtensa->core_cache->num_regs && k < num_regs; i++) { + if (xtensa->core_cache->reg_list[i].exist) { + struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs; + unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS; + int sparse_idx = rlist[ridx].dbreg_num; + if (i == XT_REG_IDX_PS && xtensa->core_config->core_type == XT_LX) { + if (xtensa->eps_dbglevel_idx == 0) { + LOG_ERROR("eps_dbglevel_idx not set\n"); + return ERROR_FAIL; + } + (*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx]; + if (xtensa_extra_debug_log) + LOG_DEBUG("SPARSE GDB reg 0x%x getting EPS%d 0x%x", + sparse_idx, xtensa->core_config->debug.irq_level, + xtensa_reg_get_value((*reg_list)[sparse_idx])); + } else if (rlist[ridx].type == XT_REG_RELGEN) { + (*reg_list)[sparse_idx - XT_REG_IDX_ARFIRST] = &xtensa->core_cache->reg_list[i]; + } else { + (*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[i]; + } + if (i == XT_REG_IDX_PC) + /* Make a duplicate copy of PC for external access */ + (*reg_list)[XT_PC_DBREG_NUM_BASE] = &xtensa->core_cache->reg_list[i]; + k++; + } + } + + if (k == num_regs) + LOG_ERROR("SPARSE GDB reg list full (size %d)", k); return ERROR_OK; } @@ -1188,9 +1581,9 @@ int xtensa_halt(struct target *target) } LOG_TARGET_DEBUG(target, "Core status 0x%" PRIx32, xtensa_dm_core_status_get(&xtensa->dbg_mod)); if (!xtensa_is_stopped(target)) { - xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRSET, OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT); xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - res = jtag_execute_queue(); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) LOG_TARGET_ERROR(target, "Failed to set OCDDCR_DEBUGINTERRUPT. Can't halt."); } @@ -1199,10 +1592,10 @@ int xtensa_halt(struct target *target) } int xtensa_prepare_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, + bool debug_execution) { struct xtensa *xtensa = target_to_xtensa(target); uint32_t bpena = 0; @@ -1215,28 +1608,29 @@ int xtensa_prepare_resume(struct target *target, debug_execution); if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } + xtensa->halt_request = false; if (address && !current) { xtensa_reg_set(target, XT_REG_IDX_PC, address); } else { - xtensa_reg_val_t cause = xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE); - if (cause & DEBUGCAUSE_DB) { + uint32_t cause = xtensa_cause_get(target); + LOG_TARGET_DEBUG(target, "DEBUGCAUSE 0x%x (watchpoint %lu) (break %lu)", + cause, (cause & DEBUGCAUSE_DB), (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN))); + if (cause & DEBUGCAUSE_DB) /* We stopped due to a watchpoint. We can't just resume executing the * instruction again because */ /* that would trigger the watchpoint again. To fix this, we single-step, * which ignores watchpoints. */ xtensa_do_step(target, current, address, handle_breakpoints); - } - if (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { + if (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN)) /* We stopped due to a break instruction. We can't just resume executing the * instruction again because */ /* that would trigger the break again. To fix this, we single-step, which * ignores break. */ xtensa_do_step(target, current, address, handle_breakpoints); - } } /* Write back hw breakpoints. Current FreeRTOS SMP code can set a hw breakpoint on an @@ -1245,10 +1639,13 @@ int xtensa_prepare_resume(struct target *target, if (xtensa->hw_brps[slot]) { /* Write IBREAKA[slot] and set bit #slot in IBREAKENABLE */ xtensa_reg_set(target, XT_REG_IDX_IBREAKA0 + slot, xtensa->hw_brps[slot]->address); + if (xtensa->core_config->core_type == XT_NX) + xtensa_reg_set(target, xtensa->nx_reg_idx[XT_NX_REG_IDX_IBREAKC0] + slot, XT_IBREAKC_FB); bpena |= BIT(slot); } } - xtensa_reg_set(target, XT_REG_IDX_IBREAKENABLE, bpena); + if (xtensa->core_config->core_type == XT_LX) + xtensa_reg_set(target, XT_REG_IDX_IBREAKENABLE, bpena); /* Here we write all registers to the targets */ int res = xtensa_write_dirty_registers(target); @@ -1263,8 +1660,9 @@ int xtensa_do_resume(struct target *target) LOG_TARGET_DEBUG(target, "start"); - xtensa_queue_exec_ins(xtensa, XT_INS_RFDO); - int res = jtag_execute_queue(); + xtensa_cause_reset(target); + xtensa_queue_exec_ins(xtensa, XT_INS_RFDO(xtensa)); + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to exec RFDO %d!", res); return res; @@ -1274,13 +1672,14 @@ int xtensa_do_resume(struct target *target) } int xtensa_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution) + bool handle_breakpoints, + bool debug_execution) { LOG_TARGET_DEBUG(target, "start"); - int res = xtensa_prepare_resume(target, current, address, handle_breakpoints, debug_execution); + int res = xtensa_prepare_resume(target, current, address, + handle_breakpoints, debug_execution); if (res != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to prepare for resume!"); return res; @@ -1304,50 +1703,54 @@ int xtensa_resume(struct target *target, static bool xtensa_pc_in_winexc(struct target *target, target_addr_t pc) { + struct xtensa *xtensa = target_to_xtensa(target); uint8_t insn_buf[XT_ISNS_SZ_MAX]; int err = xtensa_read_buffer(target, pc, sizeof(insn_buf), insn_buf); if (err != ERROR_OK) return false; xtensa_insn_t insn = buf_get_u32(insn_buf, 0, 24); - xtensa_insn_t masked = insn & XT_INS_L32E_S32E_MASK; - if (masked == XT_INS_L32E(0, 0, 0) || masked == XT_INS_S32E(0, 0, 0)) + xtensa_insn_t masked = insn & XT_INS_L32E_S32E_MASK(xtensa); + if (masked == XT_INS_L32E(xtensa, 0, 0, 0) || masked == XT_INS_S32E(xtensa, 0, 0, 0)) return true; - masked = insn & XT_INS_RFWO_RFWU_MASK; - if (masked == XT_INS_RFWO || masked == XT_INS_RFWU) + masked = insn & XT_INS_RFWO_RFWU_MASK(xtensa); + if (masked == XT_INS_RFWO(xtensa) || masked == XT_INS_RFWU(xtensa)) return true; return false; } -int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) +int xtensa_do_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { struct xtensa *xtensa = target_to_xtensa(target); int res; const uint32_t icount_val = -2; /* ICOUNT value to load for 1 step */ xtensa_reg_val_t dbreakc[XT_WATCHPOINTS_NUM_MAX]; xtensa_reg_val_t icountlvl, cause; - xtensa_reg_val_t oldps, newps, oldpc, cur_pc; + xtensa_reg_val_t oldps, oldpc, cur_pc; + bool ps_modified = false; LOG_TARGET_DEBUG(target, "current=%d, address=" TARGET_ADDR_FMT ", handle_breakpoints=%i", current, address, handle_breakpoints); if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - if (xtensa->core_config->debug.icount_sz != 32) { - LOG_TARGET_WARNING(target, "stepping for ICOUNT less then 32 bits is not implemented!"); + if (xtensa->eps_dbglevel_idx == 0 && xtensa->core_config->core_type == XT_LX) { + LOG_TARGET_ERROR(target, "eps_dbglevel_idx not set\n"); return ERROR_FAIL; } - /* Save old ps/pc */ - oldps = xtensa_reg_get(target, XT_REG_IDX_PS); + /* Save old ps (EPS[dbglvl] on LX), pc */ + oldps = xtensa_reg_get(target, (xtensa->core_config->core_type == XT_LX) ? + xtensa->eps_dbglevel_idx : XT_REG_IDX_PS); oldpc = xtensa_reg_get(target, XT_REG_IDX_PC); - cause = xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE); + cause = xtensa_cause_get(target); LOG_TARGET_DEBUG(target, "oldps=%" PRIx32 ", oldpc=%" PRIx32 " dbg_cause=%" PRIx32 " exc_cause=%" PRIx32, oldps, oldpc, @@ -1356,8 +1759,7 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in if (handle_breakpoints && (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN))) { /* handle hard-coded SW breakpoints (e.g. syscalls) */ LOG_TARGET_DEBUG(target, "Increment PC to pass break instruction..."); - xtensa_reg_set(target, XT_REG_IDX_DEBUGCAUSE, 0); /* so we don't recurse into the same routine */ - xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false; + xtensa_cause_clear(target); /* so we don't recurse into the same routine */ /* pretend that we have stepped */ if (cause & DEBUGCAUSE_BI) xtensa_reg_set(target, XT_REG_IDX_PC, oldpc + 3); /* PC = PC+3 */ @@ -1366,33 +1768,44 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in return ERROR_OK; } - /* Xtensa has an ICOUNTLEVEL register which sets the maximum interrupt level at which the - * instructions are to be counted while stepping. - * For example, if we need to step by 2 instructions, and an interrupt occurs inbetween, - * the processor will execute the interrupt, return, and halt after the 2nd instruction. - * However, sometimes we don't want the interrupt handlers to be executed at all, while - * stepping through the code. In this case (XT_STEPPING_ISR_OFF), PS.INTLEVEL can be raised - * to only allow Debug and NMI interrupts. + /* Xtensa LX has an ICOUNTLEVEL register which sets the maximum interrupt level + * at which the instructions are to be counted while stepping. + * + * For example, if we need to step by 2 instructions, and an interrupt occurs + * in between, the processor will trigger the interrupt and halt after the 2nd + * instruction within the interrupt vector and/or handler. + * + * However, sometimes we don't want the interrupt handlers to be executed at all + * while stepping through the code. In this case (XT_STEPPING_ISR_OFF), + * ICOUNTLEVEL can be lowered to the executing code's (level + 1) to prevent ISR + * code from being counted during stepping. Note that C exception handlers must + * run at level 0 and hence will be counted and stepped into, should one occur. + * + * TODO: Certain instructions should never be single-stepped and should instead + * be emulated (per DUG): RSIL >= DBGLEVEL, RSR/WSR [ICOUNT|ICOUNTLEVEL], and + * RFI >= DBGLEVEL. */ if (xtensa->stepping_isr_mode == XT_STEPPING_ISR_OFF) { - if (!xtensa->core_config->high_irq.enabled) { - LOG_TARGET_WARNING( - target, - "disabling IRQs while stepping is not implemented w/o high prio IRQs option!"); - return ERROR_FAIL; + if (xtensa->core_config->core_type == XT_LX) { + if (!xtensa->core_config->high_irq.enabled) { + LOG_TARGET_WARNING(target, + "disabling IRQs while stepping is not implemented w/o high prio IRQs option!"); + return ERROR_FAIL; + } + /* Update ICOUNTLEVEL accordingly */ + icountlvl = MIN((oldps & 0xF) + 1, xtensa->core_config->debug.irq_level); + } else { + /* Xtensa NX does not have the ICOUNTLEVEL feature present in Xtensa LX + * and instead disable interrupts while stepping. This could change + * the timing of the system while under debug */ + xtensa_reg_val_t newps = oldps | XT_PS_DI_MSK; + xtensa_reg_set(target, XT_REG_IDX_PS, newps); + icountlvl = xtensa->core_config->debug.irq_level; + ps_modified = true; } - /* Mask all interrupts below Debug, i.e. PS.INTLEVEL = DEBUGLEVEL - 1 */ - xtensa_reg_val_t temp_ps = (oldps & ~0xF) | (xtensa->core_config->debug.irq_level - 1); - xtensa_reg_set(target, XT_REG_IDX_PS, temp_ps); + } else { + icountlvl = xtensa->core_config->debug.irq_level; } - /* Regardless of ISRs masking mode we need to count instructions at any CINTLEVEL during step. - So set `icountlvl` to DEBUGLEVEL. - If ISRs are masked they are disabled in PS (see above), so having `icountlvl` set to DEBUGLEVEL - will allow to step through any type of the code, e.g. 'high int level' ISR. - If ISRs are not masked With `icountlvl` set to DEBUGLEVEL, we can step into any ISR - which can happen (enabled in PS). - */ - icountlvl = xtensa->core_config->debug.irq_level; if (cause & DEBUGCAUSE_DB) { /* We stopped due to a watchpoint. We can't just resume executing the instruction again because @@ -1401,28 +1814,40 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in LOG_TARGET_DEBUG( target, "Single-stepping to get past instruction that triggered the watchpoint..."); - xtensa_reg_set(target, XT_REG_IDX_DEBUGCAUSE, 0); /*so we don't recurse into - * the same routine */ - xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false; - /*Save all DBREAKCx registers and set to 0 to disable watchpoints */ + xtensa_cause_clear(target); /* so we don't recurse into the same routine */ + /* Save all DBREAKCx registers and set to 0 to disable watchpoints */ for (unsigned int slot = 0; slot < xtensa->core_config->debug.dbreaks_num; slot++) { dbreakc[slot] = xtensa_reg_get(target, XT_REG_IDX_DBREAKC0 + slot); xtensa_reg_set(target, XT_REG_IDX_DBREAKC0 + slot, 0); } } - if (!handle_breakpoints && (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN))) { + if (!handle_breakpoints && (cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN))) /* handle normal SW breakpoint */ - xtensa_reg_set(target, XT_REG_IDX_DEBUGCAUSE, 0); /*so we don't recurse into - * the same routine */ - xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false; + xtensa_cause_clear(target); /* so we don't recurse into the same routine */ + if (xtensa->core_config->core_type == XT_LX && ((oldps & 0xf) >= icountlvl)) { + /* Lower interrupt level to allow stepping, but flag eps[dbglvl] to be restored */ + ps_modified = true; + uint32_t newps = (oldps & ~0xf) | (icountlvl - 1); + xtensa_reg_set(target, xtensa->eps_dbglevel_idx, newps); + LOG_TARGET_DEBUG(target, + "Lowering PS.INTLEVEL to allow stepping: %s <- 0x%08" PRIx32 " (was 0x%08" PRIx32 ")", + xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx].name, + newps, + oldps); } do { - xtensa_reg_set(target, XT_REG_IDX_ICOUNTLEVEL, icountlvl); - xtensa_reg_set(target, XT_REG_IDX_ICOUNT, icount_val); + if (xtensa->core_config->core_type == XT_LX) { + xtensa_reg_set(target, XT_REG_IDX_ICOUNTLEVEL, icountlvl); + xtensa_reg_set(target, XT_REG_IDX_ICOUNT, icount_val); + } else { + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, OCDDCR_STEPREQUEST); + } - /* Now ICOUNT is set, we can resume as if we were going to run */ - res = xtensa_prepare_resume(target, current, address, 0, 0); + /* Now that ICOUNT (LX) or DCR.StepRequest (NX) is set, + * we can resume as if we were going to run + */ + res = xtensa_prepare_resume(target, current, address, false, false); if (res != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to prepare resume for single step"); return res; @@ -1459,18 +1884,15 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in target->state = TARGET_RUNNING; return ERROR_FAIL; } - target->debug_reason = DBG_REASON_SINGLESTEP; - target->state = TARGET_HALTED; xtensa_fetch_all_regs(target); - cur_pc = xtensa_reg_get(target, XT_REG_IDX_PC); LOG_TARGET_DEBUG(target, "cur_ps=%" PRIx32 ", cur_pc=%" PRIx32 " dbg_cause=%" PRIx32 " exc_cause=%" PRIx32, xtensa_reg_get(target, XT_REG_IDX_PS), cur_pc, - xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE), + xtensa_cause_get(target), xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE)); /* Do not step into WindowOverflow if ISRs are masked. @@ -1493,6 +1915,9 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in LOG_DEBUG("Stepped from %" PRIX32 " to %" PRIX32, oldpc, cur_pc); break; } while (true); + + target->debug_reason = DBG_REASON_SINGLESTEP; + target->state = TARGET_HALTED; LOG_DEBUG("Done stepping, PC=%" PRIX32, cur_pc); if (cause & DEBUGCAUSE_DB) { @@ -1503,12 +1928,12 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in } /* Restore int level */ - /* TODO: Theoretically, this can mess up stepping over an instruction that modifies - * ps.intlevel by itself. TODO: Look into this. */ - if (xtensa->stepping_isr_mode == XT_STEPPING_ISR_OFF) { - newps = xtensa_reg_get(target, XT_REG_IDX_PS); - newps = (newps & ~0xF) | (oldps & 0xf); - xtensa_reg_set(target, XT_REG_IDX_PS, newps); + if (ps_modified) { + LOG_DEBUG("Restoring %s after stepping: 0x%08" PRIx32, + xtensa->core_cache->reg_list[(xtensa->core_config->core_type == XT_LX) ? + xtensa->eps_dbglevel_idx : XT_REG_IDX_PS].name, oldps); + xtensa_reg_set(target, (xtensa->core_config->core_type == XT_LX) ? + xtensa->eps_dbglevel_idx : XT_REG_IDX_PS, oldps); } /* write ICOUNTLEVEL back to zero */ @@ -1519,9 +1944,15 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in return res; } -int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) +int xtensa_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints) { - return xtensa_do_step(target, current, address, handle_breakpoints); + int retval = xtensa_do_step(target, current, address, handle_breakpoints); + if (retval != ERROR_OK) + return retval; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + + return ERROR_OK; } /** @@ -1556,7 +1987,7 @@ static inline target_addr_t xtensa_get_overlap_size(target_addr_t r1_start, } /** - * Check if the address gets to memory regions, and it's access mode + * Check if the address gets to memory regions, and its access mode */ static bool xtensa_memory_op_validate_range(struct xtensa *xtensa, target_addr_t address, size_t size, int access) { @@ -1587,9 +2018,10 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si target_addr_t addrend_al = ALIGN_UP(address + size * count, 4); target_addr_t adr = addrstart_al; uint8_t *albuff; + bool bswap = xtensa->target->endianness == TARGET_BIG_ENDIAN; if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1601,39 +2033,62 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si } } - if (addrstart_al == address && addrend_al == address + (size * count)) { - albuff = buffer; - } else { - albuff = malloc(addrend_al - addrstart_al); - if (!albuff) { - LOG_TARGET_ERROR(target, "Out of memory allocating %" TARGET_PRIdADDR " bytes!", - addrend_al - addrstart_al); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + unsigned int alloc_bytes = ALIGN_UP(addrend_al - addrstart_al, sizeof(uint32_t)); + albuff = calloc(alloc_bytes, 1); + if (!albuff) { + LOG_TARGET_ERROR(target, "Out of memory allocating %" PRId64 " bytes!", + addrend_al - addrstart_al); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* We're going to use A3 here */ xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); /* Write start address to A3 */ - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); /* Now we can safely read data from addrstart_al up to addrend_al into albuff */ - for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) { - xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, &albuff[i]); + if (xtensa->probe_lsddr32p != 0) { + xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3)); + for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) + xtensa_queue_dbg_reg_read(xtensa, + (adr + sizeof(uint32_t) == addrend_al) ? XDMREG_DDR : XDMREG_DDREXEC, + &albuff[i]); + } else { + xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A4); + for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) { + xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A4, 0)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A4)); + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, &albuff[i]); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr + sizeof(uint32_t)); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + } } - int res = jtag_execute_queue(); - if (res == ERROR_OK) + int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res == ERROR_OK) { + bool prev_suppress = xtensa->suppress_dsr_errors; + xtensa->suppress_dsr_errors = true; res = xtensa_core_status_check(target); - if (res != ERROR_OK) - LOG_TARGET_WARNING(target, "Failed reading %d bytes at address " TARGET_ADDR_FMT, - count * size, address); - - if (albuff != buffer) { - memcpy(buffer, albuff + (address & 3), (size * count)); - free(albuff); + if (xtensa->probe_lsddr32p == -1) + xtensa->probe_lsddr32p = 1; + xtensa->suppress_dsr_errors = prev_suppress; + } + if (res != ERROR_OK) { + if (xtensa->probe_lsddr32p != 0) { + /* Disable fast memory access instructions and retry before reporting an error */ + LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P"); + xtensa->probe_lsddr32p = 0; + res = xtensa_read_memory(target, address, size, count, albuff); + bswap = false; + } else { + LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT, + count * size, address); + } } + if (bswap) + buf_bswap32(albuff, albuff, addrend_al - addrstart_al); + memcpy(buffer, albuff + (address & 3), (size * count)); + free(albuff); return res; } @@ -1659,9 +2114,10 @@ int xtensa_write_memory(struct target *target, target_addr_t adr = addrstart_al; int res; uint8_t *albuff; + bool fill_head_tail = false; if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1677,38 +2133,53 @@ int xtensa_write_memory(struct target *target, /* Allocate a temporary buffer to put the aligned bytes in, if needed. */ if (addrstart_al == address && addrend_al == address + (size * count)) { - /* We discard the const here because albuff can also be non-const */ - albuff = (uint8_t *)buffer; + if (xtensa->target->endianness == TARGET_BIG_ENDIAN) + /* Need a buffer for byte-swapping */ + albuff = malloc(addrend_al - addrstart_al); + else + /* We discard the const here because albuff can also be non-const */ + albuff = (uint8_t *)buffer; } else { + fill_head_tail = true; albuff = malloc(addrend_al - addrstart_al); - if (!albuff) { - LOG_TARGET_ERROR(target, "Out of memory allocating %" TARGET_PRIdADDR " bytes!", - addrend_al - addrstart_al); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + } + if (!albuff) { + LOG_TARGET_ERROR(target, "Out of memory allocating %" PRId64 " bytes!", + addrend_al - addrstart_al); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* We're going to use A3 here */ xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); /* If we're using a temp aligned buffer, we need to fill the head and/or tail bit of it. */ - if (albuff != buffer) { + if (fill_head_tail) { /* See if we need to read the first and/or last word. */ if (address & 3) { - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, &albuff[0]); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + if (xtensa->probe_lsddr32p == 1) { + xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3)); + } else { + xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A3, 0)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + } + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, &albuff[0]); } if ((address + (size * count)) & 3) { - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrend_al - 4); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); - xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(XT_REG_A3)); - xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrend_al - 4); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + if (xtensa->probe_lsddr32p == 1) { + xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3)); + } else { + xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A3, 0)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3)); + } + xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, &albuff[addrend_al - addrstart_al - 4]); } /* Grab bytes */ - res = jtag_execute_queue(); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) { LOG_ERROR("Error issuing unaligned memory write context instruction(s): %d", res); if (albuff != buffer) @@ -1716,24 +2187,116 @@ int xtensa_write_memory(struct target *target, return res; } xtensa_core_status_check(target); - /* Copy data to be written into the aligned buffer */ + if (xtensa->target->endianness == TARGET_BIG_ENDIAN) { + bool swapped_w0 = false; + if (address & 3) { + buf_bswap32(&albuff[0], &albuff[0], 4); + swapped_w0 = true; + } + if ((address + (size * count)) & 3) { + if ((addrend_al - addrstart_al - 4 == 0) && swapped_w0) { + /* Don't double-swap if buffer start/end are within the same word */ + } else { + buf_bswap32(&albuff[addrend_al - addrstart_al - 4], + &albuff[addrend_al - addrstart_al - 4], 4); + } + } + } + /* Copy data to be written into the aligned buffer (in host-endianness) */ memcpy(&albuff[address & 3], buffer, size * count); /* Now we can write albuff in aligned uint32s. */ } + if (xtensa->target->endianness == TARGET_BIG_ENDIAN) + buf_bswap32(albuff, fill_head_tail ? albuff : buffer, addrend_al - addrstart_al); + /* Write start address to A3 */ - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al); - xtensa_queue_exec_ins(xtensa, XT_INS_RSR(XT_SR_DDR, XT_REG_A3)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); /* Write the aligned buffer */ - for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) { - xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, buf_get_u32(&albuff[i], 0, 32)); - xtensa_queue_exec_ins(xtensa, XT_INS_SDDR32P(XT_REG_A3)); + if (xtensa->probe_lsddr32p != 0) { + for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) { + if (i == 0) { + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, buf_get_u32(&albuff[i], 0, 32)); + xtensa_queue_exec_ins(xtensa, XT_INS_SDDR32P(xtensa, XT_REG_A3)); + } else { + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDREXEC, buf_get_u32(&albuff[i], 0, 32)); + } + } + } else { + xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A4); + for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) { + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, buf_get_u32(&albuff[i], 0, 32)); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4)); + xtensa_queue_exec_ins(xtensa, XT_INS_S32I(xtensa, XT_REG_A3, XT_REG_A4, 0)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr + sizeof(uint32_t)); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + } } - res = jtag_execute_queue(); - if (res == ERROR_OK) + + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res == ERROR_OK) { + bool prev_suppress = xtensa->suppress_dsr_errors; + xtensa->suppress_dsr_errors = true; res = xtensa_core_status_check(target); - if (res != ERROR_OK) - LOG_TARGET_WARNING(target, "Failed writing %d bytes at address " TARGET_ADDR_FMT, count * size, address); + if (xtensa->probe_lsddr32p == -1) + xtensa->probe_lsddr32p = 1; + xtensa->suppress_dsr_errors = prev_suppress; + } + if (res != ERROR_OK) { + if (xtensa->probe_lsddr32p != 0) { + /* Disable fast memory access instructions and retry before reporting an error */ + LOG_TARGET_INFO(target, "Disabling LDDR32.P/SDDR32.P"); + xtensa->probe_lsddr32p = 0; + res = xtensa_write_memory(target, address, size, count, buffer); + } else { + LOG_TARGET_WARNING(target, "Failed writing %d bytes at address "TARGET_ADDR_FMT, + count * size, address); + } + } else { + /* Invalidate ICACHE, writeback DCACHE if present */ + bool issue_ihi = xtensa_is_icacheable(xtensa, address) && + xtensa_region_ar_exec(target, addrstart_al, addrend_al); + bool issue_dhwbi = xtensa_is_dcacheable(xtensa, address); + LOG_TARGET_DEBUG(target, "Cache OPs: IHI %d, DHWBI %d", issue_ihi, issue_dhwbi); + if (issue_ihi || issue_dhwbi) { + uint32_t ilinesize = issue_ihi ? xtensa->core_config->icache.line_size : UINT32_MAX; + uint32_t dlinesize = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX; + uint32_t linesize = MIN(ilinesize, dlinesize); + uint32_t off = 0; + adr = addrstart_al; + + while ((adr + off) < addrend_al) { + if (off == 0) { + /* Write start address to A3 */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + } + if (issue_ihi) + xtensa_queue_exec_ins(xtensa, XT_INS_IHI(xtensa, XT_REG_A3, off)); + if (issue_dhwbi) + xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, off)); + off += linesize; + if (off > 1020) { + /* IHI, DHWB have 8-bit immediate operands (0..1020) */ + adr += off; + off = 0; + } + } + + /* Execute cache WB/INV instructions */ + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) + LOG_TARGET_ERROR(target, + "Error queuing cache writeback/invaldate instruction(s): %d", + res); + res = xtensa_core_status_check(target); + if (res != ERROR_OK) + LOG_TARGET_ERROR(target, + "Error issuing cache writeback/invaldate instruction(s): %d", + res); + } + } if (albuff != buffer) free(albuff); @@ -1755,8 +2318,18 @@ int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_ int xtensa_poll(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); + if (xtensa_dm_poll(&xtensa->dbg_mod) != ERROR_OK) { + target->state = TARGET_UNKNOWN; + return ERROR_TARGET_NOT_EXAMINED; + } - int res = xtensa_dm_power_status_read(&xtensa->dbg_mod, PWRSTAT_DEBUGWASRESET | PWRSTAT_COREWASRESET); + int res = xtensa_dm_power_status_read(&xtensa->dbg_mod, PWRSTAT_DEBUGWASRESET(xtensa) | + PWRSTAT_COREWASRESET(xtensa)); + if (xtensa->dbg_mod.power_status.stat != xtensa->dbg_mod.power_status.stath) + LOG_TARGET_DEBUG(target, "PWRSTAT: read 0x%08" PRIx32 ", clear 0x%08lx, reread 0x%08" PRIx32, + xtensa->dbg_mod.power_status.stat, + PWRSTAT_DEBUGWASRESET(xtensa) | PWRSTAT_COREWASRESET(xtensa), + xtensa->dbg_mod.power_status.stath); if (res != ERROR_OK) return res; @@ -1774,10 +2347,16 @@ int xtensa_poll(struct target *target) if (res != ERROR_OK) return res; + uint32_t prev_dsr = xtensa->dbg_mod.core_status.dsr; res = xtensa_dm_core_status_read(&xtensa->dbg_mod); if (res != ERROR_OK) return res; - if (xtensa->dbg_mod.power_status.stath & PWRSTAT_COREWASRESET) { + if (prev_dsr != xtensa->dbg_mod.core_status.dsr) + LOG_TARGET_DEBUG(target, + "DSR has changed: was 0x%08" PRIx32 " now 0x%08" PRIx32, + prev_dsr, + xtensa->dbg_mod.core_status.dsr); + if (xtensa->dbg_mod.power_status.stath & PWRSTAT_COREWASRESET(xtensa)) { /* if RESET state is persitent */ target->state = TARGET_RESET; } else if (!xtensa_dm_is_powered(&xtensa->dbg_mod)) { @@ -1800,7 +2379,7 @@ int xtensa_poll(struct target *target) * priorities: watchpoint == breakpoint > single step > debug interrupt. */ /* Watchpoint and breakpoint events at the same time results in special * debug reason: DBG_REASON_WPTANDBKPT. */ - xtensa_reg_val_t halt_cause = xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE); + uint32_t halt_cause = xtensa_cause_get(target); /* TODO: Add handling of DBG_REASON_EXC_CATCH */ if (halt_cause & DEBUGCAUSE_IC) target->debug_reason = DBG_REASON_SINGLESTEP; @@ -1812,7 +2391,8 @@ int xtensa_poll(struct target *target) } else if (halt_cause & DEBUGCAUSE_DB) { target->debug_reason = DBG_REASON_WATCHPOINT; } - LOG_TARGET_DEBUG(target, "Target halted, pc=0x%08" PRIX32 ", debug_reason=%08x, oldstate=%08x", + LOG_TARGET_DEBUG(target, "Target halted, pc=0x%08" PRIx32 + ", debug_reason=%08" PRIx32 ", oldstate=%08" PRIx32, xtensa_reg_get(target, XT_REG_IDX_PC), target->debug_reason, oldstate); @@ -1820,13 +2400,27 @@ int xtensa_poll(struct target *target) halt_cause, xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE), xtensa->dbg_mod.core_status.dsr); - LOG_TARGET_INFO(target, "Target halted, PC=0x%08" PRIX32 ", debug_reason=%08x", - xtensa_reg_get(target, XT_REG_IDX_PC), target->debug_reason); xtensa_dm_core_status_clear( &xtensa->dbg_mod, OCDDSR_DEBUGPENDBREAK | OCDDSR_DEBUGINTBREAK | OCDDSR_DEBUGPENDTRAX | OCDDSR_DEBUGINTTRAX | OCDDSR_DEBUGPENDHOST | OCDDSR_DEBUGINTHOST); + if (xtensa->core_config->core_type == XT_NX) { + /* Enable imprecise exceptions while in halted state */ + xtensa_reg_val_t ps = xtensa_reg_get(target, XT_REG_IDX_PS); + xtensa_reg_val_t newps = ps & ~(XT_PS_DIEXC_MSK); + xtensa_mark_register_dirty(xtensa, XT_REG_IDX_PS); + LOG_TARGET_DEBUG(target, "Enabling PS.DIEXC: 0x%08x -> 0x%08x", ps, newps); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, newps); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_PS, XT_REG_A3)); + res = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (res != ERROR_OK) { + LOG_TARGET_ERROR(target, "Failed to write PS.DIEXC (%d)!", res); + return res; + } + xtensa_core_status_check(target); + } } } else { target->debug_reason = DBG_REASON_NOTHALTED; @@ -1855,25 +2449,103 @@ int xtensa_poll(struct target *target) return ERROR_OK; } +static int xtensa_update_instruction(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer) +{ + struct xtensa *xtensa = target_to_xtensa(target); + unsigned int issue_ihi = xtensa_is_icacheable(xtensa, address) && + xtensa_region_ar_exec(target, address, address + size); + unsigned int issue_dhwbi = xtensa_is_dcacheable(xtensa, address); + uint32_t icache_line_size = issue_ihi ? xtensa->core_config->icache.line_size : UINT32_MAX; + uint32_t dcache_line_size = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX; + unsigned int same_ic_line = ((address & (icache_line_size - 1)) + size) <= icache_line_size; + unsigned int same_dc_line = ((address & (dcache_line_size - 1)) + size) <= dcache_line_size; + int ret; + + if (size > icache_line_size) + return ERROR_FAIL; + + if (issue_ihi || issue_dhwbi) { + /* We're going to use A3 here */ + xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3); + + /* Write start address to A3 and invalidate */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + LOG_TARGET_DEBUG(target, "IHI %d, DHWBI %d for address " TARGET_ADDR_FMT, + issue_ihi, issue_dhwbi, address); + if (issue_dhwbi) { + xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, 0)); + if (!same_dc_line) { + LOG_TARGET_DEBUG(target, + "DHWBI second dcache line for address "TARGET_ADDR_FMT, + address + 4); + xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, 4)); + } + } + if (issue_ihi) { + xtensa_queue_exec_ins(xtensa, XT_INS_IHI(xtensa, XT_REG_A3, 0)); + if (!same_ic_line) { + LOG_TARGET_DEBUG(target, + "IHI second icache line for address "TARGET_ADDR_FMT, + address + 4); + xtensa_queue_exec_ins(xtensa, XT_INS_IHI(xtensa, XT_REG_A3, 4)); + } + } + + /* Execute invalidate instructions */ + ret = xtensa_dm_queue_execute(&xtensa->dbg_mod); + xtensa_core_status_check(target); + if (ret != ERROR_OK) { + LOG_ERROR("Error issuing cache invaldate instruction(s): %d", ret); + return ret; + } + } + + /* Write new instructions to memory */ + ret = target_write_buffer(target, address, size, buffer); + if (ret != ERROR_OK) { + LOG_TARGET_ERROR(target, "Error writing instruction to memory: %d", ret); + return ret; + } + + if (issue_dhwbi) { + /* Flush dcache so instruction propagates. A3 may be corrupted during memory write */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_DHWB(xtensa, XT_REG_A3, 0)); + LOG_DEBUG("DHWB dcache line for address "TARGET_ADDR_FMT, address); + if (!same_dc_line) { + LOG_TARGET_DEBUG(target, "DHWB second dcache line for address "TARGET_ADDR_FMT, address + 4); + xtensa_queue_exec_ins(xtensa, XT_INS_DHWB(xtensa, XT_REG_A3, 4)); + } + + /* Execute invalidate instructions */ + ret = xtensa_dm_queue_execute(&xtensa->dbg_mod); + xtensa_core_status_check(target); + } + + /* TODO: Handle L2 cache if present */ + return ret; +} + static int xtensa_sw_breakpoint_add(struct target *target, struct breakpoint *breakpoint, struct xtensa_sw_breakpoint *sw_bp) { + struct xtensa *xtensa = target_to_xtensa(target); int ret = target_read_buffer(target, breakpoint->address, XT_ISNS_SZ_MAX, sw_bp->insn); if (ret != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to read original instruction (%d)!", ret); return ret; } - sw_bp->insn_sz = xtensa_insn_size_get(buf_get_u32(sw_bp->insn, 0, 24)); + sw_bp->insn_sz = MIN(XT_ISNS_SZ_MAX, breakpoint->length); sw_bp->oocd_bp = breakpoint; - uint32_t break_insn = sw_bp->insn_sz == XT_ISNS_SZ_MAX ? XT_INS_BREAK(0, 0) : XT_INS_BREAKN(0); - /* convert to target endianness */ - uint8_t break_insn_buff[4]; - target_buffer_set_u32(target, break_insn_buff, break_insn); + uint32_t break_insn = sw_bp->insn_sz == XT_ISNS_SZ_MAX ? XT_INS_BREAK(xtensa, 0, 0) : XT_INS_BREAKN(xtensa, 0); - ret = target_write_buffer(target, breakpoint->address, sw_bp->insn_sz, break_insn_buff); + /* Underlying memory write will convert instruction endianness, don't do that here */ + ret = xtensa_update_instruction(target, breakpoint->address, sw_bp->insn_sz, (uint8_t *)&break_insn); if (ret != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to write breakpoint instruction (%d)!", ret); return ret; @@ -1884,9 +2556,9 @@ static int xtensa_sw_breakpoint_add(struct target *target, static int xtensa_sw_breakpoint_remove(struct target *target, struct xtensa_sw_breakpoint *sw_bp) { - int ret = target_write_buffer(target, sw_bp->oocd_bp->address, sw_bp->insn_sz, sw_bp->insn); + int ret = xtensa_update_instruction(target, sw_bp->oocd_bp->address, sw_bp->insn_sz, sw_bp->insn); if (ret != ERROR_OK) { - LOG_TARGET_ERROR(target, "Failed to read insn (%d)!", ret); + LOG_TARGET_ERROR(target, "Failed to write insn (%d)!", ret); return ret; } sw_bp->oocd_bp = NULL; @@ -1930,7 +2602,8 @@ int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint) xtensa->hw_brps[slot] = breakpoint; /* We will actually write the breakpoints when we resume the target. */ - LOG_TARGET_DEBUG(target, "placed HW breakpoint @ " TARGET_ADDR_FMT, + LOG_TARGET_DEBUG(target, "placed HW breakpoint %u @ " TARGET_ADDR_FMT, + slot, breakpoint->address); return ERROR_OK; @@ -1968,6 +2641,8 @@ int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoin return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } xtensa->hw_brps[slot] = NULL; + if (xtensa->core_config->core_type == XT_NX) + xtensa_reg_set(target, xtensa->nx_reg_idx[XT_NX_REG_IDX_IBREAKC0] + slot, 0); LOG_TARGET_DEBUG(target, "cleared HW breakpoint %u @ " TARGET_ADDR_FMT, slot, breakpoint->address); return ERROR_OK; } @@ -1979,11 +2654,11 @@ int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint) xtensa_reg_val_t dbreakcval; if (target->state != TARGET_HALTED) { - LOG_TARGET_WARNING(target, "target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - if (watchpoint->mask != ~(uint32_t)0) { + if (watchpoint->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) { LOG_TARGET_ERROR(target, "watchpoint value masks not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2048,10 +2723,238 @@ int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoin return ERROR_OK; } +int xtensa_start_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + void *arch_info) +{ + struct xtensa *xtensa = target_to_xtensa(target); + struct xtensa_algorithm *algorithm_info = arch_info; + int retval = ERROR_OK; + bool usr_ps = false; + uint32_t newps; + + /* NOTE: xtensa_run_algorithm requires that each algorithm uses a software breakpoint + * at the exit point */ + + if (target->state != TARGET_HALTED) { + LOG_WARNING("Target not halted!"); + return ERROR_TARGET_NOT_HALTED; + } + + for (unsigned int i = 0; i < xtensa->core_cache->num_regs; i++) { + struct reg *reg = &xtensa->core_cache->reg_list[i]; + buf_cpy(reg->value, xtensa->algo_context_backup[i], reg->size); + } + /* save debug reason, it will be changed */ + if (!algorithm_info) { + LOG_ERROR("BUG: arch_info not specified"); + return ERROR_FAIL; + } + algorithm_info->ctx_debug_reason = target->debug_reason; + if (xtensa->core_config->core_type == XT_LX) { + /* save PS and set to debug_level - 1 */ + algorithm_info->ctx_ps = xtensa_reg_get(target, xtensa->eps_dbglevel_idx); + newps = (algorithm_info->ctx_ps & ~0xf) | (xtensa->core_config->debug.irq_level - 1); + xtensa_reg_set(target, xtensa->eps_dbglevel_idx, newps); + } + /* write mem params */ + for (int i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction != PARAM_IN) { + retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) + return retval; + } + } + /* write reg params */ + for (int i = 0; i < num_reg_params; i++) { + if (reg_params[i].size > 32) { + LOG_ERROR("BUG: not supported register size (%d)", reg_params[i].size); + return ERROR_FAIL; + } + struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0); + if (!reg) { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + return ERROR_FAIL; + } + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + return ERROR_FAIL; + } + if (memcmp(reg_params[i].reg_name, "ps", 3)) { + usr_ps = true; + } else if (xtensa->core_config->core_type == XT_LX) { + unsigned int reg_id = xtensa->eps_dbglevel_idx; + assert(reg_id < xtensa->core_cache->num_regs && "Attempt to access non-existing reg!"); + reg = &xtensa->core_cache->reg_list[reg_id]; + } + xtensa_reg_set_value(reg, buf_get_u32(reg_params[i].value, 0, reg->size)); + reg->valid = 1; + } + /* ignore custom core mode if custom PS value is specified */ + if (!usr_ps && xtensa->core_config->core_type == XT_LX) { + unsigned int eps_reg_idx = xtensa->eps_dbglevel_idx; + xtensa_reg_val_t ps = xtensa_reg_get(target, eps_reg_idx); + enum xtensa_mode core_mode = XT_PS_RING_GET(ps); + if (algorithm_info->core_mode != XT_MODE_ANY && algorithm_info->core_mode != core_mode) { + LOG_DEBUG("setting core_mode: 0x%x", algorithm_info->core_mode); + xtensa_reg_val_t new_ps = (ps & ~XT_PS_RING_MSK) | XT_PS_RING(algorithm_info->core_mode); + /* save previous core mode */ + /* TODO: core_mode is not restored for now. Can be added to the end of wait_algorithm */ + algorithm_info->core_mode = core_mode; + xtensa_reg_set(target, eps_reg_idx, new_ps); + xtensa->core_cache->reg_list[eps_reg_idx].valid = 1; + } + } + + return xtensa_resume(target, false, entry_point, true, true); +} + +/** Waits for an algorithm in the target. */ +int xtensa_wait_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t exit_point, unsigned int timeout_ms, + void *arch_info) +{ + struct xtensa *xtensa = target_to_xtensa(target); + struct xtensa_algorithm *algorithm_info = arch_info; + int retval = ERROR_OK; + xtensa_reg_val_t pc; + + /* NOTE: xtensa_run_algorithm requires that each algorithm uses a software breakpoint + * at the exit point */ + + retval = target_wait_state(target, TARGET_HALTED, timeout_ms); + /* If the target fails to halt due to the breakpoint, force a halt */ + if (retval != ERROR_OK || target->state != TARGET_HALTED) { + retval = target_halt(target); + if (retval != ERROR_OK) + return retval; + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval != ERROR_OK) + return retval; + LOG_TARGET_ERROR(target, "not halted %d, pc 0x%" PRIx32 ", ps 0x%" PRIx32, retval, + xtensa_reg_get(target, XT_REG_IDX_PC), + xtensa_reg_get(target, (xtensa->core_config->core_type == XT_LX) ? + xtensa->eps_dbglevel_idx : XT_REG_IDX_PS)); + return ERROR_TARGET_TIMEOUT; + } + pc = xtensa_reg_get(target, XT_REG_IDX_PC); + if (exit_point && pc != exit_point) { + LOG_ERROR("failed algorithm halted at 0x%" PRIx32 ", expected " TARGET_ADDR_FMT, pc, exit_point); + return ERROR_TARGET_TIMEOUT; + } + /* Copy core register values to reg_params[] */ + for (int i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { + struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0); + if (!reg) { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + return ERROR_FAIL; + } + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + return ERROR_FAIL; + } + buf_set_u32(reg_params[i].value, 0, 32, xtensa_reg_get_value(reg)); + } + } + /* Read memory values to mem_params */ + LOG_DEBUG("Read mem params"); + for (int i = 0; i < num_mem_params; i++) { + LOG_DEBUG("Check mem param @ " TARGET_ADDR_FMT, mem_params[i].address); + if (mem_params[i].direction != PARAM_OUT) { + LOG_DEBUG("Read mem param @ " TARGET_ADDR_FMT, mem_params[i].address); + retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); + if (retval != ERROR_OK) + return retval; + } + } + + /* avoid gdb keep_alive warning */ + keep_alive(); + + for (int i = xtensa->core_cache->num_regs - 1; i >= 0; i--) { + struct reg *reg = &xtensa->core_cache->reg_list[i]; + if (i == XT_REG_IDX_PS) { + continue; /* restore mapped reg number of PS depends on NDEBUGLEVEL */ + } else if (i == XT_REG_IDX_DEBUGCAUSE) { + /*FIXME: restoring DEBUGCAUSE causes exception when executing corresponding + * instruction in DIR */ + LOG_DEBUG("Skip restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32, + xtensa->core_cache->reg_list[i].name, + buf_get_u32(reg->value, 0, 32), + buf_get_u32(xtensa->algo_context_backup[i], 0, 32)); + buf_cpy(xtensa->algo_context_backup[i], reg->value, reg->size); + xtensa->core_cache->reg_list[i].dirty = 0; + xtensa->core_cache->reg_list[i].valid = 0; + } else if (memcmp(xtensa->algo_context_backup[i], reg->value, reg->size / 8)) { + if (reg->size <= 32) { + LOG_DEBUG("restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32, + xtensa->core_cache->reg_list[i].name, + buf_get_u32(reg->value, 0, reg->size), + buf_get_u32(xtensa->algo_context_backup[i], 0, reg->size)); + } else if (reg->size <= 64) { + LOG_DEBUG("restoring register %s: 0x%8.8" PRIx64 " -> 0x%8.8" PRIx64, + xtensa->core_cache->reg_list[i].name, + buf_get_u64(reg->value, 0, reg->size), + buf_get_u64(xtensa->algo_context_backup[i], 0, reg->size)); + } else { + LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size); + } + buf_cpy(xtensa->algo_context_backup[i], reg->value, reg->size); + xtensa->core_cache->reg_list[i].dirty = 1; + xtensa->core_cache->reg_list[i].valid = 1; + } + } + target->debug_reason = algorithm_info->ctx_debug_reason; + if (xtensa->core_config->core_type == XT_LX) + xtensa_reg_set(target, xtensa->eps_dbglevel_idx, algorithm_info->ctx_ps); + + retval = xtensa_write_dirty_registers(target); + if (retval != ERROR_OK) + LOG_ERROR("Failed to write dirty regs (%d)!", retval); + + return retval; +} + +int xtensa_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + unsigned int timeout_ms, void *arch_info) +{ + int retval = xtensa_start_algorithm(target, + num_mem_params, mem_params, + num_reg_params, reg_params, + entry_point, exit_point, + arch_info); + + if (retval == ERROR_OK) { + retval = xtensa_wait_algorithm(target, + num_mem_params, mem_params, + num_reg_params, reg_params, + exit_point, timeout_ms, + arch_info); + } + + return retval; +} + static int xtensa_build_reg_cache(struct target *target) { struct xtensa *xtensa = target_to_xtensa(target); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + unsigned int last_dbreg_num = 0; + + if (xtensa->core_regs_num + xtensa->num_optregs != xtensa->total_regs_num) + LOG_TARGET_WARNING(target, "Register count MISMATCH: %d core regs, %d extended regs; %d expected", + xtensa->core_regs_num, xtensa->num_optregs, xtensa->total_regs_num); + struct reg_cache *reg_cache = calloc(1, sizeof(struct reg_cache)); if (!reg_cache) { @@ -2060,86 +2963,107 @@ static int xtensa_build_reg_cache(struct target *target) } reg_cache->name = "Xtensa registers"; reg_cache->next = NULL; - reg_cache->num_regs = XT_NUM_REGS + xtensa->core_config->user_regs_num; /* Init reglist */ - struct reg *reg_list = calloc(reg_cache->num_regs, sizeof(struct reg)); + unsigned int reg_list_size = XT_NUM_REGS + xtensa->num_optregs; + struct reg *reg_list = calloc(reg_list_size, sizeof(struct reg)); if (!reg_list) { LOG_ERROR("Failed to alloc reg list!"); goto fail; } - xtensa->regs_num = 0; - - for (unsigned int i = 0; i < XT_NUM_REGS; i++) { - reg_list[i].exist = false; - if (xtensa_regs[i].type == XT_REG_USER) { - if (xtensa_user_reg_exists(xtensa, i)) - reg_list[i].exist = true; - else - LOG_DEBUG("User reg '%s' (%d) does not exist", xtensa_regs[i].name, i); - } else if (xtensa_regs[i].type == XT_REG_FR) { - if (xtensa_fp_reg_exists(xtensa, i)) - reg_list[i].exist = true; - else - LOG_DEBUG("FP reg '%s' (%d) does not exist", xtensa_regs[i].name, i); - } else if (xtensa_regs[i].type == XT_REG_SPECIAL) { - if (xtensa_special_reg_exists(xtensa, i)) - reg_list[i].exist = true; - else - LOG_DEBUG("Special reg '%s' (%d) does not exist", xtensa_regs[i].name, i); - } else { - if (xtensa_regular_reg_exists(xtensa, i)) - reg_list[i].exist = true; - else - LOG_DEBUG("Regular reg '%s' (%d) does not exist", xtensa_regs[i].name, i); - } - reg_list[i].name = xtensa_regs[i].name; - reg_list[i].size = 32; - reg_list[i].value = calloc(1, 4 /*XT_REG_LEN*/);/* make Clang Static Analyzer happy */ - if (!reg_list[i].value) { - LOG_ERROR("Failed to alloc reg list value!"); + xtensa->dbregs_num = 0; + unsigned int didx = 0; + for (unsigned int whichlist = 0; whichlist < 2; whichlist++) { + struct xtensa_reg_desc *rlist = (whichlist == 0) ? xtensa_regs : xtensa->optregs; + unsigned int listsize = (whichlist == 0) ? XT_NUM_REGS : xtensa->num_optregs; + for (unsigned int i = 0; i < listsize; i++, didx++) { + reg_list[didx].exist = rlist[i].exist; + reg_list[didx].name = rlist[i].name; + reg_list[didx].size = 32; + reg_list[didx].value = calloc(1, 4 /*XT_REG_LEN*/); /* make Clang Static Analyzer happy */ + if (!reg_list[didx].value) { + LOG_ERROR("Failed to alloc reg list value!"); + goto fail; + } + reg_list[didx].dirty = false; + reg_list[didx].valid = false; + reg_list[didx].type = &xtensa_reg_type; + reg_list[didx].arch_info = xtensa; + if (rlist[i].exist && (rlist[i].dbreg_num > last_dbreg_num)) + last_dbreg_num = rlist[i].dbreg_num; + + if (xtensa_extra_debug_log) { + LOG_TARGET_DEBUG(target, + "POPULATE %-16s list %d exist %d, idx %d, type %d, dbreg_num 0x%04x", + reg_list[didx].name, + whichlist, + reg_list[didx].exist, + didx, + rlist[i].type, + rlist[i].dbreg_num); + } + } + } + + xtensa->dbregs_num = last_dbreg_num + 1; + reg_cache->reg_list = reg_list; + reg_cache->num_regs = reg_list_size; + + LOG_TARGET_DEBUG(target, "xtensa->total_regs_num %d reg_list_size %d xtensa->dbregs_num %d", + xtensa->total_regs_num, reg_list_size, xtensa->dbregs_num); + + /* Construct empty-register list for handling unknown register requests */ + xtensa->empty_regs = calloc(xtensa->dbregs_num, sizeof(struct reg)); + if (!xtensa->empty_regs) { + LOG_TARGET_ERROR(target, "Out of memory"); + goto fail; + } + for (unsigned int i = 0; i < xtensa->dbregs_num; i++) { + xtensa->empty_regs[i].name = calloc(8, sizeof(char)); + if (!xtensa->empty_regs[i].name) { + LOG_TARGET_ERROR(target, "Out of memory"); goto fail; } - reg_list[i].dirty = false; - reg_list[i].valid = false; - reg_list[i].type = &xtensa_reg_type; - reg_list[i].arch_info = xtensa; - if (reg_list[i].exist) - xtensa->regs_num++; - } - for (unsigned int i = 0; i < xtensa->core_config->user_regs_num; i++) { - reg_list[XT_USR_REG_START + i].exist = true; - reg_list[XT_USR_REG_START + i].name = xtensa->core_config->user_regs[i].name; - reg_list[XT_USR_REG_START + i].size = xtensa->core_config->user_regs[i].size; - reg_list[XT_USR_REG_START + i].value = calloc(1, reg_list[XT_USR_REG_START + i].size / 8); - if (!reg_list[XT_USR_REG_START + i].value) { - LOG_ERROR("Failed to alloc user reg list value!"); + sprintf((char *)xtensa->empty_regs[i].name, "?0x%04x", i & 0x0000FFFF); + xtensa->empty_regs[i].size = 32; + xtensa->empty_regs[i].type = &xtensa_reg_type; + xtensa->empty_regs[i].value = calloc(1, 4 /*XT_REG_LEN*/); /* make Clang Static Analyzer happy */ + if (!xtensa->empty_regs[i].value) { + LOG_ERROR("Failed to alloc empty reg list value!"); goto fail; } - reg_list[XT_USR_REG_START + i].dirty = false; - reg_list[XT_USR_REG_START + i].valid = false; - reg_list[XT_USR_REG_START + i].type = xtensa->core_config->user_regs[i].type; - reg_list[XT_USR_REG_START + i].arch_info = xtensa; - xtensa->regs_num++; - } - if (xtensa->core_config->gdb_general_regs_num >= xtensa->regs_num) { - LOG_ERROR("Regs number less then GDB general regs number!"); - goto fail; + xtensa->empty_regs[i].arch_info = xtensa; } - /* assign GDB reg numbers to registers */ - for (unsigned int gdb_reg_id = 0; gdb_reg_id < xtensa->regs_num; gdb_reg_id++) { - unsigned int reg_id = xtensa->core_config->gdb_regs_mapping[gdb_reg_id]; - if (reg_id >= reg_cache->num_regs) { - LOG_ERROR("Invalid GDB map!"); + /* Construct contiguous register list from contiguous descriptor list */ + if (xtensa->regmap_contiguous && xtensa->contiguous_regs_desc) { + xtensa->contiguous_regs_list = calloc(xtensa->total_regs_num, sizeof(struct reg *)); + if (!xtensa->contiguous_regs_list) { + LOG_TARGET_ERROR(target, "Out of memory"); goto fail; } - if (!reg_list[reg_id].exist) { - LOG_ERROR("Non-existing reg in GDB map!"); - goto fail; + for (unsigned int i = 0; i < xtensa->total_regs_num; i++) { + unsigned int j; + for (j = 0; j < reg_cache->num_regs; j++) { + if (!strcmp(reg_cache->reg_list[j].name, xtensa->contiguous_regs_desc[i]->name)) { + /* Register number field is not filled above. + Here we are assigning the corresponding index from the contiguous reg list. + These indexes are in the same order with gdb g-packet request/response. + Some more changes may be required for sparse reg lists. + */ + reg_cache->reg_list[j].number = i; + xtensa->contiguous_regs_list[i] = &(reg_cache->reg_list[j]); + LOG_TARGET_DEBUG(target, + "POPULATE contiguous regs list: %-16s, dbreg_num 0x%04x", + xtensa->contiguous_regs_list[i]->name, + xtensa->contiguous_regs_desc[i]->dbreg_num); + break; + } + } + if (j == reg_cache->num_regs) + LOG_TARGET_WARNING(target, "contiguous register %s not found", + xtensa->contiguous_regs_desc[i]->name); } - reg_list[reg_id].number = gdb_reg_id; } - reg_cache->reg_list = reg_list; xtensa->algo_context_backup = calloc(reg_cache->num_regs, sizeof(void *)); if (!xtensa->algo_context_backup) { @@ -2154,7 +3078,6 @@ static int xtensa_build_reg_cache(struct target *target) goto fail; } } - xtensa->core_cache = reg_cache; if (cache_p) *cache_p = reg_cache; @@ -2162,35 +3085,343 @@ static int xtensa_build_reg_cache(struct target *target) fail: if (reg_list) { - for (unsigned int i = 0; i < reg_cache->num_regs; i++) + for (unsigned int i = 0; i < reg_list_size; i++) free(reg_list[i].value); free(reg_list); } + if (xtensa->empty_regs) { + for (unsigned int i = 0; i < xtensa->dbregs_num; i++) { + free((void *)xtensa->empty_regs[i].name); + free(xtensa->empty_regs[i].value); + } + free(xtensa->empty_regs); + } if (xtensa->algo_context_backup) { for (unsigned int i = 0; i < reg_cache->num_regs; i++) free(xtensa->algo_context_backup[i]); free(xtensa->algo_context_backup); } - free(reg_cache); + free(reg_cache); + + return ERROR_FAIL; +} + +static int32_t xtensa_gdbqc_parse_exec_tie_ops(struct target *target, char *opstr) +{ + struct xtensa *xtensa = target_to_xtensa(target); + int32_t status = ERROR_COMMAND_ARGUMENT_INVALID; + /* Process op[] list */ + while (opstr && (*opstr == ':')) { + uint8_t ops[32]; + unsigned int oplen = strtoul(opstr + 1, &opstr, 16); + if (oplen > 32) { + LOG_TARGET_ERROR(target, "TIE access instruction too long (%d)\n", oplen); + break; + } + unsigned int i = 0; + while ((i < oplen) && opstr && (*opstr == ':')) + ops[i++] = strtoul(opstr + 1, &opstr, 16); + if (i != oplen) { + LOG_TARGET_ERROR(target, "TIE access instruction malformed (%d)\n", i); + break; + } + + char insn_buf[128]; + sprintf(insn_buf, "Exec %d-byte TIE sequence: ", oplen); + for (i = 0; i < oplen; i++) + sprintf(insn_buf + strlen(insn_buf), "%02x:", ops[i]); + LOG_TARGET_DEBUG(target, "%s", insn_buf); + xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */ + status = ERROR_OK; + } + return status; +} + +static int xtensa_gdbqc_qxtreg(struct target *target, const char *packet, char **response_p) +{ + struct xtensa *xtensa = target_to_xtensa(target); + bool iswrite = (packet[0] == 'Q'); + enum xtensa_qerr_e error; + + /* Read/write TIE register. Requires spill location. + * qxtreg<num>:<len>:<oplen>:<op[0]>:<...>[:<oplen>:<op[0]>:<...>] + * Qxtreg<num>:<len>:<oplen>:<op[0]>:<...>[:<oplen>:<op[0]>:<...>]=<value> + */ + if (!(xtensa->spill_buf)) { + LOG_ERROR("Spill location not specified. Try 'target remote <host>:3333 &spill_location0'"); + error = XT_QERR_FAIL; + goto xtensa_gdbqc_qxtreg_fail; + } + + char *delim; + uint32_t regnum = strtoul(packet + 6, &delim, 16); + if (*delim != ':') { + LOG_ERROR("Malformed qxtreg packet"); + error = XT_QERR_INVAL; + goto xtensa_gdbqc_qxtreg_fail; + } + uint32_t reglen = strtoul(delim + 1, &delim, 16); + if (*delim != ':') { + LOG_ERROR("Malformed qxtreg packet"); + error = XT_QERR_INVAL; + goto xtensa_gdbqc_qxtreg_fail; + } + uint8_t regbuf[XT_QUERYPKT_RESP_MAX]; + memset(regbuf, 0, XT_QUERYPKT_RESP_MAX); + LOG_DEBUG("TIE reg 0x%08" PRIx32 " %s (%d bytes)", regnum, iswrite ? "write" : "read", reglen); + if (reglen * 2 + 1 > XT_QUERYPKT_RESP_MAX) { + LOG_ERROR("TIE register too large"); + error = XT_QERR_MEM; + goto xtensa_gdbqc_qxtreg_fail; + } + + /* (1) Save spill memory, (1.5) [if write then store value to spill location], + * (2) read old a4, (3) write spill address to a4. + * NOTE: ensure a4 is restored properly by all error handling logic + */ + unsigned int memop_size = (xtensa->spill_loc & 3) ? 1 : 4; + int status = xtensa_read_memory(target, xtensa->spill_loc, memop_size, + xtensa->spill_bytes / memop_size, xtensa->spill_buf); + if (status != ERROR_OK) { + LOG_ERROR("Spill memory save"); + error = XT_QERR_MEM; + goto xtensa_gdbqc_qxtreg_fail; + } + if (iswrite) { + /* Extract value and store in spill memory */ + unsigned int b = 0; + char *valbuf = strchr(delim, '='); + if (!(valbuf && (*valbuf == '='))) { + LOG_ERROR("Malformed Qxtreg packet"); + error = XT_QERR_INVAL; + goto xtensa_gdbqc_qxtreg_fail; + } + valbuf++; + while (*valbuf && *(valbuf + 1)) { + char bytestr[3] = { 0, 0, 0 }; + strncpy(bytestr, valbuf, 2); + regbuf[b++] = strtoul(bytestr, NULL, 16); + valbuf += 2; + } + if (b != reglen) { + LOG_ERROR("Malformed Qxtreg packet"); + error = XT_QERR_INVAL; + goto xtensa_gdbqc_qxtreg_fail; + } + status = xtensa_write_memory(target, xtensa->spill_loc, memop_size, + reglen / memop_size, regbuf); + if (status != ERROR_OK) { + LOG_ERROR("TIE value store"); + error = XT_QERR_MEM; + goto xtensa_gdbqc_qxtreg_fail; + } + } + xtensa_reg_val_t orig_a4 = xtensa_reg_get(target, XT_REG_IDX_A4); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, xtensa->spill_loc); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4)); + + int32_t tieop_status = xtensa_gdbqc_parse_exec_tie_ops(target, delim); + + /* Restore a4 but not yet spill memory. Execute it all... */ + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, orig_a4); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4)); + status = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (status != ERROR_OK) { + LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status); + tieop_status = status; + } + status = xtensa_core_status_check(target); + if (status != ERROR_OK) { + LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status); + tieop_status = status; + } + + if (tieop_status == ERROR_OK) { + if (iswrite) { + /* TIE write succeeded; send OK */ + strcpy(*response_p, "OK"); + } else { + /* TIE read succeeded; copy result from spill memory */ + status = xtensa_read_memory(target, xtensa->spill_loc, memop_size, reglen, regbuf); + if (status != ERROR_OK) { + LOG_TARGET_ERROR(target, "TIE result read"); + tieop_status = status; + } + unsigned int i; + for (i = 0; i < reglen; i++) + sprintf(*response_p + 2 * i, "%02x", regbuf[i]); + *(*response_p + 2 * i) = '\0'; + LOG_TARGET_DEBUG(target, "TIE response: %s", *response_p); + } + } + + /* Restore spill memory first, then report any previous errors */ + status = xtensa_write_memory(target, xtensa->spill_loc, memop_size, + xtensa->spill_bytes / memop_size, xtensa->spill_buf); + if (status != ERROR_OK) { + LOG_ERROR("Spill memory restore"); + error = XT_QERR_MEM; + goto xtensa_gdbqc_qxtreg_fail; + } + if (tieop_status != ERROR_OK) { + LOG_ERROR("TIE execution"); + error = XT_QERR_FAIL; + goto xtensa_gdbqc_qxtreg_fail; + } + return ERROR_OK; + +xtensa_gdbqc_qxtreg_fail: + strcpy(*response_p, xt_qerr[error].chrval); + return xt_qerr[error].intval; +} + +int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p) +{ + struct xtensa *xtensa = target_to_xtensa(target); + enum xtensa_qerr_e error; + if (!packet || !response_p) { + LOG_TARGET_ERROR(target, "invalid parameter: packet %p response_p %p", packet, response_p); + return ERROR_FAIL; + } + + *response_p = xtensa->qpkt_resp; + if (strncmp(packet, "qxtn", 4) == 0) { + strcpy(*response_p, "OpenOCD"); + return ERROR_OK; + } else if (strncasecmp(packet, "qxtgdbversion=", 14) == 0) { + return ERROR_OK; + } else if ((strncmp(packet, "Qxtsis=", 7) == 0) || (strncmp(packet, "Qxtsds=", 7) == 0)) { + /* Confirm host cache params match core .cfg file */ + struct xtensa_cache_config *cachep = (packet[4] == 'i') ? + &xtensa->core_config->icache : &xtensa->core_config->dcache; + unsigned int line_size = 0, size = 0, way_count = 0; + sscanf(&packet[7], "%x,%x,%x", &line_size, &size, &way_count); + if ((cachep->line_size != line_size) || + (cachep->size != size) || + (cachep->way_count != way_count)) { + LOG_TARGET_WARNING(target, "%cCache mismatch; check xtensa-core-XXX.cfg file", + cachep == &xtensa->core_config->icache ? 'I' : 'D'); + } + strcpy(*response_p, "OK"); + return ERROR_OK; + } else if ((strncmp(packet, "Qxtiram=", 8) == 0) || (strncmp(packet, "Qxtirom=", 8) == 0)) { + /* Confirm host IRAM/IROM params match core .cfg file */ + struct xtensa_local_mem_config *memp = (packet[5] == 'a') ? + &xtensa->core_config->iram : &xtensa->core_config->irom; + unsigned int base = 0, size = 0, i; + char *pkt = (char *)&packet[7]; + do { + pkt++; + size = strtoul(pkt, &pkt, 16); + pkt++; + base = strtoul(pkt, &pkt, 16); + LOG_TARGET_DEBUG(target, "memcheck: %dB @ 0x%08x", size, base); + for (i = 0; i < memp->count; i++) { + if ((memp->regions[i].base == base) && (memp->regions[i].size == size)) + break; + } + if (i == memp->count) { + LOG_TARGET_WARNING(target, "%s mismatch; check xtensa-core-XXX.cfg file", + memp == &xtensa->core_config->iram ? "IRAM" : "IROM"); + break; + } + for (i = 0; i < 11; i++) { + pkt++; + strtoul(pkt, &pkt, 16); + } + } while (pkt && (pkt[0] == ',')); + strcpy(*response_p, "OK"); + return ERROR_OK; + } else if (strncmp(packet, "Qxtexcmlvl=", 11) == 0) { + /* Confirm host EXCM_LEVEL matches core .cfg file */ + unsigned int excm_level = strtoul(&packet[11], NULL, 0); + if (!xtensa->core_config->high_irq.enabled || + (excm_level != xtensa->core_config->high_irq.excm_level)) + LOG_TARGET_WARNING(target, "EXCM_LEVEL mismatch; check xtensa-core-XXX.cfg file"); + strcpy(*response_p, "OK"); + return ERROR_OK; + } else if ((strncmp(packet, "Qxtl2cs=", 8) == 0) || + (strncmp(packet, "Qxtl2ca=", 8) == 0) || + (strncmp(packet, "Qxtdensity=", 11) == 0)) { + strcpy(*response_p, "OK"); + return ERROR_OK; + } else if (strncmp(packet, "Qxtspill=", 9) == 0) { + char *delim; + uint32_t spill_loc = strtoul(packet + 9, &delim, 16); + if (*delim != ':') { + LOG_ERROR("Malformed Qxtspill packet"); + error = XT_QERR_INVAL; + goto xtensa_gdb_query_custom_fail; + } + xtensa->spill_loc = spill_loc; + xtensa->spill_bytes = strtoul(delim + 1, NULL, 16); + if (xtensa->spill_buf) + free(xtensa->spill_buf); + xtensa->spill_buf = calloc(1, xtensa->spill_bytes); + if (!xtensa->spill_buf) { + LOG_ERROR("Spill buf alloc"); + error = XT_QERR_MEM; + goto xtensa_gdb_query_custom_fail; + } + LOG_TARGET_DEBUG(target, "Set spill 0x%08" PRIx32 " (%d)", xtensa->spill_loc, xtensa->spill_bytes); + strcpy(*response_p, "OK"); + return ERROR_OK; + } else if (strncasecmp(packet, "qxtreg", 6) == 0) { + return xtensa_gdbqc_qxtreg(target, packet, response_p); + } else if ((strncmp(packet, "qTStatus", 8) == 0) || + (strncmp(packet, "qxtftie", 7) == 0) || + (strncmp(packet, "qxtstie", 7) == 0)) { + /* Return empty string to indicate trace, TIE wire debug are unsupported */ + strcpy(*response_p, ""); + return ERROR_OK; + } - return ERROR_FAIL; + /* Warn for all other queries, but do not return errors */ + LOG_TARGET_WARNING(target, "Unknown target-specific query packet: %s", packet); + strcpy(*response_p, ""); + return ERROR_OK; + +xtensa_gdb_query_custom_fail: + strcpy(*response_p, xt_qerr[error].chrval); + return xt_qerr[error].intval; } int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, - const struct xtensa_config *xtensa_config, const struct xtensa_debug_module_config *dm_cfg) { target->arch_info = xtensa; xtensa->common_magic = XTENSA_COMMON_MAGIC; xtensa->target = target; - xtensa->core_config = xtensa_config; xtensa->stepping_isr_mode = XT_STEPPING_ISR_ON; - if (!xtensa->core_config->exc.enabled || !xtensa->core_config->irq.enabled || - !xtensa->core_config->high_irq.enabled || !xtensa->core_config->debug.enabled) { - LOG_ERROR("Xtensa configuration does not support debugging!"); + xtensa->core_config = calloc(1, sizeof(struct xtensa_config)); + if (!xtensa->core_config) { + LOG_ERROR("Xtensa configuration alloc failed\n"); return ERROR_FAIL; } + + /* Default cache settings are disabled with 1 way */ + xtensa->core_config->icache.way_count = 1; + xtensa->core_config->dcache.way_count = 1; + + /* chrval: AR3/AR4 register names will change with window mapping. + * intval: tracks whether scratch register was set through gdb P packet. + */ + for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) { + xtensa->scratch_ars[s].chrval = calloc(8, sizeof(char)); + if (!xtensa->scratch_ars[s].chrval) { + for (enum xtensa_ar_scratch_set_e f = 0; f < s; f++) + free(xtensa->scratch_ars[f].chrval); + free(xtensa->core_config); + LOG_ERROR("Xtensa scratch AR alloc failed\n"); + return ERROR_FAIL; + } + xtensa->scratch_ars[s].intval = false; + sprintf(xtensa->scratch_ars[s].chrval, "%s%d", + ((s == XT_AR_SCRATCH_A3) || (s == XT_AR_SCRATCH_A4)) ? "a" : "ar", + ((s == XT_AR_SCRATCH_A3) || (s == XT_AR_SCRATCH_AR3)) ? 3 : 4); + } + return xtensa_dm_init(&xtensa->dbg_mod, dm_cfg); } @@ -2204,12 +3435,12 @@ int xtensa_target_init(struct command_context *cmd_ctx, struct target *target) struct xtensa *xtensa = target_to_xtensa(target); xtensa->come_online_probes_num = 3; - xtensa->hw_brps = calloc(xtensa->core_config->debug.ibreaks_num, sizeof(struct breakpoint *)); + xtensa->hw_brps = calloc(XT_HW_IBREAK_MAX_NUM, sizeof(struct breakpoint *)); if (!xtensa->hw_brps) { LOG_ERROR("Failed to alloc memory for HW breakpoints!"); return ERROR_FAIL; } - xtensa->hw_wps = calloc(xtensa->core_config->debug.dbreaks_num, sizeof(struct watchpoint *)); + xtensa->hw_wps = calloc(XT_HW_DBREAK_MAX_NUM, sizeof(struct watchpoint *)); if (!xtensa->hw_wps) { free(xtensa->hw_brps); LOG_ERROR("Failed to alloc memory for HW watchpoints!"); @@ -2223,6 +3454,11 @@ int xtensa_target_init(struct command_context *cmd_ctx, struct target *target) return ERROR_FAIL; } + xtensa->spill_loc = 0xffffffff; + xtensa->spill_bytes = 0; + xtensa->spill_buf = NULL; + xtensa->probe_lsddr32p = -1; /* Probe for fast load/store operations */ + return xtensa_build_reg_cache(target); } @@ -2243,6 +3479,21 @@ static void xtensa_free_reg_cache(struct target *target) } xtensa->core_cache = NULL; xtensa->algo_context_backup = NULL; + + if (xtensa->empty_regs) { + for (unsigned int i = 0; i < xtensa->dbregs_num; i++) { + free((void *)xtensa->empty_regs[i].name); + free(xtensa->empty_regs[i].value); + } + free(xtensa->empty_regs); + } + xtensa->empty_regs = NULL; + if (xtensa->optregs) { + for (unsigned int i = 0; i < xtensa->num_optregs; i++) + free((void *)xtensa->optregs[i].name); + free(xtensa->optregs); + } + xtensa->optregs = NULL; } void xtensa_target_deinit(struct target *target) @@ -2252,29 +3503,579 @@ void xtensa_target_deinit(struct target *target) LOG_DEBUG("start"); if (target_was_examined(target)) { - int ret = xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRCLR, OCDDCR_ENABLEOCD); + int ret = xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRCLR, OCDDCR_ENABLEOCD); if (ret != ERROR_OK) { LOG_ERROR("Failed to queue OCDDCR_ENABLEOCD clear operation!"); return; } xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod); - ret = jtag_execute_queue(); + ret = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (ret != ERROR_OK) { LOG_ERROR("Failed to clear OCDDCR_ENABLEOCD!"); return; } + xtensa_dm_deinit(&xtensa->dbg_mod); } xtensa_free_reg_cache(target); free(xtensa->hw_brps); free(xtensa->hw_wps); free(xtensa->sw_brps); + if (xtensa->spill_buf) { + free(xtensa->spill_buf); + xtensa->spill_buf = NULL; + } + for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) + free(xtensa->scratch_ars[s].chrval); + free(xtensa->core_config); } -const char *xtensa_get_gdb_arch(struct target *target) +const char *xtensa_get_gdb_arch(const struct target *target) { return "xtensa"; } +/* exe <ascii-encoded hexadecimal instruction bytes> */ +static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* Process ascii-encoded hex byte string */ + const char *parm = CMD_ARGV[0]; + unsigned int parm_len = strlen(parm); + if ((parm_len >= 64) || (parm_len & 1)) { + command_print(CMD, "Invalid parameter length (%d): must be even, < 64 characters", parm_len); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + uint8_t ops[32]; + memset(ops, 0, 32); + unsigned int oplen = parm_len / 2; + char encoded_byte[3] = { 0, 0, 0 }; + for (unsigned int i = 0; i < oplen; i++) { + encoded_byte[0] = *parm++; + encoded_byte[1] = *parm++; + ops[i] = strtoul(encoded_byte, NULL, 16); + } + + /* GDB must handle state save/restore. + * Flush reg cache in case spill location is in an AR + * Update CPENABLE only for this execution; later restore cached copy + * Keep a copy of exccause in case executed code triggers an exception + */ + int status = xtensa_write_dirty_registers(target); + if (status != ERROR_OK) { + command_print(CMD, "%s: Failed to write back register cache.", target_name(target)); + return ERROR_FAIL; + } + xtensa_reg_val_t exccause = xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE); + xtensa_reg_val_t cpenable = xtensa_reg_get(target, XT_REG_IDX_CPENABLE); + xtensa_reg_val_t a3 = xtensa_reg_get(target, XT_REG_IDX_A3); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, 0xffffffff); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, + xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3)); + xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, a3); + xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3)); + + /* Queue instruction list and execute everything */ + LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]); + xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */ + status = xtensa_dm_queue_execute(&xtensa->dbg_mod); + if (status != ERROR_OK) { + command_print(CMD, "exec: queue error %d", status); + } else { + status = xtensa_core_status_check(target); + if (status != ERROR_OK) + command_print(CMD, "exec: status error %d", status); + } + + /* Reread register cache and restore saved regs after instruction execution */ + if (xtensa_fetch_all_regs(target) != ERROR_OK) + command_print(CMD, "post-exec: register fetch error"); + if (status != ERROR_OK) { + command_print(CMD, "post-exec: EXCCAUSE 0x%02" PRIx32, + xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE)); + } + xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause); + xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable); + return status; +} + +COMMAND_HANDLER(xtensa_cmd_exe) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_exe_do, get_current_target(CMD_CTX)); +} + +/* xtdef <name> */ +COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + const char *core_name = CMD_ARGV[0]; + if (strcasecmp(core_name, "LX") == 0) { + xtensa->core_config->core_type = XT_LX; + } else if (strcasecmp(core_name, "NX") == 0) { + xtensa->core_config->core_type = XT_NX; + } else { + command_print(CMD, "xtdef [LX|NX]\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtdef) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +static inline bool xtensa_cmd_xtopt_legal_val(char *opt, int val, int min, int max) +{ + if ((val < min) || (val > max)) { + LOG_ERROR("xtopt %s (%d) out of range [%d..%d]\n", opt, val, min, max); + return false; + } + return true; +} + +/* xtopt <name> <value> */ +COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + const char *opt_name = CMD_ARGV[0]; + int opt_val = strtol(CMD_ARGV[1], NULL, 0); + if (strcasecmp(opt_name, "arnum") == 0) { + if (!xtensa_cmd_xtopt_legal_val("arnum", opt_val, 0, 64)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->aregs_num = opt_val; + } else if (strcasecmp(opt_name, "windowed") == 0) { + if (!xtensa_cmd_xtopt_legal_val("windowed", opt_val, 0, 1)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->windowed = opt_val; + } else if (strcasecmp(opt_name, "cpenable") == 0) { + if (!xtensa_cmd_xtopt_legal_val("cpenable", opt_val, 0, 1)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->coproc = opt_val; + } else if (strcasecmp(opt_name, "exceptions") == 0) { + if (!xtensa_cmd_xtopt_legal_val("exceptions", opt_val, 0, 1)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->exceptions = opt_val; + } else if (strcasecmp(opt_name, "intnum") == 0) { + if (!xtensa_cmd_xtopt_legal_val("intnum", opt_val, 0, 32)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->irq.enabled = (opt_val > 0); + xtensa->core_config->irq.irq_num = opt_val; + } else if (strcasecmp(opt_name, "hipriints") == 0) { + if (!xtensa_cmd_xtopt_legal_val("hipriints", opt_val, 0, 1)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->high_irq.enabled = opt_val; + } else if (strcasecmp(opt_name, "excmlevel") == 0) { + if (!xtensa_cmd_xtopt_legal_val("excmlevel", opt_val, 1, 6)) + return ERROR_COMMAND_ARGUMENT_INVALID; + if (!xtensa->core_config->high_irq.enabled) { + command_print(CMD, "xtopt excmlevel requires hipriints\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + xtensa->core_config->high_irq.excm_level = opt_val; + } else if (strcasecmp(opt_name, "intlevels") == 0) { + if (xtensa->core_config->core_type == XT_LX) { + if (!xtensa_cmd_xtopt_legal_val("intlevels", opt_val, 2, 6)) + return ERROR_COMMAND_ARGUMENT_INVALID; + } else { + if (!xtensa_cmd_xtopt_legal_val("intlevels", opt_val, 1, 255)) + return ERROR_COMMAND_ARGUMENT_INVALID; + } + if (!xtensa->core_config->high_irq.enabled) { + command_print(CMD, "xtopt intlevels requires hipriints\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + xtensa->core_config->high_irq.level_num = opt_val; + } else if (strcasecmp(opt_name, "debuglevel") == 0) { + if (xtensa->core_config->core_type == XT_LX) { + if (!xtensa_cmd_xtopt_legal_val("debuglevel", opt_val, 2, 6)) + return ERROR_COMMAND_ARGUMENT_INVALID; + } else { + if (!xtensa_cmd_xtopt_legal_val("debuglevel", opt_val, 0, 0)) + return ERROR_COMMAND_ARGUMENT_INVALID; + } + xtensa->core_config->debug.enabled = 1; + xtensa->core_config->debug.irq_level = opt_val; + } else if (strcasecmp(opt_name, "ibreaknum") == 0) { + if (!xtensa_cmd_xtopt_legal_val("ibreaknum", opt_val, 0, 2)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->debug.ibreaks_num = opt_val; + } else if (strcasecmp(opt_name, "dbreaknum") == 0) { + if (!xtensa_cmd_xtopt_legal_val("dbreaknum", opt_val, 0, 2)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->debug.dbreaks_num = opt_val; + } else if (strcasecmp(opt_name, "tracemem") == 0) { + if (!xtensa_cmd_xtopt_legal_val("tracemem", opt_val, 0, 256 * 1024)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->trace.mem_sz = opt_val; + xtensa->core_config->trace.enabled = (opt_val > 0); + } else if (strcasecmp(opt_name, "tracememrev") == 0) { + if (!xtensa_cmd_xtopt_legal_val("tracememrev", opt_val, 0, 1)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->trace.reversed_mem_access = opt_val; + } else if (strcasecmp(opt_name, "perfcount") == 0) { + if (!xtensa_cmd_xtopt_legal_val("perfcount", opt_val, 0, 8)) + return ERROR_COMMAND_ARGUMENT_INVALID; + xtensa->core_config->debug.perfcount_num = opt_val; + } else { + LOG_WARNING("Unknown xtensa command ignored: \"xtopt %s %s\"", CMD_ARGV[0], CMD_ARGV[1]); + return ERROR_OK; + } + + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtopt) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +/* xtmem <type> [parameters] */ +COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa) +{ + struct xtensa_cache_config *cachep = NULL; + struct xtensa_local_mem_config *memp = NULL; + int mem_access = 0; + bool is_dcache = false; + + if (CMD_ARGC == 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + const char *mem_name = CMD_ARGV[0]; + if (strcasecmp(mem_name, "icache") == 0) { + cachep = &xtensa->core_config->icache; + } else if (strcasecmp(mem_name, "dcache") == 0) { + cachep = &xtensa->core_config->dcache; + is_dcache = true; + } else if (strcasecmp(mem_name, "l2cache") == 0) { + /* TODO: support L2 cache */ + } else if (strcasecmp(mem_name, "l2addr") == 0) { + /* TODO: support L2 cache */ + } else if (strcasecmp(mem_name, "iram") == 0) { + memp = &xtensa->core_config->iram; + mem_access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE; + } else if (strcasecmp(mem_name, "dram") == 0) { + memp = &xtensa->core_config->dram; + mem_access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE; + } else if (strcasecmp(mem_name, "sram") == 0) { + memp = &xtensa->core_config->sram; + mem_access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE; + } else if (strcasecmp(mem_name, "irom") == 0) { + memp = &xtensa->core_config->irom; + mem_access = XT_MEM_ACCESS_READ; + } else if (strcasecmp(mem_name, "drom") == 0) { + memp = &xtensa->core_config->drom; + mem_access = XT_MEM_ACCESS_READ; + } else if (strcasecmp(mem_name, "srom") == 0) { + memp = &xtensa->core_config->srom; + mem_access = XT_MEM_ACCESS_READ; + } else { + command_print(CMD, "xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + if (cachep) { + if (CMD_ARGC != 4 && CMD_ARGC != 5) + return ERROR_COMMAND_SYNTAX_ERROR; + cachep->line_size = strtoul(CMD_ARGV[1], NULL, 0); + cachep->size = strtoul(CMD_ARGV[2], NULL, 0); + cachep->way_count = strtoul(CMD_ARGV[3], NULL, 0); + cachep->writeback = ((CMD_ARGC == 5) && is_dcache) ? + strtoul(CMD_ARGV[4], NULL, 0) : 0; + } else if (memp) { + if (CMD_ARGC != 3) + return ERROR_COMMAND_SYNTAX_ERROR; + struct xtensa_local_mem_region_config *memcfgp = &memp->regions[memp->count]; + memcfgp->base = strtoul(CMD_ARGV[1], NULL, 0); + memcfgp->size = strtoul(CMD_ARGV[2], NULL, 0); + memcfgp->access = mem_access; + memp->count++; + } + + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtmem) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +/* xtmpu <num FG seg> <min seg size> <lockable> <executeonly> */ +COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa) +{ + if (CMD_ARGC != 4) + return ERROR_COMMAND_SYNTAX_ERROR; + + unsigned int nfgseg = strtoul(CMD_ARGV[0], NULL, 0); + unsigned int minsegsize = strtoul(CMD_ARGV[1], NULL, 0); + unsigned int lockable = strtoul(CMD_ARGV[2], NULL, 0); + unsigned int execonly = strtoul(CMD_ARGV[3], NULL, 0); + + if ((nfgseg > 32)) { + command_print(CMD, "<nfgseg> must be within [0..32]\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } else if (minsegsize & (minsegsize - 1)) { + command_print(CMD, "<minsegsize> must be a power of 2 >= 32\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } else if (lockable > 1) { + command_print(CMD, "<lockable> must be 0 or 1\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } else if (execonly > 1) { + command_print(CMD, "<execonly> must be 0 or 1\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + xtensa->core_config->mpu.enabled = true; + xtensa->core_config->mpu.nfgseg = nfgseg; + xtensa->core_config->mpu.minsegsize = minsegsize; + xtensa->core_config->mpu.lockable = lockable; + xtensa->core_config->mpu.execonly = execonly; + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtmpu) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +/* xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56> */ +COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa) +{ + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + unsigned int nirefillentries = strtoul(CMD_ARGV[0], NULL, 0); + unsigned int ndrefillentries = strtoul(CMD_ARGV[1], NULL, 0); + if ((nirefillentries != 16) && (nirefillentries != 32)) { + command_print(CMD, "<nirefillentries> must be 16 or 32\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } else if ((ndrefillentries != 16) && (ndrefillentries != 32)) { + command_print(CMD, "<ndrefillentries> must be 16 or 32\n"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + xtensa->core_config->mmu.enabled = true; + xtensa->core_config->mmu.itlb_entries_count = nirefillentries; + xtensa->core_config->mmu.dtlb_entries_count = ndrefillentries; + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtmmu) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +/* xtregs <numregs> + * xtreg <regname> <regnum> */ +COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa) +{ + if (CMD_ARGC == 1) { + int32_t numregs = strtoul(CMD_ARGV[0], NULL, 0); + if ((numregs <= 0) || (numregs > UINT16_MAX)) { + command_print(CMD, "xtreg <numregs>: Invalid 'numregs' (%d)", numregs); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + if ((xtensa->genpkt_regs_num > 0) && (numregs < (int32_t)xtensa->genpkt_regs_num)) { + command_print(CMD, "xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)", + numregs, xtensa->genpkt_regs_num); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + xtensa->total_regs_num = numregs; + xtensa->core_regs_num = 0; + xtensa->num_optregs = 0; + /* A little more memory than required, but saves a second initialization pass */ + xtensa->optregs = calloc(xtensa->total_regs_num, sizeof(struct xtensa_reg_desc)); + if (!xtensa->optregs) { + LOG_ERROR("Failed to allocate xtensa->optregs!"); + return ERROR_FAIL; + } + return ERROR_OK; + } else if (CMD_ARGC != 2) { + return ERROR_COMMAND_SYNTAX_ERROR; + } + + /* "xtregfmt contiguous" must be specified prior to the first "xtreg" definition + * if general register (g-packet) requests or contiguous register maps are supported */ + if (xtensa->regmap_contiguous && !xtensa->contiguous_regs_desc) { + xtensa->contiguous_regs_desc = calloc(xtensa->total_regs_num, sizeof(struct xtensa_reg_desc *)); + if (!xtensa->contiguous_regs_desc) { + LOG_ERROR("Failed to allocate xtensa->contiguous_regs_desc!"); + return ERROR_FAIL; + } + } + + const char *regname = CMD_ARGV[0]; + unsigned int regnum = strtoul(CMD_ARGV[1], NULL, 0); + if (regnum > UINT16_MAX) { + command_print(CMD, "<regnum> must be a 16-bit number"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + if ((xtensa->num_optregs + xtensa->core_regs_num) >= xtensa->total_regs_num) { + if (xtensa->total_regs_num) + command_print(CMD, "'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)", + regname, regnum, + xtensa->total_regs_num, xtensa->core_regs_num, xtensa->num_optregs); + else + command_print(CMD, "'xtreg %s 0x%04x': Number of registers unspecified", + regname, regnum); + return ERROR_FAIL; + } + + /* Determine whether register belongs in xtensa_regs[] or xtensa->xtensa_spec_regs[] */ + struct xtensa_reg_desc *rptr = &xtensa->optregs[xtensa->num_optregs]; + bool is_extended_reg = true; + unsigned int ridx; + for (ridx = 0; ridx < XT_NUM_REGS; ridx++) { + if (strcmp(CMD_ARGV[0], xtensa_regs[ridx].name) == 0) { + /* Flag core register as defined */ + rptr = &xtensa_regs[ridx]; + xtensa->core_regs_num++; + is_extended_reg = false; + break; + } + } + + rptr->exist = true; + if (is_extended_reg) { + /* Register ID, debugger-visible register ID */ + rptr->name = strdup(CMD_ARGV[0]); + rptr->dbreg_num = regnum; + rptr->reg_num = (regnum & XT_REG_INDEX_MASK); + xtensa->num_optregs++; + + /* Register type */ + if ((regnum & XT_REG_GENERAL_MASK) == XT_REG_GENERAL_VAL) { + rptr->type = XT_REG_GENERAL; + } else if ((regnum & XT_REG_USER_MASK) == XT_REG_USER_VAL) { + rptr->type = XT_REG_USER; + } else if ((regnum & XT_REG_FR_MASK) == XT_REG_FR_VAL) { + rptr->type = XT_REG_FR; + } else if ((regnum & XT_REG_SPECIAL_MASK) == XT_REG_SPECIAL_VAL) { + rptr->type = XT_REG_SPECIAL; + } else if ((regnum & XT_REG_RELGEN_MASK) == XT_REG_RELGEN_VAL) { + /* WARNING: For these registers, regnum points to the + * index of the corresponding ARx registers, NOT to + * the processor register number! */ + rptr->type = XT_REG_RELGEN; + rptr->reg_num += XT_REG_IDX_ARFIRST; + rptr->dbreg_num += XT_REG_IDX_ARFIRST; + } else if ((regnum & XT_REG_TIE_MASK) != 0) { + rptr->type = XT_REG_TIE; + } else { + rptr->type = XT_REG_OTHER; + } + + /* Register flags: includes intsetN, intclearN for LX8 */ + if ((strcmp(rptr->name, "mmid") == 0) || (strcmp(rptr->name, "eraccess") == 0) || + (strcmp(rptr->name, "ddr") == 0) || (strncmp(rptr->name, "intset", 6) == 0) || + (strncmp(rptr->name, "intclear", 8) == 0) || (strcmp(rptr->name, "mesrclr") == 0)) + rptr->flags = XT_REGF_NOREAD; + else + rptr->flags = 0; + + if (rptr->reg_num == (XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level) && + xtensa->core_config->core_type == XT_LX && rptr->type == XT_REG_SPECIAL) { + xtensa->eps_dbglevel_idx = XT_NUM_REGS + xtensa->num_optregs - 1; + LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx); + } + if (xtensa->core_config->core_type == XT_NX) { + enum xtensa_nx_reg_idx idx = XT_NX_REG_IDX_NUM; + if (strcmp(rptr->name, "ibreakc0") == 0) + idx = XT_NX_REG_IDX_IBREAKC0; + else if (strcmp(rptr->name, "wb") == 0) + idx = XT_NX_REG_IDX_WB; + else if (strcmp(rptr->name, "ms") == 0) + idx = XT_NX_REG_IDX_MS; + else if (strcmp(rptr->name, "ievec") == 0) + idx = XT_NX_REG_IDX_IEVEC; + else if (strcmp(rptr->name, "ieextern") == 0) + idx = XT_NX_REG_IDX_IEEXTERN; + else if (strcmp(rptr->name, "mesr") == 0) + idx = XT_NX_REG_IDX_MESR; + else if (strcmp(rptr->name, "mesrclr") == 0) + idx = XT_NX_REG_IDX_MESRCLR; + if (idx < XT_NX_REG_IDX_NUM) { + if (xtensa->nx_reg_idx[idx] != 0) { + command_print(CMD, "nx_reg_idx[%d] previously set to %d", + idx, xtensa->nx_reg_idx[idx]); + return ERROR_FAIL; + } + xtensa->nx_reg_idx[idx] = XT_NUM_REGS + xtensa->num_optregs - 1; + LOG_DEBUG("NX reg %s: index %d (%d)", + rptr->name, xtensa->nx_reg_idx[idx], idx); + } + } + } else if (strcmp(rptr->name, "cpenable") == 0) { + xtensa->core_config->coproc = true; + } + + /* Build out list of contiguous registers in specified order */ + unsigned int running_reg_count = xtensa->num_optregs + xtensa->core_regs_num; + if (xtensa->contiguous_regs_desc) { + assert((running_reg_count <= xtensa->total_regs_num) && "contiguous register address internal error!"); + xtensa->contiguous_regs_desc[running_reg_count - 1] = rptr; + } + if (xtensa_extra_debug_log) + LOG_DEBUG("Added %s register %-16s: 0x%04x/0x%02x t%d (%d of %d)", + is_extended_reg ? "config-specific" : "core", + rptr->name, rptr->dbreg_num, rptr->reg_num, rptr->type, + is_extended_reg ? xtensa->num_optregs : ridx, + is_extended_reg ? xtensa->total_regs_num : XT_NUM_REGS); + return ERROR_OK; +} + +COMMAND_HANDLER(xtensa_cmd_xtreg) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + +/* xtregfmt <contiguous|sparse> [numgregs] */ +COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa) +{ + if ((CMD_ARGC == 1) || (CMD_ARGC == 2)) { + if (!strcasecmp(CMD_ARGV[0], "sparse")) { + return ERROR_OK; + } else if (!strcasecmp(CMD_ARGV[0], "contiguous")) { + xtensa->regmap_contiguous = true; + if (CMD_ARGC == 2) { + unsigned int numgregs = strtoul(CMD_ARGV[1], NULL, 0); + if ((numgregs <= 0) || + ((numgregs > xtensa->total_regs_num) && + (xtensa->total_regs_num > 0))) { + command_print(CMD, "xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)", + numgregs, xtensa->total_regs_num); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + xtensa->genpkt_regs_num = numgregs; + } + return ERROR_OK; + } + } + return ERROR_COMMAND_SYNTAX_ERROR; +} + +COMMAND_HANDLER(xtensa_cmd_xtregfmt) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa) { return CALL_COMMAND_HANDLER(handle_command_parse_bool, @@ -2375,7 +4176,7 @@ COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa) "%-12" PRIu64 "%s", result.value, result.overflow ? " (overflow)" : ""); - LOG_INFO("%s", result_buf); + command_print(CMD, "%s", result_buf); } return ERROR_OK; @@ -2403,6 +4204,7 @@ COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa) command_print(CMD, "Current ISR step mode: %s", st); return ERROR_OK; } + /* Masking is ON -> interrupts during stepping are OFF, and vice versa */ if (!strcasecmp(CMD_ARGV[0], "off")) state = XT_STEPPING_ISR_ON; @@ -2425,7 +4227,7 @@ COMMAND_HANDLER(xtensa_cmd_mask_interrupts) COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target) { - int res = ERROR_OK; + int res; uint32_t val = 0; if (CMD_ARGC >= 1) { @@ -2458,16 +4260,15 @@ COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target) } else { struct xtensa *xtensa = target_to_xtensa(target); res = xtensa_smpbreak_read(xtensa, &val); - if (res == ERROR_OK) { + if (res == ERROR_OK) command_print(CMD, "Current bits set:%s%s%s%s", (val & OCDDCR_BREAKINEN) ? " BreakIn" : "", (val & OCDDCR_BREAKOUTEN) ? " BreakOut" : "", (val & OCDDCR_RUNSTALLINEN) ? " RunStallIn" : "", (val & OCDDCR_DEBUGMODEOUTEN) ? " DebugModeOut" : "" ); - } else { + else command_print(CMD, "Failed to get smpbreak config %d", res); - } } return res; } @@ -2478,6 +4279,38 @@ COMMAND_HANDLER(xtensa_cmd_smpbreak) get_current_target(CMD_CTX)); } +COMMAND_HELPER(xtensa_cmd_dm_rw_do, struct xtensa *xtensa) +{ + if (CMD_ARGC == 1) { + // read: xtensa dm addr + uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0); + uint32_t val; + int res = xtensa_dm_read(&xtensa->dbg_mod, addr, &val); + if (res == ERROR_OK) + command_print(CMD, "xtensa DM(0x%08" PRIx32 ") -> 0x%08" PRIx32, addr, val); + else + command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : read ERROR %" PRId32, addr, res); + return res; + } else if (CMD_ARGC == 2) { + // write: xtensa dm addr value + uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0); + uint32_t val = strtoul(CMD_ARGV[1], NULL, 0); + int res = xtensa_dm_write(&xtensa->dbg_mod, addr, val); + if (res == ERROR_OK) + command_print(CMD, "xtensa DM(0x%08" PRIx32 ") <- 0x%08" PRIx32, addr, val); + else + command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : write ERROR %" PRId32, addr, res); + return res; + } + return ERROR_COMMAND_SYNTAX_ERROR; +} + +COMMAND_HANDLER(xtensa_cmd_dm_rw) +{ + return CALL_COMMAND_HANDLER(xtensa_cmd_dm_rw_do, + target_to_xtensa(get_current_target(CMD_CTX))); +} + COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa) { struct xtensa_trace_status trace_status; @@ -2588,21 +4421,21 @@ COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname } memsz = trace_config.memaddr_end - trace_config.memaddr_start + 1; - LOG_INFO("Total trace memory: %d words", memsz); + command_print(CMD, "Total trace memory: %d words", memsz); if ((trace_config.addr & ((TRAXADDR_TWRAP_MASK << TRAXADDR_TWRAP_SHIFT) | TRAXADDR_TWSAT)) == 0) { /*Memory hasn't overwritten itself yet. */ wmem = trace_config.addr & TRAXADDR_TADDR_MASK; - LOG_INFO("...but trace is only %d words", wmem); + command_print(CMD, "...but trace is only %d words", wmem); if (wmem < memsz) memsz = wmem; } else { if (trace_config.addr & TRAXADDR_TWSAT) { - LOG_INFO("Real trace is many times longer than that (overflow)"); + command_print(CMD, "Real trace is many times longer than that (overflow)"); } else { uint32_t trc_sz = (trace_config.addr >> TRAXADDR_TWRAP_SHIFT) & TRAXADDR_TWRAP_MASK; trc_sz = (trc_sz * memsz) + (trace_config.addr & TRAXADDR_TADDR_MASK); - LOG_INFO("Real trace is %d words, but the start has been truncated.", trc_sz); + command_print(CMD, "Real trace is %d words, but the start has been truncated.", trc_sz); } } @@ -2656,12 +4489,68 @@ COMMAND_HANDLER(xtensa_cmd_tracedump) target_to_xtensa(get_current_target(CMD_CTX)), CMD_ARGV[0]); } -const struct command_registration xtensa_command_handlers[] = { +static const struct command_registration xtensa_any_command_handlers[] = { + { + .name = "xtdef", + .handler = xtensa_cmd_xtdef, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa core type", + .usage = "<type>", + }, + { + .name = "xtopt", + .handler = xtensa_cmd_xtopt, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa core option", + .usage = "<name> <value>", + }, + { + .name = "xtmem", + .handler = xtensa_cmd_xtmem, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa memory/cache option", + .usage = "<type> [parameters]", + }, + { + .name = "xtmmu", + .handler = xtensa_cmd_xtmmu, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa MMU option", + .usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>", + }, + { + .name = "xtmpu", + .handler = xtensa_cmd_xtmpu, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa MPU option", + .usage = "<num FG seg> <min seg size> <lockable> <executeonly>", + }, + { + .name = "xtreg", + .handler = xtensa_cmd_xtreg, + .mode = COMMAND_CONFIG, + .help = "Configure Xtensa register", + .usage = "<regname> <regnum>", + }, + { + .name = "xtregs", + .handler = xtensa_cmd_xtreg, + .mode = COMMAND_CONFIG, + .help = "Configure number of Xtensa registers", + .usage = "<numregs>", + }, + { + .name = "xtregfmt", + .handler = xtensa_cmd_xtregfmt, + .mode = COMMAND_CONFIG, + .help = "Configure format of Xtensa register map", + .usage = "<contiguous|sparse> [numgregs]", + }, { .name = "set_permissive", .handler = xtensa_cmd_permissive_mode, .mode = COMMAND_ANY, - .help = "When set to 1, enable Xtensa permissive mode (less client-side checks)", + .help = "When set to 1, enable Xtensa permissive mode (fewer client-side checks)", .usage = "[0|1]", }, { @@ -2676,8 +4565,14 @@ const struct command_registration xtensa_command_handlers[] = { .handler = xtensa_cmd_smpbreak, .mode = COMMAND_ANY, .help = "Set the way the CPU chains OCD breaks", - .usage = - "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]", + .usage = "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]", + }, + { + .name = "dm", + .handler = xtensa_cmd_dm_rw, + .mode = COMMAND_ANY, + .help = "Xtensa DM read/write", + .usage = "addr [value]" }, { .name = "perfmon_enable", @@ -2690,8 +4585,7 @@ const struct command_registration xtensa_command_handlers[] = { .name = "perfmon_dump", .handler = xtensa_cmd_perfmon_dump, .mode = COMMAND_EXEC, - .help = - "Dump performance counter value. If no argument specified, dumps all counters.", + .help = "Dump performance counter value. If no argument specified, dumps all counters.", .usage = "[counter_id]", }, { @@ -2716,5 +4610,23 @@ const struct command_registration xtensa_command_handlers[] = { .help = "Tracing: Dump trace memory to a files. One file per core.", .usage = "<outfile>", }, + { + .name = "exe", + .handler = xtensa_cmd_exe, + .mode = COMMAND_ANY, + .help = "Xtensa stub execution", + .usage = "<ascii-encoded hexadecimal instruction bytes>", + }, + COMMAND_REGISTRATION_DONE +}; + +const struct command_registration xtensa_command_handlers[] = { + { + .name = "xtensa", + .mode = COMMAND_ANY, + .help = "Xtensa command group", + .usage = "", + .chain = xtensa_any_command_handlers, + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h index 86b6a9c9b3..a920f77cdf 100644 --- a/src/target/xtensa/xtensa.h +++ b/src/target/xtensa/xtensa.h @@ -2,8 +2,8 @@ /*************************************************************************** * Generic Xtensa target * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * * Copyright (C) 2019 Espressif Systems Ltd. * - * Author: Alexey Gerenkov <alexey@espressif.com> * ***************************************************************************/ #ifndef OPENOCD_TARGET_XTENSA_H @@ -20,41 +20,105 @@ * Holds the interface to Xtensa cores. */ -#define XT_ISNS_SZ_MAX 3 - -#define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6) -#define XT_PS_RING_MSK (0x3 << 6) -#define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3) -#define XT_PS_CALLINC_MSK (0x3 << 16) -#define XT_PS_OWB_MSK (0xF << 8) - -#define XT_LOCAL_MEM_REGIONS_NUM_MAX 8 +/* Big-endian vs. little-endian detection */ +#define XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN) + +/* 24-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */ +#define XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4)) +#define XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF)) +#define XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T)) + +/* 16-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */ +#define XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8)) +#define XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12)) +#define XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4)) + +#define XT_ISNS_SZ_MAX 3 + +/* PS register bits (LX) */ +#define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6) +#define XT_PS_RING_MSK (0x3 << 6) +#define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3) +#define XT_PS_CALLINC_MSK (0x3 << 16) +#define XT_PS_OWB_MSK (0xF << 8) +#define XT_PS_WOE_MSK BIT(18) + +/* PS register bits (NX) */ +#define XT_PS_DIEXC_MSK BIT(2) +#define XT_PS_DI_MSK BIT(3) + +/* MS register bits (NX) */ +#define XT_MS_DE_MSK BIT(5) +#define XT_MS_DISPST_MSK (0x1f) +#define XT_MS_DISPST_DBG (0x10) + +/* WB register bits (NX) */ +#define XT_WB_P_SHIFT (0) +#define XT_WB_P_MSK (0x7U << XT_WB_P_SHIFT) +#define XT_WB_C_SHIFT (4) +#define XT_WB_C_MSK (0x7U << XT_WB_C_SHIFT) +#define XT_WB_N_SHIFT (8) +#define XT_WB_N_MSK (0x7U << XT_WB_N_SHIFT) +#define XT_WB_S_SHIFT (30) +#define XT_WB_S_MSK (0x3U << XT_WB_S_SHIFT) + +/* IBREAKC register bits (NX) */ +#define XT_IBREAKC_FB (0x80000000) + +/* Definitions for imprecise exception registers (NX) */ +#define XT_IMPR_EXC_MSK (0x00000013) +#define XT_MESRCLR_IMPR_EXC_MSK (0x00000090) + +#define XT_LOCAL_MEM_REGIONS_NUM_MAX 8 + +#define XT_AREGS_NUM_MAX 64 +#define XT_USER_REGS_NUM_MAX 256 + +#define XT_MEM_ACCESS_NONE 0x0 +#define XT_MEM_ACCESS_READ 0x1 +#define XT_MEM_ACCESS_WRITE 0x2 + +#define XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */ +#define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1) + +enum xtensa_qerr_e { + XT_QERR_INTERNAL = 0, + XT_QERR_FAIL, + XT_QERR_INVAL, + XT_QERR_MEM, + XT_QERR_NUM, +}; -#define XT_AREGS_NUM_MAX 64 -#define XT_USER_REGS_NUM_MAX 256 +/* An and ARn registers potentially used as scratch regs */ +enum xtensa_ar_scratch_set_e { + XT_AR_SCRATCH_A3 = 0, + XT_AR_SCRATCH_AR3, + XT_AR_SCRATCH_A4, + XT_AR_SCRATCH_AR4, + XT_AR_SCRATCH_NUM +}; -#define XT_MEM_ACCESS_NONE 0x0 -#define XT_MEM_ACCESS_READ 0x1 -#define XT_MEM_ACCESS_WRITE 0x2 +struct xtensa_keyval_info { + char *chrval; + int intval; +}; -enum xtensa_mem_err_detect { - XT_MEM_ERR_DETECT_NONE, - XT_MEM_ERR_DETECT_PARITY, - XT_MEM_ERR_DETECT_ECC, +enum xtensa_type { + XT_UNDEF = 0, + XT_LX, + XT_NX, }; struct xtensa_cache_config { uint8_t way_count; - uint8_t line_size; - uint16_t size; - bool writeback; - enum xtensa_mem_err_detect mem_err_check; + uint32_t line_size; + uint32_t size; + int writeback; }; struct xtensa_local_mem_region_config { target_addr_t base; uint32_t size; - enum xtensa_mem_err_detect mem_err_check; int access; }; @@ -67,13 +131,14 @@ struct xtensa_mmu_config { bool enabled; uint8_t itlb_entries_count; uint8_t dtlb_entries_count; - bool ivarway56; - bool dvarway56; }; -struct xtensa_exception_config { +struct xtensa_mpu_config { bool enabled; - uint8_t depc_num; + uint8_t nfgseg; + uint32_t minsegsize; + bool lockable; + bool execonly; }; struct xtensa_irq_config { @@ -83,8 +148,8 @@ struct xtensa_irq_config { struct xtensa_high_prio_irq_config { bool enabled; + uint8_t level_num; uint8_t excm_level; - uint8_t nmi_num; }; struct xtensa_debug_config { @@ -92,7 +157,7 @@ struct xtensa_debug_config { uint8_t irq_level; uint8_t ibreaks_num; uint8_t dbreaks_num; - uint8_t icount_sz; + uint8_t perfcount_num; }; struct xtensa_tracing_config { @@ -101,48 +166,26 @@ struct xtensa_tracing_config { bool reversed_mem_access; }; -struct xtensa_timer_irq_config { - bool enabled; - uint8_t comp_num; -}; - struct xtensa_config { - bool density; + enum xtensa_type core_type; uint8_t aregs_num; bool windowed; bool coproc; - bool fp_coproc; - bool loop; - uint8_t miscregs_num; - bool threadptr; - bool boolean; - bool cond_store; - bool ext_l32r; - bool mac16; - bool reloc_vec; - bool proc_id; - bool mem_err_check; - uint16_t user_regs_num; - const struct xtensa_user_reg_desc *user_regs; - int (*fetch_user_regs)(struct target *target); - int (*queue_write_dirty_user_regs)(struct target *target); + bool exceptions; + struct xtensa_irq_config irq; + struct xtensa_high_prio_irq_config high_irq; + struct xtensa_mmu_config mmu; + struct xtensa_mpu_config mpu; + struct xtensa_debug_config debug; + struct xtensa_tracing_config trace; struct xtensa_cache_config icache; struct xtensa_cache_config dcache; struct xtensa_local_mem_config irom; struct xtensa_local_mem_config iram; struct xtensa_local_mem_config drom; struct xtensa_local_mem_config dram; - struct xtensa_local_mem_config uram; - struct xtensa_local_mem_config xlmi; - struct xtensa_mmu_config mmu; - struct xtensa_exception_config exc; - struct xtensa_irq_config irq; - struct xtensa_high_prio_irq_config high_irq; - struct xtensa_timer_irq_config tim_irq; - struct xtensa_debug_config debug; - struct xtensa_tracing_config trace; - unsigned int gdb_general_regs_num; - const unsigned int *gdb_regs_mapping; + struct xtensa_local_mem_config sram; + struct xtensa_local_mem_config srom; }; typedef uint32_t xtensa_insn_t; @@ -152,6 +195,17 @@ enum xtensa_stepping_isr_mode { XT_STEPPING_ISR_ON, /* interrupts are enabled during stepping */ }; +enum xtensa_nx_reg_idx { + XT_NX_REG_IDX_IBREAKC0 = 0, + XT_NX_REG_IDX_WB, + XT_NX_REG_IDX_MS, + XT_NX_REG_IDX_IEVEC, /* IEVEC, IEEXTERN, and MESR must be contiguous */ + XT_NX_REG_IDX_IEEXTERN, + XT_NX_REG_IDX_MESR, + XT_NX_REG_IDX_MESRCLR, + XT_NX_REG_IDX_NUM +}; + /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */ enum xtensa_mode { XT_MODE_RING0, @@ -169,6 +223,17 @@ struct xtensa_sw_breakpoint { uint8_t insn_sz; /* 2 or 3 bytes */ }; +/** + * Xtensa algorithm data. + */ +struct xtensa_algorithm { + /** User can set this to specify which core mode algorithm should be run in. */ + enum xtensa_mode core_mode; + /** Used internally to backup and restore core state. */ + enum target_debug_reason ctx_debug_reason; + xtensa_reg_val_t ctx_ps; +}; + #define XTENSA_COMMON_MAGIC 0x54E4E555U /** @@ -176,13 +241,26 @@ struct xtensa_sw_breakpoint { */ struct xtensa { unsigned int common_magic; - const struct xtensa_config *core_config; + struct xtensa_chip_common *xtensa_chip; + struct xtensa_config *core_config; struct xtensa_debug_module dbg_mod; struct reg_cache *core_cache; - unsigned int regs_num; + unsigned int total_regs_num; + unsigned int core_regs_num; + bool regmap_contiguous; + unsigned int genpkt_regs_num; + struct xtensa_reg_desc **contiguous_regs_desc; + struct reg **contiguous_regs_list; + /* Per-config Xtensa registers as specified via "xtreg" in xtensa-core*.cfg */ + struct xtensa_reg_desc *optregs; + unsigned int num_optregs; + struct reg *empty_regs; + char qpkt_resp[XT_QUERYPKT_RESP_MAX]; /* An array of pointers to buffers to backup registers' values while algo is run on target. * Size is 'regs_num'. */ void **algo_context_backup; + unsigned int eps_dbglevel_idx; + unsigned int dbregs_num; struct target *target; bool reset_asserted; enum xtensa_stepping_isr_mode stepping_isr_mode; @@ -193,11 +271,20 @@ struct xtensa { bool permissive_mode; /* bypass memory checks */ bool suppress_dsr_errors; uint32_t smp_break; + uint32_t spill_loc; + unsigned int spill_bytes; + uint8_t *spill_buf; + int8_t probe_lsddr32p; /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some * time.This is the number of polling periods after which core is considered to be powered * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by * SW running on target).*/ uint8_t come_online_probes_num; + bool proc_syscall; + bool halt_request; + uint32_t nx_stop_cause; + uint32_t nx_reg_idx[XT_NX_REG_IDX_NUM]; + struct xtensa_keyval_info scratch_ars[XT_AR_SCRATCH_NUM]; bool regs_fetched; /* true after first register fetch completed successfully */ }; @@ -211,7 +298,6 @@ static inline struct xtensa *target_to_xtensa(struct target *target) int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, - const struct xtensa_config *cfg, const struct xtensa_debug_module_config *dm_cfg); int xtensa_target_init(struct command_context *cmd_ctx, struct target *target); void xtensa_target_deinit(struct target *target); @@ -234,11 +320,41 @@ static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr) return true; if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr)) return true; - if (xtensa_addr_in_mem(&xtensa->core_config->uram, addr)) + if (xtensa_addr_in_mem(&xtensa->core_config->sram, addr)) return true; return false; } +static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data) +{ + struct xtensa_debug_module *dm = &xtensa->dbg_mod; + + if (!xtensa->core_config->trace.enabled && + (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) { + LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg); + return ERROR_FAIL; + } + return dm->dbg_ops->queue_reg_read(dm, reg, data); +} + +static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data) +{ + struct xtensa_debug_module *dm = &xtensa->dbg_mod; + + if (!xtensa->core_config->trace.enabled && + (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) { + LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg); + return ERROR_FAIL; + } + return dm->dbg_ops->queue_reg_write(dm, reg, data); +} + +static inline int xtensa_core_status_clear(struct target *target, uint32_t bits) +{ + struct xtensa *xtensa = target_to_xtensa(target); + return xtensa_dm_core_status_clear(&xtensa->dbg_mod, bits); +} + int xtensa_core_status_check(struct target *target); int xtensa_examine(struct target *target); @@ -249,27 +365,33 @@ int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set); int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val); xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id); void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value); +void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value); int xtensa_fetch_all_regs(struct target *target); int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); +uint32_t xtensa_cause_get(struct target *target); +void xtensa_cause_clear(struct target *target); +void xtensa_cause_reset(struct target *target); int xtensa_poll(struct target *target); void xtensa_on_poll(struct target *target); int xtensa_halt(struct target *target); int xtensa_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution); + bool handle_breakpoints, + bool debug_execution); int xtensa_prepare_resume(struct target *target, - int current, + bool current, target_addr_t address, - int handle_breakpoints, - int debug_execution); + bool handle_breakpoints, + bool debug_execution); int xtensa_do_resume(struct target *target); -int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints); -int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints); +int xtensa_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints); +int xtensa_do_step(struct target *target, bool current, target_addr_t address, + bool handle_breakpoints); int xtensa_mmu_is_enabled(struct target *target, int *enabled); int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer); @@ -282,16 +404,37 @@ int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t c int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum); int xtensa_assert_reset(struct target *target); int xtensa_deassert_reset(struct target *target); +int xtensa_soft_reset_halt(struct target *target); int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint); int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint); int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint); int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint); +int xtensa_start_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + void *arch_info); +int xtensa_wait_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t exit_point, unsigned int timeout_ms, + void *arch_info); +int xtensa_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + unsigned int timeout_ms, void *arch_info); void xtensa_set_permissive_mode(struct target *target, bool state); -int xtensa_fetch_user_regs_u32(struct target *target); -int xtensa_queue_write_dirty_user_regs_u32(struct target *target); -const char *xtensa_get_gdb_arch(struct target *target); - - +const char *xtensa_get_gdb_arch(const struct target *target); +int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p); + +COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa); +COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa); COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa); COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa); COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target); @@ -301,8 +444,6 @@ COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa); COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa); COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname); -extern const struct reg_arch_type xtensa_user_reg_u32_type; -extern const struct reg_arch_type xtensa_user_reg_u128_type; extern const struct command_registration xtensa_command_handlers[]; #endif /* OPENOCD_TARGET_XTENSA_H */ diff --git a/src/target/xtensa/xtensa_chip.c b/src/target/xtensa/xtensa_chip.c new file mode 100644 index 0000000000..aab7ee37c5 --- /dev/null +++ b/src/target/xtensa/xtensa_chip.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Xtensa Chip-level Target Support for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "assert.h" +#include <target/target.h> +#include <target/target_type.h> +#include <target/arm_adi_v5.h> +#include <rtos/rtos.h> +#include "xtensa_chip.h" +#include "xtensa_fileio.h" + +int xtensa_chip_init_arch_info(struct target *target, void *arch_info, + struct xtensa_debug_module_config *dm_cfg) +{ + struct xtensa_chip_common *xtensa_chip = (struct xtensa_chip_common *)arch_info; + int ret = xtensa_init_arch_info(target, &xtensa_chip->xtensa, dm_cfg); + if (ret != ERROR_OK) + return ret; + /* All xtensa target structures point back to original xtensa_chip */ + xtensa_chip->xtensa.xtensa_chip = arch_info; + return ERROR_OK; +} + +int xtensa_chip_target_init(struct command_context *cmd_ctx, struct target *target) +{ + int ret = xtensa_target_init(cmd_ctx, target); + if (ret != ERROR_OK) + return ret; + return xtensa_fileio_init(target); +} + +int xtensa_chip_arch_state(struct target *target) +{ + return ERROR_OK; +} + +static int xtensa_chip_poll(struct target *target) +{ + enum target_state old_state = target->state; + int ret = xtensa_poll(target); + + if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) { + /*Call any event callbacks that are applicable */ + if (old_state == TARGET_DEBUG_RUNNING) { + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + } else { + xtensa_fileio_detect_proc(target); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } + } + + return ret; +} + +static int xtensa_chip_virt2phys(struct target *target, + target_addr_t virtual, target_addr_t *physical) +{ + if (physical) { + *physical = virtual; + return ERROR_OK; + } + return ERROR_FAIL; +} + +static const struct xtensa_debug_ops xtensa_chip_dm_dbg_ops = { + .queue_enable = xtensa_dm_queue_enable, + .queue_reg_read = xtensa_dm_queue_reg_read, + .queue_reg_write = xtensa_dm_queue_reg_write +}; + +static const struct xtensa_power_ops xtensa_chip_dm_pwr_ops = { + .queue_reg_read = xtensa_dm_queue_pwr_reg_read, + .queue_reg_write = xtensa_dm_queue_pwr_reg_write +}; + +static int xtensa_chip_target_create(struct target *target) +{ + struct xtensa_debug_module_config xtensa_chip_dm_cfg = { + .dbg_ops = &xtensa_chip_dm_dbg_ops, + .pwr_ops = &xtensa_chip_dm_pwr_ops, + .tap = NULL, + .queue_tdi_idle = NULL, + .queue_tdi_idle_arg = NULL, + .dap = NULL, + .debug_ap = NULL, + .debug_apsel = DP_APSEL_INVALID, + .ap_offset = 0, + }; + + struct adiv5_private_config *pc = target->private_config; + if (adiv5_verify_config(pc) == ERROR_OK) { + xtensa_chip_dm_cfg.dap = pc->dap; + xtensa_chip_dm_cfg.debug_apsel = pc->ap_num; + xtensa_chip_dm_cfg.ap_offset = target->dbgbase; + LOG_DEBUG("DAP: ap_num %" PRId64 " DAP %p\n", pc->ap_num, pc->dap); + } else { + xtensa_chip_dm_cfg.tap = target->tap; + LOG_DEBUG("JTAG: %s:%s pos %u", target->tap->chip, target->tap->tapname, + target->tap->abs_chain_position); + } + + struct xtensa_chip_common *xtensa_chip = calloc(1, sizeof(struct xtensa_chip_common)); + if (!xtensa_chip) { + LOG_ERROR("Failed to alloc chip-level memory!"); + return ERROR_FAIL; + } + + int ret = xtensa_chip_init_arch_info(target, xtensa_chip, &xtensa_chip_dm_cfg); + if (ret != ERROR_OK) { + LOG_ERROR("Failed to init arch info!"); + free(xtensa_chip); + return ret; + } + + /*Assume running target. If different, the first poll will fix this. */ + target->state = TARGET_RUNNING; + target->debug_reason = DBG_REASON_NOTHALTED; + return ERROR_OK; +} + +static void xtensa_chip_target_deinit(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + xtensa_target_deinit(target); + free(xtensa->xtensa_chip); +} + +static int xtensa_chip_examine(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + int retval = xtensa_dm_examine(&xtensa->dbg_mod); + if (retval == ERROR_OK) + retval = xtensa_examine(target); + return retval; +} + +static int xtensa_chip_jim_configure(struct target *target, struct jim_getopt_info *goi) +{ + return adiv5_jim_configure_ext(target, goi, NULL, ADI_CONFIGURE_DAP_OPTIONAL); +} + +/** Methods for generic example of Xtensa-based chip-level targets. */ +struct target_type xtensa_chip_target = { + .name = "xtensa", + + .poll = xtensa_chip_poll, + .arch_state = xtensa_chip_arch_state, + + .halt = xtensa_halt, + .resume = xtensa_resume, + .step = xtensa_step, + + .assert_reset = xtensa_assert_reset, + .deassert_reset = xtensa_deassert_reset, + .soft_reset_halt = xtensa_soft_reset_halt, + + .virt2phys = xtensa_chip_virt2phys, + .mmu = xtensa_mmu_is_enabled, + .read_memory = xtensa_read_memory, + .write_memory = xtensa_write_memory, + + .read_buffer = xtensa_read_buffer, + .write_buffer = xtensa_write_buffer, + + .checksum_memory = xtensa_checksum_memory, + + .get_gdb_reg_list = xtensa_get_gdb_reg_list, + + .run_algorithm = xtensa_run_algorithm, + .start_algorithm = xtensa_start_algorithm, + .wait_algorithm = xtensa_wait_algorithm, + + .add_breakpoint = xtensa_breakpoint_add, + .remove_breakpoint = xtensa_breakpoint_remove, + + .add_watchpoint = xtensa_watchpoint_add, + .remove_watchpoint = xtensa_watchpoint_remove, + + .target_create = xtensa_chip_target_create, + .target_jim_configure = xtensa_chip_jim_configure, + .init_target = xtensa_chip_target_init, + .examine = xtensa_chip_examine, + .deinit_target = xtensa_chip_target_deinit, + + .gdb_query_custom = xtensa_gdb_query_custom, + + .commands = xtensa_command_handlers, + + .get_gdb_fileio_info = xtensa_get_gdb_fileio_info, + .gdb_fileio_end = xtensa_gdb_fileio_end, +}; diff --git a/src/target/xtensa/xtensa_chip.h b/src/target/xtensa/xtensa_chip.h new file mode 100644 index 0000000000..5200deb72b --- /dev/null +++ b/src/target/xtensa/xtensa_chip.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Xtensa Chip-level Target Support for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_XTENSA_CHIP_H +#define OPENOCD_TARGET_XTENSA_CHIP_H + +#include <target/target.h> +#include "xtensa.h" +#include "xtensa_debug_module.h" + +struct xtensa_chip_common { + struct xtensa xtensa; + /* Chip-specific extensions can be added here */ +}; + +static inline struct xtensa_chip_common *target_to_xtensa_chip(struct target *target) +{ + return container_of(target->arch_info, struct xtensa_chip_common, xtensa); +} + +int xtensa_chip_init_arch_info(struct target *target, void *arch_info, + struct xtensa_debug_module_config *dm_cfg); +int xtensa_chip_target_init(struct command_context *cmd_ctx, struct target *target); +int xtensa_chip_arch_state(struct target *target); +void xtensa_chip_queue_tdi_idle(struct target *target); +void xtensa_chip_on_reset(struct target *target); +bool xtensa_chip_on_halt(struct target *target); +void xtensa_chip_on_poll(struct target *target); + +#endif /* OPENOCD_TARGET_XTENSA_CHIP_H */ diff --git a/src/target/xtensa/xtensa_debug_module.c b/src/target/xtensa/xtensa_debug_module.c index a7de1ad5c9..943f199c1f 100644 --- a/src/target/xtensa/xtensa_debug_module.c +++ b/src/target/xtensa/xtensa_debug_module.c @@ -1,7 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** - * Generic Xtensa debug module API for OpenOCD * + * Xtensa Debug Module (XDM) Support for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * * Copyright (C) 2019 Espressif Systems Ltd. * ***************************************************************************/ @@ -9,6 +10,7 @@ #include <config.h> #endif +#include <helper/align.h> #include "xtensa_debug_module.h" #define TAPINS_PWRCTL 0x08 @@ -24,11 +26,28 @@ #define TAPINS_IDCODE_LEN 32 #define TAPINS_BYPASS_LEN 1 +/* Table of power register offsets for APB space */ +static const struct xtensa_dm_pwr_reg_offsets xdm_pwr_regs[XDMREG_PWRNUM] = + XTENSA_DM_PWR_REG_OFFSETS; + +/* Table of debug register offsets for Nexus and APB space */ +static const struct xtensa_dm_reg_offsets xdm_regs[XDMREG_NUM] = + XTENSA_DM_REG_OFFSETS; + +static enum xtensa_dm_reg xtensa_dm_regaddr_to_id(uint32_t addr) +{ + enum xtensa_dm_reg id; + uint32_t addr_masked = (addr & (XTENSA_DM_APB_ALIGN - 1)); + for (id = XDMREG_TRAXID; id < XDMREG_NUM; id++) + if (xdm_regs[id].apb == addr_masked) + break; + return id; +} static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value) { struct scan_field field; - uint8_t t[4] = { 0 }; + uint8_t t[4] = { 0, 0, 0, 0 }; memset(&field, 0, sizeof(field)); field.num_bits = dm->tap->ir_length; @@ -41,7 +60,7 @@ static void xtensa_dm_add_dr_scan(struct xtensa_debug_module *dm, int len, const uint8_t *src, uint8_t *dest, - tap_state_t endstate) + enum tap_state endstate) { struct scan_field field; @@ -56,87 +75,167 @@ int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_mod { if (!dm || !cfg) return ERROR_FAIL; + if (!IS_ALIGNED(cfg->ap_offset, XTENSA_DM_APB_ALIGN)) { + LOG_ERROR("Xtensa DM APB offset must be aligned to a %dKB multiple", + XTENSA_DM_APB_ALIGN / 1024); + return ERROR_FAIL; + } dm->pwr_ops = cfg->pwr_ops; dm->dbg_ops = cfg->dbg_ops; dm->tap = cfg->tap; dm->queue_tdi_idle = cfg->queue_tdi_idle; dm->queue_tdi_idle_arg = cfg->queue_tdi_idle_arg; + dm->dap = cfg->dap; + dm->debug_ap = cfg->debug_ap; + dm->debug_apsel = cfg->debug_apsel; + dm->ap_offset = cfg->ap_offset; return ERROR_OK; } -int xtensa_dm_queue_enable(struct xtensa_debug_module *dm) +void xtensa_dm_deinit(struct xtensa_debug_module *dm) { - return dm->dbg_ops->queue_reg_write(dm, NARADR_DCRSET, OCDDCR_ENABLEOCD); + if (dm->debug_ap) { + dap_put_ap(dm->debug_ap); + dm->debug_ap = NULL; + } } -int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *value) +int xtensa_dm_poll(struct xtensa_debug_module *dm) { - uint8_t regdata = (reg << 1) | 0; - uint8_t dummy[4] = { 0, 0, 0, 0 }; + /* Check if debug_ap is available to prevent segmentation fault. + * If the re-examination after an error does not find a MEM-AP + * (e.g. the target stopped communicating), debug_ap pointer + * can suddenly become NULL. + */ + return (!dm || (dm->dap && !dm->debug_ap)) ? ERROR_FAIL : ERROR_OK; +} - if (reg > NARADR_MAX) { +int xtensa_dm_examine(struct xtensa_debug_module *dm) +{ + struct adiv5_dap *swjdp = dm->dap; + int retval = ERROR_OK; + + if (swjdp) { + LOG_DEBUG("DM examine: DAP AP select %d", dm->debug_apsel); + if (dm->debug_ap) { + dap_put_ap(dm->debug_ap); + dm->debug_ap = NULL; + } + if (dm->debug_apsel == DP_APSEL_INVALID) { + LOG_DEBUG("DM examine: search for APB-type MEM-AP..."); + /* TODO: Determine whether AP_TYPE_AXI_AP APs can be supported... */ + retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &dm->debug_ap); + if (retval != ERROR_OK) { + LOG_ERROR("Could not find MEM-AP to control the core"); + return retval; + } + } else { + dm->debug_ap = dap_get_ap(swjdp, dm->debug_apsel); + } + + /* TODO: Allow a user-specified AP instead of relying on AP_TYPE_APB_AP */ + dm->debug_apsel = dm->debug_ap->ap_num; + LOG_DEBUG("DM examine: Setting apsel to %d", dm->debug_apsel); + + /* Leave (only) generic DAP stuff for debugport_init(); */ + dm->debug_ap->memaccess_tck = 8; + + retval = mem_ap_init(dm->debug_ap); + if (retval != ERROR_OK) { + LOG_ERROR("MEM-AP init failed: %d", retval); + return retval; + } + + /* TODO: how to set autoincrement range? Hard-code it to 1024 bytes for now */ + dm->debug_ap->tar_autoincr_block = (1 << 10); + } + + return retval; +} + +int xtensa_dm_queue_enable(struct xtensa_debug_module *dm) +{ + return dm->dbg_ops->queue_reg_write(dm, XDMREG_DCRSET, OCDDCR_ENABLEOCD); +} + +int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value) +{ + if (reg >= XDMREG_NUM) { LOG_ERROR("Invalid DBG reg ID %d!", reg); return ERROR_FAIL; } + if (dm->dap) + /* NOTE: Future optimization: mem_ap_read_u32() offers higher performance with + * queued reads, but requires an API change to pass value as a 32-bit pointer. + */ + return mem_ap_read_buf(dm->debug_ap, value, 4, 1, xdm_regs[reg].apb + dm->ap_offset); + uint8_t regdata = (xdm_regs[reg].nar << 1) | 0; + uint8_t dummy[4] = { 0, 0, 0, 0 }; xtensa_dm_add_set_ir(dm, TAPINS_NARSEL); xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE); xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, dummy, value, TAP_IDLE); return ERROR_OK; } -int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint32_t value) +int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value) { - uint8_t regdata = (reg << 1) | 1; - uint8_t valdata[] = { value, value >> 8, value >> 16, value >> 24 }; - - if (reg > NARADR_MAX) { + if (reg >= XDMREG_NUM) { LOG_ERROR("Invalid DBG reg ID %d!", reg); return ERROR_FAIL; } + if (dm->dap) + return mem_ap_write_u32(dm->debug_ap, xdm_regs[reg].apb + dm->ap_offset, value); + uint8_t regdata = (xdm_regs[reg].nar << 1) | 1; + uint8_t valdata[] = { value, value >> 8, value >> 16, value >> 24 }; xtensa_dm_add_set_ir(dm, TAPINS_NARSEL); xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE); xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, valdata, NULL, TAP_IDLE); return ERROR_OK; } -int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, uint8_t clear) +int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, + enum xtensa_dm_pwr_reg reg, + uint8_t *data, + uint32_t clear) { - uint8_t value_clr = clear; - uint8_t tap_insn; - int tap_insn_sz; - - if (reg == DMREG_PWRCTL) { - tap_insn = TAPINS_PWRCTL; - tap_insn_sz = TAPINS_PWRCTL_LEN; - } else if (reg == DMREG_PWRSTAT) { - tap_insn = TAPINS_PWRSTAT; - tap_insn_sz = TAPINS_PWRSTAT_LEN; - } else { + if (reg >= XDMREG_PWRNUM) { LOG_ERROR("Invalid PWR reg ID %d!", reg); return ERROR_FAIL; } + if (dm->dap) { + /* NOTE: Future optimization: mem_ap_read_u32() offers higher performance with + * queued reads, but requires an API change to pass value as a 32-bit pointer. + */ + uint32_t apbreg = xdm_pwr_regs[reg].apb + dm->ap_offset; + int retval = mem_ap_read_buf(dm->debug_ap, data, 4, 1, apbreg); + if (retval == ERROR_OK) + retval = mem_ap_write_u32(dm->debug_ap, apbreg, clear); + return retval; + } + uint8_t value_clr = (uint8_t)clear; + uint8_t tap_insn = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL : TAPINS_PWRSTAT; + int tap_insn_sz = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL_LEN : TAPINS_PWRSTAT_LEN; xtensa_dm_add_set_ir(dm, tap_insn); xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value_clr, data, TAP_IDLE); return ERROR_OK; } -int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data) +int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, + enum xtensa_dm_pwr_reg reg, + uint32_t data) { - uint8_t value = data; - uint8_t tap_insn; - int tap_insn_sz; - - if (reg == DMREG_PWRCTL) { - tap_insn = TAPINS_PWRCTL; - tap_insn_sz = TAPINS_PWRCTL_LEN; - } else if (reg == DMREG_PWRSTAT) { - tap_insn = TAPINS_PWRSTAT; - tap_insn_sz = TAPINS_PWRSTAT_LEN; - } else { + if (reg >= XDMREG_PWRNUM) { LOG_ERROR("Invalid PWR reg ID %d!", reg); return ERROR_FAIL; } + if (dm->dap) { + uint32_t apbreg = xdm_pwr_regs[reg].apb + dm->ap_offset; + return mem_ap_write_u32(dm->debug_ap, apbreg, data); + } + uint8_t tap_insn = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL : TAPINS_PWRSTAT; + int tap_insn_sz = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL_LEN : TAPINS_PWRSTAT_LEN; + uint8_t value = (uint8_t)data; xtensa_dm_add_set_ir(dm, tap_insn); xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value, NULL, TAP_IDLE); return ERROR_OK; @@ -146,9 +245,9 @@ int xtensa_dm_device_id_read(struct xtensa_debug_module *dm) { uint8_t id_buf[sizeof(uint32_t)]; - dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_OCDID, id_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res != ERROR_OK) return res; dm->device_id = buf_get_u32(id_buf, 0, 32); @@ -157,16 +256,22 @@ int xtensa_dm_device_id_read(struct xtensa_debug_module *dm) int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear) { - /* uint8_t id_buf[sizeof(uint32_t)]; */ + uint8_t stat_buf[sizeof(uint32_t)] = { 0, 0, 0, 0 }; + uint8_t stath_buf[sizeof(uint32_t)] = { 0, 0, 0, 0 }; /* TODO: JTAG does not work when PWRCTL_JTAGDEBUGUSE is not set. - * It is set in xtensa_examine(), need to move reading of NARADR_OCDID out of this function */ - /* dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf); + * It is set in xtensa_examine(), need to move reading of XDMREG_OCDID out of this function */ + /* dm->dbg_ops->queue_reg_read(dm, XDMREG_OCDID, id_buf); *Read reset state */ - dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stat, clear); - dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stath, clear); + dm->pwr_ops->queue_reg_read(dm, XDMREG_PWRSTAT, stat_buf, clear); + dm->pwr_ops->queue_reg_read(dm, XDMREG_PWRSTAT, stath_buf, clear); xtensa_dm_queue_tdi_idle(dm); - return jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); + if (res != ERROR_OK) + return res; + dm->power_status.stat = buf_get_u32(stat_buf, 0, 32); + dm->power_status.stath = buf_get_u32(stath_buf, 0, 32); + return res; } int xtensa_dm_core_status_read(struct xtensa_debug_module *dm) @@ -174,9 +279,9 @@ int xtensa_dm_core_status_read(struct xtensa_debug_module *dm) uint8_t dsr_buf[sizeof(uint32_t)]; xtensa_dm_queue_enable(dm); - dm->dbg_ops->queue_reg_read(dm, NARADR_DSR, dsr_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_DSR, dsr_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res != ERROR_OK) return res; dm->core_status.dsr = buf_get_u32(dsr_buf, 0, 32); @@ -185,37 +290,65 @@ int xtensa_dm_core_status_read(struct xtensa_debug_module *dm) int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits) { - dm->dbg_ops->queue_reg_write(dm, NARADR_DSR, bits); + dm->dbg_ops->queue_reg_write(dm, XDMREG_DSR, bits); xtensa_dm_queue_tdi_idle(dm); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(dm); +} + +int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val) +{ + enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr); + uint8_t buf[sizeof(uint32_t)]; + if (reg < XDMREG_NUM) { + xtensa_dm_queue_enable(dm); + dm->dbg_ops->queue_reg_read(dm, reg, buf); + xtensa_dm_queue_tdi_idle(dm); + int res = xtensa_dm_queue_execute(dm); + if (res == ERROR_OK && val) + *val = buf_get_u32(buf, 0, 32); + return res; + } + return ERROR_FAIL; +} + +int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val) +{ + enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr); + if (reg < XDMREG_NUM) { + xtensa_dm_queue_enable(dm); + dm->dbg_ops->queue_reg_write(dm, reg, val); + xtensa_dm_queue_tdi_idle(dm); + return xtensa_dm_queue_execute(dm); + } + return ERROR_FAIL; } int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg) { /*Turn off trace unit so we can start a new trace. */ - dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, 0); + dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXCTRL, 0); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res != ERROR_OK) return res; /*Set up parameters */ - dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXADDR, 0); + dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXADDR, 0); if (cfg->stopmask != XTENSA_STOPMASK_DISABLED) { - dm->dbg_ops->queue_reg_write(dm, NARADR_PCMATCHCTRL, + dm->dbg_ops->queue_reg_write(dm, XDMREG_PCMATCHCTRL, (cfg->stopmask << PCMATCHCTRL_PCML_SHIFT)); - dm->dbg_ops->queue_reg_write(dm, NARADR_TRIGGERPC, cfg->stoppc); + dm->dbg_ops->queue_reg_write(dm, XDMREG_TRIGGERPC, cfg->stoppc); } - dm->dbg_ops->queue_reg_write(dm, NARADR_DELAYCNT, cfg->after); + dm->dbg_ops->queue_reg_write(dm, XDMREG_DELAYCNT, cfg->after); /*Options are mostly hardcoded for now. ToDo: make this more configurable. */ dm->dbg_ops->queue_reg_write( dm, - NARADR_TRAXCTRL, + XDMREG_TRAXCTRL, TRAXCTRL_TREN | ((cfg->stopmask != XTENSA_STOPMASK_DISABLED) ? TRAXCTRL_PCMEN : 0) | TRAXCTRL_TMEN | (cfg->after_is_words ? 0 : TRAXCTRL_CNTU) | (0 << TRAXCTRL_SMPER_SHIFT) | TRAXCTRL_PTOWS); xtensa_dm_queue_tdi_idle(dm); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(dm); } int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable) @@ -224,9 +357,9 @@ int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable) uint32_t traxctl; struct xtensa_trace_status trace_status; - dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXCTRL, traxctl_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res != ERROR_OK) return res; traxctl = buf_get_u32(traxctl_buf, 0, 32); @@ -234,9 +367,9 @@ int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable) if (!pto_enable) traxctl &= ~(TRAXCTRL_PTOWS | TRAXCTRL_PTOWT); - dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, traxctl | TRAXCTRL_TRSTP); + dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXCTRL, traxctl | TRAXCTRL_TRSTP); xtensa_dm_queue_tdi_idle(dm); - res = jtag_execute_queue(); + res = xtensa_dm_queue_execute(dm); if (res != ERROR_OK) return res; @@ -256,9 +389,9 @@ int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_tr { uint8_t traxstat_buf[sizeof(uint32_t)]; - dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXSTAT, traxstat_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXSTAT, traxstat_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res == ERROR_OK && status) status->stat = buf_get_u32(traxstat_buf, 0, 32); return res; @@ -274,12 +407,12 @@ int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_tr if (!config) return ERROR_FAIL; - dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf); - dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDRSTART, memadrstart_buf); - dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDREND, memadrend_buf); - dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXADDR, adr_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXCTRL, traxctl_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_MEMADDRSTART, memadrstart_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_MEMADDREND, memadrend_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXADDR, adr_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res == ERROR_OK) { config->ctrl = buf_get_u32(traxctl_buf, 0, 32); config->memaddr_start = buf_get_u32(memadrstart_buf, 0, 32); @@ -295,9 +428,9 @@ int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uin return ERROR_FAIL; for (unsigned int i = 0; i < size / 4; i++) - dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXDATA, &dest[i * 4]); + dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXDATA, &dest[i * 4]); xtensa_dm_queue_tdi_idle(dm); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(dm); } int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, @@ -313,13 +446,13 @@ int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, (config->kernelcnt << 3); /* enable performance monitor */ - dm->dbg_ops->queue_reg_write(dm, NARADR_PMG, 0x1); + dm->dbg_ops->queue_reg_write(dm, XDMREG_PMG, 0x1); /* reset counter */ - dm->dbg_ops->queue_reg_write(dm, NARADR_PM0 + counter_id, 0); - dm->dbg_ops->queue_reg_write(dm, NARADR_PMCTRL0 + counter_id, pmctrl); - dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf); + dm->dbg_ops->queue_reg_write(dm, XDMREG_PM0 + counter_id, 0); + dm->dbg_ops->queue_reg_write(dm, XDMREG_PMCTRL0 + counter_id, pmctrl); + dm->dbg_ops->queue_reg_read(dm, XDMREG_PMSTAT0 + counter_id, pmstat_buf); xtensa_dm_queue_tdi_idle(dm); - return jtag_execute_queue(); + return xtensa_dm_queue_execute(dm); } int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, @@ -328,10 +461,10 @@ int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, uint8_t pmstat_buf[4]; uint8_t pmcount_buf[4]; - dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf); - dm->dbg_ops->queue_reg_read(dm, NARADR_PM0 + counter_id, pmcount_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_PMSTAT0 + counter_id, pmstat_buf); + dm->dbg_ops->queue_reg_read(dm, XDMREG_PM0 + counter_id, pmcount_buf); xtensa_dm_queue_tdi_idle(dm); - int res = jtag_execute_queue(); + int res = xtensa_dm_queue_execute(dm); if (res == ERROR_OK) { uint32_t stat = buf_get_u32(pmstat_buf, 0, 32); uint64_t result = buf_get_u32(pmcount_buf, 0, 32); diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h index 88f9eb2a7b..8391a96382 100644 --- a/src/target/xtensa/xtensa_debug_module.h +++ b/src/target/xtensa/xtensa_debug_module.h @@ -1,25 +1,39 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /*************************************************************************** - * Xtensa debug module API * + * Xtensa Debug Module (XDM) Support for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * * Copyright (C) 2019 Espressif Systems Ltd. * - * <alexey@espressif.com> * - * * * Derived from original ESP8266 target. * - * Copyright (C) 2015 by Angus Gratton * - * gus@projectgus.com * + * Author: Angus Gratton gus@projectgus.com * ***************************************************************************/ #ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H #define OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H #include <jtag/jtag.h> +#include <target/arm_adi_v5.h> #include <helper/bits.h> #include <target/target.h> /* Virtual IDs for using with xtensa_power_ops API */ -#define DMREG_PWRCTL 0x00 -#define DMREG_PWRSTAT 0x01 +enum xtensa_dm_pwr_reg { + XDMREG_PWRCTL = 0x00, + XDMREG_PWRSTAT, + XDMREG_PWRNUM +}; + +/* Debug Module Power Register offsets within APB */ +struct xtensa_dm_pwr_reg_offsets { + uint16_t apb; +}; + +/* Debug Module Power Register offset structure; must include XDMREG_PWRNUM entries */ +#define XTENSA_DM_PWR_REG_OFFSETS { \ + /* Power/Reset Registers */ \ + { .apb = 0x3020 }, /* XDMREG_PWRCTL */ \ + { .apb = 0x3024 }, /* XDMREG_PWRSTAT */ \ +} /* From the manual: @@ -32,84 +46,241 @@ Module to happen correctly. When it is set, any write to this bit clears it. Either don't access it, or re-write it to 1 so JTAG accesses continue. */ -#define PWRCTL_JTAGDEBUGUSE BIT(7) -#define PWRCTL_DEBUGRESET BIT(6) -#define PWRCTL_CORERESET BIT(4) -#define PWRCTL_DEBUGWAKEUP BIT(2) -#define PWRCTL_MEMWAKEUP BIT(1) -#define PWRCTL_COREWAKEUP BIT(0) - -#define PWRSTAT_DEBUGWASRESET BIT(6) -#define PWRSTAT_COREWASRESET BIT(4) -#define PWRSTAT_CORESTILLNEEDED BIT(3) -#define PWRSTAT_DEBUGDOMAINON BIT(2) -#define PWRSTAT_MEMDOMAINON BIT(1) -#define PWRSTAT_COREDOMAINON BIT(0) - -/* *** NAR addresses (also used as IDs for debug registers in xtensa_debug_ops API) *** - *TRAX registers */ -#define NARADR_TRAXID 0x00 -#define NARADR_TRAXCTRL 0x01 -#define NARADR_TRAXSTAT 0x02 -#define NARADR_TRAXDATA 0x03 -#define NARADR_TRAXADDR 0x04 -#define NARADR_TRIGGERPC 0x05 -#define NARADR_PCMATCHCTRL 0x06 -#define NARADR_DELAYCNT 0x07 -#define NARADR_MEMADDRSTART 0x08 -#define NARADR_MEMADDREND 0x09 -/*Performance monitor registers */ -#define NARADR_PMG 0x20 -#define NARADR_INTPC 0x24 -#define NARADR_PM0 0x28 -/*... */ -#define NARADR_PM7 0x2F -#define NARADR_PMCTRL0 0x30 -/*... */ -#define NARADR_PMCTRL7 0x37 -#define NARADR_PMSTAT0 0x38 -/*... */ -#define NARADR_PMSTAT7 0x3F -/*OCD registers */ -#define NARADR_OCDID 0x40 -#define NARADR_DCRCLR 0x42 -#define NARADR_DCRSET 0x43 -#define NARADR_DSR 0x44 -#define NARADR_DDR 0x45 -#define NARADR_DDREXEC 0x46 -#define NARADR_DIR0EXEC 0x47 -#define NARADR_DIR0 0x48 -#define NARADR_DIR1 0x49 -/*... */ -#define NARADR_DIR7 0x4F -/*Misc registers */ -#define NARADR_PWRCTL 0x58 -#define NARADR_PWRSTAT 0x59 -#define NARADR_ERISTAT 0x5A -/*CoreSight registers */ -#define NARADR_ITCTRL 0x60 -#define NARADR_CLAIMSET 0x68 -#define NARADR_CLAIMCLR 0x69 -#define NARADR_LOCKACCESS 0x6c -#define NARADR_LOCKSTATUS 0x6d -#define NARADR_AUTHSTATUS 0x6e -#define NARADR_DEVID 0x72 -#define NARADR_DEVTYPE 0x73 -#define NARADR_PERID4 0x74 -/*... */ -#define NARADR_PERID7 0x77 -#define NARADR_PERID0 0x78 -/*... */ -#define NARADR_PERID3 0x7b -#define NARADR_COMPID0 0x7c -/*... */ -#define NARADR_COMPID3 0x7f -#define NARADR_MAX NARADR_COMPID3 - -/*OCD registers, bit definitions */ +#define PWRCTL_JTAGDEBUGUSE(x) (((x)->dbg_mod.dap) ? (0) : BIT(7)) +#define PWRCTL_DEBUGRESET(x) (((x)->dbg_mod.dap) ? BIT(28) : BIT(6)) +#define PWRCTL_CORERESET(x) (((x)->dbg_mod.dap) ? BIT(16) : BIT(4)) +#define PWRCTL_DEBUGWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2)) +#define PWRCTL_MEMWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1)) +#define PWRCTL_COREWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0)) + +#define PWRSTAT_DEBUGWASRESET_DM(d) (((d)->dap) ? BIT(28) : BIT(6)) +#define PWRSTAT_COREWASRESET_DM(d) (((d)->dap) ? BIT(16) : BIT(4)) +#define PWRSTAT_DEBUGWASRESET(x) (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod))) +#define PWRSTAT_COREWASRESET(x) (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod))) +#define PWRSTAT_CORESTILLNEEDED(x) (((x)->dbg_mod.dap) ? BIT(4) : BIT(3)) +#define PWRSTAT_DEBUGDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2)) +#define PWRSTAT_MEMDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1)) +#define PWRSTAT_COREDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0)) + +/* Virtual IDs for using with xtensa_debug_ops API */ +enum xtensa_dm_reg { + /* TRAX Registers */ + XDMREG_TRAXID = 0x00, + XDMREG_TRAXCTRL, + XDMREG_TRAXSTAT, + XDMREG_TRAXDATA, + XDMREG_TRAXADDR, + XDMREG_TRIGGERPC, + XDMREG_PCMATCHCTRL, + XDMREG_DELAYCNT, + XDMREG_MEMADDRSTART, + XDMREG_MEMADDREND, + XDMREG_DEBUGPC,/*Unsupported, undocumented, may not be present*/ + XDMREG_EXTTIMELO, + XDMREG_EXTTIMEHI, + XDMREG_TRAXRSVD48, + XDMREG_TRAXRSVD4C, + XDMREG_TRAXRSVD50, + XDMREG_TRAXRSVD54, + XDMREG_TRAXRSVD58, + XDMREG_TRAXRSVD5C, + XDMREG_TRAXRSVD60, + XDMREG_TRAXRSVD64, + XDMREG_TRAXRSVD68, + XDMREG_TRAXRSVD6C, + XDMREG_TRAXRSVD70, + XDMREG_TRAXRSVD74, + XDMREG_CONFIGID0, + XDMREG_CONFIGID1, + + /* Performance Monitor Registers */ + XDMREG_PMG, + XDMREG_INTPC, + XDMREG_PM0, + XDMREG_PM1, + XDMREG_PM2, + XDMREG_PM3, + XDMREG_PM4, + XDMREG_PM5, + XDMREG_PM6, + XDMREG_PM7, + XDMREG_PMCTRL0, + XDMREG_PMCTRL1, + XDMREG_PMCTRL2, + XDMREG_PMCTRL3, + XDMREG_PMCTRL4, + XDMREG_PMCTRL5, + XDMREG_PMCTRL6, + XDMREG_PMCTRL7, + XDMREG_PMSTAT0, + XDMREG_PMSTAT1, + XDMREG_PMSTAT2, + XDMREG_PMSTAT3, + XDMREG_PMSTAT4, + XDMREG_PMSTAT5, + XDMREG_PMSTAT6, + XDMREG_PMSTAT7, + + /* OCD Registers */ + XDMREG_OCDID, + XDMREG_DCRCLR, + XDMREG_DCRSET, + XDMREG_DSR, + XDMREG_DDR, + XDMREG_DDREXEC, + XDMREG_DIR0EXEC, + XDMREG_DIR0, + XDMREG_DIR1, + XDMREG_DIR2, + XDMREG_DIR3, + XDMREG_DIR4, + XDMREG_DIR5, + XDMREG_DIR6, + XDMREG_DIR7, + + /* Misc Registers */ + XDMREG_ERISTAT, + + /* CoreSight Registers */ + XDMREG_ITCTRL, + XDMREG_CLAIMSET, + XDMREG_CLAIMCLR, + XDMREG_LOCKACCESS, + XDMREG_LOCKSTATUS, + XDMREG_AUTHSTATUS, + XDMREG_DEVID, + XDMREG_DEVTYPE, + XDMREG_PERID4, + XDMREG_PERID5, + XDMREG_PERID6, + XDMREG_PERID7, + XDMREG_PERID0, + XDMREG_PERID1, + XDMREG_PERID2, + XDMREG_PERID3, + XDMREG_COMPID0, + XDMREG_COMPID1, + XDMREG_COMPID2, + XDMREG_COMPID3, + + XDMREG_NUM +}; + +/* Debug Module Register offsets within Nexus (NAR) or APB */ +struct xtensa_dm_reg_offsets { + uint8_t nar; + uint16_t apb; +}; + +/* Debug Module Register offset structure; must include XDMREG_NUM entries */ +#define XTENSA_DM_REG_OFFSETS { \ + /* TRAX Registers */ \ + { .nar = 0x00, .apb = 0x0000 }, /* XDMREG_TRAXID */ \ + { .nar = 0x01, .apb = 0x0004 }, /* XDMREG_TRAXCTRL */ \ + { .nar = 0x02, .apb = 0x0008 }, /* XDMREG_TRAXSTAT */ \ + { .nar = 0x03, .apb = 0x000c }, /* XDMREG_TRAXDATA */ \ + { .nar = 0x04, .apb = 0x0010 }, /* XDMREG_TRAXADDR */ \ + { .nar = 0x05, .apb = 0x0014 }, /* XDMREG_TRIGGERPC */ \ + { .nar = 0x06, .apb = 0x0018 }, /* XDMREG_PCMATCHCTRL */ \ + { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \ + { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \ + { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \ + { .nar = 0x0f, .apb = 0x003c }, /* XDMREG_DEBUGPC */ \ + { .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */ \ + { .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */ \ + { .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */ \ + { .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */ \ + { .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */ \ + { .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */ \ + { .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */ \ + { .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */ \ + { .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */ \ + { .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */ \ + { .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */ \ + { .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */ \ + { .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */ \ + { .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */ \ + { .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */ \ + { .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */ \ + \ + /* Performance Monitor Registers */ \ + { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \ + { .nar = 0x24, .apb = 0x1010 }, /* XDMREG_INTPC */ \ + { .nar = 0x28, .apb = 0x1080 }, /* XDMREG_PM0 */ \ + { .nar = 0x29, .apb = 0x1084 }, /* XDMREG_PM1 */ \ + { .nar = 0x2a, .apb = 0x1088 }, /* XDMREG_PM2 */ \ + { .nar = 0x2b, .apb = 0x108c }, /* XDMREG_PM3 */ \ + { .nar = 0x2c, .apb = 0x1090 }, /* XDMREG_PM4 */ \ + { .nar = 0x2d, .apb = 0x1094 }, /* XDMREG_PM5 */ \ + { .nar = 0x2e, .apb = 0x1098 }, /* XDMREG_PM6 */ \ + { .nar = 0x2f, .apb = 0x109c }, /* XDMREG_PM7 */ \ + { .nar = 0x30, .apb = 0x1100 }, /* XDMREG_PMCTRL0 */ \ + { .nar = 0x31, .apb = 0x1104 }, /* XDMREG_PMCTRL1 */ \ + { .nar = 0x32, .apb = 0x1108 }, /* XDMREG_PMCTRL2 */ \ + { .nar = 0x33, .apb = 0x110c }, /* XDMREG_PMCTRL3 */ \ + { .nar = 0x34, .apb = 0x1110 }, /* XDMREG_PMCTRL4 */ \ + { .nar = 0x35, .apb = 0x1114 }, /* XDMREG_PMCTRL5 */ \ + { .nar = 0x36, .apb = 0x1118 }, /* XDMREG_PMCTRL6 */ \ + { .nar = 0x37, .apb = 0x111c }, /* XDMREG_PMCTRL7 */ \ + { .nar = 0x38, .apb = 0x1180 }, /* XDMREG_PMSTAT0 */ \ + { .nar = 0x39, .apb = 0x1184 }, /* XDMREG_PMSTAT1 */ \ + { .nar = 0x3a, .apb = 0x1188 }, /* XDMREG_PMSTAT2 */ \ + { .nar = 0x3b, .apb = 0x118c }, /* XDMREG_PMSTAT3 */ \ + { .nar = 0x3c, .apb = 0x1190 }, /* XDMREG_PMSTAT4 */ \ + { .nar = 0x3d, .apb = 0x1194 }, /* XDMREG_PMSTAT5 */ \ + { .nar = 0x3e, .apb = 0x1198 }, /* XDMREG_PMSTAT6 */ \ + { .nar = 0x3f, .apb = 0x119c }, /* XDMREG_PMSTAT7 */ \ + \ + /* OCD Registers */ \ + { .nar = 0x40, .apb = 0x2000 }, /* XDMREG_OCDID */ \ + { .nar = 0x42, .apb = 0x2008 }, /* XDMREG_DCRCLR */ \ + { .nar = 0x43, .apb = 0x200c }, /* XDMREG_DCRSET */ \ + { .nar = 0x44, .apb = 0x2010 }, /* XDMREG_DSR */ \ + { .nar = 0x45, .apb = 0x2014 }, /* XDMREG_DDR */ \ + { .nar = 0x46, .apb = 0x2018 }, /* XDMREG_DDREXEC */ \ + { .nar = 0x47, .apb = 0x201c }, /* XDMREG_DIR0EXEC */ \ + { .nar = 0x48, .apb = 0x2020 }, /* XDMREG_DIR0 */ \ + { .nar = 0x49, .apb = 0x2024 }, /* XDMREG_DIR1 */ \ + { .nar = 0x4a, .apb = 0x2028 }, /* XDMREG_DIR2 */ \ + { .nar = 0x4b, .apb = 0x202c }, /* XDMREG_DIR3 */ \ + { .nar = 0x4c, .apb = 0x2030 }, /* XDMREG_DIR4 */ \ + { .nar = 0x4d, .apb = 0x2034 }, /* XDMREG_DIR5 */ \ + { .nar = 0x4e, .apb = 0x2038 }, /* XDMREG_DIR6 */ \ + { .nar = 0x4f, .apb = 0x203c }, /* XDMREG_DIR7 */ \ + \ + /* Misc Registers */ \ + { .nar = 0x5a, .apb = 0x3028 }, /* XDMREG_ERISTAT */ \ + \ + /* CoreSight Registers */ \ + { .nar = 0x60, .apb = 0x3f00 }, /* XDMREG_ITCTRL */ \ + { .nar = 0x68, .apb = 0x3fa0 }, /* XDMREG_CLAIMSET */ \ + { .nar = 0x69, .apb = 0x3fa4 }, /* XDMREG_CLAIMCLR */ \ + { .nar = 0x6c, .apb = 0x3fb0 }, /* XDMREG_LOCKACCESS */ \ + { .nar = 0x6d, .apb = 0x3fb4 }, /* XDMREG_LOCKSTATUS */ \ + { .nar = 0x6e, .apb = 0x3fb8 }, /* XDMREG_AUTHSTATUS */ \ + { .nar = 0x72, .apb = 0x3fc8 }, /* XDMREG_DEVID */ \ + { .nar = 0x73, .apb = 0x3fcc }, /* XDMREG_DEVTYPE */ \ + { .nar = 0x74, .apb = 0x3fd0 }, /* XDMREG_PERID4 */ \ + { .nar = 0x75, .apb = 0x3fd4 }, /* XDMREG_PERID5 */ \ + { .nar = 0x76, .apb = 0x3fd8 }, /* XDMREG_PERID6 */ \ + { .nar = 0x77, .apb = 0x3fdc }, /* XDMREG_PERID7 */ \ + { .nar = 0x78, .apb = 0x3fe0 }, /* XDMREG_PERID0 */ \ + { .nar = 0x79, .apb = 0x3fe4 }, /* XDMREG_PERID1 */ \ + { .nar = 0x7a, .apb = 0x3fe8 }, /* XDMREG_PERID2 */ \ + { .nar = 0x7b, .apb = 0x3fec }, /* XDMREG_PERID3 */ \ + { .nar = 0x7c, .apb = 0x3ff0 }, /* XDMREG_COMPID0 */ \ + { .nar = 0x7d, .apb = 0x3ff4 }, /* XDMREG_COMPID1 */ \ + { .nar = 0x7e, .apb = 0x3ff8 }, /* XDMREG_COMPID2 */ \ + { .nar = 0x7f, .apb = 0x3ffc }, /* XDMREG_COMPID3 */ \ +} + +#define XTENSA_DM_APB_ALIGN 0x4000 + +/* OCD registers, bit definitions */ #define OCDDCR_ENABLEOCD BIT(0) #define OCDDCR_DEBUGINTERRUPT BIT(1) #define OCDDCR_INTERRUPTALLCONDS BIT(2) +#define OCDDCR_STEPREQUEST BIT(3) /* NX only */ #define OCDDCR_BREAKINEN BIT(16) #define OCDDCR_BREAKOUTEN BIT(17) #define OCDDCR_DEBUGSWACTIVE BIT(20) @@ -123,6 +294,8 @@ #define OCDDSR_EXECBUSY BIT(2) #define OCDDSR_EXECOVERRUN BIT(3) #define OCDDSR_STOPPED BIT(4) +#define OCDDSR_STOPCAUSE (0xF << 5) /* NX only */ +#define OCDDSR_STOPCAUSE_SHIFT (5) /* NX only */ #define OCDDSR_COREWROTEDDR BIT(10) #define OCDDSR_COREREADDDR BIT(11) #define OCDDSR_HOSTWROTEDDR BIT(14) @@ -139,12 +312,29 @@ #define OCDDSR_BREAKINITI BIT(26) #define OCDDSR_DBGMODPOWERON BIT(31) +/* NX stop cause */ +#define OCDDSR_STOPCAUSE_DI (0) /* Debug Interrupt */ +#define OCDDSR_STOPCAUSE_SS (1) /* Single-step completed */ +#define OCDDSR_STOPCAUSE_IB (2) /* HW breakpoint (IBREAKn match) */ +#define OCDDSR_STOPCAUSE_B1 (4) /* SW breakpoint (BREAK.1 instruction) */ +#define OCDDSR_STOPCAUSE_BN (5) /* SW breakpoint (BREAK.N instruction) */ +#define OCDDSR_STOPCAUSE_B (6) /* SW breakpoint (BREAK instruction) */ +#define OCDDSR_STOPCAUSE_DB0 (8) /* HW watchpoint (DBREAK0 match) */ +#define OCDDSR_STOPCAUSE_DB1 (9) /* HW watchpoint (DBREAK0 match) */ + +/* LX stop cause */ #define DEBUGCAUSE_IC BIT(0) /* ICOUNT exception */ #define DEBUGCAUSE_IB BIT(1) /* IBREAK exception */ #define DEBUGCAUSE_DB BIT(2) /* DBREAK exception */ #define DEBUGCAUSE_BI BIT(3) /* BREAK instruction encountered */ #define DEBUGCAUSE_BN BIT(4) /* BREAK.N instruction encountered */ #define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */ +#define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */ + +/* TRAXID */ +#define TRAXID_PRODNO_TRAX 0 /* TRAXID.PRODNO value for TRAX module */ +#define TRAXID_PRODNO_SHIFT 28 +#define TRAXID_PRODNO_MASK 0xf #define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */ #define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */ @@ -153,7 +343,7 @@ #define TRAXCTRL_CTIEN BIT(5) /* Cross-trigger enable */ #define TRAXCTRL_TMEN BIT(7) /* Tracemem Enable. Always set. */ #define TRAXCTRL_CNTU BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens. - *0 - every 32-bit word written to tracemem, 1 - every cpu instruction */ + * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */ #define TRAXCTRL_TSEN BIT(11) /* Undocumented/deprecated? */ #define TRAXCTRL_SMPER_SHIFT 12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */ #define TRAXCTRL_SMPER_MASK 0x07 /* Synchronization message period */ @@ -191,7 +381,7 @@ #define PCMATCHCTRL_PCML_SHIFT 0 /* Amount of lower bits to ignore in pc trigger register */ #define PCMATCHCTRL_PCML_MASK 0x1F #define PCMATCHCTRL_PCMS BIT(31) /* PC Match Sense, 0-match when procs PC is in-range, 1-match when - *out-of-range */ + * out-of-range */ #define XTENSA_MAX_PERF_COUNTERS 2 #define XTENSA_MAX_PERF_SELECT 32 @@ -205,20 +395,24 @@ struct xtensa_debug_ops { /** enable operation */ int (*queue_enable)(struct xtensa_debug_module *dm); /** register read. */ - int (*queue_reg_read)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data); + int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data); /** register write. */ - int (*queue_reg_write)(struct xtensa_debug_module *dm, unsigned int reg, uint32_t data); + int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data); }; +/* Xtensa power registers are 8 bits wide on JTAG interfaces but 32 bits wide + * when accessed via APB/DAP. In order to use DAP queuing APIs (for optimal + * performance), the XDM power register APIs take 32-bit register params. + */ struct xtensa_power_ops { /** register read. */ - int (*queue_reg_read)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, - uint8_t clear); + int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, + uint32_t clear); /** register write. */ - int (*queue_reg_write)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data); + int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data); }; -typedef uint8_t xtensa_pwrstat_t; +typedef uint32_t xtensa_pwrstat_t; typedef uint32_t xtensa_ocdid_t; typedef uint32_t xtensa_dsr_t; typedef uint32_t xtensa_traxstat_t; @@ -272,29 +466,62 @@ struct xtensa_perfmon_result { struct xtensa_debug_module_config { const struct xtensa_power_ops *pwr_ops; const struct xtensa_debug_ops *dbg_ops; + + /* Either JTAG or DAP structures will be populated */ struct jtag_tap *tap; void (*queue_tdi_idle)(struct target *target); void *queue_tdi_idle_arg; + + /* For targets conforming to ARM Debug Interface v5, + * "dap" references the Debug Access Port (DAP) + * used to make requests to the target; + * "debug_ap" is AP instance connected to processor + */ + struct adiv5_dap *dap; + struct adiv5_ap *debug_ap; + int debug_apsel; + uint32_t ap_offset; }; struct xtensa_debug_module { const struct xtensa_power_ops *pwr_ops; const struct xtensa_debug_ops *dbg_ops; + + /* Either JTAG or DAP structures will be populated */ struct jtag_tap *tap; void (*queue_tdi_idle)(struct target *target); void *queue_tdi_idle_arg; + /* DAP struct; AP instance connected to processor */ + struct adiv5_dap *dap; + struct adiv5_ap *debug_ap; + int debug_apsel; + struct xtensa_power_status power_status; struct xtensa_core_status core_status; xtensa_ocdid_t device_id; + uint32_t ap_offset; }; int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg); +void xtensa_dm_deinit(struct xtensa_debug_module *dm); +int xtensa_dm_poll(struct xtensa_debug_module *dm); +int xtensa_dm_examine(struct xtensa_debug_module *dm); int xtensa_dm_queue_enable(struct xtensa_debug_module *dm); -int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *value); -int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint32_t value); -int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, uint8_t clear); -int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data); +int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value); +int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value); +int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, + enum xtensa_dm_pwr_reg reg, + uint8_t *data, + uint32_t clear); +int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, + enum xtensa_dm_pwr_reg reg, + uint32_t data); + +static inline int xtensa_dm_queue_execute(struct xtensa_debug_module *dm) +{ + return dm->dap ? dap_run(dm->dap) : jtag_execute_queue(); +} static inline void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm) { @@ -324,6 +551,9 @@ static inline xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module return dm->core_status.dsr; } +int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val); +int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val); + int xtensa_dm_device_id_read(struct xtensa_debug_module *dm); static inline xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm) { @@ -341,19 +571,19 @@ static inline bool xtensa_dm_is_online(struct xtensa_debug_module *dm) int res = xtensa_dm_device_id_read(dm); if (res != ERROR_OK) return false; - return (dm->device_id != 0xffffffff && dm->device_id != 0); + return dm->device_id != 0xffffffff && dm->device_id != 0; } static inline bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm) { - return !(dm->power_status.prev_stat & PWRSTAT_DEBUGWASRESET) && - dm->power_status.stat & PWRSTAT_DEBUGWASRESET; + return !(dm->power_status.prev_stat & PWRSTAT_DEBUGWASRESET_DM(dm)) && + dm->power_status.stat & PWRSTAT_DEBUGWASRESET_DM(dm); } static inline bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm) { - return !(dm->power_status.prev_stat & PWRSTAT_COREWASRESET) && - dm->power_status.stat & PWRSTAT_COREWASRESET; + return !(dm->power_status.prev_stat & PWRSTAT_COREWASRESET_DM(dm)) && + dm->power_status.stat & PWRSTAT_COREWASRESET_DM(dm); } static inline bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm) diff --git a/src/target/xtensa/xtensa_fileio.c b/src/target/xtensa/xtensa_fileio.c new file mode 100644 index 0000000000..7628fbe31b --- /dev/null +++ b/src/target/xtensa/xtensa_fileio.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Xtensa Target File-I/O Support for OpenOCD * + * Copyright (C) 2020-2023 Cadence Design Systems, Inc. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xtensa_chip.h" +#include "xtensa_fileio.h" +#include "xtensa.h" + +#define XTENSA_SYSCALL(x) XT_INS_BREAK(x, 1, 14) +#define XTENSA_SYSCALL_SZ 3 +#define XTENSA_SYSCALL_LEN_MAX 255 + + +int xtensa_fileio_init(struct target *target) +{ + char *idmem = malloc(XTENSA_SYSCALL_LEN_MAX + 1); + target->fileio_info = malloc(sizeof(struct gdb_fileio_info)); + if (!idmem || !target->fileio_info) { + LOG_TARGET_ERROR(target, "Out of memory!"); + free(idmem); + free(target->fileio_info); + return ERROR_FAIL; + } + target->fileio_info->identifier = idmem; + return ERROR_OK; +} + +/** + * Checks for and processes an Xtensa File-IO request. + * + * Return ERROR_OK if request was found and handled; or + * return ERROR_FAIL if no request was detected. + */ +int xtensa_fileio_detect_proc(struct target *target) +{ + struct xtensa *xtensa = target_to_xtensa(target); + int retval; + + xtensa_reg_val_t dbg_cause = xtensa_cause_get(target); + if ((dbg_cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN)) == 0 || xtensa->halt_request) + return ERROR_FAIL; + + uint8_t brk_insn_buf[sizeof(uint32_t)] = {0}; + xtensa_reg_val_t pc = xtensa_reg_get(target, XT_REG_IDX_PC); + retval = target_read_memory(target, + pc, + XTENSA_SYSCALL_SZ, + 1, + (uint8_t *)brk_insn_buf); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read break instruction!"); + return ERROR_FAIL; + } + if (buf_get_u32(brk_insn_buf, 0, 32) != XTENSA_SYSCALL(xtensa)) + return ERROR_FAIL; + + LOG_TARGET_DEBUG(target, "File-I/O: syscall breakpoint found at 0x%x", pc); + xtensa->proc_syscall = true; + return ERROR_OK; +} + +int xtensa_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info) +{ + /* fill syscall parameters to file-I/O info */ + if (!fileio_info) { + LOG_ERROR("File-I/O data structure uninitialized"); + return ERROR_FAIL; + } + + struct xtensa *xtensa = target_to_xtensa(target); + if (!xtensa->proc_syscall) + return ERROR_FAIL; + + xtensa_reg_val_t syscall = xtensa_reg_get(target, XTENSA_SYSCALL_OP_REG); + xtensa_reg_val_t arg0 = xtensa_reg_get(target, XT_REG_IDX_A6); + xtensa_reg_val_t arg1 = xtensa_reg_get(target, XT_REG_IDX_A3); + xtensa_reg_val_t arg2 = xtensa_reg_get(target, XT_REG_IDX_A4); + xtensa_reg_val_t arg3 = xtensa_reg_get(target, XT_REG_IDX_A5); + int retval = ERROR_OK; + + LOG_TARGET_DEBUG(target, "File-I/O: syscall 0x%x 0x%x 0x%x 0x%x 0x%x", + syscall, arg0, arg1, arg2, arg3); + + switch (syscall) { + case XTENSA_SYSCALL_OPEN: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "open"); + fileio_info->param_1 = arg0; // pathp + fileio_info->param_2 = arg3; // len + fileio_info->param_3 = arg1; // flags + fileio_info->param_4 = arg2; // mode + break; + case XTENSA_SYSCALL_CLOSE: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "close"); + fileio_info->param_1 = arg0; // fd + break; + case XTENSA_SYSCALL_READ: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "read"); + fileio_info->param_1 = arg0; // fd + fileio_info->param_2 = arg1; // bufp + fileio_info->param_3 = arg2; // count + break; + case XTENSA_SYSCALL_WRITE: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "write"); + fileio_info->param_1 = arg0; // fd + fileio_info->param_2 = arg1; // bufp + fileio_info->param_3 = arg2; // count + break; + case XTENSA_SYSCALL_LSEEK: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "lseek"); + fileio_info->param_1 = arg0; // fd + fileio_info->param_2 = arg1; // offset + fileio_info->param_3 = arg2; // flags + break; + case XTENSA_SYSCALL_RENAME: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "rename"); + fileio_info->param_1 = arg0; // old pathp + fileio_info->param_2 = arg3; // old len + fileio_info->param_3 = arg1; // new pathp + fileio_info->param_4 = arg2; // new len + break; + case XTENSA_SYSCALL_UNLINK: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "unlink"); + fileio_info->param_1 = arg0; // pathnamep + fileio_info->param_2 = arg1; // len + break; + case XTENSA_SYSCALL_STAT: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "stat"); + fileio_info->param_1 = arg0; // pathnamep + fileio_info->param_2 = arg2; // len + fileio_info->param_3 = arg1; // bufp + break; + case XTENSA_SYSCALL_FSTAT: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "fstat"); + fileio_info->param_1 = arg0; // fd + fileio_info->param_2 = arg1; // bufp + break; + case XTENSA_SYSCALL_GETTIMEOFDAY: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "gettimeofday"); + fileio_info->param_1 = arg0; // tvp + fileio_info->param_2 = arg1; // tzp + break; + case XTENSA_SYSCALL_ISATTY: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "isatty"); + fileio_info->param_1 = arg0; // fd + break; + case XTENSA_SYSCALL_SYSTEM: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "system"); + fileio_info->param_1 = arg0; // cmdp + fileio_info->param_2 = arg1; // len + break; + default: + snprintf(fileio_info->identifier, XTENSA_SYSCALL_LEN_MAX, "unknown"); + LOG_TARGET_DEBUG(target, "File-I/O: syscall unknown (%d), pc=0x%08X", + syscall, xtensa_reg_get(target, XT_REG_IDX_PC)); + LOG_INFO("File-I/O: syscall unknown (%d), pc=0x%08X", + syscall, xtensa_reg_get(target, XT_REG_IDX_PC)); + retval = ERROR_FAIL; + break; + } + + return retval; +} + +int xtensa_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c) +{ + struct xtensa *xtensa = target_to_xtensa(target); + if (!xtensa->proc_syscall) + return ERROR_FAIL; + + LOG_TARGET_DEBUG(target, "File-I/O: syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s", + retcode, fileio_errno, ctrl_c ? "true" : "false"); + + /* If interrupt was requested before FIO completion (ERRNO==4), halt and repeat + * syscall. Otherwise, set File-I/O Ax and underlying ARx registers, increment PC. + * NOTE: sporadic cases of ((ERRNO==4) && !ctrl_c) were observed; most have ctrl_c. + */ + if (fileio_errno != 4) { + xtensa_reg_set_deep_relgen(target, XTENSA_SYSCALL_RETVAL_REG, retcode); + xtensa_reg_set_deep_relgen(target, XTENSA_SYSCALL_ERRNO_REG, fileio_errno); + + xtensa_reg_val_t pc = xtensa_reg_get(target, XT_REG_IDX_PC); + xtensa_reg_set(target, XT_REG_IDX_PC, pc + XTENSA_SYSCALL_SZ); + } + + xtensa->proc_syscall = false; + xtensa->halt_request = true; + return ctrl_c ? ERROR_FAIL : ERROR_OK; +} diff --git a/src/target/xtensa/xtensa_fileio.h b/src/target/xtensa/xtensa_fileio.h new file mode 100644 index 0000000000..5e1af5f864 --- /dev/null +++ b/src/target/xtensa/xtensa_fileio.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Xtensa Target File-I/O Support for OpenOCD * + * Copyright (C) 2020-2023 Cadence Design Systems, Inc. * + ***************************************************************************/ + +#ifndef OPENOCD_TARGET_XTENSA_FILEIO_H +#define OPENOCD_TARGET_XTENSA_FILEIO_H + +#include <target/target.h> +#include <helper/command.h> +#include "xtensa.h" + +#define XTENSA_SYSCALL_OP_REG XT_REG_IDX_A2 +#define XTENSA_SYSCALL_RETVAL_REG XT_REG_IDX_A2 +#define XTENSA_SYSCALL_ERRNO_REG XT_REG_IDX_A3 + +#define XTENSA_SYSCALL_OPEN (-2) +#define XTENSA_SYSCALL_CLOSE (-3) +#define XTENSA_SYSCALL_READ (-4) +#define XTENSA_SYSCALL_WRITE (-5) +#define XTENSA_SYSCALL_LSEEK (-6) +#define XTENSA_SYSCALL_RENAME (-7) +#define XTENSA_SYSCALL_UNLINK (-8) +#define XTENSA_SYSCALL_STAT (-9) +#define XTENSA_SYSCALL_FSTAT (-10) +#define XTENSA_SYSCALL_GETTIMEOFDAY (-11) +#define XTENSA_SYSCALL_ISATTY (-12) +#define XTENSA_SYSCALL_SYSTEM (-13) + +int xtensa_fileio_init(struct target *target); +int xtensa_fileio_detect_proc(struct target *target); +int xtensa_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info); +int xtensa_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c); + +#endif /* OPENOCD_TARGET_XTENSA_FILEIO_H */ diff --git a/src/target/xtensa/xtensa_regs.h b/src/target/xtensa/xtensa_regs.h index 632400abf9..1d9d3657ac 100644 --- a/src/target/xtensa/xtensa_regs.h +++ b/src/target/xtensa/xtensa_regs.h @@ -2,10 +2,11 @@ /*************************************************************************** * Generic Xtensa target API for OpenOCD * + * Copyright (C) 2020-2022 Cadence Design Systems, Inc. * * Copyright (C) 2016-2019 Espressif Systems Ltd. * * Author: Angus Gratton gus@projectgus.com * - * Author: Jeroen Domburg <jeroen@espressif.com> * ***************************************************************************/ + #ifndef OPENOCD_TARGET_XTENSA_REGS_H #define OPENOCD_TARGET_XTENSA_REGS_H @@ -14,6 +15,7 @@ struct reg_arch_type; enum xtensa_reg_id { XT_REG_IDX_PC = 0, XT_REG_IDX_AR0, + XT_REG_IDX_ARFIRST = XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3, @@ -29,152 +31,23 @@ enum xtensa_reg_id { XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15, - XT_REG_IDX_AR16, - XT_REG_IDX_AR17, - XT_REG_IDX_AR18, - XT_REG_IDX_AR19, - XT_REG_IDX_AR20, - XT_REG_IDX_AR21, - XT_REG_IDX_AR22, - XT_REG_IDX_AR23, - XT_REG_IDX_AR24, - XT_REG_IDX_AR25, - XT_REG_IDX_AR26, - XT_REG_IDX_AR27, - XT_REG_IDX_AR28, - XT_REG_IDX_AR29, - XT_REG_IDX_AR30, - XT_REG_IDX_AR31, - XT_REG_IDX_AR32, - XT_REG_IDX_AR33, - XT_REG_IDX_AR34, - XT_REG_IDX_AR35, - XT_REG_IDX_AR36, - XT_REG_IDX_AR37, - XT_REG_IDX_AR38, - XT_REG_IDX_AR39, - XT_REG_IDX_AR40, - XT_REG_IDX_AR41, - XT_REG_IDX_AR42, - XT_REG_IDX_AR43, - XT_REG_IDX_AR44, - XT_REG_IDX_AR45, - XT_REG_IDX_AR46, - XT_REG_IDX_AR47, - XT_REG_IDX_AR48, - XT_REG_IDX_AR49, - XT_REG_IDX_AR50, - XT_REG_IDX_AR51, - XT_REG_IDX_AR52, - XT_REG_IDX_AR53, - XT_REG_IDX_AR54, - XT_REG_IDX_AR55, - XT_REG_IDX_AR56, - XT_REG_IDX_AR57, - XT_REG_IDX_AR58, - XT_REG_IDX_AR59, - XT_REG_IDX_AR60, - XT_REG_IDX_AR61, - XT_REG_IDX_AR62, - XT_REG_IDX_AR63, - XT_REG_IDX_LBEG, - XT_REG_IDX_LEND, - XT_REG_IDX_LCOUNT, - XT_REG_IDX_SAR, + XT_REG_IDX_ARLAST = 64, /* Max 64 ARs */ XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, - XT_REG_IDX_CONFIGID0, - XT_REG_IDX_CONFIGID1, XT_REG_IDX_PS, - XT_REG_IDX_THREADPTR, - XT_REG_IDX_BR, - XT_REG_IDX_SCOMPARE1, - XT_REG_IDX_ACCLO, - XT_REG_IDX_ACCHI, - XT_REG_IDX_M0, - XT_REG_IDX_M1, - XT_REG_IDX_M2, - XT_REG_IDX_M3, - XT_REG_IDX_F0, - XT_REG_IDX_F1, - XT_REG_IDX_F2, - XT_REG_IDX_F3, - XT_REG_IDX_F4, - XT_REG_IDX_F5, - XT_REG_IDX_F6, - XT_REG_IDX_F7, - XT_REG_IDX_F8, - XT_REG_IDX_F9, - XT_REG_IDX_F10, - XT_REG_IDX_F11, - XT_REG_IDX_F12, - XT_REG_IDX_F13, - XT_REG_IDX_F14, - XT_REG_IDX_F15, - XT_REG_IDX_FCR, - XT_REG_IDX_FSR, - XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, - XT_REG_IDX_MEMCTL, - XT_REG_IDX_ATOMCTL, + XT_REG_IDX_DDR, XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1, XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1, - XT_REG_IDX_EPC1, - XT_REG_IDX_EPC2, - XT_REG_IDX_EPC3, - XT_REG_IDX_EPC4, - XT_REG_IDX_EPC5, - XT_REG_IDX_EPC6, - XT_REG_IDX_EPC7, - XT_REG_IDX_DEPC, - XT_REG_IDX_EPS2, - XT_REG_IDX_EPS3, - XT_REG_IDX_EPS4, - XT_REG_IDX_EPS5, - XT_REG_IDX_EPS6, - XT_REG_IDX_EPS7, - XT_REG_IDX_EXCSAVE1, - XT_REG_IDX_EXCSAVE2, - XT_REG_IDX_EXCSAVE3, - XT_REG_IDX_EXCSAVE4, - XT_REG_IDX_EXCSAVE5, - XT_REG_IDX_EXCSAVE6, - XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE, - XT_REG_IDX_INTERRUPT, - XT_REG_IDX_INTSET, - XT_REG_IDX_INTCLEAR, - XT_REG_IDX_INTENABLE, - XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, - XT_REG_IDX_CCOUNT, - XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, - XT_REG_IDX_EXCVADDR, - XT_REG_IDX_CCOMPARE0, - XT_REG_IDX_CCOMPARE1, - XT_REG_IDX_CCOMPARE2, - XT_REG_IDX_MISC0, - XT_REG_IDX_MISC1, - XT_REG_IDX_MISC2, - XT_REG_IDX_MISC3, - XT_REG_IDX_LITBASE, - XT_REG_IDX_PTEVADDR, - XT_REG_IDX_RASID, - XT_REG_IDX_ITLBCFG, - XT_REG_IDX_DTLBCFG, - XT_REG_IDX_MEPC, - XT_REG_IDX_MEPS, - XT_REG_IDX_MESAVE, - XT_REG_IDX_MESR, - XT_REG_IDX_MECR, - XT_REG_IDX_MEVADDR, XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, @@ -191,77 +64,72 @@ enum xtensa_reg_id { XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15, - XT_REG_IDX_PWRCTL, - XT_REG_IDX_PWRSTAT, - XT_REG_IDX_ERISTAT, - XT_REG_IDX_CS_ITCTRL, - XT_REG_IDX_CS_CLAIMSET, - XT_REG_IDX_CS_CLAIMCLR, - XT_REG_IDX_CS_LOCKACCESS, - XT_REG_IDX_CS_LOCKSTATUS, - XT_REG_IDX_CS_AUTHSTATUS, - XT_REG_IDX_FAULT_INFO, - XT_REG_IDX_TRAX_ID, - XT_REG_IDX_TRAX_CTRL, - XT_REG_IDX_TRAX_STAT, - XT_REG_IDX_TRAX_DATA, - XT_REG_IDX_TRAX_ADDR, - XT_REG_IDX_TRAX_PCTRIGGER, - XT_REG_IDX_TRAX_PCMATCH, - XT_REG_IDX_TRAX_DELAY, - XT_REG_IDX_TRAX_MEMSTART, - XT_REG_IDX_TRAX_MEMEND, - XT_REG_IDX_PMG, - XT_REG_IDX_PMPC, - XT_REG_IDX_PM0, - XT_REG_IDX_PM1, - XT_REG_IDX_PMCTRL0, - XT_REG_IDX_PMCTRL1, - XT_REG_IDX_PMSTAT0, - XT_REG_IDX_PMSTAT1, - XT_REG_IDX_OCD_ID, - XT_REG_IDX_OCD_DCRCLR, - XT_REG_IDX_OCD_DCRSET, - XT_REG_IDX_OCD_DSR, - XT_REG_IDX_OCD_DDR, - XT_NUM_REGS, - /* chip-specific user registers go after ISA-defined ones */ - XT_USR_REG_START = XT_NUM_REGS + XT_NUM_REGS }; typedef uint32_t xtensa_reg_val_t; +#define XT_NUM_A_REGS 16 + enum xtensa_reg_type { XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */ XT_REG_USER = 1, /* User register, needs RUR to read */ XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */ XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */ XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window - *index */ + * index */ XT_REG_FR = 5, /* Floating-point register */ + XT_REG_TIE = 6, /* TIE (custom) register */ + XT_REG_OTHER = 7, /* Other (typically legacy) register */ + XT_REG_TYPE_NUM, + + /* enum names must be one of the above types + _VAL or _MASK */ + XT_REG_GENERAL_MASK = 0xFFC0, + XT_REG_GENERAL_VAL = 0x0100, + XT_REG_USER_MASK = 0xFF00, + XT_REG_USER_VAL = 0x0300, + XT_REG_SPECIAL_MASK = 0xFF00, + XT_REG_SPECIAL_VAL = 0x0200, + XT_REG_DEBUG_MASK = 0xFF00, + XT_REG_DEBUG_VAL = 0x0200, + XT_REG_RELGEN_MASK = 0xFFE0, + XT_REG_RELGEN_VAL = 0x0000, + XT_REG_FR_MASK = 0xFFF0, + XT_REG_FR_VAL = 0x0030, + XT_REG_TIE_MASK = 0xF000, + XT_REG_TIE_VAL = 0xF000, /* unused */ + XT_REG_OTHER_MASK = 0xFFFF, + XT_REG_OTHER_VAL = 0xF000, /* unused */ + + XT_REG_INDEX_MASK = 0x00FF }; enum xtensa_reg_flags { XT_REGF_NOREAD = 0x01, /* Register is write-only */ - XT_REGF_COPROC0 = 0x02 /* Can't be read if coproc0 isn't enabled */ + XT_REGF_COPROC0 = 0x02, /* Can't be read if coproc0 isn't enabled */ + XT_REGF_MASK = 0x03 }; struct xtensa_reg_desc { const char *name; + bool exist; unsigned int reg_num; /* ISA register num (meaning depends on register type) */ + unsigned int dbreg_num; /* Debugger-visible register num (reg type encoded) */ enum xtensa_reg_type type; enum xtensa_reg_flags flags; }; -struct xtensa_user_reg_desc { - const char *name; - /* ISA register num (meaning depends on register type) */ - unsigned int reg_num; - enum xtensa_reg_flags flags; - uint32_t size; - const struct reg_arch_type *type; -}; +#define _XT_MK_DBREGN(reg_num, reg_type) \ + ((reg_type ## _VAL) | (reg_num)) + +#define _XT_MK_DBREGN_MASK(reg_num, reg_mask) \ + ((reg_mask) | (reg_num)) + +#define XT_MK_REG_DESC(n, r, t, f) \ + { .name = (n), .exist = false, .reg_num = (r), \ + .dbreg_num = _XT_MK_DBREGN(r, t), .type = (t), \ + .flags = (f) } -extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS]; +extern struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS]; #endif /* OPENOCD_TARGET_XTENSA_REGS_H */ diff --git a/src/transport/transport.c b/src/transport/transport.c index b5eab0b784..5323a7ca0a 100644 --- a/src/transport/transport.c +++ b/src/transport/transport.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2010 by David Brownell @@ -30,6 +30,9 @@ * messaging and error handling. */ +#include <helper/align.h> +#include <helper/bits.h> +#include <helper/list.h> #include <helper/log.h> #include <helper/replacements.h> #include <transport/transport.h> @@ -43,24 +46,82 @@ extern struct command_context *global_cmd_ctx; */ /** List of transports known to OpenOCD. */ -static struct transport *transport_list; +static const struct { + unsigned int id; + const char *name; + const char *full_name; + const char *deprecated_name; +} transport_names[] = { + { TRANSPORT_JTAG, "jtag", "jtag", NULL, }, + { TRANSPORT_SWD, "swd", "swd", NULL, }, + { TRANSPORT_HLA_JTAG, "jtag", "jtag (hla)", "hla_jtag", }, + { TRANSPORT_HLA_SWD, "swd", "swd (hla)", "hla_swd", }, + { TRANSPORT_DAPDIRECT_JTAG, "jtag", "jtag (dapdirect)", "dapdirect_jtag", }, + { TRANSPORT_DAPDIRECT_SWD, "swd", "swd (dapdirect)", "dapdirect_swd", }, + { TRANSPORT_SWIM, "swim", "swim", NULL, }, +}; + +/** List of transports registered in OpenOCD, alphabetically sorted per name. */ +static OOCD_LIST_HEAD(transport_list); + +/** + * Bitmask of transport IDs which the currently selected debug adapter supports. + * This is declared by the time that adapter is fully set up. + */ +static unsigned int allowed_transports; + +/** + * Transport ID auto-selected when not specified by the user. + */ +static unsigned int preferred_transport; /** - * NULL-terminated Vector of names of transports which the - * currently selected debug adapter supports. This is declared - * by the time that adapter is fully set up. + * Adapter supports a single transport; it has been auto-selected */ -static const char * const *allowed_transports; +static bool transport_single_is_autoselected; /** * The transport being used for the current OpenOCD session. */ static struct transport *session; -static int transport_select(struct command_context *ctx, const char *name) +const char *transport_name(unsigned int id) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(transport_names); i++) + if (id == transport_names[i].id) + return transport_names[i].name; + + return NULL; +} + +static const char *transport_full_name(unsigned int id) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(transport_names); i++) + if (id == transport_names[i].id) + return transport_names[i].full_name; + + return NULL; +} + +static const char *transport_deprecated_name(unsigned int id) +{ + for (unsigned int i = 0; i < ARRAY_SIZE(transport_names); i++) + if (id == transport_names[i].id) + return transport_names[i].deprecated_name; + + return NULL; +} + +static bool is_transport_id_valid(unsigned int id) +{ + return (id != 0) && ((id & ~TRANSPORT_VALID_MASK) == 0) && IS_PWR_OF_2(id); +} + +static int transport_select(struct command_context *ctx, unsigned int transport_id) { /* name may only identify a known transport; * caller guarantees session's transport isn't yet set.*/ - for (struct transport *t = transport_list; t; t = t->next) { - if (strcmp(t->name, name) == 0) { + struct transport *t; + list_for_each_entry(t, &transport_list, lh) { + if (t->id == transport_id) { int retval = t->select(ctx); /* select() registers commands specific to this * transport, and may also reset the link, e.g. @@ -69,12 +130,14 @@ static int transport_select(struct command_context *ctx, const char *name) if (retval == ERROR_OK) session = t; else - LOG_ERROR("Error selecting '%s' as transport", t->name); + LOG_ERROR("Error selecting '%s' as transport", + transport_full_name(transport_id)); return retval; } } - LOG_ERROR("No transport named '%s' is available.", name); + LOG_ERROR("No transport named '%s' is available.", + transport_full_name(transport_id)); return ERROR_FAIL; } @@ -83,29 +146,48 @@ static int transport_select(struct command_context *ctx, const char *name) * to declare the set of transports supported by an adapter. When * there is only one member of that set, it is automatically selected. */ -int allow_transports(struct command_context *ctx, const char * const *vector) +int allow_transports(struct command_context *ctx, unsigned int transport_ids, + unsigned int transport_preferred_id) { - /* NOTE: caller is required to provide only a list - * of *valid* transport names - * - * REVISIT should we validate that? and insist there's - * at least one non-NULL element in that list? - * - * ... allow removals, e.g. external strapping prevents use - * of one transport; C code should be definitive about what - * can be used when all goes well. - */ if (allowed_transports || session) { LOG_ERROR("Can't modify the set of allowed transports."); return ERROR_FAIL; } - allowed_transports = vector; + /* validate the values in transport_ids and transport_preferred_id */ + if (transport_ids == 0 || (transport_ids & ~TRANSPORT_VALID_MASK) != 0) { + LOG_ERROR("BUG: Unknown transport IDs %lu", transport_ids & ~TRANSPORT_VALID_MASK); + return ERROR_FAIL; + } + + if ((transport_ids & transport_preferred_id) == 0 + || !IS_PWR_OF_2(transport_preferred_id)) { + LOG_ERROR("BUG: Invalid adapter transport_preferred_id"); + return ERROR_FAIL; + } + + unsigned int mask = transport_ids & + (TRANSPORT_JTAG | TRANSPORT_HLA_JTAG | TRANSPORT_DAPDIRECT_JTAG); + if (mask && !IS_PWR_OF_2(mask)) { + LOG_ERROR("BUG: Multiple JTAG transports"); + return ERROR_FAIL; + } + + mask = transport_ids & + (TRANSPORT_SWD | TRANSPORT_HLA_SWD | TRANSPORT_DAPDIRECT_SWD); + if (mask && !IS_PWR_OF_2(mask)) { + LOG_ERROR("BUG: Multiple SWD transports"); + return ERROR_FAIL; + } + + allowed_transports = transport_ids; + preferred_transport = transport_preferred_id; /* autoselect if there's no choice ... */ - if (!vector[1]) { - LOG_INFO("only one transport option; autoselect '%s'", vector[0]); - return transport_select(ctx, vector[0]); + if (IS_PWR_OF_2(transport_ids)) { + LOG_DEBUG("only one transport option; autoselecting '%s'", transport_name(transport_ids)); + transport_single_is_autoselected = true; + return transport_select(ctx, transport_ids); } return ERROR_OK; @@ -130,20 +212,33 @@ int transport_register(struct transport *new_transport) { struct transport *t; - for (t = transport_list; t; t = t->next) { - if (strcmp(t->name, new_transport->name) == 0) { - LOG_ERROR("transport name already used"); + if (!is_transport_id_valid(new_transport->id)) { + LOG_ERROR("invalid transport ID 0x%x", new_transport->id); + return ERROR_FAIL; + } + + list_for_each_entry(t, &transport_list, lh) { + if (t->id == new_transport->id) { + LOG_ERROR("transport '%s' already registered", + transport_name(t->id)); return ERROR_FAIL; } } if (!new_transport->select || !new_transport->init) - LOG_ERROR("invalid transport %s", new_transport->name); + LOG_ERROR("invalid transport %s", + transport_full_name(new_transport->id)); - /* splice this into the list */ - new_transport->next = transport_list; - transport_list = new_transport; - LOG_DEBUG("register '%s'", new_transport->name); + /* splice this into the list, sorted in alphabetic order */ + list_for_each_entry(t, &transport_list, lh) { + if (strcmp(transport_name(t->id), + transport_name(new_transport->id)) >= 0) + break; + } + list_add_tail(&new_transport->lh, &t->lh); + + LOG_DEBUG("register '%s' (ID %d)", + transport_full_name(new_transport->id), new_transport->id); return ERROR_OK; } @@ -160,60 +255,20 @@ struct transport *get_current_transport(void) return session; } +const char *get_current_transport_name(void) +{ + if (!session || !is_transport_id_valid(session->id)) + return NULL; + + return transport_full_name(session->id); +} + /*-----------------------------------------------------------------------*/ /* * Infrastructure for Tcl interface to transports. */ -/** - * Makes and stores a copy of a set of transports passed as - * parameters to a command. - * - * @param vector where the resulting copy is stored, as an argv-style - * NULL-terminated vector. - */ -COMMAND_HELPER(transport_list_parse, char ***vector) -{ - char **argv; - unsigned n = CMD_ARGC; - unsigned j = 0; - - *vector = NULL; - - if (n < 1) - return ERROR_COMMAND_SYNTAX_ERROR; - - /* our return vector must be NULL terminated */ - argv = calloc(n + 1, sizeof(char *)); - if (!argv) - return ERROR_FAIL; - - for (unsigned i = 0; i < n; i++) { - struct transport *t; - - for (t = transport_list; t; t = t->next) { - if (strcmp(t->name, CMD_ARGV[i]) != 0) - continue; - argv[j++] = strdup(CMD_ARGV[i]); - break; - } - if (!t) { - LOG_ERROR("no such transport '%s'", CMD_ARGV[i]); - goto fail; - } - } - - *vector = argv; - return ERROR_OK; - -fail: - for (unsigned i = 0; i < n; i++) - free(argv[i]); - free(argv); - return ERROR_FAIL; -} - COMMAND_HANDLER(handle_transport_init) { LOG_DEBUG("%s", __func__); @@ -222,14 +277,18 @@ COMMAND_HANDLER(handle_transport_init) /* no session transport configured, print transports then fail */ LOG_ERROR("Transports available:"); - const char * const *vector = allowed_transports; - while (*vector) { - LOG_ERROR("%s", *vector); - vector++; + for (unsigned int i = BIT(0); i & TRANSPORT_VALID_MASK; i <<= 1) { + if (i & allowed_transports) + LOG_ERROR("%s", transport_full_name(i)); } return ERROR_FAIL; } + if (transport_single_is_autoselected) + LOG_WARNING("DEPRECATED: auto-selecting transport \"%s\". " + "Use 'transport select %s' to suppress this message.", + transport_full_name(session->id), transport_name(session->id)); + return session->init(CMD_CTX); } @@ -240,8 +299,15 @@ COMMAND_HANDLER(handle_transport_list) command_print(CMD, "The following transports are available:"); - for (struct transport *t = transport_list; t; t = t->next) - command_print(CMD, "\t%s", t->name); + struct transport *t; + const char *prev_name = NULL; + /* list is sorted, don't print duplicated transport names */ + list_for_each_entry(t, &transport_list, lh) { + const char *name = transport_name(t->id); + if (!prev_name || strcmp(prev_name, name)) + command_print(CMD, "\t%s", name); + prev_name = name; + } return ERROR_OK; } @@ -252,64 +318,75 @@ COMMAND_HANDLER(handle_transport_list) * set supported by the debug adapter being used. Return value * is scriptable (allowing "if swd then..." etc). */ -static int jim_transport_select(Jim_Interp *interp, int argc, Jim_Obj * const *argv) +COMMAND_HANDLER(handle_transport_select) { - int res; - switch (argc) { - case 1: /* autoselect if necessary, then return/display current config */ - if (!session) { - if (!allowed_transports) { - LOG_ERROR("Debug adapter does not support any transports? Check config file order."); - return JIM_ERR; - } - LOG_INFO("auto-selecting first available session transport \"%s\". " - "To override use 'transport select <transport>'.", allowed_transports[0]); - res = transport_select(global_cmd_ctx, allowed_transports[0]); - if (res != JIM_OK) - return res; - } - Jim_SetResultString(interp, session->name, -1); - return JIM_OK; - case 2: /* assign */ - if (session) { - if (!strcmp(session->name, argv[1]->bytes)) { - LOG_WARNING("Transport \"%s\" was already selected", session->name); - Jim_SetResultString(interp, session->name, -1); - return JIM_OK; - } else { - LOG_ERROR("Can't change session's transport after the initial selection was made"); - return JIM_ERR; - } - } + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; - /* Is this transport supported by our debug adapter? - * Example, "JTAG-only" means SWD is not supported. - * - * NOTE: requires adapter to have been set up, with - * transports declared via C. - */ + if (CMD_ARGC == 0) { + /* autoselect if necessary, then return/display current config */ + if (!session) { if (!allowed_transports) { - LOG_ERROR("Debug adapter doesn't support any transports?"); - return JIM_ERR; + command_print(CMD, "Debug adapter does not support any transports? Check config file order."); + return ERROR_FAIL; } + LOG_WARNING("DEPRECATED: auto-selecting transport \"%s\". " + "Use 'transport select %s' to suppress this message.", + transport_full_name(preferred_transport), + transport_name(preferred_transport)); + int retval = transport_select(CMD_CTX, preferred_transport); + if (retval != ERROR_OK) + return retval; + } + command_print(CMD, "%s", transport_full_name(session->id)); + return ERROR_OK; + } - for (unsigned i = 0; allowed_transports[i]; i++) { - - if (strcmp(allowed_transports[i], argv[1]->bytes) == 0) { - if (transport_select(global_cmd_ctx, argv[1]->bytes) == ERROR_OK) { - Jim_SetResultString(interp, session->name, -1); - return JIM_OK; - } - return JIM_ERR; - } + /* assign transport */ + if (session) { + if (!strcmp(transport_name(session->id), CMD_ARGV[0]) + || (transport_deprecated_name(session->id) + && !strcmp(transport_deprecated_name(session->id), CMD_ARGV[0]))) { + if (transport_single_is_autoselected) { + /* Nothing to do, but also nothing to complain */ + transport_single_is_autoselected = false; + return ERROR_OK; } + LOG_WARNING("Transport \"%s\" was already selected", CMD_ARGV[0]); + return ERROR_OK; + } + command_print(CMD, "Can't change session's transport after the initial selection was made"); + return ERROR_FAIL; + } - LOG_ERROR("Debug adapter doesn't support '%s' transport", argv[1]->bytes); - return JIM_ERR; - default: - Jim_WrongNumArgs(interp, 1, argv, "[too many parameters]"); - return JIM_ERR; + /* Is this transport supported by our debug adapter? + * Example, "JTAG-only" means SWD is not supported. + * + * NOTE: requires adapter to have been set up, with + * transports declared via C. + */ + if (!allowed_transports) { + command_print(CMD, "Debug adapter doesn't support any transports?"); + return ERROR_FAIL; } + + for (unsigned int i = BIT(0); i & TRANSPORT_VALID_MASK; i <<= 1) { + if (!(i & allowed_transports)) + continue; + + if (!strcmp(transport_name(i), CMD_ARGV[0])) + return transport_select(CMD_CTX, i); + + if (transport_deprecated_name(i) + && !strcmp(transport_deprecated_name(i), CMD_ARGV[0])) { + LOG_WARNING("DEPRECATED! use 'transport select %s', not 'transport select %s'", + transport_name(i), transport_deprecated_name(i)); + return transport_select(CMD_CTX, i); + } + } + + command_print(CMD, "Debug adapter doesn't support '%s' transport", CMD_ARGV[0]); + return ERROR_FAIL; } static const struct command_registration transport_commands[] = { @@ -333,7 +410,7 @@ static const struct command_registration transport_commands[] = { }, { .name = "select", - .jim_handler = jim_transport_select, + .handler = handle_transport_select, .mode = COMMAND_ANY, .help = "Select this session's transport", .usage = "[transport_name]", diff --git a/src/transport/transport.h b/src/transport/transport.h index 00d8b07e11..5445bcf3b2 100644 --- a/src/transport/transport.h +++ b/src/transport/transport.h @@ -12,7 +12,27 @@ #include "config.h" #endif +#include "helper/bits.h" #include "helper/command.h" +#include "helper/list.h" + +#define TRANSPORT_JTAG BIT(0) +#define TRANSPORT_SWD BIT(1) +#define TRANSPORT_HLA_JTAG BIT(2) +#define TRANSPORT_HLA_SWD BIT(3) +#define TRANSPORT_DAPDIRECT_JTAG BIT(4) +#define TRANSPORT_DAPDIRECT_SWD BIT(5) +#define TRANSPORT_SWIM BIT(6) + +/* mask for valid ID */ +#define TRANSPORT_VALID_MASK \ + (TRANSPORT_JTAG | \ + TRANSPORT_SWD | \ + TRANSPORT_HLA_JTAG | \ + TRANSPORT_HLA_SWD | \ + TRANSPORT_DAPDIRECT_JTAG | \ + TRANSPORT_DAPDIRECT_SWD | \ + TRANSPORT_SWIM) /** * Wrapper for transport lifecycle operations. @@ -34,11 +54,10 @@ */ struct transport { /** - * Each transport has a unique name, used to select it - * from among the alternatives. Examples might include - * "jtag", * "swd", "AVR_ISP" and more. + * Each transport has a unique ID, used to select it + * from among the alternatives. */ - const char *name; + unsigned int id; /** * When a transport is selected, this method registers @@ -66,20 +85,23 @@ struct transport { int (*override_target)(const char **targetname); /** - * Transports are stored in a singly linked list. + * Transports are stored in a linked list. */ - struct transport *next; + struct list_head lh; }; int transport_register(struct transport *new_transport); struct transport *get_current_transport(void); -int transport_register_commands(struct command_context *ctx); +const char *get_current_transport_name(void); + +const char *transport_name(unsigned int id); -COMMAND_HELPER(transport_list_parse, char ***vector); +int transport_register_commands(struct command_context *ctx); -int allow_transports(struct command_context *ctx, const char * const *vector); +int allow_transports(struct command_context *ctx, unsigned int transport_ids, + unsigned int transport_preferred_id); bool transport_is_jtag(void); bool transport_is_swd(void); diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c index 153cc15f9d..617c2f423e 100644 --- a/src/xsvf/xsvf.c +++ b/src/xsvf/xsvf.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * @@ -111,10 +111,10 @@ TDO (1); static int xsvf_fd; -/* map xsvf tap state to an openocd "tap_state_t" */ -static tap_state_t xsvf_to_tap(int xsvf_state) +/* map xsvf tap state to an openocd "enum tap_state" */ +static enum tap_state xsvf_to_tap(int xsvf_state) { - tap_state_t ret; + enum tap_state ret; switch (xsvf_state) { case XSV_RESET: @@ -196,16 +196,16 @@ COMMAND_HANDLER(handle_xsvf_command) int xruntest = 0; /* number of TCK cycles OR *microseconds */ int xrepeat = 0; /* number of retries */ - tap_state_t xendir = TAP_IDLE; /* see page 8 of the SVF spec, initial + enum tap_state xendir = TAP_IDLE; /* see page 8 of the SVF spec, initial *xendir to be TAP_IDLE */ - tap_state_t xenddr = TAP_IDLE; + enum tap_state xenddr = TAP_IDLE; uint8_t opcode; uint8_t uc = 0; long file_offset = 0; int loop_count = 0; - tap_state_t loop_state = TAP_IDLE; + enum tap_state loop_state = TAP_IDLE; int loop_clocks = 0; int loop_usecs = 0; @@ -216,8 +216,8 @@ COMMAND_HANDLER(handle_xsvf_command) int verbose = 1; bool collecting_path = false; - tap_state_t path[XSTATE_MAX_PATH]; - unsigned pathlen = 0; + enum tap_state path[XSTATE_MAX_PATH]; + unsigned int pathlen = 0; /* a flag telling whether to clock TCK during waits, * or simply sleep, controlled by virt2 @@ -272,7 +272,7 @@ COMMAND_HANDLER(handle_xsvf_command) * or terminate a path. */ if (collecting_path) { - tap_state_t mystate; + enum tap_state mystate; switch (opcode) { case XCOMMENT: @@ -455,7 +455,7 @@ COMMAND_HANDLER(handle_xsvf_command) * will be skipped entirely if xrepeat is set to zero. */ - static tap_state_t exception_path[] = { + static enum tap_state exception_path[] = { TAP_DREXIT2, TAP_DRSHIFT, TAP_DREXIT1, @@ -563,7 +563,7 @@ COMMAND_HANDLER(handle_xsvf_command) case XSTATE: { - tap_state_t mystate; + enum tap_state mystate; if (read(xsvf_fd, &uc, 1) < 0) { do_abort = 1; @@ -654,7 +654,7 @@ COMMAND_HANDLER(handle_xsvf_command) uint8_t short_buf[2]; uint8_t *ir_buf; int bitcount; - tap_state_t my_end_state = xruntest ? TAP_IDLE : xendir; + enum tap_state my_end_state = xruntest ? TAP_IDLE : xendir; if (opcode == XSIR) { /* one byte bitcount */ @@ -744,15 +744,15 @@ COMMAND_HANDLER(handle_xsvf_command) uint8_t end; uint8_t delay_buf[4]; - tap_state_t wait_state; - tap_state_t end_state; + enum tap_state wait_state; + enum tap_state end_state; int delay; if (read(xsvf_fd, &wait_local, 1) < 0 - || read(xsvf_fd, &end, 1) < 0 - || read(xsvf_fd, delay_buf, 4) < 0) { - do_abort = 1; - break; + || read(xsvf_fd, &end, 1) < 0 + || read(xsvf_fd, delay_buf, 4) < 0) { + do_abort = 1; + break; } wait_state = xsvf_to_tap(wait_local); @@ -788,8 +788,8 @@ COMMAND_HANDLER(handle_xsvf_command) uint8_t usecs_buf[4]; uint8_t wait_local; uint8_t end; - tap_state_t wait_state; - tap_state_t end_state; + enum tap_state wait_state; + enum tap_state end_state; int clock_count; int usecs; diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg index edb529c889..7c2ce06773 100644 --- a/tcl/board/actux3.cfg +++ b/tcl/board/actux3.cfg @@ -50,7 +50,7 @@ reset init # setup to debug u-boot in flash proc uboot_debug {} { - gdb_breakpoint_override hard + gdb breakpoint_override hard xscale vector_catch 0xFF xscale vector_table low 1 0xe59ff018 diff --git a/tcl/board/advantech_imx8qm_dmsse20.cfg b/tcl/board/advantech_imx8qm_dmsse20.cfg new file mode 100644 index 0000000000..a867b2de01 --- /dev/null +++ b/tcl/board/advantech_imx8qm_dmsse20.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for Advantech IMX8QM DMSSE20 +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + +# board has an i.MX8QM with 4 Cortex-A53 cores and 2 Cortex-A72 +set CHIPNAME imx8qm +set CHIPCORES 6 + +# source SoC configuration +source [find tcl/target/imx8qm.cfg] diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index a5831cd91c..22a38a7089 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -7,10 +7,6 @@ # # ################################################################################################# -# FIXME use some standard target config, maybe create one from this -# -# source [find target/...cfg] - source [find target/at91sam9g20.cfg] set _FLASHTYPE nandflash_cs3 @@ -47,7 +43,7 @@ proc read_register {register} { proc at91sam9g20_reset_start { } { - # Make sure that the the jtag is running slow, since there are a number of different ways the board + # Make sure that the jtag is running slow, since there are a number of different ways the board # can be configured coming into this state that can cause communication problems with the jtag # adapter. Also since this call can be made following a "reset init" where fast memory accesses # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower @@ -206,7 +202,7 @@ proc at91sam9g20_reset_init { } { mww 0xffffea00 0x3 mww 0x20000000 0 - # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting + # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting # memory location for the SDRAM. mww 0xffffea00 0x0 diff --git a/tcl/board/bemicro_cycloneiii.cfg b/tcl/board/bemicro_cycloneiii.cfg new file mode 100644 index 0000000000..3c92b500c1 --- /dev/null +++ b/tcl/board/bemicro_cycloneiii.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BeMicro Cyclone III + + +adapter driver ftdi +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +ftdi vid_pid 0x0403 0xa4a0 +reset_config none +transport select jtag + +adapter speed 10000 + +source [find fpga/altera-cycloneiii.cfg] + +#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf + +#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load cycloneiii.pld cycloneiii_blinker.rbf" +# "ipdbg create-hub cycloneiii.ipdbghub -tap cycloneiii.tap -ir 0x00e" +# "cycloneiii.ipdbghub ipdbg start -tool 0 -port 5555" + + +set JTAGSPI_CHAIN_ID cycloneiii.pld +source [find cpld/jtagspi.cfg] diff --git a/tcl/board/calao-usb-a9260.cfg b/tcl/board/calao-usb-a9260.cfg new file mode 100644 index 0000000000..52fede0fa5 --- /dev/null +++ b/tcl/board/calao-usb-a9260.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# CALAO Systems USB-A9260 (C01 and C02) + +adapter driver ftdi +ftdi device_desc "USB-A9260" +ftdi vid_pid 0x0403 0x6001 0x0403 0x6010 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 + +transport select jtag + +source [find target/at91sam9260.cfg] diff --git a/tcl/board/calao-usb-a9g20-c01.cfg b/tcl/board/calao-usb-a9g20-c01.cfg new file mode 100644 index 0000000000..d2017864a9 --- /dev/null +++ b/tcl/board/calao-usb-a9g20-c01.cfg @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# CALAO Systems USB-A9G20-C01 +# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang + +adapter driver ftdi +ftdi device_desc "USB-A9G20" +ftdi vid_pid 0x0403 0x6010 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 + +transport select jtag + +source [find target/at91sam9g20.cfg] +source [find mem_helper.tcl] + +proc at91sam9g20_reset_start { } { + + # Make sure that the jtag is running slow, since there are a number of different ways the board + # can be configured coming into this state that can cause communication problems with the jtag + # adapter. Also since this call can be made following a "reset init" where fast memory accesses + # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower + # jtag speed without causing GDB keep alive problem. + + arm7_9 fast_memory_access disable + adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. + halt 0 ;# Make sure processor is halted, or error will result in following steps. + wait_halt 10000 + # RSTC_MR : enable user reset, MMU may be enabled... use physical address + mww phys 0xfffffd08 0xa5000501 +} + +proc at91sam9g20_reset_init { } { + + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires + # a number of steps that must be carefully performed. The process outline below follows the + # recommended procedure outlined in the AT91SAM9G20 technical manual. + # + # Several key and very important things to keep in mind: + # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This + # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor + # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. + + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog. + + # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register. + + mww 0xfffffc20 0x00000002 + + # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132). + # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. + + mww 0xfffffc28 0x20843F02 + while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 } + + # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001300 + while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 } + + # Now change PMC_MCKR register to select PLLA. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001302 + while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 } + + # Processor and master clocks are now operating and stable at maximum frequency possible: + # -> MCLK = 133.000 MHz + # -> PCLK = 400.000 MHz + + # Switch to fast JTAG speed + + adapter speed 9500 + + # Enable faster DCC downloads. + + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable + + # To be able to use external SDRAM, several peripheral configuration registers must + # be modified. The first change is made to PIO_ASR to select peripheral functions + # for D15 through D31. The second change is made to the PIO_PDR register to disable + # this for D15 through D31. + + mww 0xfffff870 0xffff0000 + mww 0xfffff804 0xffff0000 + + # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller + # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on + # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller. + + mww 0xffffef1c 0x000000a + + # The USB-A9G20 Embedded computer has built-in NandFlash. The exact physical timing characteristics + # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting + # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. + + mww 0xffffec30 0x00020002 + mww 0xffffec34 0x04040404 + mww 0xffffec38 0x00070007 + mww 0xffffec3c 0x00030003 + + # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations + # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference + # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted + # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock + # of 133.000 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires: + # + # CAS latency = 3 cycles + # TXSR = 10 cycles + # TRAS = 6 cycles + # TRCD = 3 cycles + # TRP = 3 cycles + # TRC = 9 cycles + # TWR = 2 cycles + # 9 column, 13 row, 4 banks + # refresh equal to or less then 7.8 us for commercial/industrial rated devices + # + # Thus SDRAM_CR = 0xa6339279 + + mww 0xffffea08 0xa6339279 + + # Memory Device Type: SDRAM (low-power would be 0x1) + mww 0xffffea24 0x00000000 + + # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000001 + mww 0x20000000 0 + + # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero + # value into the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000002 + mww 0x20000000 0 + + # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing + # zero values eight times into the starting memory location for the SDRAM. + + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + + # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x3 + mww 0x20000000 0 + + # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting + # memory location for the SDRAM. + + mww 0xffffea00 0x0 + mww 0x20000000 0 + + # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles). + + mww 0xffffea04 0x0000039c +} + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start} +$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init} diff --git a/tcl/board/certuspro_evaluation.cfg b/tcl/board/certuspro_evaluation.cfg new file mode 100644 index 0000000000..ba2f17c221 --- /dev/null +++ b/tcl/board/certuspro_evaluation.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 10000 + +source [find fpga/lattice_certuspro.cfg] + +#openocd -f board/certuspro_evaluation.cfg -c "init" -c "pld load certuspro.pld shared_folder/certuspro_blinker_impl_1.bit" + +set JTAGSPI_CHAIN_ID certuspro.pld +source [find cpld/jtagspi.cfg] + +#jtagspi_init certuspro.pld "" -1 +#jtagspi_program shared_folder/certuspro_blinker_impl1.bit 0 diff --git a/tcl/board/digilent_anvyl.cfg b/tcl/board/digilent_anvyl.cfg new file mode 100644 index 0000000000..e820028779 --- /dev/null +++ b/tcl/board/digilent_anvyl.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Digilent Anvyl with Xilinx Spartan-6 FPGA +# https://digilent.com/reference/programmable-logic/anvyl/start +# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1 +# adapter. +adapter driver ftdi +adapter speed 30000 + +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6010 + +# channel 0 is the JTAG channel +# channel 1 is a user serial channel to pins on the FPGA +ftdi channel 0 + +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0088 0x008b +reset_config none + +# Enable sampling on falling edge for high JTAG speeds. +ftdi tdo_sample_edge falling + +transport select jtag + +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] diff --git a/tcl/board/digilent_cmod_s7.cfg b/tcl/board/digilent_cmod_s7.cfg new file mode 100644 index 0000000000..4fa45a17a7 --- /dev/null +++ b/tcl/board/digilent_cmod_s7.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# digilent CMOD S7 +# https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual + + +adapter driver ftdi +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +ftdi vid_pid 0x0403 0x6010 +reset_config none +transport select jtag + +adapter speed 10000 + +source [find cpld/xilinx-xc7.cfg] + +# "ipdbg create-hub xc7.ipdbghub -tap xc7.tap -ir 0x02" +# "xc7.ipdbghub ipdbg start -tool 0 -port 5555" +#openocd -f board/digilent_cmod_s7.cfg -c "init" -c "pld load xc7.pld shared_folder/cmod_s7_fast.bit" + +set JTAGSPI_CHAIN_ID xc7.pld +source [find cpld/jtagspi.cfg] + +#jtagspi_init xc7.pld "shared_folder/bscan_spi_xc7s25.bit" 0xab +#jtagspi_program shared_folder/cmod_s7_fast.bit 0 diff --git a/tcl/board/digilent_nexys2.cfg b/tcl/board/digilent_nexys2.cfg new file mode 100644 index 0000000000..c1c5b2ac68 --- /dev/null +++ b/tcl/board/digilent_nexys2.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://digilent.com/reference/programmable-logic/nexys-2/start +# +# The Digilent Nexy2 normally requires proprietary tools to program and will +# enumerate as: +# ID 1443:0005 1443 ONBOARD USB +# +# However, the ixo-usb-jtag project provides an alternative open firmware for +# the on board programmer. When using this firmware the board will then +# enumerate as: +# ID 16c0:06ad ixo.de USB-JTAG-IF (With SerialNumber == hw_nexys) +# +# See the interface/usb-jtag.cfg for more information. + +source [find interface/usb-jtag.cfg] +source [find cpld/xilinx-xcf-s.cfg] +source [find fpga/xilinx-xc3s.cfg] + +# Usage: +# +# Load Bitstream into FPGA: +# openocd -f board/digilent_nexys2.cfg -c "init;\ +# pld load 0 bitstream.bit;\ +# shutdown" + +# Read Unique Device Identifier (DNA): +# openocd -f board/digilent_nexys2.cfg -c "init;\ +# xilinx_print_dna [xc3s_get_dna xc3s.tap];\ +# shutdown" diff --git a/tcl/board/ecp5_evaluation.cfg b/tcl/board/ecp5_evaluation.cfg new file mode 100644 index 0000000000..71769f6074 --- /dev/null +++ b/tcl/board/ecp5_evaluation.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Lattice ECP5 evaluation Kit +# https://www.latticesemi.com/view_document?document_id=52479 +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/lattice_ecp5.cfg] + +#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load ecp5.pld shared_folder/ecp5_blinker_impl1.bit" +#ipdbg create-hub ecp5.ipdbghub -tap ecp5.tap -ir 0x32 +#ecp5.ipdbghub ipdbg start -tool 0 -port 5555 + +set JTAGSPI_CHAIN_ID ecp5.pld +source [find cpld/jtagspi.cfg] + +#jtagspi_init ecp5.pld "" -1 +#jtagspi_program shared_folder/ecp5_blinker_impl1_slow.bit 0 diff --git a/tcl/board/ek-lm4f120xl.cfg b/tcl/board/ek-lm4f120xl.cfg index db8b2010ba..44b1b1ea12 100644 --- a/tcl/board/ek-lm4f120xl.cfg +++ b/tcl/board/ek-lm4f120xl.cfg @@ -12,7 +12,7 @@ # source [find interface/ti-icdi.cfg] -transport select hla_jtag +transport select jtag set WORKAREASIZE 0x8000 set CHIPNAME lm4f120h5qr diff --git a/tcl/board/ek-lm4f232.cfg b/tcl/board/ek-lm4f232.cfg index 89b2c3ce88..bb7f9ea5b0 100644 --- a/tcl/board/ek-lm4f232.cfg +++ b/tcl/board/ek-lm4f232.cfg @@ -12,7 +12,7 @@ # source [find interface/ti-icdi.cfg] -transport select hla_jtag +transport select jtag set WORKAREASIZE 0x8000 set CHIPNAME lm4f23x diff --git a/tcl/board/esp32-bridge.cfg b/tcl/board/esp32-bridge.cfg new file mode 100644 index 0000000000..17146e59c3 --- /dev/null +++ b/tcl/board/esp32-bridge.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32 connected via ESP USB Bridge board +# +# For example, OpenOCD can be started for ESP32 debugging on +# +# openocd -f board/esp32-bridge.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_bridge.cfg] +# ESP32 chip id defined in the idf esp_chip_model_t +espusbjtag chip_id 1 +# Source the ESP32 configuration file +source [find target/esp32.cfg] diff --git a/tcl/board/esp32s3-bridge.cfg b/tcl/board/esp32s3-bridge.cfg new file mode 100644 index 0000000000..a42e257c58 --- /dev/null +++ b/tcl/board/esp32s3-bridge.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S3 connected via ESP USB Bridge board +# +# For example, OpenOCD can be started for ESP32-S3 debugging on +# +# openocd -f board/esp32s3-bridge.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_bridge.cfg] +# ESP32S3 chip id defined in the idf esp_chip_model_t +espusbjtag chip_id 9 +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/tcl/board/esp32s3-builtin.cfg b/tcl/board/esp32s3-builtin.cfg new file mode 100644 index 0000000000..353099c98f --- /dev/null +++ b/tcl/board/esp32s3-builtin.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter. +# +# For example, OpenOCD can be started for ESP32-S3 debugging on +# +# openocd -f board/esp32s3-builtin.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] + +adapter speed 40000 diff --git a/tcl/board/gatemate_eval.cfg b/tcl/board/gatemate_eval.cfg new file mode 100644 index 0000000000..c4d3f3dfda --- /dev/null +++ b/tcl/board/gatemate_eval.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# GateMateTM FPGA Evaluation Board +# https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/ +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0014 0x011b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/gatemate.cfg] + +set JTAGSPI_CHAIN_ID gatemate.pld +source [find cpld/jtagspi.cfg] + +#jtagspi_init gatemate.pld "" -1 +#jtagspi_program workspace/blink/blink_slow.cfg.bit 0 diff --git a/tcl/board/gowin_runber.cfg b/tcl/board/gowin_runber.cfg new file mode 100644 index 0000000000..6cb07362b9 --- /dev/null +++ b/tcl/board/gowin_runber.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Gowin RUNBER FPGA Development Board +# https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/gowin_gw1n.cfg] + + +#openocd -f board/gowin_runber.cfg -c "init" -c "pld load 0 impl/pnr/gw1n_blinker.fs" +#ipdbg create-hub gw1n.ipdbghub -tap gw1n.tap -ir 0x42 +#gw1n.ipdbghubipdbg start -tool 0 -port 5555 diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 790b4c7c83..5642cb1ab8 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -123,13 +123,12 @@ reset_config trst_and_srst #------------------------------------------------------------------------- adapter speed 12000 - jtag interface #------------------------------------------------------------------------- # GDB Setup #------------------------------------------------------------------------- - gdb_breakpoint_override hard + gdb breakpoint_override hard #------------------------------------------------ # ARM SPECIFIC diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg index 18f9e8d25a..276e7180ea 100644 --- a/tcl/board/mini6410.cfg +++ b/tcl/board/mini6410.cfg @@ -95,7 +95,7 @@ adapter srst delay 100 jtag_ntrst_delay 100 reset_config trst_and_srst -gdb_breakpoint_override hard +gdb breakpoint_override hard targets nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu diff --git a/tcl/board/nds32_xc5.cfg b/tcl/board/nds32_xc5.cfg deleted file mode 100644 index 82a117e714..0000000000 --- a/tcl/board/nds32_xc5.cfg +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -set _CPUTAPID 0x1000063d -set _CHIPNAME nds32 -source [find target/nds32v3.cfg] - -jtag init diff --git a/tcl/board/netgear-wg102.cfg b/tcl/board/netgear-wg102.cfg index 15f9c118af..0a7dad5ab2 100644 --- a/tcl/board/netgear-wg102.cfg +++ b/tcl/board/netgear-wg102.cfg @@ -27,7 +27,7 @@ $_TARGETNAME configure -event reset-init { # 0x00003800 - 0x07 << FLASHCTL_WST2_S # FLASHCTL_AC_8M 0x00060000 - Size of flash # FLASHCTL_E 0x00080000 - Flash bank enable (added) - # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode wont work!! + # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode won't work!! # FLASHCTL_MWx16 0x10000000 - 16bit mode. Do not use it!! # FLASHCTL_MWx8 0x00000000 - 8bit mode. mww 0xb8400000 0x000d3ce1 diff --git a/tcl/board/nordic_nrf51_dk.cfg b/tcl/board/nordic/nrf51-dk.cfg similarity index 81% rename from tcl/board/nordic_nrf51_dk.cfg rename to tcl/board/nordic/nrf51-dk.cfg index 7ddae2d438..4ccd3272e5 100644 --- a/tcl/board/nordic_nrf51_dk.cfg +++ b/tcl/board/nordic/nrf51-dk.cfg @@ -8,4 +8,4 @@ source [find interface/jlink.cfg] transport select swd -source [find target/nrf51.cfg] +source [find target/nordic/nrf51.cfg] diff --git a/tcl/board/nordic_nrf51822_mkit.cfg b/tcl/board/nordic/nrf51822-mkit.cfg similarity index 79% rename from tcl/board/nordic_nrf51822_mkit.cfg rename to tcl/board/nordic/nrf51822-mkit.cfg index 266d710704..fd32271789 100644 --- a/tcl/board/nordic_nrf51822_mkit.cfg +++ b/tcl/board/nordic/nrf51822-mkit.cfg @@ -5,4 +5,4 @@ # source [find interface/cmsis-dap.cfg] -source [find target/nrf51.cfg] +source [find target/nordic/nrf51.cfg] diff --git a/tcl/board/nordic_nrf52_dk.cfg b/tcl/board/nordic/nrf52-dk.cfg similarity index 81% rename from tcl/board/nordic_nrf52_dk.cfg rename to tcl/board/nordic/nrf52-dk.cfg index 7366bf94af..9b2390a624 100644 --- a/tcl/board/nordic_nrf52_dk.cfg +++ b/tcl/board/nordic/nrf52-dk.cfg @@ -8,4 +8,4 @@ source [find interface/jlink.cfg] transport select swd -source [find target/nrf52.cfg] +source [find target/nordic/nrf52.cfg] diff --git a/tcl/board/nordic/nrf5340-dk.cfg b/tcl/board/nordic/nrf5340-dk.cfg new file mode 100644 index 0000000000..fd7a40d666 --- /dev/null +++ b/tcl/board/nordic/nrf5340-dk.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor nRF5340 Development Kit +# https://www.nordicsemi.com/Products/Development-hardware/nRF5340-DK +# + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/nordic/nrf53.cfg] diff --git a/tcl/board/nordic/nrf54l15-dk.cfg b/tcl/board/nordic/nrf54l15-dk.cfg new file mode 100644 index 0000000000..d785d852db --- /dev/null +++ b/tcl/board/nordic/nrf54l15-dk.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor nRF54L15 Development kit +# https://www.nordicsemi.com/Products/Development-hardware/nRF54L15-DK +# + +source [find interface/jlink.cfg] +source [find target/nordic/nrf54l.cfg] diff --git a/tcl/board/nordic/nrf9160-dk.cfg b/tcl/board/nordic/nrf9160-dk.cfg new file mode 100644 index 0000000000..dc456202c1 --- /dev/null +++ b/tcl/board/nordic/nrf9160-dk.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor nRF9160 Development Kit +# https://www.nordicsemi.com/Products/Development-hardware/nRF9160-DK +# + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/nordic/nrf91.cfg] diff --git a/tcl/board/nordic_nrf52_ftx232.cfg b/tcl/board/nordic_nrf52_ftx232.cfg index c3c69a89a5..772d176d6f 100644 --- a/tcl/board/nordic_nrf52_ftx232.cfg +++ b/tcl/board/nordic_nrf52_ftx232.cfg @@ -5,9 +5,11 @@ # or any FT232H/FT2232H/FT4232H based board/module # +echo "WARNING: 'board/nordic_nrf52_ftx232.cfg' is deprecated, use '-f interface/ftdi/ft232h-module-swd.cfg -f target/nordic/nrf52.cfg' instead" + source [find interface/ftdi/ft232h-module-swd.cfg] #source [find interface/ftdi/minimodule-swd.cfg] transport select swd -source [find target/nrf52.cfg] +source [find target/nordic/nrf52.cfg] diff --git a/tcl/board/nxp/frdm-kv11z-jlink.cfg b/tcl/board/nxp/frdm-kv11z-jlink.cfg new file mode 100644 index 0000000000..725a37b9e6 --- /dev/null +++ b/tcl/board/nxp/frdm-kv11z-jlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for NXP FRDM-KV11Z development boards. +# +# This configuration file is only for FRDM-KV11Z development boards with the +# SEGGER J-Link OpenSDA firmware, see: +# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/ + +source [find interface/jlink.cfg] + +# Set working area size to 16 KiB. +set WORKAREASIZE 0x4000 + +# Set the chip name. +set CHIPNAME kv11z + +transport select swd + +source [find target/kx.cfg] + +reset_config srst_only diff --git a/tcl/board/nxp/frdm-kv31f-jlink.cfg b/tcl/board/nxp/frdm-kv31f-jlink.cfg new file mode 100644 index 0000000000..e55a01cd70 --- /dev/null +++ b/tcl/board/nxp/frdm-kv31f-jlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for NXP FRDM-KV31F development boards. +# +# This configuration file is only for FRDM-KV31F development boards with the +# SEGGER J-Link OpenSDA firmware, see: +# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/ + +source [find interface/jlink.cfg] + +# Set working area size to 32 KiB. +set WORKAREASIZE 0x8000 + +# Set the chip name. +set CHIPNAME kv31f + +transport select swd + +source [find target/kx.cfg] + +reset_config srst_only diff --git a/tcl/board/nxp_imx8mp-evk.cfg b/tcl/board/nxp_imx8mp-evk.cfg new file mode 100644 index 0000000000..4e101d454f --- /dev/null +++ b/tcl/board/nxp_imx8mp-evk.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP IMX8M Plus EVK +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + + +# board has an i.MX8MP with 4 Cortex-A55 cores +set CHIPNAME imx8mp +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8mp.cfg] diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg index 915a0de249..b6cf3a0978 100644 --- a/tcl/board/or1k_generic.cfg +++ b/tcl/board/or1k_generic.cfg @@ -22,7 +22,7 @@ poll_period 1 adapter speed 3000 # Enable the target description feature -gdb_target_description enable +gdb target_description enable # Add a new register in the cpu register list. This register will be # included in the generated target descriptor file. diff --git a/tcl/board/orange_pi_zero_3.cfg b/tcl/board/orange_pi_zero_3.cfg new file mode 100644 index 0000000000..2af983c650 --- /dev/null +++ b/tcl/board/orange_pi_zero_3.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Orange Pi Zero 3 board with Allwinner H618 chip +# http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-3.html +# +# Accessing JTAG signals on Orange Pi Zero 3 board requires connection to pins +# on the microSD card slot. +# 1 - DAT2 - TCK +# 2 - CD/DAT3 - NC +# 3 - CMD - TDO +# 4 - VDD - NC +# 5 - CLK - NC +# 6 - VSS - NC +# 7 - DAT0 - TDI +# 8 - DAT1 - TMS +# +# PF Configure Register 0 at address 0x0300b0b4 must be set 0x07373733 to set +# the JTAG function on these pins (which is what the factory installed image on +# the SPI flash does when the board is powered without a microSD inserted). + +source [find target/allwinner_h618.cfg] + +# To this contributor's knowledge, the board neither exposes TRST nor SRST. +reset_config none diff --git a/tcl/board/rpi3.cfg b/tcl/board/rpi3.cfg index fd93a9d9d8..a08bfeb12e 100644 --- a/tcl/board/rpi3.cfg +++ b/tcl/board/rpi3.cfg @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is the Raspberry Pi 3 board with BCM2837 chip -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2837 # # Enable JTAG GPIO on Raspberry Pi boards -# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md +# https://www.raspberrypi.com/documentation/computers/legacy_config_txt.html#enable_jtag_gpio source [find target/bcm2837.cfg] transport select jtag diff --git a/tcl/board/rpi4b.cfg b/tcl/board/rpi4b.cfg index 5b046af7b5..7d937e8c05 100644 --- a/tcl/board/rpi4b.cfg +++ b/tcl/board/rpi4b.cfg @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is the Raspberry Pi 4 model B board with BCM2711 chip -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2711 # # Enable JTAG GPIO on Raspberry Pi boards -# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md +# https://www.raspberrypi.com/documentation/computers/legacy_config_txt.html#enable_jtag_gpio source [find target/bcm2711.cfg] transport select jtag diff --git a/tcl/board/snps_hsdk_4xd.cfg b/tcl/board/snps_hsdk_4xd.cfg new file mode 100644 index 0000000000..5901533d28 --- /dev/null +++ b/tcl/board/snps_hsdk_4xd.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2023 Synopsys, Inc. +# Artemiy Volkov <artemiy@synopsys.com> + +# Adapted from tcl/board/snps_hsdk.cfg. + +# +# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores) +# + +source [find interface/ftdi/snps_sdp.cfg] +adapter speed 10000 + +# ARCs supports only JTAG. +transport select jtag + +# Configure SoC +source [find target/snps_hsdk_4xd.cfg] diff --git a/tcl/board/st/nucleo-u083rc.cfg b/tcl/board/st/nucleo-u083rc.cfg new file mode 100644 index 0000000000..03e9569305 --- /dev/null +++ b/tcl/board/st/nucleo-u083rc.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NUCLEO-U083RC +# https://www.st.com/en/evaluation-tools/nucleo-u083rc.html + +source [find interface/stlink.cfg] + +transport select swd + +source [find target/stm32u0x.cfg] + +reset_config srst_only diff --git a/tcl/board/st_b-l475e-iot01a.cfg b/tcl/board/st_b-l475e-iot01a.cfg index e75c99d7a5..5bdbdb4a26 100644 --- a/tcl/board/st_b-l475e-iot01a.cfg +++ b/tcl/board/st_b-l475e-iot01a.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/st_nucleo_8l152r8.cfg b/tcl/board/st_nucleo_8l152r8.cfg index f06d74981c..681b5a2433 100644 --- a/tcl/board/st_nucleo_8l152r8.cfg +++ b/tcl/board/st_nucleo_8l152r8.cfg @@ -3,10 +3,10 @@ # This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip. # http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select swim -source [find target/stm8l152.cfg] +source [find target/stm8l15xx8.cfg] reset_config srst_only diff --git a/tcl/board/st_nucleo_8s208rb.cfg b/tcl/board/st_nucleo_8s208rb.cfg index 0d3c0c9125..0f6bde215c 100644 --- a/tcl/board/st_nucleo_8s208rb.cfg +++ b/tcl/board/st_nucleo_8s208rb.cfg @@ -3,7 +3,7 @@ # This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip. # https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select swim diff --git a/tcl/board/st_nucleo_c0.cfg b/tcl/board/st_nucleo_c0.cfg new file mode 100644 index 0000000000..845b7b50e9 --- /dev/null +++ b/tcl/board/st_nucleo_c0.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find interface/stlink.cfg] + +transport select swd + +source [find target/stm32c0x.cfg] + +reset_config srst_only diff --git a/tcl/board/st_nucleo_f0.cfg b/tcl/board/st_nucleo_f0.cfg index 31a95f59d2..4d80711275 100644 --- a/tcl/board/st_nucleo_f0.cfg +++ b/tcl/board/st_nucleo_f0.cfg @@ -10,7 +10,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f0x.cfg] diff --git a/tcl/board/st_nucleo_f103rb.cfg b/tcl/board/st_nucleo_f103rb.cfg index 9815d4546e..1b440ed9e7 100644 --- a/tcl/board/st_nucleo_f103rb.cfg +++ b/tcl/board/st_nucleo_f103rb.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f1x.cfg] diff --git a/tcl/board/st_nucleo_f3.cfg b/tcl/board/st_nucleo_f3.cfg index 8833724945..8ff57eecee 100644 --- a/tcl/board/st_nucleo_f3.cfg +++ b/tcl/board/st_nucleo_f3.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f3x.cfg] diff --git a/tcl/board/st_nucleo_f4.cfg b/tcl/board/st_nucleo_f4.cfg index a1908e4031..574417c967 100644 --- a/tcl/board/st_nucleo_f4.cfg +++ b/tcl/board/st_nucleo_f4.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f4x.cfg] diff --git a/tcl/board/st_nucleo_f7.cfg b/tcl/board/st_nucleo_f7.cfg index 9c5b36ea46..eaf79669ca 100644 --- a/tcl/board/st_nucleo_f7.cfg +++ b/tcl/board/st_nucleo_f7.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f7x.cfg] diff --git a/tcl/board/st_nucleo_g0.cfg b/tcl/board/st_nucleo_g0.cfg index f8e67a0432..c68d3d0e5a 100644 --- a/tcl/board/st_nucleo_g0.cfg +++ b/tcl/board/st_nucleo_g0.cfg @@ -12,7 +12,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32g0x.cfg] diff --git a/tcl/board/st_nucleo_g4.cfg b/tcl/board/st_nucleo_g4.cfg index 8e583e77d5..3debdc3815 100644 --- a/tcl/board/st_nucleo_g4.cfg +++ b/tcl/board/st_nucleo_g4.cfg @@ -12,7 +12,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32g4x.cfg] diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg index b857b00e05..a996d744b1 100644 --- a/tcl/board/st_nucleo_h743zi.cfg +++ b/tcl/board/st_nucleo_h743zi.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32h7x_dual_bank.cfg] diff --git a/tcl/board/st_nucleo_h745zi.cfg b/tcl/board/st_nucleo_h745zi.cfg index ad563b7d31..697d1972a0 100644 --- a/tcl/board/st_nucleo_h745zi.cfg +++ b/tcl/board/st_nucleo_h745zi.cfg @@ -2,8 +2,8 @@ # This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip. -source [find interface/stlink-dap.cfg] -transport select dapdirect_swd +source [find interface/stlink.cfg] +transport select swd # STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4) set DUAL_CORE 1 diff --git a/tcl/board/st_nucleo_l073rz.cfg b/tcl/board/st_nucleo_l073rz.cfg index 10fac5ef84..d1a2e07689 100644 --- a/tcl/board/st_nucleo_l073rz.cfg +++ b/tcl/board/st_nucleo_l073rz.cfg @@ -4,7 +4,7 @@ # http://www.st.com/en/evaluation-tools/nucleo-l073rz.html source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set WORKAREASIZE 0x2000 diff --git a/tcl/board/st_nucleo_l1.cfg b/tcl/board/st_nucleo_l1.cfg index 50688d2b67..0ffc71dfee 100644 --- a/tcl/board/st_nucleo_l1.cfg +++ b/tcl/board/st_nucleo_l1.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32l1x_dual_bank.cfg] diff --git a/tcl/board/st_nucleo_l4.cfg b/tcl/board/st_nucleo_l4.cfg index 8c63d8cbf8..dad3cc4b9a 100644 --- a/tcl/board/st_nucleo_l4.cfg +++ b/tcl/board/st_nucleo_l4.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32l4x.cfg] diff --git a/tcl/board/st_nucleo_l5.cfg b/tcl/board/st_nucleo_l5.cfg index 6450f08b8d..f3cb680c25 100644 --- a/tcl/board/st_nucleo_l5.cfg +++ b/tcl/board/st_nucleo_l5.cfg @@ -3,9 +3,9 @@ # This is for STM32L5 Nucleo Dev Boards. # http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] -transport select dapdirect_swd +transport select swd source [find target/stm32l5x.cfg] diff --git a/tcl/board/st_nucleo_wb55.cfg b/tcl/board/st_nucleo_wb55.cfg index 29b7ec98d6..79ddb1ccd2 100644 --- a/tcl/board/st_nucleo_wb55.cfg +++ b/tcl/board/st_nucleo_wb55.cfg @@ -6,7 +6,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32wbx.cfg] diff --git a/tcl/board/stm320518_eval_stlink.cfg b/tcl/board/stm320518_eval_stlink.cfg index 153f7e5cbc..8f4652eff9 100644 --- a/tcl/board/stm320518_eval_stlink.cfg +++ b/tcl/board/stm320518_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 8KB set WORKAREASIZE 0x2000 diff --git a/tcl/board/stm3220g_eval_stlink.cfg b/tcl/board/stm3220g_eval_stlink.cfg index d5296720c2..d212bbc298 100644 --- a/tcl/board/stm3220g_eval_stlink.cfg +++ b/tcl/board/stm3220g_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg index d2d5790776..e1ab2026b4 100644 --- a/tcl/board/stm3241g_eval_stlink.cfg +++ b/tcl/board/stm3241g_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32429i_eval_stlink.cfg b/tcl/board/stm32429i_eval_stlink.cfg index be3c482263..ec7e10c437 100644 --- a/tcl/board/stm32429i_eval_stlink.cfg +++ b/tcl/board/stm32429i_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32439i_eval_stlink.cfg b/tcl/board/stm32439i_eval_stlink.cfg index 7a1a396fcb..bac64c81a5 100644 --- a/tcl/board/stm32439i_eval_stlink.cfg +++ b/tcl/board/stm32439i_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f0discovery.cfg b/tcl/board/stm32f0discovery.cfg index 60fb4a65e4..9a8e921538 100644 --- a/tcl/board/stm32f0discovery.cfg +++ b/tcl/board/stm32f0discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set WORKAREASIZE 0x2000 source [find target/stm32f0x.cfg] diff --git a/tcl/board/stm32f3discovery.cfg b/tcl/board/stm32f3discovery.cfg index f28e11f6a6..661082acfa 100644 --- a/tcl/board/stm32f3discovery.cfg +++ b/tcl/board/stm32f3discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f3x.cfg] diff --git a/tcl/board/stm32f412g-disco.cfg b/tcl/board/stm32f412g-disco.cfg index 757b25d75c..e278062919 100644 --- a/tcl/board/stm32f412g-disco.cfg +++ b/tcl/board/stm32f412g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f413h-disco.cfg b/tcl/board/stm32f413h-disco.cfg index 6abf495514..9a72c121c5 100644 --- a/tcl/board/stm32f413h-disco.cfg +++ b/tcl/board/stm32f413h-disco.cfg @@ -10,7 +10,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f429disc1.cfg b/tcl/board/stm32f429disc1.cfg index 657aa1986f..a5646c9ecc 100644 --- a/tcl/board/stm32f429disc1.cfg +++ b/tcl/board/stm32f429disc1.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32f4x.cfg] diff --git a/tcl/board/stm32f429discovery.cfg b/tcl/board/stm32f429discovery.cfg index d1b5f5a118..735254e7f6 100644 --- a/tcl/board/stm32f429discovery.cfg +++ b/tcl/board/stm32f429discovery.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f469discovery.cfg b/tcl/board/stm32f469discovery.cfg index cca25b7f04..7d39929064 100644 --- a/tcl/board/stm32f469discovery.cfg +++ b/tcl/board/stm32f469discovery.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f469i-disco.cfg b/tcl/board/stm32f469i-disco.cfg index 7ce57f6e75..45ec9a2691 100644 --- a/tcl/board/stm32f469i-disco.cfg +++ b/tcl/board/stm32f469i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f4discovery.cfg b/tcl/board/stm32f4discovery.cfg index 714f1e9032..73ede7ed71 100644 --- a/tcl/board/stm32f4discovery.cfg +++ b/tcl/board/stm32f4discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 64KB set WORKAREASIZE 0x10000 diff --git a/tcl/board/stm32f723e-disco.cfg b/tcl/board/stm32f723e-disco.cfg index 2dee2f9023..8acefff4c3 100644 --- a/tcl/board/stm32f723e-disco.cfg +++ b/tcl/board/stm32f723e-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f746g-disco.cfg b/tcl/board/stm32f746g-disco.cfg index fed1d8ec9b..04ed72cc50 100644 --- a/tcl/board/stm32f746g-disco.cfg +++ b/tcl/board/stm32f746g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32f769i-disco.cfg b/tcl/board/stm32f769i-disco.cfg index 2969bb9272..89e197c525 100644 --- a/tcl/board/stm32f769i-disco.cfg +++ b/tcl/board/stm32f769i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg index 4cc22ea625..3f3bceb845 100644 --- a/tcl/board/stm32f7discovery.cfg +++ b/tcl/board/stm32f7discovery.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK/V2-1 source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32h735g-disco.cfg b/tcl/board/stm32h735g-disco.cfg index 4097ae28b2..e839c7a547 100644 --- a/tcl/board/stm32h735g-disco.cfg +++ b/tcl/board/stm32h735g-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set CHIPNAME stm32h735igk6 diff --git a/tcl/board/stm32h745i-disco.cfg b/tcl/board/stm32h745i-disco.cfg index 1c0bc6748c..700f141d26 100644 --- a/tcl/board/stm32h745i-disco.cfg +++ b/tcl/board/stm32h745i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set CHIPNAME stm32h745xih6 diff --git a/tcl/board/stm32h747i-disco.cfg b/tcl/board/stm32h747i-disco.cfg index e0a348ef08..e95ad8a12b 100644 --- a/tcl/board/stm32h747i-disco.cfg +++ b/tcl/board/stm32h747i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set CHIPNAME stm32h747xih6 diff --git a/tcl/board/stm32h750b-disco.cfg b/tcl/board/stm32h750b-disco.cfg index efb32b1dfb..8f0f15b53e 100644 --- a/tcl/board/stm32h750b-disco.cfg +++ b/tcl/board/stm32h750b-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set CHIPNAME stm32h750xbh6 diff --git a/tcl/board/stm32h7b3i-disco.cfg b/tcl/board/stm32h7b3i-disco.cfg index 58ad9f7814..de009570f5 100644 --- a/tcl/board/stm32h7b3i-disco.cfg +++ b/tcl/board/stm32h7b3i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set CHIPNAME stm32h7b3lih6q diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg index b9c4c74c26..1880bb871e 100644 --- a/tcl/board/stm32h7x3i_eval.cfg +++ b/tcl/board/stm32h7x3i_eval.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32h7x_dual_bank.cfg] diff --git a/tcl/board/stm32l0discovery.cfg b/tcl/board/stm32l0discovery.cfg index c711d9c8a8..06d02ed024 100644 --- a/tcl/board/stm32l0discovery.cfg +++ b/tcl/board/stm32l0discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set WORKAREASIZE 0x2000 source [find target/stm32l0.cfg] diff --git a/tcl/board/stm32l476g-disco.cfg b/tcl/board/stm32l476g-disco.cfg index a32d20fb3f..e3d4de3c0d 100644 --- a/tcl/board/stm32l476g-disco.cfg +++ b/tcl/board/stm32l476g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l496g-disco.cfg b/tcl/board/stm32l496g-disco.cfg index 1ba2299ca9..a715bb058d 100644 --- a/tcl/board/stm32l496g-disco.cfg +++ b/tcl/board/stm32l496g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l4discovery.cfg b/tcl/board/stm32l4discovery.cfg index f089550780..7f724f9bd2 100644 --- a/tcl/board/stm32l4discovery.cfg +++ b/tcl/board/stm32l4discovery.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd source [find target/stm32l4x.cfg] diff --git a/tcl/board/stm32l4p5g-disco.cfg b/tcl/board/stm32l4p5g-disco.cfg index 20d781a1a4..86c05a18d4 100644 --- a/tcl/board/stm32l4p5g-disco.cfg +++ b/tcl/board/stm32l4p5g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l4r9i-disco.cfg b/tcl/board/stm32l4r9i-disco.cfg index f364ad3d58..de23cc1ae5 100644 --- a/tcl/board/stm32l4r9i-disco.cfg +++ b/tcl/board/stm32l4r9i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32ldiscovery.cfg b/tcl/board/stm32ldiscovery.cfg index d760edaba7..38b8a8bd0a 100644 --- a/tcl/board/stm32ldiscovery.cfg +++ b/tcl/board/stm32ldiscovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set WORKAREASIZE 0x4000 source [find target/stm32l1.cfg] diff --git a/tcl/board/stm32mp13x_dk.cfg b/tcl/board/stm32mp13x_dk.cfg index 6328ddb4c0..8ece24844c 100644 --- a/tcl/board/stm32mp13x_dk.cfg +++ b/tcl/board/stm32mp13x_dk.cfg @@ -3,9 +3,9 @@ # board MB1635x # http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] -transport select dapdirect_swd +transport select swd source [find target/stm32mp13x.cfg] diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg index 9503428d1a..ba1c7f78a6 100644 --- a/tcl/board/stm32mp15x_dk2.cfg +++ b/tcl/board/stm32mp15x_dk2.cfg @@ -4,9 +4,9 @@ # http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html # http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] -transport select dapdirect_swd +transport select swd source [find target/stm32mp15x.cfg] diff --git a/tcl/board/stm32vldiscovery.cfg b/tcl/board/stm32vldiscovery.cfg index 30e35b9817..d79c62ea43 100644 --- a/tcl/board/stm32vldiscovery.cfg +++ b/tcl/board/stm32vldiscovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select swd set WORKAREASIZE 0x2000 source [find target/stm32f1x.cfg] diff --git a/tcl/board/ti/launchxl2-tms57012.cfg b/tcl/board/ti/launchxl2-tms57012.cfg new file mode 100644 index 0000000000..99cb26e204 --- /dev/null +++ b/tcl/board/ti/launchxl2-tms57012.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hercules TMS570LS12x LaunchPad Development Kit +# https://www.ti.com/tool/LAUNCHXL2-TMS57012 + +source [find interface/xds110.cfg] + +transport select jtag + +source [find target/ti_tms570ls1x.cfg] diff --git a/tcl/board/ti_am243_launchpad.cfg b/tcl/board/ti_am243_launchpad.cfg new file mode 100644 index 0000000000..aa75dda888 --- /dev/null +++ b/tcl/board/ti_am243_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM243 Launchpad +# https://www.ti.com/tool/LP-AM243 +# + +# AM243 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am243 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am261_launchpad.cfg b/tcl/board/ti_am261_launchpad.cfg new file mode 100644 index 0000000000..c6c4609ed1 --- /dev/null +++ b/tcl/board/ti_am261_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM261 Launchpad +# https://www.ti.com/tool/LP-AM261 +# + +# AM263 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am261 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am263_launchpad.cfg b/tcl/board/ti_am263_launchpad.cfg new file mode 100644 index 0000000000..a07a21b3d5 --- /dev/null +++ b/tcl/board/ti_am263_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM263 Launchpad +# https://www.ti.com/tool/LP-AM263 +# + +# AM263 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am263 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am263p_launchpad.cfg b/tcl/board/ti_am263p_launchpad.cfg new file mode 100644 index 0000000000..96e06fab6b --- /dev/null +++ b/tcl/board/ti_am263p_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM263P Launchpad +# https://www.ti.com/tool/LP-AM263P +# + +# AM263P Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am263p +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am273_launchpad.cfg b/tcl/board/ti_am273_launchpad.cfg new file mode 100644 index 0000000000..c17170bf13 --- /dev/null +++ b/tcl/board/ti_am273_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM273 Launchpad +# https://www.ti.com/tool/LP-AM273 +# + +# AM273 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am273 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti_am625_swd_native.cfg new file mode 100644 index 0000000000..65314fe5dc --- /dev/null +++ b/tcl/board/ti_am625_swd_native.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am625 +# Link: https://www.ti.com/product/AM625 +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM625 platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM625 and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem +transport select swd + +if { ![info exists SOC] } { + set SOC am625 +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg new file mode 100644 index 0000000000..3d5e892289 --- /dev/null +++ b/tcl/board/ti_am62a7_swd_native.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM62A7 +# Link: https://www.ti.com/product/AM62A7 +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM62A7 platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM62A7 and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem +transport select swd + +if { ![info exists SOC] } { + set SOC am62a7 +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_am62a7evm.cfg b/tcl/board/ti_am62a7evm.cfg new file mode 100644 index 0000000000..e40790950b --- /dev/null +++ b/tcl/board/ti_am62a7evm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am62a7 EVM/SK +# Link: https://www.ti.com/tool/SK-AM62A-LP +# + +# AM62a7 EVM/SK has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62a7 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_am62levm.cfg b/tcl/board/ti_am62levm.cfg new file mode 100644 index 0000000000..6debdd49f4 --- /dev/null +++ b/tcl/board/ti_am62levm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM62L EVM: +# Links: https://www.ti.com/tool/TMDS62LEVM +# + +# the AM62L3 EVM/SK has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62l +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg new file mode 100644 index 0000000000..a8c6bd1204 --- /dev/null +++ b/tcl/board/ti_am62p_swd_native.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am62p +# Link: https://www.ti.com/product/AM62P +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM62P platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM62P and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem +transport select swd + +if { ![info exists SOC] } { + set SOC am62p +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_am62pevm.cfg b/tcl/board/ti_am62pevm.cfg new file mode 100644 index 0000000000..2322b3d943 --- /dev/null +++ b/tcl/board/ti_am62pevm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments SK-AM62P: https://www.ti.com/lit/zip/sprr487 +# + +# AM62P SK/EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62p +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_cc26x2x7_launchpad.cfg b/tcl/board/ti_cc26x2x7_launchpad.cfg new file mode 100644 index 0000000000..9e6e72e89c --- /dev/null +++ b/tcl/board/ti_cc26x2x7_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC1352P7 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 5500 +transport select jtag +source [find target/ti_cc26x2x7.cfg] diff --git a/tcl/board/ti_dk-tm4c129.cfg b/tcl/board/ti_dk-tm4c129.cfg index d8210e32d2..e0574fa870 100644 --- a/tcl/board/ti_dk-tm4c129.cfg +++ b/tcl/board/ti_dk-tm4c129.cfg @@ -8,7 +8,7 @@ source [find interface/ti-icdi.cfg] -transport select hla_jtag +transport select jtag set WORKAREASIZE 0x8000 set CHIPNAME tm4c129xnczad diff --git a/tcl/board/ti_ek-tm4c123gxl.cfg b/tcl/board/ti_ek-tm4c123gxl.cfg index 91390fa82f..7b8fc267f5 100644 --- a/tcl/board/ti_ek-tm4c123gxl.cfg +++ b/tcl/board/ti_ek-tm4c123gxl.cfg @@ -8,7 +8,7 @@ source [find interface/ti-icdi.cfg] -transport select hla_jtag +transport select jtag set WORKAREASIZE 0x8000 set CHIPNAME tm4c123gh6pm diff --git a/tcl/board/ti_ek-tm4c1294xl.cfg b/tcl/board/ti_ek-tm4c1294xl.cfg index 63612c686b..8cceb49c96 100644 --- a/tcl/board/ti_ek-tm4c1294xl.cfg +++ b/tcl/board/ti_ek-tm4c1294xl.cfg @@ -8,7 +8,7 @@ source [find interface/ti-icdi.cfg] -transport select hla_jtag +transport select jtag set WORKAREASIZE 0x8000 set CHIPNAME tm4c1294ncpdt diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti_j721e_swd_native.cfg new file mode 100644 index 0000000000..38316387af --- /dev/null +++ b/tcl/board/ti_j721e_swd_native.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments TDA4VM/J721E +# Link: https://www.ti.com/product/TDA4VM +# +# This configuration file is used as a self hosted debug configuration that +# works on every TDA4VM platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside TDA4VM and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem +transport select swd + +if { ![info exists SOC] } { + set SOC j721e +} +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg new file mode 100644 index 0000000000..a171ec3586 --- /dev/null +++ b/tcl/board/ti_j722s_swd_native.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J722S/AM67/TDA4VEN +# Link: https://www.ti.com/product/AM67 +# Link: https://www.ti.com/product/TDA4VEN-Q1 +# +# This configuration file is used as a self hosted debug configuration that +# works on every J722S platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside J722S and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem +transport select swd + +if { ![info exists SOC] } { + set SOC j722s +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_j722sevm.cfg b/tcl/board/ti_j722sevm.cfg new file mode 100644 index 0000000000..6a5c2d9cd9 --- /dev/null +++ b/tcl/board/ti_j722sevm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments EVM-J722S: https://www.ti.com/lit/zip/sprr495 +# + +# J722S EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC j722s +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_j784s4evm.cfg b/tcl/board/ti_j784s4evm.cfg new file mode 100644 index 0000000000..d23dc8ce67 --- /dev/null +++ b/tcl/board/ti_j784s4evm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J784S4 EVM: https://www.ti.com/tool/J784S4XEVM +# Texas Instruments SK-AM69: https://www.ti.com/tool/SK-AM69 +# + +# J784S4/AM69 SK/EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC j784s4 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_mspm0_launchpad.cfg b/tcl/board/ti_mspm0_launchpad.cfg new file mode 100644 index 0000000000..132fdc2a30 --- /dev/null +++ b/tcl/board/ti_mspm0_launchpad.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# TI MSPM0L1306 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0L1306 +# TI MSPM0C1104 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0C1104 +# TI MSPM0G3507 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0G3507 +# + +source [find interface/xds110.cfg] +adapter speed 10000 +source [find target/ti_mspm0.cfg] diff --git a/tcl/board/trion_t20_bga256.cfg b/tcl/board/trion_t20_bga256.cfg new file mode 100644 index 0000000000..ca44f0b8ce --- /dev/null +++ b/tcl/board/trion_t20_bga256.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Trion® T20 BGA256 Development Kit +# https://www.efinixinc.com/docs/trion20-devkit-ug-v1.5.pdf +# +# works after power cycle or pushing sw1. +# it is because we cannot control CDONE which is connected to ftdi channel 0 +# note from an006: For JTAG programming, T4, T8, T13, and T20 FPGAs use the +# CRESET_N and SS_N pins in addition to the standard JTAG pins. + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 1 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/efinix_trion.cfg] + +#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load trion.pld outflow/trion_blinker.bit" +#ipdbg create-hub trion.ipdbghub -tap trion.tap -ir 0x8 +#trion.ipdbghub ipdbg start -tool 0 -port 5555 + +set JTAGSPI_CHAIN_ID trion.pld +source [find cpld/jtagspi.cfg] + +#jtagspi_init trion.pld "trion_jtagspi/outflow/trion_jtagspi.bit" 0xAB +#jtagspi_program trion_blinker/outflow/trion_blinker.bin 0 diff --git a/tcl/board/vd_a53x2_dap.cfg b/tcl/board/vd_a53x2_dap.cfg new file mode 100644 index 0000000000..3251afd066 --- /dev/null +++ b/tcl/board/vd_a53x2_dap.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex A53x2 through DAP + +source [find interface/vdebug.cfg] + +set CORES 2 +set CHIPNAME a53 +set ACCESSPORT 0 +set MEMSTART 0x00000000 +set MEMSIZE 0x1000000 +set DBGBASE {0x80810000 0x80910000} +set CTIBASE {0x80820000 0x80920000} + +# vdebug select transport +transport select swd + +# JTAG reset config, frequency and reset delay +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_swdp_bfm 10ns + +# DMA Memories to access backdoor (up to 20) +vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE + +swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +source [find target/vd_aarch64.cfg] diff --git a/tcl/board/vd_a53x2_jtag.cfg b/tcl/board/vd_a53x2_jtag.cfg index 869bc4db01..0c3eebd7a7 100644 --- a/tcl/board/vd_a53x2_jtag.cfg +++ b/tcl/board/vd_a53x2_jtag.cfg @@ -4,14 +4,17 @@ source [find interface/vdebug.cfg] -set _CORES 2 -set _CHIPNAME a53 -set _MEMSTART 0x00000000 -set _MEMSIZE 0x1000000 -set _CPUTAPID 0x5ba00477 +set CORES 2 +set CHIPNAME a53 +set ACCESSPORT 0 +set MEMSTART 0x00000000 +set MEMSIZE 0x1000000 +set DBGBASE {0x80810000 0x80910000} +set CTIBASE {0x80820000 0x80920000} +set CPUTAPID 0x5ba00477 # vdebug select transport -#transport select jtag +transport select jtag # JTAG reset config, frequency and reset delay reset_config trst_and_srst @@ -21,11 +24,10 @@ adapter srst delay 5 # BFM hierarchical path and input clk period vdebug bfm_path tbench.u_vd_jtag_bfm 10ns -# DMA Memories to access backdoor (up to 4) -vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +# DMA Memories to access backdoor (up to 20) +vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE +jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID jtag arp_init-reset source [find target/vd_aarch64.cfg] diff --git a/tcl/board/vd_a75x4_dap.cfg b/tcl/board/vd_a75x4_dap.cfg new file mode 100644 index 0000000000..2f4406b038 --- /dev/null +++ b/tcl/board/vd_a75x4_dap.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex A53x2 through DAP + +source [find interface/vdebug.cfg] + +set CORES 4 +set CHIPNAME a75 +set ACCESSPORT 0x00040000 +set MEMSTART 0x00000000 +set MEMSIZE 0x1000000 +set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000} +set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000} + +# vdebug select transport +transport select swd + +# JTAG reset config, frequency and reset delay +adapter speed 200000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps + +# DMA Memories to access backdoor (up to 20) +#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE + +swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +source [find target/vd_aarch64.cfg] diff --git a/tcl/board/vd_a75x4_jtag.cfg b/tcl/board/vd_a75x4_jtag.cfg new file mode 100644 index 0000000000..a91f8b8cfc --- /dev/null +++ b/tcl/board/vd_a75x4_jtag.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex A53x2 through DAP + +source [find interface/vdebug.cfg] + +set CORES 4 +set CHIPNAME a75 +set ACCESSPORT 0x00040000 +set MEMSTART 0x00000000 +set MEMSIZE 0x1000000 +set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000} +set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000} +set CPUTAPID 0x4ba06477 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_only +adapter speed 1500000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 333ps + +jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID +jtag arp_init-reset + +source [find target/vd_aarch64.cfg] diff --git a/tcl/board/vd_m4_dap.cfg b/tcl/board/vd_m4_dap.cfg new file mode 100644 index 0000000000..f56334e834 --- /dev/null +++ b/tcl/board/vd_m4_dap.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex m4 through DAP + +source [find interface/vdebug.cfg] + +set CHIPNAME m4 +set MEMSTART 0x00000000 +set MEMSIZE 0x10000 + +# vdebug select transport +transport select swd +adapter speed 25000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_swdp_bfm 20ns + +# DMA Memories to access backdoor (up to 20) +vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE + +swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +source [find target/vd_cortex_m.cfg] diff --git a/tcl/board/vd_m4_jtag.cfg b/tcl/board/vd_m4_jtag.cfg index ca21476d29..3b32e17be3 100644 --- a/tcl/board/vd_m4_jtag.cfg +++ b/tcl/board/vd_m4_jtag.cfg @@ -4,13 +4,13 @@ source [find interface/vdebug.cfg] -set _CHIPNAME m4 -set _MEMSTART 0x00000000 -set _MEMSIZE 0x10000 -set _CPUTAPID 0x4ba00477 +set CHIPNAME m4 +set MEMSTART 0x00000000 +set MEMSIZE 0x10000 +set CPUTAPID 0x4ba00477 # vdebug select transport -#transport select jtag +transport select jtag # JTAG reset config, frequency and reset delay reset_config trst_and_srst @@ -20,11 +20,10 @@ adapter srst delay 5 # BFM hierarchical path and input clk period vdebug bfm_path tbench.u_vd_jtag_bfm 20ns -# DMA Memories to access backdoor (up to 4) -vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +# DMA Memories to access backdoor (up to 20) +vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE +jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID jtag arp_init-reset source [find target/vd_cortex_m.cfg] diff --git a/tcl/board/vd_m7_jtag.cfg b/tcl/board/vd_m7_jtag.cfg new file mode 100644 index 0000000000..9a89584c83 --- /dev/null +++ b/tcl/board/vd_m7_jtag.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex m7 through JTAG + +source [find interface/vdebug.cfg] + +set CHIPNAME m7 +set MEMSTART 0x00000000 +set MEMSIZE 0x100000 +set CPUTAPID 0x0ba02477 + +# vdebug select JTAG transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor (up to 20) +vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE + +jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID +jtag arp_init-reset + +source [find target/vd_cortex_m.cfg] diff --git a/tcl/board/vd_pulpissimo_jtag.cfg b/tcl/board/vd_pulpissimo_jtag.cfg index 69dd9e6dbe..5a6725fd62 100644 --- a/tcl/board/vd_pulpissimo_jtag.cfg +++ b/tcl/board/vd_pulpissimo_jtag.cfg @@ -4,12 +4,12 @@ source [find interface/vdebug.cfg] -set _CHIPNAME ibex -set _HARTID 0x20 -set _CPUTAPID 0x249511c3 +set CHIPNAME ibex +set HARTID 0x20 +set CPUTAPID 0x249511c3 # vdebug select transport -#transport select jtag +transport select jtag # JTAG reset config, frequency and reset delay reset_config trst_and_srst @@ -25,7 +25,7 @@ vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_ar vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000 # need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01 -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID +jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $CPUTAPID jtag arp_init-reset diff --git a/tcl/board/vd_swerv_jtag.cfg b/tcl/board/vd_swerv_jtag.cfg index ff6c6835fc..c5d33f268a 100644 --- a/tcl/board/vd_swerv_jtag.cfg +++ b/tcl/board/vd_swerv_jtag.cfg @@ -11,7 +11,7 @@ set _MEMSTART 0x00000000 set _MEMSIZE 0x10000 # vdebug select transport -#transport select jtag +transport select jtag # JTAG reset config, frequency and reset delay reset_config trst_and_srst diff --git a/tcl/board/vd_xt8_jtag.cfg b/tcl/board/vd_xt8_jtag.cfg new file mode 100644 index 0000000000..867b9e76e5 --- /dev/null +++ b/tcl/board/vd_xt8_jtag.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Xtensa xt8 through JTAG + +source [find interface/vdebug.cfg] + +set CHIPNAME xt8 +set CPUTAPID 0x120034e5 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg +#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000 +#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000 + +# Create Xtensa target first +source [find target/xtensa.cfg] +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" +source [find target/xtensa-core-xt8.cfg] diff --git a/tcl/board/xtensa-kc705-ext-dap.cfg b/tcl/board/xtensa-kc705-ext-dap.cfg new file mode 100644 index 0000000000..ac92c708d6 --- /dev/null +++ b/tcl/board/xtensa-kc705-ext-dap.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with various external adapters that support DAP, e.g. JLink +# + +adapter speed 5000 + +# KC705 supports DAP/JTAG +transport select jtag +set XTENSA_DAP enable +set XTENSA_DAP_BASE 0x10000 + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/tcl/board/xtensa-kc705-ext.cfg b/tcl/board/xtensa-kc705-ext.cfg new file mode 100644 index 0000000000..6be06817c2 --- /dev/null +++ b/tcl/board/xtensa-kc705-ext.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with various external adapters, e.g. Flyswatter2 or JLink +# + +adapter speed 10000 + +# KC705 supports JTAG only +transport select jtag + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/tcl/board/xtensa-kc705-onboard.cfg b/tcl/board/xtensa-kc705-onboard.cfg new file mode 100644 index 0000000000..f0a616cd7d --- /dev/null +++ b/tcl/board/xtensa-kc705-onboard.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with on-board (FTDI) adapter or various external adapters +# + +source [find interface/ftdi/xt_kc705_ml605.cfg] +adapter speed 10000 + +# KC705 supports JTAG only +transport select jtag + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/tcl/board/xtensa-palladium-vdebug-dual.cfg b/tcl/board/xtensa-palladium-vdebug-dual.cfg new file mode 100644 index 0000000000..447bc1fa0c --- /dev/null +++ b/tcl/board/xtensa-palladium-vdebug-dual.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# for Palladium emulation systems +# + +source [find interface/vdebug.cfg] + +# vdebug select JTAG transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# Future improvement: Enable backdoor memory access +# set _MEMSTART 0x00000000 +# set _MEMSIZE 0x100000 + +# BFM hierarchical path and input clk period +vdebug bfm_path Testbench.VJTAG 10ns + +# DMA Memories to access backdoor (up to 4) +# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE + +# Configure dual-core TAP chain +set XTENSA_NUM_CORES 2 + +# Create Xtensa target first +source [find target/xtensa.cfg] + +# Configure Xtensa core parameters next +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" diff --git a/tcl/board/xtensa-palladium-vdebug.cfg b/tcl/board/xtensa-palladium-vdebug.cfg new file mode 100644 index 0000000000..f14d92da86 --- /dev/null +++ b/tcl/board/xtensa-palladium-vdebug.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# for Palladium emulation systems +# + +source [find interface/vdebug.cfg] + +# vdebug select JTAG transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# Future improvement: Enable backdoor memory access +# set _MEMSTART 0x00000000 +# set _MEMSIZE 0x100000 + +# BFM hierarchical path and input clk period +vdebug bfm_path Testbench.VJTAG 10ns + +# DMA Memories to access backdoor (up to 4) +# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE + +# Create Xtensa target first +source [find target/xtensa.cfg] + +# Configure Xtensa core parameters next +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" diff --git a/tcl/board/xtensa-rt685-ext.cfg b/tcl/board/xtensa-rt685-ext.cfg new file mode 100644 index 0000000000..03edb8d3c6 --- /dev/null +++ b/tcl/board/xtensa-rt685-ext.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP RT6XX Developemnt Platform with Xtensa HiFi DSP +# Can be used with various external adapters that support DAP, e.g. JLink +# + +adapter speed 10000 + +# RT6XX supports SWD only +transport select swd +set XTENSA_DAP enable + +# Create Xtensa target first +source [find target/xtensa.cfg] + +source [find target/xtensa-core-nxp_rt600.cfg] diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl index 59925672dc..06962215b2 100644 --- a/tcl/chip/st/spear/spear3xx_ddr.tcl +++ b/tcl/chip/st/spear/spear3xx_ddr.tcl @@ -10,7 +10,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { if { $ddr_chips != 1 && $ddr_chips != 2 } { - error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips + error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips" } if { $ddr_type == "mt47h64m16_3_333_cl5_async" } { @@ -21,7 +21,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { # ????? $ddr_chips # set ddr_size 0x????? } else { - error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type + error "sp3xx_ddr_init: unrecognized DDR type $ddr_type" } # MPMC START diff --git a/tcl/cpld/altera-5m570z-cpld.cfg b/tcl/cpld/altera-5m570z-cpld.cfg index 5dbd0deee8..4504a80648 100644 --- a/tcl/cpld/altera-5m570z-cpld.cfg +++ b/tcl/cpld/altera-5m570z-cpld.cfg @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# Altera MAXV 5M24OZ/5M570Z CPLD -# see MAX V Device Handbook -# Table 6-3: 32-Bit MAX V Device IDCODE -# Version Part Number Manuf. ID LSB -# 0000 0010 0000 1010 0111 000 0110 1110 1 -jtag newtap 5m570z tap -expected-id 0x020a60dd -irlen 10 +# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg +echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg" + +#just to be backward compatible: +#tap will be 5m570z.tap instead of maxv.tap: +set CHIPNAME 5m570z +source [find cpld/altera-maxv.cfg] diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg index 39c409bc3a..185925a16f 100644 --- a/tcl/cpld/altera-epm240.cfg +++ b/tcl/cpld/altera-epm240.cfg @@ -1,24 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# Altera MAXII EPM240T100C CPLD +# file altera-epm240.cfg replaced by altera-maxii.cfg +echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg" -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME epm240 -} - -# see MAX II Device Handbook -# Table 3-3: 32-Bit MAX II Device IDCODE -# Version Part Number Manuf. ID LSB -# 0000 0010 0000 1010 0001 000 0110 1110 1 -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x020a10dd \ - -expected-id 0x020a20dd \ - -expected-id 0x020a30dd \ - -expected-id 0x020a40dd \ - -expected-id 0x020a50dd \ - -expected-id 0x020a60dd +#just to be backward compatible: +#tap will be epm240.tap instead of maxii.tap: +set CHIPNAME epm240 +source [find cpld/altera-maxii.cfg] # 200ns seems like a good speed # c.f. Table 5-34: MAX II JTAG Timing Parameters diff --git a/tcl/cpld/altera-max10.cfg b/tcl/cpld/altera-max10.cfg new file mode 100644 index 0000000000..a2ed00ac84 --- /dev/null +++ b/tcl/cpld/altera-max10.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# see MAX 10 FPGA Device Architecture +# Table 3-1: IDCODE Information for MAX 10 Devices +# Intel MAX 10M02 0x31810dd +# Intel MAX 10M04 0x318a0dd +# Intel MAX 10M08 0x31820dd +# Intel MAX 10M16 0x31830dd +# Intel MAX 10M25 0x31840dd +# Intel MAX 10M40 0x318d0dd +# Intel MAX 10M50 0x31850dd +# Intel MAX 10M02 0x31010dd +# Intel MAX 10M04 0x310a0dd +# Intel MAX 10M08 0x31020dd +# Intel MAX 10M16 0x31030dd +# Intel MAX 10M25 0x31040dd +# Intel MAX 10M40 0x310d0dd +# Intel MAX 10M50 0x31050dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME max10 +} + +jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \ + -expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \ + -expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \ + -expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \ + -expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd diff --git a/tcl/cpld/altera-maxii.cfg b/tcl/cpld/altera-maxii.cfg new file mode 100644 index 0000000000..2dee37f41c --- /dev/null +++ b/tcl/cpld/altera-maxii.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Altera MAXII CPLD + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME maxii +} + +# see MAX II Device Handbook +# Table 3-3: 32-Bit MAX II Device IDCODE +# Version Part Number Manuf. ID LSB +# 0000 0010 0000 1010 0001 000 0110 1110 1 +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020a10dd \ + -expected-id 0x020a20dd \ + -expected-id 0x020a30dd \ + -expected-id 0x020a40dd \ + -expected-id 0x020a50dd \ + -expected-id 0x020a60dd diff --git a/tcl/cpld/altera-maxv.cfg b/tcl/cpld/altera-maxv.cfg new file mode 100644 index 0000000000..03fad076f1 --- /dev/null +++ b/tcl/cpld/altera-maxv.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Altera MAXV 5M24OZ/5M570Z CPLD +# see MAX V Device Handbook +# Table 6-3: 32-Bit MAX V Device IDCODE +# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD +# 5M570Z: 0x020A60DD +# 5M1270Z: 0x020A30DD +# 5M1270Z 5M2210Z: 0x020A40DD + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME maxv +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020A50DD -expected-id 0x020A60DD \ + -expected-id 0x020A30DD -expected-id 0x020A40DD diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg index 7071e5e340..a7f02b9770 100644 --- a/tcl/cpld/jtagspi.cfg +++ b/tcl/cpld/jtagspi.cfg @@ -4,6 +4,8 @@ set _USER1 0x02 if { [info exists JTAGSPI_IR] } { set _JTAGSPI_IR $JTAGSPI_IR +} elseif {[info exists JTAGSPI_CHAIN_ID]} { + set _JTAGSPI_CHAIN_ID $JTAGSPI_CHAIN_ID } else { set _JTAGSPI_IR $_USER1 } @@ -21,13 +23,29 @@ if { [info exists FLASHNAME] } { } target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap -flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR +if { [info exists _JTAGSPI_IR] } { + flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR +} else { + flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID +} + +# initialize jtagspi flash +# chain_id: identifier of pld (you can get a list with 'pld devices') +# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD. +# release_from_pwr_down_cmd: optional, command sent to spi flash before probing. +# ex: 0xAB to release from power-dowm. +# Just omit it to not send a command. -proc jtagspi_init {chain_id proxy_bit} { +proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} { # load proxy bitstream $proxy_bit and probe spi flash global _FLASHNAME - pld load $chain_id $proxy_bit + if { $proxy_bit ne "" } { + pld load $chain_id $proxy_bit + } reset halt + if {$release_from_pwr_down_cmd != -1} { + jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd + } flash probe $_FLASHNAME } diff --git a/tcl/cpld/xilinx-xc3s.cfg b/tcl/cpld/xilinx-xc3s.cfg new file mode 100644 index 0000000000..a8867395b1 --- /dev/null +++ b/tcl/cpld/xilinx-xc3s.cfg @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx spartan3 +# https://docs.xilinx.com/v/u/en-US/ug332 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc3s +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x01414093 \ + -expected-id 0x0141C093 \ + -expected-id 0x01428093 \ + -expected-id 0x01434093 \ + -expected-id 0x01440093 \ + -expected-id 0x01448093 \ + -expected-id 0x01450093 \ + -expected-id 0x01C10093 \ + -expected-id 0x01C1A093 \ + -expected-id 0x01C22093 \ + -expected-id 0x01C2E093 \ + -expected-id 0x01C3A093 \ + -expected-id 0x0140C093 \ + -expected-id 0x02210093 \ + -expected-id 0x02218093 \ + -expected-id 0x02220093 \ + -expected-id 0x02228093 \ + -expected-id 0x02230093 \ + -expected-id 0x02610093 \ + -expected-id 0x02618093 \ + -expected-id 0x02620093 \ + -expected-id 0x02628093 \ + -expected-id 0x02630093 \ + -expected-id 0x03840093 \ + -expected-id 0x0384e093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap diff --git a/tcl/cpld/xilinx-xc4v.cfg b/tcl/cpld/xilinx-xc4v.cfg new file mode 100644 index 0000000000..3eb46ebc44 --- /dev/null +++ b/tcl/cpld/xilinx-xc4v.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 4 +# https://docs.xilinx.com/v/u/en-US/ug071 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc4v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x01658093 \ + -expected-id 0x01E58093 \ + -expected-id 0x0167C093 \ + -expected-id 0x02068093 \ + -expected-id 0x01E64093 \ + -expected-id 0x016A4093 \ + -expected-id 0x02088093 \ + -expected-id 0x016B4093 \ + -expected-id 0x020B0093 \ + -expected-id 0x016D8093 \ + -expected-id 0x01700093 \ + -expected-id 0x01718093 \ + -expected-id 0x01734093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg new file mode 100644 index 0000000000..14dde02703 --- /dev/null +++ b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 4 +# https://docs.xilinx.com/v/u/en-US/ug071 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc4vfx +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \ + -expected-id 0x01E8C093 \ + -expected-id 0x01EB4093 \ + -expected-id 0x01EE4093 \ + -expected-id 0x01F14093 \ + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD +virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3 diff --git a/tcl/cpld/xilinx-xc5v.cfg b/tcl/cpld/xilinx-xc5v.cfg new file mode 100644 index 0000000000..f88bbc1e81 --- /dev/null +++ b/tcl/cpld/xilinx-xc5v.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 5 +# https://docs.xilinx.com/v/u/en-US/ug191 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc5v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x0286E093 \ + -expected-id 0x02896093 \ + -expected-id 0x028AE093 \ + -expected-id 0x028D6093 \ + -expected-id 0x028EC093 \ + -expected-id 0x0290C093 \ + -expected-id 0x0295C093 \ + -expected-id 0x02A56093 \ + -expected-id 0x02A6E093 \ + -expected-id 0x02A96093 \ + -expected-id 0x02AAE093 \ + -expected-id 0x02AD6093 \ + -expected-id 0x02AEC093 \ + -expected-id 0x02B0C093 \ + -expected-id 0x02B5C093 \ + -expected-id 0x02E72093 \ + -expected-id 0x02E9A093 \ + -expected-id 0x02ECE093 \ + -expected-id 0x02F3E093 \ + -expected-id 0x03276093 \ + -expected-id 0x032C6093 \ + -expected-id 0x04502093 \ + -expected-id 0x0453E093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg new file mode 100644 index 0000000000..7420233f48 --- /dev/null +++ b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 5 +# https://docs.xilinx.com/v/u/en-US/ug191 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc5vfx +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \ + -expected-id 0x032D8093 \ + -expected-id 0x03300093 \ + -expected-id 0x03334093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD +virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3 diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg index 82b87fb415..862c4aa897 100644 --- a/tcl/cpld/xilinx-xc6s.cfg +++ b/tcl/cpld/xilinx-xc6s.cfg @@ -25,7 +25,8 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ -expected-id 0x0401D093 \ -expected-id 0x0403D093 -pld device virtex2 $_CHIPNAME.tap +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B set XC6S_CFG_IN 0x05 set XC6S_JSHUTDOWN 0x0d @@ -34,6 +35,7 @@ set XC6S_JSTART 0x0c set XC6S_BYPASS 0x3f proc xc6s_program {tap} { + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program'" global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS irscan $tap $XC6S_JSHUTDOWN irscan $tap $XC6S_JPROGRAM @@ -43,6 +45,7 @@ proc xc6s_program {tap} { #xtp038 and xc3sprog approach proc xc6s_program_iprog {tap} { + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program_iprog'" global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN irscan $tap $XC6S_JSHUTDOWN runtest 16 diff --git a/tcl/cpld/xilinx-xc6v.cfg b/tcl/cpld/xilinx-xc6v.cfg new file mode 100644 index 0000000000..d37439c984 --- /dev/null +++ b/tcl/cpld/xilinx-xc6v.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 6 +# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc6v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x042A2093 \ + -expected-id 0x042A4093 \ + -expected-id 0x042A8093 \ + -expected-id 0x042AC093 \ + -expected-id 0x04244093 \ + -expected-id 0x0424A093 \ + -expected-id 0x0424C093 \ + -expected-id 0x04250093 \ + -expected-id 0x04252093 \ + -expected-id 0x04256093 \ + -expected-id 0x0423A093 \ + -expected-id 0x04286093 \ + -expected-id 0x04288093 \ + -expected-id 0x042C4093 \ + -expected-id 0x042CA093 \ + -expected-id 0x042CC093 \ + -expected-id 0x042D0093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg index 22e0aea7f9..6f8f4ae5cb 100644 --- a/tcl/cpld/xilinx-xc7.cfg +++ b/tcl/cpld/xilinx-xc7.cfg @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# xilinx series 7 (artix, kintex, virtex) +# xilinx series 7 (spartan, artix, kintex, virtex) # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf if { [info exists CHIPNAME] } { @@ -33,21 +33,15 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ -expected-id 0x03752093 \ -expected-id 0x03751093 \ -expected-id 0x03671093 \ - -expected-id 0x036B3093 \ - -expected-id 0x036B7093 \ - -expected-id 0x036BB093 \ - -expected-id 0x036BF093 \ -expected-id 0x03667093 \ -expected-id 0x03682093 \ -expected-id 0x03687093 \ -expected-id 0x03692093 \ -expected-id 0x03691093 \ - -expected-id 0x03696093 \ - -expected-id 0x036D5093 \ - -expected-id 0x036D9093 \ - -expected-id 0x036DB093 + -expected-id 0x03696093 -pld device virtex2 $_CHIPNAME.tap 1 +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23 set XC7_JSHUTDOWN 0x0d set XC7_JPROGRAM 0x0b @@ -55,6 +49,7 @@ set XC7_JSTART 0x0c set XC7_BYPASS 0x3f proc xc7_program {tap} { + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc7_program'" global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS irscan $tap $XC7_JSHUTDOWN irscan $tap $XC7_JPROGRAM diff --git a/tcl/cpld/xilinx-xc7v.cfg b/tcl/cpld/xilinx-xc7v.cfg new file mode 100644 index 0000000000..8385948323 --- /dev/null +++ b/tcl/cpld/xilinx-xc7v.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77 +# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77 +# +# this config file is for XC7VX1140T and XC7V2000T only. +# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7v +} + +#0x036D5093: XC7VX1140T +#0x036By093: XC7V2000T +#y = xx11 = 3, 7, B or F + +jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \ + -expected-id 0x036B3093 -expected-id 0x036B7093 \ + -expected-id 0x036BB093 -expected-id 0x036BF093 \ + -expected-id 0x036D5093 + +#CFG_OUT_SLR0 0x124924 +#CFG_IN_SLR0 0x164924 +#CFG_OUT_SLR1 0x904924 +#CFG_IN_SLR1 0x905924 +#CFG_OUT_SLR2 0x924124 +#CFG_IN_SLR2 0x924164 +#CFG_OUT_SLR3 0x924904 +#CFG_IN_SLR3 0x924905 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D diff --git a/tcl/cpld/xilinx-xc7vh580t.cfg b/tcl/cpld/xilinx-xc7vh580t.cfg new file mode 100644 index 0000000000..3748049803 --- /dev/null +++ b/tcl/cpld/xilinx-xc7vh580t.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77 +# +# this config file is for xc7vh580t only. +# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7vh580t +} + +jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093 + +#CFG_OUT_SLR0 0x0492A0 +#CFG_IN_SLR0 0x0592A0 +#CFG_OUT_SLR1 0x2412A0 +#CFG_IN_SLR1 0x2416A0 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0 diff --git a/tcl/cpld/xilinx-xc7vh870t.cfg b/tcl/cpld/xilinx-xc7vh870t.cfg new file mode 100644 index 0000000000..25e2e63615 --- /dev/null +++ b/tcl/cpld/xilinx-xc7vh870t.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77 +# +# this config file is for xc7vh870t only. +# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7vh870t +} + +jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093 + +#CFG_OUT_SLR0 0x0492A092A0 +#CFG_IN_SLR0 0x0592A092A0 +#CFG_OUT_SLR1 0x2412A092A0 +#CFG_IN_SLR1 0x2416A092A0 +#CFG_OUT_SLR2 0x2492A012A0 +#CFG_IN_SLR2 0x2492A016A0 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0 diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg index 57a59f59a8..63a67da202 100644 --- a/tcl/cpld/xilinx-xcu.cfg +++ b/tcl/cpld/xilinx-xcu.cfg @@ -9,35 +9,64 @@ if { [info exists CHIPNAME] } { set _CHIPNAME xcu } -# The cvarious chips in the Ultrascale family have different IR length. +# The various chips in the Ultrascale family have different IR length. # Set $CHIP before including this file to determine the device. array set _XCU_DATA { - XCKU025 {0x03824093 6} - XCKU035 {0x03823093 6} - XCKU040 {0x03822093 6} - XCKU060 {0x03919093 6} - XCKU095 {0x03844093 6} - XCKU3P {0x04A63093 6} - XCKU5P {0x04A62093 6} - XCKU9P {0x0484A093 6} - XCKU11P {0x04A4E093 6} - XCKU13P {0x04A52093 6} - XCKU15P {0x04A56093 6} - XCVU065 {0x03939093 6} - XCVU080 {0x03843093 6} - XCVU095 {0x03842093 6} - XCVU3P {0x04B39093 6} - XCKU085 {0x0380F093 12} - XCKU115 {0x0390D093 12} - XCVU125 {0x0392D093 12} - XCVU5P {0x04B2B093 12} - XCVU7P {0x04B29093 12} - XCVU160 {0x03933093 18} - XCVU190 {0x03931093 18} - XCVU440 {0x0396D093 18} - XCVU9P {0x04B31093 18} - XCVU11P {0x04B49093 18} - XCVU13P {0x04B51093 24} + XCKU025 {0x03824093 6} + XCKU035 {0x03823093 6} + XCKU040 {0x03822093 6} + XCKU060 {0x03919093 6} + XCKU060_CIV {0x0381b093 6} + XCKU095 {0x03844093 6} + XCKU095_CIV {0x03845093 6} + XCKU3P {0x04A63093 6} + XCKU5P {0x04A62093 6} + XCKU9P {0x0484A093 6} + XCKU11P {0x04A4E093 6} + XCKU11P_CIV {0x04A51093 6} + XCKU13P {0x04A52093 6} + XCKU15P {0x04A56093 6} + XCKU15P_CIV {0x04A59093 6} + XCVU065 {0x03939093 6} + XCVU065_CIV {0x0393b093 6} + XCVU080 {0x03843093 6} + XCVU080_CIV {0x03845093 6} + XCVU095 {0x03842093 6} + XCVU2P {0x04aea093 6} + XCVU3P {0x04B39093 6} + XCVU3P_CIV {0x04b3d093 6} + XCAU10P {0x04AC4033 6} + XCAU10P_FFVB676 {0x04AC4093 6} + XCAU15P {0x04AC2033 6} + XCAU15P_FFVB676 {0x04AC2093 6} + XCAU20P {0x04A65093 6} + XCAU25P {0x04A64093 6} + XCKU5P_CIV {0x04A64093 6} + XCKU19P {0x04ACF093 6} + XCKU19P_CIV {0x04AD3093 6} + XCKU085 {0x0380F093 12} + XCKU115 {0x0390D093 12} + XCVU125 {0x0392D093 12} + XCVU125_CIV {0x0392f093 12} + XCVU5P {0x04B2B093 12} + XCVU5P_CIV {0x04b2f093 12} + XCVU7P {0x04B29093 12} + XCVU7P_CIV {0x04b2d093 12} + XCVU160 {0x03933093 18} + XCVU190 {0x03931093 18} + XCVU440 {0x0396D093 18} + XCVU440_CIV {0x0396f093 18} + XCVU9P {0x04B31093 18} + XCVU9P_CIV {0x04b35093 18} + XCVU11P {0x04B49093 18} + XCVU11P_CIV {0x04b4f093 18} + XCU200_FSGD2104 {0x04b37093 18} + XCU250 {0x04b57093 24} + XCVU13P {0x04B51093 24} + XCVU13P_CIV {0x04b55093 24} + XCVU15P {0x04ba3093 24} + XCVU19P {0x04ba1093 24} + XCVU19P_CIV {0x04ba5093 24} } if { ![info exists CHIP] } { @@ -54,7 +83,25 @@ set _IRLEN [lindex $_XCU_DATA($CHIP) 1] # the 4 top bits (28:31) are the die stepping/revisions. ignore it. jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID -pld device virtex2 $_CHIPNAME.tap 1 +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart + +# set the correct instruction codes for jtag hub and +# at least the right code for jprogb, jstart and jshutdown for SSI devices +if { $_IRLEN == 6 } { + virtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23 +} elseif {$_IRLEN == 12 } { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d + virtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4 +} elseif {$_IRLEN == 18 } { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d + virtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4 +} else { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d + virtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924 +} set XCU_JSHUTDOWN 0x0d set XCU_JPROGRAM 0x0b @@ -62,6 +109,7 @@ set XCU_JSTART 0x0c set XCU_BYPASS 0x3f proc xcu_program {tap} { + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xcu_program'" global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS irscan $tap $XCU_JSHUTDOWN irscan $tap $XCU_JPROGRAM diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl index d28b9d9744..b24a67d0bd 100644 --- a/tcl/cpu/arc/v2.tcl +++ b/tcl/cpu/arc/v2.tcl @@ -173,8 +173,8 @@ proc arc_v2_init_regs { } { r19 19 uint32 r20 20 uint32 r21 21 uint32 - r22 23 uint32 - r23 24 uint32 + r22 22 uint32 + r23 23 uint32 r24 24 uint32 r25 25 uint32 gp 26 data_ptr diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg new file mode 100644 index 0000000000..0a3c7ba65b --- /dev/null +++ b/tcl/file_renaming.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This file is used to remap configuration files that has been +# renamed, except simple renames that are taken care automatically +# like: +# .../file.cfg ==> .../${vendor}/file.cfg +# .../vendor-file.cfg ==> .../vendor/file.cfg +# .../vendor_file.cfg ==> .../vendor/file.cfg +# +# The formatting below is a TCL dict, so pairs of key-value +# in a simple TCL list, using for each line +# old_name new_name +# including in each name one of the prefix folder between +# board, chip, cpld, cpu, fpga, interface, target, test, tools + +set _file_renaming { + board/nordic_nrf51822_mkit.cfg board/nordic/nrf51822-mkit.cfg + board/nordic_nrf51_dk.cfg board/nordic/nrf51-dk.cfg + board/nordic_nrf52_dk.cfg board/nordic/nrf52-dk.cfg + target/nrf51.cfg target/nordic/nrf51.cfg + target/nrf52.cfg target/nordic/nrf52.cfg + target/nrf53.cfg target/nordic/nrf53.cfg + target/nrf91.cfg target/nordic/nrf91.cfg +} diff --git a/tcl/fpga/altera-10m50.cfg b/tcl/fpga/altera-10m50.cfg index 1937cb4b63..94228d26fd 100644 --- a/tcl/fpga/altera-10m50.cfg +++ b/tcl/fpga/altera-10m50.cfg @@ -1,24 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# see MAX 10 FPGA Device Architecture -# Table 3-1: IDCODE Information for MAX 10 Devices -# Intel MAX 10M02 0x31810dd -# Intel MAX 10M04 0x318a0dd -# Intel MAX 10M08 0x31820dd -# Intel MAX 10M16 0x31830dd -# Intel MAX 10M25 0x31840dd -# Intel MAX 10M40 0x318d0dd -# Intel MAX 10M50 0x31850dd -# Intel MAX 10M02 0x31010dd -# Intel MAX 10M04 0x310a0dd -# Intel MAX 10M08 0x31020dd -# Intel MAX 10M16 0x31030dd -# Intel MAX 10M25 0x31040dd -# Intel MAX 10M40 0x310d0dd -# Intel MAX 10M50 0x31050dd +# file altera-10m50.cfg replaced by altera-max10.cfg +echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg" -jtag newtap 10m50 tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \ - -expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \ - -expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \ - -expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \ - -expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd +#just to be backward compatible: +#tap will be 10m50.tap instead of max10.tap: +set CHIPNAME 10m50 +source [find cpld/altera-max10.cfg] diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg new file mode 100644 index 0000000000..9cf680d5fd --- /dev/null +++ b/tcl/fpga/altera-arriaii.cfg @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Arria II FPGA +# Arria II Device Handbook +# Table 11–2. 32-Bit IDCODE for Arria II Devices + +#GX: +#EP2AGX45: 0x025120dd +#EP2AGX65: 0x025020dd +#EP2AGX95: 0x025130dd +#EP2AGX125: 0x025030dd +#EP2AGX190: 0x025140dd +#EP2AGX260: 0x025040dd +#EP2AGZ225: 0x024810dd +#EP2AGZ300: 0x0240a0dd +#EP2AGZ350: 0x024820dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME arriaii +} + +array set _ARRIA_2_DATA { + 0x025120dd {1227 1174 EP2AGX45} + 0x025020dd {1227 -1 EP2AGX65} + 0x025130dd {1467 -1 EP2AGX95} + 0x025030dd {1467 -1 EP2AGX125} + 0x025140dd {1971 -1 EP2AGX190} + 0x025040dd {1971 -1 EP2AGX260} + 0x024810dd {2274 -1 EP2AGZ225} + 0x0240a0dd {2682 -1 EP2AGZ300} + 0x024820dd {2682 -1 EP2AGZ350} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _ARRIA_2_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}" + diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg new file mode 100644 index 0000000000..0898c74e17 --- /dev/null +++ b/tcl/fpga/altera-cyclone10.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone 10 FPGA +# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html +# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cyclone10 +} + +array set _CYCLONE_10_DATA { + 0x020f10dd { 603 226 10cl006_10cl010} + 0x020f20dd {1080 409 10cl016} + 0x020f30dd { 732 286 10cl025} + 0x020f40dd {1632 604 10cl040} + 0x020f50dd {1164 442 10cl055} + 0x020f60dd {1314 502 10cl080} + 0x020f70dd {1620 613 10cl120} + 0x02e120dd {1339 -1 GX085} + 0x02e320dd {1339 -1 GX105} + 0x02e720dd {1339 -1 GX150} + 0x02ef20dd {1339 -1 GX220} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_10_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10 +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}" diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg new file mode 100644 index 0000000000..b0da418c0a --- /dev/null +++ b/tcl/fpga/altera-cycloneiii.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone III FPGA +# see Cyclone III Device Handbook +# Table 12-2: Device IDCODE for Cyclone III Device Family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cycloneiii +} + +array set _CYCLONE_3_DATA { + 0x020f10dd { 603 226 EP3C5_EP3C10} + 0x020f20dd {1080 409 EP3C16} + 0x020f30dd { 732 286 EP3C25} + 0x020f40dd {1632 604 EP3C40} + 0x020f50dd {1164 442 EP3C55} + 0x020f60dd {1314 502 EP3C80} + 0x020f70dd {1620 613 EP3C120} + 0x027010dd {1314 226 EP3CLS70} + 0x027000dd {1314 226 EP3CLS100} + 0x027030dd {1314 409 EP3CLS150} + 0x027020dd {1314 409 EP3CLS200} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_3_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}" diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg new file mode 100644 index 0000000000..44eb89dec4 --- /dev/null +++ b/tcl/fpga/altera-cycloneiv.cfg @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone IV FPGA +# see Cyclone IV Device Handbook +# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cycloneiv +} + +array set _CYCLON_4_DATA { + 0x020f10dd { 603 226 EP4CE6_EP4CE10} + 0x020f20dd {1080 409 EP4CE15} + 0x020f30dd { 732 286 EP4CE22} + 0x020f40dd {1632 604 EP4CE30_EP4CE40} + 0x020f50dd {1164 442 EP4CE55} + 0x020f60dd {1314 502 EP4CE75} + 0x020f70dd {1620 613 EP4CE115} + 0x028010dd { 260 229 EP4CGX15} + 0x028120dd { 494 463 EP4CGX22} + 0x028020dd { 494 463 EP4CGX30} + 0x028230dd {1006 943 EP4CGX30} + 0x028130dd {1006 943 EP4CGX50} + 0x028030dd {1006 943 EP4CGX75} + 0x028140dd {1495 1438 EP4CGX110} + 0x028040dd {1495 1438 EP4CGX150} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLON_4_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}" diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg new file mode 100644 index 0000000000..8d19cd8de8 --- /dev/null +++ b/tcl/fpga/altera-cyclonev.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone 5 FPGA +# see Cyclone V Device Handbook +# Table 9-1: IDCODE Information for Cyclone V Devices + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cyclonev +} + +array set _CYCLONE_5_DATA { + 0x02b150dd { 864 163 5CEA2} + 0x02d020dd {1485 19 5CSEA6_5CSXC6_5CSTD6} + 0x02b040dd {1728 -1 5CGXC9_5CGTD9} + 0x02b050dd { 864 163 5CEA4} + 0x02b030dd {1488 19 5CGXC7_5CGTD7} + 0x02d120dd {1485 -1 5CSEA5_5CSXC5_5CSTD5} + 0x02b220dd {1104 19 5CEA5} + 0x02b020dd {1104 19 5CGXC5_5CGTD5} + 0x02d010dd {1197 -1 5CSEA4_5CSXC4} + 0x02b120dd {1104 19 5CGXC4} + 0x02b140dd {1728 -1 5CEA9} + 0x02b010dd { 720 19 5CGXC3} + 0x02b130dd {1488 19 5CEA7} + 0x02d110dd {1197 -1 5CSEA2_5CSXC2} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_5_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}" diff --git a/tcl/fpga/altera-ep3c10.cfg b/tcl/fpga/altera-ep3c10.cfg index 7c231f9424..d7a92d7484 100644 --- a/tcl/fpga/altera-ep3c10.cfg +++ b/tcl/fpga/altera-ep3c10.cfg @@ -1,6 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# Altera Cyclone III EP3C10 -# see Cyclone III Device Handbook, Volume 1; -# Table 14–5. 32-Bit Cyclone III Device IDCODE -jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10 +# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg +echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg" + +#just to be backward compatible: +#tap will be ep3c10.tap instead of cycloneiii.tap: +set CHIPNAME ep3c10 +source [find fpga/altera-cycloneiii.cfg] diff --git a/tcl/fpga/altera_common_init.cfg b/tcl/fpga/altera_common_init.cfg new file mode 100644 index 0000000000..683a844cba --- /dev/null +++ b/tcl/fpga/altera_common_init.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc set_bscan_checkpos_on_setup {chipname data} { + set tapid_w_version [jtag cget $chipname.tap -idcode] + set version_mask 0x0fffffff + set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]] + intel set_bscan $chipname.pld [lindex $data($tapid) 0] + intel set_check_pos $chipname.pld [lindex $data($tapid) 1] +} diff --git a/tcl/fpga/efinix_titanium.cfg b/tcl/fpga/efinix_titanium.cfg new file mode 100644 index 0000000000..3c2cdd71f7 --- /dev/null +++ b/tcl/fpga/efinix_titanium.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# efinix titanium +# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME titanium +} + +jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \ + -expected-id 0x10661A79 \ + -expected-id 0x00360A79 \ + -expected-id 0x10660A79 \ + -expected-id 0x00681A79 \ + -expected-id 0x00688A79 \ + -expected-id 0x00682A79 \ + -expected-id 0x0068CA79 \ + -expected-id 0x00680A79 \ + -expected-id 0x00684A79 + +pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium diff --git a/tcl/fpga/efinix_trion.cfg b/tcl/fpga/efinix_trion.cfg new file mode 100644 index 0000000000..1c789f5642 --- /dev/null +++ b/tcl/fpga/efinix_trion.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# efinix trion +# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME trion +} + +jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \ + -expected-id 0x00210A79 \ + -expected-id 0x00240A79 \ + -expected-id 0x00220A79 + +pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion diff --git a/tcl/fpga/gatemate.cfg b/tcl/fpga/gatemate.cfg new file mode 100644 index 0000000000..e8f338236d --- /dev/null +++ b/tcl/fpga/gatemate.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# GateMateTM FPGA +# https://www.colognechip.com/programmable-logic/gatemate/ +# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gatemate +} + +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x20000001 + +pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/gowin_gw1n.cfg b/tcl/fpga/gowin_gw1n.cfg new file mode 100644 index 0000000000..5e85066f99 --- /dev/null +++ b/tcl/fpga/gowin_gw1n.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Gowin FPGA IDCODEs +# from JTAG Programming and Configuration Guide +# http://cdn.gowinsemi.com.cn/TN653E.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gw1n +} + +jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \ + -expected-id 0x0900281B \ + -expected-id 0x0900381B \ + -expected-id 0x0100681B \ + -expected-id 0x0300081B \ + -expected-id 0x0300181B \ + -expected-id 0x0120681B \ + -expected-id 0x0100381B \ + -expected-id 0x1100381B \ + -expected-id 0x0100981B \ + -expected-id 0x1100581B \ + -expected-id 0x1100481B \ + -expected-id 0x0100181B \ + -expected-id 0x1100181B \ + -expected-id 0x0100481B + +pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_certus.cfg b/tcl/fpga/lattice_certus.cfg new file mode 100644 index 0000000000..9ddb7d8431 --- /dev/null +++ b/tcl/fpga/lattice_certus.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME certus +} + +# Lattice Certus +# +# Certus NX LFD2NX-17 0x310f0043 +# Certus NX LFD2NX-40 0x310f1043 + + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x310F1043 -expected-id 0x310F0043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_certuspro.cfg b/tcl/fpga/lattice_certuspro.cfg new file mode 100644 index 0000000000..acaaa57392 --- /dev/null +++ b/tcl/fpga/lattice_certuspro.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME certuspro +} + +# Lattice CertusPro +# +# 0x010f4043 - LFCPNX-100 +# 0x 043 - LFCPNX-50 + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x010f4043 +# -expected-id 0x01112043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_ecp2.cfg b/tcl/fpga/lattice_ecp2.cfg new file mode 100644 index 0000000000..5b01787bdd --- /dev/null +++ b/tcl/fpga/lattice_ecp2.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ecp2 +} + +# Lattice ECP2 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M +# +# LFE2M20E: 0x01279043 +# LFE2M35E: 0x0127A043 +# LFE2M50E: 0x0127B043 +# LFE2M70E: 0x0127C043 +# LFE2M100E: 0x0127D043 +# LFEC2_6E: 0x01270043 +# LFEC2_12E: 0x01271043 +# LFEC2_20E: 0x01272043 +# LFEC2_35E: 0x01274043 +# LFEC2_50E: 0x01273043 +# LFEC2_70E: 0x01275043 + +jtag newtap $_CHIPNAME tap -irlen 8 \ + -expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \ + -expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \ + -expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \ + -expected-id 0x01273043 -expected-id 0x01275043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_ecp3.cfg b/tcl/fpga/lattice_ecp3.cfg new file mode 100644 index 0000000000..21c8ffa842 --- /dev/null +++ b/tcl/fpga/lattice_ecp3.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ecp3 +} + +# Lattice ECP3 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3 +# +# LFE3_17: 0x01010043 +# LFE3_35: 0x01012043 +# LFE3_95: 0x01014043 and LFE3_70 +# LFE3_150: 0x01015043 + +jtag newtap $_CHIPNAME tap -irlen 8 \ + -expected-id 0x01010043 -expected-id 0x01012043 \ + -expected-id 0x01014043 -expected-id 0x01015043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_ecp5.cfg b/tcl/fpga/lattice_ecp5.cfg index a94ada7404..cdc63f0c11 100644 --- a/tcl/fpga/lattice_ecp5.cfg +++ b/tcl/fpga/lattice_ecp5.cfg @@ -26,3 +26,5 @@ jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ -expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \ -expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \ -expected-id 0x81113043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/tcl/fpga/lattice_machxo3.cfg b/tcl/fpga/lattice_machxo3.cfg new file mode 100644 index 0000000000..37fa054300 --- /dev/null +++ b/tcl/fpga/lattice_machxo3.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME machxo3 +} + +# Lattice MachXO3 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3 +# +# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121 +# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49 +# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81 +# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324 +# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256 +# 0x412bb043 - LCMXO3L_2100C_XXBG256 +# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324 +# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400 +# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484 +# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36 +# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49 +# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81 +# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324 +# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256 +# 0x612bb043 - LCMXO3LF_2100C_XXBG256 +# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324 +# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400 +# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484 +# 0xc12b2043 - LCMXO3L_640E_XXMG121 +# 0xc12b4043 - LCMXO3L_2100E_XXMG324 +# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256 +# 0xc12bc043 - LCMXO3L_2100C_XXBG324 +# 0xc12bd043 - LCMXO3L_4300C_XXBG400 +# 0xe12b2043 - LCMXO3LF_640E_XXMG121 +# 0xe12b3043 - LCMXO3LF_1300E_XXMG256 +# 0xe12b4043 - LCMXO3LF_2100E_XXMG324 +# 0xe12bb043 - LCMXO3LF_1300C_XXBG256 +# 0xe12bc043 - LCMXO3LF_2100C_XXBG324 +# 0xe12bd043 - LCMXO3LF_4300C_XXBG400 + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \ + -expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \ + -expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \ + -expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \ + -expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \ + -expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \ + -expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \ + -expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \ + -expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \ + -expected-id 0xe12bc043 -expected-id 0xe12bd043 diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg index 56f8c14119..6b16b78fb1 100644 --- a/tcl/fpga/xilinx-dna.cfg +++ b/tcl/fpga/xilinx-dna.cfg @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later +# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf proc xilinx_dna_addr {chip} { array set addrs { + Spartan3 0x31 Spartan6 0x30 Series7 0x17 } @@ -43,3 +45,7 @@ proc xc7_get_dna {tap} { proc xc6s_get_dna {tap} { return [xilinx_get_dna $tap Spartan6] } + +proc xc3s_get_dna {tap} { + return [xilinx_get_dna $tap Spartan3] +} diff --git a/tcl/fpga/xilinx-xc3s.cfg b/tcl/fpga/xilinx-xc3s.cfg new file mode 100644 index 0000000000..7c17206c95 --- /dev/null +++ b/tcl/fpga/xilinx-xc3s.cfg @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Xilinx Spartan3 generation +# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc3s +} + +# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf +# the 4 top bits (28:31) are the die stepping, ignore them. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x02210093 \ + -expected-id 0x02218093 \ + -expected-id 0x02220093 \ + -expected-id 0x02228093 \ + -expected-id 0x02230093 \ + -expected-id 0x02610093 \ + -expected-id 0x02618093 \ + -expected-id 0x02620093 \ + -expected-id 0x02628093 \ + -expected-id 0x02630093 \ + -expected-id 0x03840093 \ + -expected-id 0x0384E093 \ + -expected-id 0x01C10093 \ + -expected-id 0x01C1A093 \ + -expected-id 0x01C22093 \ + -expected-id 0x01C2E093 \ + -expected-id 0x01C3A093 \ + -expected-id 0x0140C093 \ + -expected-id 0x01414093 \ + -expected-id 0x0141C093 \ + -expected-id 0x01428093 \ + -expected-id 0x01434093 \ + -expected-id 0x01440093 \ + -expected-id 0x01448093 \ + -expected-id 0x01450093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap + +source [find fpga/xilinx-dna.cfg] diff --git a/tcl/interface/angie.cfg b/tcl/interface/angie.cfg new file mode 100644 index 0000000000..26cbe393b5 --- /dev/null +++ b/tcl/interface/angie.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2023 by NanoXplore, France - all rights reserved +# +# configuration file for ANGIE Adapter from NanoXplore. +# + +adapter driver angie +adapter speed 10000 +reset_config trst_and_srst trst_push_pull srst_open_drain diff --git a/tcl/interface/ast2600-gpiod.cfg b/tcl/interface/ast2600-gpiod.cfg new file mode 100644 index 0000000000..5cad02fbdf --- /dev/null +++ b/tcl/interface/ast2600-gpiod.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Use AST2600 GPIO through linuxgpiod +# +# +-----------+-------------+-------------+ +# | signal | GPIO name | gpio offset | +# +-----------+-------------+-------------+ +# | TCK/SWCLK | GPIOI2 | 66 | +# | TMS/SWDIO | GPIOI3 | 67 | +# | TDI | GPIOI1 | 65 | +# | TDO | GPIOI4 | 68 | +# | nTRST | GPIOI0 | 64 | +# +-----------+-------------+-------------+ + +adapter driver linuxgpiod + +adapter gpio trst 64 -chip 0 +adapter gpio tdi 65 -chip 0 +adapter gpio tck 66 -chip 0 +adapter gpio swclk 66 -chip 0 +adapter gpio tms 67 -chip 0 +adapter gpio swdio 67 -chip 0 +adapter gpio tdo 68 -chip 0 + +reset_config trst_only separate trst_push_pull diff --git a/tcl/interface/beaglebone-jtag-native.cfg b/tcl/interface/beaglebone-jtag-native.cfg index cd32ca49b5..0240e5d8b8 100644 --- a/tcl/interface/beaglebone-jtag-native.cfg +++ b/tcl/interface/beaglebone-jtag-native.cfg @@ -16,13 +16,21 @@ adapter driver am335xgpio # am335xgpio speed SPEED_COEFF SPEED_OFFSET am335xgpio speed_coeffs 600000 575 -am335xgpio tdo_num 20 -am335xgpio tdi_num 60 -am335xgpio tms_num 4 -am335xgpio tck_num 2 +# BeagleBone pin P9_41 +adapter gpio tdo 20 -chip 0 -am335xgpio led_num 51 -am335xgpio led_on_state on +# BeagleBone pin P9_12 +adapter gpio tdi 28 -chip 1 -am335xgpio srst_num 65 +# BeagleBone pin P9_18 +adapter gpio tms 4 -chip 0 + +# BeagleBone pin P9_22 +adapter gpio tck 2 -chip 0 + +# BeagleBone pin P9_16 +adapter gpio led 19 -chip 1 + +# BeagleBone pin P8_18 +adapter gpio srst 1 -chip 2 reset_config srst_only srst_push_pull diff --git a/tcl/interface/beaglebone-swd-native.cfg b/tcl/interface/beaglebone-swd-native.cfg index f7bff6e57b..6c40849798 100644 --- a/tcl/interface/beaglebone-swd-native.cfg +++ b/tcl/interface/beaglebone-swd-native.cfg @@ -16,14 +16,18 @@ adapter driver am335xgpio # am335xgpio speed SPEED_COEFF SPEED_OFFSET am335xgpio speed_coeffs 600000 575 -am335xgpio swclk_num 2 -am335xgpio swdio_num 4 -am335xgpio swdio_dir_num 60 -am335xgpio swdio_dir_output_state on +# BeagleBone pin P9_22 +adapter gpio swclk 2 -chip 0 + +# BeagleBone pin P9_18 +adapter gpio swdio 4 -chip 0 + +# BeagleBone pin P9_12 +adapter gpio swdio_dir 28 -chip 1 # USR0 LED -am335xgpio led_num 53 -am335xgpio led_on_state on +adapter gpio led 21 -chip 1 -am335xgpio srst_num 65 +# BeagleBone pin P8_18 +adapter gpio srst 1 -chip 2 reset_config srst_only srst_push_pull diff --git a/tcl/interface/calao-usb-a9260.cfg b/tcl/interface/calao-usb-a9260.cfg deleted file mode 100644 index ff652ef8fb..0000000000 --- a/tcl/interface/calao-usb-a9260.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# CALAO Systems USB-A9260 common -C01 -C02 setup -# -# http://www.calao-systems.com/ -# -# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg. -# - -adapter srst delay 200 -jtag_ntrst_delay 200 diff --git a/tcl/interface/dln-2-gpiod.cfg b/tcl/interface/dln-2-gpiod.cfg index cd6061fd98..c9e33881f7 100644 --- a/tcl/interface/dln-2-gpiod.cfg +++ b/tcl/interface/dln-2-gpiod.cfg @@ -17,11 +17,14 @@ adapter driver linuxgpiod -linuxgpiod gpiochip 0 -linuxgpiod jtag_nums 2 3 4 1 -linuxgpiod trst_num 5 -linuxgpiod swd_nums 2 3 -linuxgpiod srst_num 0 -linuxgpiod led_num 6 +adapter gpio srst 0 -chip 0 +adapter gpio tdo 1 -chip 0 +adapter gpio tck 2 -chip 0 +adapter gpio swclk 2 -chip 0 +adapter gpio tms 3 -chip 0 +adapter gpio swdio 3 -chip 0 +adapter gpio tdi 4 -chip 0 +adapter gpio trst 5 -chip 0 +adapter gpio led 6 -chip 0 reset_config trst_and_srst separate srst_push_pull diff --git a/tcl/interface/esp_usb_jtag.cfg b/tcl/interface/esp_usb_jtag.cfg new file mode 100644 index 0000000000..40427d0e3e --- /dev/null +++ b/tcl/interface/esp_usb_jtag.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Espressif builtin USB-JTAG adapter +# + +adapter driver esp_usb_jtag + +espusbjtag vid_pid 0x303a 0x1001 +espusbjtag caps_descriptor 0x2000 diff --git a/tcl/interface/ft232r/radiona_ulx3s.cfg b/tcl/interface/ft232r/radiona_ulx3s.cfg index 424777e9e8..3fc3d7105e 100644 --- a/tcl/interface/ft232r/radiona_ulx3s.cfg +++ b/tcl/interface/ft232r/radiona_ulx3s.cfg @@ -7,10 +7,10 @@ adapter driver ft232r adapter speed 1000 -ft232r_vid_pid 0x0403 0x6015 -ft232r_tck_num DSR -ft232r_tms_num DCD -ft232r_tdi_num RI -ft232r_tdo_num CTS -ft232r_trst_num RTS -ft232r_srst_num DTR +ft232r vid_pid 0x0403 0x6015 +ft232r tck_num DSR +ft232r tms_num DCD +ft232r tdi_num RI +ft232r tdo_num CTS +ft232r trst_num RTS +ft232r srst_num DTR diff --git a/tcl/interface/ftdi/ashling-opella-ld-jtag.cfg b/tcl/interface/ftdi/ashling-opella-ld-jtag.cfg old mode 100755 new mode 100644 diff --git a/tcl/interface/ftdi/ashling-opella-ld-swd.cfg b/tcl/interface/ftdi/ashling-opella-ld-swd.cfg old mode 100755 new mode 100644 diff --git a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg deleted file mode 100644 index c84e778746..0000000000 --- a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# CALAO Systems USB-A9260-C01 -# -# http://www.calao-systems.com/ -# - -echo "WARNING!" -echo "This file was not tested with real interface, but is assumed to work as this" -echo "interface uses the same layout as configs that were verified. Please report your" -echo "experience with this file to openocd-devel mailing list, so it could be marked" -echo "as working or fixed." - -adapter driver ftdi -ftdi device_desc "USB-A9260" -ftdi vid_pid 0x0403 0x6010 - -ftdi layout_init 0x0c08 0x0f1b -ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 - -script interface/calao-usb-a9260.cfg -script target/at91sam9260minimal.cfg diff --git a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg deleted file mode 100644 index 9d79b26005..0000000000 --- a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# CALAO Systems USB-A9260-C02 -# -# http://www.calao-systems.com/ -# - -echo "WARNING!" -echo "This file was not tested with real interface, but is assumed to work as this" -echo "interface uses the same layout as configs that were verified. Please report your" -echo "experience with this file to openocd-devel mailing list, so it could be marked" -echo "as working or fixed." - -adapter driver ftdi -ftdi device_desc "USB-A9260" -ftdi vid_pid 0x0403 0x6001 - -ftdi layout_init 0x0c08 0x0f1b -ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 - -script interface/calao-usb-a9260.cfg -script target/at91sam9260minimal.cfg diff --git a/tcl/interface/ftdi/digilent-hs2.cfg b/tcl/interface/ftdi/digilent-hs2.cfg index e9fe94eb6c..89c9e4b6c4 100644 --- a/tcl/interface/ftdi/digilent-hs2.cfg +++ b/tcl/interface/ftdi/digilent-hs2.cfg @@ -2,11 +2,17 @@ # this supports JTAG-HS2 (and apparently Nexys4 as well) +# ADBUS5 controls TMS tri-state buffer enable +# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI +# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS + adapter driver ftdi ftdi device_desc "Digilent Adept USB Device" ftdi vid_pid 0x0403 0x6014 ftdi channel 0 ftdi layout_init 0x00e8 0x60eb +ftdi layout_signal SWD_EN -data 0x6000 +ftdi layout_signal SWDIO_OE -data 0x20 reset_config none diff --git a/tcl/interface/ftdi/esp32_devkitj_v1.cfg b/tcl/interface/ftdi/esp32_devkitj_v1.cfg index c34a500a6a..1b455a9ac8 100644 --- a/tcl/interface/ftdi/esp32_devkitj_v1.cfg +++ b/tcl/interface/ftdi/esp32_devkitj_v1.cfg @@ -21,5 +21,5 @@ ftdi layout_signal LED4 -data 0x8000 # ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin. # The target code doesn't handle SRST reset properly yet, so this is commented out: -# ftdi_layout_signal nSRST -oe 0x0020 +# ftdi layout_signal nSRST -oe 0x0020 # reset_config srst_only diff --git a/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg b/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg index b61caff64a..df4955f8a1 100644 --- a/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg +++ b/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg @@ -7,8 +7,8 @@ adapter driver ftdi adapter speed 10000 -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0xfff8 0xfffb +ftdi layout_init 0xfff8 0xfffb transport select jtag diff --git a/tcl/interface/ftdi/sipeed-rv-debugger.cfg b/tcl/interface/ftdi/sipeed-rv-debugger.cfg new file mode 100644 index 0000000000..ca65398c6e --- /dev/null +++ b/tcl/interface/ftdi/sipeed-rv-debugger.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Interface file for BL702-based SIPEED RV Debugger +# + +adapter driver ftdi +adapter speed 6000 + +ftdi device_desc "JTAG Debugger" +ftdi vid_pid 0x0403 0x6010 +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nSRST -oe 0x0020 -data 0x0020 diff --git a/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg new file mode 100644 index 0000000000..8a804eca67 --- /dev/null +++ b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Sipeed USB-JTAG/TTL RISC-V Debugger +# +# https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html +# + +adapter driver ftdi +ftdi device_desc "Dual RS232" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 0 + +# Every pin set as high impedance except TCK, TDI, TDO, TMS and RST +ftdi layout_init 0x0028 0x002b + +transport select jtag + +# nSRST defined on pin RST of the Debugger (pin ADBUS5 [AD5] on the FT2232D chip) +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/tcl/interface/ftdi/xt_kc705_ml605.cfg b/tcl/interface/ftdi/xt_kc705_ml605.cfg new file mode 100644 index 0000000000..dda8c0a2b6 --- /dev/null +++ b/tcl/interface/ftdi/xt_kc705_ml605.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232 +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 +# Specify "adapter serial <identifier>" here as needed + +ftdi layout_init 0x0010 0x007b +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -ndata 0x0020 diff --git a/tcl/interface/jtag_hat_rpi2.cfg b/tcl/interface/jtag_hat_rpi2.cfg index 495ff0f042..cd1cbfb8af 100644 --- a/tcl/interface/jtag_hat_rpi2.cfg +++ b/tcl/interface/jtag_hat_rpi2.cfg @@ -7,31 +7,35 @@ adapter driver bcm2835gpio -bcm2835gpio_peripheral_base 0x3F000000 +bcm2835gpio peripheral_base 0x3F000000 # Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET # These depend on system clock, calibrated for stock 700MHz # bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET -bcm2835gpio_speed_coeffs 146203 36 +bcm2835gpio speed_coeffs 146203 36 # Each of the JTAG lines need a gpio number set: tck tms tdi tdo # Header pin numbers: 23 22 19 21 -bcm2835gpio_jtag_nums 11 25 10 9 +adapter gpio tck -chip 0 11 +adapter gpio tms -chip 0 25 +adapter gpio tdi -chip 0 10 +adapter gpio tdo -chip 0 9 # Each of the SWD lines need a gpio number set: swclk swdio # Header pin numbers: 23 22 -bcm2835gpio_swd_nums 11 25 +adapter gpio swclk -chip 0 11 +adapter gpio swdio -chip 0 25 # Direction pin for SWDIO level shifting buffer -bcm2835gpio_swdio_dir_num 6 +adapter gpio swdio_dir -chip 0 6 # If you define trst or srst, use appropriate reset_config # Header pin numbers: TRST - 26, SRST - 18 -bcm2835gpio_trst_num 7 +adapter gpio trst -chip 0 7 #reset_config trst_only -bcm2835gpio_srst_num 24 +adapter gpio srst -chip 0 24 #reset_config srst_only # or if you have both connected diff --git a/tcl/interface/nds32-aice.cfg b/tcl/interface/nds32-aice.cfg deleted file mode 100644 index 1d9717c4c2..0000000000 --- a/tcl/interface/nds32-aice.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# Andes AICE -# -# http://www.andestech.com -# - -adapter driver aice -aice desc "Andes AICE adapter" -# adapter serial "C001-42163" -aice vid_pid 0x1CFC 0x0000 -aice port aice_usb -reset_config trst_and_srst -adapter speed 24000 -aice retry_times 50 -aice count_to_check_dbger 30 diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg index 2a4bc0b93b..be68347e73 100644 --- a/tcl/interface/nulink.cfg +++ b/tcl/interface/nulink.cfg @@ -5,9 +5,9 @@ # adapter driver hla -hla_layout nulink -hla_device_desc "Nu-Link" -hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201 +hla layout nulink +hla device_desc "Nu-Link" +hla vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201 # Only swd is supported -transport select hla_swd +transport select swd diff --git a/tcl/interface/parport.cfg b/tcl/interface/parport.cfg index b9fceeb852..8fb1c148b2 100644 --- a/tcl/interface/parport.cfg +++ b/tcl/interface/parport.cfg @@ -5,17 +5,6 @@ # # Addresses: 0x378/LPT1 or 0x278/LPT2 ... # +echo "DEPRECATED: use interface/parport/wiggler.cfg instead of deprecated interface/parport.cfg" -if { [info exists PARPORTADDR] } { - set _PARPORTADDR $PARPORTADDR -} else { - if {$tcl_platform(platform) eq "windows"} { - set _PARPORTADDR 0x378 - } { - set _PARPORTADDR 0 - } -} - -adapter driver parport -parport port $_PARPORTADDR -parport cable wiggler +source [find interface/parport/wiggler.cfg] diff --git a/tcl/interface/parport/dlc5.cfg b/tcl/interface/parport/dlc5.cfg new file mode 100644 index 0000000000..24acea7a95 --- /dev/null +++ b/tcl/interface/parport/dlc5.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Xilinx Parallel Cable III 'DLC 5' (and various clones) +# +# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + set _PARPORTADDR 0 +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable dlc5 diff --git a/tcl/interface/parport/wiggler.cfg b/tcl/interface/parport/wiggler.cfg new file mode 100644 index 0000000000..b9fceeb852 --- /dev/null +++ b/tcl/interface/parport/wiggler.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Parallel port wiggler (many clones available) on port 0x378 +# +# Addresses: 0x378/LPT1 or 0x278/LPT2 ... +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + if {$tcl_platform(platform) eq "windows"} { + set _PARPORTADDR 0x378 + } { + set _PARPORTADDR 0 + } +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable wiggler diff --git a/tcl/interface/parport_dlc5.cfg b/tcl/interface/parport_dlc5.cfg index 24acea7a95..83f3b56c48 100644 --- a/tcl/interface/parport_dlc5.cfg +++ b/tcl/interface/parport_dlc5.cfg @@ -5,13 +5,6 @@ # # http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html # +echo "DEPRECATED: use interface/parport/dlc5.cfg instead of deprecated interface/parport_dlc5.cfg" -if { [info exists PARPORTADDR] } { - set _PARPORTADDR $PARPORTADDR -} else { - set _PARPORTADDR 0 -} - -adapter driver parport -parport port $_PARPORTADDR -parport cable dlc5 +source [find interface/parport/dlc5.cfg] diff --git a/tcl/interface/raspberrypi-gpio-connector.cfg b/tcl/interface/raspberrypi-gpio-connector.cfg new file mode 100644 index 0000000000..af7266b51b --- /dev/null +++ b/tcl/interface/raspberrypi-gpio-connector.cfg @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Config for Raspberry Pi GPIO header +# +# This is best used with a fast enough buffer but also +# is suitable for direct connection if the target voltage +# matches RPi's 3.3V and the cable is short enough. +# +# Do not forget the GND connection, e.g. pin 20 of the GPIO header. +# + +if { [info exists GPIO_CHIP] } { + set _GPIO_CHIP $GPIO_CHIP +} else { + set _GPIO_CHIP 0 +} + +# GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default. +# The JTAG/SWD specification requires pull-up at the target board +# for either signal. Connecting the signal pulled-up on the target +# to the pull-down on the adapter is not a good idea. +# GPIO 8 is pulled-up by default. +echo "Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!" + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +# Header pin numbers: 23 24 19 21 +adapter gpio tck -chip $_GPIO_CHIP 11 +adapter gpio tms -chip $_GPIO_CHIP 8 +adapter gpio tdi -chip $_GPIO_CHIP 10 +adapter gpio tdo -chip $_GPIO_CHIP 9 + +# Each of the SWD lines need a gpio number set: swclk swdio +# Header pin numbers: 23 24 +adapter gpio swclk -chip $_GPIO_CHIP 11 +adapter gpio swdio -chip $_GPIO_CHIP 8 + +# If you define trst or srst, use appropriate reset_config +# Header pin numbers: TRST - 26, SRST - 18 + +# adapter gpio trst -chip $_GPIO_CHIP 7 +# reset_config trst_only + +# adapter gpio srst -chip $_GPIO_CHIP 24 +# reset_config srst_only srst_push_pull + +# or if you have both connected, +# reset_config trst_and_srst srst_push_pull diff --git a/tcl/interface/raspberrypi-native.cfg b/tcl/interface/raspberrypi-native.cfg index 6d5c3bfd49..c80f90a146 100644 --- a/tcl/interface/raspberrypi-native.cfg +++ b/tcl/interface/raspberrypi-native.cfg @@ -1,40 +1,75 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# -# Config for using Raspberry Pi's expansion header -# -# This is best used with a fast enough buffer but also -# is suitable for direct connection if the target voltage -# matches RPi's 3.3V and the cable is short enough. -# -# Do not forget the GND connection, pin 6 of the expansion header. -# +# Config for Raspberry Pi used as a bitbang adapter. +# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html + +# Supports all models with 40-pin or 26-pin GPIO connector up to Raspberry Pi 4 B +# also supports Raspberry Pi Zero, Zero W and Zero 2 W. + +# Adapter speed calibration is computed from cpufreq/scaling_max_freq. +# Adjusts automatically if CPU is overclocked. adapter driver bcm2835gpio -bcm2835gpio peripheral_base 0x20000000 +proc read_file { name } { + if {[catch {open $name r} fd]} { + return "" + } + set result [read $fd] + close $fd + return $result +} -# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET -# These depend on system clock, calibrated for stock 700MHz -# bcm2835gpio speed SPEED_COEFF SPEED_OFFSET -bcm2835gpio speed_coeffs 113714 28 +proc measure_clock {} { + set result [exec vcgencmd measure_clock arm] + set clock_hz [lindex [split $result "="] 1] + expr { $clock_hz / 1000 } +} + +proc get_max_cpu_clock { default } { + set clock [read_file /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq] + if { $clock > 100000 } { + return $clock + } -# Each of the JTAG lines need a gpio number set: tck tms tdi tdo -# Header pin numbers: 23 22 19 21 -bcm2835gpio jtag_nums 11 25 10 9 + # cpufreq not available. As the last resort try Broadcom's proprietary utility + if {![catch measure_clock clock] && $clock > 100000} { + return $clock + } -# Each of the SWD lines need a gpio number set: swclk swdio -# Header pin numbers: 23 22 -bcm2835gpio swd_nums 11 25 + echo "Warn : Host CPU clock unknown." + echo "Warn : Using the highest possible value $default kHz as a safe default." + echo "Warn : Expect JTAG/SWD clock significantly slower than requested." -# If you define trst or srst, use appropriate reset_config -# Header pin numbers: TRST - 26, SRST - 18 + return $default +} -# bcm2835gpio trst_num 7 -# reset_config trst_only +set compat [read_file /proc/device-tree/compatible] +set clocks_per_timing_loop 4 -# bcm2835gpio srst_num 24 -# reset_config srst_only srst_push_pull +if {[string match *bcm2711* $compat]} { + set speed_offset 52 +} elseif {[string match *bcm2837* $compat] || [string match *bcm2710* $compat]} { + set speed_offset 34 +} elseif {[string match *bcm2836* $compat] || [string match *bcm2709* $compat]} { + set speed_offset 36 +} elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} { + set clocks_per_timing_loop 6 + set speed_offset 32 +} elseif {[string match *bcm2712* $compat]} { + echo "Error: Raspberrypi Pi 5 has moved GPIOs to PCIe connected RP1 chip." + echo "Error: Native GPIO handling is not supported, use 'raspberrypi5-gpiod.cfg'" + shutdown +} else { + set speed_offset 32 + echo "Warn : Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested." +} + +set clock [get_max_cpu_clock 2000000] +set speed_coeff [expr { $clock / $clocks_per_timing_loop }] + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# The coefficients depend on system clock and CPU frequency scaling. +bcm2835gpio speed_coeffs $speed_coeff $speed_offset -# or if you have both connected, -# reset_config trst_and_srst srst_push_pull +source [find interface/raspberrypi-gpio-connector.cfg] diff --git a/tcl/interface/raspberrypi2-native.cfg b/tcl/interface/raspberrypi2-native.cfg index 547df0872f..fe9186f239 100644 --- a/tcl/interface/raspberrypi2-native.cfg +++ b/tcl/interface/raspberrypi2-native.cfg @@ -1,40 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# -# Config for using Raspberry Pi's expansion header -# -# This is best used with a fast enough buffer but also -# is suitable for direct connection if the target voltage -# matches RPi's 3.3V and the cable is short enough. -# -# Do not forget the GND connection, pin 6 of the expansion header. -# +echo "WARNING: interface/raspberrypi2-native.cfg is deprecated." +echo "WARNING: Please use interface/raspberrypi-native.cfg for all Raspberry Pi models." -adapter driver bcm2835gpio - -bcm2835gpio peripheral_base 0x3F000000 - -# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET -# These depend on system clock, calibrated for stock 700MHz -# bcm2835gpio speed SPEED_COEFF SPEED_OFFSET -bcm2835gpio speed_coeffs 146203 36 - -# Each of the JTAG lines need a gpio number set: tck tms tdi tdo -# Header pin numbers: 23 22 19 21 -bcm2835gpio jtag_nums 11 25 10 9 - -# Each of the SWD lines need a gpio number set: swclk swdio -# Header pin numbers: 23 22 -bcm2835gpio swd_nums 11 25 - -# If you define trst or srst, use appropriate reset_config -# Header pin numbers: TRST - 26, SRST - 18 - -# bcm2835gpio trst_num 7 -# reset_config trst_only - -# bcm2835gpio srst_num 24 -# reset_config srst_only srst_push_pull - -# or if you have both connected, -# reset_config trst_and_srst srst_push_pull +source [find interface/raspberrypi-native.cfg] diff --git a/tcl/interface/raspberrypi5-gpiod.cfg b/tcl/interface/raspberrypi5-gpiod.cfg new file mode 100644 index 0000000000..03f3fdb6e6 --- /dev/null +++ b/tcl/interface/raspberrypi5-gpiod.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Raspberry Pi 5 used as a bitbang adapter. +# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html + +# Raspberry Pi 5 is not compatible with bcm2835gpio native GPIO driver. +# The linuxgpiod driver without configurable adapter speed runs at approximately +# 800 kHz (SWD writes) and 360 kHz (SWD reads) + +adapter driver linuxgpiod + +proc read_file { name } { + if {[catch {open $name r} fd]} { + return "" + } + set result [read $fd] + close $fd + return $result +} + +proc find_rp1_alias {} { + foreach f [glob -directory "/proc/device-tree/aliases" "gpio\[0-9\]"] { + if {[string match "*/rp1/*" [read_file $f]]} { + return $f + } + } +} + +set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy] +if {![string match {*\[performance\]*} $pcie_aspm]} { + echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz" + echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'" +} + +set GPIO_CHIP [string index [find_rp1_alias] end] +source [find interface/raspberrypi-gpio-connector.cfg] diff --git a/tcl/interface/rshim.cfg b/tcl/interface/rshim.cfg index 1d5da593e7..327212f681 100644 --- a/tcl/interface/rshim.cfg +++ b/tcl/interface/rshim.cfg @@ -5,4 +5,4 @@ # adapter driver rshim -transport select dapdirect_swd +transport select swd diff --git a/tcl/interface/spidev_example.cfg b/tcl/interface/spidev_example.cfg new file mode 100644 index 0000000000..2354c781bb --- /dev/null +++ b/tcl/interface/spidev_example.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Example config for using Linux spidev as a SWD adapter. + +adapter driver linuxspidev +adapter speed 3000 +spidev path "/dev/spidev0.0" +spidev mode 3 +spidev queue_entries 64 diff --git a/tcl/interface/stlink-dap.cfg b/tcl/interface/stlink-dap.cfg index 5c24cbdab7..009fdb7e0f 100644 --- a/tcl/interface/stlink-dap.cfg +++ b/tcl/interface/stlink-dap.cfg @@ -1,22 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# -# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit -# debugger/programmer -# -# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" -# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" -# -# SWIM transport is natively supported -# +echo "WARNING: interface/stlink-dap.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] -adapter driver st-link -st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 - -# transport select dapdirect_jtag -# transport select dapdirect_swd -# transport select swim - -# Optionally specify the serial number of usb device -# e.g. -# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/stlink-hla.cfg b/tcl/interface/stlink-hla.cfg new file mode 100644 index 0000000000..5c4adb8973 --- /dev/null +++ b/tcl/interface/stlink-hla.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# + +echo "DEPRECATED: OpenOCD support for ST-Link HLA transport will be dropped soon!" +echo "Consider updating your ST-Link firmware to a version >= V2J24 (2015)" + +adapter driver hla +hla layout stlink +hla device_desc "ST-LINK" +hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 +# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 +# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial +# number reset issues. +# eg. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg index e4906b74ed..48c5656615 100644 --- a/tcl/interface/stlink.cfg +++ b/tcl/interface/stlink.cfg @@ -4,15 +4,25 @@ # STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit # debugger/programmer # +# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" +# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" +# +# SWIM transport is natively supported +# + +if { [adapter name] == "hla" } { + # Deprecated HLA adapter driver already selected. + # Quit silently, as the ST-LINK driver already complains. + return +} + +adapter driver st-link +st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 -adapter driver hla -hla_layout stlink -hla_device_desc "ST-LINK" -hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 +# transport select jtag +# transport select swd +# transport select swim -# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 -# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 -# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial -# number reset issues. -# eg. +# Optionally specify the serial number of usb device +# e.g. # adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/ti-icdi.cfg b/tcl/interface/ti-icdi.cfg index db4e1e0a04..c13d27e8b1 100644 --- a/tcl/interface/ti-icdi.cfg +++ b/tcl/interface/ti-icdi.cfg @@ -10,8 +10,8 @@ # adapter driver hla -hla_layout ti-icdi -hla_vid_pid 0x1cbe 0x00fd +hla layout ti-icdi +hla vid_pid 0x1cbe 0x00fd # Optionally specify the serial number of TI-ICDI devices, for when using # multiple devices. Serial numbers can be obtained using lsusb -v diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg index 7350bb9a91..27a8aafd7b 100644 --- a/tcl/interface/vdebug.cfg +++ b/tcl/interface/vdebug.cfg @@ -22,12 +22,12 @@ vdebug server $_VDEBUGHOST:$_VDEBUGPORT # example config listen on all interfaces, disable tcl/telnet server bindto 0.0.0.0 -#gdb_port 3333 -#telnet_port disabled -tcl_port disabled +#gdb port 3333 +#telnet port disabled +tcl port disabled # transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw vdebug batching 1 # Polling values -vdebug polling 100 1000 +vdebug polling 100 500 diff --git a/tcl/memory.tcl b/tcl/memory.tcl index b111749954..8b93b515eb 100644 --- a/tcl/memory.tcl +++ b/tcl/memory.tcl @@ -66,10 +66,10 @@ proc iswithin { ADDRESS BASE LEN } { proc address_info { ADDRESS } { foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } { - if { info exists $WHERE } { + if { [info exists $WHERE] } { set lmt [set N_[set WHERE]] for { set region 0 } { $region < $lmt } { incr region } { - if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } { + if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } { return "$WHERE $region"; } } diff --git a/tcl/target/allwinner_h618.cfg b/tcl/target/allwinner_h618.cfg new file mode 100644 index 0000000000..98d3ace0de --- /dev/null +++ b/tcl/target/allwinner_h618.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Allwinner H618 chip. It is an updated version of the Allwinner H616. + +# Information is available on linux-sunxi.org: +# Datasheet: https://linux-sunxi.org/images/b/b9/H616_Datasheet_V1.0_cleaned.pdf +# Manual: https://linux-sunxi.org/images/2/24/H616_User_Manual_V1.0_cleaned.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME h618 +} + +if { [info exists USE_SMP] } { + set _USE_SMP $USE_SMP +} else { + set _USE_SMP 0 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +set _cores 4 +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 +adapter speed 4000 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# MEM-AP for direct access +target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 1 + +# these addresses are obtained from the ROM table via 'dap info 1' command +set _DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000} +set _CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000} + +set _smp_command "target smp" + +for { set _core 0 } { $_core < $_cores } { incr _core } { + set _CTINAME $_CHIPNAME.cti$_core + set _TARGETNAME $_CHIPNAME.cpu$_core + + cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $_CTIBASE $_core] + target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME + + set _smp_command "$_smp_command $_TARGETNAME" +} + +if {$_USE_SMP} { + eval $_smp_command +} + +# default target is cpu0 +targets $_CHIPNAME.cpu0 diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg index 437bd956df..6c3435ed74 100644 --- a/tcl/target/allwinner_v3s.cfg +++ b/tcl/target/allwinner_v3s.cfg @@ -28,7 +28,7 @@ # UART2_TX PB0 Per default disabled # UART2_RX PB1 Per default disabled # -# JTAG is enabled by default after power on on listed JTAG_* pins. So far the +# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the # boot sequence is: # Time Action # 0000ms Power ON diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 0b0bd9e88d..fd68fcd482 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -8,7 +8,7 @@ # # Configure defaults for target -# Can be overriden in board configuration file +# Can be overridden in board configuration file # if { [info exists CHIPNAME] } { diff --git a/tcl/target/at91sama5d2.cfg b/tcl/target/at91sama5d2.cfg index 65e5217e1e..30ddc92a9d 100644 --- a/tcl/target/at91sama5d2.cfg +++ b/tcl/target/at91sama5d2.cfg @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # +# SAMA5D2 devices support both JTAG and SWD transports. +# # The JTAG connection is disabled at reset, and during the ROM Code execution. # It is re-enabled when the ROM code jumps in the boot file copied from an # external Flash memory into the internalSRAM, or when the ROM code launches @@ -12,14 +14,28 @@ # - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F. # - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477 # + +source [find target/swj-dp.tcl] + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x5ba00477 + } else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x5ba02477 + } +} + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME at91sama5d2 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ - -expected-id 0x5ba00477 +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # Cortex-A5 target set _TARGETNAME $_CHIPNAME.cpu_a5 diff --git a/tcl/target/atmega32u4.cfg b/tcl/target/atmega32u4.cfg new file mode 100644 index 0000000000..9199c741e6 --- /dev/null +++ b/tcl/target/atmega32u4.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# ATmega32U4 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME avr +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4958703f +} + +adapter speed 4500 + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/bcm2711.cfg b/tcl/target/bcm2711.cfg index f8d2b3a65b..9704daf812 100644 --- a/tcl/target/bcm2711.cfg +++ b/tcl/target/bcm2711.cfg @@ -3,8 +3,8 @@ # The Broadcom BCM2711 used in Raspberry Pi 4 # No documentation was found on Broadcom website -# Partial information is available in raspberry pi website: -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/ +# Partial information is available on the Raspberry Pi website: +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2711 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/bcm2835.cfg b/tcl/target/bcm2835.cfg index 32a03666c4..645588730d 100644 --- a/tcl/target/bcm2835.cfg +++ b/tcl/target/bcm2835.cfg @@ -3,8 +3,8 @@ # This is the Broadcom chip used in the Raspberry Pi Model A, B, B+, # the Compute Module, and the Raspberry Pi Zero. -# Partial information is available in raspberry pi website: -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835 +# Partial information is available on the Raspberry Pi website: +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2835 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/bcm2836.cfg b/tcl/target/bcm2836.cfg index 04921315ed..695426e7a8 100644 --- a/tcl/target/bcm2836.cfg +++ b/tcl/target/bcm2836.cfg @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# The Broadcom chip used in the Raspberry Pi 2 Model B +# The Broadcom chip used in the Raspberry Pi 2 Model B v1.1 -# Partial information is available in raspberry pi website: -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836 +# Partial information is available on the Raspberry Pi website: +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2836 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/bcm2837.cfg b/tcl/target/bcm2837.cfg index 749de31037..d41892c431 100644 --- a/tcl/target/bcm2837.cfg +++ b/tcl/target/bcm2837.cfg @@ -3,9 +3,9 @@ # This is the Broadcom chip used in the Raspberry Pi 3, # and in later models of the Raspberry Pi 2. -# Partial information is available in raspberry pi website: -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837 -# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0 +# Partial information is available on the Raspberry Pi website: +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2837 +# https://www.raspberrypi.com/documentation/computers/processors.html#bcm2837b0 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/bl602.cfg b/tcl/target/bl602.cfg new file mode 100644 index 0000000000..d110d3e3bd --- /dev/null +++ b/tcl/target/bl602.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL602 and BL604 target +# +# https://en.bouffalolab.com/product/?type=detail&id=1 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TDO - GPIO11 +# TMS - GPIO12 +# TCK - GPIO14 +# TDI - GPIO17 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl602 +} + +set CPUTAPID 0x20000c05 + +# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP +set WORKAREAADDR 0x42014000 +set WORKAREASIZE 0xC000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information +$_TARGETNAME configure -event reset-assert { + halt + + bl602_sw_reset_hbn_wait +} diff --git a/tcl/target/bl602_common.cfg b/tcl/target/bl602_common.cfg new file mode 100644 index 0000000000..cf4bc3947c --- /dev/null +++ b/tcl/target/bl602_common.cfg @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Script for Bouffalo chips with similar architecture used in BL602 +# based on SiFive E21 core + +source [find mem_helper.tcl] + +transport select jtag + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + error "you must specify a tap id" +} + +if { [info exists BL602_CHIPNAME] } { + set _CHIPNAME $BL602_CHIPNAME +} else { + error "you must specify a chip name" +} + +if { [info exists WORKAREAADDR] } { + set _WORKAREAADDR $WORKAREAADDR +} else { + error "you must specify a work area address" +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + error "you must specify a work area size" +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_mem_access sysbus +riscv set_enable_virt2phys off + +$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 + +# Internal RC ticks on 32 MHz, so this speed should be safe to use. +adapter speed 8000 + +# Useful functions + +set dmcontrol 0x10 +set dmcontrol_dmactive [expr {1 << 0}] +set dmcontrol_ndmreset [expr {1 << 1}] +set dmcontrol_resumereq [expr {1 << 30}] +set dmcontrol_haltreq [expr {1 << 31}] + +proc bl602_restore_clock_defaults { } { + # Switch clock to internal RC32M + # In HBN_GLB, set ROOT_CLK_SEL = 0 + mmw 0x4000f030 0x0 0x00000003 + # Wait for clock switch + sleep 10 + + # GLB_REG_BCLK_DIS_FALSE + mww 0x40000ffc 0x0 + + # HCLK is RC32M, so BCLK/HCLK doesn't need divider + # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0 + mmw 0x40000000 0x0 0x00FFFF00 + # Wait for clock to stabilize + sleep 10 +} + +# By spec, ndmreset should reset whole chip. This implementation resets only few parts of the chip. +# CTRL_PWRON_RESET register in GLB core triggers full "power-on like" reset, so we use it instead +# for full software reset. +proc bl602_sw_reset { } { + # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET + mmw 0x40000018 0x0 0x00000007 + + # This Software reset method resets everything, so CPU as well. + # It does that in not much good way, resulting in Debug Module being reset as well. + # This also means, that right after CPU and Debug Module are turned on, we need to + # enable Debug Module and halt CPU if needed. Additionally, we trigger this SW reset + # through system bus access directly with DMI commands, to avoid errors printed by + # OpenOCD about unsuccessful register write. + + # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1 + riscv dmi_write 0x39 0x40000018 + riscv dmi_write 0x3c 0x7 + + # We need to wait for chip to finish reset and execute BootROM + sleep 1 + + # JTAG Debug Transport Module is reset as well, so we need to get into RUN/IDLE state + runtest 10 + + # We need to enable Debug Module and halt the CPU, so we can reset Program Counter + # and to do additional clean-ups. If reset was called without halt, resume is handled + # by reset-deassert-post event handler. + + # In Debug Module Control (dmcontrol), set dmactive to 1 and then haltreq to 1 + riscv dmi_write $::dmcontrol $::dmcontrol_dmactive + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_haltreq} ] + + # Set Program Counter to start of BootROM + set_reg {pc 0x21000000} +} + +# On BL602 and BL702, the only way to force chip stay in BootROM (until JTAG attaches) +# is by putting infinity loop into HBN RAM (which is not reset by sw reset), and then +# configure HBN registers, which will cause BootROM to jump into our code early in BootROM. +proc bl602_sw_reset_hbn_wait {} { + # Restore clocks to defaults + bl602_restore_clock_defaults + + # In HBN RAM, write infinity loop instruction + # beq zero, zero, 0 + mww 0x40010000 0x00000063 + # In HNB, set HBN_RSV0 (Status Flag) to "EHBN" (as uint32_t) + mww 0x4000f100 0x4e424845 + # In HBN, set HBN_RSV1 (WakeUp Address) to HBN RAM address + mww 0x4000f104 0x40010000 + + # Perform software reset + bl602_sw_reset + + # Clear HBN RAM, HBN_RSV0 and HBN_RSV1 + mww 0x40010000 0x00000000 + mww 0x4000f100 0x00000000 + mww 0x4000f104 0x00000000 + + # This early jump method locks up BootROM through Trust Zone Controller. + # That means any read of BootROM returns 0xDEADBEEF. + # Only way to reset it, is through JTAG Reset, thus toggling ndmreset in dmcontrol. + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_ndmreset} ] + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive} ] +} + +$_TARGETNAME configure -event reset-deassert-post { + # Resume the processor if reset was triggered without halt request + if {$halt == 0} { + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_resumereq} ] + } +} diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg new file mode 100644 index 0000000000..8caf06ebe1 --- /dev/null +++ b/tcl/target/bl702.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL702, BL704 and BL706 target +# +# https://en.bouffalolab.com/product/?type=detail&id=8 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TMS - GPIO0 +# TDI - GPIO1 +# TCK - GPIO2 +# TDO - GPIO9 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl702 +} + +set CPUTAPID 0x20000e05 + +# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP +set WORKAREAADDR 0x22014000 +set WORKAREASIZE 0xC000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information +$_TARGETNAME configure -event reset-assert { + halt + + bl602_sw_reset_hbn_wait +} diff --git a/tcl/target/bl702l.cfg b/tcl/target/bl702l.cfg new file mode 100644 index 0000000000..467dd8ce6b --- /dev/null +++ b/tcl/target/bl702l.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL702L and BL704L target +# +# https://en.bouffalolab.com/product/?type=detail&id=26 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TMS - GPIO0 +# TDI - GPIO1 +# TCK - GPIO2 +# TDO - GPIO7 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl702l +} + +set CPUTAPID 0x20000e05 + +# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken +# by L1 cache and XIP during runtime. +set WORKAREAADDR 0x42020000 +set WORKAREASIZE 0x10000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset function for more information +# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach +$_TARGETNAME configure -event reset-assert { + halt + + # Restore clocks to defaults + bl602_restore_clock_defaults + + # In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4) + # and HBN_USER_BOOT_SEL to 1 (ISP) + mww 0x4000f108 0x44000000 + + # Perform software reset + bl602_sw_reset + + # Reset HBN_RSV2 so BootROM will not force ISP mode again + mww 0x4000f108 0x00000000 +} diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index d1d3f258bc..ba0e4fe0af 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -176,7 +176,7 @@ proc setupAmbaClk {} { mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -250,7 +250,7 @@ proc setupArmClk {} { mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX diff --git a/tcl/target/cavium_cn61xx.cfg b/tcl/target/cavium_cn61xx.cfg new file mode 100644 index 0000000000..60b56a5192 --- /dev/null +++ b/tcl/target/cavium_cn61xx.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Cavium Octeon II CN61xx (PrID 0x000D9301) + +jtag newtap cpu tap0 -irlen 5 +jtag newtap cpu tap1 -irlen 5 + +target create cpu.core0 mips_mips64 -chain-position cpu.tap0 -endian big -rtos hwthread -coreid 0 +target create cpu.core1 mips_mips64 -chain-position cpu.tap1 -endian big -rtos hwthread -coreid 1 +target smp cpu.core0 cpu.core1 + +cpu.core0 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000 +cpu.core1 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000 + +targets cpu.core0 diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg index a8b0823dac..d29c636cfa 100644 --- a/tcl/target/esi32xx.cfg +++ b/tcl/target/esi32xx.cfg @@ -35,4 +35,4 @@ reset_config none # The default linker scripts provided by the eSi-RISC toolchain do not # specify attributes on memory regions, which results in incorrect # application of software breakpoints by GDB. -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg index f5ca78ac86..b30a170247 100644 --- a/tcl/target/esp32.cfg +++ b/tcl/target/esp32.cfg @@ -1,70 +1,35 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# The ESP32 only supports JTAG. -transport select jtag -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME esp32 -} +# Source the ESP common configuration file. +source [find target/esp_common.cfg] -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x120034e5 -} +# Target specific global variables +set _CHIPNAME "esp32" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 3 +set _FLASH_VOLTAGE 3.3 +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004 if { [info exists ESP32_ONLYCPU] } { set _ONLYCPU $ESP32_ONLYCPU -} else { - set _ONLYCPU 2 } if { [info exists ESP32_FLASH_VOLTAGE] } { set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE -} else { - set _FLASH_VOLTAGE 3.3 } -set _CPU0NAME cpu0 -set _CPU1NAME cpu1 -set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME -set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME - -jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID -if { $_ONLYCPU != 1 } { - jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID -} else { - jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID +proc esp32_memprot_is_enabled { } { + return 0 } -# PRO-CPU -target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0 -# APP-CPU -if { $_ONLYCPU != 1 } { - target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1 - target smp $_TARGETNAME_0 $_TARGETNAME_1 +proc esp32_soc_reset { } { + soft_reset_halt } -$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE -$_TARGETNAME_0 xtensa maskisr on -$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut -$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt } - -$_TARGETNAME_0 configure -event gdb-attach { - $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut - # necessary to auto-probe flash bank when GDB is connected - halt 1000 -} - -if { $_ONLYCPU != 1 } { - $_TARGETNAME_1 configure -event gdb-attach { - $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut - # necessary to auto-probe flash bank when GDB is connected - halt 1000 - } - $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt } -} +create_esp_target $_ESP_ARCH -gdb_breakpoint_override hard +source [find target/xtensa-core-esp32.cfg] diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg index 8c5835da60..4c1362a346 100644 --- a/tcl/target/esp32s2.cfg +++ b/tcl/target/esp32s2.cfg @@ -1,30 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# The ESP32-S2 only supports JTAG. -transport select jtag -set CPU_MAX_ADDRESS 0xFFFFFFFF -source [find bitsbytes.tcl] -source [find memory.tcl] -source [find mmr_helpers.tcl] +# Source the ESP common configuration file. +source [find target/esp_common.cfg] -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME esp32s2 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x120034e5 -} - -set _TARGETNAME $_CHIPNAME -set _CPUNAME cpu -set _TAPNAME $_CHIPNAME.$_CPUNAME - -jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID +# Target specific global variables +set _CHIPNAME "esp32s2" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3f41A004 proc esp32s2_memprot_is_enabled { } { # IRAM0, DPORT_PMS_PRO_IRAM0_0_REG @@ -46,20 +33,10 @@ proc esp32s2_memprot_is_enabled { } { return 0 } -target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME - -$_TARGETNAME configure -event gdb-attach { - # necessary to auto-probe flash bank when GDB is connected and generate proper memory map - halt 1000 - if { [esp32s2_memprot_is_enabled] } { - # 'reset halt' to disable memory protection and allow flasher to work correctly - echo "Memory protection is enabled. Reset target to disable it..." - reset halt - } +proc esp32s2_soc_reset { } { + soft_reset_halt } -xtensa maskisr on - -$_TARGETNAME configure -event reset-assert-post { soft_reset_halt } +create_esp_target $_ESP_ARCH -gdb_breakpoint_override hard +source [find target/xtensa-core-esp32s2.cfg] diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg index 967c3a2d10..12c166c463 100644 --- a/tcl/target/esp32s3.cfg +++ b/tcl/target/esp32s3.cfg @@ -1,41 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# The ESP32-S3 only supports JTAG. -transport select jtag -set CPU_MAX_ADDRESS 0xFFFFFFFF -source [find bitsbytes.tcl] -source [find memory.tcl] -source [find mmr_helpers.tcl] +# Source the ESP common configuration file. +source [find target/esp_common.cfg] -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME esp32s3 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x120034e5 -} +# Target specific global variables +set _CHIPNAME "esp32s3" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 3 +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x60007044 if { [info exists ESP32_S3_ONLYCPU] } { set _ONLYCPU $ESP32_S3_ONLYCPU -} else { - set _ONLYCPU 2 -} - -set _CPU0NAME cpu0 -set _CPU1NAME cpu1 -set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME -set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME - -jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID -if { $_ONLYCPU != 1 } { - jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID -} else { - jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID } proc esp32s3_memprot_is_enabled { } { @@ -86,41 +65,10 @@ proc esp32s3_memprot_is_enabled { } { return 0 } -# PRO-CPU -target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0 -# APP-CPU -if { $_ONLYCPU != 1 } { - target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1 - target smp $_TARGETNAME_0 $_TARGETNAME_1 +proc esp32s3_soc_reset { } { + soft_reset_halt } -$_TARGETNAME_0 xtensa maskisr on -$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut - -$_TARGETNAME_0 configure -event gdb-attach { - $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut - # necessary to auto-probe flash bank when GDB is connected and generate proper memory map - halt 1000 - if { [esp32s3_memprot_is_enabled] } { - # 'reset halt' to disable memory protection and allow flasher to work correctly - echo "Memory protection is enabled. Reset target to disable it..." - reset halt - } -} -$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt } - -if { $_ONLYCPU != 1 } { - $_TARGETNAME_1 configure -event gdb-attach { - $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut - # necessary to auto-probe flash bank when GDB is connected - halt 1000 - if { [esp32s3_memprot_is_enabled] } { - # 'reset halt' to disable memory protection and allow flasher to work correctly - echo "Memory protection is enabled. Reset target to disable it..." - reset halt - } - } - $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt } -} +create_esp_target $_ESP_ARCH -gdb_breakpoint_override hard +source [find target/xtensa-core-esp32s3.cfg] diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg new file mode 100644 index 0000000000..e9a188f9f6 --- /dev/null +++ b/tcl/target/esp_common.cfg @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# + +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +# Common ESP chips definitions + +# Espressif supports only NuttX in the upstream. +# FreeRTOS support is not upstreamed yet. +set _RTOS "hwthread" +if { [info exists ESP_RTOS] } { + set _RTOS "$ESP_RTOS" +} + +# by default current dir (when OOCD has been started) +set _SEMIHOST_BASEDIR "." +if { [info exists ESP_SEMIHOST_BASEDIR] } { + set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR +} + +proc set_esp_common_variables { } { + global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET + global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 + global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED + + # For now we support dual core at most. + if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} { + set _TARGETNAME_0 $_CHIPNAME + set _CPUNAME_0 cpu + set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0 + } else { + set _CPUNAME_0 cpu0 + set _CPUNAME_1 cpu1 + set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0 + set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1 + set _TAPNAME_0 $_TARGETNAME_0 + set _TAPNAME_1 $_TARGETNAME_1 + } + + set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable" + set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset" + set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled" +} + +proc create_esp_jtag { } { + global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU + jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID + if { $_ONLYCPU != 1 } { + jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID + } elseif [info exists _CPUNAME_1] { + jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID + } +} + +proc create_openocd_targets { } { + global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU + + target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS + if { $_ONLYCPU != 1 } { + target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS + target smp $_TARGETNAME_0 $_TARGETNAME_1 + } +} + +proc create_esp_target { ARCH } { + set_esp_common_variables + create_esp_jtag + create_openocd_targets + configure_openocd_events + + if { $ARCH == "xtensa"} { + configure_esp_xtensa_default_settings + } else { + # riscv targets are not upstreamed yet. + # they can be found at the official Espressif fork. + } +} + +#################### Set event handlers and default settings #################### + +proc configure_event_examine_end { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } + } +} + +proc configure_event_reset_assert_post { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event reset-assert-post { + global _ESP_SOC_RESET + $_ESP_SOC_RESET + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event reset-assert-post { + global _ESP_SOC_RESET + $_ESP_SOC_RESET + } + } +} + +proc configure_event_halted { } { + global _TARGETNAME_0 + + $_TARGETNAME_0 configure -event halted { + global _ESP_WDT_DISABLE + $_ESP_WDT_DISABLE + esp halted_event_handler + } +} + +proc configure_event_gdb_attach { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event gdb-attach { + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + } + # necessary to auto-probe flash bank when GDB is connected and generate proper memory map + halt 1000 + if { [$_ESP_MEMPROT_IS_ENABLED] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event gdb-attach { + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut + } + # necessary to auto-probe flash bank when GDB is connected + halt 1000 + if { [$_ESP_MEMPROT_IS_ENABLED] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } + } + } +} + +proc configure_openocd_events { } { + configure_event_examine_end + configure_event_reset_assert_post + configure_event_gdb_attach +} + +proc configure_esp_xtensa_default_settings { } { + global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME + + $_TARGETNAME_0 xtensa maskisr on + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + } + + gdb breakpoint_override hard + + if { [info exists _FLASH_VOLTAGE] } { + $_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE + } +} diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg index 0681243343..54a74e8cc5 100644 --- a/tcl/target/gd32vf103.cfg +++ b/tcl/target/gd32vf103.cfg @@ -28,6 +28,12 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME +proc default_mem_access {} { + riscv set_mem_access progbuf +} + +default_mem_access + $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash @@ -40,3 +46,74 @@ $_TARGETNAME configure -event reset-init { # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } + +# On this chip, ndmreset (the debug module bit that triggers a software reset) +# doesn't work. So for JTAG connections without an SRST, we need to trigger a +# reset manually. This is an undocumented reset sequence that's used by the +# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin: +# +# https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2 +# +$_TARGETNAME configure -event reset-assert { + set dmcontrol 0x10 + set dmcontrol_dmactive [expr {1 << 0}] + set dmcontrol_ackhavereset [expr {1 << 28}] + set dmcontrol_haltreq [expr {1 << 31}] + + global _RESETMODE + + # If hardware NRST signal is connected and configured (reset_config srst_only) + # the device has been recently reset in 'jtag arp_init-reset', therefore + # DM_DMSTATUS_ANYHAVERESET reads 1. + # The following 'halt' command checks this status bit + # and shows 'Hart 0 unexpectedly reset!' if set. + # Prevent this message by sending an acknowledge first. + set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}] + riscv dmi_write $dmcontrol $val + + # Halt the core so that we can write to memory. We do this first so + # that it doesn't clobber our dmcontrol configuration. + halt + + # Set haltreq appropriately for the type of reset we're doing. This + # replicates what the generic RISC-V reset_assert() function would + # do if we weren't overriding it. The $_RESETMODE hack sucks, but + # it's the least invasive way to determine whether we need to halt. + # + # If we didn't override the generic handler, we'd actually still have + # to do this: the default handler sets ndmreset, which prevents memory + # access even though it doesn't actually trigger a reset on this chip. + # So we'd need to unset it here, which involves a write to dmcontrol, + # Since haltreq is write-only and there's no way to leave it unchanged, + # we'd have to figure out its proper value anyway. + set val $dmcontrol_dmactive + if {$_RESETMODE ne "run"} { + set val [expr {$val | $dmcontrol_haltreq}] + } + riscv dmi_write $dmcontrol $val + + # Unlock 0xe0042008 so that the next write triggers a reset + mww 0xe004200c 0x4b5a6978 + + # We need to trigger the reset using abstract memory access, since + # progbuf access tries to read a status code out of a core register + # after the write happens, which fails when the core is in reset. + riscv set_mem_access abstract + + # Go! + mww 0xe0042008 0x1 + + # Put the memory access mode back to what it was. + default_mem_access +} + +# Capture the mode of a given reset so that we can use it later in the +# reset-assert handler. +proc init_reset { mode } { + global _RESETMODE + set _RESETMODE $mode + + if {[using_jtag]} { + jtag arp_init-reset + } +} diff --git a/tcl/target/geehy/apm32f0x.cfg b/tcl/target/geehy/apm32f0x.cfg new file mode 100644 index 0000000000..502c092751 --- /dev/null +++ b/tcl/target/geehy/apm32f0x.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Geehy APM32F0x target +# +# https://global.geehy.com/MCU +# + +# +# APM32F0x devices support SWD transport only. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME apm32f0x +} + +# Work-area is a space in RAM used for flash programming, by default use 1 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +adapter speed 1000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset. + cortex_m reset_config sysresetreq +} diff --git a/tcl/target/geehy/apm32f1x.cfg b/tcl/target/geehy/apm32f1x.cfg new file mode 100644 index 0000000000..dc42e060a6 --- /dev/null +++ b/tcl/target/geehy/apm32f1x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Geehy APM32F1x target +# +# https://global.geehy.com/MCU +# + +# +# APM32F1x devices support JTAG and SWD transport. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME apm32f1x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME + +adapter speed 1000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset. + cortex_m reset_config sysresetreq +} diff --git a/tcl/target/geehy/apm32f4x.cfg b/tcl/target/geehy/apm32f4x.cfg new file mode 100644 index 0000000000..3ed58d15b5 --- /dev/null +++ b/tcl/target/geehy/apm32f4x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Geehy APM32F4x target +# +# https://global.geehy.com/MCU +# + +# +# APM32F4x devices support JTAG and SWD transport. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME apm32f4x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } else { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if { [using_jtag] } { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +adapter speed 1000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset. + cortex_m reset_config sysresetreq +} diff --git a/tcl/target/hi3798.cfg b/tcl/target/hi3798.cfg index 4373962e44..722305dcf4 100644 --- a/tcl/target/hi3798.cfg +++ b/tcl/target/hi3798.cfg @@ -42,8 +42,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { #set _command "$_command -defer-examine" set _smp_command "$_smp_command ${_TARGETNAME}$_core" } else { - # uncomment when "hawt" rtos is merged - # set _command "$_command -rtos hawt" + set _command "$_command -rtos hwthread" set _smp_command "target smp ${_TARGETNAME}$_core" } diff --git a/tcl/target/hi6220.cfg b/tcl/target/hi6220.cfg index f5f7fc9a49..5b03899256 100644 --- a/tcl/target/hi6220.cfg +++ b/tcl/target/hi6220.cfg @@ -49,8 +49,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { set _command "$_command -defer-examine" set _smp_command "$_smp_command ${_TARGETNAME}$_core" } else { - # uncomment when "hawt" rtos is merged - # set _command "$_command -rtos hawt" + set _command "$_command -rtos hwthread" set _smp_command "target smp ${_TARGETNAME}$_core" } diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index 5509532111..e5d5706f02 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -6,7 +6,7 @@ # # Utilities for TI ICEpick-C/D used in most TI SoCs -# Details about the ICEPick are available in the the TRM for each SoC +# Details about the ICEPick are available in the TRM for each SoC # and http://processors.wiki.ti.com/index.php/ICEPICK # create "constants" diff --git a/tcl/target/imx8mp.cfg b/tcl/target/imx8mp.cfg new file mode 100644 index 0000000000..bddbcfd20e --- /dev/null +++ b/tcl/target/imx8mp.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP i.MX8M Plus SoCs +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8m +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# the DAP tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core +} + +# declare the auxiliary Cortex-M7 core on AP #4 +target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# default target is A53 core 0 +targets $_TARGETNAME.0 diff --git a/tcl/target/lsch3_common.cfg b/tcl/target/lsch3_common.cfg index f48d59b9d8..ad88b2e1b3 100644 --- a/tcl/target/lsch3_common.cfg +++ b/tcl/target/lsch3_common.cfg @@ -51,8 +51,8 @@ proc release_cpu {cpu} { } # Release the cpu; it will start executing something bogus - mem2array regs 32 $RST_BRRL 1 - mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}] + set reg [read_memory $RST_BRRL 32 1] + mww $RST_BRRL [expr {$reg | 1 << $cpu}] if {$not_halted} { resume diff --git a/tcl/target/marvell/88f37x0.cfg b/tcl/target/marvell/88f37x0.cfg index d80f4ef6fc..738d22110c 100644 --- a/tcl/target/marvell/88f37x0.cfg +++ b/tcl/target/marvell/88f37x0.cfg @@ -57,8 +57,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { set _command "$_command -defer-examine" set _smp_command "$_smp_command ${_TARGETNAME}$_core" } else { - # uncomment when "hawt" rtos is merged - # set _command "$_command -rtos hawt" + set _command "$_command -rtos hwthread" set _smp_command "target smp ${_TARGETNAME}$_core" } diff --git a/tcl/target/marvell/cn9130.cfg b/tcl/target/marvell/cn9130.cfg new file mode 100644 index 0000000000..23e472f284 --- /dev/null +++ b/tcl/target/marvell/cn9130.cfg @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family +# +# henrik.nordstorm@addiva.se, Nov 2023 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cn9130 +} + +if { [info exists MASTERTAPID] } { + set _MASTERTAPID $MASTERTAPID +} else { + set _MASTERTAPID 0x07025357 +} + +if { [info exists APTAPID] } { + set _APTAPID $APTAPID +} else { + set _APTAPID 0x4ba00477 +} + +if { [info exists SBTAPID] } { + set _SBTAPID $SBTAPID +} else { + set _SBTAPID 0x4ba00477 +} + +if { [info exists CORES] } { + set _CORES $CORES +} else { + set _CORES 4 +} + +# CTI base address should be possible to read from the CoreSight +# ROM table like how the DBG base address is when not specified. +if { [info exists CTIBASE] } { + set _CTIBASE $CTIBASE +} else { + set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +} + +# CN9130 is a multi-die chip and has a multi level hierarchical +# JTAG TAP, where all the DAPs are disabled at reset, requiring +# both configuration to enable access to the chip DAPs, and a +# vendor specific bypass IR instruction to access the slave TAPs +# via the master TAP. In addition there is a number of sample +# bits that should be ignored. +# +# The default BYPASS instruction in the master TAP bypasses the +# whole chip and not only the master TAP. And similarly on +# IDCODE the master TAP only responds with it's own ID and +# bypasses the other TAPs on the chip, while OpenOCD expects +# ID from all enabled TAPs in the chain. + +# Bootstrap with the default boundary scan oriented TAP configuration +# where the master,ap,sb TAPs are seen as one big fat TAP, which matches +# what OpenOCD expects from IDCODE and BYPASS. + +jtag newtap $_CHIPNAME bs -irlen 19 -enable -expected-id $_MASTERTAPID + +# Declare the full JTAG chain, but in disabled state during setup + +jtag newtap $_CHIPNAME sample4 -irlen 1 -disable +jtag newtap $_CHIPNAME sample3 -irlen 1 -disable +jtag newtap $_CHIPNAME sample2 -irlen 1 -disable +jtag newtap $_CHIPNAME ap.cpu -irlen 4 -disable -expected-id $_APTAPID +jtag newtap $_CHIPNAME ap -irlen 5 -disable +jtag newtap $_CHIPNAME sample1 -irlen 1 -disable +jtag newtap $_CHIPNAME sb.cpu -irlen 4 -disable -expected-id $_SBTAPID +jtag newtap $_CHIPNAME sb -irlen 5 -disable +jtag newtap $_CHIPNAME master -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID + +# Once the iniial IDCODE scan has completed switch to more detailed +# scan chain giving access to the individual chip TAPs. + +jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME" + +proc cn9130_enable_full_chain { _CHIPNAME } { + # Switch to detailed TAP declaration + jtag tapdisable $_CHIPNAME.bs + jtag tapenable $_CHIPNAME.master + jtag tapenable $_CHIPNAME.sb + jtag tapenable $_CHIPNAME.sample1 + jtag tapenable $_CHIPNAME.ap + jtag tapenable $_CHIPNAME.sample2 + jtag tapenable $_CHIPNAME.sample3 + jtag tapenable $_CHIPNAME.sample4 +} + +# AP & SB TAPs have a config register to enable/disable access to +# the auxilary DAP TAP. Default off which hides the DAP TAP from +# the scan chain. +proc cn9130_dap_config { chip tap state } { + irscan $chip.$tap 0x12 + drscan $chip.$tap 32 $state +} + +jtag configure $_CHIPNAME.bs -event tap-disable "" +jtag configure $_CHIPNAME.bs -event tap-enable "" +jtag configure $_CHIPNAME.sample4 -event tap-enable "" +jtag configure $_CHIPNAME.sample3 -event tap-enable "" +jtag configure $_CHIPNAME.sample2 -event tap-enable "" +jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0" +jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1" +jtag configure $_CHIPNAME.ap -event tap-enable "" +jtag configure $_CHIPNAME.sample1 -event tap-enable "" +jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0" +jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1" +jtag configure $_CHIPNAME.sb -event tap-enable "" +jtag configure $_CHIPNAME.master -event tap-enable "" + +dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu + +# Main bus +target create $_CHIPNAME.ap.axi mem_ap \ + -dap $_CHIPNAME.ap.dap \ + -ap-num 0 + +# Periperials bus +target create $_CHIPNAME.ap.apb mem_ap \ + -dap $_CHIPNAME.ap.dap \ + -ap-num 1 + +# MSS bus +target create $_CHIPNAME.ap.ahb mem_ap \ + -dap $_CHIPNAME.ap.dap \ + -ap-num 2 + +# AP A72 CPU cores +set _smp_command "" +for { set _core 0 } { $_core < $_CORES } { incr _core 1 } { + cti create $_CHIPNAME.ap.cti.$_core \ + -dap $_CHIPNAME.ap.dap \ + -baseaddr [ lindex $_CTIBASE $_core ] \ + -ap-num 1 + + if { $_core == 0 } { + target create $_CHIPNAME.ap.a72.$_core aarch64 \ + -dap $_CHIPNAME.ap.dap \ + -ap-num 1 \ + -cti $_CHIPNAME.ap.cti.$_core \ + -coreid $_core \ + -rtos hwthread + set _smp_command "target smp $_CHIPNAME.ap.a72.$_core" + } else { + # Defer non-boot cores. Held hard in reset until + # SMP is activated. + target create $_CHIPNAME.ap.a72.$_core aarch64 \ + -dap $_CHIPNAME.ap.dap \ + -ap-num 1 \ + -cti $_CHIPNAME.ap.cti.$_core \ + -coreid $_core \ + -defer-examine + set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core" + } + +} + +# Set up the A72 cluster as SMP +# Note: Only the boot core is active by default. The other core DAPs can +# be enabled by arp_examine after they have been released from hard reset. +eval $_smp_command + +# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded. +target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine + +# Why is this needed? reset fails with "Debug regions are unpowered" otherwise +$_CHIPNAME.ap.axi configure -event examine-start "dap init" + +# Automate enabling the AP A72 DAP once the full scan chain is enabled +proc cn9130_ap_setup { _CHIPNAME } { + jtag tapenable $_CHIPNAME.ap.cpu + targets $_CHIPNAME.ap.a72.0 +} +jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME" diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg index 9f0f4929d3..f3a9f84c88 100644 --- a/tcl/target/max32620.cfg +++ b/tcl/target/max32620.cfg @@ -16,8 +16,10 @@ if {[using_jtag]} { swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version } +dap create max32620.dap -chain-position max32620.cpu + # target configuration -target create max32620.cpu cortex_m -chain-position max32620.cpu +target create max32620.cpu cortex_m -dap max32620.dap max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options] diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg index 35e1c3bbd1..90eb392668 100644 --- a/tcl/target/max32625.cfg +++ b/tcl/target/max32625.cfg @@ -16,8 +16,10 @@ if {[using_jtag]} { swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version } +dap create max32625.dap -chain-position max32625.cpu + # target configuration -target create max32625.cpu cortex_m -chain-position max32625.cpu +target create max32625.cpu cortex_m -dap max32625.dap max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options] diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg index 52a5a770e2..852e04af1e 100644 --- a/tcl/target/max3263x.cfg +++ b/tcl/target/max3263x.cfg @@ -16,8 +16,10 @@ if {[using_jtag]} { swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version } +dap create max3263x.dap -chain-position max3263x.cpu + # target configuration -target create max3263x.cpu cortex_m -chain-position max3263x.cpu +target create max3263x.cpu cortex_m -dap max3263x.dap max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options] diff --git a/tcl/target/nds32v2.cfg b/tcl/target/nds32v2.cfg deleted file mode 100644 index 07814b7f34..0000000000 --- a/tcl/target/nds32v2.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v2 -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/nds32v3.cfg b/tcl/target/nds32v3.cfg deleted file mode 100644 index 0fd136910f..0000000000 --- a/tcl/target/nds32v3.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v3 -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/nds32v3m.cfg b/tcl/target/nds32v3m.cfg deleted file mode 100644 index 29a247805c..0000000000 --- a/tcl/target/nds32v3m.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v3m -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/netl_xlp304.cfg b/tcl/target/netl_xlp304.cfg new file mode 100644 index 0000000000..27c30a0d27 --- /dev/null +++ b/tcl/target/netl_xlp304.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target: XLP304 processor by NetLogic Microsystems +# + +set XLP_NT 4 +source [find target/netl_xlp3xx.cfg] diff --git a/tcl/target/netl_xlp308.cfg b/tcl/target/netl_xlp308.cfg new file mode 100644 index 0000000000..c3ba11e781 --- /dev/null +++ b/tcl/target/netl_xlp308.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target: XLP308 processor by NetLogic Microsystems +# + +set XLP_NT 8 +source [find target/netl_xlp3xx.cfg] diff --git a/tcl/target/netl_xlp316.cfg b/tcl/target/netl_xlp316.cfg new file mode 100644 index 0000000000..961b67f180 --- /dev/null +++ b/tcl/target/netl_xlp316.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target: XLP316 processor by NetLogic Microsystems +# + +set XLP_NT 16 +source [find target/netl_xlp3xx.cfg] diff --git a/tcl/target/netl_xlp3xx.cfg b/tcl/target/netl_xlp3xx.cfg new file mode 100644 index 0000000000..2366503cb6 --- /dev/null +++ b/tcl/target/netl_xlp3xx.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target: XLP 300-series processors by NetLogic Microsystems +# +# See http://www.broadcom.com/products/Processors/Enterprise/XLP300-Series +# +# Use xlp304.cfg, xlp308.cfg, xlp316.cfg for particular processor model. +# + +transport select jtag + +global XLP_NT + +for {set i $XLP_NT} {$i > 0} {incr i -1} { + jtag newtap xlp cpu_$i -irlen 5 -disable + if {$i != 1} { + jtag configure xlp.cpu_$i -event tap-enable {} + } +} +jtag newtap xlp jrc -irlen 16 -expected-id 0x00011449 + +jtag configure xlp.cpu_1 -event tap-enable { + global XLP_NT + irscan xlp.jrc 0xe0 + drscan xlp.jrc 1 1 + for {set i $XLP_NT} {$i > 1} {incr i -1} { + jtag tapenable xlp.cpu_$i + } +} + +proc chipreset {} { + irscan xlp.jrc 0xab + drscan xlp.jrc 1 1 + drscan xlp.jrc 1 0 +} + +jtag configure xlp.jrc -event setup "jtag tapenable xlp.cpu_1" + +target create xlp.cpu_1 mips_mips64 -endian big -chain-position xlp.cpu_1 diff --git a/tcl/target/ngultra.cfg b/tcl/target/ngultra.cfg index 956fdbb5ca..9f9814fd75 100644 --- a/tcl/target/ngultra.cfg +++ b/tcl/target/ngultra.cfg @@ -36,12 +36,11 @@ dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu for { set _core 0 } { $_core < $_cores } { incr _core } { cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \ -baseaddr [lindex $CTIBASE $_core] -# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet). if { $_core == 0} { - target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \ -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core } else { - target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \ -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine } } diff --git a/tcl/target/nordic/common.cfg b/tcl/target/nordic/common.cfg new file mode 100644 index 0000000000..2ae5011e4e --- /dev/null +++ b/tcl/target/nordic/common.cfg @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling +# + +if { [using_hla] } { + echo "" + echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock." + echo "A high level adapter (like a ST-Link) you are currently using cannot access" + echo "the CTRL-AP so 'nrfxx_recover' command will not work." + echo "Do not enable UICR APPROTECT." + echo "" +} else { + + # Test if debug/MEM-AP is locked by UICR APPROTECT + proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } { + set target [target current] + set dap [$target cget -dap] + set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}] + if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} { + echo "" + echo "****** WARNING ******" + echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)." + echo "Debug access is denied." + echo "Use 'nrfxx_recover' to erase and unlock the device." + echo "" + poll off + return 1 + } + return 0 + } + + # Mass erase and unlock the device using proprietary nRF CTRL-AP + proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg $ctrl_ap_num 0xfc] + if {$IDR != 0x12880000} { + echo "Error: Cannot access nRF CTRL-AP!" + return + } + + poll off + + # Reset and trigger ERASEALL task + $dap apreg $ctrl_ap_num 4 0 + $dap apreg $ctrl_ap_num 4 1 + + for {set i 0} {1} {incr i} { + set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8] + if {$ERASEALLSTATUS == 0} { + echo "\[$target\] device has been successfully erased and unlocked." + break + } + if {$i == 0} { + echo "Waiting for chip erase..." + } + if {$i >= 150} { + echo "Error: \[$target\] recovery failed." + break + } + sleep 100 + } + + # Assert reset + $dap apreg $ctrl_ap_num 0 1 + + # Deassert reset + $dap apreg $ctrl_ap_num 0 0 + + # Reset ERASEALL task + $dap apreg $ctrl_ap_num 4 0 + + if { $is_cpunet } { + reset init + } else { + sleep 100 + $target arp_examine + poll on + } + } + + lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover +} diff --git a/tcl/target/nrf51.cfg b/tcl/target/nordic/nrf51.cfg similarity index 88% rename from tcl/target/nrf51.cfg rename to tcl/target/nordic/nrf51.cfg index 48c2715d10..3781eccb50 100644 --- a/tcl/target/nrf51.cfg +++ b/tcl/target/nordic/nrf51.cfg @@ -45,13 +45,11 @@ if {![using_hla]} { cortex_m reset_config sysresetreq } -flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME -flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME +flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME -# # The chip should start up from internal 16Mhz RC, so setting adapter # clock to 1Mhz should be OK -# adapter speed 1000 proc enable_all_ram {} { @@ -60,4 +58,4 @@ proc enable_all_ram {} { # resetting we enable all banks via the RAMON register mww 0x40000524 0xF } -$_TARGETNAME configure -event reset-end { enable_all_ram } +$_TARGETNAME configure -event reset-init { enable_all_ram } diff --git a/tcl/target/nrf52.cfg b/tcl/target/nordic/nrf52.cfg similarity index 61% rename from tcl/target/nrf52.cfg rename to tcl/target/nordic/nrf52.cfg index 2539be049d..0703b18862 100644 --- a/tcl/target/nrf52.cfg +++ b/tcl/target/nordic/nrf52.cfg @@ -5,6 +5,7 @@ # source [find target/swj-dp.tcl] +source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -116,3 +117,68 @@ proc nrf52_recover {} { } add_help_text nrf52_recover "Mass erase and unlock nRF52 device" + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} { + targets $_targetname + + # Read FICR.INFO.PART + set PART [mrw 0x10000100] + + switch $PART { + 0x52840 - + 0x52833 - + 0x52832 { + # Configuration values for all supported trace port speeds, see + # TRACECONFIG.TRACEPORTSPEED + set trace_port_speeds { + 32000000 0 + 16000000 1 + 8000000 2 + 4000000 3 + } + + # Note that trace port clock stands for what is referred to as + # TRACECLKIN in the Arm CoreSight documentation. + set trace_port_clock [$_chipname.tpiu cget -traceclk] + + if { ![dict exists $trace_port_speeds $trace_port_clock] } { + error "Trace clock speed is not supported" + } + + # Set TRACECONFIG.TRACEPORTSPEED + mmw 0x4000055C [dict get $trace_port_speeds $trace_port_clock] 0x3 + + if { [$_chipname.tpiu cget -protocol] eq "sync" } { + if { [$_chipname.tpiu cget -port-width] != 4 } { + error "Device only supports 4-bit sync traces" + } + + # Set TRACECONFIG.TRACEMUX to enable synchronous trace + mmw 0x4000055C 0x00020000 0x00010000 + $_targetname configure -event reset-end { + mmw 0x4000055C 0x00020000 0x00010000 + } + } else { + # Set TRACECONFIG.TRACEMUX to enable SWO + mmw 0x4000055C 0x00010000 0x00020000 + $_targetname configure -event reset-end { + mmw 0x4000055C 0x00010000 0x00020000 + } + } + } + 0x52820 - + 0x52811 - + 0x52810 - + 0x52805 { + error "Device does not support TPIU" + } + default { + error "Unknown device, cannot configure TPIU" + } + } +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME" diff --git a/tcl/target/nordic/nrf53.cfg b/tcl/target/nordic/nrf53.cfg new file mode 100644 index 0000000000..0dcfd55eca --- /dev/null +++ b/tcl/target/nordic/nrf53.cfg @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf53 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +# Configurable instance ID resides in application UICR TINSTANCE +if { [info exists SWD_INSTANCE_ID] } { + set _SWD_INSTANCE_ID $SWD_INSTANCE_ID +} else { + set _SWD_INSTANCE_ID 0 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME_APP $_CHIPNAME.cpuapp +target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# The network core is not accessible over HLA +if { ![using_hla] } { + set _TARGETNAME_NET $_CHIPNAME.cpunet + target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine + + targets $_TARGETNAME_APP + + $_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 +} + +# Keep adapter speed less or equal 2000 kHz or flash programming fails! +adapter speed 1000 + +source [find target/nordic/common.cfg] + +flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP +flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP + +if { ![using_hla] } { + + flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET + flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET + + # System reset sets NETWORK.FORCEOFF which keeps the network core in reset + # Don't touch network core during reset + $_TARGETNAME_NET configure -event reset-assert {} + # and start it after application core reset is finished to make all flash accessible + $_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME" + + $_TARGETNAME_APP cortex_m reset_config sysresetreq + $_TARGETNAME_NET cortex_m reset_config sysresetreq + + $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 } + $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 } + + $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME" + + proc _nrf53_cpunet_gdb_attach { _CHIPNAME } { + set _TARGETNAME_APP $_CHIPNAME.cpuapp + set _TARGETNAME_NET $_CHIPNAME.cpunet + set RESET_NETWORK_FORCEOFF 0x50005614 + + set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1] + if { $is_off } { + nrf53_cpunet_release $_CHIPNAME + $_TARGETNAME_NET arp_poll + $_TARGETNAME_NET arp_waitstate halted 100 + } else { + if { ![$_TARGETNAME_NET was_examined] } { + $_TARGETNAME_NET arp_examine + $_TARGETNAME_NET arp_poll + } + set s [$_TARGETNAME_NET curstate] + if { ![string compare $s "halted"] } { + halt + } + } + } + lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach + + # Release the network core + proc nrf53_cpunet_release { {_CHIPNAME nrf53} } { + set _TARGETNAME_APP $_CHIPNAME.cpuapp + set _TARGETNAME_NET $_CHIPNAME.cpunet + set RESET_NETWORK_FORCEOFF 0x50005614 + set RESET_NETWORK_WORKAROUND 0x50005618 + set CORTEX_M_DCB_DEMCR 0xE000EDFC + + $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1 + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0 + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1 + set err [catch {$_TARGETNAME_NET arp_examine}] + if { $err } { + if { ![_nrf_check_ap_lock 3 3] } { + echo "Error: \[$_TARGETNAME_NET\] examination failed" + } + return + } + # set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET + $_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501 + # Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset + # following cortex_m_endreset_event() restores the original DEMCR value + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0 + $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0 + } + + # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3) + proc nrf53_cpuapp_recover {} { + _nrf_ctrl_ap_recover 2 + } + add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU" + + proc nrf53_recover {} { + _nrf_ctrl_ap_recover 3 1 + } + add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53" +} diff --git a/tcl/target/nordic/nrf54l.cfg b/tcl/target/nordic/nrf54l.cfg new file mode 100644 index 0000000000..3e14055f14 --- /dev/null +++ b/tcl/target/nordic/nrf54l.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF54L series +# +# Arm Cortex-M33 processor with RISC-V coprocessor +# +# The device uses resistive RAM (RRAM) as non-volatile memory. +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf54l +} + +# Work-area is a space in RAM used for flash programming, by default use 16 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +# Multidrop instance ID should be configurable by FW in TAD TINSTANCE register. +# Writes to the register are ignored due to a silicon erratum. +if { [info exists SWD_INSTANCE_ID] } { + set _SWD_INSTANCE_ID $SWD_INSTANCE_ID +} else { + set _SWD_INSTANCE_ID 0 +} + +transport select swd + +swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x001c0289 -instance-id $_SWD_INSTANCE_ID +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Create target for the AUX access port (AUX-AP). +target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1 + +# AUX-AP is accessible only if CSW Prot[0] bit (Data Access) is set +$_CHIPNAME.dap apsel 1 +$_CHIPNAME.dap apcsw 0x01000000 0x01000000 + +adapter speed 1000 + +# Use main processor as default target. +targets $_TARGETNAME + +if {![using_hla]} { + $_TARGETNAME cortex_m reset_config sysresetreq +} diff --git a/tcl/target/nordic/nrf91.cfg b/tcl/target/nordic/nrf91.cfg new file mode 100644 index 0000000000..64ed864e75 --- /dev/null +++ b/tcl/target/nordic/nrf91.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF91 series: ARM Cortex-M33, SWD only +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf91 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +# Contrary to the product specification at least nRF9161 supports multidrop SWD. +# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus. +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0 +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# Keep adapter speed less or equal 2000 kHz or flash programming fails! +adapter speed 1000 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +source [find target/nordic/common.cfg] + +flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME + +if { ![using_hla] } { + $_TARGETNAME cortex_m reset_config sysresetreq + + $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 } +} + +# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4) +proc nrf91_recover {} { + _nrf_ctrl_ap_recover 4 +} +add_help_text nrf91_recover "Mass erase and unlock nRF91 device" diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg index 1a21e1f7f5..84bb0b7a53 100644 --- a/tcl/target/npcx.cfg +++ b/tcl/target/npcx.cfg @@ -9,7 +9,7 @@ source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME NPCX_M4 + set _CHIPNAME npcx } # SWD DAP ID of Nuvoton NPCX Cortex-M4. @@ -27,6 +27,12 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } +if { [info exists FIUNAME]} { + set _FIUNAME $FIUNAME +} else { + set _FIUNAME npcx.fiu +} + # Debug Adapter Target Settings swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu @@ -48,4 +54,4 @@ cortex_m reset_config sysresetreq # flash configuration set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME diff --git a/tcl/target/numicro_m4.cfg b/tcl/target/numicro_m4.cfg new file mode 100644 index 0000000000..1302515d34 --- /dev/null +++ b/tcl/target/numicro_m4.cfg @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Nuvoton MuMicro Cortex-M4 Series + +source [find target/swj-dp.tcl] + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NuMicro +} + +# SWD DP-ID Nuvoton NuMicro Cortex-M4 has SWD Transport only. +if { [info exists CPUDAPID] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x2BA01477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#> +#set _FLASHNAME $_CHIPNAME.flash +#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash_aprom +flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_data +flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_ldrom +flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_config +flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME + +# set default SWCLK frequency +adapter speed 1000 + +# set default srst setting "none" +reset_config none + +# HLA doesn't have cortex_m commands +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index a448550f67..4bc7fe1bf7 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { } $_CHIPNAME.m31 configure -event reset-assert { } # Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index bbc824b2af..85ba96c51f 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { } $_CHIPNAME.m31 configure -event reset-assert { } # Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg index 2d670b98a3..78c456d5c0 100644 --- a/tcl/target/omapl138.cfg +++ b/tcl/target/omapl138.cfg @@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable etm config $_TARGETNAME 16 normal full etb etb config $_TARGETNAME $_CHIPNAME.etb -gdb_breakpoint_override hard +gdb breakpoint_override hard arm7_9 dbgrq enable diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg index d69515cdf7..52b04f5694 100644 --- a/tcl/target/psoc6.cfg +++ b/tcl/target/psoc6.cfg @@ -113,7 +113,7 @@ proc psoc6_deassert_post { target } { } if { $_ENABLE_CM0 } { - target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0 @@ -128,7 +128,7 @@ if { $_ENABLE_CM0 } { } if { $_ENABLE_CM4 } { - target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4 diff --git a/tcl/target/qn908x.cfg b/tcl/target/qn908x.cfg new file mode 100644 index 0000000000..ac3e06b69c --- /dev/null +++ b/tcl/target/qn908x.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP QN908x Cortex-M4F with 128 KiB SRAM + +source [find target/swj-dp.tcl] + +set CHIPNAME qn908x +set CHIPSERIES qn9080 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x20000 +} + +# SWD IDCODE (Cortex M4). +set CPUTAPID 0x2ba01477 + +swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID +dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu + +set TARGETNAME $CHIPNAME.cpu +target create $TARGETNAME cortex_m -dap $CHIPNAME.dap + +# SRAM is mapped at 0x04000000. +$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE + +# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum] +# The base must be set as 0x01000000, and the size parameter is unused. +set FLASHNAME $CHIPNAME.flash +flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum + +# We write directly to flash memory over this adapter interface. For debugging +# this could in theory be faster (the Core clock on reset is normally at 32MHz), +# but for flashing 1MHz is more reliable. +adapter speed 1000 + +# Delay on reset line. +adapter srst delay 200 + +cortex_m reset_config sysresetreq diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg index 3e449832f7..f6bc5e4c8f 100644 --- a/tcl/target/renesas_rcar_gen3.cfg +++ b/tcl/target/renesas_rcar_gen3.cfg @@ -90,6 +90,18 @@ switch $_soc { set _num_cr52 1 set _boot_core CA76 } + V4H { + set _CHIPNAME r8a779g0 + set _num_ca76 4 + set _num_cr52 3 + set _boot_core CR52 + } + V4M { + set _CHIPNAME r8a779h0 + set _num_ca76 4 + set _num_cr52 3 + set _boot_core CR52 + } default { error "'$_soc' is invalid!" } @@ -126,8 +138,8 @@ set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} -set CR52_DBGBASE 0x80c10000 -set CR52_CTIBASE 0x80c20000 +set CR52_DBGBASE {0x80C10000 0x80D10000 0x80E10000} +set CR52_CTIBASE {0x80C20000 0x80D20000 0x80E20000} set CR7_DBGBASE 0x80910000 set CR7_CTIBASE 0x80918000 @@ -156,41 +168,50 @@ proc setup_a5x {core_name dbgbase ctibase num boot} { } } -proc setup_cr7 {core_name dbgbase ctibase num boot} { +proc setup_crx {core_name dbgbase ctibase num boot} { global _CHIPNAME global _DAPNAME + global smp_targets + global _targets for { set _core 0 } { $_core < $num } { incr _core } { - set _TARGETNAME $_CHIPNAME.$core_name + set _TARGETNAME $_CHIPNAME.$core_name.$_core set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase - set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \ - -ap-num 1 -dbgbase $dbgbase" - if { $boot == 1 } { + cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr [lindex $ctibase $_core] + if { $core_name == "r52" } { + set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \ + -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME" + } else { + set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \ + -ap-num 1 -dbgbase [lindex $dbgbase $_core]" + } + if { $_core == 0 && $boot == 1 } { set _targets "$_TARGETNAME" } else { set _command "$_command -defer-examine" } + set smp_targets "$smp_targets $_TARGETNAME" eval $_command + $_TARGETNAME configure -event examine-end { halt } } } # Organize target list based on the boot core if { [string equal $_boot_core CA76] } { setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1 - setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0 + setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0 } elseif { [string equal $_boot_core CA57] } { setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 - setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 } elseif { [string equal $_boot_core CA53] } { setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 - setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 } elseif { [string equal $_boot_core CR52] } { - setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1 + setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1 setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0 } else { - setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 1 + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 1 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 } diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz.cfg similarity index 70% rename from tcl/target/renesas_rz_g2.cfg rename to tcl/target/renesas_rz.cfg index a3d5f48fbc..a0489de3dd 100644 --- a/tcl/target/renesas_rz_g2.cfg +++ b/tcl/target/renesas_rz.cfg @@ -1,23 +1,25 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# Renesas RZ/G2 SOCs +# Renesas RZ SOCs # - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7 # and Cortex-M33 for each SOC -# - Each SOC can boot through the Cortex-A5x cores +# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33 -# Supported RZ/G2 SOCs and their cores: +# Supported RZ SOCs and their cores: # RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 # RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 # RZ/G2N: Cortex-A57 x2, Cortex-R7 # RZ/G2E: Cortex-A53 x2, Cortex-R7 # RZ/G2L: Cortex-A55 x2, Cortex-M33 +# RZ/V2L: Cortex-A55 x2, Cortex-M33 # RZ/G2LC: Cortex-A55 x2, Cortex-M33 # RZ/G2UL: Cortex-A55 x1, Cortex-M33 +# RZ/G3S: Cortex-A55 x1, Cortex-M33 x2 # Usage: # There are 2 configuration options: # SOC: Selects the supported SOC. (Default 'G2L') -# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55' +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33 transport select jtag reset_config trst_and_srst srst_gates_jtag @@ -77,6 +79,13 @@ switch $_soc { set _boot_core CA55 set _ap_num 0 } + V2L { + set _CHIPNAME r9a07g054l + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } G2LC { set _CHIPNAME r9a07g044c set _num_ca55 2 @@ -91,6 +100,13 @@ switch $_soc { set _boot_core CA55 set _ap_num 0 } + G3S { + set _CHIPNAME r9a08g045s + set _num_ca55 1 + set _num_cm33 2 + set _boot_core CA55 + set _ap_num 0 + } default { error "'$_soc' is invalid!" } @@ -112,16 +128,16 @@ if { [info exists DAP_TAPID] } { set _DAP_TAPID 0x6ba00477 } -echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \ - $_num_cm33 CM33(s)" +echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \ + $_num_cr7 CR7(s), $_num_cm33 CM33(s)" echo "\tBoot Core - $_boot_core\n" set _DAPNAME $_CHIPNAME.dap # TAP and DAP -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \ - -ignore-version +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID -ignore-version dap create $_DAPNAME -chain-position $_CHIPNAME.cpu echo "$_CHIPNAME.cpu" @@ -133,8 +149,8 @@ set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} set CR7_DBGBASE 0x80910000 set CR7_CTIBASE 0x80918000 -set CM33_DBGBASE 0xE000E000 -set CM33_CTIBASE 0xE0042000 +set CM33_DBGBASE {0xE000E000 0xE010E000} +set CM33_CTIBASE {0xE0042000 0xE0142000} set smp_targets "" @@ -145,7 +161,8 @@ proc setup_a5x {core_name dbgbase ctibase num boot} { cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \ -baseaddr [lindex $ctibase $_core] target create $_TARGETNAME aarch64 -dap $::_DAPNAME \ - -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME + -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \ + -cti $_CTINAME if { $_core > 0 || $boot == 0 } { $_TARGETNAME configure -defer-examine } @@ -160,13 +177,29 @@ proc setup_cr7 {dbgbase ctibase} { target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \ -ap-num 1 -dbgbase $dbgbase -defer-examine } - -proc setup_cm33 {dbgbase ctibase} { - set _TARGETNAME $::_CHIPNAME.m33 - set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase - target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ - -ap-num 2 -dbgbase $dbgbase -defer-examine +proc setup_cm33 {dbgbase ctibase num boot} { + if { $::_soc == "G2L" || $::_soc == "V2L" \ + || $::_soc == "G2LC" || $::_soc == "G2UL" } { + set _ap_num 2 + } elseif { $::_soc == "G3S" } { + set _ap_num 3 + } + for { set _core 0 } { $_core < $num } { incr _core } { + if { $num <= 1 } { + set _TARGETNAME $::_CHIPNAME.m33 + } else { + set _TARGETNAME $::_CHIPNAME.m33.$_core + } + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \ + -baseaddr [lindex $ctibase $_core] + target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ + -ap-num $_ap_num -dbgbase [lindex $dbgbase $_core] + if { $boot == 0 } { + $_TARGETNAME configure -defer-examine + } + incr $_ap_num + } } # Organize target list based on the boot core @@ -180,12 +213,17 @@ if { $_boot_core == "CA57" } { setup_cr7 $CR7_DBGBASE $CR7_CTIBASE } elseif { $_boot_core == "CA55" } { setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1 - setup_cm33 $CM33_DBGBASE $CM33_CTIBASE + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0 +} elseif { $_boot_core == "CM33" } { + setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0 + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1 } + echo "SMP targets:$smp_targets" eval "target smp $smp_targets" -if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } { +if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \ +|| $_soc == "G2UL" || $_soc == "G3S"} { target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 } diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg deleted file mode 100644 index 8c3533bfb1..0000000000 --- a/tcl/target/rp2040-core0.cfg +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -transport select swd - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME rp2040 -} - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x01002927 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE - -set _FLASHNAME $_CHIPNAME.flash -set _FLASHSIZE 0x200000 -set _FLASHBASE 0x10000000 -flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME - -# srst does not exist; use SYSRESETREQ to perform a soft reset -cortex_m reset_config sysresetreq diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg new file mode 100644 index 0000000000..da88a3125b --- /dev/null +++ b/tcl/target/rp2040.cfg @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# RP2040 is a microcontroller with dual Cortex-M0+ core. +# https://www.raspberrypi.com/documentation/microcontrollers/silicon.html#rp2040 + +# The device requires multidrop SWD for debug. +transport select swd + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rp2040 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# Nonzero FLASHSIZE supresses QSPI flash size detection +if { [info exists FLASHSIZE] } { + set _FLASHSIZE $FLASHSIZE +} else { + # Detect QSPI flash size based on flash ID or SFDP + set _FLASHSIZE 0 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x01002927 +} + +# Set to '1' to start rescue mode +if { [info exists RESCUE] } { + set _RESCUE $RESCUE +} else { + set _RESCUE 0 +} + +# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread +# handling of both cores, anything else for isolated debugging of both cores +if { [info exists USE_CORE] } { + set _USE_CORE $USE_CORE +} else { + set _USE_CORE SMP +} +set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }] + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the +# PSM (power on state machine) of the RP2040 with a flag set in the +# VREG_AND_POR_CHIP_RESET register. Once the reset is released +# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag, +# and halt. Allowing the user to load some fresh code, rather than loading +# the potentially broken code stored in flash +if { $_RESCUE } { + dap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack + init + + # Clear DBGPWRUPREQ + $_CHIPNAME.rescue_dap dpreg 0x4 0x00000000 + + # Verifying CTRL/STAT is 0 + set _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4] + if {[expr {$_CTRLSTAT & 0xf0000000}]} { + echo "Rescue failed, DP CTRL/STAT readback $_CTRLSTAT" + } else { + echo "Now restart OpenOCD without RESCUE flag and load code to RP2040" + } + shutdown +} + +# core 0 +if { $_USE_CORE != 1 } { + dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0 + set _TARGETNAME_0 $_CHIPNAME.core0 + target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0 + # srst does not exist; use SYSRESETREQ to perform a soft reset + $_TARGETNAME_0 cortex_m reset_config sysresetreq + + # After a rescue reset and fi BOOTSEL is halted connect the flash to enable + # reads from the XIP cached mapping area + $_TARGETNAME_0 configure -event reset-init { rp2xxx rom_api_call 0 CX } +} + +# core 1 +if { $_USE_CORE != 0 } { + dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1 + set _TARGETNAME_1 $_CHIPNAME.core1 + target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1 + $_TARGETNAME_1 cortex_m reset_config sysresetreq +} + +if {[string compare $_USE_CORE SMP] == 0} { + $_TARGETNAME_0 configure -rtos hwthread + $_TARGETNAME_1 configure -rtos hwthread + target smp $_TARGETNAME_0 $_TARGETNAME_1 +} + +if { $_USE_CORE == 1 } { + set _FLASH_TARGET $_TARGETNAME_1 +} else { + set _FLASH_TARGET $_TARGETNAME_0 +} +# QSPI flash size detection during gdb connect requires to back-up RAM +set _WKA_BACKUP [expr { $_FLASHSIZE == 0 }] +$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup $_WKA_BACKUP +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME rp2xxx 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET + +if { $_BOTH_CORES } { + # Alias to ensure gdb connecting to core 1 gets the correct memory map + flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME + + # Select core 0 + targets $_TARGETNAME_0 +} diff --git a/tcl/target/rp2350.cfg b/tcl/target/rp2350.cfg new file mode 100644 index 0000000000..96bb9298fb --- /dev/null +++ b/tcl/target/rp2350.cfg @@ -0,0 +1,234 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# RP2350 is a microcontroller with dual Cortex-M33 cores or dual Hazard3 RISC-V cores. +# https://www.raspberrypi.com/documentation/microcontrollers/silicon.html#rp2350 + +transport select swd + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rp2350 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# Nonzero FLASHSIZE supresses QSPI flash size detection +if { [info exists FLASHSIZE] } { + set _FLASHSIZE $FLASHSIZE +} else { + # Detect QSPI flash size based on flash ID or SFDP + set _FLASHSIZE 0 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00040927 +} + +# Set to '1' to start rescue mode +if { [info exists RESCUE] } { + set _RESCUE $RESCUE +} else { + set _RESCUE 0 +} + +# Set to 'cm0' or 'cm1' for Cortex-M33 single core configuration +# To keep compatibility with RP2040 aliases '0' and '1' are provided for Cortex-M33 cores +# Use 'rv0' or 'rv1' for RISC-V single core configuration +# List more for a multicore configuration +if { [info exists USE_CORE] } { + set _USE_CORE $USE_CORE +} else { + # defaults to both Cortex-M33 cores + set _USE_CORE { cm0 cm1 } +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -adiv6 -chain-position $_CHIPNAME.cpu -dp-id 0x0040927 -instance-id 0 +} else { + dap create $_CHIPNAME.dap -adiv6 -chain-position $_CHIPNAME.cpu +} + +# Cortex-M33 core 0 +if { [lsearch $_USE_CORE cm0] >= 0 || [lsearch $_USE_CORE 0] >= 0 } { + set _TARGETNAME_CM0 $_CHIPNAME.cm0 + set _TARGETNAME_0 $_TARGETNAME_CM0 +} + +# RISC-V core 0 +if { [lsearch $_USE_CORE rv0] >= 0 } { + set _TARGETNAME_RV0 $_CHIPNAME.rv0 + if { ![info exists _TARGETNAME_0] } { + set _TARGETNAME_0 $_TARGETNAME_RV0 + } +} + +# Cortex-M33 core 1 +if { [lsearch $_USE_CORE cm1] >= 0 || [lsearch $_USE_CORE 1] >= 0 } { + set _TARGETNAME_CM1 $_CHIPNAME.cm1 + set _TARGETNAME_1 $_TARGETNAME_CM1 +} + +# RISC-V core 1 +if { [lsearch $_USE_CORE rv1] >= 0 } { + set _TARGETNAME_RV1 $_CHIPNAME.rv1 + if { ![info exists _TARGETNAME_1] } { + set _TARGETNAME_1 $_TARGETNAME_RV1 + } +} + + +if { [info exists _TARGETNAME_CM0] } { + target create $_TARGETNAME_CM0 cortex_m -dap $_CHIPNAME.dap -ap-num 0x2000 + # srst does not exist; use SYSRESETREQ to perform a soft reset + $_TARGETNAME_CM0 cortex_m reset_config sysresetreq + + # After a rescue reset the cache requires invalidate to allow SPI flash + # reads from the XIP cached mapping area + $_TARGETNAME_CM0 configure -event reset-init { rp2xxx rom_api_call FC } +} + +if { [info exists _TARGETNAME_RV0] } { + target create $_TARGETNAME_RV0 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 0 + $_TARGETNAME_RV0 riscv set_enable_virt2phys off + + $_TARGETNAME_RV0 configure -event reset-init "_rv_reset_init" + + if { [info exists _TARGETNAME_CM0] } { + # just for setting after init when the event become-available is not fired + $_TARGETNAME_RV0 configure -event examine-end "rp2xxx _switch_target $_TARGETNAME_CM0 $_TARGETNAME_RV0" + } +} + +if { [info exists _TARGETNAME_CM1] } { + target create $_TARGETNAME_CM1 cortex_m -dap $_CHIPNAME.dap -ap-num 0x4000 + $_TARGETNAME_CM1 cortex_m reset_config sysresetreq +} + +if { [info exists _TARGETNAME_RV1] } { + target create $_TARGETNAME_RV1 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 1 + $_TARGETNAME_RV1 riscv set_enable_virt2phys off +} + +if { [info exists USE_SMP] } { + set _USE_SMP $USE_SMP +} elseif { [info exists _TARGETNAME_CM0] == [info exists _TARGETNAME_CM1] + && [info exists _TARGETNAME_RV0] == [info exists _TARGETNAME_RV1] } { + set _USE_SMP 1 +} else { + set _USE_SMP 0 +} +if { $_USE_SMP } { + if { [info exists _TARGETNAME_CM0] && [info exists _TARGETNAME_CM1] } { + $_TARGETNAME_CM0 configure -rtos hwthread + $_TARGETNAME_CM1 configure -rtos hwthread + target smp $_TARGETNAME_CM0 $_TARGETNAME_CM1 + } + if { [info exists _TARGETNAME_RV0] && [info exists _TARGETNAME_RV1] } { + $_TARGETNAME_RV0 configure -rtos hwthread + $_TARGETNAME_RV1 configure -rtos hwthread + target smp $_TARGETNAME_RV0 $_TARGETNAME_RV1 + } +} + +if { [info exists _TARGETNAME_0] } { + set _FLASH_TARGET $_TARGETNAME_0 +} +if { ![info exists _FLASH_TARGET] && [info exists _TARGETNAME_1] } { + set _FLASH_TARGET $_TARGETNAME_1 + if { [info exists _TARGETNAME_CM1] && [info exists _TARGETNAME_RV1] } { + echo "Info : $_CHIPNAME.flash will be handled by $_TARGETNAME_1 without switching" + } +} +if { [info exists _FLASH_TARGET] } { + # QSPI flash size detection during gdb connect requires to back-up RAM + set _WKA_BACKUP [expr { $_FLASHSIZE == 0 }] + $_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup $_WKA_BACKUP + if { [info exists _TARGETNAME_CM0] && [info exists _TARGETNAME_RV0] } { + $_TARGETNAME_RV0 configure -work-area-phys 0x20010000 \ + -work-area-size $_WORKAREASIZE -work-area-backup $_WKA_BACKUP + echo "Info : $_CHIPNAME.flash will be handled by the active one of $_FLASH_TARGET and $_TARGETNAME_RV0 cores" + } + set _FLASHNAME $_CHIPNAME.flash + flash bank $_FLASHNAME rp2xxx 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET +} + +if { [info exists _TARGETNAME_1] } { + # Alias to ensure gdb connecting to core 1 gets the correct memory map + flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME +} + +if { [info exists _TARGETNAME_0] } { + # Select core 0 + targets $_TARGETNAME_0 +} + +# Cold reset resets everything except DP +proc cold_reset { { __CHIPNAME "" } } { + if { $__CHIPNAME == "" } { + global _CHIPNAME + set __CHIPNAME $_CHIPNAME + } + poll off + # set CDBGRSTREQ (and keep set CSYSPWRUPREQ and CDBGPWRUPREQ) + $__CHIPNAME.dap dpreg 4 0x54000000 + set dpstat [$__CHIPNAME.dap dpreg 4] + if { [expr { $dpstat & 0xcc000000 }] != 0xcc000000 } { + echo "Warn : dpstat_reset failed, DP STAT $dpstat" + } + $__CHIPNAME.dap dpreg 4 0x50000000 + dap init + poll on +} + +# Rescue reset resets everything except DP and RP_AP +# Both Cortex-M33 cores stop in bootrom +proc rescue_reset { { __CHIPNAME "" } } { + if { $__CHIPNAME == "" } { + global _CHIPNAME + set __CHIPNAME $_CHIPNAME + } + poll off + # set bit RESCUE_RESTART in RP_AP: CTRL register + $__CHIPNAME.dap apreg 0x80000 0 0x80000000 + $__CHIPNAME.dap apreg 0x80000 0 0 + dap init + poll on + if { [lsearch [target names] $__CHIPNAME.cm0] < 0 } { + echo "Info : restart OpenOCD with 'set USE_CORE { cm0 cm1 }' to debug after rescue" + } +} + +if { $_RESCUE } { + init + rescue_reset +} + +proc _rv_reset_init { } { + set chip_id [format 0x%08x [read_memory 0x40000000 32 1]] + + # Version related workarounds + switch $chip_id { + 0x00004927 { # A0 + # remove IO_QSPI isolation + mww 0x40030014 0 + mww 0x4003001c 0 + mww 0x40030024 0 + mww 0x4003002c 0 + mww 0x40030034 0 + mww 0x4003003c 0 + } + } + + rp2xxx rom_api_call FC +} diff --git a/tcl/target/rsl10.cfg b/tcl/target/rsl10.cfg new file mode 100644 index 0000000000..f4692cc7fe --- /dev/null +++ b/tcl/target/rsl10.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# RSL10: ARM Cortex-M3 +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rsl10 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# TODO: configure reset +# reset_config srst_only srst_nogate connect_assert_srst + +$_TARGETNAME configure -event examine-fail rsl10_lock_warning + +proc rsl10_check_connection {} { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg 0 0xfc] + if {$IDR != 0x24770011} { + echo "Error: Cannot access RSL10 AP, maybe connection problem!" + return 1 + } + return 0 +} + +proc rsl10_lock_warning {} { + if {[rsl10_check_connection]} {return} + + poll off + echo "****** WARNING ******" + echo "RSL10 device probably has lock engaged." + echo "Debug access is denied." + echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device." + echo "****** ....... ******" + echo "" +} + +flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME + +# TODO: implement flashing for nvr4 +# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME diff --git a/tcl/target/rtl872xd.cfg b/tcl/target/rtl872xd.cfg new file mode 100644 index 0000000000..65730e217f --- /dev/null +++ b/tcl/target/rtl872xd.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR MIT +# Realtek RTL872xD (ARM Cortex-M33 + M23, wifi+bt dualband soc) + +# HLA does not support AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + shutdown +} + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rtl872xd +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.km0 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 +target create $_TARGETNAME.km4 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 2 + +cortex_m reset_config sysresetreq + +adapter speed 1000 diff --git a/tcl/target/s32k.cfg b/tcl/target/s32k.cfg new file mode 100644 index 0000000000..3ff3239739 --- /dev/null +++ b/tcl/target/s32k.cfg @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale S32K devices +# Similar to Kinetis Kx series devices. +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s32k +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0995001d +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.pflash +flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME -s32k +kinetis create_banks + +adapter speed 1000 + +reset_config srst_nogate + +if {[using_hla]} { + echo "" + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions." + echo " A high level adapter (like a ST-Link) you are currently using cannot access" + echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your" + echo " configuration. Also security locked state of the device will not be reported." + echo " Expect problems connecting to a blank device without boot ROM." + echo "" + echo " Be very careful as you can lock the device though there is no way to unlock" + echo " it without mass erase. Don't set write protection on the first block." + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo "" +} else { + # Detect secured MCU or boot lock-up in RESET/WDOG loop + $_TARGETNAME configure -event examine-fail { + kinetis mdm check_security + } + # During RESET/WDOG loop the target is sometimes falsely examined + $_TARGETNAME configure -event examine-end { + kinetis mdm check_security + } + + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +# Disable watchdog not to disturb OpenOCD algorithms running on MCU +# (e.g. armv7m_checksum_memory() in verify_image) +# Flash driver also disables watchdog before FTFA flash programming. +$_TARGETNAME configure -event reset-init { + kinetis disable_wdog +} diff --git a/tcl/target/snps_hsdk_4xd.cfg b/tcl/target/snps_hsdk_4xd.cfg new file mode 100644 index 0000000000..1520e3d7c9 --- /dev/null +++ b/tcl/target/snps_hsdk_4xd.cfg @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2023 Synopsys, Inc. +# Artemiy Volkov <artemiy@synopsys.com> + +# Adapted from tcl/target/snps_hsdk.cfg. + +# +# HS Development Kit SoC. +# +# Contains quad-core ARC HS47D. +# + +source [find cpu/arc/hs.tcl] + +set _coreid 0 +set _dbgbase [expr {$_coreid << 13}] + +# CHIPNAME will be used to choose core family (600, 700 or EM). As far as +# OpenOCD is concerned EM and HS are identical. +set _CHIPNAME arc-em + + +proc setup_cpu {core_index expected_id} { + global _coreid + global _dbgbase + global _CHIPNAME + + set _TARGETNAME $_CHIPNAME.cpu$core_index + jtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id + + target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME + $_TARGETNAME configure -coreid $_coreid + $_TARGETNAME configure -dbgbase $_dbgbase + $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" + + arc_hs_init_regs + + $_TARGETNAME arc cache l2 auto 1 + + set _coreid [expr {$_coreid + 1}] + set _dbgbase [expr {$_coreid << 13}] +} + +# OpenOCD discovers JTAG TAPs in reverse order. + +setup_cpu 4 0x100c54b1 +setup_cpu 3 0x100854b1 +setup_cpu 2 0x100454b1 +setup_cpu 1 0x100054b1 diff --git a/tcl/target/spacemit-k1.cfg b/tcl/target/spacemit-k1.cfg new file mode 100644 index 0000000000..e57d1adbc8 --- /dev/null +++ b/tcl/target/spacemit-k1.cfg @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# SpacemiT Key Stone K1 target +# +# https://www.spacemit.com/key-stone-k1 +# + +transport select jtag + +adapter speed 2000 + +# Set TARGET to "rcpu" to enable JTAG for RCPU +if { [info exists TARGET] } { + set _TARGET $TARGET +} else { + set _TARGET x60 +} + +if { $_TARGET == "rcpu" } { + set CPUTAPID 0x10308A6D + set DRVAL 0xe +} else { + set CPUTAPID 0x10000E21 + set DRVAL 0xa +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME k1 +} + +if { [info exists CORES] } { + set _cores $CORES +} else { + set _cores 1 +} + +if { [info exists SECJTAG] } { + jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID +} else { + jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable + jtag configure pre.unknown -event tap-enable "" + + jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID -disable + jtag configure $_CHIPNAME.cpu -event tap-enable "" + + jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version + + jtag configure post.unknown -event setup { + global _CHIPNAME DRVAL + + irscan post.unknown 0x98 + drscan post.unknown 16 $DRVAL + + jtag tapenable pre.unknown + jtag tapenable $_CHIPNAME.cpu + } +} + +set _TARGETNAME $_CHIPNAME.cpu_$_TARGET + +if { $_TARGET == "rcpu" } { + target create $_TARGETNAME.0 riscv -chain-position $_CHIPNAME.cpu +} else { + set DBGBASE {0x0 0x400} + set _smp_command "target smp" + + for { set _core 0 } { $_core < $_cores } { incr _core } { + target create $_TARGETNAME.$_core riscv -chain-position $_CHIPNAME.cpu \ + -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]] + + if { [expr {$_core % 4}] == 0 } { + $_TARGETNAME.$_core configure -rtos hwthread + } + + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } + + eval $_smp_command +} + +set _SPEED 8000 + +$_TARGETNAME.0 configure -event examine-start { + adapter speed $_SPEED + puts [ adapter speed ] +} + +foreach t [target names] { + # $t riscv set_mem_access sysbus progbuf + $t riscv set_mem_access progbuf +} diff --git a/tcl/target/stm32c0x.cfg b/tcl/target/stm32c0x.cfg new file mode 100644 index 0000000000..d015120319 --- /dev/null +++ b/tcl/target/stm32c0x.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32c0x family +# +# stm32c0 devices support SWD transports only. +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32c0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 6kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1800 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +# reasonable default +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable DBGMCU clock + # RCC_APB1ENR |= DBGMCUEN + mmw 0x4002103C 0x08000000 0 + + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg index 4c4ff25f2b..53e81a59f6 100644 --- a/tcl/target/stm32f1x.cfg +++ b/tcl/target/stm32f1x.cfg @@ -83,9 +83,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042004 0x00000307 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg index a20941d124..f47582648a 100644 --- a/tcl/target/stm32f2x.cfg +++ b/tcl/target/stm32f2x.cfg @@ -83,9 +83,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index ebec04f857..aa978d9c84 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -24,6 +24,14 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x4000 } +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz # # Since we may be running of an RC oscilator, we crank down the speed a @@ -63,7 +71,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME reset_config srst_nogate @@ -103,9 +111,16 @@ $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end } $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start } $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xe0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg index 5be0cf505b..a77527c46d 100644 --- a/tcl/target/stm32f4x.cfg +++ b/tcl/target/stm32f4x.cfg @@ -40,8 +40,6 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 - if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 } @@ -93,24 +91,33 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -proc proc_post_enable {_chipname} { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { targets $_chipname.cpu if { [$_chipname.tpiu cget -protocol] eq "sync" } { + # Enable the GPIOE clock. + mmw 0x40023830 0x00000010 0x00000010 + switch [$_chipname.tpiu cget -port-width] { 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 mmw 0xE0042004 0x00000060 0x000000c0 mmw 0x40021020 0x00000000 0x0000ff00 mmw 0x40021000 0x000000a0 0x000000f0 mmw 0x40021008 0x000000f0 0x00000000 } 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 mmw 0xE0042004 0x000000a0 0x000000c0 mmw 0x40021020 0x00000000 0x000fff00 mmw 0x40021000 0x000002a0 0x000003f0 mmw 0x40021008 0x000003f0 0x00000000 } 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 mmw 0xE0042004 0x000000e0 0x000000c0 mmw 0x40021020 0x00000000 0x0fffff00 mmw 0x40021000 0x00002aa0 0x00003ff0 @@ -118,11 +125,12 @@ proc proc_post_enable {_chipname} { } } } else { + # Set TRACE_IOEN; TRACE_MODE to async mmw 0xE0042004 0x00000020 0x000000c0 } } -$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME" +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" $_TARGETNAME configure -event reset-init { # Configure PLL to boost clock to HSI x 4 (64 MHz) diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index 92cf30e0b5..3782b9a9cc 100644 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -109,13 +109,20 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" + $_TARGETNAME configure -event reset-init { # If the HSE was previously enabled and the external clock source # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg index 04cc9447c6..39ed1e3818 100644 --- a/tcl/target/stm32g4x.cfg +++ b/tcl/target/stm32g4x.cfg @@ -97,9 +97,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg index 91360d829b..53d9076e19 100644 --- a/tcl/target/stm32l1.cfg +++ b/tcl/target/stm32l1.cfg @@ -101,9 +101,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg index dabdacd417..9a696736cd 100644 --- a/tcl/target/stm32l4x.cfg +++ b/tcl/target/stm32l4x.cfg @@ -40,8 +40,6 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 - if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 } @@ -103,24 +101,30 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -proc proc_post_enable {_chipname} { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { targets $_chipname.cpu if { [$_chipname.tpiu cget -protocol] eq "sync" } { switch [$_chipname.tpiu cget -port-width] { 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 mmw 0xE0042004 0x00000060 0x000000c0 mmw 0x48001020 0x00000000 0x0000ff00 mmw 0x48001000 0x000000a0 0x000000f0 mmw 0x48001008 0x000000f0 0x00000000 } 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 mmw 0xE0042004 0x000000a0 0x000000c0 mmw 0x48001020 0x00000000 0x000fff00 mmw 0x48001000 0x000002a0 0x000003f0 mmw 0x48001008 0x000003f0 0x00000000 } 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 mmw 0xE0042004 0x000000e0 0x000000c0 mmw 0x48001020 0x00000000 0x0fffff00 mmw 0x48001000 0x00002aa0 0x00003ff0 @@ -128,11 +132,12 @@ proc proc_post_enable {_chipname} { } } } else { + # Set TRACE_IOEN; TRACE_MODE to async mmw 0xE0042004 0x00000020 0x000000c0 } } -$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME" +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" $_TARGETNAME configure -event reset-init { # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz). diff --git a/tcl/target/stm32u0x.cfg b/tcl/target/stm32u0x.cfg new file mode 100644 index 0000000000..d3aaed3cbb --- /dev/null +++ b/tcl/target/stm32u0x.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for STM32U0x series. +# +# STM32U0 devices support only SWD transport. +# + +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32u0x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1FFF6800 0 0 0 $_TARGETNAME + +adapter speed 2000 + +if {![using_hla]} { + # Use SYSRESETREQ to perform a soft reset if SRST is not fitted. + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power). + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters when core is halted. + # DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} diff --git a/tcl/target/stm32wbax.cfg b/tcl/target/stm32wbax.cfg new file mode 100644 index 0000000000..129940720b --- /dev/null +++ b/tcl/target/stm32wbax.cfg @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32wbax family + +# +# stm32wba devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32wbax +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x6ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME + +# Common knowledges tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://openocd.zylin.com/#/c/3366/ +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event reset-init { + # CPU comes out of reset with HSION | HSIRDY. + # Use HSI 16 MHz clock, compliant even with VOS == 2. + # 1 WS compliant with VOS == 2 and 16 MHz. + mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1 + mmw 0x56020C00 0x00000100 0x00000000 ;# RCC_CR |= HSION + mmw 0x56020C1C 0x00000000 0x00000002 ;# RCC_CFGR1: SW=HSI16 + # Boost JTAG frequency + adapter speed 4000 +} + +$_TARGETNAME configure -event reset-start { + # Reset clock is HSI (16 MHz) + adapter speed 2000 +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0xE0042004 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg index 0c5b76148c..737b1447c0 100644 --- a/tcl/target/stm32wbx.cfg +++ b/tcl/target/stm32wbx.cfg @@ -97,9 +97,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE004203C 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg index 81e590f255..39c897fc5d 100644 --- a/tcl/target/stm32wlx.cfg +++ b/tcl/target/stm32wlx.cfg @@ -119,9 +119,7 @@ $_CHIPNAME.cpu0 configure -event examine-end { } } -$_CHIPNAME.cpu0 configure -event trace-config { - # nothing to do -} +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 if {[set $_CHIPNAME.DUAL_CORE]} { target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 diff --git a/tcl/target/stm32x5x_common.cfg b/tcl/target/stm32x5x_common.cfg index 276d0cca0c..fb3aeb18c1 100644 --- a/tcl/target/stm32x5x_common.cfg +++ b/tcl/target/stm32x5x_common.cfg @@ -58,7 +58,9 @@ if {[using_jtag]} { reset_config srst_nogate -if {![using_hla]} { +if {[using_hla]} { + echo "Warn : The selected adapter does not support debugging this device in secure mode" +} else { # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq @@ -71,13 +73,18 @@ proc stm32x5x_is_secure {} { } proc stm32x5x_ahb_ap_non_secure_access {} { - # SPROT=1=Non Secure access, Priv=1 - [[target current] cget -dap] apcsw 0x4B000000 0x4F000000 + # in HLA mode, non-secure debugging is possible without changing the AP CSW + if {![using_hla]} { + # SPROT=1=Non Secure access, Priv=1 + [[target current] cget -dap] apcsw 0x4B000000 0x4F000000 + } } proc stm32x5x_ahb_ap_secure_access {} { - # SPROT=0=Secure access, Priv=1 - [[target current] cget -dap] apcsw 0x0B000000 0x4F000000 + if {![using_hla]} { + # SPROT=0=Secure access, Priv=1 + [[target current] cget -dap] apcsw 0x0B000000 0x4F000000 + } } $_TARGETNAME configure -event reset-start { @@ -146,9 +153,17 @@ $_TARGETNAME configure -event gdb-flash-erase-start { $_TARGETNAME configure -work-area-phys $workarea_addr } -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_EN and TRACE_IOEN in DBGMCU_CR + # Leave TRACE_MODE untouched (defaults to async). + # When using sync change this value accordingly to configure trace pins # assignment - mmw 0xE0044004 0x00000020 0 + mmw 0xE0044004 0x00000030 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm8l151x2.cfg b/tcl/target/stm8l151x2.cfg new file mode 100644 index 0000000000..db88c715ba --- /dev/null +++ b/tcl/target/stm8l151x2.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x2 +# Supported Devices: +# STM8L151C2 +# STM8L151F2 +# STM8L151G2 +# STM8L151K2 + +# 1kB RAM +# Start 0x0000 +# End 0x03ff +set WORKAREASIZE 1024 + +# 4kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0x8fff + +# 256B EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x10ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x487f + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/tcl/target/stm8l151x3.cfg b/tcl/target/stm8l151x3.cfg new file mode 100644 index 0000000000..fe904b4f28 --- /dev/null +++ b/tcl/target/stm8l151x3.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x3 +# Supported Devices: +# STM8L151C3 +# STM8L151F3 +# STM8L151G3 +# STM8L151K3 + +# 1kB RAM +# Start 0x0000 +# End 0x03ff +set WORKAREASIZE 1024 + +# 8kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0x9fff + +# 256B EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x10ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x487f + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/tcl/target/stm8l152.cfg b/tcl/target/stm8l152.cfg index b716ce18ef..033b826d8e 100644 --- a/tcl/target/stm8l152.cfg +++ b/tcl/target/stm8l152.cfg @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later -#config script for STM8L152 +echo 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg' +echo ' using stm8l152.cfg for backwards compatability' set EEPROMSTART 0x1000 set EEPROMEND 0x13ff diff --git a/tcl/target/stm8l15xx4.cfg b/tcl/target/stm8l15xx4.cfg new file mode 100644 index 0000000000..443819357b --- /dev/null +++ b/tcl/target/stm8l15xx4.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x4/STM8L152x4 +# Supported Devices: +# STM8L151C4 +# STM8L151G4 +# STM8L151K4 +# STM8L152C4 +# STM8L152K4 + +# 2kB RAM +# Start 0x0000 +# End 0x07ff +set WORKAREASIZE 2048 + +# 16kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0xbfff + +# 1kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x13ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/tcl/target/stm8l15xx6.cfg b/tcl/target/stm8l15xx6.cfg new file mode 100644 index 0000000000..5243295173 --- /dev/null +++ b/tcl/target/stm8l15xx6.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x6/STM8L152x6 +# Supported Devices: +# STM8L151C6 +# STM8L151G6 +# STM8L151K6 +# STM8L151R6 +# STM8L152C6 +# STM8L152K6 +# STM8L152R6 + +# 2kB RAM +# Start 0x0000 +# End 0x07ff +set WORKAREASIZE 2048 + +# 32kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0xffff + +# 1kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x13ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/tcl/target/stm8l15xx8.cfg b/tcl/target/stm8l15xx8.cfg new file mode 100644 index 0000000000..e354827377 --- /dev/null +++ b/tcl/target/stm8l15xx8.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x8/STM8L152x8 +# Supported Devices: +# STM8L151C8 +# STM8L151M8 +# STM8L151R8 +# STM8L152C8 +# STM8L152K8 +# STM8L152M8 +# STM8L152R8 + +# 4kB RAM +# Start 0x0000 +# End 0x0fff +set WORKAREASIZE 4096 + +# 64kB Flash +set FLASHSTART 0x08000 +set FLASHEND 0x17fff + +# 2kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x17ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg index d5e13e269a..97111f1cc4 100644 --- a/tcl/target/ti-cjtag.cfg +++ b/tcl/target/ti-cjtag.cfg @@ -5,6 +5,7 @@ # Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information. proc ti_cjtag_to_4pin_jtag {jrc} { # Bypass + runtest 20 irscan $jrc 0x3f -endstate RUN/IDLE # Two zero bit scans and a one bit drshift pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE diff --git a/tcl/target/ti_cc26x2x7.cfg b/tcl/target/ti_cc26x2x7.cfg new file mode 100644 index 0000000000..91c1a80596 --- /dev/null +++ b/tcl/target/ti_cc26x2x7.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC26x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc26x2x7 +set JRC_TAPID 0x1BB7702F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 254bb69716..0dee74e5ee 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -2,16 +2,42 @@ # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ # # Texas Instruments K3 devices: +# * AM243: https://www.ti.com/lit/pdf/spruim2 +# Has 4 R5 Cores, M4F and an M3 +# * AM261: https://www.ti.com/lit/pdf/sprujb6 +# Has 2 R5 Cores and an M4F +# * AM263: https://www.ti.com/lit/pdf/spruj17 +# Has 4 R5 Cores and an M3 +# * AM263P: https://www.ti.com/lit/pdf/spruj55 +# Has 4 R5 Cores and an M4F +# * AM273: https://www.ti.com/lit/pdf/spruiu0 +# Has 2 R5 Cores and an M3 +# * AM625: https://www.ti.com/lit/pdf/spruiv7a +# Has 4 ARMV8 Cores and 1 R5 Core and an M4F +# * AM62A7: https://www.ti.com/lit/pdf/spruj16a +# Has 4 ARMV8 Cores and 2 R5 Cores +# * AM62P: https://www.ti.com/lit/pdf/spruj83 +# Has 4 ARMV8 Cores and 2 R5 Cores +# * AM62L: https://www.ti.com/lit/pdf/sprujb4 +# Has 2 ARMv8 Cores only +# * AM642: https://www.ti.com/lit/pdf/spruim2 +# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 # * AM654x: https://www.ti.com/lit/pdf/spruid7 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3 -# * J721E: https://www.ti.com/lit/pdf/spruil1 -# Has 2 ARMV8 Cores and 6 R5 Cores and an M3 # * J7200: https://www.ti.com/lit/pdf/spruiu1 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3 -# * AM642: https://www.ti.com/lit/pdf/spruim2 -# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 +# * J721E: https://www.ti.com/lit/pdf/spruil1 +# Has 2 ARMV8 Cores and 6 R5 Cores and an M3 +# * J721S2: https://www.ti.com/lit/pdf/spruj28 +# Has 2 ARMV8 Cores and 6 R5 Cores and an M4F +# * J722S: https://www.ti.com/lit/zip/sprujb3 +# Has 4 ARMV8 Cores and 3 R5 Cores +# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52 +# Has 8 ARMV8 Cores and 8 R5 Cores # +source [find target/swj-dp.tcl] + if { [info exists SOC] } { set _soc $SOC } else { @@ -32,6 +58,7 @@ set CM3_CTIBASE {0x3C016000} # sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x44} +set _sysctrl_ap_num 7 # All the ARMV8s are the next processors. # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1 @@ -43,6 +70,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000} set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000} set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} +set _r5_ap_num 1 # Finally an General Purpose(GP) MCU set CM4_CTIBASE {0x20001000} @@ -52,10 +80,65 @@ set _gp_mcu_cores 0 # General Purpose MCU power-ap unlock offsets set _gp_mcu_ap_unlock_offsets {0xf0 0x60} +# Generic mem-ap port number +set _mem_ap_num 2 + +# Generic AP_SEL PWR Register number +set _power_ap_num 3 + +# Generic SPREC RESET BANK and Field number +set _powerap_sprec_reset 0xf0 + # Set configuration overrides for each SOC switch $_soc { + am261 - + am263p - + am263 { + set _K3_DAP_TAPID 0x2bb7d02f + + # Mem-ap port + set _mem_ap_num 6 + + # AM263 has 0 ARMV8 CPUs + set _armv8_cores 0 + + # AM263 has 2 cluster of 2 R5s cores. + set _r5_cores 4 + set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} + set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000} + set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000} + set _r5_ap_num 5 + + set _power_ap_num 7 + + if { "$_soc" == "am263p" } { + set _K3_DAP_TAPID 0x1bb9502f + } + if { "$_soc" == "am261" } { + set _K3_DAP_TAPID 0x1bba602f + set _r5_cores 2 + } + } + am273 { + set _K3_DAP_TAPID 0x1bb6a02f + + # Mem-ap port + set _mem_ap_num 6 + + # system controller is on AP0 + set _sysctrl_ap_num 0 + + # AM273 has 0 ARMV8 CPUs + set _armv8_cores 0 + + # AM273 has 1 cluster of 2 R5s cores. + set _r5_cores 2 + set R5_NAMES {main0_r5.0 main0_r5.1} + set R5_DBGBASE {0x90030000 0x90032000} + set R5_CTIBASE {0x90038000 0x90039000} + set _r5_ap_num 5 + } am654 { - set _CHIPNAME am654 set _K3_DAP_TAPID 0x0bb5a02f # AM654 has 2 clusters of 2 A53 cores each. @@ -69,8 +152,8 @@ switch $_soc { # Sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x50} } + am243 - am642 { - set _CHIPNAME am642 set _K3_DAP_TAPID 0x0bb3802f # AM642 has 1 clusters of 2 A53 cores each. @@ -87,9 +170,14 @@ switch $_soc { # M4 processor set _gp_mcu_cores 1 + + # Overrides for am243 + if { "$_soc" == "am243" } { + # Uses the same JTAG ID + set _armv8_cores 0 + } } am625 { - set _CHIPNAME am625 set _K3_DAP_TAPID 0x0bb7e02f # AM625 has 1 clusters of 4 A53 cores. @@ -112,9 +200,76 @@ switch $_soc { # M4 processor set _gp_mcu_cores 1 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c} + + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x740002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 10 + # Emulated AP description + set _dmem_emu_base_address 0x760000000 + set _dmem_emu_base_address_map_to 0x1d500000 + set _dmem_emu_ap_list 1 + } + j722s - + am62p - + am62a7 { + set _K3_DAP_TAPID 0x0bb8d02f + + # AM62a7/AM62P has 1 cluster of 4 A53 cores. + set _armv8_cpu_name a53 + set _armv8_cores 4 + set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000} + set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000} + + # AM62a7/AM62P has 2 cluster of 1 R5 core. + set _r5_cores 2 + set R5_NAMES {main0_r5.0 mcu0_r5.0} + set R5_DBGBASE {0x9d410000 0x9d810000} + set R5_CTIBASE {0x9d418000 0x9d818000} + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x740002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 10 + # Emulated AP description + set _dmem_emu_base_address 0x760000000 + set _dmem_emu_base_address_map_to 0x1d500000 + set _dmem_emu_ap_list 1 + + # Overrides for am62p + if { "$_soc" == "am62p" } { + set _K3_DAP_TAPID 0x0bb9d02f + set R5_NAMES {wkup0_r5.0 mcu0_r5.0} + } + # Overrides for j722s + if { "$_soc" == "j722s" } { + set _K3_DAP_TAPID 0x0bba002f + set _r5_cores 3 + set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0} + set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000} + set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000} + } + } + am62l { + set _K3_DAP_TAPID 0x0bba702f + + # AM62Lx has 1 cluster of 2 A53 cores. + set _armv8_cpu_name a53 + set _armv8_cores 2 + set ARMV8_DBGBASE {0x90010000 0x90110000} + set ARMV8_CTIBASE {0x90020000 0x90120000} + + # Has no supporting microcontrollers + set _r5_cores 0 } j721e { - set _CHIPNAME j721e set _K3_DAP_TAPID 0x0bb6402f # J721E has 1 cluster of 2 A72 cores. set _armv8_cpu_name a72 @@ -122,9 +277,18 @@ switch $_soc { # J721E has 3 clusters of 2 R5 cores each. set _r5_cores 6 + + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x4c40002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 8 + # Emulated AP description + set _dmem_emu_base_address 0x4c60000000 + set _dmem_emu_base_address_map_to 0x1d600000 + set _dmem_emu_ap_list 1 } j7200 { - set _CHIPNAME j7200 set _K3_DAP_TAPID 0x0bb6d02f # J7200 has 1 cluster of 2 A72 cores. @@ -140,7 +304,6 @@ switch $_soc { set CM3_CTIBASE {0x20001000} } j721s2 { - set _CHIPNAME j721s2 set _K3_DAP_TAPID 0x0bb7502f # J721s2 has 1 cluster of 2 A72 cores. @@ -159,12 +322,53 @@ switch $_soc { set _gp_mcu_cores 1 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c} } + j784s4 { + set _K3_DAP_TAPID 0x0bb8002f + + # j784s4 has 2 cluster of 4 A72 cores each. + set _armv8_cpu_name a72 + set _armv8_cores 8 + set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000 + 0x90810000 0x90910000 0x90a10000 0x90b10000} + set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000 + 0x90820000 0x90920000 0x90a20000 0x90b20000} + + # J721s2 has 4 clusters of 2 R5 cores each. + set _r5_cores 8 + set R5_DBGBASE {0x9d010000 0x9d012000 + 0x9d410000 0x9d412000 + 0x9d510000 0x9d512000 + 0x9d610000 0x9d612000} + set R5_CTIBASE {0x9d018000 0x9d019000 + 0x9d418000 0x9d419000 + 0x9d518000 0x9d519000 + 0x9d618000 0x9d619000} + set R5_NAMES {mcu_r5.0 mcu_r5.1 + main0_r5.0 main0_r5.1 + main1_r5.0 main1_r5.1 + main2_r5.0 main2_r5.1} + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + } default { echo "'$_soc' is invalid!" } } -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version +proc _get_rtos_type_for_cpu { target_name } { + if { [info exists ::RTOS($target_name)] } { + return $::RTOS($target_name) + } + return none +} + +set _CHIPNAME $_soc + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu set _TARGETNAME $_CHIPNAME.cpu @@ -172,8 +376,13 @@ set _TARGETNAME $_CHIPNAME.cpu set _CTINAME $_CHIPNAME.cti # sysctrl is always present -cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] -target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine +cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0] + +target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl] + $_TARGETNAME.sysctrl configure -event reset-assert { } proc sysctrl_up {} { @@ -216,8 +425,9 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \ -baseaddr [lindex $ARMV8_CTIBASE $_core] - target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine + target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \ + -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core] set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core" @@ -236,34 +446,37 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { } } -# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs -set _armv8_up_cmd "$_armv8_cpu_name"_up -# Available if V8_SMP_DEBUG is set to non-zero value -set _armv8_smp_cmd "$_armv8_cpu_name"_smp +if { $_armv8_cores > 0 } { + # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs + set _armv8_up_cmd "$_armv8_cpu_name"_up + # Available if V8_SMP_DEBUG is set to non-zero value + set _armv8_smp_cmd "$_armv8_cpu_name"_smp -if { $_v8_smp_debug == 0 } { - proc $_armv8_up_cmd { args } { - foreach _core $args { - targets $_core - _cpu_no_smp_up + if { $_v8_smp_debug == 0 } { + proc $_armv8_up_cmd { args } { + foreach _core $args { + targets $_core + _cpu_no_smp_up + } } + } else { + proc $_armv8_smp_cmd { args } { + _armv8_smp_up + } + # Declare SMP + target smp {*}$_v8_smp_targets } -} else { - proc $_armv8_smp_cmd { args } { - _armv8_smp_up - } - # Declare SMP - target smp $:::_v8_smp_targets } for { set _core 0 } { $_core < $_r5_cores } { incr _core } { set _r5_name [lindex $R5_NAMES $_core] - cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \ + cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \ -baseaddr [lindex $R5_CTIBASE $_core] # inactive core examination will fail - wait till startup of additional core target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine + -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name] $_TARGETNAME.$_r5_name configure -event gdb-attach { _cpu_no_smp_up @@ -281,7 +494,8 @@ proc r5_up { args } { if { $_gp_mcu_cores != 0 } { cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] - target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu] $_TARGETNAME.gp_mcu configure -event reset-assert { } proc gp_mcu_up {} { @@ -299,3 +513,32 @@ if { $_gp_mcu_cores != 0 } { halt 1000 } } + +# In case of DMEM access, configure the dmem adapter with offsets from above. +if { 0 == [string compare [adapter name] dmem ] } { + if { [info exists _dmem_base_address] } { + # DAPBUS (Debugger) description + dmem base_address $_dmem_base_address + dmem ap_address_offset $_dmem_ap_address_offset + dmem max_aps $_dmem_max_aps + + # The following are the details of APs to be emulated for direct address access. + # Debug Config (Debugger) description + dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to + dmem emu_ap_list $_dmem_emu_ap_list + # We are going local bus, so speed is really dummy here. + adapter speed 2500 + } else { + puts "ERROR: ${SOC} data is missing to support dmem access!" + } +} else { + # AXI AP access port for SoC address map + target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num +} + +# Reset system using (Debug Reset) SPREC Register,SYSTEMRESET bit field via apreg +proc dbg_sys_reset {} { + $::_CHIPNAME.dap apreg $::_power_ap_num $::_powerap_sprec_reset 0x1 +} + +add_help_text dbg_sys_reset "Debugger initiated system reset attempt via Power-AP" diff --git a/tcl/target/ti_mspm0.cfg b/tcl/target/ti_mspm0.cfg new file mode 100644 index 0000000000..4e9b89c1f5 --- /dev/null +++ b/tcl/target/ti_mspm0.cfg @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments MSPM0L/G - ARM Cortex-M0 @ 32MHz +# https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html +# + +source [find bitsbytes.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + # Meant to work with MSPM0L and MSPM0G class of devices. + set _CHIPNAME mspm0x +} + +if { [info exists CPUTAPID] } { + set _DAP_TAPID $CPUTAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists DAP_SWD_ID] } { + set _DAP_SWD_ID $DAP_SWD_ID +} else { + set _DAP_SWD_ID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +# MSPM0 only supports swd, so set it here and save a line for custom boards +transport select swd + +set _DAP_ID $_DAP_SWD_ID + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREABASE] } { + set _WORKAREABASE $WORKAREABASE +} else { + set _WORKAREABASE 0x20000000 +} +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # Smallest SRAM size is 1K SRAM. + set _WORKAREASIZE 0x400 +} + +# +# MSPM0 Debug SubSystem Mailbox (DSSM) Communication helpers +# + +proc _mspm0_wait_for_dssm_response {command} { + # Wait for SECAP::RCR rx_valid to be set + set timeout 1000 + while { [expr { [$::_CHIPNAME.dap apreg 2 0xc] & 0x1}] != 0x1 } { + sleep 1 + set timeout [expr {$timeout - 1}] + if { $timeout == 0 } { + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + return -code error [format "MSPM0 SECAP RCR=0x%08x timeout rx_valid" $rcr] + } + } + + # Read SECAP::RXD to clear the RX_VALID bit + set rxd [$::_CHIPNAME.dap apreg 2 0x8] + # Read SECAP::RCR + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + + # Check if we got successful response. This is denoted as: + # 8 LSBits of $command should matchup with SECAP::RCR + # and + # SECAP::RXD should be 0x10003 + if { ([expr { $command & 0xff}] == $rcr) && ($rxd == 0x10003) } { + return 0 + } + + # Provide some debug log for users to report back if CMD fails. + return -code error [format "MSPM0 SECAP CMD FAIL! RXD: 0x%08X RCR: 0x%08X" $rxd $rcr] +} + +proc _mspm0_dssm_command {command} { + # SECAP::TCR = command + $::_CHIPNAME.dap apreg 2 0x4 $command + # SECAP::TDR = 0x0 + $::_CHIPNAME.dap apreg 2 0x0 0x0 + # Read SECAP::RCR and RXD to clear up any prev pending reads + set rxd [$::_CHIPNAME.dap apreg 2 0x8] + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + # Make sure everything is synced + sleep 1000 + # Trigger nRST + mspm0_board_reset + + # Wait for ROM to do it's magic and respond back + set res [_mspm0_wait_for_dssm_response $command] + if { $res } { + return $res + } + # Paranoid.. make sure ROM does what it is meant to do + # RX valid should have been cleared after the operation is + # complete + sleep 1000 + + # Trigger nRST to get back to sane system + mspm0_board_reset + sleep 1000 + + return 0 +} + +# NOTE: Password authentication scheme is NOT supported atm. +# mspm0_factory_reset: Factory reset the board +proc mspm0_factory_reset {} { + set res [_mspm0_dssm_command 0x020a] + if { $res } { + echo "Factory Reset failed!" + } else { + echo "Factory reset success! Halting processor" + # We need to halt the processor else the WDT fires! + halt + } + return $res +} + +add_help_text mspm0_factory_reset "Force Factory reset to recover 'bricked' board" + +# NOTE: Password authentication scheme is NOT supported atm. +# mspm0_mass_erase: Mass erase flash +proc mspm0_mass_erase {} { + set res [_mspm0_dssm_command 0x020c] + if { $res } { + echo "Mass Erase failed!" + } else { + echo "Mass Erase success! Halting Processor" + # We need to halt the processor else the WDT fires! + halt + } + return $res +} + +add_help_text mspm0_mass_erase "Mass erase flash" + +# mspm0_start_bootloader: Ask explicitly for bootloader startup +proc mspm0_start_bootloader {} { + set res [_mspm0_dssm_command 0x0108] + if { $res } { + echo "Start BL failed!" + } + return $res +} + +add_help_text mspm0_start_bootloader "Ask explicitly for bootloader startup" + +# MSPM0 requires board level NRST reset to be toggled for +# Factory reset operations to function. +# However this cannot be the default configuration as this +# prevents reset init reset halt to function properly +# since the Debug Subsystem (debugss) logic or coresight +# seems impacted by nRST. +# This can be overridden in board file as required. +# +# mspm0_board_reset: Board level reset +proc mspm0_board_reset {} { + set user_reset_config [reset_config] + reset_config srst_only + set errno [catch {reset}] + eval reset_config $user_reset_config + if {$errno} {error} +} + +add_help_text mspm0_board_reset "Request a board level reset" + +# If the flash is empty or the device is already in low-power state, then +# debug access is not available. to handle this, explicitly control power ap +# to provide access. Refer to Technical Reference Manual for further info. +proc _mspm0_enable_low_power_mode { } { + # PWR_AP::DPREC <= FRCACT(3)=1, RST_CTL(14:16)=1, IHIB_SLP(20)=1 + $::_CHIPNAME.dap apreg 4 0x00 0x104008 + # PWR_AP::SPREC <= SYSRST=1 + $::_CHIPNAME.dap apreg 4 0xF0 0x01 + # PWR_AP::DPREC <= FRCACT(3)=1, IHIB_SLP(20)=1 + $::_CHIPNAME.dap apreg 4 0x00 0x100008 +} + +$_TARGETNAME configure -event examine-start { _mspm0_enable_low_power_mode } +$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME.main mspm0 0 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME.nonmain mspm0 0x41c00000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME.data mspm0 0x41d00000 0 0 0 $_TARGETNAME + +cortex_m reset_config sysresetreq diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg index 213fb094b9..18e0d82941 100644 --- a/tcl/target/ti_tms570.cfg +++ b/tcl/target/ti_tms570.cfg @@ -22,7 +22,7 @@ source [find target/icepick.cfg] if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" # ICEpick-C (JTAG route controller) @@ -35,10 +35,7 @@ set _JRC_TAPID2 0x0B7B302F set _JRC_TAPID3 0x0B95502F set _JRC_TAPID4 0x0B97102F set _JRC_TAPID5 0x0D8A002F -set _JRC_TAPID6 0x2B8A002F -set _JRC_TAPID7 0x2D8A002F -set _JRC_TAPID8 0x3B8A002F -set _JRC_TAPID9 0x3D8A002F +set _JRC_TAPID6 0x0B8A002F jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ @@ -48,9 +45,6 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ -expected-id $_JRC_TAPID4 \ -expected-id $_JRC_TAPID5 \ -expected-id $_JRC_TAPID6 \ - -expected-id $_JRC_TAPID7 \ - -expected-id $_JRC_TAPID8 \ - -expected-id $_JRC_TAPID9 \ -ignore-version jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" @@ -60,7 +54,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu # Cortex-R4 target set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \ - -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003 + -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000 # TMS570 uses quirky BE-32 mode $_CHIPNAME.dap ti_be_32_quirks 1 diff --git a/tcl/target/ti_tms570lc43xx.cfg b/tcl/target/ti_tms570lc43xx.cfg new file mode 100644 index 0000000000..ffda989f97 --- /dev/null +++ b/tcl/target/ti_tms570lc43xx.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set DAP_TAPID 0x0B95A02F +set JRC_TAPID 0x0B95A02F + +source [find target/ti_tms570.cfg] diff --git a/tcl/target/ti_tms570ls1x.cfg b/tcl/target/ti_tms570ls1x.cfg new file mode 100644 index 0000000000..3c25777578 --- /dev/null +++ b/tcl/target/ti_tms570ls1x.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TMS570LS1114, TMS570LS1115 +# TMS570LS1224, TMS570LS1225, TMS570LS1227 +set DAP_TAPID 0x0B95502F +set JRC_TAPID 0x0B95502F + +source [find target/ti_tms570.cfg] diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 417fdd18f2..ea3c7218ee 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -133,7 +133,7 @@ proc enable_apetap {} { set status [$_TARGETNAME_1 curstate] if {[string equal "unknown" $status]} { $_TARGETNAME_1 arp_examine - cache_config l2x 0xa0412000 8 + cache l2x conf 0xa0412000 8 } set status [$_TARGETNAME_2 curstate] @@ -142,9 +142,9 @@ proc enable_apetap {} { } } -tcl_port 5555 -telnet_port 4444 -gdb_port 3333 +tcl port 5555 +telnet port 4444 +gdb port 3333 if { [info exists CHIPNAME] } { global _CHIPNAME @@ -319,7 +319,7 @@ global _MAXSPEED adapter speed $_MAXSPEED -gdb_breakpoint_override hard +gdb breakpoint_override hard set mem inaccessible-by-default-off jtag_ntrst_delay 100 diff --git a/tcl/target/vd_aarch64.cfg b/tcl/target/vd_aarch64.cfg index 619134aa64..177416bd0a 100644 --- a/tcl/target/vd_aarch64.cfg +++ b/tcl/target/vd_aarch64.cfg @@ -2,36 +2,44 @@ # Cadence virtual debug interface # Arm v8 64b Cortex A -if {![info exists _CORES]} { - set _CORES 1 +if {![info exists CORES]} { + set CORES 1 } -if {![info exists _CHIPNAME]} { - set _CHIPNAME aarch64 +if {![info exists CHIPNAME]} { + set CHIPNAME aarch64 +} +if {[info exists ACCESSPORT]} { + set _APNUM "-ap-num $ACCESSPORT" + if { $ACCESSPORT > 0xff } { + set _DAP6 "-adiv6" + } else { + set _DAP6 "-adiv5" + } +} else { + set _APNUM "" } -set _TARGETNAME $_CHIPNAME.cpu -set _CTINAME $_CHIPNAME.cti -set DBGBASE {0x80810000 0x80910000} -set CTIBASE {0x80820000 0x80920000} +set _TARGETNAME $CHIPNAME.cpu +set _CTINAME $CHIPNAME.cti +set _DAPNAME $CHIPNAME.dap -dap create $_CHIPNAME.dap -chain-position $_TARGETNAME -$_CHIPNAME.dap apsel 1 +dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME -for { set _core 0 } { $_core < $_CORES } { incr _core } \ +for { set _core 0 } { $_core < $CORES } { incr _core } \ { - cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core] - set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" + set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]" + eval $_cmd + set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" if { $_core != 0 } { # non-boot core examination may fail - set _command "$_command -defer-examine" - set _smp_command "$_smp_command $_TARGETNAME.$_core" + set _cmd "$_cmd -defer-examine" + set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core" } else { - set _smp_command "target smp $_TARGETNAME.$_core" + set _smp_cmd "target smp $_TARGETNAME.$_core" } - eval $_command + eval $_cmd } -eval $_smp_command +eval $_smp_cmd -# default target is core 0 -targets $_TARGETNAME.0 +set _TARGETCUR $_TARGETNAME.0 +targets $_TARGETCUR diff --git a/tcl/target/vd_cortex_m.cfg b/tcl/target/vd_cortex_m.cfg index 4d7b0df267..7db9d3aba4 100644 --- a/tcl/target/vd_cortex_m.cfg +++ b/tcl/target/vd_cortex_m.cfg @@ -2,11 +2,12 @@ # Cadence virtual debug interface # ARM Cortex M -if {![info exists _CHIPNAME]} { - set _CHIPNAME cortex_m +if {![info exists CHIPNAME]} { + set CHIPNAME cortex_m } -set _TARGETNAME $_CHIPNAME.cpu +set _TARGETNAME $CHIPNAME.cpu +set _DAPNAME $CHIPNAME.dap -dap create $_CHIPNAME.dap -chain-position $_TARGETNAME +dap create $_DAPNAME -chain-position $_TARGETNAME -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +target create $_TARGETNAME cortex_m -dap $_DAPNAME diff --git a/tcl/target/vd_riscv.cfg b/tcl/target/vd_riscv.cfg index b42b25a3a5..44a80524a6 100644 --- a/tcl/target/vd_riscv.cfg +++ b/tcl/target/vd_riscv.cfg @@ -2,17 +2,16 @@ # Cadence virtual debug interface # RISCV core -if {![info exists _HARTID]} { - set _HARTID 0x00 +if {![info exists HARTID]} { + set HARTID 0x00 } -if {![info exists _CHIPNAME]} { - set _CHIPNAME riscv +if {![info exists CHIPNAME]} { + set CHIPNAME riscv } -set _TARGETNAME $_CHIPNAME.cpu +set _TARGETNAME $CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $HARTID riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 -# prefer to use sba for system bus access -riscv set_prefer_sba on +riscv set_mem_access sysbus progbuf diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index 8933729789..e8224be043 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -86,8 +86,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core } { set _command "$_command -defer-examine" set _smp_command "$_smp_command $_TARGETNAME.$_core" } else { - # uncomment when "hawt" rtos is merged - #set _command "$_command -rtos hawt" + set _command "$_command -rtos hwthread" set _smp_command "target smp $_TARGETNAME.$_core" } @@ -105,3 +104,137 @@ proc core_up { args } { $_TARGETNAME.$core arp_examine } } + +proc BIT {n} { + return [expr {1 << $n}] +} + +set IPI_BASE 0xff300000 +set IPI_PMU_0_TRIG [expr {$IPI_BASE + 0x30000}] +set IPI_PMU_0_IER [expr {$IPI_BASE + 0x30018}] +set IPI_PMU_0 [BIT 16] + +set CRF_APB_BASE 0xfd1a0000 +set CRF_APB_RST_FPD_APU [expr {$CRF_APB_BASE + 0x104}] +set CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET [BIT 10] +set CRF_APB_RST_FPD_APU_L2_RESET [BIT 8] +set CRF_APB_RST_FPD_APU_ACPU0_RESET [BIT 0] + +set APU_BASE 0xfd5c0000 +set APU_RVBARADDR_BASE [expr {$APU_BASE + 0x40}] + +set PMU_BASE 0xffd80000 +set PMU_GLOBAL $PMU_BASE +set PMU_GLOBAL_MB_SLEEP [BIT 16] +set PMU_GLOBAL_FW_IS_PRESENT [BIT 4] +set PMU_GLOBAL_DONT_SLEEP [BIT 0] + +set PMU_RAM_BASE 0xffdc0000 + +set OCM_RAM_BASE 0xfffc0000 + +rename BIT {} + +add_help_text halt_pmu "Halt the PMU in preparation for loading new firmware.\ + This should be matched with a call to resume_pmu." +proc halt_pmu {} { + set axi $::_CHIPNAME.axi + set val [$axi read_memory $::IPI_PMU_0_IER 32 1] + $axi write_memory $::IPI_PMU_0_IER 32 [expr {$val | $::IPI_PMU_0}] + + set val [$axi read_memory $::IPI_PMU_0_TRIG 32 1] + $axi write_memory $::IPI_PMU_0_TRIG 32 [expr {$val | $::IPI_PMU_0}] + + set start [ms] + while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_MB_SLEEP)} { + if {[ms] - $start > 1000} { + error "Timed out waiting for PMU to halt" + } + } +} + +add_help_text resume_pmu "Resume the PMU after loading new firmware. This\ + should be matched with a call to halt_pmu." +proc resume_pmu {} { + set axi $::_CHIPNAME.axi + set val [$axi read_memory $::PMU_GLOBAL 32 1] + $axi write_memory $::PMU_GLOBAL 32 [expr {$val | $::PMU_GLOBAL_DONT_SLEEP}] + + set start [ms] + while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_FW_IS_PRESENT)} { + if {[ms] - $start > 5000} { + error "Timed out waiting for PMU firmware" + } + } +} + +add_usage_text release_apu {apu} +add_help_text release_apu "Release an APU from reset. It will start executing\ + at RVBARADDR. You probably want resume_apu or start_apu instead." +proc release_apu {apu} { + set axi $::_CHIPNAME.axi + set val [$axi read_memory $::CRF_APB_RST_FPD_APU 32 1] + set mask [expr { + (($::CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET | \ + $::CRF_APB_RST_FPD_APU_ACPU0_RESET) << $apu) | \ + $::CRF_APB_RST_FPD_APU_L2_RESET + }] + $axi write_memory $::CRF_APB_RST_FPD_APU 32 [expr {$val & ~$mask}] + + core_up $apu + $::_TARGETNAME.$apu aarch64 dbginit +} + +proc _rvbaraddr {apu} { + return [expr {$::APU_RVBARADDR_BASE + 8 * $apu}] +} + +add_usage_text resume_apu {apu addr} +add_help_text resume_apu "Resume an APU at a given address." +proc resume_apu {apu addr} { + set addrl [expr {$addr & 0xffffffff}] + set addrh [expr {$addr >> 32}] + $::_CHIPNAME.axi write_memory [_rvbaraddr $apu] 32 [list $addrl $addrh] + + release_apu $apu +} + +add_usage_text start_apu {apu} +add_help_text start_apu "Start an APU and put it into an infinite loop at\ + RVBARADDR. This can be convenient if you just want to halt the APU\ + (since it won't execute anything unusual)." +proc start_apu {apu} { + set axi $::_CHIPNAME.axi + foreach {addrl addrh} [$axi read_memory [_rvbaraddr $apu] 32 2] { + set addr [expr {($addrh << 32) | $addrl}] + } + # write the infinite loop instruction + $axi write_memory $addr 32 0x14000000 + + release_apu $apu +} + +add_usage_text boot_pmu {image} +add_help_text boot_pmu "Boot the PMU with a given firmware image, loading it\ + to the beginning of PMU RAM. The PMU ROM will jump to this location\ + after we resume it." +proc boot_pmu {image} { + halt_pmu + echo "Info : Loading PMU firmware $image to $::PMU_RAM_BASE" + load_image $image $::PMU_RAM_BASE + resume_pmu +} + +add_usage_text boot_apu "image \[apu=0 \[addr=$OCM_RAM_BASE\]\]" +add_help_text boot_apu "Boot an APU with a given firmware image. The default\ + address is the beginning of OCM RAM. Upon success, the default target\ + will be changed to the (running) apu." +proc boot_apu [list image {apu 0} [list addr $OCM_RAM_BASE]] { + start_apu $apu + targets $::_TARGETNAME.$apu + halt + + echo "Info : Loading APU$apu firmware $image to $addr" + load_image $image $addr + resume $addr +} diff --git a/tcl/target/xtensa-core-esp32.cfg b/tcl/target/xtensa-core-esp32.cfg new file mode 100644 index 0000000000..9a70072e45 --- /dev/null +++ b/tcl/target/xtensa-core-esp32.cfg @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x400D0000 0x330000 +xtensa xtmem irom 0x40000000 0x64F00 +xtensa xtmem iram 0x40070000 0x30000 +xtensa xtmem iram 0x400C0000 0x2000 +xtensa xtmem drom 0x3F400000 0x800000 +xtensa xtmem drom 0x3FF90000 0x10000 +xtensa xtmem dram 0x3FFAE000 0x52000 +xtensa xtmem dram 0x3FF80000 0x2000 +xtensa xtmem dram 0x3F800000 0x400000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3FF00000 0x71000 +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 1 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 173 +xtensa xtregfmt contiguous 105 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg expstate 0x03e6 +xtensa xtreg f64r_lo 0x03ea +xtensa xtreg f64r_hi 0x03eb +xtensa xtreg f64s 0x03ec +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/tcl/target/xtensa-core-esp32s2.cfg b/tcl/target/xtensa-core-esp32s2.cfg new file mode 100644 index 0000000000..b38cb1dbb5 --- /dev/null +++ b/tcl/target/xtensa-core-esp32s2.cfg @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S2 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x40080000 0x780000 +xtensa xtmem irom 0x40000000 0x20000 +xtensa xtmem iram 0x40020000 0x50000 +xtensa xtmem iram 0x40070000 0x2000 +xtensa xtmem drom 0x3F000000 0x400000 +xtensa xtmem drom 0x3F4D3FFC 0xAAC004 +xtensa xtmem drom 0x3FFA0000 0x10000 +xtensa xtmem dram 0x3FFB0000 0x50000 +xtensa xtmem dram 0x3FF9E000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3F500000 0xA80000 +xtensa xtmem dram 0x3F400000 0xD3FFC +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 0 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 171 +xtensa xtregfmt contiguous 73 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg gpio_out 0x0300 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg pwrctl 0x2014 +xtensa xtreg pwrstat 0x2015 +xtensa xtreg eristat 0x2016 +xtensa xtreg cs_itctrl 0x2017 +xtensa xtreg cs_claimset 0x2018 +xtensa xtreg cs_claimclr 0x2019 +xtensa xtreg cs_lockaccess 0x201a +xtensa xtreg cs_lockstatus 0x201b +xtensa xtreg cs_authstatus 0x201c +xtensa xtreg fault_info 0x202b +xtensa xtreg trax_id 0x202c +xtensa xtreg trax_control 0x202d +xtensa xtreg trax_status 0x202e +xtensa xtreg trax_data 0x202f +xtensa xtreg trax_address 0x2030 +xtensa xtreg trax_pctrigger 0x2031 +xtensa xtreg trax_pcmatch 0x2032 +xtensa xtreg trax_delay 0x2033 +xtensa xtreg trax_memstart 0x2034 +xtensa xtreg trax_memend 0x2035 +xtensa xtreg pmg 0x2043 +xtensa xtreg pmpc 0x2044 +xtensa xtreg pm0 0x2045 +xtensa xtreg pm1 0x2046 +xtensa xtreg pmctrl0 0x2047 +xtensa xtreg pmctrl1 0x2048 +xtensa xtreg pmstat0 0x2049 +xtensa xtreg pmstat1 0x204a +xtensa xtreg ocdid 0x204b +xtensa xtreg ocd_dcrclr 0x204c +xtensa xtreg ocd_dcrset 0x204d +xtensa xtreg ocd_dsr 0x204e +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/tcl/target/xtensa-core-esp32s3.cfg b/tcl/target/xtensa-core-esp32s3.cfg new file mode 100644 index 0000000000..b3f20e39d5 --- /dev/null +++ b/tcl/target/xtensa-core-esp32s3.cfg @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S3 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options + +# Memory Options +xtensa xtmem irom 0x42000000 0x2000000 +xtensa xtmem irom 0x40000000 0x60000 +xtensa xtmem iram 0x40370000 0x70000 +xtensa xtmem iram 0x600FE000 0x2000 +xtensa xtmem drom 0x3C000000 0x1000000 +xtensa xtmem drom 0x3FF00000 0x20000 +xtensa xtmem dram 0x3FC88000 0x78000 +xtensa xtmem dram 0x600FE000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x60000000 0x10000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 0 +xtensa xtopt perfcount 2 + + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 228 +xtensa xtregfmt contiguous 128 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg gpio_out 0x030c +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 +xtensa xtreg accx_0 0x0300 +xtensa xtreg accx_1 0x0301 +xtensa xtreg qacc_h_0 0x0302 +xtensa xtreg qacc_h_1 0x0303 +xtensa xtreg qacc_h_2 0x0304 +xtensa xtreg qacc_h_3 0x0305 +xtensa xtreg qacc_h_4 0x0306 +xtensa xtreg qacc_l_0 0x0307 +xtensa xtreg qacc_l_1 0x0308 +xtensa xtreg qacc_l_2 0x0309 +xtensa xtreg qacc_l_3 0x030a +xtensa xtreg qacc_l_4 0x030b +xtensa xtreg sar_byte 0x030d +xtensa xtreg fft_bit_width 0x030e +xtensa xtreg ua_state_0 0x030f +xtensa xtreg ua_state_1 0x0310 +xtensa xtreg ua_state_2 0x0311 +xtensa xtreg ua_state_3 0x0312 +xtensa xtreg q0 0x1008 +xtensa xtreg q1 0x1009 +xtensa xtreg q2 0x100a +xtensa xtreg q3 0x100b +xtensa xtreg q4 0x100c +xtensa xtreg q5 0x100d +xtensa xtreg q6 0x100e +xtensa xtreg q7 0x100f +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg pwrctl 0x2028 +xtensa xtreg pwrstat 0x2029 +xtensa xtreg eristat 0x202a +xtensa xtreg cs_itctrl 0x202b +xtensa xtreg cs_claimset 0x202c +xtensa xtreg cs_claimclr 0x202d +xtensa xtreg cs_lockaccess 0x202e +xtensa xtreg cs_lockstatus 0x202f +xtensa xtreg cs_authstatus 0x2030 +xtensa xtreg fault_info 0x203f +xtensa xtreg trax_id 0x2040 +xtensa xtreg trax_control 0x2041 +xtensa xtreg trax_status 0x2042 +xtensa xtreg trax_data 0x2043 +xtensa xtreg trax_address 0x2044 +xtensa xtreg trax_pctrigger 0x2045 +xtensa xtreg trax_pcmatch 0x2046 +xtensa xtreg trax_delay 0x2047 +xtensa xtreg trax_memstart 0x2048 +xtensa xtreg trax_memend 0x2049 +xtensa xtreg pmg 0x2057 +xtensa xtreg pmpc 0x2058 +xtensa xtreg pm0 0x2059 +xtensa xtreg pm1 0x205a +xtensa xtreg pmctrl0 0x205b +xtensa xtreg pmctrl1 0x205c +xtensa xtreg pmstat0 0x205d +xtensa xtreg pmstat1 0x205e +xtensa xtreg ocdid 0x205f +xtensa xtreg ocd_dcrclr 0x2060 +xtensa xtreg ocd_dcrset 0x2061 +xtensa xtreg ocd_dsr 0x2062 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/tcl/target/xtensa-core-nxp_rt600.cfg b/tcl/target/xtensa-core-nxp_rt600.cfg new file mode 100644 index 0000000000..ca7fd68480 --- /dev/null +++ b/tcl/target/xtensa-core-nxp_rt600.cfg @@ -0,0 +1,255 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target + + +# Core instance default definition +if { [info exists XTNAME] } { + set _XTNAME $XTNAME +} else { + set _XTNAME xtensa.cpu +} + + +# Core definition and ABI +$_XTNAME xtensa xtdef LX +$_XTNAME xtensa xtopt arnum 32 +$_XTNAME xtensa xtopt windowed 1 + + +# Exception/Interrupt Options +$_XTNAME xtensa xtopt exceptions 1 +$_XTNAME xtensa xtopt hipriints 1 +$_XTNAME xtensa xtopt intlevels 4 +$_XTNAME xtensa xtopt excmlevel 2 + + +# Cache Options +$_XTNAME xtensa xtmem icache 256 32768 4 +$_XTNAME xtensa xtmem dcache 256 65536 4 1 + + +# Memory Options +$_XTNAME xtensa xtmem iram 0x24020000 65536 +$_XTNAME xtensa xtmem dram 0x24000000 65536 +$_XTNAME xtensa xtmem sram 0x00000000 603979776 + + +# Memory Protection/Translation Options + + +# Debug Options +$_XTNAME xtensa xtopt debuglevel 4 +$_XTNAME xtensa xtopt ibreaknum 2 +$_XTNAME xtensa xtopt dbreaknum 2 + + +# Core Registers +$_XTNAME xtensa xtregs 208 +$_XTNAME xtensa xtreg pc 0x0020 +$_XTNAME xtensa xtreg ar0 0x0100 +$_XTNAME xtensa xtreg ar1 0x0101 +$_XTNAME xtensa xtreg ar2 0x0102 +$_XTNAME xtensa xtreg ar3 0x0103 +$_XTNAME xtensa xtreg ar4 0x0104 +$_XTNAME xtensa xtreg ar5 0x0105 +$_XTNAME xtensa xtreg ar6 0x0106 +$_XTNAME xtensa xtreg ar7 0x0107 +$_XTNAME xtensa xtreg ar8 0x0108 +$_XTNAME xtensa xtreg ar9 0x0109 +$_XTNAME xtensa xtreg ar10 0x010a +$_XTNAME xtensa xtreg ar11 0x010b +$_XTNAME xtensa xtreg ar12 0x010c +$_XTNAME xtensa xtreg ar13 0x010d +$_XTNAME xtensa xtreg ar14 0x010e +$_XTNAME xtensa xtreg ar15 0x010f +$_XTNAME xtensa xtreg ar16 0x0110 +$_XTNAME xtensa xtreg ar17 0x0111 +$_XTNAME xtensa xtreg ar18 0x0112 +$_XTNAME xtensa xtreg ar19 0x0113 +$_XTNAME xtensa xtreg ar20 0x0114 +$_XTNAME xtensa xtreg ar21 0x0115 +$_XTNAME xtensa xtreg ar22 0x0116 +$_XTNAME xtensa xtreg ar23 0x0117 +$_XTNAME xtensa xtreg ar24 0x0118 +$_XTNAME xtensa xtreg ar25 0x0119 +$_XTNAME xtensa xtreg ar26 0x011a +$_XTNAME xtensa xtreg ar27 0x011b +$_XTNAME xtensa xtreg ar28 0x011c +$_XTNAME xtensa xtreg ar29 0x011d +$_XTNAME xtensa xtreg ar30 0x011e +$_XTNAME xtensa xtreg ar31 0x011f +$_XTNAME xtensa xtreg lbeg 0x0200 +$_XTNAME xtensa xtreg lend 0x0201 +$_XTNAME xtensa xtreg lcount 0x0202 +$_XTNAME xtensa xtreg sar 0x0203 +$_XTNAME xtensa xtreg prefctl 0x0228 +$_XTNAME xtensa xtreg windowbase 0x0248 +$_XTNAME xtensa xtreg windowstart 0x0249 +$_XTNAME xtensa xtreg configid0 0x02b0 +$_XTNAME xtensa xtreg configid1 0x02d0 +$_XTNAME xtensa xtreg ps 0x02e6 +$_XTNAME xtensa xtreg threadptr 0x03e7 +$_XTNAME xtensa xtreg br 0x0204 +$_XTNAME xtensa xtreg scompare1 0x020c +$_XTNAME xtensa xtreg acclo 0x0210 +$_XTNAME xtensa xtreg acchi 0x0211 +$_XTNAME xtensa xtreg m0 0x0220 +$_XTNAME xtensa xtreg m1 0x0221 +$_XTNAME xtensa xtreg m2 0x0222 +$_XTNAME xtensa xtreg m3 0x0223 +$_XTNAME xtensa xtreg expstate 0x03e6 +$_XTNAME xtensa xtreg f64r_lo 0x03ea +$_XTNAME xtensa xtreg f64r_hi 0x03eb +$_XTNAME xtensa xtreg f64s 0x03ec +$_XTNAME xtensa xtreg ae_ovf_sar 0x03f0 +$_XTNAME xtensa xtreg ae_bithead 0x03f1 +$_XTNAME xtensa xtreg ae_ts_fts_bu_bp 0x03f2 +$_XTNAME xtensa xtreg ae_cw_sd_no 0x03f3 +$_XTNAME xtensa xtreg ae_cbegin0 0x03f6 +$_XTNAME xtensa xtreg ae_cend0 0x03f7 +$_XTNAME xtensa xtreg ae_cbegin1 0x03f8 +$_XTNAME xtensa xtreg ae_cend1 0x03f9 +$_XTNAME xtensa xtreg aed0 0x1010 +$_XTNAME xtensa xtreg aed1 0x1011 +$_XTNAME xtensa xtreg aed2 0x1012 +$_XTNAME xtensa xtreg aed3 0x1013 +$_XTNAME xtensa xtreg aed4 0x1014 +$_XTNAME xtensa xtreg aed5 0x1015 +$_XTNAME xtensa xtreg aed6 0x1016 +$_XTNAME xtensa xtreg aed7 0x1017 +$_XTNAME xtensa xtreg aed8 0x1018 +$_XTNAME xtensa xtreg aed9 0x1019 +$_XTNAME xtensa xtreg aed10 0x101a +$_XTNAME xtensa xtreg aed11 0x101b +$_XTNAME xtensa xtreg aed12 0x101c +$_XTNAME xtensa xtreg aed13 0x101d +$_XTNAME xtensa xtreg aed14 0x101e +$_XTNAME xtensa xtreg aed15 0x101f +$_XTNAME xtensa xtreg u0 0x1020 +$_XTNAME xtensa xtreg u1 0x1021 +$_XTNAME xtensa xtreg u2 0x1022 +$_XTNAME xtensa xtreg u3 0x1023 +$_XTNAME xtensa xtreg aep0 0x1024 +$_XTNAME xtensa xtreg aep1 0x1025 +$_XTNAME xtensa xtreg aep2 0x1026 +$_XTNAME xtensa xtreg aep3 0x1027 +$_XTNAME xtensa xtreg fcr_fsr 0x1029 +$_XTNAME xtensa xtreg mmid 0x0259 +$_XTNAME xtensa xtreg ibreakenable 0x0260 +$_XTNAME xtensa xtreg memctl 0x0261 +$_XTNAME xtensa xtreg atomctl 0x0263 +$_XTNAME xtensa xtreg ddr 0x0268 +$_XTNAME xtensa xtreg ibreaka0 0x0280 +$_XTNAME xtensa xtreg ibreaka1 0x0281 +$_XTNAME xtensa xtreg dbreaka0 0x0290 +$_XTNAME xtensa xtreg dbreaka1 0x0291 +$_XTNAME xtensa xtreg dbreakc0 0x02a0 +$_XTNAME xtensa xtreg dbreakc1 0x02a1 +$_XTNAME xtensa xtreg epc1 0x02b1 +$_XTNAME xtensa xtreg epc2 0x02b2 +$_XTNAME xtensa xtreg epc3 0x02b3 +$_XTNAME xtensa xtreg epc4 0x02b4 +$_XTNAME xtensa xtreg epc5 0x02b5 +$_XTNAME xtensa xtreg depc 0x02c0 +$_XTNAME xtensa xtreg eps2 0x02c2 +$_XTNAME xtensa xtreg eps3 0x02c3 +$_XTNAME xtensa xtreg eps4 0x02c4 +$_XTNAME xtensa xtreg eps5 0x02c5 +$_XTNAME xtensa xtreg excsave1 0x02d1 +$_XTNAME xtensa xtreg excsave2 0x02d2 +$_XTNAME xtensa xtreg excsave3 0x02d3 +$_XTNAME xtensa xtreg excsave4 0x02d4 +$_XTNAME xtensa xtreg excsave5 0x02d5 +$_XTNAME xtensa xtreg cpenable 0x02e0 +$_XTNAME xtensa xtreg interrupt 0x02e2 +$_XTNAME xtensa xtreg intset 0x02e2 +$_XTNAME xtensa xtreg intclear 0x02e3 +$_XTNAME xtensa xtreg intenable 0x02e4 +$_XTNAME xtensa xtreg vecbase 0x02e7 +$_XTNAME xtensa xtreg exccause 0x02e8 +$_XTNAME xtensa xtreg debugcause 0x02e9 +$_XTNAME xtensa xtreg ccount 0x02ea +$_XTNAME xtensa xtreg prid 0x02eb +$_XTNAME xtensa xtreg icount 0x02ec +$_XTNAME xtensa xtreg icountlevel 0x02ed +$_XTNAME xtensa xtreg excvaddr 0x02ee +$_XTNAME xtensa xtreg ccompare0 0x02f0 +$_XTNAME xtensa xtreg ccompare1 0x02f1 +$_XTNAME xtensa xtreg misc0 0x02f4 +$_XTNAME xtensa xtreg misc1 0x02f5 +$_XTNAME xtensa xtreg pwrctl 0x2024 +$_XTNAME xtensa xtreg pwrstat 0x2025 +$_XTNAME xtensa xtreg eristat 0x2026 +$_XTNAME xtensa xtreg cs_itctrl 0x2027 +$_XTNAME xtensa xtreg cs_claimset 0x2028 +$_XTNAME xtensa xtreg cs_claimclr 0x2029 +$_XTNAME xtensa xtreg cs_lockaccess 0x202a +$_XTNAME xtensa xtreg cs_lockstatus 0x202b +$_XTNAME xtensa xtreg cs_authstatus 0x202c +$_XTNAME xtensa xtreg pmg 0x203b +$_XTNAME xtensa xtreg pmpc 0x203c +$_XTNAME xtensa xtreg pm0 0x203d +$_XTNAME xtensa xtreg pm1 0x203e +$_XTNAME xtensa xtreg pmctrl0 0x203f +$_XTNAME xtensa xtreg pmctrl1 0x2040 +$_XTNAME xtensa xtreg pmstat0 0x2041 +$_XTNAME xtensa xtreg pmstat1 0x2042 +$_XTNAME xtensa xtreg ocdid 0x2043 +$_XTNAME xtensa xtreg ocd_dcrclr 0x2044 +$_XTNAME xtensa xtreg ocd_dcrset 0x2045 +$_XTNAME xtensa xtreg ocd_dsr 0x2046 +$_XTNAME xtensa xtreg a0 0x0000 +$_XTNAME xtensa xtreg a1 0x0001 +$_XTNAME xtensa xtreg a2 0x0002 +$_XTNAME xtensa xtreg a3 0x0003 +$_XTNAME xtensa xtreg a4 0x0004 +$_XTNAME xtensa xtreg a5 0x0005 +$_XTNAME xtensa xtreg a6 0x0006 +$_XTNAME xtensa xtreg a7 0x0007 +$_XTNAME xtensa xtreg a8 0x0008 +$_XTNAME xtensa xtreg a9 0x0009 +$_XTNAME xtensa xtreg a10 0x000a +$_XTNAME xtensa xtreg a11 0x000b +$_XTNAME xtensa xtreg a12 0x000c +$_XTNAME xtensa xtreg a13 0x000d +$_XTNAME xtensa xtreg a14 0x000e +$_XTNAME xtensa xtreg a15 0x000f +$_XTNAME xtensa xtreg b0 0x0010 +$_XTNAME xtensa xtreg b1 0x0011 +$_XTNAME xtensa xtreg b2 0x0012 +$_XTNAME xtensa xtreg b3 0x0013 +$_XTNAME xtensa xtreg b4 0x0014 +$_XTNAME xtensa xtreg b5 0x0015 +$_XTNAME xtensa xtreg b6 0x0016 +$_XTNAME xtensa xtreg b7 0x0017 +$_XTNAME xtensa xtreg b8 0x0018 +$_XTNAME xtensa xtreg b9 0x0019 +$_XTNAME xtensa xtreg b10 0x001a +$_XTNAME xtensa xtreg b11 0x001b +$_XTNAME xtensa xtreg b12 0x001c +$_XTNAME xtensa xtreg b13 0x001d +$_XTNAME xtensa xtreg b14 0x001e +$_XTNAME xtensa xtreg b15 0x001f +$_XTNAME xtensa xtreg psintlevel 0x2006 +$_XTNAME xtensa xtreg psum 0x2007 +$_XTNAME xtensa xtreg pswoe 0x2008 +$_XTNAME xtensa xtreg psexcm 0x2009 +$_XTNAME xtensa xtreg pscallinc 0x200a +$_XTNAME xtensa xtreg psowb 0x200b +$_XTNAME xtensa xtreg acc 0x200c +$_XTNAME xtensa xtreg dbnum 0x2011 +$_XTNAME xtensa xtreg ae_overflow 0x2014 +$_XTNAME xtensa xtreg ae_sar 0x2015 +$_XTNAME xtensa xtreg ae_cwrap 0x2016 +$_XTNAME xtensa xtreg ae_bitptr 0x2017 +$_XTNAME xtensa xtreg ae_bitsused 0x2018 +$_XTNAME xtensa xtreg ae_tablesize 0x2019 +$_XTNAME xtensa xtreg ae_first_ts 0x201a +$_XTNAME xtensa xtreg ae_nextoffset 0x201b +$_XTNAME xtensa xtreg ae_searchdone 0x201c +$_XTNAME xtensa xtreg roundmode 0x201d +$_XTNAME xtensa xtreg invalidflag 0x201e +$_XTNAME xtensa xtreg divzeroflag 0x201f +$_XTNAME xtensa xtreg overflowflag 0x2020 +$_XTNAME xtensa xtreg underflowflag 0x2021 +$_XTNAME xtensa xtreg inexactflag 0x2022 diff --git a/tcl/target/xtensa-core-xt8.cfg b/tcl/target/xtensa-core-xt8.cfg new file mode 100644 index 0000000000..523dc74e1f --- /dev/null +++ b/tcl/target/xtensa-core-xt8.cfg @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa xt8 target + + +# Core instance default definition +if { [info exists XTNAME] } { + set _XTNAME $XTNAME +} else { + set _XTNAME xtensa +} + + +# Core definition and ABI +$_XTNAME xtensa xtdef LX +$_XTNAME xtensa xtopt arnum 32 +$_XTNAME xtensa xtopt windowed 1 + + +# Exception/Interrupt Options +$_XTNAME xtensa xtopt exceptions 1 +$_XTNAME xtensa xtopt hipriints 1 +$_XTNAME xtensa xtopt intlevels 3 +$_XTNAME xtensa xtopt excmlevel 1 + + +# Cache Options +$_XTNAME xtensa xtmem icache 16 1024 1 +$_XTNAME xtensa xtmem dcache 16 1024 1 1 + + +# Memory Options +$_XTNAME xtensa xtmem iram 0x40000000 1048576 +$_XTNAME xtensa xtmem dram 0x3ff00000 262144 +$_XTNAME xtensa xtmem srom 0x50000000 131072 +$_XTNAME xtensa xtmem sram 0x60000000 4194304 + + +# Memory Protection/Translation Options + + +# Debug Options +$_XTNAME xtensa xtopt debuglevel 3 +$_XTNAME xtensa xtopt ibreaknum 2 +$_XTNAME xtensa xtopt dbreaknum 2 + + +# Core Registers +$_XTNAME xtensa xtregs 127 +$_XTNAME xtensa xtreg a0 0x0000 +$_XTNAME xtensa xtreg a1 0x0001 +$_XTNAME xtensa xtreg a2 0x0002 +$_XTNAME xtensa xtreg a3 0x0003 +$_XTNAME xtensa xtreg a4 0x0004 +$_XTNAME xtensa xtreg a5 0x0005 +$_XTNAME xtensa xtreg a6 0x0006 +$_XTNAME xtensa xtreg a7 0x0007 +$_XTNAME xtensa xtreg a8 0x0008 +$_XTNAME xtensa xtreg a9 0x0009 +$_XTNAME xtensa xtreg a10 0x000a +$_XTNAME xtensa xtreg a11 0x000b +$_XTNAME xtensa xtreg a12 0x000c +$_XTNAME xtensa xtreg a13 0x000d +$_XTNAME xtensa xtreg a14 0x000e +$_XTNAME xtensa xtreg a15 0x000f +$_XTNAME xtensa xtreg pc 0x0020 +$_XTNAME xtensa xtreg ar0 0x0100 +$_XTNAME xtensa xtreg ar1 0x0101 +$_XTNAME xtensa xtreg ar2 0x0102 +$_XTNAME xtensa xtreg ar3 0x0103 +$_XTNAME xtensa xtreg ar4 0x0104 +$_XTNAME xtensa xtreg ar5 0x0105 +$_XTNAME xtensa xtreg ar6 0x0106 +$_XTNAME xtensa xtreg ar7 0x0107 +$_XTNAME xtensa xtreg ar8 0x0108 +$_XTNAME xtensa xtreg ar9 0x0109 +$_XTNAME xtensa xtreg ar10 0x010a +$_XTNAME xtensa xtreg ar11 0x010b +$_XTNAME xtensa xtreg ar12 0x010c +$_XTNAME xtensa xtreg ar13 0x010d +$_XTNAME xtensa xtreg ar14 0x010e +$_XTNAME xtensa xtreg ar15 0x010f +$_XTNAME xtensa xtreg ar16 0x0110 +$_XTNAME xtensa xtreg ar17 0x0111 +$_XTNAME xtensa xtreg ar18 0x0112 +$_XTNAME xtensa xtreg ar19 0x0113 +$_XTNAME xtensa xtreg ar20 0x0114 +$_XTNAME xtensa xtreg ar21 0x0115 +$_XTNAME xtensa xtreg ar22 0x0116 +$_XTNAME xtensa xtreg ar23 0x0117 +$_XTNAME xtensa xtreg ar24 0x0118 +$_XTNAME xtensa xtreg ar25 0x0119 +$_XTNAME xtensa xtreg ar26 0x011a +$_XTNAME xtensa xtreg ar27 0x011b +$_XTNAME xtensa xtreg ar28 0x011c +$_XTNAME xtensa xtreg ar29 0x011d +$_XTNAME xtensa xtreg ar30 0x011e +$_XTNAME xtensa xtreg ar31 0x011f +$_XTNAME xtensa xtreg lbeg 0x0200 +$_XTNAME xtensa xtreg lend 0x0201 +$_XTNAME xtensa xtreg lcount 0x0202 +$_XTNAME xtensa xtreg sar 0x0203 +$_XTNAME xtensa xtreg windowbase 0x0248 +$_XTNAME xtensa xtreg windowstart 0x0249 +$_XTNAME xtensa xtreg configid0 0x02b0 +$_XTNAME xtensa xtreg configid1 0x02d0 +$_XTNAME xtensa xtreg ps 0x02e6 +$_XTNAME xtensa xtreg expstate 0x03e6 +$_XTNAME xtensa xtreg mmid 0x0259 +$_XTNAME xtensa xtreg ibreakenable 0x0260 +$_XTNAME xtensa xtreg ddr 0x0268 +$_XTNAME xtensa xtreg ibreaka0 0x0280 +$_XTNAME xtensa xtreg ibreaka1 0x0281 +$_XTNAME xtensa xtreg dbreaka0 0x0290 +$_XTNAME xtensa xtreg dbreaka1 0x0291 +$_XTNAME xtensa xtreg dbreakc0 0x02a0 +$_XTNAME xtensa xtreg dbreakc1 0x02a1 +$_XTNAME xtensa xtreg epc1 0x02b1 +$_XTNAME xtensa xtreg epc2 0x02b2 +$_XTNAME xtensa xtreg epc3 0x02b3 +$_XTNAME xtensa xtreg depc 0x02c0 +$_XTNAME xtensa xtreg eps2 0x02c2 +$_XTNAME xtensa xtreg eps3 0x02c3 +$_XTNAME xtensa xtreg excsave1 0x02d1 +$_XTNAME xtensa xtreg excsave2 0x02d2 +$_XTNAME xtensa xtreg excsave3 0x02d3 +$_XTNAME xtensa xtreg interrupt 0x02e2 +$_XTNAME xtensa xtreg intset 0x02e2 +$_XTNAME xtensa xtreg intclear 0x02e3 +$_XTNAME xtensa xtreg intenable 0x02e4 +$_XTNAME xtensa xtreg exccause 0x02e8 +$_XTNAME xtensa xtreg debugcause 0x02e9 +$_XTNAME xtensa xtreg ccount 0x02ea +$_XTNAME xtensa xtreg icount 0x02ec +$_XTNAME xtensa xtreg icountlevel 0x02ed +$_XTNAME xtensa xtreg excvaddr 0x02ee +$_XTNAME xtensa xtreg ccompare0 0x02f0 +$_XTNAME xtensa xtreg ccompare1 0x02f1 +$_XTNAME xtensa xtreg pwrctl 0x200f +$_XTNAME xtensa xtreg pwrstat 0x2010 +$_XTNAME xtensa xtreg eristat 0x2011 +$_XTNAME xtensa xtreg cs_itctrl 0x2012 +$_XTNAME xtensa xtreg cs_claimset 0x2013 +$_XTNAME xtensa xtreg cs_claimclr 0x2014 +$_XTNAME xtensa xtreg cs_lockaccess 0x2015 +$_XTNAME xtensa xtreg cs_lockstatus 0x2016 +$_XTNAME xtensa xtreg cs_authstatus 0x2017 +$_XTNAME xtensa xtreg fault_info 0x2026 +$_XTNAME xtensa xtreg trax_id 0x2027 +$_XTNAME xtensa xtreg trax_control 0x2028 +$_XTNAME xtensa xtreg trax_status 0x2029 +$_XTNAME xtensa xtreg trax_data 0x202a +$_XTNAME xtensa xtreg trax_address 0x202b +$_XTNAME xtensa xtreg trax_pctrigger 0x202c +$_XTNAME xtensa xtreg trax_pcmatch 0x202d +$_XTNAME xtensa xtreg trax_delay 0x202e +$_XTNAME xtensa xtreg trax_memstart 0x202f +$_XTNAME xtensa xtreg trax_memend 0x2030 +$_XTNAME xtensa xtreg pmg 0x203e +$_XTNAME xtensa xtreg pmpc 0x203f +$_XTNAME xtensa xtreg pm0 0x2040 +$_XTNAME xtensa xtreg pm1 0x2041 +$_XTNAME xtensa xtreg pmctrl0 0x2042 +$_XTNAME xtensa xtreg pmctrl1 0x2043 +$_XTNAME xtensa xtreg pmstat0 0x2044 +$_XTNAME xtensa xtreg pmstat1 0x2045 +$_XTNAME xtensa xtreg ocdid 0x2046 +$_XTNAME xtensa xtreg ocd_dcrclr 0x2047 +$_XTNAME xtensa xtreg ocd_dcrset 0x2048 +$_XTNAME xtensa xtreg ocd_dsr 0x2049 +$_XTNAME xtensa xtreg psintlevel 0x2003 +$_XTNAME xtensa xtreg psum 0x2004 +$_XTNAME xtensa xtreg pswoe 0x2005 +$_XTNAME xtensa xtreg psexcm 0x2006 +$_XTNAME xtensa xtreg pscallinc 0x2007 +$_XTNAME xtensa xtreg psowb 0x2008 diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg new file mode 100644 index 0000000000..c277673e47 --- /dev/null +++ b/tcl/target/xtensa.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Target Support for Xtensa Processors +# + +set xtensa_ids { 0x120034e5 0x120134e5 + 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5 + 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5 + 0x20b034e5 0x20b33ac5 0x20b33ac7 } +set expected_xtensa_ids {} +foreach i $xtensa_ids { + lappend expected_xtensa_ids -expected-id $i +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xtensa +} + +if { [info exists CPUTAPID] } { + set _CPUTAPARGLIST "-expected-id $CPUTAPID" +} else { + set _CPUTAPARGLIST [join $expected_xtensa_ids] +} + +if { [info exists XTENSA_NUM_CORES] } { + set _XTENSA_NUM_CORES $XTENSA_NUM_CORES +} else { + set _XTENSA_NUM_CORES 1 +} + +set _TARGETNAME $_CHIPNAME +set _CPU0NAME cpu +set _TAPNAME $_CHIPNAME.$_CPU0NAME + +if { [info exists XTENSA_DAP] } { + source [find target/swj-dp.tcl] + # SWD mode ignores the -irlen parameter + eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + + set _TARGETNAME $_CHIPNAME.cpu + if { [info exists XTENSA_DAP_BASE] } { + # Specify fixed offset for accessing XDM via APB behind a DAP interface + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE + } else { + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap + } +} elseif { $_XTENSA_NUM_CORES > 1 } { + # JTAG direct (without DAP) + for {set i 0} {$i < $_XTENSA_NUM_CORES} {incr i} { + set _LCPUNAME $_CPU0NAME$i + set _LTAPNAME $_CHIPNAME.$_LCPUNAME + eval jtag newtap $_CHIPNAME $_LCPUNAME -irlen 5 $_CPUTAPARGLIST + target create $_LTAPNAME xtensa -chain-position $_LTAPNAME -coreid $i + + $_LTAPNAME configure -event reset-assert-post { soft_reset_halt } + } +} else { + # JTAG direct (without DAP) - for legacy xtensa-config-XXX.cfg format + eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST + target create $_TARGETNAME xtensa -chain-position $_TAPNAME +} + +if { $_XTENSA_NUM_CORES == 1 } { + # DAP and single-core legacy JTAG + $_TARGETNAME configure -event reset-assert-post { soft_reset_halt } +} + +gdb report_register_access_error enable diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg index 0272587c1e..5a88b6e9d5 100644 --- a/tcl/target/zynq_7000.cfg +++ b/tcl/target/zynq_7000.cfg @@ -1,18 +1,34 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# # Xilinx Zynq-7000 All Programmable SoC # # http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm +# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip # +# 0x03736093 XQ7Z100 XC7Z100I XC7Z100 +# 0x03731093 XQ7Z045 XC7Z045I XC7Z045 +# 0x0372c093 XQ7Z030 XC7Z030I XC7Z030 XA7Z030 +# 0x03727093 XQ7Z020 XC7Z020I XC7Z020 XA7Z020 +# 0x03732093 XC7Z035I XC7Z035 +# 0x0373b093 XC7Z015I XC7Z015 +# 0x03728093 XC7Z014S +# 0x0373c093 XC7Z012S +# 0x03722093 XC7Z010I XC7Z010 XA7Z010 +# 0x03723093 XC7Z007S set _CHIPNAME zynq set _TARGETNAME $_CHIPNAME.cpu -jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \ - -expected-id 0x23727093 \ - -expected-id 0x13722093 \ +jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \ + -expected-id 0x03723093 \ + -expected-id 0x03722093 \ + -expected-id 0x0373c093 \ + -expected-id 0x03728093 \ + -expected-id 0x0373B093 \ + -expected-id 0x03732093 \ -expected-id 0x03727093 \ + -expected-id 0x0372C093 \ + -expected-id 0x03731093 \ -expected-id 0x03736093 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 @@ -30,7 +46,8 @@ adapter speed 1000 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" -pld device virtex2 zynq_pl.bs 1 +pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart +virtex2 set_user_codes zynq_pl.pld 0x02 0x03 0x22 0x23 set XC7_JSHUTDOWN 0x0d set XC7_JPROGRAM 0x0b @@ -38,6 +55,7 @@ set XC7_JSTART 0x0c set XC7_BYPASS 0x3f proc zynqpl_program {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'" global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS irscan $tap $XC7_JSHUTDOWN irscan $tap $XC7_JPROGRAM diff --git a/tcl/tools/test_cpu_speed.tcl b/tcl/tools/test_cpu_speed.tcl index cef2bbbd73..f1a3fb30e0 100644 --- a/tcl/tools/test_cpu_speed.tcl +++ b/tcl/tools/test_cpu_speed.tcl @@ -18,7 +18,7 @@ proc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } { halt # Backup registers and memory. - set backup_regs [get_reg -force {pc r0 xPSR}] + set backup_regs [get_reg -force {pc r0 xpsr}] set backup_mem [read_memory $address 16 3] # We place the following code at the given address to measure the diff --git a/testing/Makefile.am b/testing/Makefile.am new file mode 100644 index 0000000000..22778a4c21 --- /dev/null +++ b/testing/Makefile.am @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +SUBDIRS = tcl_commands +DIST_SUBDIRS = tcl_commands diff --git a/testing/tcl_commands/Makefile.am b/testing/tcl_commands/Makefile.am new file mode 100644 index 0000000000..fe8d150707 --- /dev/null +++ b/testing/tcl_commands/Makefile.am @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +TESTS = + +if DUMMY +TESTS += \ + test-target-create-command.cfg \ + test-target-configure-cget-command.cfg +endif + +EXTRA_DIST = utils.tcl $(TESTS) + +TEST_EXTENSIONS = .cfg +CFG_LOG_COMPILER = $(top_builddir)/src/openocd +AM_CFG_LOG_FLAGS = -f $(abs_srcdir)/utils.tcl -f diff --git a/testing/tcl_commands/test-target-configure-cget-command.cfg b/testing/tcl_commands/test-target-configure-cget-command.cfg new file mode 100644 index 0000000000..2d546c83da --- /dev/null +++ b/testing/tcl_commands/test-target-configure-cget-command.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +namespace import testing_helpers::* +namespace import configure_testing::* + +adapter driver dummy +jtag newtap tap cpu -irlen 5 + +{*}[target_create_first_args] {*}[simple_configure_options] + +set target_name [lindex [target names] 0] + +check_matches testee {$target_name cget -type} + +foreach {opt arg} [simple_configure_options] { + check_syntax_err {$target_name cget $opt extra_arg} + check_matches [dict get [simple_configure_options] $opt] \ + {$target_name cget $opt} +} + +check_error_matches .*-event.* {$target_name cget -event} +$target_name cget -event examine-start +check_syntax_err {$target_name cget -event examine-start extra_arg} + +check_syntax_err {$target_name configure} + +foreach {opt arg} [simple_configure_options] { + $target_name configure $opt [$target_name cget $opt] +} + +shutdown diff --git a/testing/tcl_commands/test-target-create-command.cfg b/testing/tcl_commands/test-target-create-command.cfg new file mode 100644 index 0000000000..11264316c3 --- /dev/null +++ b/testing/tcl_commands/test-target-create-command.cfg @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +namespace import testing_helpers::* +namespace import configure_testing::* + +adapter driver dummy +jtag newtap tap cpu -irlen 5 + +check_syntax_err {target create} +check_syntax_err {target create} +check_syntax_err {target create test.target} +check_error_matches -chain-position {target create test.target testee} + +{*}[target_create_first_args] {*}[simple_configure_options] + +foreach {opt arg} [simple_configure_options] { + check_error_matches ".*${opt}.*" {{*}[target_create_first_args] $opt} +} + +foreach {opt1 arg1} [simple_configure_options] { + foreach {opt2 arg2} [simple_configure_options] { + check_error_matches ".*${opt2}.*" \ + {{*}[target_create_first_args] $opt1 $arg1 $opt2} + check_error_matches {} \ + {{*}[target_create_first_args] $opt1 $opt2 $arg2} + } +} + +check_error_matches ".*-type.*" \ + {{*}[target_create_first_args] -type} + +check_error_matches ".*-type.*" \ + {{*}[target_create_first_args] {*}[simple_configure_options] -type} + +check_error_matches {.*-event [^ ]+ .*} \ + {{*}[target_create_first_args] -event} + +check_error_matches {.*not-an-event.*} \ + {{*}[target_create_first_args] -event not-an-event} + +check_error_matches {.*-event examine-start [^ ]+.*} \ + {{*}[target_create_first_args] -event examine-start} + +{*}[target_create_first_args] {*}[simple_configure_options] \ + -event examine-start body +{*}[target_create_first_args] {*}[simple_configure_options] \ + -event examine-start body \ + -event examine-end another-body \ + -event examine-start new-body +{*}[target_create_first_args] -event examine-start body {*}[simple_configure_options] + +{*}[target_create_first_args] {*}[simple_configure_options] -defer-examine + +shutdown diff --git a/testing/tcl_commands/utils.tcl b/testing/tcl_commands/utils.tcl new file mode 100644 index 0000000000..dfc8966613 --- /dev/null +++ b/testing/tcl_commands/utils.tcl @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +namespace eval testing_helpers { + + proc test_failure message { + echo $message + shutdown error + } + + proc check_for_error {expctd_code msg_ptrn script} { + set code [catch {uplevel $script} msg] + set expanded_script [uplevel subst \"$script\"] + if {!$code} { + test_failure \ + "'$expanded_script' finished successfully. \ + Was expecting an error." + } + if {$expctd_code ne "" && $code != $expctd_code} { + test_failure \ + "'$expanded_script' returned unexpected error code $code. \ + Was expecting $expctd_code. Error message: '$msg'" + } + if {$msg_ptrn ne "" && ![regexp -- $msg_ptrn $msg]} { + test_failure \ + "'$expanded_script' returned unexpected error message '$msg'. \ + Was expecting '$msg_ptrn'. Error code: $code" + } + } + + proc check_error_matches {pattern script} { + tailcall check_for_error {} $pattern $script + } + + proc check_syntax_err script { + tailcall check_for_error -601 {} $script + } + + proc check_matches {pattern script} { + set result [uplevel $script] + if {[regexp $pattern $result]} {return} + test_failure \ + "'$script' produced unexpected result '$result'. \ + Was expecting '$pattern'." + } + + namespace export check_error_matches check_syntax_err check_matches +} + +namespace eval configure_testing { + + variable target_idx 0 + + proc unique_tgt_name {} { + variable target_idx + incr target_idx + return test_target$target_idx + } + + proc target_create_first_args {} { + return "target create [unique_tgt_name] testee" + } + + proc simple_configure_options {} { + return { + -work-area-virt 0 + -work-area-phys 0 + -work-area-size 1 + -work-area-backup 0 + -endian little + -coreid 1 + -chain-position tap.cpu + -dbgbase 0 + -rtos hwthread + -gdb-port 0 + -gdb-max-connections 1 + } + } + + namespace export target_create_first_args simple_configure_options +} diff --git a/testing/test-am335xgpio-deprecated-commands.cfg b/testing/test-am335xgpio-deprecated-commands.cfg new file mode 100644 index 0000000000..09b2040161 --- /dev/null +++ b/testing/test-am335xgpio-deprecated-commands.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OpenOCD script to test that the deprecated "am335xgpio *" commands produce the +# expected results. Run this command as: +# +# openocd -f <path>/test-linuxgpiod-deprecated-commands.cfg + +# Raise an error if the "actual" value does not match the "expected" value. Trim +# whitespace (including newlines) from strings before comparing. +proc expected_value {expected actual} { + if {[string trim $expected] ne [string trim $actual]} { + error [puts "ERROR: '${actual}' != '${expected}'"] + } +} + +adapter driver am335xgpio + +am335xgpio jtag_nums 1 2 3 4 +expected_value "adapter gpio tck (output): num 1, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] +expected_value "adapter gpio tms (output): num 2, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] +expected_value "adapter gpio tdi (output): num 3, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] +expected_value "adapter gpio tdo (input): num 4, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +am335xgpio tck_num 5 +expected_value "adapter gpio tck (output): num 5, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] + +am335xgpio tms_num 6 +expected_value "adapter gpio tms (output): num 6, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] + +am335xgpio tdi_num 7 +expected_value "adapter gpio tdi (output): num 7, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] + +am335xgpio tdo_num 8 +expected_value "adapter gpio tdo (input): num 8, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +am335xgpio swd_nums 9 10 +expected_value "adapter gpio swclk (output): num 9, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] +expected_value "adapter gpio swdio (bidirectional): num 10, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +am335xgpio swclk_num 11 +expected_value "adapter gpio swclk (output): num 11, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] + +am335xgpio swdio_num 12 +expected_value "adapter gpio swdio (bidirectional): num 12, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +am335xgpio swdio_dir_num 13 +expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir] + +am335xgpio swdio_dir_output_state low +expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-low, push-pull, pull-none" [eval adapter gpio swdio_dir] + +am335xgpio swdio_dir_output_state high +expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir] + +am335xgpio srst_num 14 +expected_value "adapter gpio srst (output): num 14, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio srst] + +am335xgpio trst_num 15 +expected_value "adapter gpio trst (output): num 15, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio trst] + +am335xgpio led_num 16 +expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led] + +am335xgpio led_on_state low +expected_value "adapter gpio led (output): num 16, chip 0, active-low, push-pull, pull-none, init-state inactive" [eval adapter gpio led] + +am335xgpio led_on_state high +expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led] + +puts "SUCCESS" diff --git a/testing/test-bcm2835gpio-deprecated-commands.cfg b/testing/test-bcm2835gpio-deprecated-commands.cfg new file mode 100644 index 0000000000..b34eb36bb9 --- /dev/null +++ b/testing/test-bcm2835gpio-deprecated-commands.cfg @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OpenOCD script to test that the deprecated "bcm2835gpio *" and "bcm2835gpio_*" +# commands produce the expected results. Run this command as: +# openocd -f <path>/test-bcm2835gpio-deprecated-commands.cfg + +# Raise an error if the "actual" value does not match the "expected" value. Trim +# whitespace (including newlines) from strings before comparing. +proc expected_value {expected actual} { + if {[string trim $expected] ne [string trim $actual]} { + error [puts "ERROR: '${actual}' != '${expected}'"] + } +} + +set supported_signals {tdo tdi tms tck trst swdio swdio_dir swclk srst} + +adapter speed 100 +adapter driver bcm2835gpio +puts "Driver is '[adapter name]'" +expected_value "bcm2835gpio" [adapter name] +echo [adapter gpio] + +##################################### +# Test the "bcm2835gpio *" commands + +# Change the GPIO chip for all signals. Don't check directly here, do so when +# each signal command is tested. +# bcm2835gpio gpiochip 0 + +bcm2835gpio jtag_nums 1 2 3 4 +expected_value "adapter gpio tck (output): num 1, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] +expected_value "adapter gpio tms (output): num 2, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] +expected_value "adapter gpio tdi (output): num 3, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] +expected_value "adapter gpio tdo (input): num 4, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +bcm2835gpio tck_num 5 +expected_value "adapter gpio tck (output): num 5, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] + +bcm2835gpio tms_num 6 +expected_value "adapter gpio tms (output): num 6, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] + +bcm2835gpio tdi_num 7 +expected_value "adapter gpio tdi (output): num 7, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] + +bcm2835gpio tdo_num 8 +expected_value "adapter gpio tdo (input): num 8, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +bcm2835gpio swd_nums 9 10 +expected_value "adapter gpio swclk (output): num 9, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] +expected_value "adapter gpio swdio (bidirectional): num 10, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +bcm2835gpio swclk_num 11 +expected_value "adapter gpio swclk (output): num 11, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] + +bcm2835gpio swdio_num 12 +expected_value "adapter gpio swdio (bidirectional): num 12, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +bcm2835gpio swdio_dir_num 13 +expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir] + +bcm2835gpio srst_num 14 +expected_value "adapter gpio srst (output): num 14, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio srst] + +bcm2835gpio trst_num 15 +expected_value "adapter gpio trst (output): num 15, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio trst] + + +##################################### +# Test the old bcm2835gpio_* commands + +# Reset the GPIO chip for all signals. Don't check directly here, do so when +# each signal command is tested. +foreach sig_name $supported_signals { + eval adapter gpio $sig_name -chip -1 +} + +bcm2835gpio_jtag_nums 17 18 19 20 +expected_value "adapter gpio tck (output): num 17, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] +expected_value "adapter gpio tms (output): num 18, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] +expected_value "adapter gpio tdi (output): num 19, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] +expected_value "adapter gpio tdo (input): num 20, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +bcm2835gpio_tck_num 21 +expected_value "adapter gpio tck (output): num 21, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] + +bcm2835gpio_tms_num 22 +expected_value "adapter gpio tms (output): num 22, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] + +bcm2835gpio_tdi_num 23 +expected_value "adapter gpio tdi (output): num 23, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] + +bcm2835gpio_tdo_num 24 +expected_value "adapter gpio tdo (input): num 24, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +bcm2835gpio_swd_nums 25 26 +expected_value "adapter gpio swclk (output): num 25, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] +expected_value "adapter gpio swdio (bidirectional): num 26, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +bcm2835gpio_swclk_num 27 +expected_value "adapter gpio swclk (output): num 27, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] + +bcm2835gpio_swdio_num 28 +expected_value "adapter gpio swdio (bidirectional): num 28, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +puts "SUCCESS" diff --git a/testing/test-linuxgpiod-deprecated-commands.cfg b/testing/test-linuxgpiod-deprecated-commands.cfg new file mode 100644 index 0000000000..3d4f5cb4c4 --- /dev/null +++ b/testing/test-linuxgpiod-deprecated-commands.cfg @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OpenOCD script to test that the deprecated "linuxgpiod *" and "linuxgpiod_*" +# commands produce the expected results. Run this command as: +# openocd -f <path>/test-linuxgpiod-deprecated-commands.cfg + +# Raise an error if the "actual" value does not match the "expected" value. Trim +# whitespace (including newlines) from strings before comparing. +proc expected_value {expected actual} { + if {[string trim $expected] ne [string trim $actual]} { + error [puts "ERROR: '${actual}' != '${expected}'"] + } +} + +adapter driver linuxgpiod +puts "Driver is '[adapter name]'" +expected_value "linuxgpiod" [adapter name] +echo [adapter gpio] + +##################################### +# Test the "linuxgpiod *" commands + +# Change the GPIO chip for all signals. Don't check directly here, do so when +# each signal command is tested. +linuxgpiod gpiochip 0 + +linuxgpiod jtag_nums 1 2 3 4 +expected_value "adapter gpio tck (output): num 1, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] +expected_value "adapter gpio tms (output): num 2, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] +expected_value "adapter gpio tdi (output): num 3, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] +expected_value "adapter gpio tdo (input): num 4, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +linuxgpiod tck_num 5 +expected_value "adapter gpio tck (output): num 5, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] + +linuxgpiod tms_num 6 +expected_value "adapter gpio tms (output): num 6, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] + +linuxgpiod tdi_num 7 +expected_value "adapter gpio tdi (output): num 7, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] + +linuxgpiod tdo_num 8 +expected_value "adapter gpio tdo (input): num 8, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +linuxgpiod swd_nums 9 10 +expected_value "adapter gpio swclk (output): num 9, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] +expected_value "adapter gpio swdio (bidirectional): num 10, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +linuxgpiod swclk_num 11 +expected_value "adapter gpio swclk (output): num 11, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] + +linuxgpiod swdio_num 12 +expected_value "adapter gpio swdio (bidirectional): num 12, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +linuxgpiod swdio_dir_num 13 +expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir] + +linuxgpiod srst_num 14 +expected_value "adapter gpio srst (output): num 14, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio srst] + +linuxgpiod trst_num 15 +expected_value "adapter gpio trst (output): num 15, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio trst] + +linuxgpiod led_num 16 +expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led] + +##################################### +# Test the old linuxgpiod_* commands + +# Change the GPIO chip for all signals. Don't check directly here, do so when +# each signal command is tested. +linuxgpiod_gpiochip 1 + +linuxgpiod_jtag_nums 17 18 19 20 +expected_value "adapter gpio tck (output): num 17, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] +expected_value "adapter gpio tms (output): num 18, chip 1, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] +expected_value "adapter gpio tdi (output): num 19, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] +expected_value "adapter gpio tdo (input): num 20, chip 1, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +linuxgpiod_tck_num 21 +expected_value "adapter gpio tck (output): num 21, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck] + +linuxgpiod_tms_num 22 +expected_value "adapter gpio tms (output): num 22, chip 1, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms] + +linuxgpiod_tdi_num 23 +expected_value "adapter gpio tdi (output): num 23, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi] + +linuxgpiod_tdo_num 24 +expected_value "adapter gpio tdo (input): num 24, chip 1, active-high, pull-none, init-state input" [eval adapter gpio tdo] + +linuxgpiod_swd_nums 25 26 +expected_value "adapter gpio swclk (output): num 25, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] +expected_value "adapter gpio swdio (bidirectional): num 26, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +linuxgpiod_swclk_num 27 +expected_value "adapter gpio swclk (output): num 27, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk] + +linuxgpiod_swdio_num 28 +expected_value "adapter gpio swdio (bidirectional): num 28, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio] + +linuxgpiod_led_num 29 +expected_value "adapter gpio led (output): num 29, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led] + +puts "SUCCESS" diff --git a/tools/checkpatch.sh b/tools/checkpatch.sh index 0a630a2483..7375fc2b6d 100755 --- a/tools/checkpatch.sh +++ b/tools/checkpatch.sh @@ -1,5 +1,5 @@ #!/bin/sh -# +# SPDX-License-Identifier: GPL-2.0-or-later since=${1:-HEAD^} -git format-patch -M --stdout $since | tools/scripts/checkpatch.pl - +tools/scripts/checkpatch.pl --git ${since}.. diff --git a/tools/disassemble_inc.sh b/tools/disassemble_inc.sh new file mode 100755 index 0000000000..d4b5f80dce --- /dev/null +++ b/tools/disassemble_inc.sh @@ -0,0 +1,50 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-or-later + +# Simple script to disassemble a file .inc generated by +# src/helper/bin2char.sh +# Can be useful to check the correctness of the file .inc +# +# By default it decodes ARM thumb little-endian, e.g. cortex-m. +# Set CROSS_COMPILE for other toolchains. +# Set OBJDUMP_FLAGS for different objdump flags. +# +# Usage: +# contrib/loaders/disassemble_inc.sh file.inc + +default_CROSS_COMPILE="arm-none-eabi-" +default_OBJDUMP_FLAGS="-m arm -EL -M force-thumb" + +if [ $# != 1 -o ! -f "$1" ]; then + echo "Usage:" + echo " $0 path/to/file.inc" + echo "" + echo "Set CROSS_COMPILE and/or OBJDUMP_FLAGS to override current default:" + echo " export CROSS_COMPILE=\"${default_CROSS_COMPILE}\"" + echo " export OBJDUMP_FLAGS=\"${default_OBJDUMP_FLAGS}\"" + exit 1 +fi + +if [ -z "${CROSS_COMPILE}" ]; then + CROSS_COMPILE="${default_CROSS_COMPILE}" +fi + +if [ -z "${OBJDUMP_FLAGS}" ]; then + OBJDUMP_FLAGS="${default_OBJDUMP_FLAGS}" +fi + +perl -v > /dev/null 2>&1 +if [ $? != 0 ]; then + echo "Error: 'perl' interpreter not available." + exit 1 +fi + +tmpfile=$(mktemp --suffix=.bin) + +echo "Disassemble $1:" +echo "${CROSS_COMPILE}objdump ${OBJDUMP_FLAGS} -b binary -D ${tmpfile}" + +perl -e 'while (<>){while ($_=~/(0x..)/g){print chr(hex($1));}}' $1 > ${tmpfile} +${CROSS_COMPILE}objdump ${OBJDUMP_FLAGS} -b binary -D ${tmpfile} + +rm ${tmpfile} diff --git a/tools/git2cl b/tools/git2cl deleted file mode 160000 index 8373c9f749..0000000000 --- a/tools/git2cl +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 8373c9f74993e218a08819cbcdbab3f3564bbeba diff --git a/tools/scripts/camelcase.txt b/tools/scripts/camelcase.txt new file mode 100644 index 0000000000..058df4d808 --- /dev/null +++ b/tools/scripts/camelcase.txt @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The OpenOCD coding-style rules forbids CamelCase names for symbols, +# either functions, variables, macros and enums. +# The script checkpatch detects the CamelCase symbols. +# This file contains the exceptions to the coding-style, mainly due +# to external dependencies and libraries. + +# format types from inttypes.h (only some are already used) +PRId8 +PRId16 +PRId32 +PRId64 +PRIi8 +PRIi16 +PRIi32 +PRIi64 +PRIo8 +PRIo16 +PRIo32 +PRIo64 +PRIu8 +PRIu16 +PRIu32 +PRIu64 +PRIx8 +PRIx16 +PRIx32 +PRIx64 +PRIX8 +PRIX16 +PRIX32 +PRIX64 +SCNd8 +SCNd16 +SCNd32 +SCNd64 +SCNi8 +SCNi16 +SCNi32 +SCNi64 +SCNo8 +SCNo16 +SCNo32 +SCNo64 +SCNu8 +SCNu16 +SCNu32 +SCNu64 +SCNx8 +SCNx16 +SCNx32 +SCNx64 +SCNX8 +SCNX16 +SCNX32 +SCNX64 + +# OpenOCD format types +TARGET_PRIdADDR +TARGET_PRIoADDR +TARGET_PRIuADDR +TARGET_PRIxADDR + +# from libusb.h +bcdDevice +bConfigurationValue +bEndpointAddress +bInterfaceClass +bInterfaceNumber +bInterfaceProtocol +bInterfaceSubClass +bmAttributes +bNumConfigurations +bNumEndpoints +bNumInterfaces +idProduct +idVendor +iInterface +iManufacturer +iProduct +iSerialNumber +wMaxPacketSize + +# from jimtcl/jim.h and jimtcl/jim-eventloop.h +Jim_AppendString +Jim_AppendStrings +Jim_Cmd +Jim_CmdPrivData +Jim_CreateCommand +Jim_CreateInterp +Jim_DecrRefCount +Jim_DeleteAssocData +Jim_DeleteCommand +Jim_DictPairs +Jim_DuplicateObj +Jim_Eval +Jim_EvalObj +Jim_EvalObjPrefix +Jim_EvalSource +Jim_Eval_Named +Jim_FreeInterp +Jim_FreeObj +Jim_GetAssocData +Jim_GetCommand +Jim_GetDouble +Jim_GetEnum +Jim_GetExitCode +Jim_GetGlobalVariableStr +Jim_GetResult +Jim_GetString +Jim_GetWide +Jim_IncrRefCount +Jim_InitStaticExtensions +Jim_Interp +Jim_ListGetIndex +Jim_ListLength +Jim_MakeErrorMessage +Jim_NewEmptyStringObj +Jim_NewIntObj +Jim_NewStringObj +Jim_Obj +Jim_ProcessEvents +Jim_RegisterCoreCommands +Jim_SetAssocData +Jim_SetEmptyResult +Jim_SetResult +Jim_SetResultFormatted +Jim_SetResultString +Jim_String +Jim_WrongNumArgs +cmdProc +privData +returnCode + +# from elf.h +Elf32_Addr +Elf32_Ehdr +Elf32_Half +Elf32_Off +Elf32_Phdr +Elf32_Size +Elf32_Word +Elf64_Addr +Elf64_Ehdr +Elf64_Half +Elf64_Off +Elf64_Phdr +Elf64_Word +Elf64_Xword + +# for BSD's +__FreeBSD__ +__FreeBSD_kernel__ + +# for Windows +CreateFile +CloseHandle +FormatMessage +GetModuleFileName +GetSystemTimeAsFileTime +GetTickCount +GetVersionEx +HighPart +LowPart +MsgWaitForMultipleObjects +PeekMessage +PeekNamedPipe +QuadPart +SetConsoleCtrlHandler +Sleep +WaitForSingleObject +WSACleanup +WSAGetLastError +WSAStartup +dwHighDateTime +dwLowDateTime +dwPlatformId +dwOSVersionInfoSize + +# OpenOCD exceptions that should be removed +KiB diff --git a/tools/scripts/checkpatch.pl b/tools/scripts/checkpatch.pl index 0a119f1ba1..1011b33055 100755 --- a/tools/scripts/checkpatch.pl +++ b/tools/scripts/checkpatch.pl @@ -1,38 +1,96 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# # (c) 2001, Dave Jones. (the file handling bit) # (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit) # (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite) # (c) 2008-2010 Andy Whitcroft <apw@canonical.com> -# Licensed under the terms of the GNU GPL License version 2 +# (c) 2010-2018 Joe Perches <joe@perches.com> use strict; +use warnings; +use POSIX; +use File::Basename; +use Cwd 'abs_path'; +use Term::ANSIColor qw(:constants); +use Encode qw(decode encode); my $P = $0; -$P =~ s@.*/@@g; +my $D = dirname(abs_path($P)); my $V = '0.32'; use Getopt::Long qw(:config no_auto_abbrev); +# ATTENTION: easily track modification to this script for OpenOCD. +# When possible, don't modify the existing code, don't change its indentation, +# but remove it enclosing it within: +# +# if (!$OpenOCD) { +# original_code; +# } # !$OpenOCD +# +# Mark every addition within comments +# # OpenOCD specific: Begin[: additional comment] +# # OpenOCD specific: End +my $OpenOCD = 1; + my $quiet = 0; +my $verbose = 0; +my %verbose_messages = (); +my %verbose_emitted = (); my $tree = 1; my $chk_signoff = 1; my $chk_patch = 1; my $tst_only; my $emacs = 0; my $terse = 0; +my $showfile = 0; my $file = 0; +my $git = 0; +my %git_commits = (); my $check = 0; +my $check_orig = 0; my $summary = 1; my $mailback = 0; my $summary_file = 0; my $show_types = 0; +my $list_types = 0; +my $fix = 0; +my $fix_inplace = 0; my $root; +my $gitroot = $ENV{'GIT_DIR'}; +$gitroot = ".git" if !defined($gitroot); my %debug; +my %camelcase = (); +my %use_type = (); +my @use = (); my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; +my $max_line_length = 100; +my $ignore_perl_version = 0; +my $minimum_perl_version = 5.10.0; +my $min_conf_desc_length = 4; +my $spelling_file = "$D/spelling.txt"; +my $codespell = 0; +my $codespellfile = "/usr/share/codespell/dictionary.txt"; +my $user_codespellfile = ""; +my $conststructsfile = "$D/const_structs.checkpatch"; +if (!$OpenOCD) { +my $docsfile = "$D/../Documentation/dev-tools/checkpatch.rst"; +} # !$OpenOCD +# OpenOCD Specific: Begin +my $docsfile = "$D/../../doc/checkpatch.rst"; +# OpenOCD Specific: End +my $typedefsfile; +my $color = "auto"; +my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE +# git output parsing needs US English output, so first set backtick child process LANGUAGE +my $git_command ='export LANGUAGE=en_US.UTF-8; git'; +my $tabsize = 8; +my ${CONFIG_} = "CONFIG_"; sub help { my ($exitcode) = @_; @@ -43,16 +101,35 @@ sub help { Options: -q, --quiet quiet - --no-tree run without a openocd tree + -v, --verbose verbose mode + --no-tree run without an OpenOCD tree --no-signoff do not check for 'Signed-off-by' line --patch treat FILE as patchfile (default) --emacs emacs compile window format --terse one line per report + --showfile emit diffed file position, not input file position + -g, --git treat FILE as a single commit or git revision range + single git commit with: + <rev> + <rev>^ + <rev>~n + multiple git commits with: + <rev1>..<rev2> + <rev1>...<rev2> + <rev>-<count> + git merges are ignored -f, --file treat FILE as regular source file --subjective, --strict enable more subjective tests + --list-types list the possible message types + --types TYPE(,TYPE2...) show only these comma separated message types --ignore TYPE(,TYPE2...) ignore various comma separated message types - --show-types show the message "types" in the output - --root=PATH PATH to the openocd tree root + --show-types show the specific message type in the output + --max-line-length=n set the maximum line length, (default $max_line_length) + if exceeded, warn on patches + requires --strict for use with --file + --min-conf-desc-length=n set the min description length, if shorter, warn + --tab-size=n set the number of spaces for tab (default $tabsize) + --root=PATH PATH to the OpenOCD tree root --no-summary suppress the per-file summary --mailback only produce a report in case of warnings/errors --summary-file include the filename in summary @@ -61,6 +138,24 @@ sub help { is all off) --test-only=WORD report only warnings/errors containing WORD literally + --fix EXPERIMENTAL - may create horrible results + If correctable single-line errors exist, create + "<inputfile>.EXPERIMENTAL-checkpatch-fixes" + with potential errors corrected to the preferred + checkpatch style + --fix-inplace EXPERIMENTAL - may create horrible results + Is the same as --fix, but overwrites the input + file. It's your fault if there's no backup or git + --ignore-perl-version override checking of perl version. expect + runtime errors. + --codespell Use the codespell dictionary for spelling/typos + (default:$codespellfile) + --codespellfile Use this codespell dictionary + --typedefsfile Read additional types from this file + --color[=WHEN] Use colors 'always', 'never', or only when output + is a terminal ('auto'). Default is 'auto'. + --kconfig-prefix=WORD use WORD as a prefix for Kconfig symbols (default + ${CONFIG_}) -h, --help, --version display this help and exit When FILE is - read standard input. @@ -69,6 +164,74 @@ sub help { exit($exitcode); } +sub uniq { + my %seen; + return grep { !$seen{$_}++ } @_; +} + +sub list_types { + my ($exitcode) = @_; + + my $count = 0; + + local $/ = undef; + + open(my $script, '<', abs_path($P)) or + die "$P: Can't read '$P' $!\n"; + + my $text = <$script>; + close($script); + + my %types = (); + # Also catch when type or level is passed through a variable + while ($text =~ /(?:(\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { + if (defined($1)) { + if (exists($types{$2})) { + $types{$2} .= ",$1" if ($types{$2} ne $1); + } else { + $types{$2} = $1; + } + } else { + $types{$2} = "UNDETERMINED"; + } + } + + print("#\tMessage type\n\n"); + if ($color) { + print(" ( Color coding: "); + print(RED . "ERROR" . RESET); + print(" | "); + print(YELLOW . "WARNING" . RESET); + print(" | "); + print(GREEN . "CHECK" . RESET); + print(" | "); + print("Multiple levels / Undetermined"); + print(" )\n\n"); + } + + foreach my $type (sort keys %types) { + my $orig_type = $type; + if ($color) { + my $level = $types{$type}; + if ($level eq "ERROR") { + $type = RED . $type . RESET; + } elsif ($level eq "WARN") { + $type = YELLOW . $type . RESET; + } elsif ($level eq "CHK") { + $type = GREEN . $type . RESET; + } + } + print(++$count . "\t" . $type . "\n"); + if ($verbose && exists($verbose_messages{$orig_type})) { + my $message = $verbose_messages{$orig_type}; + $message =~ s/\n/\n\t/g; + print("\t" . $message . "\n\n"); + } + } + + exit($exitcode); +} + my $conf = which_conf($configuration_file); if (-f $conf) { my @conf_args; @@ -95,51 +258,189 @@ sub help { unshift(@ARGV, @conf_args) if @conf_args; } +sub load_docs { + open(my $docs, '<', "$docsfile") + or warn "$P: Can't read the documentation file $docsfile $!\n"; + + my $type = ''; + my $desc = ''; + my $in_desc = 0; + + while (<$docs>) { + chomp; + my $line = $_; + $line =~ s/\s+$//; + + if ($line =~ /^\s*\*\*(.+)\*\*$/) { + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + $type = $1; + $desc = ''; + $in_desc = 1; + } elsif ($in_desc) { + if ($line =~ /^(?:\s{4,}|$)/) { + $line =~ s/^\s{4}//; + $desc .= $line; + $desc .= "\n"; + } else { + $verbose_messages{$type} = trim($desc); + $type = ''; + $desc = ''; + $in_desc = 0; + } + } + } + + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + close($docs); +} + +# Perl's Getopt::Long allows options to take optional arguments after a space. +# Prevent --color by itself from consuming other arguments +foreach (@ARGV) { + if ($_ eq "--color" || $_ eq "-color") { + $_ = "--color=$color"; + } +} + GetOptions( 'q|quiet+' => \$quiet, + 'v|verbose!' => \$verbose, 'tree!' => \$tree, 'signoff!' => \$chk_signoff, 'patch!' => \$chk_patch, 'emacs!' => \$emacs, 'terse!' => \$terse, + 'showfile!' => \$showfile, 'f|file!' => \$file, + 'g|git!' => \$git, 'subjective!' => \$check, 'strict!' => \$check, 'ignore=s' => \@ignore, + 'types=s' => \@use, 'show-types!' => \$show_types, + 'list-types!' => \$list_types, + 'max-line-length=i' => \$max_line_length, + 'min-conf-desc-length=i' => \$min_conf_desc_length, + 'tab-size=i' => \$tabsize, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, 'summary-file!' => \$summary_file, - + 'fix!' => \$fix, + 'fix-inplace!' => \$fix_inplace, + 'ignore-perl-version!' => \$ignore_perl_version, 'debug=s' => \%debug, 'test-only=s' => \$tst_only, + 'codespell!' => \$codespell, + 'codespellfile=s' => \$user_codespellfile, + 'typedefsfile=s' => \$typedefsfile, + 'color=s' => \$color, + 'no-color' => \$color, #keep old behaviors of -nocolor + 'nocolor' => \$color, #keep old behaviors of -nocolor + 'kconfig-prefix=s' => \${CONFIG_}, 'h|help' => \$help, 'version' => \$help -) or help(1); +) or $help = 2; + +if ($user_codespellfile) { + # Use the user provided codespell file unconditionally + $codespellfile = $user_codespellfile; +} elsif (!(-f $codespellfile)) { + # If /usr/share/codespell/dictionary.txt is not present, try to find it + # under codespell's install directory: <codespell_root>/data/dictionary.txt + if (($codespell || $help) && which("python3") ne "") { + my $python_codespell_dict = << "EOF"; + +import os.path as op +import codespell_lib +codespell_dir = op.dirname(codespell_lib.__file__) +codespell_file = op.join(codespell_dir, 'data', 'dictionary.txt') +print(codespell_file, end='') +EOF + + my $codespell_dict = `python3 -c "$python_codespell_dict" 2> /dev/null`; + $codespellfile = $codespell_dict if (-f $codespell_dict); + } +} + +# $help is 1 if either -h, --help or --version is passed as option - exitcode: 0 +# $help is 2 if invalid option is passed - exitcode: 1 +help($help - 1) if ($help); + +die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix)); +die "$P: --verbose cannot be used with --terse\n" if ($verbose && $terse); + +if ($color =~ /^[01]$/) { + $color = !$color; +} elsif ($color =~ /^always$/i) { + $color = 1; +} elsif ($color =~ /^never$/i) { + $color = 0; +} elsif ($color =~ /^auto$/i) { + $color = (-t STDOUT); +} else { + die "$P: Invalid color mode: $color\n"; +} + +load_docs() if ($verbose); +list_types(0) if ($list_types); -help(0) if ($help); +$fix = 1 if ($fix_inplace); +$check_orig = $check; my $exit = 0; +my $perl_version_ok = 1; +if ($^V && $^V lt $minimum_perl_version) { + $perl_version_ok = 0; + printf "$P: requires at least perl version %vd\n", $minimum_perl_version; + exit(1) if (!$ignore_perl_version); +} + +#if no filenames are given, push '-' to read patch from stdin if ($#ARGV < 0) { - print "$P: no input files\n"; - exit(1); + push(@ARGV, '-'); } -@ignore = split(/,/, join(',',@ignore)); -foreach my $word (@ignore) { - $word =~ s/\s*\n?$//g; - $word =~ s/^\s*//g; - $word =~ s/\s+/ /g; - $word =~ tr/[a-z]/[A-Z]/; +# skip TAB size 1 to avoid additional checks on $tabsize - 1 +die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2); + +sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; + + my @array = split(/,/, join(',', @$arrayRef)); + foreach my $word (@array) { + $word =~ s/\s*\n?$//g; + $word =~ s/^\s*//g; + $word =~ s/\s+/ /g; + $word =~ tr/[a-z]/[A-Z]/; - next if ($word =~ m/^\s*#/); - next if ($word =~ m/^\s*$/); + next if ($word =~ m/^\s*#/); + next if ($word =~ m/^\s*$/); - $ignore_type{$word}++; + $hashRef->{$word}++; + } +} + +sub hash_show_words { + my ($hashRef, $prefix) = @_; + + if (keys %$hashRef) { + print "\nNOTE: $prefix message types:"; + foreach my $word (sort keys %$hashRef) { + print " $word"; + } + print "\n"; + } } +hash_save_array_words(\%ignore_type, \@ignore); +hash_save_array_words(\%use_type, \@use); + my $dbg_values = 0; my $dbg_possible = 0; my $dbg_type = 0; @@ -165,14 +466,16 @@ sub help { } else { if (top_of_kernel_tree('.')) { $root = '.'; + # OpenOCD specific: Begin: replace s"/scripts/"/tools/scripts/" } elsif ($0 =~ m@(.*)/tools/scripts/[^/]*$@ && top_of_kernel_tree($1)) { $root = $1; } + # OpenOCD specific: End } if (!defined $root) { - print "Must be run from the top-level dir. of a openocd tree\n"; + print "Must be run from the top-level dir. of an OpenOCD tree\n"; exit(2); } } @@ -190,20 +493,28 @@ sub help { __force| __iomem| __must_check| - __init_refok| __kprobes| __ref| - __rcu + __refconst| + __refdata| + __rcu| + __private }x; +our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)}; +our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)}; +our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)}; +our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)}; +our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit}; # Notes to $Attribute: # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check our $Attribute = qr{ const| + volatile| __percpu| __nocast| __safe| - __bitwise__| + __bitwise| __packed__| __packed2__| __naked| @@ -212,37 +523,57 @@ sub help { __noreturn| __used| __cold| + __pure| __noclone| __deprecated| __read_mostly| + __ro_after_init| __kprobes| - __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| + $InitAttribute| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| - __weak + __weak| + __alloc_size\s*\(\s*\d+\s*(?:,\s*\d+\s*)?\) }x; our $Modifier; -our $Inline = qr{inline|__always_inline|noinline}; +our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__}; our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; our $Lval = qr{$Ident(?:$Member)*}; -our $Constant = qr{(?:[0-9]+|0x[0-9a-fA-F]+)[UL]*}; -our $Assignment = qr{(?:\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=)}; -our $Compare = qr{<=|>=|==|!=|<|>}; +our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u}; +our $Binary = qr{(?i)0b[01]+$Int_type?}; +our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; +our $Int = qr{[0-9]+$Int_type?}; +our $Octal = qr{0[0-7]+$Int_type?}; +our $String = qr{(?:\b[Lu])?"[X\t]*"}; +our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; +our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; +our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; +our $Float = qr{$Float_hex|$Float_dec|$Float_int}; +our $Constant = qr{$Float|$Binary|$Octal|$Hex|$Int}; +our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; +our $Compare = qr{<=|>=|==|!=|<|(?<!-)>}; +our $Arithmetic = qr{\+|-|\*|\/|%}; our $Operators = qr{ <=|>=|==|!=| =>|->|<<|>>|<|>|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% + &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic }x; +our $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x; + +our $BasicType; our $NonptrType; +our $NonptrTypeMisordered; +our $NonptrTypeWithAttr; our $Type; +our $TypeMisordered; our $Declare; +our $DeclareMisordered; -our $UTF8 = qr { - [\x09\x0A\x0D\x20-\x7E] # ASCII - | [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte +our $NON_ASCII_UTF8 = qr{ + [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates @@ -251,40 +582,179 @@ sub help { | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 }x; -our $typeTypedefs = qr{(?x: +our $UTF8 = qr{ + [\x09\x0A\x0D\x20-\x7E] # ASCII + | $NON_ASCII_UTF8 +}x; + +our $typeC99Typedefs = qr{(?:__)?(?:[us]_?)?int_?(?:8|16|32|64)_t}; +our $typeOtherOSTypedefs = qr{(?x: + u_(?:char|short|int|long) | # bsd + u(?:nchar|short|int|long) # sysv +)}; +our $typeKernelTypedefs = qr{(?x: (?:__)?(?:u|s|be|le)(?:8|16|32|64)| atomic_t )}; +our $typeTypedefs = qr{(?x: + $typeC99Typedefs\b| + $typeOtherOSTypedefs\b| + $typeKernelTypedefs\b +)}; +our $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\b}; + +if (!$OpenOCD) { our $logFunctions = qr{(?x: - printk(?:_ratelimited|_once|)| - [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + printk(?:_ratelimited|_once|_deferred_once|_deferred|)| + (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + TP_printk| WARN(?:_RATELIMIT|_ONCE|)| panic| MODULE_[A-Z_]+| - LOG_(?:DEBUG|INFO|WARNING|ERROR|USER|USER_N|OUTPUT)+ + seq_vprintf|seq_printf|seq_puts +)}; +} # !$OpenOCD +# OpenOCD specific: Begin: list log functions +our $logFunctions = qr{(?x: + LOG_(?:TARGET_|)(?:DEBUG_IO|DEBUG|INFO|WARNING|ERROR|USER|USER_N|OUTPUT) +)}; +# OpenOCD specific: End + +our $allocFunctions = qr{(?x: + (?:(?:devm_)? + (?:kv|k|v)[czm]alloc(?:_array)?(?:_node)? | + kstrdup(?:_const)? | + kmemdup(?:_nul)?) | + (?:\w+)?alloc_skb(?:_ip_align)? | + # dev_alloc_skb/netdev_alloc_skb, et al + dma_alloc_coherent )}; our $signature_tags = qr{(?xi: Signed-off-by:| + Co-developed-by:| Acked-by:| Tested-by:| Reviewed-by:| Reported-by:| + Suggested-by:| To:| Cc: )}; +our $tracing_logging_tags = qr{(?xi: + [=-]*> | + <[=-]* | + \[ | + \] | + start | + called | + entered | + entry | + enter | + in | + inside | + here | + begin | + exit | + end | + done | + leave | + completed | + out | + return | + [\.\!:\s]* +)}; + +sub edit_distance_min { + my (@arr) = @_; + my $len = scalar @arr; + if ((scalar @arr) < 1) { + # if underflow, return + return; + } + my $min = $arr[0]; + for my $i (0 .. ($len-1)) { + if ($arr[$i] < $min) { + $min = $arr[$i]; + } + } + return $min; +} + +sub get_edit_distance { + my ($str1, $str2) = @_; + $str1 = lc($str1); + $str2 = lc($str2); + $str1 =~ s/-//g; + $str2 =~ s/-//g; + my $len1 = length($str1); + my $len2 = length($str2); + # two dimensional array storing minimum edit distance + my @distance; + for my $i (0 .. $len1) { + for my $j (0 .. $len2) { + if ($i == 0) { + $distance[$i][$j] = $j; + } elsif ($j == 0) { + $distance[$i][$j] = $i; + } elsif (substr($str1, $i-1, 1) eq substr($str2, $j-1, 1)) { + $distance[$i][$j] = $distance[$i - 1][$j - 1]; + } else { + my $dist1 = $distance[$i][$j - 1]; #insert distance + my $dist2 = $distance[$i - 1][$j]; # remove + my $dist3 = $distance[$i - 1][$j - 1]; #replace + $distance[$i][$j] = 1 + edit_distance_min($dist1, $dist2, $dist3); + } + } + } + return $distance[$len1][$len2]; +} + +sub find_standard_signature { + my ($sign_off) = @_; + my @standard_signature_tags = ( + 'Signed-off-by:', 'Co-developed-by:', 'Acked-by:', 'Tested-by:', + 'Reviewed-by:', 'Reported-by:', 'Suggested-by:' + ); + foreach my $signature (@standard_signature_tags) { + return $signature if (get_edit_distance($sign_off, $signature) <= 2); + } + + return ""; +} + +our @typeListMisordered = ( + qr{char\s+(?:un)?signed}, + qr{int\s+(?:(?:un)?signed\s+)?short\s}, + qr{int\s+short(?:\s+(?:un)?signed)}, + qr{short\s+int(?:\s+(?:un)?signed)}, + qr{(?:un)?signed\s+int\s+short}, + qr{short\s+(?:un)?signed}, + qr{long\s+int\s+(?:un)?signed}, + qr{int\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed\s+int}, + qr{int\s+(?:un)?signed\s+long}, + qr{int\s+(?:un)?signed}, + qr{int\s+long\s+long\s+(?:un)?signed}, + qr{long\s+long\s+int\s+(?:un)?signed}, + qr{long\s+long\s+(?:un)?signed\s+int}, + qr{long\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed}, +); + our @typeList = ( qr{void}, - qr{(?:unsigned\s+)?char}, - qr{(?:unsigned\s+)?short}, - qr{(?:unsigned\s+)?int}, - qr{(?:unsigned\s+)?long}, - qr{(?:unsigned\s+)?long\s+int}, - qr{(?:unsigned\s+)?long\s+long}, - qr{(?:unsigned\s+)?long\s+long\s+int}, - qr{unsigned}, + qr{(?:(?:un)?signed\s+)?char}, + qr{(?:(?:un)?signed\s+)?short\s+int}, + qr{(?:(?:un)?signed\s+)?short}, + qr{(?:(?:un)?signed\s+)?int}, + qr{(?:(?:un)?signed\s+)?long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long}, + qr{(?:(?:un)?signed\s+)?long}, + qr{(?:un)?signed}, qr{float}, qr{double}, qr{bool}, @@ -294,82 +764,578 @@ sub help { qr{${Ident}_t}, qr{${Ident}_handler}, qr{${Ident}_handler_fn}, + @typeListMisordered, +); + +our $C90_int_types = qr{(?x: + long\s+long\s+int\s+(?:un)?signed| + long\s+long\s+(?:un)?signed\s+int| + long\s+long\s+(?:un)?signed| + (?:(?:un)?signed\s+)?long\s+long\s+int| + (?:(?:un)?signed\s+)?long\s+long| + int\s+long\s+long\s+(?:un)?signed| + int\s+(?:(?:un)?signed\s+)?long\s+long| + + long\s+int\s+(?:un)?signed| + long\s+(?:un)?signed\s+int| + long\s+(?:un)?signed| + (?:(?:un)?signed\s+)?long\s+int| + (?:(?:un)?signed\s+)?long| + int\s+long\s+(?:un)?signed| + int\s+(?:(?:un)?signed\s+)?long| + + int\s+(?:un)?signed| + (?:(?:un)?signed\s+)?int +)}; + +our @typeListFile = (); +our @typeListWithAttr = ( + @typeList, + qr{struct\s+$InitAttribute\s+$Ident}, + qr{union\s+$InitAttribute\s+$Ident}, ); + our @modifierList = ( qr{fastcall}, ); +our @modifierListFile = (); + +our @mode_permission_funcs = ( + ["module_param", 3], + ["module_param_(?:array|named|string)", 4], + ["module_param_array_named", 5], + ["debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)", 2], + ["proc_create(?:_data|)", 2], + ["(?:CLASS|DEVICE|SENSOR|SENSOR_DEVICE|IIO_DEVICE)_ATTR", 2], + ["IIO_DEV_ATTR_[A-Z_]+", 1], + ["SENSOR_(?:DEVICE_|)ATTR_2", 2], + ["SENSOR_TEMPLATE(?:_2|)", 3], + ["__ATTR", 2], +); + +my $word_pattern = '\b[A-Z]?[a-z]{2,}\b'; + +#Create a search pattern for all these functions to speed up a loop below +our $mode_perms_search = ""; +foreach my $entry (@mode_permission_funcs) { + $mode_perms_search .= '|' if ($mode_perms_search ne ""); + $mode_perms_search .= $entry->[0]; +} +$mode_perms_search = "(?:${mode_perms_search})"; + +our %deprecated_apis = ( + "synchronize_rcu_bh" => "synchronize_rcu", + "synchronize_rcu_bh_expedited" => "synchronize_rcu_expedited", + "call_rcu_bh" => "call_rcu", + "rcu_barrier_bh" => "rcu_barrier", + "synchronize_sched" => "synchronize_rcu", + "synchronize_sched_expedited" => "synchronize_rcu_expedited", + "call_rcu_sched" => "call_rcu", + "rcu_barrier_sched" => "rcu_barrier", + "get_state_synchronize_sched" => "get_state_synchronize_rcu", + "cond_synchronize_sched" => "cond_synchronize_rcu", +); + +#Create a search pattern for all these strings to speed up a loop below +our $deprecated_apis_search = ""; +foreach my $entry (keys %deprecated_apis) { + $deprecated_apis_search .= '|' if ($deprecated_apis_search ne ""); + $deprecated_apis_search .= $entry; +} +$deprecated_apis_search = "(?:${deprecated_apis_search})"; + +our $mode_perms_world_writable = qr{ + S_IWUGO | + S_IWOTH | + S_IRWXUGO | + S_IALLUGO | + 0[0-7][0-7][2367] +}x; + +our %mode_permission_string_types = ( + "S_IRWXU" => 0700, + "S_IRUSR" => 0400, + "S_IWUSR" => 0200, + "S_IXUSR" => 0100, + "S_IRWXG" => 0070, + "S_IRGRP" => 0040, + "S_IWGRP" => 0020, + "S_IXGRP" => 0010, + "S_IRWXO" => 0007, + "S_IROTH" => 0004, + "S_IWOTH" => 0002, + "S_IXOTH" => 0001, + "S_IRWXUGO" => 0777, + "S_IRUGO" => 0444, + "S_IWUGO" => 0222, + "S_IXUGO" => 0111, +); + +#Create a search pattern for all these strings to speed up a loop below +our $mode_perms_string_search = ""; +foreach my $entry (keys %mode_permission_string_types) { + $mode_perms_string_search .= '|' if ($mode_perms_string_search ne ""); + $mode_perms_string_search .= $entry; +} +our $single_mode_perms_string_search = "(?:${mode_perms_string_search})"; +our $multi_mode_perms_string_search = qr{ + ${single_mode_perms_string_search} + (?:\s*\|\s*${single_mode_perms_string_search})* +}x; + +sub perms_to_octal { + my ($string) = @_; + + return trim($string) if ($string =~ /^\s*0[0-7]{3,3}\s*$/); + + my $val = ""; + my $oval = ""; + my $to = 0; + my $curpos = 0; + my $lastpos = 0; + while ($string =~ /\b(($single_mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) { + $curpos = pos($string); + my $match = $2; + my $omatch = $1; + last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos)); + $lastpos = $curpos; + $to |= $mode_permission_string_types{$match}; + $val .= '\s*\|\s*' if ($val ne ""); + $val .= $match; + $oval .= $omatch; + } + $oval =~ s/^\s*\|\s*//; + $oval =~ s/\s*\|\s*$//; + return sprintf("%04o", $to); +} our $allowed_asm_includes = qr{(?x: irq| - memory + memory| + time| + reboot )}; # memory.h: ARM has a custom one +# Load common spelling mistakes and build regular expression list. +my $misspellings; +my %spelling_fix; + +if (open(my $spelling, '<', $spelling_file)) { + while (<$spelling>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my ($suspect, $fix) = split(/\|\|/, $line); + + $spelling_fix{$suspect} = $fix; + } + close($spelling); +} else { + warn "No typos will be found - file '$spelling_file': $!\n"; +} + +if ($codespell) { + if (open(my $spelling, '<', $codespellfile)) { + while (<$spelling>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + next if ($line =~ m/, disabled/i); + + $line =~ s/,.*$//; + + my ($suspect, $fix) = split(/->/, $line); + + $spelling_fix{$suspect} = $fix; + } + close($spelling); + } else { + warn "No codespell typos will be found - file '$codespellfile': $!\n"; + } +} + +$misspellings = join("|", sort keys %spelling_fix) if keys %spelling_fix; + +sub read_words { + my ($wordsRef, $file) = @_; + + if (open(my $words, '<', $file)) { + while (<$words>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + if ($line =~ /\s/) { + print("$file: '$line' invalid - ignored\n"); + next; + } + + $$wordsRef .= '|' if (defined $$wordsRef); + $$wordsRef .= $line; + } + close($file); + return 1; + } + + return 0; +} + +# OpenOCD specific: Begin: Load list of allowed CamelCase symbols +if (show_type("CAMELCASE")) { + my $allowed_camelcase_file = "tools/scripts/camelcase.txt"; + if (!$root) { + warn "Ignore list of allowed camelcase symbols.\n"; + } elsif (open(my $words, '<', "$root/$allowed_camelcase_file")) { + while (<$words>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + if ($line =~ /\s/) { + print("$allowed_camelcase_file: '$line' invalid - ignored\n"); + next; + } + + $camelcase{$line} = 1; + } + close("$root/$allowed_camelcase_file"); + } else { + warn "Failed opening file '$root/$allowed_camelcase_file': $!\n"; + } +} +# OpenOCD specific: End + +my $const_structs; +if (show_type("CONST_STRUCT")) { + read_words(\$const_structs, $conststructsfile) + or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; +} + +if (defined($typedefsfile)) { + my $typeOtherTypedefs; + read_words(\$typeOtherTypedefs, $typedefsfile) + or warn "No additional types will be considered - file '$typedefsfile': $!\n"; + $typeTypedefs .= '|' . $typeOtherTypedefs if (defined $typeOtherTypedefs); +} + sub build_types { - my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; - my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; + my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)"; + my $all = "(?x: \n" . join("|\n ", (@typeList, @typeListFile)) . "\n)"; + my $Misordered = "(?x: \n" . join("|\n ", @typeListMisordered) . "\n)"; + my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)"; $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; + $BasicType = qr{ + (?:$typeTypedefs\b)| + (?:${all}\b) + }x; $NonptrType = qr{ (?:$Modifier\s+|const\s+)* (?: - (?:typeof|__typeof__)\s*\(\s*\**\s*$Ident\s*\)| + (?:typeof|__typeof__)\s*\([^\)]*\)| (?:$typeTypedefs\b)| (?:${all}\b) ) (?:\s+$Modifier|\s+const)* }x; + $NonptrTypeMisordered = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:${Misordered}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeWithAttr = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${allWithAttr}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; $Type = qr{ $NonptrType - (?:[\s\*]+\s*const|[\s\*]+|(?:\s*\[\s*\])+)? + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4} + (?:\s+$Inline|\s+$Modifier)* + }x; + $TypeMisordered = qr{ + $NonptrTypeMisordered + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4} (?:\s+$Inline|\s+$Modifier)* }x; - $Declare = qr{(?:$Storage\s+)?$Type}; + $Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type}; + $DeclareMisordered = qr{(?:$Storage\s+(?:$Inline\s+)?)?$TypeMisordered}; } build_types(); -our $match_balanced_parentheses = qr/(\((?:[^\(\)]+|(-1))*\))/; - our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; -our $LvalOrFunc = qr{($Lval)\s*($match_balanced_parentheses{0,1})\s*}; + +# Using $balanced_parens, $LvalOrFunc, or $FuncArg +# requires at least perl version v5.10.0 +# Any use must be runtime checked with $^V + +our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; +our $LvalOrFunc = qr{((?:[\&\*]\s*)?$Lval)\s*($balanced_parens{0,1})\s*}; +our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)}; + +our $declaration_macros = qr{(?x: + (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| + (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| + (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\(| + (?:$Storage\s+)?(?:XA_STATE|XA_STATE_ORDER)\s*\( +)}; + +our %allow_repeated_words = ( + add => '', + added => '', + bad => '', + be => '', +); sub deparenthesize { my ($string) = @_; return "" if (!defined($string)); - $string =~ s@^\s*\(\s*@@g; - $string =~ s@\s*\)\s*$@@g; + + while ($string =~ /^\s*\(.*\)\s*$/) { + $string =~ s@^\s*\(\s*@@; + $string =~ s@\s*\)\s*$@@; + } + $string =~ s@\s+@ @g; + return $string; } -$chk_signoff = 0 if ($file); +sub seed_camelcase_file { + my ($file) = @_; -my @dep_includes = (); -my @dep_functions = (); -my $removal = "Documentation/feature-removal-schedule.txt"; -if ($tree && -f "$root/$removal") { - open(my $REMOVE, '<', "$root/$removal") || - die "$P: $removal: open failed - $!\n"; - while (<$REMOVE>) { - if (/^Check:\s+(.*\S)/) { - for my $entry (split(/[, ]+/, $1)) { - if ($entry =~ m@include/(.*)@) { - push(@dep_includes, $1); + return if (!(-f $file)); - } elsif ($entry !~ m@/@) { - push(@dep_functions, $entry); - } - } + local $/; + + open(my $include_file, '<', "$file") + or warn "$P: Can't read '$file' $!\n"; + my $text = <$include_file>; + close($include_file); + + my @lines = split('\n', $text); + + foreach my $line (@lines) { + if (!$OpenOCD) { + next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + } # !$OpenOCD + # OpenOCD Specific: Begin: extend to camel[0-9_]*CASE + next if ($line !~ /(?:[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + # OpenOCD Specific: End + } +} + +our %maintained_status = (); + +sub is_maintained_obsolete { + my ($filename) = @_; + + return 0 if (!$tree || !(-e "$root/scripts/get_maintainer.pl")); + + if (!exists($maintained_status{$filename})) { + $maintained_status{$filename} = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`; + } + + return $maintained_status{$filename} =~ /obsolete/i; +} + +sub is_SPDX_License_valid { + my ($license) = @_; + + # OpenOCD specific: Begin: replace s"scripts"tools/scripts" + return 1 if (!$tree || which("python3") eq "" || !(-x "$root/tools/scripts/spdxcheck.py") || !(-e "$gitroot")); + + my $root_path = abs_path($root); + my $status = `cd "$root_path"; echo "$license" | tools/scripts/spdxcheck.py -`; + # OpenOCD specific: End + return 0 if ($status ne ""); + return 1; +} + +my $camelcase_seeded = 0; +sub seed_camelcase_includes { + return if ($camelcase_seeded); + + my $files; + my $camelcase_cache = ""; + my @include_files = (); + + $camelcase_seeded = 1; + + if (-e "$gitroot") { + my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; + } else { + my $last_mod_date = 0; + $files = `find $root/include -name "*.h"`; + @include_files = split('\n', $files); + foreach my $file (@include_files) { + my $date = POSIX::strftime("%Y%m%d%H%M", + localtime((stat $file)[9])); + $last_mod_date = $date if ($last_mod_date < $date); + } + $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date"; + } + + if ($camelcase_cache ne "" && -f $camelcase_cache) { + open(my $camelcase_file, '<', "$camelcase_cache") + or warn "$P: Can't read '$camelcase_cache' $!\n"; + while (<$camelcase_file>) { + chomp; + $camelcase{$_} = 1; + } + close($camelcase_file); + + return; + } + + if (-e "$gitroot") { + $files = `${git_command} ls-files "include/*.h"`; + @include_files = split('\n', $files); + } + + foreach my $file (@include_files) { + seed_camelcase_file($file); + } + + if ($camelcase_cache ne "") { + unlink glob ".checkpatch-camelcase.*"; + open(my $camelcase_file, '>', "$camelcase_cache") + or warn "$P: Can't write '$camelcase_cache' $!\n"; + foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) { + print $camelcase_file ("$_\n"); } + close($camelcase_file); + } +} + +sub git_is_single_file { + my ($filename) = @_; + + return 0 if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} ls-files -- $filename 2>/dev/null`; + my $count = $output =~ tr/\n//; + return $count eq 1 && $output =~ m{^${filename}$}; +} + +sub git_commit_info { + my ($commit, $id, $desc) = @_; + + return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`; + $output =~ s/^\s*//gm; + my @lines = split("\n", $output); + + return ($id, $desc) if ($#lines < 0); + + if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous/) { +# Maybe one day convert this block of bash into something that returns +# all matching commit ids, but it's very slow... +# +# echo "checking commits $1..." +# git rev-list --remotes | grep -i "^$1" | +# while read line ; do +# git log --format='%H %s' -1 $line | +# echo "commit $(cut -c 1-12,41-)" +# done + } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./ || + $lines[0] =~ /^fatal: bad object $commit/) { + $id = undef; + } else { + $id = substr($lines[0], 0, 12); + $desc = substr($lines[0], 41); } - close($REMOVE); + + return ($id, $desc); } +$chk_signoff = 0 if ($file); + my @rawlines = (); my @lines = (); +my @fixed = (); +my @fixed_inserted = (); +my @fixed_deleted = (); +my $fixlinenr = -1; + +# If input is git commits, extract all commits from the commit expressions. +# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'. +die "$P: No git repository found\n" if ($git && !-e "$gitroot"); + +if ($git) { + my @commits = (); + foreach my $commit_expr (@ARGV) { + my $git_range; + if ($commit_expr =~ m/^(.*)-(\d+)$/) { + $git_range = "-$2 $1"; + } elsif ($commit_expr =~ m/\.\./) { + $git_range = "$commit_expr"; + } else { + $git_range = "-1 $commit_expr"; + } + my $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`; + foreach my $line (split(/\n/, $lines)) { + $line =~ /^([0-9a-fA-F]{40,40}) (.*)$/; + next if (!defined($1) || !defined($2)); + my $sha1 = $1; + my $subject = $2; + unshift(@commits, $sha1); + $git_commits{$sha1} = $subject; + } + } + die "$P: no git commits after extraction!\n" if (@commits == 0); + @ARGV = @commits; +} + my $vname; +$allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"}; for my $filename (@ARGV) { my $FILE; - if ($file) { + my $is_git_file = git_is_single_file($filename); + my $oldfile = $file; + $file = 1 if ($is_git_file); + if ($git) { + open($FILE, '-|', "git format-patch -M --stdout -1 $filename") || + die "$P: $filename: git format-patch failed - $!\n"; + } elsif ($file) { open($FILE, '-|', "diff -u /dev/null $filename") || die "$P: $filename: diff failed - $!\n"; } elsif ($filename eq '-') { @@ -380,30 +1346,87 @@ sub deparenthesize { } if ($filename eq '-') { $vname = 'Your patch'; + } elsif ($git) { + $vname = "Commit " . substr($filename, 0, 12) . ' ("' . $git_commits{$filename} . '")'; } else { $vname = $filename; } while (<$FILE>) { chomp; push(@rawlines, $_); + $vname = qq("$1") if ($filename eq '-' && $_ =~ m/^Subject:\s+(.+)/i); } close($FILE); + + if ($#ARGV > 0 && $quiet == 0) { + print '-' x length($vname) . "\n"; + print "$vname\n"; + print '-' x length($vname) . "\n"; + } + if (!process($filename)) { $exit = 1; } @rawlines = (); @lines = (); + @fixed = (); + @fixed_inserted = (); + @fixed_deleted = (); + $fixlinenr = -1; + @modifierListFile = (); + @typeListFile = (); + build_types(); + $file = $oldfile if ($is_git_file); } -exit($exit); +if (!$quiet) { + hash_show_words(\%use_type, "Used"); + hash_show_words(\%ignore_type, "Ignored"); + + if (!$perl_version_ok) { + print << "EOM" + +NOTE: perl $^V is not modern enough to detect all possible issues. + An upgrade to at least perl $minimum_perl_version is suggested. +EOM + } + if ($exit) { + if (!$OpenOCD) { + print << "EOM" + +NOTE: If any of the errors are false positives, please report + them to the maintainer, see CHECKPATCH in MAINTAINERS. +EOM + } # !$OpenOCD + # OpenOCD specific: Begin + print << "EOM" + +NOTE: If any of the errors are false positives, please report + them to the openocd-devel mailing list or prepare a patch + and send it to Gerrit for review. +EOM + # OpenOCD specific: End + } +} + +exit($exit); sub top_of_kernel_tree { my ($root) = @_; + if (!$OpenOCD) { + my @tree_check = ( + "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", + "README", "Documentation", "arch", "include", "drivers", + "fs", "init", "ipc", "kernel", "lib", "scripts", + ); + } # !$OpenOCD + # OpenOCD specific: Begin my @tree_check = ( "AUTHORS", "BUGS", "COPYING", "HACKING", "Makefile.am", "README", "contrib", "doc", "src", "tcl", "testing", "tools", ); + # OpenOCD specific: End foreach my $check (@tree_check) { if (! -e $root . '/' . $check) { @@ -411,12 +1434,14 @@ sub top_of_kernel_tree { } } return 1; - } +} sub parse_email { my ($formatted_email) = @_; my $name = ""; + my $quoted = ""; + my $name_comment = ""; my $address = ""; my $comment = ""; @@ -430,9 +1455,9 @@ sub parse_email { } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { $address = $1; $comment = $2 if defined $2; - $formatted_email =~ s/$address.*$//; + $formatted_email =~ s/\Q$address\E.*$//; $name = $formatted_email; - $name =~ s/^\s+|\s+$//g; + $name = trim($name); $name =~ s/^\"|\"$//g; # If there's a name left after stripping spaces and # leading quotes, and the address doesn't have both @@ -445,46 +1470,94 @@ sub parse_email { $address = ""; $comment = ""; } + # OpenOCD specific: Begin: handle jenkins as valid email } elsif ($formatted_email eq "jenkins") { - $address = "jenkins" + $address = "jenkins"; + # OpenOCD specific: End + } + + # Extract comments from names excluding quoted parts + # "John D. (Doe)" - Do not extract + if ($name =~ s/\"(.+)\"//) { + $quoted = $1; + } + while ($name =~ s/\s*($balanced_parens)\s*/ /) { + $name_comment .= trim($1); } + $name =~ s/^[ \"]+|[ \"]+$//g; + $name = trim("$quoted $name"); - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; + $address = trim($address); $address =~ s/^\<|\>$//g; + $comment = trim($comment); if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?<!\\)"/\\"/g; ##escape quotes $name = "\"$name\""; } - return ($name, $address, $comment); + return ($name, $name_comment, $address, $comment); } sub format_email { - my ($name, $address) = @_; + my ($name, $name_comment, $address, $comment) = @_; my $formatted_email; - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; + $name =~ s/^[ \"]+|[ \"]+$//g; + $address = trim($address); + $address =~ s/(?:\.|\,|\")+$//; ##trailing commas, dots or quotes if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?<!\\)"/\\"/g; ##escape quotes $name = "\"$name\""; } + $name_comment = trim($name_comment); + $name_comment = " $name_comment" if ($name_comment ne ""); + $comment = trim($comment); + $comment = " $comment" if ($comment ne ""); + if ("$name" eq "") { $formatted_email = "$address"; } else { - $formatted_email = "$name <$address>"; + $formatted_email = "$name$name_comment <$address>"; } - + $formatted_email .= "$comment"; return $formatted_email; } +sub reformat_email { + my ($email) = @_; + + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); + return format_email($email_name, $name_comment, $email_address, $comment); +} + +sub same_email_addresses { + my ($email1, $email2) = @_; + + my ($email1_name, $name1_comment, $email1_address, $comment1) = parse_email($email1); + my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2); + + return $email1_name eq $email2_name && + $email1_address eq $email2_address && + $name1_comment eq $name2_comment && + $comment1 eq $comment2; +} + +sub which { + my ($bin) = @_; + + foreach my $path (split(/:/, $ENV{PATH})) { + if (-e "$path/$bin") { + return "$path/$bin"; + } + } + + return ""; +} + sub which_conf { my ($conf) = @_; @@ -506,7 +1579,7 @@ sub expand_tabs { if ($c eq "\t") { $res .= ' '; $n++; - for (; ($n % 4) != 0; $n++) { + for (; ($n % $tabsize) != 0; $n++) { $res .= ' '; } next; @@ -562,7 +1635,7 @@ sub sanitise_line { for ($off = 1; $off < length($line); $off++) { $c = substr($line, $off, 1); - # Comments we are wacking completly including the begin + # Comments we are whacking completely including the begin # and end, all to $;. if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { $sanitise_quote = '*/'; @@ -631,9 +1704,22 @@ sub sanitise_line { $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; } + if ($allow_c99_comments && $res =~ m@(//.*$)@) { + my $match = $1; + $res =~ s/\Q$match\E/"$;" x length($match)/e; + } + return $res; } +sub get_quoted_string { + my ($line, $rawline) = @_; + + return "" if (!defined($line) || !defined($rawline)); + return "" if ($line !~ m/($String)/g); + return substr($rawline, $-[0], $+[0] - $-[0]); +} + sub ctx_statement_block { my ($linenr, $remain, $off) = @_; my $line = $linenr - 1; @@ -674,6 +1760,10 @@ sub ctx_statement_block { if ($off >= $len) { last; } + if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { + $level++; + $type = '#'; + } } $p = $c; $c = substr($blk, $off, 1); @@ -699,7 +1789,7 @@ sub ctx_statement_block { # An else is really a conditional as long as its not else if if ($level == 0 && $coff_set == 0 && (!defined($p) || $p =~ /(?:\s|\}|\+)/) && - $remainder =~ /^(else)(?:\s|\{)/ && + $remainder =~ /^(else)(?:\s|{)/ && $remainder !~ /^else\s+if\b/) { $coff = $off + length($1) - 1; $coff_set = 1; @@ -736,6 +1826,13 @@ sub ctx_statement_block { last; } } + # Preprocessor commands end at the newline unless escaped. + if ($type eq '#' && $c eq "\n" && $p ne "\\") { + $level--; + $type = ''; + $off++; + last; + } $off++; } # We are truly at the end, so shuffle to the next line. @@ -782,7 +1879,7 @@ sub statement_block_size { my ($stmt) = @_; $stmt =~ s/(^|\n)./$1/g; - $stmt =~ s/^\s*\{//; + $stmt =~ s/^\s*{//; $stmt =~ s/}\s*$//; $stmt =~ s/^\s*//; $stmt =~ s/\s*$//; @@ -911,8 +2008,16 @@ sub ctx_statement_level { sub ctx_locate_comment { my ($first_line, $end_line) = @_; + # If c99 comment on the current line, or the line before or after + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\+.*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + # Catch a comment on the end of the line itself. - my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); return $current_comment if (defined $current_comment); # Look through the context and try and figure out if there is a @@ -966,6 +2071,28 @@ sub raw_line { return $line; } +sub get_stat_real { + my ($linenr, $lc) = @_; + + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + + return $stat_real; +} + +sub get_stat_here { + my ($linenr, $cnt, $here) = @_; + + my $herectx = $here . "\n"; + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + return $herectx; +} + sub cat_vet { my ($vet) = @_; my ($res, $coded); @@ -1018,7 +2145,7 @@ sub annotate_values { } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { print "CAST($1)\n" if ($dbg_values > 1); push(@av_paren_type, $type); - $type = 'C'; + $type = 'c'; } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { print "DECLARE($1)\n" if ($dbg_values > 1); @@ -1136,7 +2263,7 @@ sub annotate_values { print "ASSIGN($1)\n" if ($dbg_values > 1); $type = 'N'; - } elsif ($cur =~/^(;|\{|})/) { + } elsif ($cur =~/^(;|{|})/) { print "END($1)\n" if ($dbg_values > 1); $type = 'E'; $av_pend_colon = 'O'; @@ -1210,7 +2337,9 @@ sub possible { case| else| asm|__asm__| - do + do| + \#| + \#\#| )(?:\s|$)| ^(?:typedef|struct|enum)\b )}x; @@ -1226,13 +2355,13 @@ sub possible { for my $modifier (split(' ', $possible)) { if ($modifier !~ $notPermitted) { warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); - push(@modifierList, $modifier); + push(@modifierListFile, $modifier); } } } else { warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); - push(@typeList, $possible); + push(@typeListFile, $possible); } build_types(); } else { @@ -1243,47 +2372,182 @@ sub possible { my $prefix = ''; sub show_type { - return !defined $ignore_type{$_[0]}; + my ($type) = @_; + + $type =~ tr/[a-z]/[A-Z]/; + + return defined $use_type{$type} if (scalar keys %use_type > 0); + + return !defined $ignore_type{$type}; } sub report { - if (!show_type($_[1]) || - (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { + my ($level, $type, $msg) = @_; + + # OpenOCD specific: Begin: Flatten ERROR, WARNING and CHECK as ERROR + $level = 'ERROR'; + # OpenOCD specific: End + + if (!show_type($type) || + (defined $tst_only && $msg !~ /\Q$tst_only\E/)) { return 0; } - my $line; + my $output = ''; + if ($color) { + if ($level eq 'ERROR') { + $output .= RED; + } elsif ($level eq 'WARNING') { + $output .= YELLOW; + } else { + $output .= GREEN; + } + } + $output .= $prefix . $level . ':'; if ($show_types) { - $line = "$prefix$_[0]:$_[1]: $_[2]\n"; - } else { - $line = "$prefix$_[0]: $_[2]\n"; + $output .= BLUE if ($color); + $output .= "$type:"; + } + $output .= RESET if ($color); + $output .= ' ' . $msg . "\n"; + + if ($showfile) { + my @lines = split("\n", $output, -1); + splice(@lines, 1, 1); + $output = join("\n", @lines); } - $line = (split('\n', $line))[0] . "\n" if ($terse); - push(our @report, $line); + if ($terse) { + $output = (split('\n', $output))[0] . "\n"; + } + + if ($verbose && exists($verbose_messages{$type}) && + !exists($verbose_emitted{$type})) { + $output .= $verbose_messages{$type} . "\n\n"; + $verbose_emitted{$type} = 1; + } + + push(our @report, $output); return 1; } + sub report_dump { our @report; } +sub fixup_current_range { + my ($lineRef, $offset, $length) = @_; + + if ($$lineRef =~ /^\@\@ -\d+,\d+ \+(\d+),(\d+) \@\@/) { + my $o = $1; + my $l = $2; + my $no = $o + $offset; + my $nl = $l + $length; + $$lineRef =~ s/\+$o,$l \@\@/\+$no,$nl \@\@/; + } +} + +sub fix_inserted_deleted_lines { + my ($linesRef, $insertedRef, $deletedRef) = @_; + + my $range_last_linenr = 0; + my $delta_offset = 0; + + my $old_linenr = 0; + my $new_linenr = 0; + + my $next_insert = 0; + my $next_delete = 0; + + my @lines = (); + + my $inserted = @{$insertedRef}[$next_insert++]; + my $deleted = @{$deletedRef}[$next_delete++]; + + foreach my $old_line (@{$linesRef}) { + my $save_line = 1; + my $line = $old_line; #don't modify the array + if ($line =~ /^(?:\+\+\+|\-\-\-)\s+\S+/) { #new filename + $delta_offset = 0; + } elsif ($line =~ /^\@\@ -\d+,\d+ \+\d+,\d+ \@\@/) { #new hunk + $range_last_linenr = $new_linenr; + fixup_current_range(\$line, $delta_offset, 0); + } + + while (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) { + $deleted = @{$deletedRef}[$next_delete++]; + $save_line = 0; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset--, -1); + } + + while (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) { + push(@lines, ${$inserted}{'LINE'}); + $inserted = @{$insertedRef}[$next_insert++]; + $new_linenr++; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset++, 1); + } + + if ($save_line) { + push(@lines, $line); + $new_linenr++; + } + + $old_linenr++; + } + + return @lines; +} + +sub fix_insert_line { + my ($linenr, $line) = @_; + + my $inserted = { + LINENR => $linenr, + LINE => $line, + }; + push(@fixed_inserted, $inserted); +} + +sub fix_delete_line { + my ($linenr, $line) = @_; + + my $deleted = { + LINENR => $linenr, + LINE => $line, + }; + + push(@fixed_deleted, $deleted); +} + sub ERROR { - if (report("ERROR", $_[0], $_[1])) { + my ($type, $msg) = @_; + + if (report("ERROR", $type, $msg)) { our $clean = 0; our $cnt_error++; + return 1; } + return 0; } sub WARN { - if (report("WARNING", $_[0], $_[1])) { + my ($type, $msg) = @_; + + if (report("WARNING", $type, $msg)) { our $clean = 0; our $cnt_warn++; + return 1; } + return 0; } sub CHK { - if ($check && report("CHECK", $_[0], $_[1])) { + my ($type, $msg) = @_; + + if ($check && report("CHECK", $type, $msg)) { our $clean = 0; our $cnt_chk++; + return 1; } + return 0; } sub check_absolute_file { @@ -1314,6 +2578,105 @@ sub check_absolute_file { } } +sub trim { + my ($string) = @_; + + $string =~ s/^\s+|\s+$//g; + + return $string; +} + +sub ltrim { + my ($string) = @_; + + $string =~ s/^\s+//; + + return $string; +} + +sub rtrim { + my ($string) = @_; + + $string =~ s/\s+$//; + + return $string; +} + +sub string_find_replace { + my ($string, $find, $replace) = @_; + + $string =~ s/$find/$replace/g; + + return $string; +} + +sub tabify { + my ($leading) = @_; + + my $source_indent = $tabsize; + my $max_spaces_before_tab = $source_indent - 1; + my $spaces_to_tab = " " x $source_indent; + + #convert leading spaces to tabs + 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g; + #Remove spaces before a tab + 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g; + + return "$leading"; +} + +sub pos_last_openparen { + my ($line) = @_; + + my $pos = 0; + + my $opens = $line =~ tr/\(/\(/; + my $closes = $line =~ tr/\)/\)/; + + my $last_openparen = 0; + + if (($opens == 0) || ($closes >= $opens)) { + return -1; + } + + my $len = length($line); + + for ($pos = 0; $pos < $len; $pos++) { + my $string = substr($line, $pos); + if ($string =~ /^($FuncArg|$balanced_parens)/) { + $pos += length($1) - 1; + } elsif (substr($line, $pos, 1) eq '(') { + $last_openparen = $pos; + } elsif (index($string, '(') == -1) { + last; + } + } + + return length(expand_tabs(substr($line, 0, $last_openparen))) + 1; +} + +sub get_raw_comment { + my ($line, $rawline) = @_; + my $comment = ''; + + for my $i (0 .. (length($line) - 1)) { + if (substr($line, $i, 1) eq "$;") { + $comment .= substr($rawline, $i, 1); + } + } + + return $comment; +} + +sub exclude_global_initialisers { + my ($realfile) = @_; + + # Do not check for BPF programs (tools/testing/selftests/bpf/progs/*.c, samples/bpf/*_kern.c, *.bpf.c). + return $realfile =~ m@^tools/testing/selftests/bpf/progs/.*\.c$@ || + $realfile =~ m@^samples/bpf/.*_kern\.c$@ || + $realfile =~ m@/bpf/.*\.bpf\.c$@; +} + sub process { my $filename = shift; @@ -1330,7 +2693,26 @@ sub process { our $clean = 1; my $signoff = 0; + my $author = ''; + my $authorsignoff = 0; + my $author_sob = ''; my $is_patch = 0; + my $is_binding_patch = -1; + my $in_header_lines = $file ? 0 : 1; + my $in_commit_log = 0; #Scanning lines before patch + my $has_patch_separator = 0; #Found a --- line + my $has_commit_log = 0; #Encountered lines before patch + my $commit_log_lines = 0; #Number of commit log lines + my $commit_log_possible_stack_dump = 0; + my $commit_log_long_line = 0; + my $commit_log_has_diff = 0; + my $reported_maintainer_file = 0; + my $non_utf8_charset = 0; + + my $last_git_commit_id_linenr = -1; + + my $last_blank_line = 0; + my $last_coalesced_string_linenr = -1; our @report = (); our $cnt_lines = 0; @@ -1343,6 +2725,7 @@ sub process { my $realline = 0; my $realcnt = 0; my $here = ''; + my $context_function; #undef'd unless there's a known function my $in_comment = 0; my $comment_edge = 0; my $first_line = 0; @@ -1354,6 +2737,9 @@ sub process { my %suppress_ifbraces; my %suppress_whiletrailers; my %suppress_export; + my $suppress_statement = 0; + + my %signatures = (); # Pre-scan the patch sanitizing the lines. # Pre-scan the patch looking for any __setup documentation. @@ -1361,20 +2747,26 @@ sub process { my @setup_docs = (); my $setup_docs = 0; + my $camelcase_file_seeded = 0; + + my $checklicenseline = 1; + sanitise_line_reset(); my $line; foreach my $rawline (@rawlines) { $linenr++; $line = $rawline; + push(@fixed, $rawline) if ($fix); + if ($rawline=~/^\+\+\+\s+(\S+)/) { $setup_docs = 0; - if ($1 =~ m@Documentation/kernel-parameters.txt$@) { + if ($1 =~ m@Documentation/admin-guide/kernel-parameters.txt$@) { $setup_docs = 1; } #next; } - if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + if ($rawline =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { $realline=$1-1; if (defined $2) { $realcnt=$3+1; @@ -1442,13 +2834,28 @@ sub process { $realcnt = 0; $linenr = 0; + $fixlinenr = -1; foreach my $line (@lines) { $linenr++; + $fixlinenr++; + my $sline = $line; #copy of $line + $sline =~ s/$;/ /g; #with comments as spaces my $rawline = $rawlines[$linenr - 1]; + my $raw_comment = get_raw_comment($line, $rawline); + +# check if it's a mode change, rename or start of a patch + if (!$in_commit_log && + ($line =~ /^ mode change [0-7]+ => [0-7]+ \S+\s*$/ || + ($line =~ /^rename (?:from|to) \S+\s*$/ || + $line =~ /^diff --git a\/[\w\/\.\_\-]+ b\/\S+\s*$/))) { + $is_patch = 1; + } #extract the line range in the file after the patch is applied - if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + if (!$in_commit_log && + $line =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@(.*)/) { + my $context = $4; $is_patch = 1; $first_line = $linenr + 1; $realline=$1-1; @@ -1463,6 +2870,12 @@ sub process { %suppress_ifbraces = (); %suppress_whiletrailers = (); %suppress_export = (); + $suppress_statement = 0; + if ($context =~ /\b(\w+)\s*\(/) { + $context_function = $1; + } else { + undef $context_function; + } next; # track the line number as we move through the hunk, note that @@ -1488,21 +2901,20 @@ sub process { my $hunk_line = ($realcnt != 0); -#make up the handle for any error we report on this line - $prefix = "$filename:$realline: " if ($emacs && $file); - $prefix = "$filename:$linenr: " if ($emacs && !$file); - $here = "#$linenr: " if (!$file); $here = "#$realline: " if ($file); + my $found_file = 0; # extract the filename as it passes if ($line =~ /^diff --git.*?(\S+)$/) { $realfile = $1; - $realfile =~ s@^([^/]*)/@@; - + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + $found_file = 1; } elsif ($line =~ /^\+\+\+\s+(\S+)/) { $realfile = $1; - $realfile =~ s@^([^/]*)/@@; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; $p1_prefix = $1; if (!$file && $tree && $p1_prefix ne '' && @@ -1515,6 +2927,44 @@ sub process { ERROR("MODIFIED_INCLUDE_ASM", "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n"); } + $found_file = 1; + } + +#make up the handle for any error we report on this line + if ($showfile) { + $prefix = "$realfile:$realline: " + } elsif ($emacs) { + if ($file) { + $prefix = "$filename:$realline: "; + } else { + $prefix = "$filename:$linenr: "; + } + } + + if ($found_file) { + if (is_maintained_obsolete($realfile)) { + WARN("OBSOLETE", + "$realfile is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please.\n"); + } + if ($realfile =~ m@^(?:drivers/net/|net/|drivers/staging/)@) { + $check = 1; + } else { + $check = $check_orig; + } + $checklicenseline = 1; + + if ($realfile !~ /^MAINTAINERS/) { + my $last_binding_patch = $is_binding_patch; + + $is_binding_patch = () = $realfile =~ m@^(?:Documentation/devicetree/|include/dt-bindings/)@; + + if (($last_binding_patch != -1) && + ($last_binding_patch ^ $is_binding_patch)) { + WARN("DT_SPLIT_BINDING_PATCH", + "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst\n"); + } + } + next; } @@ -1526,43 +2976,159 @@ sub process { $cnt_lines++ if ($realcnt != 0); +# Verify the existence of a commit log if appropriate +# 2 is used because a $signature is counted in $commit_log_lines + if ($in_commit_log) { + if ($line !~ /^\s*$/) { + $commit_log_lines++; #could be a $signature + } + } elsif ($has_commit_log && $commit_log_lines < 2) { + WARN("COMMIT_MESSAGE", + "Missing commit description - Add an appropriate one\n"); + $commit_log_lines = 2; #warn only once + } + +# Check if the commit log has what seems like a diff which can confuse patch + if ($in_commit_log && !$commit_log_has_diff && + (($line =~ m@^\s+diff\b.*a/([\w/]+)@ && + $line =~ m@^\s+diff\b.*a/[\w/]+\s+b/$1\b@) || + $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ || + $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) { + ERROR("DIFF_IN_COMMIT_MSG", + "Avoid using diff content in the commit message - patch(1) might not work\n" . $herecurr); + $commit_log_has_diff = 1; + } + # Check for incorrect file permissions if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { my $permhere = $here . "FILE: $realfile\n"; - if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) { + if ($realfile !~ m@scripts/@ && + $realfile !~ /\.(py|pl|awk|sh)$/) { ERROR("EXECUTE_PERMISSIONS", "do not set execute permissions for source files\n" . $permhere); } } +# Check the patch for a From: + if (decode("MIME-Header", $line) =~ /^From:\s*(.*)/) { + $author = $1; + my $curline = $linenr; + while(defined($rawlines[$curline]) && ($rawlines[$curline++] =~ /^[ \t]\s*(.*)/)) { + $author .= $1; + } + $author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i); + $author =~ s/"//g; + $author = reformat_email($author); + } + # Check the patch for a signoff: - if ($line =~ /^\s*signed-off-by:/i) { + if ($line =~ /^\s*signed-off-by:\s*(.*)/i) { $signoff++; + $in_commit_log = 0; + if ($author ne '' && $authorsignoff != 1) { + if (same_email_addresses($1, $author)) { + $authorsignoff = 1; + } else { + my $ctx = $1; + my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx); + my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author); + + if (lc $email_address eq lc $author_address && $email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 2; + } elsif (lc $email_address eq lc $author_address) { + $author_sob = $ctx; + $authorsignoff = 3; + } elsif ($email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 4; + + my $address1 = $email_address; + my $address2 = $author_address; + + if ($address1 =~ /(\S+)\+\S+(\@.*)/) { + $address1 = "$1$2"; + } + if ($address2 =~ /(\S+)\+\S+(\@.*)/) { + $address2 = "$1$2"; + } + if ($address1 eq $address2) { + $authorsignoff = 5; + } + } + } + } + } + +# OpenOCD specific: Begin: Extend list of checkpatch tests to ignore + if ($in_commit_log && $line =~ /^\s*Checkpatch-ignore:\s*(.*)/) { + my @array = split(/[\s,]+/, $1); + hash_save_array_words(\%ignore_type, \@array); + } +# OpenOCD specific: End + +# Check for patch separator + if ($line =~ /^---$/) { + $has_patch_separator = 1; + $in_commit_log = 0; + } + +# Check if MAINTAINERS is being updated. If so, there's probably no need to +# emit the "does MAINTAINERS need updating?" message on file add/move/delete + if ($line =~ /^\s*MAINTAINERS\s*\|/) { + $reported_maintainer_file = 1; } # Check signature styles - if ($line =~ /^(\s*)($signature_tags)(\s*)(.*)/) { + if (!$in_header_lines && + $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { my $space_before = $1; my $sign_off = $2; my $space_after = $3; my $email = $4; my $ucfirst_sign_off = ucfirst(lc($sign_off)); + if ($sign_off !~ /$signature_tags/) { + my $suggested_signature = find_standard_signature($sign_off); + if ($suggested_signature eq "") { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } else { + if (WARN("BAD_SIGN_OFF", + "Non-standard signature: '$sign_off' - perhaps '$suggested_signature'?\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/$sign_off/$suggested_signature/; + } + } + } if (defined $space_before && $space_before ne "") { - WARN("BAD_SIGN_OFF", - "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } } if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { - WARN("BAD_SIGN_OFF", - "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + } if (!defined $space_after || $space_after ne " ") { - WARN("BAD_SIGN_OFF", - "Use a single space after $ucfirst_sign_off\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "Use a single space after $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } } - my ($email_name, $email_address, $comment) = parse_email($email); - my $suggested_email = format_email(($email_name, $email_address)); + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); + my $suggested_email = format_email(($email_name, $name_comment, $email_address, $comment)); if ($suggested_email eq "") { ERROR("BAD_SIGN_OFF", "Unrecognized email address: '$email'\n" . $herecurr); @@ -1572,36 +3138,274 @@ sub process { $dequoted =~ s/" </ </; # Don't force email to have quotes # Allow just an angle bracketed address - if ("$dequoted$comment" ne $email && - "<$email_address>$comment" ne $email && - "$suggested_email$comment" ne $email) { + if (!same_email_addresses($email, $suggested_email)) { + if (WARN("BAD_SIGN_OFF", + "email address '$email' might be better as '$suggested_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$suggested_email/; + } + } + + # Address part shouldn't have comments + my $stripped_address = $email_address; + $stripped_address =~ s/\([^\(\)]*\)//g; + if ($email_address ne $stripped_address) { + if (WARN("BAD_SIGN_OFF", + "address part of email should not have comments: '$email_address'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email_address\E/$stripped_address/; + } + } + + # Only one name comment should be allowed + my $comment_count = () = $name_comment =~ /\([^\)]+\)/g; + if ($comment_count > 1) { WARN("BAD_SIGN_OFF", - "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); + "Use a single name comment in email: '$email'\n" . $herecurr); + } + + + # stable@vger.kernel.org or stable@kernel.org shouldn't + # have an email name. In addition comments should strictly + # begin with a # + if ($email =~ /^.*stable\@(?:vger\.)?kernel\.org/i) { + if (($comment ne "" && $comment !~ /^#.+/) || + ($email_name ne "")) { + my $cur_name = $email_name; + my $new_comment = $comment; + $cur_name =~ s/[a-zA-Z\s\-\"]+//g; + + # Remove brackets enclosing comment text + # and # from start of comments to get comment text + $new_comment =~ s/^\((.*)\)$/$1/; + $new_comment =~ s/^\[(.*)\]$/$1/; + $new_comment =~ s/^[\s\#]+|\s+$//g; + + $new_comment = trim("$new_comment $cur_name") if ($cur_name ne $new_comment); + $new_comment = " # $new_comment" if ($new_comment ne ""); + my $new_email = "$email_address$new_comment"; + + if (WARN("BAD_STABLE_ADDRESS_STYLE", + "Invalid email format for stable: '$email', prefer '$new_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; + } + } + } elsif ($comment ne "" && $comment !~ /^(?:#.+|\(.+\))$/) { + my $new_comment = $comment; + + # Extract comment text from within brackets or + # c89 style /*...*/ comments + $new_comment =~ s/^\[(.*)\]$/$1/; + $new_comment =~ s/^\/\*(.*)\*\/$/$1/; + + $new_comment = trim($new_comment); + $new_comment =~ s/^[^\w]$//; # Single lettered comment with non word character is usually a typo + $new_comment = "($new_comment)" if ($new_comment ne ""); + my $new_email = format_email($email_name, $name_comment, $email_address, $new_comment); + + if (WARN("BAD_SIGN_OFF", + "Unexpected content after email: '$email', should be: '$new_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; + } } } - } -# Check for wrappage within a valid hunk of the file - if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { - ERROR("CORRUPTED_PATCH", - "patch seems to be corrupt (line wrapped?)\n" . - $herecurr) if (!$emitted_corrupt++); +# Check for duplicate signatures + my $sig_nospace = $line; + $sig_nospace =~ s/\s//g; + $sig_nospace = lc($sig_nospace); + if (defined $signatures{$sig_nospace}) { + WARN("BAD_SIGN_OFF", + "Duplicate signature\n" . $herecurr); + } else { + $signatures{$sig_nospace} = 1; + } + +# Check Co-developed-by: immediately followed by Signed-off-by: with same name and email + if ($sign_off =~ /^co-developed-by:$/i) { + if ($email eq $author) { + WARN("BAD_SIGN_OFF", + "Co-developed-by: should not be used to attribute nominal patch author '$author'\n" . "$here\n" . $rawline); + } + if (!defined $lines[$linenr]) { + WARN("BAD_SIGN_OFF", + "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline); + } elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) { + WARN("BAD_SIGN_OFF", + "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]); + } elsif ($1 ne $email) { + WARN("BAD_SIGN_OFF", + "Co-developed-by and Signed-off-by: name/email do not match \n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]); + } + } } -# Check for absolute kernel paths. - if ($tree) { - while ($line =~ m{(?:^|\s)(/\S*)}g) { - my $file = $1; +# Check email subject for common tools that don't need to be mentioned + if ($in_header_lines && + $line =~ /^Subject:.*\b(?:checkpatch|sparse|smatch)\b[^:]/i) { + WARN("EMAIL_SUBJECT", + "A patch subject line should describe the change not the tool that found it\n" . $herecurr); + } - if ($file =~ m{^(.*?)(?::\d+)+:?$} && - check_absolute_file($1, $herecurr)) { - # - } else { - check_absolute_file($file, $herecurr); - } +# Check for Gerrit Change-Ids not in any patch context + if ($realfile eq '' && !$has_patch_separator && $line =~ /^\s*change-id:/i) { + # OpenOCD specific: Begin: exclude gerrit's Change-Id line from commit description + $in_commit_log = 0; + # OpenOCD specific: End + if (ERROR("GERRIT_CHANGE_ID", + "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); } } +# Check if the commit log is in a possible stack dump + if ($in_commit_log && !$commit_log_possible_stack_dump && + ($line =~ /^\s*(?:WARNING:|BUG:)/ || + $line =~ /^\s*\[\s*\d+\.\d{6,6}\s*\]/ || + # timestamp + $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/) || + $line =~ /^(?:\s+\w+:\s+[0-9a-fA-F]+){3,3}/ || + $line =~ /^\s*\#\d+\s*\[[0-9a-fA-F]+\]\s*\w+ at [0-9a-fA-F]+/) { + # stack dump address styles + $commit_log_possible_stack_dump = 1; + } + +# Check for line lengths > 75 in commit log, warn once + if ($in_commit_log && !$commit_log_long_line && + length($line) > 75 && + !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ || + # file delta changes + $line =~ /^\s*(?:[\w\.\-\+]*\/)++[\w\.\-\+]+:/ || + # filename then : + $line =~ /^\s*(?:Fixes:|Link:|$signature_tags)/i || + # A Fixes: or Link: line or signature tag line + $commit_log_possible_stack_dump)) { + WARN("COMMIT_LOG_LONG_LINE", + "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr); + $commit_log_long_line = 1; + } + +# Reset possible stack dump if a blank line is found + if ($in_commit_log && $commit_log_possible_stack_dump && + $line =~ /^\s*$/) { + $commit_log_possible_stack_dump = 0; + } + +# Check for lines starting with a # + if ($in_commit_log && $line =~ /^#/) { + if (WARN("COMMIT_COMMENT_SYMBOL", + "Commit log lines starting with '#' are dropped by git as comments\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^/ /; + } + } + +# Check for git id commit length and improperly formed commit descriptions +# A correctly formed commit description is: +# commit <SHA-1 hash length 12+ chars> ("Complete commit subject") +# with the commit subject '("' prefix and '")' suffix +# This is a fairly compilicated block as it tests for what appears to be +# bare SHA-1 hash with minimum length of 5. It also avoids several types of +# possible SHA-1 matches. +# A commit match can span multiple lines so this block attempts to find a +# complete typical commit on a maximum of 3 lines + if ($perl_version_ok && + $in_commit_log && !$commit_log_possible_stack_dump && + $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i && + $line !~ /^This reverts commit [0-9a-f]{7,40}/ && + (($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i || + ($line =~ /\bcommit\s*$/i && defined($rawlines[$linenr]) && $rawlines[$linenr] =~ /^\s*[0-9a-f]{5,}\b/i)) || + ($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i && + $line !~ /[\<\[][0-9a-f]{12,40}[\>\]]/i && + $line !~ /\bfixes:\s*[0-9a-f]{12,40}/i))) { + my $init_char = "c"; + my $orig_commit = ""; + my $short = 1; + my $long = 0; + my $case = 1; + my $space = 1; + my $id = '0123456789ab'; + my $orig_desc = "commit description"; + my $description = ""; + my $herectx = $herecurr; + my $has_parens = 0; + my $has_quotes = 0; + + my $input = $line; + if ($line =~ /(?:\bcommit\s+[0-9a-f]{5,}|\bcommit\s*$)/i) { + for (my $n = 0; $n < 2; $n++) { + if ($input =~ /\bcommit\s+[0-9a-f]{5,}\s*($balanced_parens)/i) { + $orig_desc = $1; + $has_parens = 1; + # Always strip leading/trailing parens then double quotes if existing + $orig_desc = substr($orig_desc, 1, -1); + if ($orig_desc =~ /^".*"$/) { + $orig_desc = substr($orig_desc, 1, -1); + $has_quotes = 1; + } + last; + } + last if ($#lines < $linenr + $n); + $input .= " " . trim($rawlines[$linenr + $n]); + $herectx .= "$rawlines[$linenr + $n]\n"; + } + $herectx = $herecurr if (!$has_parens); + } + + if ($input =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) { + $init_char = $1; + $orig_commit = lc($2); + $short = 0 if ($input =~ /\bcommit\s+[0-9a-f]{12,40}/i); + $long = 1 if ($input =~ /\bcommit\s+[0-9a-f]{41,}/i); + $space = 0 if ($input =~ /\bcommit [0-9a-f]/i); + $case = 0 if ($input =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/); + } elsif ($input =~ /\b([0-9a-f]{12,40})\b/i) { + $orig_commit = lc($1); + } + + ($id, $description) = git_commit_info($orig_commit, + $id, $orig_desc); + + if (defined($id) && + ($short || $long || $space || $case || ($orig_desc ne $description) || !$has_quotes) && + $last_git_commit_id_linenr != $linenr - 1) { + ERROR("GIT_COMMIT_ID", + "Please use git commit description style 'commit <12+ chars of sha1> (\"<title line>\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herectx); + } + #don't report the next line if this line ends in commit and the sha1 hash is the next line + $last_git_commit_id_linenr = $linenr if ($line =~ /\bcommit\s*$/i); + } + +# Check for added, moved or deleted files + if (!$reported_maintainer_file && !$in_commit_log && + ($line =~ /^(?:new|deleted) file mode\s*\d+\s*$/ || + $line =~ /^rename (?:from|to) [\w\/\.\-]+\s*$/ || + ($line =~ /\{\s*([\w\/\.\-]*)\s*\=\>\s*([\w\/\.\-]*)\s*\}/ && + (defined($1) || defined($2))))) { + $is_patch = 1; + $reported_maintainer_file = 1; + WARN("FILE_PATH_CHANGES", + "added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr); + } + +# Check for adding new DT bindings not in schema format + if (!$in_commit_log && + ($line =~ /^new file mode\s*\d+\s*$/) && + ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) { + WARN("DT_SCHEMA_BINDING_PATCH", + "DT bindings should be in DT schema format. See: Documentation/devicetree/bindings/writing-schema.rst\n"); + } + +# Check for wrappage within a valid hunk of the file + if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { + ERROR("CORRUPTED_PATCH", + "patch seems to be corrupt (line wrapped?)\n" . + $herecurr) if (!$emitted_corrupt++); + } + # UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php if (($realfile =~ /^$/ || $line =~ /^\+/) && $rawline !~ m/^$UTF8*$/) { @@ -1615,136 +3419,766 @@ sub process { "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); } +# Check if it's the start of a commit log +# (not a header line and we haven't seen the patch filename) + if ($in_header_lines && $realfile =~ /^$/ && + !($rawline =~ /^\s+(?:\S|$)/ || + $rawline =~ /^(?:commit\b|from\b|[\w-]+:)/i)) { + $in_header_lines = 0; + $in_commit_log = 1; + $has_commit_log = 1; + } + +# Check if there is UTF-8 in a commit log when a mail header has explicitly +# declined it, i.e defined some charset where it is missing. + if ($in_header_lines && + $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && + $1 !~ /utf-8/i) { + $non_utf8_charset = 1; + } + + if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && + $rawline =~ /$NON_ASCII_UTF8/) { + WARN("UTF8_BEFORE_PATCH", + "8-bit UTF-8 used in possible commit log\n" . $herecurr); + } + +# Check for absolute kernel paths in commit message + if ($tree && $in_commit_log) { + while ($line =~ m{(?:^|\s)(/\S*)}g) { + my $file = $1; + + if ($file =~ m{^(.*?)(?::\d+)+:?$} && + check_absolute_file($1, $herecurr)) { + # + } else { + check_absolute_file($file, $herecurr); + } + } + } + +# Check for various typo / spelling mistakes + if (defined($misspellings) && + # OpenOCD specific: Begin: don't check spelling on spelling_file + index($spelling_file, $realfile) + length($realfile) != length($spelling_file) && + # OpenOCD specific: End + ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { + while ($rawline =~ /(?:^|[^\w\-'`])($misspellings)(?:[^\w\-'`]|$)/gi) { + my $typo = $1; + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, $-[1]) . "^" x length($typo); + my $hereptr = "$hereline$ptr\n"; + my $typo_fix = $spelling_fix{lc($typo)}; + $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); + $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("TYPO_SPELLING", + "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $hereptr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; + } + } + } + +# check for invalid commit id + if ($in_commit_log && $line =~ /(^fixes:|\bcommit)\s+([0-9a-f]{6,40})\b/i) { + my $id; + my $description; + ($id, $description) = git_commit_info($2, undef, undef); + if (!defined($id)) { + WARN("UNKNOWN_COMMIT_ID", + "Unknown commit id '$2', maybe rebased or not pulled?\n" . $herecurr); + } + } + +# check for repeated words separated by a single space +# avoid false positive from list command eg, '-rw-r--r-- 1 root root' + if (($rawline =~ /^\+/ || $in_commit_log) && + $rawline !~ /[bcCdDlMnpPs\?-][rwxsStT-]{9}/) { + pos($rawline) = 1 if (!$in_commit_log); + while ($rawline =~ /\b($word_pattern) (?=($word_pattern))/g) { + + my $first = $1; + my $second = $2; + my $start_pos = $-[1]; + my $end_pos = $+[2]; + if ($first =~ /(?:struct|union|enum)/) { + pos($rawline) += length($first) + length($second) + 1; + next; + } + + next if (lc($first) ne lc($second)); + next if ($first eq 'long'); + + # check for character before and after the word matches + my $start_char = ''; + my $end_char = ''; + $start_char = substr($rawline, $start_pos - 1, 1) if ($start_pos > ($in_commit_log ? 0 : 1)); + $end_char = substr($rawline, $end_pos, 1) if ($end_pos < length($rawline)); + + next if ($start_char =~ /^\S$/); + next if (index(" \t.,;?!", $end_char) == -1); + + # avoid repeating hex occurrences like 'ff ff fe 09 ...' + if ($first =~ /\b[0-9a-f]{2,}\b/i) { + next if (!exists($allow_repeated_words{lc($first)})); + } + + if (WARN("REPEATED_WORD", + "Possible repeated word: '$first'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$first $second\b/$first/; + } + } + + # if it's a repeated word on consecutive lines in a comment block + if ($prevline =~ /$;+\s*$/ && + $prevrawline =~ /($word_pattern)\s*$/) { + my $last_word = $1; + if ($rawline =~ /^\+\s*\*\s*$last_word /) { + if (WARN("REPEATED_WORD", + "Possible repeated word: '$last_word'\n" . $hereprev) && + $fix) { + $fixed[$fixlinenr] =~ s/(\+\s*\*\s*)$last_word /$1/; + } + } + } + } + # ignore non-hunk lines and lines being removed next if (!$hunk_line || $line =~ /^-/); #trailing whitespace if ($line =~ /^\+.*\015/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("DOS_LINE_ENDINGS", - "DOS line endings\n" . $herevet); - + if (ERROR("DOS_LINE_ENDINGS", + "DOS line endings\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/[\s\015]+$//; + } } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("TRAILING_WHITESPACE", - "trailing whitespace\n" . $herevet); + if (ERROR("TRAILING_WHITESPACE", + "trailing whitespace\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } + $rpt_cleaners = 1; } +# Check for FSF mailing addresses. if ($rawline =~ /\bwrite to the Free/i || + $rawline =~ /\b675\s+Mass\s+Ave/i || $rawline =~ /\b59\s+Temple\s+Pl/i || $rawline =~ /\b51\s+Franklin\s+St/i) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("FSF_MAILING_ADDRESS", - "Do not include the paragraph about writing to the Free Software Foundation's mailing address " . - "from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. " . - "OpenOCD already includes a copy of the GPL.\n" . $herevet) + my $msg_level = \&ERROR; + $msg_level = \&CHK if ($file); + &{$msg_level}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. OpenOCD already includes a copy of the GPL.\n" . $herevet) } # check for Kconfig help text having a real description # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. if ($realfile =~ /Kconfig/ && - $line =~ /\+\s*(?:---)?help(?:---)?$/) { - my $length = 0; - my $cnt = $realcnt; - my $ln = $linenr + 1; - my $f; - my $is_end = 0; - while ($cnt > 0 && defined $lines[$ln - 1]) { - $f = $lines[$ln - 1]; - $cnt-- if ($lines[$ln - 1] !~ /^-/); - $is_end = $lines[$ln - 1] =~ /^\+/; - $ln++; + # 'choice' is usually the last thing on the line (though + # Kconfig supports named choices), so use a word boundary + # (\b) rather than a whitespace character (\s) + $line =~ /^\+\s*(?:config|menuconfig|choice)\b/) { + my $ln = $linenr; + my $needs_help = 0; + my $has_help = 0; + my $help_length = 0; + while (defined $lines[$ln]) { + my $f = $lines[$ln++]; next if ($f =~ /^-/); - $f =~ s/^.//; - $f =~ s/#.*//; - $f =~ s/^\s+//; - next if ($f =~ /^$/); - if ($f =~ /^\s*config\s/) { - $is_end = 1; + last if ($f !~ /^[\+ ]/); # !patch context + + if ($f =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) { + $needs_help = 1; + next; + } + if ($f =~ /^\+\s*help\s*$/) { + $has_help = 1; + next; + } + + $f =~ s/^.//; # strip patch context [+ ] + $f =~ s/#.*//; # strip # directives + $f =~ s/^\s+//; # strip leading blanks + next if ($f =~ /^$/); # skip blank lines + + # At the end of this Kconfig block: + # This only checks context lines in the patch + # and so hopefully shouldn't trigger false + # positives, even though some of these are + # common words in help texts + if ($f =~ /^(?:config|menuconfig|choice|endchoice| + if|endif|menu|endmenu|source)\b/x) { last; } - $length++; + $help_length++ if ($has_help); + } + if ($needs_help && + $help_length < $min_conf_desc_length) { + my $stat_real = get_stat_real($linenr, $ln - 1); + WARN("CONFIG_DESCRIPTION", + "please write a help paragraph that fully describes the config symbol\n" . "$here\n$stat_real\n"); + } + } + +# check MAINTAINERS entries + if ($realfile =~ /^MAINTAINERS$/) { +# check MAINTAINERS entries for the right form + if ($rawline =~ /^\+[A-Z]:/ && + $rawline !~ /^\+[A-Z]:\t\S/) { + if (WARN("MAINTAINERS_STYLE", + "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; + } + } +# check MAINTAINERS entries for the right ordering too + my $preferred_order = 'MRLSWQBCPTFXNK'; + if ($rawline =~ /^\+[A-Z]:/ && + $prevrawline =~ /^[\+ ][A-Z]:/) { + $rawline =~ /^\+([A-Z]):\s*(.*)/; + my $cur = $1; + my $curval = $2; + $prevrawline =~ /^[\+ ]([A-Z]):\s*(.*)/; + my $prev = $1; + my $prevval = $2; + my $curindex = index($preferred_order, $cur); + my $previndex = index($preferred_order, $prev); + if ($curindex < 0) { + WARN("MAINTAINERS_STYLE", + "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr); + } else { + if ($previndex >= 0 && $curindex < $previndex) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev); + } elsif ((($prev eq 'F' && $cur eq 'F') || + ($prev eq 'X' && $cur eq 'X')) && + ($prevval cmp $curval) > 0) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev); + } + } + } + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && + ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { + my $flag = $1; + my $replacement = { + 'EXTRA_AFLAGS' => 'asflags-y', + 'EXTRA_CFLAGS' => 'ccflags-y', + 'EXTRA_CPPFLAGS' => 'cppflags-y', + 'EXTRA_LDFLAGS' => 'ldflags-y', + }; + + WARN("DEPRECATED_VARIABLE", + "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); + } + +# check for DT compatible documentation + if (defined $root && + (($realfile =~ /\.dtsi?$/ && $line =~ /^\+\s*compatible\s*=\s*\"/) || + ($realfile =~ /\.[ch]$/ && $line =~ /^\+.*\.compatible\s*=\s*\"/))) { + + my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; + + my $dt_path = $root . "/Documentation/devicetree/bindings/"; + my $vp_file = $dt_path . "vendor-prefixes.yaml"; + + foreach my $compat (@compats) { + my $compat2 = $compat; + $compat2 =~ s/\,[a-zA-Z0-9]*\-/\,<\.\*>\-/; + my $compat3 = $compat; + $compat3 =~ s/\,([a-z]*)[0-9]*\-/\,$1<\.\*>\-/; + `grep -Erq "$compat|$compat2|$compat3" $dt_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr); + } + + next if $compat !~ /^([a-zA-Z0-9\-]+)\,/; + my $vendor = $1; + `grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr); + } + } + } + +# check for using SPDX license tag at beginning of files + if ($realline == $checklicenseline) { + if ($rawline =~ /^[ \+]\s*\#\!\s*\//) { + $checklicenseline = 2; + } elsif ($rawline =~ /^\+/) { + my $comment = ""; + if ($realfile =~ /\.(h|s|S)$/) { + $comment = '/*'; + } elsif ($realfile =~ /\.(c|dts|dtsi)$/) { + $comment = '//'; + } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc|yaml)$/) { + $comment = '#'; + } elsif ($realfile =~ /\.rst$/) { + $comment = '..'; + # OpenOCD specific: Begin + } elsif (($realfile =~ /\.(am|cfg|tcl)$/) || ($realfile =~ /\/Makefile$/)) { + $comment = '#'; + } elsif ($realfile =~ /\.(ld)$/) { + $comment = '/*'; + # OpenOCD specific: End + } + +# check SPDX comment style for .[chsS] files + if ($realfile =~ /\.[chsS]$/ && + $rawline =~ /SPDX-License-Identifier:/ && + $rawline !~ m@^\+\s*\Q$comment\E\s*@) { + WARN("SPDX_LICENSE_TAG", + "Improper SPDX comment style for '$realfile', please use '$comment' instead\n" . $herecurr); + } + + if ($comment !~ /^$/ && + $rawline !~ m@^\+\Q$comment\E SPDX-License-Identifier: @) { + WARN("SPDX_LICENSE_TAG", + "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr); + } elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) { + my $spdx_license = $1; + if (!is_SPDX_License_valid($spdx_license)) { + WARN("SPDX_LICENSE_TAG", + "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr); + } + if ($realfile =~ m@^Documentation/devicetree/bindings/@ && + not $spdx_license =~ /GPL-2\.0.*BSD-2-Clause/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("SPDX_LICENSE_TAG", + + "DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/SPDX-License-Identifier: .*/SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)/; + } + } + } } - WARN("CONFIG_DESCRIPTION", - "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_end && $length < 4); - #print "is_end<$is_end> length<$length>\n"; + } + +# check for embedded filenames + if ($rawline =~ /^\+.*\Q$realfile\E/) { + WARN("EMBEDDED_FILENAME", + "It's generally not useful to have the filename in the file\n" . $herecurr); } # check we are in a valid source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); - -#120 column limit - if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && - $rawline !~ /^.\s*\*\s*\@$Ident\s/ && - !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || - $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && - $length > 120) - { - WARN("LONG_LINE", - "line over 120 characters\n" . $herecurr); + if (!$OpenOCD) { + next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); + } else { # !$OpenOCD + next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts|tcl|cfg|ac|am)$/); + } # !$OpenOCD + +# check for using SPDX-License-Identifier on the wrong line number + if ($realline != $checklicenseline && + $rawline =~ /\bSPDX-License-Identifier:/ && + substr($line, @-, @+ - @-) eq "$;" x (@+ - @-)) { + WARN("SPDX_LICENSE_TAG", + "Misplaced SPDX-License-Identifier tag - use line $checklicenseline instead\n" . $herecurr); } -# check for spaces before a quoted newline - if ($rawline =~ /^.*\".*\s\\n/) { - WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", - "unnecessary whitespace before a quoted newline\n" . $herecurr); +# line length limit (with some exclusions) +# +# There are a few types of lines that may extend beyond $max_line_length: +# logging functions like pr_info that end in a string +# lines with a single string +# #defines that are a single string +# lines with an RFC3986 like URL +# +# There are 3 different line length message types: +# LONG_LINE_COMMENT a comment starts before but extends beyond $max_line_length +# LONG_LINE_STRING a string starts before but extends beyond $max_line_length +# LONG_LINE all other lines longer than $max_line_length +# +# if LONG_LINE is ignored, the other 2 types are also ignored +# + + if ($line =~ /^\+/ && $length > $max_line_length) { + my $msg_type = "LONG_LINE"; + + # Check the allowed long line types first + + # logging functions that end in a string that starts + # before $max_line_length + if ($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(?:KERN_\S+\s*|[^"]*))?($String\s*(?:|,|\)\s*;)\s*)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = ""; + + # lines with only strings (w/ possible termination) + # #defines with only strings + } elsif ($line =~ /^\+\s*$String\s*(?:\s*|,|\)\s*;)\s*$/ || + $line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) { + $msg_type = ""; + + # More special cases + } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/ || + $line =~ /^\+\s*(?:\w+)?\s*DEFINE_PER_CPU/) { + $msg_type = ""; + + # URL ($rawline is used in case the URL is in a comment) + } elsif ($rawline =~ /^\+.*\b[a-z][\w\.\+\-]*:\/\/\S+/i) { + $msg_type = ""; + + # Otherwise set the alternate message types + + # a comment starts before $max_line_length + } elsif ($line =~ /($;[\s$;]*)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = "LONG_LINE_COMMENT" + + # a quoted string starts before $max_line_length + } elsif ($sline =~ /\s*($String(?:\s*(?:\\|,\s*|\)\s*;\s*))?)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = "LONG_LINE_STRING" + } + + if ($msg_type ne "" && + (show_type("LONG_LINE") || show_type($msg_type))) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}($msg_type, + "line length of $length exceeds $max_line_length columns\n" . $herecurr); + } } # check for adding lines without a newline. if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { - WARN("MISSING_EOF_NEWLINE", - "adding a line without newline at end of file\n" . $herecurr); + if (WARN("MISSING_EOF_NEWLINE", + "adding a line without newline at end of file\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr+1, "No newline at end of file"); + } } -# Blackfin: use hi/lo macros - if ($realfile =~ m@arch/blackfin/.*\.S$@) { - if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("LO_MACRO", - "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); - } - if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("HI_MACRO", - "use the HI() macro, not (... >> 16)\n" . $herevet); - } +# check for .L prefix local symbols in .S files + if ($realfile =~ /\.S$/ && + $line =~ /^\+\s*(?:[A-Z]+_)?SYM_[A-Z]+_(?:START|END)(?:_[A-Z_]+)?\s*\(\s*\.L/) { + WARN("AVOID_L_PREFIX", + "Avoid using '.L' prefixed local symbol names for denoting a range of code via 'SYM_*_START/END' annotations; see Documentation/asm-annotations.rst\n" . $herecurr); } # check we are in a valid source file C or perl if not then ignore this hunk - next if ($realfile !~ /\.(h|c|pl)$/); + next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); # at the beginning of a line any tabs must come first and anything -# more than 8 must use tabs. +# more than $tabsize must use tabs. if ($rawline =~ /^\+\s* \t\s*\S/ || $rawline =~ /^\+\s* \s*/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("CODE_INDENT", - "code indent should use tabs where possible\n" . $herevet); $rpt_cleaners = 1; + if (ERROR("CODE_INDENT", + "code indent should use tabs where possible\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } } # check for space before tabs. if ($rawline =~ /^\+/ && $rawline =~ / \t/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("SPACE_BEFORE_TAB", - "please, no space before tabs\n" . $herevet); + if (WARN("SPACE_BEFORE_TAB", + "please, no space before tabs\n" . $herevet) && + $fix) { + while ($fixed[$fixlinenr] =~ + s/(^\+.*) {$tabsize,$tabsize}\t/$1\t\t/) {} + while ($fixed[$fixlinenr] =~ + s/(^\+.*) +\t/$1\t/) {} + } } -# check we are in a valid C source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c)$/); +# check for assignments on the start of a line + if ($sline =~ /^\+\s+($Assignment)[^=]/) { + my $operator = $1; + if (CHK("ASSIGNMENT_CONTINUATIONS", + "Assignment operator '$1' should be on the previous line\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + # add assignment operator to the previous line, remove from current line + $fixed[$fixlinenr - 1] .= " $operator"; + $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; + } + } + +# check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { + my $operator = $1; + if (CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + # insert logical operator at last non-comment, non-whitepsace char on previous line + $prevline =~ /[\s$;]*$/; + my $line_end = substr($prevrawline, $-[0]); + $fixed[$fixlinenr - 1] =~ s/\Q$line_end\E$/ $operator$line_end/; + $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; + } + } + +# check indentation starts on a tab stop + if ($perl_version_ok && + $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) { + my $indent = length($1); + if ($indent % $tabsize) { + if (WARN("TABSTOP", + "Statements should start on a tabstop\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/$tabsize)@e; + } + } + } + +# check multi-line statement indentation matches previous line + if ($perl_version_ok && + $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|(?:\*\s*)*$Lval\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) { + $prevline =~ /^\+(\t*)(.*)$/; + my $oldindent = $1; + my $rest = $2; + + my $pos = pos_last_openparen($rest); + if ($pos >= 0) { + $line =~ /^(\+| )([ \t]*)/; + my $newindent = $2; + + my $goodtabindent = $oldindent . + "\t" x ($pos / $tabsize) . + " " x ($pos % $tabsize); + my $goodspaceindent = $oldindent . " " x $pos; + + if ($newindent ne $goodtabindent && + $newindent ne $goodspaceindent) { + + if (CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev) && + $fix && $line =~ /^\+/) { + $fixed[$fixlinenr] =~ + s/^\+[ \t]*/\+$goodtabindent/; + } + } + } + } + +# check for space after cast like "(int) foo" or "(struct foo) bar" +# avoid checking a few false positives: +# "sizeof(<type>)" or "__alignof__(<type>)" +# function pointer declarations like "(*foo)(int) = bar;" +# structure definitions like "(struct foo) { 0 };" +# multiline macros that define functions +# known attributes or the __attribute__ keyword + if ($line =~ /^\+(.*)\(\s*$Type\s*\)([ \t]++)((?![={]|\\$|$Attribute|__attribute__))/ && + (!defined($1) || $1 !~ /\b(?:sizeof|__alignof__)\s*$/)) { + if (CHK("SPACING", + "No space is necessary after a cast\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/(\(\s*$Type\s*\))[ \t]+/$1/; + } + } + +# Block comment styles +# Networking with an initial /* + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/ && + $realline > 3) { # Do not warn about the initial copyright comment block after SPDX-License-Identifier + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } + +# Block comments use * on subsequent lines + if ($prevline =~ /$;[ \t]*$/ && #ends in comment + $prevrawline =~ /^\+.*?\/\*/ && #starting /* + $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */ + $rawline =~ /^\+/ && #line is new + $rawline !~ /^\+[ \t]*\*/) { #no leading * + WARN("BLOCK_COMMENT_STYLE", + "Block comments use * on subsequent lines\n" . $hereprev); + } + +# Block comments use */ on trailing lines + if ($rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ + $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ + $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ + $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ + WARN("BLOCK_COMMENT_STYLE", + "Block comments use a trailing */ on a separate line\n" . $herecurr); + } + +# Block comment * alignment + if ($prevline =~ /$;[ \t]*$/ && #ends in comment + $line =~ /^\+[ \t]*$;/ && #leading comment + $rawline =~ /^\+[ \t]*\*/ && #leading * + (($prevrawline =~ /^\+.*?\/\*/ && #leading /* + $prevrawline !~ /\*\/[ \t]*$/) || #no trailing */ + $prevrawline =~ /^\+[ \t]*\*/)) { #leading * + my $oldindent; + $prevrawline =~ m@^\+([ \t]*/?)\*@; + if (defined($1)) { + $oldindent = expand_tabs($1); + } else { + $prevrawline =~ m@^\+(.*/?)\*@; + $oldindent = expand_tabs($1); + } + $rawline =~ m@^\+([ \t]*)\*@; + my $newindent = $1; + $newindent = expand_tabs($newindent); + if (length($oldindent) ne length($newindent)) { + WARN("BLOCK_COMMENT_STYLE", + "Block comments should align the * on each line\n" . $hereprev); + } + } + +# check for missing blank lines after struct/union declarations +# with exceptions for various attributes and macros + if ($prevline =~ /^[\+ ]};?\s*$/ && + $line =~ /^\+/ && + !($line =~ /^\+\s*$/ || + $line =~ /^\+\s*(?:EXPORT_SYMBOL|early_param)/ || + $line =~ /^\+\s*MODULE_/i || + $line =~ /^\+\s*\#\s*(?:end|elif|else)/ || + $line =~ /^\+[a-z_]*init/ || + $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ || + $line =~ /^\+\s*DECLARE/ || + $line =~ /^\+\s*builtin_[\w_]*driver/ || + $line =~ /^\+\s*__setup/)) { + if (CHK("LINE_SPACING", + "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + +# check for multiple consecutive blank lines + if ($prevline =~ /^[\+ ]\s*$/ && + $line =~ /^\+\s*$/ && + $last_blank_line != ($linenr - 1)) { + if (CHK("LINE_SPACING", + "Please don't use multiple blank lines\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + + $last_blank_line = $linenr; + } + +# check for missing blank lines after declarations +# (declarations must have the same indentation and not be at the start of line) + if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) { + # use temporaries + my $sl = $sline; + my $pl = $prevline; + # remove $Attribute/$Sparse uses to simplify comparisons + $sl =~ s/\b(?:$Attribute|$Sparse)\b//g; + $pl =~ s/\b(?:$Attribute|$Sparse)\b//g; + if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $pl =~ /^\+\s+$declaration_macros/) && + # for "else if" which can look like "$Ident $Ident" + !($pl =~ /^\+\s+$c90_Keywords\b/ || + # other possible extensions of declaration lines + $pl =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + # not starting a section or a macro "\" extended line + $pl =~ /(?:\{\s*|\\)$/) && + # looks like a declaration + !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $sl =~ /^\+\s+$declaration_macros/ || + # start of struct or union or enum + $sl =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || + # start or end of block or continuation of declaration + $sl =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + # bitfield continuation + $sl =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + # other possible extensions of declaration lines + $sl =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/)) { + if (WARN("LINE_SPACING", + "Missing a blank line after declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + } # check for spaces at the beginning of a line. # Exceptions: # 1) within comments # 2) indented preprocessor commands # 3) hanging labels - if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { + if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("LEADING_SPACE", - "please, no spaces at the start of a line\n" . $herevet); + if (WARN("LEADING_SPACE", + "please, no spaces at the start of a line\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check we are in a valid C source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c)$/); + +# check for unusual line ending [ or ( + if ($line =~ /^\+.*([\[\(])\s*$/) { + CHK("OPEN_ENDED_LINE", + "Lines should not end with a '$1'\n" . $herecurr); + } + +# check if this appears to be the start function declaration, save the name + if ($sline =~ /^\+\{\s*$/ && + $prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) { + $context_function = $1; + } + +# check if this appears to be the end of function declaration + if ($sline =~ /^\+\}\s*$/) { + undef $context_function; + } + +# check indentation of any line with a bare else +# (but not if it is a multiple line "if (foo) return bar; else return baz;") +# if the previous line is a break or return and is indented 1 tab more... + if ($sline =~ /^\+([\t]+)(?:}[ \t]*)?else(?:[ \t]*{)?\s*$/) { + my $tabs = length($1) + 1; + if ($prevline =~ /^\+\t{$tabs,$tabs}break\b/ || + ($prevline =~ /^\+\t{$tabs,$tabs}return\b/ && + defined $lines[$linenr] && + $lines[$linenr] !~ /^[ \+]\t{$tabs,$tabs}return/)) { + WARN("UNNECESSARY_ELSE", + "else is not generally useful after a break or return\n" . $hereprev); + } + } + +# check indentation of a line with a break; +# if the previous line is a goto, return or break +# and is indented the same # of tabs + if ($sline =~ /^\+([\t]+)break\s*;\s*$/) { + my $tabs = $1; + if ($prevline =~ /^\+$tabs(goto|return|break)\b/) { + if (WARN("UNNECESSARY_BREAK", + "break is not useful after a $1\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + } } # check for RCS/CVS revision markers @@ -1753,27 +4187,33 @@ sub process { "CVS style keyword markers, these will _not_ be updated\n". $herecurr); } -# Blackfin: don't use __builtin_bfin_[cs]sync - if ($line =~ /__builtin_bfin_csync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("CSYNC", - "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); - } - if ($line =~ /__builtin_bfin_ssync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("SSYNC", - "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); +# check for old HOTPLUG __dev<foo> section markings + if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { + WARN("HOTPLUG_SECTION", + "Using $1 is unnecessary\n" . $herecurr); } # Check for potential 'bare' types my ($stat, $cond, $line_nr_next, $remain_next, $off_next, $realline_next); - if ($realcnt && $line =~ /.\s*\S/) { +#print "LINE<$line>\n"; + if ($linenr > $suppress_statement && + $realcnt && $sline =~ /.\s*\S/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0); $stat =~ s/\n./\n /g; $cond =~ s/\n./\n /g; +#print "linenr<$linenr> <$stat>\n"; + # If this statement has no statement boundaries within + # it there is no point in retrying a statement scan + # until we hit end of it. + my $frag = $stat; $frag =~ s/;+\s*$//; + if ($frag !~ /(?:{|;)/) { +#print "skip<$line_nr_next>\n"; + $suppress_statement = $line_nr_next; + } + # Find the real next line. $realline_next = $line_nr_next; if (defined $realline_next && @@ -1783,7 +4223,7 @@ sub process { } my $s = $stat; - $s =~ s/\{.*$//s; + $s =~ s/{.*$//s; # Ignore goto labels. if ($s =~ /$Ident:\*$/s) { @@ -1835,33 +4275,41 @@ sub process { # Check for switch () and associated case and default # statements should be at the same indent. -# if ($line=~/\bswitch\s*\(.*\)/) { -# my $err = ''; -# my $sep = ''; -# my @ctx = ctx_block_outer($linenr, $realcnt); -# shift(@ctx); -# for my $ctx (@ctx) { -# my ($clen, $cindent) = line_stats($ctx); -# if ($ctx =~ /^\+\s*(case\s+|default:)/ && -# $indent != $cindent) { -# $err .= "$sep$ctx\n"; -# $sep = ''; -# } else { -# $sep = "[...]\n"; -# } -# } -# if ($err ne '') { -# ERROR("SWITCH_CASE_INDENT_LEVEL", -# "switch and case should be at the same indent\n$hereline$err"); -# } -# } + if ($line=~/\bswitch\s*\(.*\)/) { + my $err = ''; + my $sep = ''; + my @ctx = ctx_block_outer($linenr, $realcnt); + shift(@ctx); + for my $ctx (@ctx) { + my ($clen, $cindent) = line_stats($ctx); + if ($ctx =~ /^\+\s*(case\s+|default:)/ && + $indent != $cindent) { + $err .= "$sep$ctx\n"; + $sep = ''; + } else { + $sep = "[...]\n"; + } + } + if ($err ne '') { + ERROR("SWITCH_CASE_INDENT_LEVEL", + "switch and case should be at the same indent\n$hereline$err"); + } + } # if/while/etc brace do not go on next line, unless defining a do while loop, # or if that brace on the next line is for something else - if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { my $pre_ctx = "$1$2"; my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + + # OpenOCD specific: Begin: replace s/6/10/ + if ($line =~ /^\+\t{10,}/) { + # OpenOCD specific: End + WARN("DEEP_INDENTATION", + "Too many leading tabs - consider code refactoring\n" . $herecurr); + } + my $ctx_cnt = $realcnt - $#ctx - 1; my $ctx = join("\n", @ctx); @@ -1879,7 +4327,7 @@ sub process { #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; - if ($ctx !~ /\{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*\{/) { + if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { ERROR("OPEN_BRACE", "that open brace { should be on the previous line\n" . "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); @@ -1898,20 +4346,30 @@ sub process { } # Check relative indent for conditionals and blocks. - if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + if ($line =~ /\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|(?:do|else)\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); my ($s, $c) = ($stat, $cond); substr($s, 0, length($c), ''); - # Make sure we remove the line prefixes as we have - # none on the first line, and are going to readd them - # where necessary. - $s =~ s/\n./\n/gs; + # remove inline comments + $s =~ s/$;/ /g; + $c =~ s/$;/ /g; # Find out how long the conditional actually is. my @newlines = ($c =~ /\n/gs); my $cond_lines = 1 + $#newlines; + # Make sure we remove the line prefixes as we have + # none on the first line, and are going to readd them + # where necessary. + $s =~ s/\n./\n/gs; + while ($s =~ /\n\s+\\\n/) { + $cond_lines += $s =~ s/\n\s+\\\n/\n/g; + } + # We want to check the first line inside the block # starting at the end of the conditional, so remove: # 1) any blank line termination @@ -1920,7 +4378,7 @@ sub process { my $continuation = 0; my $check = 0; $s =~ s/^.*\bdo\b//; - $s =~ s/^\s*\{//; + $s =~ s/^\s*{//; if ($s =~ s/^\s*\\//) { $continuation = 1; } @@ -1977,8 +4435,12 @@ sub process { #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; - if ($check && (($sindent % 4) != 0 || - ($sindent <= $indent && $s ne ''))) { + if ($check && $s ne '' && + (($sindent % $tabsize) != 0 || + ($sindent < $indent) || + ($sindent == $indent && + ($s !~ /^\s*(?:\}|\{|else\b)/)) || + ($sindent > $indent + $tabsize))) { WARN("SUSPECT_CODE_INDENT", "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); } @@ -1998,7 +4460,54 @@ sub process { $prev_values = substr($curr_values, -1); #ignore lines not being added - if ($line=~/^[^\+]/) {next;} + next if ($line =~ /^[^\+]/); + +# check for self assignments used to avoid compiler warnings +# e.g.: int foo = foo, *bar = NULL; +# struct foo bar = *(&(bar)); + if ($line =~ /^\+\s*(?:$Declare)?([A-Za-z_][A-Za-z\d_]*)\s*=/) { + my $var = $1; + if ($line =~ /^\+\s*(?:$Declare)?$var\s*=\s*(?:$var|\*\s*\(?\s*&\s*\(?\s*$var\s*\)?\s*\)?)\s*[;,]/) { + WARN("SELF_ASSIGNMENT", + "Do not use self-assignments to avoid compiler warnings\n" . $herecurr); + } + } + +# check for dereferences that span multiple lines + if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ && + $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) { + $prevline =~ /($Lval\s*(?:\.|->))\s*$/; + my $ref = $1; + $line =~ /^.\s*($Lval)/; + $ref .= $1; + $ref =~ s/\s//g; + WARN("MULTILINE_DEREFERENCE", + "Avoid multiple line dereference - prefer '$ref'\n" . $hereprev); + } + +# check for declarations of signed or unsigned without int + while ($line =~ m{\b($Declare)\s*(?!char\b|short\b|int\b|long\b)\s*($Ident)?\s*[=,;\[\)\(]}g) { + my $type = $1; + my $var = $2; + $var = "" if (!defined $var); + if ($type =~ /^(?:(?:$Storage|$Inline|$Attribute)\s+)*((?:un)?signed)((?:\s*\*)*)\s*$/) { + my $sign = $1; + my $pointer = $2; + + $pointer = "" if (!defined $pointer); + + if (WARN("UNSPECIFIED_INT", + "Prefer '" . trim($sign) . " int" . rtrim($pointer) . "' to bare use of '$sign" . rtrim($pointer) . "'\n" . $herecurr) && + $fix) { + my $decl = trim($sign) . " int "; + my $comp_pointer = $pointer; + $comp_pointer =~ s/\s//g; + $decl .= $comp_pointer; + $decl = rtrim($decl) if ($var eq ""); + $fixed[$fixlinenr] =~ s@\b$sign\s*\Q$pointer\E\s*$var\b@$decl$var@; + } + } + } # TEST: allow direct testing of the type matcher. if ($dbg_type) { @@ -2024,10 +4533,20 @@ sub process { } # check for initialisation to aggregates open brace on the next line - if ($line =~ /^.\s*\{/ && + if ($line =~ /^.\s*{/ && $prevline =~ /(?:^|[^=])=\s*$/) { - ERROR("OPEN_BRACE", - "that open brace { should be on the previous line\n" . $hereprev); + if (ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/\s*=\s*$/ = {/; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $line; + $fixedline =~ s/^(.\s*)\{\s*/$1/; + fix_insert_line($fixlinenr, $fixedline); + } } # @@ -2039,15 +4558,25 @@ sub process { my $path = $1; if ($path =~ m{//}) { ERROR("MALFORMED_INCLUDE", - "malformed #include filename\n" . - $herecurr); + "malformed #include filename\n" . $herecurr); + } + if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { + ERROR("UAPI_INCLUDE", + "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); } } # no C99 // comments if ($line =~ m{//}) { - ERROR("C99_COMMENTS", - "do not use C99 // comments\n" . $herecurr); + if (ERROR("C99_COMMENTS", + "do not use C99 // comments\n" . $herecurr) && + $fix) { + my $line = $fixed[$fixlinenr]; + if ($line =~ /\/\/(.*)$/) { + my $comment = trim($1); + $fixed[$fixlinenr] =~ s@\/\/(.*)$@/\* $comment \*/@; + } + } } # Remove C99 comments. $line =~ s@//.*@@; @@ -2059,14 +4588,14 @@ sub process { if (defined $realline_next && exists $lines[$realline_next - 1] && !defined $suppress_export{$realline_next} && - ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/)) { # Handle definitions which produce identifiers with # a prefix: # XXX(foo); # EXPORT_SYMBOL(something_foo); my $name = $1; - if ($stat =~ /^.([A-Z_]+)\s*\(\s*($Ident)/ && + $name =~ s/^\s*($Ident).*/$1/; + if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && $name =~ /^${Ident}_$2/) { #print "FOO C name<$name>\n"; $suppress_export{$realline_next} = 1; @@ -2087,8 +4616,7 @@ sub process { } if (!defined $suppress_export{$linenr} && $prevline =~ /^.\s*$/ && - ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/)) { #print "FOO B <$lines[$linenr - 1]>\n"; $suppress_export{$linenr} = 2; } @@ -2099,16 +4627,49 @@ sub process { } # check for global initialisers. - if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { - ERROR("GLOBAL_INITIALISERS", - "do not initialise globals to 0 or NULL\n" . - $herecurr); + if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/ && + !exclude_global_initialisers($realfile)) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to $1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^.$Type\s*$Ident(?:\s+$Modifier)*)\s*=\s*$zero_initializer\s*;/$1;/; + } } # check for static initialisers. - if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { - ERROR("INITIALISED_STATIC", - "do not initialise statics to 0 or NULL\n" . - $herecurr); + if ($line =~ /^\+.*\bstatic\s.*=\s*($zero_initializer)\s*;/) { + if (ERROR("INITIALISED_STATIC", + "do not initialise statics to $1\n" . + $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s.*?)\s*=\s*$zero_initializer\s*;/$1;/; + } + } + +# check for misordered declarations of char/short/int/long with signed/unsigned + while ($sline =~ m{(\b$TypeMisordered\b)}g) { + my $tmp = trim($1); + WARN("MISORDERED_TYPE", + "type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\n" . $herecurr); + } + +# check for unnecessary <signed> int declarations of short/long/long long + while ($sline =~ m{\b($TypeMisordered(\s*\*)*|$C90_int_types)\b}g) { + my $type = trim($1); + next if ($type !~ /\bint\b/); + next if ($type !~ /\b(?:short|long\s+long|long)\b/); + my $new_type = $type; + $new_type =~ s/\b\s*int\s*\b/ /; + $new_type =~ s/\b\s*(?:un)?signed\b\s*/ /; + $new_type =~ s/^const\s+//; + $new_type = "unsigned $new_type" if ($type =~ /\bunsigned\b/); + $new_type = "const $new_type" if ($type =~ /^const\b/); + $new_type =~ s/\s+/ /g; + $new_type = trim($new_type); + if (WARN("UNNECESSARY_INT", + "Prefer '$new_type' over '$type' as the int is unnecessary\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b\Q$type\E\b/$new_type/; + } } # check for static const char * arrays. @@ -2116,36 +4677,93 @@ sub process { WARN("STATIC_CONST_CHAR_ARRAY", "static const char * array should probably be static const char * const\n" . $herecurr); - } + } + +# check for initialized const char arrays that should be static const + if ($line =~ /^\+\s*const\s+(char|unsigned\s+char|_*u8|(?:[us]_)?int8_t)\s+\w+\s*\[\s*(?:\w+\s*)?\]\s*=\s*"/) { + if (WARN("STATIC_CONST_CHAR_ARRAY", + "const array should probably be static const\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^.\s*)const\b/${1}static const/; + } + } # check for static char foo[] = "bar" declarations. if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { WARN("STATIC_CONST_CHAR_ARRAY", "static char array declaration should probably be static const char\n" . $herecurr); - } + } + +# check for const <foo> const where <foo> is not a pointer or array type + if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) { + my $found = $1; + if ($sline =~ /\bconst\s+\Q$found\E\s+const\b\s*\*/) { + WARN("CONST_CONST", + "'const $found const *' should probably be 'const $found * const'\n" . $herecurr); + } elsif ($sline !~ /\bconst\s+\Q$found\E\s+const\s+\w+\s*\[/) { + WARN("CONST_CONST", + "'const $found const' should probably be 'const $found'\n" . $herecurr); + } + } + +# check for const static or static <non ptr type> const declarations +# prefer 'static const <foo>' over 'const static <foo>' and 'static <foo> const' + if ($sline =~ /^\+\s*const\s+static\s+($Type)\b/ || + $sline =~ /^\+\s*static\s+($BasicType)\s+const\b/) { + if (WARN("STATIC_CONST", + "Move const after static - use 'static const $1'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bconst\s+static\b/static const/; + $fixed[$fixlinenr] =~ s/\bstatic\s+($BasicType)\s+const\b/static const $1/; + } + } + +# check for non-global char *foo[] = {"bar", ...} declarations. + if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "char * array declaration might be better as static const\n" . + $herecurr); + } + +# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo) + if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) { + my $array = $1; + if ($line =~ m@\b(sizeof\s*\(\s*\Q$array\E\s*\)\s*/\s*sizeof\s*\(\s*\Q$array\E\s*\[\s*0\s*\]\s*\))@) { + my $array_div = $1; + if (WARN("ARRAY_SIZE", + "Prefer ARRAY_SIZE($array)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$array_div\E/ARRAY_SIZE($array)/; + } + } + } -# check for declarations of struct pci_device_id - if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { - WARN("DEFINE_PCI_DEVICE_TABLE", - "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); +# check for function declarations without arguments like "int foo()" + if ($line =~ /(\b$Type\s*$Ident)\s*\(\s*\)/) { + if (ERROR("FUNCTION_WITHOUT_ARGS", + "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/; + } } # check for new typedefs, only function parameters and sparse annotations # make sense. -# if ($line =~ /\btypedef\s/ && -# $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && -# $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && -# $line !~ /\b$typeTypedefs\b/ && -# $line !~ /\b__bitwise(?:__|)\b/) { -# WARN("NEW_TYPEDEFS", -# "do not add new typedefs\n" . $herecurr); -# } + if ($line =~ /\btypedef\s/ && + $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && + $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && + $line !~ /\b$typeTypedefs\b/ && + $line !~ /\b__bitwise\b/) { + WARN("NEW_TYPEDEFS", + "do not add new typedefs\n" . $herecurr); + } # * goes on variable not on type # (char*[ const]) - if ($line =~ m{\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\)}) { - my ($from, $to) = ($1, $1); + while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { + #print "AA<$1>\n"; + my ($ident, $from, $to) = ($1, $2, $2); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2155,13 +4773,22 @@ sub process { while ($to =~ s/\*\s+\*/\*\*/) { } - #print "from<$from> to<$to>\n"; +## print "1: from<$from> to<$to> ident<$ident>\n"; if ($from ne $to) { - ERROR("POINTER_LOCATION", - "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); + if (ERROR("POINTER_LOCATION", + "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) && + $fix) { + my $sub_from = $ident; + my $sub_to = $ident; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } } - } elsif ($line =~ m{\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident)}) { - my ($from, $to, $ident) = ($1, $1, $2); + } + while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { + #print "BB<$1>\n"; + my ($match, $from, $to, $ident) = ($1, $2, $2, $3); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2173,20 +4800,30 @@ sub process { # Modifiers should have spaces. $to =~ s/(\b$Modifier$)/$1 /; - #print "from<$from> to<$to> ident<$ident>\n"; +## print "2: from<$from> to<$to> ident<$ident>\n"; if ($from ne $to && $ident !~ /^$Modifier$/) { - ERROR("POINTER_LOCATION", - "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); + if (ERROR("POINTER_LOCATION", + "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) && + $fix) { + + my $sub_from = $match; + my $sub_to = $match; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } } } -# # no BUG() or BUG_ON() -# if ($line =~ /\b(BUG|BUG_ON)\b/) { -# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; -# print "$herecurr"; -# $clean = 0; -# } +# avoid BUG() or BUG_ON() + if ($line =~ /\b(?:BUG|BUG_ON)\b/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}("AVOID_BUG", + "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr); + } +# avoid LINUX_VERSION_CODE if ($line =~ /\bLINUX_VERSION_CODE\b/) { WARN("LINUX_VERSION_CODE", "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); @@ -2195,52 +4832,184 @@ sub process { # check for uses of printk_ratelimit if ($line =~ /\bprintk_ratelimit\s*\(/) { WARN("PRINTK_RATELIMITED", -"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr); - } - -# printk should use KERN_* levels. Note that follow on printk's on the -# same line do not need a level, so we use the current block context -# to try and find and validate the current printk. In summary the current -# printk includes all preceding printk's which have no newline on the end. -# we assume the first bad printk is the one to report. - if ($line =~ /\bprintk\((?!KERN_)\s*"/) { - my $ok = 0; - for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { - #print "CHECK<$lines[$ln - 1]\n"; - # we have a preceding printk if it ends - # with "\n" ignore it, else it is to blame - if ($lines[$ln - 1] =~ m{\bprintk\(}) { - if ($rawlines[$ln - 1] !~ m{\\n"}) { - $ok = 1; - } - last; - } - } - if ($ok == 0) { - WARN("PRINTK_WITHOUT_KERN_LEVEL", - "printk() should include KERN_ facility level\n" . $herecurr); + "Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr); + } + +# printk should use KERN_* levels + if ($line =~ /\bprintk\s*\(\s*(?!KERN_[A-Z]+\b)/) { + WARN("PRINTK_WITHOUT_KERN_LEVEL", + "printk() should include KERN_<LEVEL> facility level\n" . $herecurr); + } + +# prefer variants of (subsystem|netdev|dev|pr)_<level> to printk(KERN_<LEVEL> + if ($line =~ /\b(printk(_once|_ratelimited)?)\s*\(\s*KERN_([A-Z]+)/) { + my $printk = $1; + my $modifier = $2; + my $orig = $3; + $modifier = "" if (!defined($modifier)); + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); + $level .= $modifier; + $level2 .= $modifier; + WARN("PREFER_PR_LEVEL", + "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to $printk(KERN_$orig ...\n" . $herecurr); + } + +# prefer dev_<level> to dev_printk(KERN_<LEVEL> + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + $level = "dbg" if ($level eq "debug"); + WARN("PREFER_DEV_LEVEL", + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + +# trace_printk should not be used in production code. + if ($line =~ /\b(trace_printk|trace_puts|ftrace_vprintk)\s*\(/) { + WARN("TRACE_PRINTK", + "Do not use $1() in production code (this can be ignored if built only with a debug config option)\n" . $herecurr); + } + +# ENOSYS means "bad syscall nr" and nothing else. This will have a small +# number of false positives, but assembly files are not checked, so at +# least the arch entry code will not trigger this warning. + if ($line =~ /\bENOSYS\b/) { + WARN("ENOSYS", + "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr); + } + +# ENOTSUPP is not a standard error code and should be avoided in new patches. +# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP. +# Similarly to ENOSYS warning a small number of false positives is expected. + if (!$file && $line =~ /\bENOTSUPP\b/) { + if (WARN("ENOTSUPP", + "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bENOTSUPP\b/EOPNOTSUPP/; } } # function brace can't be on same line, except for #defines of do while, # or if closed on same line - if (($line=~/$Type\s*$Ident\(.*\).*\s\{/) and - !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) { - ERROR("OPEN_BRACE", - "open brace '{' following function declarations go on the next line\n" . $herecurr); + if ($perl_version_ok && + $sline =~ /$Type\s*$Ident\s*$balanced_parens\s*\{/ && + $sline !~ /\#\s*define\b.*do\s*\{/ && + $sline !~ /}/) { + if (ERROR("OPEN_BRACE", + "open brace '{' following function definitions go on the next line\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + my $fixed_line = $rawline; + $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*)\{(.*)$/; + my $line1 = $1; + my $line2 = $2; + fix_insert_line($fixlinenr, ltrim($line1)); + fix_insert_line($fixlinenr, "\+{"); + if ($line2 !~ /^\s*$/) { + fix_insert_line($fixlinenr, "\+\t" . trim($line2)); + } + } } # open braces for enum, union and struct go on the same line. - if ($line =~ /^.\s*\{/ && + if ($line =~ /^.\s*{/ && $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { - ERROR("OPEN_BRACE", - "open brace '{' following $1 go on the same line\n" . $hereprev); + if (ERROR("OPEN_BRACE", + "open brace '{' following $1 go on the same line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = rtrim($prevrawline) . " {"; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $rawline; + $fixedline =~ s/^(.\s*)\{\s*/$1\t/; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + } } # missing space after union, struct or enum definition - if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { - WARN("SPACING", - "missing space after $1 definition\n" . $herecurr); + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) { + if (WARN("SPACING", + "missing space after $1 definition\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/; + } + } + +# Function pointer declarations +# check spacing between type, funcptr, and args +# canonical declaration is "type (*funcptr)(args...)" + if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)($Ident)(\s*)\)(\s*)\(/) { + my $declare = $1; + my $pre_pointer_space = $2; + my $post_pointer_space = $3; + my $funcname = $4; + my $post_funcname_space = $5; + my $pre_args_space = $6; + +# the $Declare variable will capture all spaces after the type +# so check it for a missing trailing missing space but pointer return types +# don't need a space so don't warn for those. + my $post_declare_space = ""; + if ($declare =~ /(\s+)$/) { + $post_declare_space = $1; + $declare = rtrim($declare); + } + if ($declare !~ /\*$/ && $post_declare_space =~ /^$/) { + WARN("SPACING", + "missing space after return type\n" . $herecurr); + $post_declare_space = " "; + } + +# unnecessary space "type (*funcptr)(args...)" +# This test is not currently implemented because these declarations are +# equivalent to +# int foo(int bar, ...) +# and this is form shouldn't/doesn't generate a checkpatch warning. +# +# elsif ($declare =~ /\s{2,}$/) { +# WARN("SPACING", +# "Multiple spaces after return type\n" . $herecurr); +# } + +# unnecessary space "type ( *funcptr)(args...)" + if (defined $pre_pointer_space && + $pre_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer open parenthesis\n" . $herecurr); + } + +# unnecessary space "type (* funcptr)(args...)" + if (defined $post_pointer_space && + $post_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr )(args...)" + if (defined $post_funcname_space && + $post_funcname_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr) (args...)" + if (defined $pre_args_space && + $pre_args_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer arguments\n" . $herecurr); + } + + if (show_type("SPACING") && $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*)$Declare\s*\(\s*\*\s*$Ident\s*\)\s*\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex; + } } # check for spacing round square brackets; allowed: @@ -2251,9 +5020,13 @@ sub process { my ($where, $prefix) = ($-[1], $1); if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && - $prefix !~ /\{\s+$/) { - ERROR("BRACKET_SPACE", - "space prohibited before open square bracket '['\n" . $herecurr); + $prefix !~ /[{,:]\s+$/) { + if (ERROR("BRACKET_SPACE", + "space prohibited before open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(\+.*?)\s+\[/$1\[/; + } } } @@ -2270,7 +5043,6 @@ sub process { __attribute__|format|__extension__| asm|__asm__)$/x) { - # cpp #define statements have non-optional spaces, ie # if there is a space between the name and the open # parenthesis it is simply not a parameter group. @@ -2284,25 +5056,53 @@ sub process { } elsif ($ctx =~ /$Type$/) { } else { - WARN("SPACING", - "space prohibited between function name and open parenthesis '('\n" . $herecurr); + if (WARN("SPACING", + "space prohibited between function name and open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b$name\s+\(/$name\(/; + } } } + # Check operator spacing. if (!($line=~/\#\s*include/)) { + my $fixed_line = ""; + my $line_fixed = 0; + my $ops = qr{ <<=|>>=|<=|>=|==|!=| \+=|-=|\*=|\/=|%=|\^=|\|=|&=| =>|->|<<|>>|<|>|=|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| - \?|: + \?:|\?|: }x; my @elements = split(/($ops|;)/, $opline); + +## print("element count: <" . $#elements . ">\n"); +## foreach my $el (@elements) { +## print("el: <$el>\n"); +## } + + my @fix_elements = (); my $off = 0; + foreach my $el (@elements) { + push(@fix_elements, substr($rawline, $off, length($el))); + $off += length($el); + } + + $off = 0; + my $blank = copy_spacing($opline); + my $last_after = -1; for (my $n = 0; $n < $#elements; $n += 2) { + + my $good = $fix_elements[$n] . $fix_elements[$n + 1]; + +## print("n: <$n> good: <$good>\n"); + $off += length($elements[$n]); # Pick up the preceding and succeeding characters. @@ -2350,7 +5150,7 @@ sub process { # Ignore operators passed as parameters. if ($op_type ne 'V' && - $ca =~ /\s$/ && $cc =~ /^\s*,/) { + $ca =~ /\s$/ && $cc =~ /^\s*[,\)]/) { # # Ignore comments # } elsif ($op =~ /^$;+$/) { @@ -2359,27 +5159,62 @@ sub process { } elsif ($op eq ';') { if ($ctx !~ /.x[WEBC]/ && $cc !~ /^\\/ && $cc !~ /^;/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } } # // is a comment } elsif ($op eq '//') { + # : when part of a bitfield + } elsif ($opv eq ':B') { + # skip the bitfield test for now + # No spaces for: # -> - # : when part of a bitfield - } elsif ($op eq '->' || $opv eq ':B') { + } elsif ($op eq '->') { if ($ctx =~ /Wx.|.xW/) { - ERROR("SPACING", - "spaces prohibited around that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "spaces prohibited around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } - # , must have a space on the right. + # , must not have a space before and must have a space on the right. } elsif ($op eq ',') { + my $rtrim_before = 0; + my $space_after = 0; + if ($ctx =~ /Wx./) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $line_fixed = 1; + $rtrim_before = 1; + } + } if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $line_fixed = 1; + $last_after = $n; + $space_after = 1; + } + } + if ($rtrim_before || $space_after) { + if ($rtrim_before) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + } else { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + } + if ($space_after) { + $good .= " "; + } } # '*' as part of a type definition -- reported already. @@ -2393,34 +5228,56 @@ sub process { $opv eq '*U' || $opv eq '-U' || $opv eq '&U' || $opv eq '&&U') { if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { - ERROR("SPACING", - "space required before that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required before that '$op' $at\n" . $hereptr)) { + if ($n != $last_after + 2) { + $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } } if ($op eq '*' && $cc =~/\s*$Modifier\b/) { # A unary '*' may be const } elsif ($ctx =~ /.xW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } # unary ++ and unary -- are allowed no space on one side. } elsif ($op eq '++' or $op eq '--') { if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { - ERROR("SPACING", - "space required one side of that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required one side of that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } } if ($ctx =~ /Wx[BE]/ || ($ctx =~ /Wx./ && $cc =~ /^;/)) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } } if ($ctx =~ /ExW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } - # << and >> may either have or not have spaces both sides } elsif ($op eq '<<' or $op eq '>>' or $op eq '&' or $op eq '^' or $op eq '|' or @@ -2428,18 +5285,41 @@ sub process { $op eq '*' or $op eq '/' or $op eq '%') { - if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { - ERROR("SPACING", - "need consistent spacing around '$op' $at\n" . - $hereptr); + if ($check) { + if (defined $fix_elements[$n + 2] && $ctx !~ /[EW]x[EW]/) { + if (CHK("SPACING", + "spaces preferred around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + $fix_elements[$n + 2] =~ s/^\s+//; + $line_fixed = 1; + } + } elsif (!defined $fix_elements[$n + 2] && $ctx !~ /Wx[OE]/) { + if (CHK("SPACING", + "space preferred before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + } elsif ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { + if (ERROR("SPACING", + "need consistent spacing around '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } # A colon needs no spaces before when it is # terminating a case value or a label. } elsif ($opv eq ':C' || $opv eq ':L') { - if ($ctx =~ /Wx./) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); + if ($ctx =~ /Wx./ and $realfile !~ m@.*\.lds\.h$@) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } } # All the others need spaces both sides. @@ -2452,21 +5332,57 @@ sub process { ($op eq '>' && $ca =~ /<\S+\@\S+$/)) { - $ok = 1; + $ok = 1; } - # Ignore ?: - if (($opv eq ':O' && $ca =~ /\?$/) || - ($op eq '?' && $cc =~ /^:/)) { - $ok = 1; + # for asm volatile statements + # ignore a colon with another + # colon immediately before or after + if (($op eq ':') && + ($ca =~ /:$/ || $cc =~ /^:/)) { + $ok = 1; } + # messages are ERROR, but ?: are CHK if ($ok == 0) { - ERROR("SPACING", - "spaces required around that '$op' $at\n" . $hereptr); + my $msg_level = \&ERROR; + $msg_level = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + + if (&{$msg_level}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } } $off += length($elements[$n + 1]); + +## print("n: <$n> GOOD: <$good>\n"); + + $fixed_line = $fixed_line . $good; + } + + if (($#elements % 2) == 0) { + $fixed_line = $fixed_line . $fix_elements[$#elements]; + } + + if ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) { + $fixed[$fixlinenr] = $fixed_line; + } + + + } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;\s*$/) { + if (WARN("SPACING", + "space prohibited before semicolon\n" . $herecurr) && + $fix) { + 1 while $fixed[$fixlinenr] =~ + s/^(\+.*\S)\s+;/$1;/; } } @@ -2482,7 +5398,7 @@ sub process { ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { ## ## # Remove any bracketed sections to ensure we do not -## # falsly report the parameters of functions. +## # falsely report the parameters of functions. ## my $ln = $line; ## while ($ln =~ s/\([^\(\)]*\)//g) { ## } @@ -2494,111 +5410,247 @@ sub process { #need space before brace following if, while, etc if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\)\{/) || - $line =~ /do\{/) { - ERROR("SPACING", - "space required before the open brace '{'\n" . $herecurr); + $line =~ /\b(?:else|do)\{/) { + if (ERROR("SPACING", + "space required before the open brace '{'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*(?:do|else|\)))\{/$1 {/; + } } +## # check for blank lines before declarations +## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ && +## $prevrawline =~ /^.\s*$/) { +## WARN("SPACING", +## "No blank lines before declarations\n" . $hereprev); +## } +## + # closing brace should have a space following it when it has anything # on the line - if ($line =~ /}(?!(?:,|;|\)))\S/) { - ERROR("SPACING", - "space required after that close brace '}'\n" . $herecurr); + if ($line =~ /}(?!(?:,|;|\)|\}))\S/) { + if (ERROR("SPACING", + "space required after that close brace '}'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/}((?!(?:,|;|\)))\S)/} $1/; + } } # check spacing on square brackets if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { - ERROR("SPACING", - "space prohibited after that open square bracket '['\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited after that open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\[\s+/\[/; + } } if ($line =~ /\s\]/) { - ERROR("SPACING", - "space prohibited before that close square bracket ']'\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited before that close square bracket ']'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\]/\]/; + } } # check spacing on parentheses if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && $line !~ /for\s*\(\s+;/) { - ERROR("SPACING", - "space prohibited after that open parenthesis '('\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited after that open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\(\s+/\(/; + } } if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && $line !~ /for\s*\(.*;\s+\)/ && $line !~ /:\s+\)/) { - ERROR("SPACING", - "space prohibited before that close parenthesis ')'\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited before that close parenthesis ')'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\)/\)/; + } } -#goto labels aren't indented, allow a single space however - if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and - !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { - WARN("INDENTED_LABEL", - "labels should not be indented\n" . $herecurr); +# check unnecessary parentheses around addressof/dereference single $Lvals +# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar + + while ($line =~ /(?:[^&]&\s*|\*)\(\s*($Ident\s*(?:$Member\s*)+)\s*\)/g) { + my $var = $1; + if (CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around $var\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\(\s*\Q$var\E\s*\)/$var/; + } } -# Return is not a function. - if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { - my $spacing = $1; - my $value = $2; - - # Flatten any parentheses - $value =~ s/\(/ \(/g; - $value =~ s/\)/\) /g; - while ($value =~ s/\[[^\{\}]*\]/1/ || - $value !~ /(?:$Ident|-?$Constant)\s* - $Compare\s* - (?:$Ident|-?$Constant)/x && - $value =~ s/\([^\(\)]*\)/1/) { - } -#print "value<$value>\n"; - if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { - ERROR("RETURN_PARENTHESES", - "return is not a function, parentheses are not required\n" . $herecurr); +# check for unnecessary parentheses around function pointer uses +# ie: (foo->bar)(); should be foo->bar(); +# but not "if (foo->bar) (" to avoid some false positives + if ($line =~ /(\bif\s*|)(\(\s*$Ident\s*(?:$Member\s*)+\))[ \t]*\(/ && $1 !~ /^if/) { + my $var = $2; + if (CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around function pointer $var\n" . $herecurr) && + $fix) { + my $var2 = deparenthesize($var); + $var2 =~ s/\s//g; + $fixed[$fixlinenr] =~ s/\Q$var\E/$var2/; + } + } + +# check for unnecessary parentheses around comparisons in if uses +# when !drivers/staging or command-line uses --strict + if (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) && + $perl_version_ok && defined($stat) && + $stat =~ /(^.\s*if\s*($balanced_parens))/) { + my $if_stat = $1; + my $test = substr($2, 1, -1); + my $herectx; + while ($test =~ /(?:^|[^\w\&\!\~])+\s*\(\s*([\&\!\~]?\s*$Lval\s*(?:$Compare\s*$FuncArg)?)\s*\)/g) { + my $match = $1; + # avoid parentheses around potential macro args + next if ($match =~ /^\s*\w+\s*$/); + if (!defined($herectx)) { + $herectx = $here . "\n"; + my $cnt = statement_rawlines($if_stat); + for (my $n = 0; $n < $cnt; $n++) { + my $rl = raw_line($linenr, $n); + $herectx .= $rl . "\n"; + last if $rl =~ /^[ \+].*\{/; + } + } + CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around '$match'\n" . $herectx); + } + } + +# check that goto labels aren't indented (allow a single space indentation) +# and ignore bitfield definitions like foo:1 +# Strictly, labels can have whitespace after the identifier and before the : +# but this is not allowed here as many ?: uses would appear to be labels + if ($sline =~ /^.\s+[A-Za-z_][A-Za-z\d_]*:(?!\s*\d+)/ && + $sline !~ /^. [A-Za-z\d_][A-Za-z\d_]*:/ && + $sline !~ /^.\s+default:/) { + if (WARN("INDENTED_LABEL", + "labels should not be indented\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.)\s+/$1/; + } + } + +# check if a statement with a comma should be two statements like: +# foo = bar(), /* comma should be semicolon */ +# bar = baz(); + if (defined($stat) && + $stat =~ /^\+\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*,\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*;\s*$/) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + WARN("SUSPECT_COMMA_SEMICOLON", + "Possible comma where semicolon could be used\n" . $herectx); + } +# return is not a function + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { + my $spacing = $1; + if ($perl_version_ok && + $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) { + my $value = $1; + $value = deparenthesize($value); + if ($value =~ m/^\s*$FuncArg\s*(?:\?|$)/) { + ERROR("RETURN_PARENTHESES", + "return is not a function, parentheses are not required\n" . $herecurr); + } } elsif ($spacing !~ /\s+/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); } } -# Return of what appears to be an errno should normally be -'ve - if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { - my $name = $1; - if ($name ne 'EOF' && $name ne 'ERROR') { - WARN("USE_NEGATIVE_ERRNO", - "return of an errno should typically be -ve (return -$1)\n" . $herecurr); + +# unnecessary return in a void function +# at end-of-function, with the previous line a single leading tab, then return; +# and the line before that not a goto label target like "out:" + if ($sline =~ /^[ \+]}\s*$/ && + $prevline =~ /^\+\treturn\s*;\s*$/ && + $linenr >= 3 && + $lines[$linenr - 3] =~ /^[ +]/ && + $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { + WARN("RETURN_VOID", + "void function return statements are not generally useful\n" . $hereprev); + } + +# if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($perl_version_ok && + $line =~ /\bif\s*((?:\(\s*){2,})/) { + my $openparens = $1; + my $count = $openparens =~ tr@\(@\(@; + my $msg = ""; + if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) { + my $comp = $4; #Not $1 because of $LvalOrFunc + $msg = " - maybe == should be = ?" if ($comp eq "=="); + WARN("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses$msg\n" . $herecurr); } } -# typecasts on min/max could be min_t/max_t - if ($line =~ /^\+(?:.*?)\b(min|max)\s*\($Typecast{0,1}($LvalOrFunc)\s*,\s*$Typecast{0,1}($LvalOrFunc)\s*\)/) { - if (defined $2 || defined $8) { - my $call = $1; - my $cast1 = deparenthesize($2); - my $arg1 = $3; - my $cast2 = deparenthesize($8); - my $arg2 = $9; - my $cast; - - if ($cast1 ne "" && $cast2 ne "") { - $cast = "$cast1 or $cast2"; - } elsif ($cast1 ne "") { - $cast = $cast1; - } else { - $cast = $cast2; +# comparisons with a constant or upper case identifier on the left +# avoid cases like "foo + BAR < baz" +# only fix matches surrounded by parentheses to avoid incorrect +# conversions like "FOO < baz() + 5" being "misfixed" to "baz() > FOO + 5" + if ($perl_version_ok && + $line =~ /^\+(.*)\b($Constant|[A-Z_][A-Z0-9_]*)\s*($Compare)\s*($LvalOrFunc)/) { + my $lead = $1; + my $const = $2; + my $comp = $3; + my $to = $4; + my $newcomp = $comp; + if ($lead !~ /(?:$Operators|\.)\s*$/ && + $to !~ /^(?:Constant|[A-Z_][A-Z0-9_]*)$/ && + WARN("CONSTANT_COMPARISON", + "Comparisons should place the constant on the right side of the test\n" . $herecurr) && + $fix) { + if ($comp eq "<") { + $newcomp = ">"; + } elsif ($comp eq "<=") { + $newcomp = ">="; + } elsif ($comp eq ">") { + $newcomp = "<"; + } elsif ($comp eq ">=") { + $newcomp = "<="; } - WARN("MINMAX", - "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . $herecurr); + $fixed[$fixlinenr] =~ s/\(\s*\Q$const\E\s*$Compare\s*\Q$to\E\s*\)/($to $newcomp $const)/; + } + } + +# Return of what appears to be an errno should normally be negative + if ($sline =~ /\breturn(?:\s*\(+\s*|\s+)(E[A-Z]+)(?:\s*\)+\s*|\s*)[;:,]/) { + my $name = $1; + if ($name ne 'EOF' && $name ne 'ERROR' && $name !~ /^EPOLL/) { + WARN("USE_NEGATIVE_ERRNO", + "return of an errno should typically be negative (ie: return -$1)\n" . $herecurr); } } # Need a space before open parenthesis after if, while etc - if ($line=~/\b(if|while|for|switch)\(/) { - ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); + if ($line =~ /\b(if|while|for|switch)\(/) { + if (ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b(if|while|for|switch)\(/$1 \(/; + } } # Check for illegal assignment in if conditional -- and check for trailing # statements after the conditional. - if ($line =~ /do\s*(?!\{)/) { + if ($line =~ /do\s*(?!{)/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); my ($stat_next) = ctx_statement_block($line_nr_next, $remain_next, $off_next); $stat_next =~ s/\n./\n /g; @@ -2617,20 +5669,45 @@ sub process { } } if (!defined $suppress_whiletrailers{$linenr} && + defined($stat) && defined($cond) && $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { my ($s, $c) = ($stat, $cond); + my $fixed_assign_in_if = 0; if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { - ERROR("ASSIGN_IN_IF", - "do not use assignment in if condition\n" . $herecurr); + if (ERROR("ASSIGN_IN_IF", + "do not use assignment in if condition\n" . $herecurr) && + $fix && $perl_version_ok) { + if ($rawline =~ /^\+(\s+)if\s*\(\s*(\!)?\s*\(\s*(($Lval)\s*=\s*$LvalOrFunc)\s*\)\s*(?:($Compare)\s*($FuncArg))?\s*\)\s*(\{)?\s*$/) { + my $space = $1; + my $not = $2; + my $statement = $3; + my $assigned = $4; + my $test = $8; + my $against = $9; + my $brace = $15; + fix_delete_line($fixlinenr, $rawline); + fix_insert_line($fixlinenr, "$space$statement;"); + my $newline = "${space}if ("; + $newline .= '!' if defined($not); + $newline .= '(' if (defined $not && defined($test) && defined($against)); + $newline .= "$assigned"; + $newline .= " $test $against" if (defined($test) && defined($against)); + $newline .= ')' if (defined $not && defined($test) && defined($against)); + $newline .= ')'; + $newline .= " {" if (defined($brace)); + fix_insert_line($fixlinenr + 1, $newline); + $fixed_assign_in_if = 1; + } + } } # Find out what is on the end of the line after the # conditional. substr($s, 0, length($c), ''); $s =~ s/\n.*//g; - $s =~ s/$;//g; # Remove any comments - if (length($c) && $s !~ /^\s*\{?\s*\\*\s*$/ && + $s =~ s/$;//g; # Remove any comments + if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && $c !~ /}\s*while\s*/) { # Find out how long the conditional actually is. @@ -2644,8 +5721,20 @@ sub process { $stat_real = "[...]\n$stat_real"; } - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr . $stat_real); + if (ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr . $stat_real) && + !$fixed_assign_in_if && + $cond_lines == 0 && + $fix && $perl_version_ok && + $fixed[$fixlinenr] =~ /^\+(\s*)((?:if|while|for)\s*$balanced_parens)\s*(.*)$/) { + my $indent = $1; + my $test = $2; + my $rest = rtrim($4); + if ($rest =~ /;$/) { + $fixed[$fixlinenr] = "\+$indent$test"; + fix_insert_line($fixlinenr + 1, "$indent\t$rest"); + } + } } } @@ -2668,8 +5757,8 @@ sub process { # if and else should not have general statements after it if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { my $s = $1; - $s =~ s/$;//g; # Remove any comments - if ($s !~ /^\s*(?:\sif|(?:\{|)\s*\\?\s*$)/) { + $s =~ s/$;//g; # Remove any comments + if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } @@ -2677,7 +5766,7 @@ sub process { # if should not continue a brace if ($line =~ /}\s*if\b/) { ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . + "trailing statements should be on next line (or did you mean 'else if'?)\n" . $herecurr); } # case and default should not have general statements after them @@ -2693,14 +5782,26 @@ sub process { # Check for }<nl>else {, these must be at the same # indent level to be relevant to each other. - if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and - $previndent == $indent) { - ERROR("ELSE_AFTER_BRACE", - "else should follow close brace '}'\n" . $hereprev); + if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ && + $previndent == $indent) { + if (ERROR("ELSE_AFTER_BRACE", + "else should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/}\s*$//; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + $fixedline = $rawline; + $fixedline =~ s/^(.\s*)else/$1} else/; + fix_insert_line($fixlinenr, $fixedline); + } } - if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and - $previndent == $indent) { + if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ && + $previndent == $indent) { my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); # Find out what is on the end of the line after the @@ -2709,25 +5810,84 @@ sub process { $s =~ s/\n.*//g; if ($s =~ /^\s*;/) { - ERROR("WHILE_AFTER_BRACE", - "while should follow close brace '}'\n" . $hereprev); + if (ERROR("WHILE_AFTER_BRACE", + "while should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + my $trailing = $rawline; + $trailing =~ s/^\+//; + $trailing = trim($trailing); + $fixedline =~ s/}\s*$/} $trailing/; + fix_insert_line($fixlinenr, $fixedline); + } } } -#studly caps, commented out until figure out how to distinguish between use of existing and adding new -# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) { -# print "No studly caps, use _\n"; -# print "$herecurr"; -# $clean = 0; -# } +#Specific variable tests + while ($line =~ m{($Constant|$Lval)}g) { + my $var = $1; + +#CamelCase + if (!$OpenOCD) { + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore some autogenerated defines and enum values + $var !~ /^(?:[A-Z]+_){1,5}[A-Z]{1,3}[a-z]/ && +#Ignore Page<foo> variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && +#Ignore SI style variants like nS, mV and dB +#(ie: max_uV, regulator_min_uA_show, RANGE_mA_VALUE) + $var !~ /^(?:[a-z0-9_]*|[A-Z0-9_]*)?_?[a-z][A-Z](?:_[a-z0-9_]+|_[A-Z0-9_]+)?$/ && +#Ignore some three character SI units explicitly, like MiB and KHz + $var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) { + } + } # !$OpenOCD + # OpenOCD Specific: Begin: remove Linux exceptions, extend to camel[0-9_]*CASE + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z]/) { + # OpenOCD Specific: End + while ($var =~ m{\b($Ident)}g) { + my $word = $1; + if (!$OpenOCD) { + next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/); + } # !$OpenOCD + # OpenOCD Specific: Begin: extend to camel[0-9_]*CASE + next if ($word !~ /[A-Z][0-9_]*[a-z]|[a-z][0-9_]*[A-Z]/); + # OpenOCD Specific: End + if (!$OpenOCD) { + # This will not work for OpenOCD jenkins because it runs + # checkpatch from a tree already patched. Any new camelcase + # in include file will be ignored as it was pre-existing. + if ($check) { + seed_camelcase_includes(); + if (!$file && !$camelcase_file_seeded) { + seed_camelcase_file($realfile); + $camelcase_file_seeded = 1; + } + } + } # !$OpenOCD + if (!defined $camelcase{$word}) { + $camelcase{$word} = 1; + CHK("CAMELCASE", + "Avoid CamelCase: <$word>\n" . $herecurr); + } + } + } + } #no spaces allowed after \ in define - if ($line=~/\#\s*define.*\\\s$/) { - WARN("WHITESPACE_AFTER_LINE_CONTINUATION", - "Whitepspace after \\ makes next lines useless\n" . $herecurr); + if ($line =~ /\#\s*define.*\\\s+$/) { + if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION", + "Whitespace after \\ makes next lines useless\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } } -#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line) +# warn if <asm/foo.h> is #included and <linux/foo.h> is available and includes +# itself <asm/foo.h> (uses RAW line) if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) { my $file = "$1.h"; my $checkfile = "include/linux/$file"; @@ -2735,12 +5895,15 @@ sub process { $realfile ne $checkfile && $1 !~ /$allowed_asm_includes/) { - if ($realfile =~ m{^arch/}) { - CHK("ARCH_INCLUDE_LINUX", - "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr); - } else { - WARN("INCLUDE_LINUX", - "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + my $asminclude = `grep -Ec "#include\\s+<asm/$file>" $root/$checkfile`; + if ($asminclude > 0) { + if ($realfile =~ m{^arch/}) { + CHK("ARCH_INCLUDE_LINUX", + "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } else { + WARN("INCLUDE_LINUX", + "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } } } } @@ -2754,101 +5917,201 @@ sub process { my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; - - my $args = defined($1); - - # Find the end of the macro and limit our statement - # search to that. - while ($cnt > 0 && defined $lines[$ln - 1] && - $lines[$ln - 1] =~ /^(?:-|..*\\$)/) - { - $ctx .= $rawlines[$ln - 1] . "\n"; - $cnt-- if ($lines[$ln - 1] !~ /^-/); - $ln++; - } - $ctx .= $rawlines[$ln - 1]; - + my $has_flow_statement = 0; + my $has_arg_concat = 0; ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $ln - $linenr + 1, 0); + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; - # Extract the remainder of the define (if any) and - # rip off surrounding spaces, and trailing \'s. - $rest = ''; - while ($off != 0 || ($cnt > 0 && $rest =~ /\\\s*$/)) { - #print "ADDING cnt<$cnt> $off <" . substr($lines[$ln - 1], $off) . "> rest<$rest>\n"; - if ($off != 0 || $lines[$ln - 1] !~ /^-/) { - $rest .= substr($lines[$ln - 1], $off) . "\n"; - $cnt--; - } - $ln++; - $off = 0; - } - $rest =~ s/\\\n.//g; - $rest =~ s/^\s*//s; - $rest =~ s/\s*$//s; - - # Clean up the original statement. - if ($args) { - substr($dstat, 0, length($dcond), ''); - } else { - $dstat =~ s/^.\s*\#\s*define\s+$Ident\s*//; + $has_flow_statement = 1 if ($ctx =~ /\b(goto|return)\b/); + $has_arg_concat = 1 if ($ctx =~ /\#\#/ && $ctx !~ /\#\#\s*(?:__VA_ARGS__|args)\b/); + + $dstat =~ s/^.\s*\#\s*define\s+$Ident(\([^\)]*\))?\s*//; + my $define_args = $1; + my $define_stmt = $dstat; + my @def_args = (); + + if (defined $define_args && $define_args ne "") { + $define_args = substr($define_args, 1, length($define_args) - 2); + $define_args =~ s/\s*//g; + $define_args =~ s/\\\+?//g; + @def_args = split(",", $define_args); } + $dstat =~ s/$;//g; $dstat =~ s/\\\n.//g; $dstat =~ s/^\s*//s; $dstat =~ s/\s*$//s; # Flatten any parentheses and braces - while ($dstat =~ s/\([^\(\)]*\)/1/ || - $dstat =~ s/\{[^\{\}]*\}/1/ || - $dstat =~ s/\[[^\{\}]*\]/1/) + while ($dstat =~ s/\([^\(\)]*\)/1u/ || + $dstat =~ s/\{[^\{\}]*\}/1u/ || + $dstat =~ s/.\[[^\[\]]*\]/1u/) { } + # Flatten any obvious string concatenation. + while ($dstat =~ s/($String)\s*$Ident/$1/ || + $dstat =~ s/$Ident\s*($String)/$1/) + { + } + + # Make asm volatile uses seem like a generic function + $dstat =~ s/\b_*asm_*\s+_*volatile_*\b/asm_volatile/g; + my $exceptions = qr{ $Declare| module_param_named| - MODULE_PARAM_DESC| + MODULE_PARM_DESC| DECLARE_PER_CPU| DEFINE_PER_CPU| __typeof__\(| union| struct| \.$Ident\s*=\s*| - ^\"|\"$ + ^\"|\"$| + ^\[ }x; #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; - if ($rest ne '' && $rest ne ',') { - if ($rest !~ /while\s*\(/ && - $dstat !~ /$exceptions/) - { + + $ctx =~ s/\n*$//; + my $stmt_cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $stmt_cnt, $here); + + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), + $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); + $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz + $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ && # character constants + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^while\s*$Constant\s*$Constant\s*$/ && # while (...) {...} + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^\(\{/ && # ({... + $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) + { + if ($dstat =~ /^\s*if\b/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros starting with if should be enclosed by a do - while loop to avoid possible if/else logic defects\n" . "$herectx"); + } elsif ($dstat =~ /;/) { ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", - "Macros with multiple statements should be enclosed in a do - while loop\n" . "$here\n$ctx\n"); + "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); + } else { + ERROR("COMPLEX_MACRO", + "Macros with complex values should be enclosed in parentheses\n" . "$herectx"); } - } elsif ($ctx !~ /;/) { - if ($dstat ne '' && - $dstat !~ /^(?:$Ident|-?$Constant)$/ && - $dstat !~ /$exceptions/ && - $dstat !~ /^\.$Ident\s*=/ && - $dstat =~ /$Operators/) - { - ERROR("COMPLEX_MACRO", - "Macros with complex values should be enclosed in parenthesis\n" . "$here\n$ctx\n"); + } + + # Make $define_stmt single line, comment-free, etc + my @stmt_array = split('\n', $define_stmt); + my $first = 1; + $define_stmt = ""; + foreach my $l (@stmt_array) { + $l =~ s/\\$//; + if ($first) { + $define_stmt = $l; + $first = 0; + } elsif ($l =~ /^[\+ ]/) { + $define_stmt .= substr($l, 1); + } + } + $define_stmt =~ s/$;//g; + $define_stmt =~ s/\s+/ /g; + $define_stmt = trim($define_stmt); + +# check if any macro arguments are reused (ignore '...' and 'type') + foreach my $arg (@def_args) { + next if ($arg =~ /\.\.\./); + next if ($arg =~ /^type$/i); + my $tmp_stmt = $define_stmt; + $tmp_stmt =~ s/\b(__must_be_array|offsetof|sizeof|sizeof_field|__stringify|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; + $tmp_stmt =~ s/\#+\s*$arg\b//g; + $tmp_stmt =~ s/\b$arg\s*\#\#//g; + my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g; + if ($use_cnt > 1) { + CHK("MACRO_ARG_REUSE", + "Macro argument reuse '$arg' - possible side-effects?\n" . "$herectx"); + } +# check if any macro arguments may have other precedence issues + if ($tmp_stmt =~ m/($Operators)?\s*\b$arg\b\s*($Operators)?/m && + ((defined($1) && $1 ne ',') || + (defined($2) && $2 ne ','))) { + CHK("MACRO_ARG_PRECEDENCE", + "Macro argument '$arg' may be better as '($arg)' to avoid precedence issues\n" . "$herectx"); } } + +# check for macros with flow control, but without ## concatenation +# ## concatenation is commonly a macro that defines a function so ignore those + if ($has_flow_statement && !$has_arg_concat) { + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("MACRO_WITH_FLOW_CONTROL", + "Macros with flow control statements should be avoided\n" . "$herectx"); + } + +# check for line continuations outside of #defines, preprocessor #, and asm + + } else { + if ($prevline !~ /^..*\\$/ && + $line !~ /^\+\s*\#.*\\$/ && # preprocessor + $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm + $line =~ /^\+.*\\$/) { + WARN("LINE_CONTINUATIONS", + "Avoid unnecessary line continuations\n" . $herecurr); + } } -# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... -# all assignments may have only one of the following with an assignment: -# . -# ALIGN(...) -# VMLINUX_SYMBOL(...) - if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { - WARN("MISSING_VMLINUX_SYMBOL", - "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); +# do {} while (0) macro tests: +# single-statement macros do not need to be enclosed in do while (0) loop, +# macro should not end with a semicolon + if ($perl_version_ok && + $realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + + $dstat =~ s/\\\n.//g; + $dstat =~ s/$;/ /g; + + if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { + my $stmts = $2; + my $semis = $3; + + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + if (($stmts =~ tr/;/;/) == 1 && + $stmts !~ /^\s*(if|while|for|switch)\b/) { + WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", + "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); + } + if (defined $semis && $semis ne "") { + WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", + "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); + } + } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) { + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("TRAILING_SEMICOLON", + "macros should not use a trailing semicolon\n" . "$herectx"); + } } # check for redundant bracing round if etc @@ -2858,7 +6121,8 @@ sub process { #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; if ($#chunks > 0 && $level == 0) { - my $allowed = 0; + my @allowed = (); + my $allow = 0; my $seen = 0; my $herectx = $here . "\n"; my $ln = $linenr - 1; @@ -2869,6 +6133,7 @@ sub process { my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; + $allowed[$allow] = 0; #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; # We have looked at and allowed this specific line. @@ -2879,25 +6144,36 @@ sub process { substr($block, 0, length($cond), ''); - $seen++ if ($block =~ /^\s*\{/); + $seen++ if ($block =~ /^\s*{/); - #print "cond<$cond> block<$block> allowed<$allowed>\n"; + #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; if (statement_lines($cond) > 1) { #print "APW: ALLOWED: cond<$cond>\n"; - $allowed = 1; + $allowed[$allow] = 1; } if ($block =~/\b(?:if|for|while)\b/) { #print "APW: ALLOWED: block<$block>\n"; - $allowed = 1; + $allowed[$allow] = 1; } if (statement_block_size($block) > 1) { #print "APW: ALLOWED: lines block<$block>\n"; - $allowed = 1; + $allowed[$allow] = 1; } + $allow++; } - if ($seen && !$allowed) { - WARN("BRACES", - "braces {} are not necessary for any arm of this statement\n" . $herectx); + if ($seen) { + my $sum_allowed = 0; + foreach (@allowed) { + $sum_allowed += $_; + } + if ($sum_allowed == 0) { + WARN("BRACES", + "braces {} are not necessary for any arm of this statement\n" . $herectx); + } elsif ($sum_allowed != $allow && + $seen != $allow) { + CHK("BRACES", + "braces {} should be used on all arms of this statement\n" . $herectx); + } } } } @@ -2944,71 +6220,377 @@ sub process { } } if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { - my $herectx = $here . "\n"; my $cnt = statement_rawlines($block); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); WARN("BRACES", "braces {} are not necessary for single statement blocks\n" . $herectx); } } -# don't include deprecated include files (uses RAW line) - for my $inc (@dep_includes) { - if ($rawline =~ m@^.\s*\#\s*include\s*\<$inc>@) { - ERROR("DEPRECATED_INCLUDE", - "Don't use <$inc>: see Documentation/feature-removal-schedule.txt\n" . $herecurr); - } +# check for single line unbalanced braces + if ($sline =~ /^.\s*\}\s*else\s*$/ || + $sline =~ /^.\s*else\s*\{\s*$/) { + CHK("BRACES", "Unbalanced braces around else statement\n" . $herecurr); } -# don't use deprecated functions - for my $func (@dep_functions) { - if ($line =~ /\b$func\b/) { - ERROR("DEPRECATED_FUNCTION", - "Don't use $func(): see Documentation/feature-removal-schedule.txt\n" . $herecurr); +# check for unnecessary blank lines around braces + if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) { + if (CHK("BRACES", + "Blank lines aren't necessary before a close brace '}'\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + } + } + if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + if (CHK("BRACES", + "Blank lines aren't necessary after an open brace '{'\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); } } # no volatiles please -# my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; -# if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { -# WARN("VOLATILE", -# "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); -# } + my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; + if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { + WARN("VOLATILE", + "Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst\n" . $herecurr); + } + +# Check for user-visible strings broken across lines, which breaks the ability +# to grep for the string. Make exceptions when the previous string ends in a +# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{' +# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value + if ($line =~ /^\+\s*$String/ && + $prevline =~ /"\s*$/ && + $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) { + if (WARN("SPLIT_STRING", + "quoted string split across lines\n" . $hereprev) && + $fix && + $prevrawline =~ /^\+.*"\s*$/ && + $last_coalesced_string_linenr != $linenr - 1) { + my $extracted_string = get_quoted_string($line, $rawline); + my $comma_close = ""; + if ($rawline =~ /\Q$extracted_string\E(\s*\)\s*;\s*$|\s*,\s*)/) { + $comma_close = $1; + } + + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/"\s*$//; + $fixedline .= substr($extracted_string, 1) . trim($comma_close); + fix_insert_line($fixlinenr - 1, $fixedline); + $fixedline = $rawline; + $fixedline =~ s/\Q$extracted_string\E\Q$comma_close\E//; + if ($fixedline !~ /\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + $last_coalesced_string_linenr = $linenr; + } + } + +# check for missing a space in a string concatenation + if ($prevrawline =~ /[^\\]\w"$/ && $rawline =~ /^\+[\t ]+"\w/) { + WARN('MISSING_SPACE', + "break quoted strings at a space character\n" . $hereprev); + } + +# check for an embedded function name in a string when the function is known +# This does not work very well for -f --file checking as it depends on patch +# context providing the function name or a single line form for in-file +# function declarations + if ($line =~ /^\+.*$String/ && + defined($context_function) && + get_quoted_string($line, $rawline) =~ /\b$context_function\b/ && + length(get_quoted_string($line, $rawline)) != (length($context_function) + 2)) { + WARN("EMBEDDED_FUNCTION_NAME", + "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr); + } + +# check for unnecessary function tracing like uses +# This does not use $logFunctions because there are many instances like +# 'dprintk(FOO, "%s()\n", __func__);' which do not match $logFunctions + if ($rawline =~ /^\+.*\([^"]*"$tracing_logging_tags{0,3}%s(?:\s*\(\s*\)\s*)?$tracing_logging_tags{0,3}(?:\\n)?"\s*,\s*__func__\s*\)\s*;/) { + if (WARN("TRACING_LOGGING", + "Unnecessary ftrace-like logging - prefer using ftrace\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + } + +# check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", + "unnecessary whitespace before a quoted newline\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*\".*)\s+\\n/$1\\n/; + } + + } + +# concatenated string without spaces between elements + if ($line =~ /$String[A-Z_]/ || + ($line =~ /([A-Za-z0-9_]+)$String/ && $1 !~ /^[Lu]$/)) { + if (CHK("CONCATENATED_STRING", + "Concatenated strings should use spaces between elements\n" . $herecurr) && + $fix) { + while ($line =~ /($String)/g) { + my $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]); + $fixed[$fixlinenr] =~ s/\Q$extracted_string\E([A-Za-z0-9_])/$extracted_string $1/; + $fixed[$fixlinenr] =~ s/([A-Za-z0-9_])\Q$extracted_string\E/$1 $extracted_string/; + } + } + } + +# uncoalesced string fragments + if ($line =~ /$String\s*[Lu]?"/) { + if (WARN("STRING_FRAGMENTS", + "Consecutive strings are generally better as a single string\n" . $herecurr) && + $fix) { + while ($line =~ /($String)(?=\s*")/g) { + my $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]); + $fixed[$fixlinenr] =~ s/\Q$extracted_string\E\s*"/substr($extracted_string, 0, -1)/e; + } + } + } + +# check for non-standard and hex prefixed decimal printf formats + my $show_L = 1; #don't show the same defect twice + my $show_Z = 1; + while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { + my $string = substr($rawline, $-[1], $+[1] - $-[1]); + $string =~ s/%%/__/g; + # check for %L + if ($show_L && $string =~ /%[\*\d\.\$]*L([diouxX])/) { + WARN("PRINTF_L", + "\%L$1 is non-standard C, use %ll$1\n" . $herecurr); + $show_L = 0; + } + # check for %Z + if ($show_Z && $string =~ /%[\*\d\.\$]*Z([diouxX])/) { + WARN("PRINTF_Z", + "%Z$1 is non-standard C, use %z$1\n" . $herecurr); + $show_Z = 0; + } + # check for 0x<decimal> + if ($string =~ /0x%[\*\d\.\$\Llzth]*[diou]/) { + ERROR("PRINTF_0XDECIMAL", + "Prefixing 0x with decimal output is defective\n" . $herecurr); + } + } + +# check for line continuations in quoted strings with odd counts of " + if ($rawline =~ /\\$/ && $sline =~ tr/"/"/ % 2) { + WARN("LINE_CONTINUATIONS", + "Avoid line continuations in quoted strings\n" . $herecurr); + } # warn about #if 0 if ($line =~ /^.\s*\#\s*if\s+0\b/) { - CHK("REDUNDANT_CODE", - "if this code is redundant consider removing it\n" . - $herecurr); + WARN("IF_0", + "Consider removing the code enclosed by this #if 0 and its #endif\n" . $herecurr); + } + +# warn about #if 1 + if ($line =~ /^.\s*\#\s*if\s+1\b/) { + WARN("IF_1", + "Consider removing the #if 1 and its #endif\n" . $herecurr); + } + +# check for needless "if (<foo>) fn(<foo>)" uses + if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { + my $tested = quotemeta($1); + my $expr = '\s*\(\s*' . $tested . '\s*\)\s*;'; + if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?|(?:kmem_cache|mempool|dma_pool)_destroy)$expr/) { + my $func = $1; + if (WARN('NEEDLESS_IF', + "$func(NULL) is safe and this check is probably not required\n" . $hereprev) && + $fix) { + my $do_fix = 1; + my $leading_tabs = ""; + my $new_leading_tabs = ""; + if ($lines[$linenr - 2] =~ /^\+(\t*)if\s*\(\s*$tested\s*\)\s*$/) { + $leading_tabs = $1; + } else { + $do_fix = 0; + } + if ($lines[$linenr - 1] =~ /^\+(\t+)$func\s*\(\s*$tested\s*\)\s*;\s*$/) { + $new_leading_tabs = $1; + if (length($leading_tabs) + 1 ne length($new_leading_tabs)) { + $do_fix = 0; + } + } else { + $do_fix = 0; + } + if ($do_fix) { + fix_delete_line($fixlinenr - 1, $prevrawline); + $fixed[$fixlinenr] =~ s/^\+$new_leading_tabs/\+$leading_tabs/; + } + } + } + } + +# check for unnecessary "Out of Memory" messages + if ($line =~ /^\+.*\b$logFunctions\s*\(/ && + $prevline =~ /^[ \+]\s*if\s*\(\s*(\!\s*|NULL\s*==\s*)?($Lval)(\s*==\s*NULL\s*)?\s*\)/ && + (defined $1 || defined $3) && + $linenr > 3) { + my $testval = $2; + my $testline = $lines[$linenr - 3]; + + my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0); +# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n"); + + if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*$allocFunctions\s*\(/ && + $s !~ /\b__GFP_NOWARN\b/ ) { + WARN("OOM_MESSAGE", + "Possible unnecessary 'out of memory' message\n" . $hereprev); + } } -# check for needless kfree() checks - if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { - my $expr = $1; - if ($line =~ /\bkfree\(\Q$expr\E\);/) { - WARN("NEEDLESS_KFREE", - "kfree(NULL) is safe this check is probably not required\n" . $hereprev); +# check for logging functions with KERN_<LEVEL> + if ($line !~ /printk(?:_ratelimited|_once)?\s*\(/ && + $line =~ /\b$logFunctions\s*\(.*\b(KERN_[A-Z]+)\b/) { + my $level = $1; + if (WARN("UNNECESSARY_KERN_LEVEL", + "Possible unnecessary $level\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s*$level\s*//; } } -# check for needless usb_free_urb() checks - if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { - my $expr = $1; - if ($line =~ /\busb_free_urb\(\Q$expr\E\);/) { - WARN("NEEDLESS_USB_FREE_URB", - "usb_free_urb(NULL) is safe this check is probably not required\n" . $hereprev); + +# check for logging continuations + if ($line =~ /\bprintk\s*\(\s*KERN_CONT\b|\bpr_cont\s*\(/) { + WARN("LOGGING_CONTINUATION", + "Avoid logging continuation uses where feasible\n" . $herecurr); + } + +# check for unnecessary use of %h[xudi] and %hh[xudi] in logging functions + if (defined $stat && + $line =~ /\b$logFunctions\s*\(/ && + index($stat, '"') >= 0) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + pos($stat_real) = index($stat_real, '"'); + while ($stat_real =~ /[^\"%]*(%[\#\d\.\*\-]*(h+)[idux])/g) { + my $pspec = $1; + my $h = $2; + my $lineoff = substr($stat_real, 0, $-[1]) =~ tr@\n@@; + if (WARN("UNNECESSARY_MODIFIER", + "Integer promotion: Using '$h' in '$pspec' is unnecessary\n" . "$here\n$stat_real\n") && + $fix && $fixed[$fixlinenr + $lineoff] =~ /^\+/) { + my $nspec = $pspec; + $nspec =~ s/h//g; + $fixed[$fixlinenr + $lineoff] =~ s/\Q$pspec\E/$nspec/; + } + } + } + +# check for mask then right shift without a parentheses + if ($perl_version_ok && + $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ && + $4 !~ /^\&/) { # $LvalOrFunc may be &foo, ignore if so + WARN("MASK_THEN_SHIFT", + "Possible precedence defect with mask then right shift - may need parentheses\n" . $herecurr); + } + +# check for pointer comparisons to NULL + if ($perl_version_ok) { + while ($line =~ /\b$LvalOrFunc\s*(==|\!=)\s*NULL\b/g) { + my $val = $1; + my $equal = "!"; + $equal = "" if ($4 eq "!="); + if (CHK("COMPARISON_TO_NULL", + "Comparison to NULL could be written \"${equal}${val}\"\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b\Q$val\E\s*(?:==|\!=)\s*NULL\b/$equal$val/; + } + } + } + +# check for bad placement of section $InitAttribute (e.g.: __initdata) + if ($line =~ /(\b$InitAttribute\b)/) { + my $attr = $1; + if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) { + my $ptr = $1; + my $var = $2; + if ((($ptr =~ /\b(union|struct)\s+$attr\b/ && + ERROR("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr)) || + ($ptr !~ /\b(union|struct)\s+$attr\b/ && + WARN("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr))) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e; + } + } + } + +# check for $InitAttributeData (ie: __initdata) with const + if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) { + my $attr = $1; + $attr =~ /($InitAttributePrefix)(.*)/; + my $attr_prefix = $1; + my $attr_type = $2; + if (ERROR("INIT_ATTRIBUTE", + "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/$InitAttributeData/${attr_prefix}initconst/; + } + } + +# check for $InitAttributeConst (ie: __initconst) without const + if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) { + my $attr = $1; + if (ERROR("INIT_ATTRIBUTE", + "Use of $attr requires a separate use of const\n" . $herecurr) && + $fix) { + my $lead = $fixed[$fixlinenr] =~ + /(^\+\s*(?:static\s+))/; + $lead = rtrim($1); + $lead = "$lead " if ($lead !~ /^\+$/); + $lead = "${lead}const "; + $fixed[$fixlinenr] =~ s/(^\+\s*(?:static\s+))/$lead/; + } + } + +# check for __read_mostly with const non-pointer (should just be const) + if ($line =~ /\b__read_mostly\b/ && + $line =~ /($Type)\s*$Ident/ && $1 !~ /\*\s*$/ && $1 =~ /\bconst\b/) { + if (ERROR("CONST_READ_MOSTLY", + "Invalid use of __read_mostly with const type\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+__read_mostly\b//; + } + } + +# don't use __constant_<foo> functions outside of include/uapi/ + if ($realfile !~ m@^include/uapi/@ && + $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\s*\(/) { + my $constant_func = $1; + my $func = $constant_func; + $func =~ s/^__constant_//; + if (WARN("CONSTANT_CONVERSION", + "$constant_func should be $func\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$constant_func\b/$func/g; } } # prefer usleep_range over udelay - if ($line =~ /\budelay\s*\(\s*(\w+)\s*\)/) { + if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { + my $delay = $1; # ignore udelay's < 10, however - if (! (($1 =~ /(\d+)/) && ($1 < 10)) ) { + if (! ($delay < 10) ) { CHK("USLEEP_RANGE", - "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); + "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst\n" . $herecurr); + } + if ($delay > 2000) { + WARN("LONG_UDELAY", + "long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\n" . $herecurr); } } @@ -3016,10 +6598,22 @@ sub process { if ($line =~ /\bmsleep\s*\((\d+)\);/) { if ($1 < 20) { WARN("MSLEEP", - "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); + "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst\n" . $herecurr); } } +# check for comparisons of jiffies + if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) { + WARN("JIFFIES_COMPARISON", + "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr); + } + +# check for comparisons of get_jiffies_64() + if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) { + WARN("JIFFIES_COMPARISON", + "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr); + } + # warn about #ifdefs in C files # if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { # print "#ifdef in C files should be avoided\n"; @@ -3029,8 +6623,13 @@ sub process { # warn about spacing in #ifdefs if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { - ERROR("SPACING", - "exactly one space required after that #$1\n" . $herecurr); + if (ERROR("SPACING", + "exactly one space required after that #$1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /; + } + } # check for spinlock_t definitions without a comment. @@ -3043,22 +6642,77 @@ sub process { } } # check for memory barriers without a comment. - if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { + + my $barriers = qr{ + mb| + rmb| + wmb + }x; + my $barrier_stems = qr{ + mb__before_atomic| + mb__after_atomic| + store_release| + load_acquire| + store_mb| + (?:$barriers) + }x; + my $all_barriers = qr{ + (?:$barriers)| + smp_(?:$barrier_stems)| + virt_(?:$barrier_stems) + }x; + + if ($line =~ /\b(?:$all_barriers)\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("MEMORY_BARRIER", + "memory barrier without comment\n" . $herecurr); + } + } + + my $underscore_smp_barriers = qr{__smp_(?:$barrier_stems)}x; + + if ($realfile !~ m@^include/asm-generic/@ && + $realfile !~ m@/barrier\.h$@ && + $line =~ m/\b(?:$underscore_smp_barriers)\s*\(/ && + $line !~ m/^.\s*\#\s*define\s+(?:$underscore_smp_barriers)\s*\(/) { + WARN("MEMORY_BARRIER", + "__smp memory barriers shouldn't be used outside barrier.h and asm-generic\n" . $herecurr); + } + +# check for waitqueue_active without a comment. + if ($line =~ /\bwaitqueue_active\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("WAITQUEUE_ACTIVE", + "waitqueue_active without comment\n" . $herecurr); + } + } + +# check for data_race without a comment. + if ($line =~ /\bdata_race\s*\(/) { if (!ctx_has_comment($first_line, $linenr)) { - CHK("MEMORY_BARRIER", - "memory barrier without comment\n" . $herecurr); + WARN("DATA_RACE", + "data_race without comment\n" . $herecurr); } } + # check of hardware specific defines if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { CHK("ARCH_DEFINES", "architecture specific defines should be avoided\n" . $herecurr); } +# check that the storage class is not after a type + if ($line =~ /\b($Type)\s+($Storage)\b/) { + WARN("STORAGE_CLASS", + "storage class '$2' should be located before type '$1'\n" . $herecurr); + } # Check that the storage class is at the beginning of a declaration - if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { + if ($line =~ /\b$Storage\b/ && + $line !~ /^.\s*$Storage/ && + $line =~ /^.\s*(.+?)\$Storage\s/ && + $1 !~ /[\,\)]\s*$/) { WARN("STORAGE_CLASS", - "storage class should be at the beginning of the declaration\n" . $herecurr) + "storage class should be at the beginning of the declaration\n" . $herecurr); } # check the location of the inline attribute, that it is between @@ -3070,22 +6724,128 @@ sub process { } # Check for __inline__ and __inline, prefer inline - if ($line =~ /\b(__inline__|__inline)\b/) { - WARN("INLINE", - "plain inline is preferred over $1\n" . $herecurr); + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b(__inline__|__inline)\b/) { + if (WARN("INLINE", + "plain inline is preferred over $1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b(__inline__|__inline)\b/inline/; + + } } -# Check for __attribute__ packed, prefer __packed -# if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { -# WARN("PREFER_PACKED", -# "__packed is preferred over __attribute__((packed))\n" . $herecurr); -# } +# Check for compiler attributes + if ($realfile !~ m@\binclude/uapi/@ && + $rawline =~ /\b__attribute__\s*\(\s*($balanced_parens)\s*\)/) { + my $attr = $1; + $attr =~ s/\s*\(\s*(.*)\)\s*/$1/; + + my %attr_list = ( + "alias" => "__alias", + "aligned" => "__aligned", + "always_inline" => "__always_inline", + "assume_aligned" => "__assume_aligned", + "cold" => "__cold", + "const" => "__attribute_const__", + "copy" => "__copy", + "designated_init" => "__designated_init", + "externally_visible" => "__visible", + "format" => "printf|scanf", + "gnu_inline" => "__gnu_inline", + "malloc" => "__malloc", + "mode" => "__mode", + "no_caller_saved_registers" => "__no_caller_saved_registers", + "noclone" => "__noclone", + "noinline" => "noinline", + "nonstring" => "__nonstring", + "noreturn" => "__noreturn", + "packed" => "__packed", + "pure" => "__pure", + "section" => "__section", + "used" => "__used", + "weak" => "__weak" + ); + + while ($attr =~ /\s*(\w+)\s*(${balanced_parens})?/g) { + my $orig_attr = $1; + my $params = ''; + $params = $2 if defined($2); + my $curr_attr = $orig_attr; + $curr_attr =~ s/^[\s_]+|[\s_]+$//g; + if (exists($attr_list{$curr_attr})) { + my $new = $attr_list{$curr_attr}; + if ($curr_attr eq "format" && $params) { + $params =~ /^\s*\(\s*(\w+)\s*,\s*(.*)/; + $new = "__$1\($2"; + } else { + $new = "$new$params"; + } + if (WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", + "Prefer $new over __attribute__(($orig_attr$params))\n" . $herecurr) && + $fix) { + my $remove = "\Q$orig_attr\E" . '\s*' . "\Q$params\E" . '(?:\s*,\s*)?'; + $fixed[$fixlinenr] =~ s/$remove//; + $fixed[$fixlinenr] =~ s/\b__attribute__/$new __attribute__/; + $fixed[$fixlinenr] =~ s/\}\Q$new\E/} $new/; + $fixed[$fixlinenr] =~ s/ __attribute__\s*\(\s*\(\s*\)\s*\)//; + } + } + } -# Check for __attribute__ aligned, prefer __aligned -# if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { -# WARN("PREFER_ALIGNED", -# "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); -# } + # Check for __attribute__ unused, prefer __always_unused or __maybe_unused + if ($attr =~ /^_*unused/) { + WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", + "__always_unused or __maybe_unused is preferred over __attribute__((__unused__))\n" . $herecurr); + } + } + +# Check for __attribute__ weak, or __weak declarations (may have link issues) + if ($perl_version_ok && + $line =~ /(?:$Declare|$DeclareMisordered)\s*$Ident\s*$balanced_parens\s*(?:$Attribute)?\s*;/ && + ($line =~ /\b__attribute__\s*\(\s*\(.*\bweak\b/ || + $line =~ /\b__weak\b/)) { + ERROR("WEAK_DECLARATION", + "Using weak declarations can have unintended link defects\n" . $herecurr); + } + +# check for c99 types like uint8_t used outside of uapi/ and tools/ + if ($realfile !~ m@\binclude/uapi/@ && + $realfile !~ m@\btools/@ && + $line =~ /\b($Declare)\s*$Ident\s*[=;,\[]/) { + my $type = $1; + if ($type =~ /\b($typeC99Typedefs)\b/) { + $type = $1; + my $kernel_type = 'u'; + $kernel_type = 's' if ($type =~ /^_*[si]/); + $type =~ /(\d+)/; + $kernel_type .= $1; + if (CHK("PREFER_KERNEL_TYPES", + "Prefer kernel type '$kernel_type' over '$type'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$type\b/$kernel_type/; + } + } + } + +# check for cast of C90 native int or longer types constants + if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) { + my $cast = $1; + my $const = $2; + my $suffix = ""; + my $newconst = $const; + $newconst =~ s/${Int_type}$//; + $suffix .= 'U' if ($cast =~ /\bunsigned\b/); + if ($cast =~ /\blong\s+long\b/) { + $suffix .= 'LL'; + } elsif ($cast =~ /\blong\b/) { + $suffix .= 'L'; + } + if (WARN("TYPECAST_INT_CONSTANT", + "Unnecessary typecast of c90 int constant - '$cast$const' could be '$const$suffix'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/; + } + } # check for sizeof(&) if ($line =~ /\bsizeof\s*\(\s*\&/) { @@ -3093,156 +6853,573 @@ sub process { "sizeof(& should be avoided\n" . $herecurr); } -# check for line continuations in quoted strings with odd counts of " - if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { - WARN("LINE_CONTINUATIONS", - "Avoid line continuations in quoted strings\n" . $herecurr); +# check for sizeof without parenthesis + if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { + if (WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex; + } } -# check for new externs in .c files. -# if ($realfile =~ /\.c$/ && defined $stat && -# $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) -# { -# my $function_name = $1; -# my $paren_space = $2; -# -# my $s = $stat; -# if (defined $cond) { -# substr($s, 0, length($cond), ''); -# } -# if ($s =~ /^\s*;/ && -# $function_name ne 'uninitialized_var') -# { -# WARN("AVOID_EXTERNS", -# "externs should be avoided in .c files\n" . $herecurr); +# check for struct spinlock declarations + if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { + WARN("USE_SPINLOCK_T", + "struct spinlock should be spinlock_t\n" . $herecurr); + } + +# check for seq_printf uses that could be seq_puts + if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) { + my $fmt = get_quoted_string($line, $rawline); + $fmt =~ s/%%//g; + if ($fmt !~ /%/) { + if (WARN("PREFER_SEQ_PUTS", + "Prefer seq_puts to seq_printf\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bseq_printf\b/seq_puts/; + } + } + } + +# check for vsprintf extension %p<foo> misuses + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s && + $1 !~ /^_*volatile_*$/) { + my $stat_real; + + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + for (my $count = $linenr; $count <= $lc; $count++) { + my $specifier; + my $extension; + my $qualifier; + my $bad_specifier = ""; + my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0)); + $fmt =~ s/%%//g; + + while ($fmt =~ /(\%[\*\d\.]*p(\w)(\w*))/g) { + $specifier = $1; + $extension = $2; + $qualifier = $3; + if ($extension !~ /[4SsBKRraEehMmIiUDdgVCbGNOxtf]/ || + ($extension eq "f" && + defined $qualifier && $qualifier !~ /^w/) || + ($extension eq "4" && + defined $qualifier && $qualifier !~ /^cc/)) { + $bad_specifier = $specifier; + last; + } + if ($extension eq "x" && !defined($stat_real)) { + if (!defined($stat_real)) { + $stat_real = get_stat_real($linenr, $lc); + } + WARN("VSPRINTF_SPECIFIER_PX", + "Using vsprintf specifier '\%px' potentially exposes the kernel memory layout, if you don't really need the address please consider using '\%p'.\n" . "$here\n$stat_real\n"); + } + } + if ($bad_specifier ne "") { + my $stat_real = get_stat_real($linenr, $lc); + my $ext_type = "Invalid"; + my $use = ""; + if ($bad_specifier =~ /p[Ff]/) { + $use = " - use %pS instead"; + $use =~ s/pS/ps/ if ($bad_specifier =~ /pf/); + } + + WARN("VSPRINTF_POINTER_EXTENSION", + "$ext_type vsprintf pointer extension '$bad_specifier'$use\n" . "$here\n$stat_real\n"); + } + } + } + +# Check for misused memsets + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/) { + + my $ms_addr = $2; + my $ms_val = $7; + my $ms_size = $12; + + if ($ms_size =~ /^(0x|)0$/i) { + ERROR("MEMSET", + "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); + } elsif ($ms_size =~ /^(0x|)1$/i) { + WARN("MEMSET", + "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); + } + } + +# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { +# if (WARN("PREFER_ETHER_ADDR_COPY", +# "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/; # } +# } + +# Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar) +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemcmp\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { +# WARN("PREFER_ETHER_ADDR_EQUAL", +# "Prefer ether_addr_equal() or ether_addr_equal_unaligned() over memcmp()\n" . "$here\n$stat\n") +# } + +# check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr +# check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { # -# if ($paren_space =~ /\n/) { -# WARN("FUNCTION_ARGUMENTS", -# "arguments for function declarations should follow identifier\n" . $herecurr); -# } +# my $ms_val = $7; # -# } elsif ($realfile =~ /\.c$/ && defined $stat && -# $stat =~ /^.\s*extern\s+/) -# { -# WARN("AVOID_EXTERNS", -# "externs should be avoided in .c files\n" . $herecurr); +# if ($ms_val =~ /^(?:0x|)0+$/i) { +# if (WARN("PREFER_ETH_ZERO_ADDR", +# "Prefer eth_zero_addr over memset()\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_zero_addr($2)/; +# } +# } elsif ($ms_val =~ /^(?:0xff|255)$/i) { +# if (WARN("PREFER_ETH_BROADCAST_ADDR", +# "Prefer eth_broadcast_addr() over memset()\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_broadcast_addr($2)/; +# } +# } # } +# strlcpy uses that should likely be strscpy + if ($line =~ /\bstrlcpy\s*\(/) { + WARN("STRLCPY", + "Prefer strscpy over strlcpy - see: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw\@mail.gmail.com/\n" . $herecurr); + } + +# typecasts on min/max could be min_t/max_t + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { + if (defined $2 || defined $7) { + my $call = $1; + my $cast1 = deparenthesize($2); + my $arg1 = $3; + my $cast2 = deparenthesize($7); + my $arg2 = $8; + my $cast; + + if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { + $cast = "$cast1 or $cast2"; + } elsif ($cast1 ne "") { + $cast = $cast1; + } else { + $cast = $cast2; + } + WARN("MINMAX", + "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); + } + } + +# check usleep_range arguments + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { + my $min = $1; + my $max = $7; + if ($min eq $max) { + WARN("USLEEP_RANGE", + "usleep_range should not use min == max args; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n"); + } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && + $min > $max) { + WARN("USLEEP_RANGE", + "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n"); + } + } + +# check for naked sscanf + if ($perl_version_ok && + defined $stat && + $line =~ /\bsscanf\b/ && + ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && + $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ && + $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + WARN("NAKED_SSCANF", + "unchecked sscanf return value\n" . "$here\n$stat_real\n"); + } + +# check for simple sscanf that should be kstrto<foo> + if ($perl_version_ok && + defined $stat && + $line =~ /\bsscanf\b/) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) { + my $format = $6; + my $count = $format =~ tr@%@%@; + if ($count == 1 && + $format =~ /^"\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])"$/) { + WARN("SSCANF_TO_KSTRTO", + "Prefer kstrto<type> to single variable sscanf\n" . "$here\n$stat_real\n"); + } + } + } + +# check for new externs in .h files. + if ($realfile =~ /\.h$/ && + $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) { + if (CHK("AVOID_EXTERNS", + "extern prototypes should be avoided in .h files\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(.*)\bextern\b\s*(.*)/$1$2/; + } + } + +# check for new externs in .c files. + if ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) + { + my $function_name = $1; + my $paren_space = $2; + + my $s = $stat; + if (defined $cond) { + substr($s, 0, length($cond), ''); + } + if ($s =~ /^\s*;/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + + if ($paren_space =~ /\n/) { + WARN("FUNCTION_ARGUMENTS", + "arguments for function declarations should follow identifier\n" . $herecurr); + } + + } elsif ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*extern\s+/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + +# check for function declarations that have arguments without identifier names + if (defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && + $1 ne "void") { + my $args = trim($1); + while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) { + my $arg = trim($1); + if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) { + WARN("FUNCTION_ARGUMENTS", + "function definition argument '$arg' should also have an identifier name\n" . $herecurr); + } + } + } + +# check for function definitions + if ($perl_version_ok && + defined $stat && + $stat =~ /^.\s*(?:$Storage\s+)?$Type\s*($Ident)\s*$balanced_parens\s*{/s) { + $context_function = $1; + +# check for multiline function definition with misplaced open brace + my $ok = 0; + my $cnt = statement_rawlines($stat); + my $herectx = $here . "\n"; + for (my $n = 0; $n < $cnt; $n++) { + my $rl = raw_line($linenr, $n); + $herectx .= $rl . "\n"; + $ok = 1 if ($rl =~ /^[ \+]\{/); + $ok = 1 if ($rl =~ /\{/ && $n == 0); + last if $rl =~ /^[ \+].*\{/; + } + if (!$ok) { + ERROR("OPEN_BRACE", + "open brace '{' following function definitions go on the next line\n" . $herectx); + } + } + # checks for new __setup's if ($rawline =~ /\b__setup\("([^"]*)"/) { my $name = $1; if (!grep(/$name/, @setup_docs)) { CHK("UNDOCUMENTED_SETUP", - "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); + "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.txt\n" . $herecurr); } } -# check for pointless casting of kmalloc return - if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { +# check for pointless casting of alloc functions + if ($line =~ /\*\s*\)\s*$allocFunctions\b/) { WARN("UNNECESSARY_CASTS", "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); } +# alloc style +# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) + if ($perl_version_ok && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k|v)[mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { + CHK("ALLOC_SIZEOF_STRUCT", + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +# check for (kv|k)[mz]alloc with multiplies that could be kmalloc_array/kvmalloc_array/kvcalloc/kcalloc + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { + my $oldfunc = $3; + my $a1 = $4; + my $a2 = $10; + my $newfunc = "kmalloc_array"; + $newfunc = "kvmalloc_array" if ($oldfunc eq "kvmalloc"); + $newfunc = "kvcalloc" if ($oldfunc eq "kvzalloc"); + $newfunc = "kcalloc" if ($oldfunc eq "kzalloc"); + my $r1 = $a1; + my $r2 = $a2; + if ($a1 =~ /^sizeof\s*\S/) { + $r1 = $a2; + $r2 = $a1; + } + if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ && + !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + + if (WARN("ALLOC_WITH_MULTIPLY", + "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) && + $cnt == 1 && + $fix) { + $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e; + } + } + } + +# check for krealloc arg reuse + if ($perl_version_ok && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*($Lval)\s*,/ && + $1 eq $3) { + WARN("KREALLOC_ARG_REUSE", + "Reusing the krealloc arg is almost always a bug\n" . $herecurr); + } + +# check for alloc argument mismatch + if ($line =~ /\b((?:devm_)?(?:kcalloc|kmalloc_array))\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } + # check for multiple semicolons if ($line =~ /;\s*;\s*$/) { - WARN("ONE_SEMICOLON", - "Statements terminations use 1 semicolon\n" . $herecurr); + if (WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\s*;\s*){2,}$/;/g; + } + } + +# check for #defines like: 1 << <digit> that could be BIT(digit), it is not exported to uapi + if ($realfile !~ m@^include/uapi/@ && + $line =~ /#\s*define\s+\w+\s+\(?\s*1\s*([ulUL]*)\s*\<\<\s*(?:\d+|$Ident)\s*\)?/) { + my $ull = ""; + $ull = "_ULL" if (defined($1) && $1 =~ /ll/i); + if (CHK("BIT_MACRO", + "Prefer using the BIT$ull macro\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\(?\s*1\s*[ulUL]*\s*<<\s*(\d+|$Ident)\s*\)?/BIT${ull}($1)/; + } + } + +# check for IS_ENABLED() without CONFIG_<FOO> ($rawline for comments too) + if ($rawline =~ /\bIS_ENABLED\s*\(\s*(\w+)\s*\)/ && $1 !~ /^${CONFIG_}/) { + WARN("IS_ENABLED_CONFIG", + "IS_ENABLED($1) is normally used as IS_ENABLED(${CONFIG_}$1)\n" . $herecurr); + } + +# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE + if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(${CONFIG_}[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { + my $config = $1; + if (WARN("PREFER_IS_ENABLED", + "Prefer IS_ENABLED(<FOO>) to ${CONFIG_}<FOO> || ${CONFIG_}<FOO>_MODULE\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; + } + } + +# check for /* fallthrough */ like comment, prefer fallthrough; + my @fallthroughs = ( + 'fallthrough', + '@fallthrough@', + 'lint -fallthrough[ \t]*', + 'intentional(?:ly)?[ \t]*fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)', + '(?:else,?\s*)?FALL(?:S | |-)?THR(?:OUGH|U|EW)[ \t.!]*(?:-[^\n\r]*)?', + 'Fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?', + 'fall(?:s | |-)?thr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?', + ); + if ($raw_comment ne '') { + foreach my $ft (@fallthroughs) { + if ($raw_comment =~ /$ft/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}("PREFER_FALLTHROUGH", + "Prefer 'fallthrough;' over fallthrough comment\n" . $herecurr); + last; + } + } + } + +# check for switch/default statements without a break; + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("DEFAULT_NO_BREAK", + "switch default: should use break\n" . $herectx); } # check for gcc specific __FUNCTION__ - if ($line =~ /__FUNCTION__/) { - WARN("USE_FUNC", - "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); + if ($line =~ /\b__FUNCTION__\b/) { + if (WARN("USE_FUNC", + "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__FUNCTION__\b/__func__/g; + } + } + +# check for uses of __DATE__, __TIME__, __TIMESTAMP__ + while ($line =~ /\b(__(?:DATE|TIME|TIMESTAMP)__)\b/g) { + ERROR("DATE_TIME", + "Use of the '$1' macro makes the build non-deterministic\n" . $herecurr); + } + +# check for use of yield() + if ($line =~ /\byield\s*\(\s*\)/) { + WARN("YIELD", + "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); + } + +# check for comparisons against true and false + if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) { + my $lead = $1; + my $arg = $2; + my $test = $3; + my $otype = $4; + my $trail = $5; + my $op = "!"; + + ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i); + + my $type = lc($otype); + if ($type =~ /^(?:true|false)$/) { + if (("$test" eq "==" && "$type" eq "true") || + ("$test" eq "!=" && "$type" eq "false")) { + $op = ""; + } + + CHK("BOOL_COMPARISON", + "Using comparison to $otype is error prone\n" . $herecurr); + +## maybe suggesting a correct construct would better +## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr); + + } } # check for semaphores initialized locked if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { WARN("CONSIDER_COMPLETION", "consider using a completion\n" . $herecurr); - } -# recommend kstrto* over simple_strto* - if ($line =~ /\bsimple_(strto.*?)\s*\(/) { + +# recommend kstrto* over simple_strto* and strict_strto* + if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { WARN("CONSIDER_KSTRTO", - "consider using kstrto* in preference to simple_$1\n" . $herecurr); + "$1 is obsolete, use k$3 instead\n" . $herecurr); } -# check for __initcall(), use device_initcall() explicitly please + +# check for __initcall(), use device_initcall() explicitly or more appropriate function please if ($line =~ /^.\s*__initcall\s*\(/) { WARN("USE_DEVICE_INITCALL", - "please use device_initcall() instead of __initcall()\n" . $herecurr); - } -# check for various ops structs, ensure they are const. - my $struct_ops = qr{acpi_dock_ops| - address_space_operations| - backlight_ops| - block_device_operations| - dentry_operations| - dev_pm_ops| - dma_map_ops| - extent_io_ops| - file_lock_operations| - file_operations| - hv_ops| - ide_dma_ops| - intel_dvo_dev_ops| - item_operations| - iwl_ops| - kgdb_arch| - kgdb_io| - kset_uevent_ops| - lock_manager_operations| - microcode_ops| - mtrr_ops| - neigh_ops| - nlmsvc_binding| - pci_raw_ops| - pipe_buf_operations| - platform_hibernation_ops| - platform_suspend_ops| - proto_ops| - rpc_pipe_ops| - seq_operations| - snd_ac97_build_ops| - soc_pcmcia_socket_ops| - stacktrace_ops| - sysfs_ops| - tty_operations| - usb_mon_operations| - wd_ops}x; - if ($line !~ /\bconst\b/ && - $line =~ /\bstruct\s+($struct_ops)\b/) { + "please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr); + } + +# check for spin_is_locked(), suggest lockdep instead + if ($line =~ /\bspin_is_locked\(/) { + WARN("USE_LOCKDEP", + "Where possible, use lockdep_assert_held instead of assertions based on spin_is_locked\n" . $herecurr); + } + +# check for deprecated apis + if ($line =~ /\b($deprecated_apis_search)\b\s*\(/) { + my $deprecated_api = $1; + my $new_api = $deprecated_apis{$deprecated_api}; + WARN("DEPRECATED_API", + "Deprecated use of '$deprecated_api', prefer '$new_api' instead\n" . $herecurr); + } + +# check for various structs that are normally const (ops, kgdb, device_tree) +# and avoid what seem like struct definitions 'struct foo {' + if (defined($const_structs) && + $line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) { WARN("CONST_STRUCT", - "struct $1 should normally be const\n" . - $herecurr); + "struct $1 should normally be const\n" . $herecurr); } # use of NR_CPUS is usually wrong # ignore definitions of NR_CPUS and usage to define arrays as likely right +# ignore designated initializers using NR_CPUS if ($line =~ /\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/ && + $line !~ /^.\s*\.\w+\s*=\s*.*\bNR_CPUS\b/) { WARN("NR_CPUS", "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); } -# check for %L{u,d,i} in strings - my $string; - while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { - $string = substr($rawline, $-[1], $+[1] - $-[1]); - $string =~ s/%%/__/g; - if ($string =~ /(?<!%)%L[udi]/) { - WARN("PRINTF_L", - "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr); - last; +# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong. + if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) { + ERROR("DEFINE_ARCH_HAS", + "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr); + } + +# likely/unlikely comparisons similar to "(likely(foo) > 0)" + if ($perl_version_ok && + $line =~ /\b((?:un)?likely)\s*\(\s*$FuncArg\s*\)\s*$Compare/) { + WARN("LIKELY_MISUSE", + "Using $1 should generally have parentheses around the comparison\n" . $herecurr); + } + +# return sysfs_emit(foo, fmt, ...) fmt without newline + if ($line =~ /\breturn\s+sysfs_emit\s*\(\s*$FuncArg\s*,\s*($String)/ && + substr($rawline, $-[6], $+[6] - $-[6]) !~ /\\n"$/) { + my $offset = $+[6] - 1; + if (WARN("SYSFS_EMIT", + "return sysfs_emit(...) formats should include a terminating newline\n" . $herecurr) && + $fix) { + substr($fixed[$fixlinenr], $offset, 0) = '\\n'; } } +# nested likely/unlikely calls + if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) { + WARN("LIKELY_MISUSE", + "nested (un)?likely() calls, $1 already uses unlikely() internally\n" . $herecurr); + } + # whine mightly about in_atomic if ($line =~ /\bin_atomic\s*\(/) { if ($realfile =~ m@^drivers/@) { @@ -3265,16 +7442,149 @@ sub process { } } - if ($line =~ /debugfs_create_file.*S_IWUGO/ || - $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { + if ($line =~ /debugfs_create_\w+.*\b$mode_perms_world_writable\b/ || + $line =~ /DEVICE_ATTR.*\b$mode_perms_world_writable\b/) { WARN("EXPORTED_WORLD_WRITABLE", "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); } - # Check for memset with swapped arguments - if ($line =~ /memset.*\,(\ |)(0x|)0(\ |0|)\);/) { - ERROR("MEMSET", - "memset size is 3rd argument, not the second.\n" . $herecurr); +# check for DEVICE_ATTR uses that could be DEVICE_ATTR_<FOO> +# and whether or not function naming is typical and if +# DEVICE_ATTR permissions uses are unusual too + if ($perl_version_ok && + defined $stat && + $stat =~ /\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?\s*(\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\s*)\s*\)?\s*,\s*(\w+)\s*,\s*(\w+)\s*\)/) { + my $var = $1; + my $perms = $2; + my $show = $3; + my $store = $4; + my $octal_perms = perms_to_octal($perms); + if ($show =~ /^${var}_show$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0644") { + if (WARN("DEVICE_ATTR_RW", + "Use DEVICE_ATTR_RW\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*$store\s*\)/DEVICE_ATTR_RW(${var})/; + } + } elsif ($show =~ /^${var}_show$/ && + $store =~ /^NULL$/ && + $octal_perms eq "0444") { + if (WARN("DEVICE_ATTR_RO", + "Use DEVICE_ATTR_RO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*NULL\s*\)/DEVICE_ATTR_RO(${var})/; + } + } elsif ($show =~ /^NULL$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0200") { + if (WARN("DEVICE_ATTR_WO", + "Use DEVICE_ATTR_WO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*NULL\s*,\s*$store\s*\)/DEVICE_ATTR_WO(${var})/; + } + } elsif ($octal_perms eq "0644" || + $octal_perms eq "0444" || + $octal_perms eq "0200") { + my $newshow = "$show"; + $newshow = "${var}_show" if ($show ne "NULL" && $show ne "${var}_show"); + my $newstore = $store; + $newstore = "${var}_store" if ($store ne "NULL" && $store ne "${var}_store"); + my $rename = ""; + if ($show ne $newshow) { + $rename .= " '$show' to '$newshow'"; + } + if ($store ne $newstore) { + $rename .= " '$store' to '$newstore'"; + } + WARN("DEVICE_ATTR_FUNCTIONS", + "Consider renaming function(s)$rename\n" . $herecurr); + } else { + WARN("DEVICE_ATTR_PERMS", + "DEVICE_ATTR unusual permissions '$perms' used\n" . $herecurr); + } + } + +# Mode permission misuses where it seems decimal should be octal +# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop +# o Ignore module_param*(...) uses with a decimal 0 permission as that has a +# specific definition of not visible in sysfs. +# o Ignore proc_create*(...) uses with a decimal 0 permission as that means +# use the default permissions + if ($perl_version_ok && + defined $stat && + $line =~ /$mode_perms_search/) { + foreach my $entry (@mode_permission_funcs) { + my $func = $entry->[0]; + my $arg_pos = $entry->[1]; + + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + + my $skip_args = ""; + if ($arg_pos > 1) { + $arg_pos--; + $skip_args = "(?:\\s*$FuncArg\\s*,\\s*){$arg_pos,$arg_pos}"; + } + my $test = "\\b$func\\s*\\(${skip_args}($FuncArg(?:\\|\\s*$FuncArg)*)\\s*[,\\)]"; + if ($stat =~ /$test/) { + my $val = $1; + $val = $6 if ($skip_args ne ""); + if (!($func =~ /^(?:module_param|proc_create)/ && $val eq "0") && + (($val =~ /^$Int$/ && $val !~ /^$Octal$/) || + ($val =~ /^$Octal$/ && length($val) ne 4))) { + ERROR("NON_OCTAL_PERMISSIONS", + "Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real); + } + if ($val =~ /^$Octal$/ && (oct($val) & 02)) { + ERROR("EXPORTED_WORLD_WRITABLE", + "Exporting writable files is usually an error. Consider more restrictive permissions.\n" . "$here\n" . $stat_real); + } + } + } + } + +# check for uses of S_<PERMS> that could be octal for readability + while ($line =~ m{\b($multi_mode_perms_string_search)\b}g) { + my $oval = $1; + my $octal = perms_to_octal($oval); + if (WARN("SYMBOLIC_PERMS", + "Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$oval\E/$octal/; + } + } + +# validate content of MODULE_LICENSE against list from include/linux/module.h + if ($line =~ /\bMODULE_LICENSE\s*\(\s*($String)\s*\)/) { + my $extracted_string = get_quoted_string($line, $rawline); + my $valid_licenses = qr{ + GPL| + GPL\ v2| + GPL\ and\ additional\ rights| + Dual\ BSD/GPL| + Dual\ MIT/GPL| + Dual\ MPL/GPL| + Proprietary + }x; + if ($extracted_string !~ /^"(?:$valid_licenses)"$/x) { + WARN("MODULE_LICENSE", + "unknown module license " . $extracted_string . "\n" . $herecurr); + } + if (!$file && $extracted_string eq '"GPL v2"') { + if (WARN("MODULE_LICENSE", + "Prefer \"GPL\" over \"GPL v2\" - see commit bf7fbeeae6db (\"module: Cure the MODULE_LICENSE \"GPL\" vs. \"GPL v2\" bogosity\")\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bMODULE_LICENSE\s*\(\s*"GPL v2"\s*\)/MODULE_LICENSE("GPL")/; + } + } + } + +# check for sysctl duplicate constants + if ($line =~ /\.extra[12]\s*=\s*&(zero|one|int_max)\b/) { + WARN("DUPLICATED_SYSCTL_CONST", + "duplicated sysctl range checking value '$1', consider using the shared one in include/linux/sysctl.h\n" . $herecurr); } } @@ -3290,61 +7600,131 @@ sub process { exit(0); } - # This is not a patch, and we are are in 'no-patch' mode so + # This is not a patch, and we are in 'no-patch' mode so # just keep quiet. if (!$chk_patch && !$is_patch) { exit(0); } - if (!$is_patch) { + if (!$is_patch && $filename !~ /cover-letter\.patch$/) { ERROR("NOT_UNIFIED_DIFF", "Does not appear to be a unified-diff format patch\n"); } - if ($is_patch && $chk_signoff && $signoff == 0) { - ERROR("MISSING_SIGN_OFF", - "Missing Signed-off-by: line(s)\n"); + if ($is_patch && $has_commit_log && $chk_signoff) { + if ($signoff == 0) { + ERROR("MISSING_SIGN_OFF", + "Missing Signed-off-by: line(s)\n"); + } elsif ($authorsignoff != 1) { + # authorsignoff values: + # 0 -> missing sign off + # 1 -> sign off identical + # 2 -> names and addresses match, comments mismatch + # 3 -> addresses match, names different + # 4 -> names match, addresses different + # 5 -> names match, addresses excluding subaddress details (refer RFC 5233) match + + my $sob_msg = "'From: $author' != 'Signed-off-by: $author_sob'"; + + if ($authorsignoff == 0) { + ERROR("NO_AUTHOR_SIGN_OFF", + "Missing Signed-off-by: line by nominal patch author '$author'\n"); + } elsif ($authorsignoff == 2) { + CHK("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email comments mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 3) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email name mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 4) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email address mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 5) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email subaddress mismatch: $sob_msg\n"); + } + } } print report_dump(); if ($summary && !($clean == 1 && $quiet == 1)) { print "$filename " if ($summary_file); + if (!$OpenOCD) { print "total: $cnt_error errors, $cnt_warn warnings, " . (($check)? "$cnt_chk checks, " : "") . "$cnt_lines lines checked\n"; - print "\n" if ($quiet == 0); + } # $OpenOCD + # OpenOCD specific: Begin: Report total as errors + my $total = $cnt_error + $cnt_warn + $cnt_chk; + print "total: $total errors, $cnt_lines lines checked\n"; + # OpenOCD specific: End } if ($quiet == 0) { + # If there were any defects found and not already fixing them + if (!$clean and !$fix) { + print << "EOM" + +NOTE: For some of the reported defects, checkpatch may be able to + mechanically convert to the typical style using --fix or --fix-inplace. +EOM + } # If there were whitespace errors which cleanpatch can fix # then suggest that. if ($rpt_cleaners) { - print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; - print " scripts/cleanfile\n\n"; $rpt_cleaners = 0; + print << "EOM" + +NOTE: Whitespace errors detected. + You may wish to use scripts/cleanpatch or scripts/cleanfile +EOM } } - if (keys %ignore_type) { - print "NOTE: Ignored message types:"; - foreach my $ignore (sort keys %ignore_type) { - print " $ignore"; - } - print "\n"; - print "\n" if ($quiet == 0); - } + if ($clean == 0 && $fix && + ("@rawlines" ne "@fixed" || + $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) { + my $newfile = $filename; + $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace); + my $linecount = 0; + my $f; + + @fixed = fix_inserted_deleted_lines(\@fixed, \@fixed_inserted, \@fixed_deleted); + + open($f, '>', $newfile) + or die "$P: Can't open $newfile for write\n"; + foreach my $fixed_line (@fixed) { + $linecount++; + if ($file) { + if ($linecount > 3) { + $fixed_line =~ s/^\+//; + print $f $fixed_line . "\n"; + } + } else { + print $f $fixed_line . "\n"; + } + } + close($f); - if ($clean == 1 && $quiet == 0) { - print "$vname has no obvious style problems and is ready for submission.\n" - } - if ($clean == 0 && $quiet == 0) { - print << "EOM"; -$vname has style problems, please review. + if (!$quiet) { + print << "EOM"; -If any of these errors are false positives, please report -them to the openocd-devel mailing list or prepare a patch -and send it to Gerrit for review. +Wrote EXPERIMENTAL --fix correction(s) to '$newfile' + +Do _NOT_ trust the results written to this file. +Do _NOT_ submit these changes without inspecting them for correctness. + +This EXPERIMENTAL file is simply a convenience to help rewrite patches. +No warranties, expressed or implied... EOM + } } + if ($quiet == 0) { + print "\n"; + if ($clean == 1) { + print "$vname has no obvious style problems and is ready for submission.\n"; + } else { + print "$vname has style problems, please review.\n"; + } + } return $clean; } diff --git a/tools/scripts/const_structs.checkpatch b/tools/scripts/const_structs.checkpatch new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tools/scripts/spdxcheck.py b/tools/scripts/spdxcheck.py new file mode 100755 index 0000000000..9180f61fa6 --- /dev/null +++ b/tools/scripts/spdxcheck.py @@ -0,0 +1,449 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# Copyright Thomas Gleixner <tglx@linutronix.de> + +from argparse import ArgumentParser +from ply import lex, yacc +import locale +import traceback +import fnmatch +import sys +import git +import re +import os + +class ParserException(Exception): + def __init__(self, tok, txt): + self.tok = tok + self.txt = txt + +class SPDXException(Exception): + def __init__(self, el, txt): + self.el = el + self.txt = txt + +class SPDXdata(object): + def __init__(self): + self.license_files = 0 + self.exception_files = 0 + self.licenses = [ ] + self.exceptions = { } + +class dirinfo(object): + def __init__(self): + self.missing = 0 + self.total = 0 + self.files = [] + + def update(self, fname, basedir, miss): + self.total += 1 + self.missing += miss + if miss: + fname = './' + fname + bdir = os.path.dirname(fname) + if bdir == basedir.rstrip('/'): + self.files.append(fname) + +# Read the spdx data from the LICENSES directory +def read_spdxdata(repo): + + # The subdirectories of LICENSES in the kernel source + # Note: exceptions needs to be parsed as last directory. + # OpenOCD specific: Begin + license_dirs = [ "preferred", "dual", "exceptions", "stand-alone" ] + # OpenOCD specific: End + lictree = repo.head.commit.tree['LICENSES'] + + spdx = SPDXdata() + + for d in license_dirs: + for el in lictree[d].traverse(): + if not os.path.isfile(el.path): + continue + + exception = None + for l in open(el.path, encoding="utf-8").readlines(): + if l.startswith('Valid-License-Identifier:'): + lid = l.split(':')[1].strip().upper() + if lid in spdx.licenses: + raise SPDXException(el, 'Duplicate License Identifier: %s' %lid) + else: + spdx.licenses.append(lid) + + elif l.startswith('SPDX-Exception-Identifier:'): + exception = l.split(':')[1].strip().upper() + spdx.exceptions[exception] = [] + + elif l.startswith('SPDX-Licenses:'): + for lic in l.split(':')[1].upper().strip().replace(' ', '').replace('\t', '').split(','): + if not lic in spdx.licenses: + raise SPDXException(None, 'Exception %s missing license %s' %(exception, lic)) + spdx.exceptions[exception].append(lic) + + elif l.startswith("License-Text:"): + if exception: + if not len(spdx.exceptions[exception]): + raise SPDXException(el, 'Exception %s is missing SPDX-Licenses' %exception) + spdx.exception_files += 1 + else: + spdx.license_files += 1 + break + return spdx + +class id_parser(object): + + reserved = [ 'AND', 'OR', 'WITH' ] + tokens = [ 'LPAR', 'RPAR', 'ID', 'EXC' ] + reserved + + precedence = ( ('nonassoc', 'AND', 'OR'), ) + + t_ignore = ' \t' + + def __init__(self, spdx): + self.spdx = spdx + self.lasttok = None + self.lastid = None + self.lexer = lex.lex(module = self, reflags = re.UNICODE) + # Initialize the parser. No debug file and no parser rules stored on disk + # The rules are small enough to be generated on the fly + self.parser = yacc.yacc(module = self, write_tables = False, debug = False) + self.lines_checked = 0 + self.checked = 0 + self.excluded = 0 + self.spdx_valid = 0 + self.spdx_errors = 0 + self.spdx_dirs = {} + self.dirdepth = -1 + self.basedir = '.' + self.curline = 0 + self.deepest = 0 + + def set_dirinfo(self, basedir, dirdepth): + if dirdepth >= 0: + self.basedir = basedir + bdir = basedir.lstrip('./').rstrip('/') + if bdir != '': + parts = bdir.split('/') + else: + parts = [] + self.dirdepth = dirdepth + len(parts) + + # Validate License and Exception IDs + def validate(self, tok): + id = tok.value.upper() + if tok.type == 'ID': + if not id in self.spdx.licenses: + raise ParserException(tok, 'Invalid License ID') + self.lastid = id + elif tok.type == 'EXC': + if id not in self.spdx.exceptions: + raise ParserException(tok, 'Invalid Exception ID') + if self.lastid not in self.spdx.exceptions[id]: + raise ParserException(tok, 'Exception not valid for license %s' %self.lastid) + self.lastid = None + elif tok.type != 'WITH': + self.lastid = None + + # Lexer functions + def t_RPAR(self, tok): + r'\)' + self.lasttok = tok.type + return tok + + def t_LPAR(self, tok): + r'\(' + self.lasttok = tok.type + return tok + + def t_ID(self, tok): + r'[A-Za-z.0-9\-+]+' + + if self.lasttok == 'EXC': + print(tok) + raise ParserException(tok, 'Missing parentheses') + + tok.value = tok.value.strip() + val = tok.value.upper() + + if val in self.reserved: + tok.type = val + elif self.lasttok == 'WITH': + tok.type = 'EXC' + + self.lasttok = tok.type + self.validate(tok) + return tok + + def t_error(self, tok): + raise ParserException(tok, 'Invalid token') + + def p_expr(self, p): + '''expr : ID + | ID WITH EXC + | expr AND expr + | expr OR expr + | LPAR expr RPAR''' + pass + + def p_error(self, p): + if not p: + raise ParserException(None, 'Unfinished license expression') + else: + raise ParserException(p, 'Syntax error') + + def parse(self, expr): + self.lasttok = None + self.lastid = None + self.parser.parse(expr, lexer = self.lexer) + + def parse_lines(self, fd, maxlines, fname): + self.checked += 1 + self.curline = 0 + fail = 1 + try: + for line in fd: + line = line.decode(locale.getpreferredencoding(False), errors='ignore') + self.curline += 1 + if self.curline > maxlines: + break + self.lines_checked += 1 + if line.find("SPDX-License-Identifier:") < 0: + continue + expr = line.split(':')[1].strip() + # Remove trailing comment closure + if line.strip().endswith('*/'): + expr = expr.rstrip('*/').strip() + # Remove trailing xml comment closure + if line.strip().endswith('-->'): + expr = expr.rstrip('-->').strip() + # Special case for SH magic boot code files + if line.startswith('LIST \"'): + expr = expr.rstrip('\"').strip() + self.parse(expr) + self.spdx_valid += 1 + # + # Should we check for more SPDX ids in the same file and + # complain if there are any? + # + fail = 0 + break + + except ParserException as pe: + if pe.tok: + col = line.find(expr) + pe.tok.lexpos + tok = pe.tok.value + sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok)) + else: + sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, pe.txt)) + self.spdx_errors += 1 + + if fname == '-': + return + + base = os.path.dirname(fname) + if self.dirdepth > 0: + parts = base.split('/') + i = 0 + base = '.' + while i < self.dirdepth and i < len(parts) and len(parts[i]): + base += '/' + parts[i] + i += 1 + elif self.dirdepth == 0: + base = self.basedir + else: + base = './' + base.rstrip('/') + base += '/' + + di = self.spdx_dirs.get(base, dirinfo()) + di.update(fname, base, fail) + self.spdx_dirs[base] = di + +class pattern(object): + def __init__(self, line): + self.pattern = line + self.match = self.match_file + if line == '.*': + self.match = self.match_dot + elif line.endswith('/'): + self.pattern = line[:-1] + self.match = self.match_dir + elif line.startswith('/'): + self.pattern = line[1:] + self.match = self.match_fn + + def match_dot(self, fpath): + return os.path.basename(fpath).startswith('.') + + def match_file(self, fpath): + return os.path.basename(fpath) == self.pattern + + def match_fn(self, fpath): + return fnmatch.fnmatchcase(fpath, self.pattern) + + def match_dir(self, fpath): + if self.match_fn(os.path.dirname(fpath)): + return True + return fpath.startswith(self.pattern) + +def exclude_file(fpath): + for rule in exclude_rules: + if rule.match(fpath): + return True + return False + +def scan_git_tree(tree, basedir, dirdepth): + parser.set_dirinfo(basedir, dirdepth) + for el in tree.traverse(): + if not os.path.isfile(el.path): + continue + if exclude_file(el.path): + parser.excluded += 1 + continue + with open(el.path, 'rb') as fd: + parser.parse_lines(fd, args.maxlines, el.path) + +def scan_git_subtree(tree, path, dirdepth): + for p in path.strip('/').split('/'): + tree = tree[p] + scan_git_tree(tree, path.strip('/'), dirdepth) + +def read_exclude_file(fname): + rules = [] + if not fname: + return rules + with open(fname) as fd: + for line in fd: + line = line.strip() + if line.startswith('#'): + continue + if not len(line): + continue + rules.append(pattern(line)) + return rules + +if __name__ == '__main__': + + ap = ArgumentParser(description='SPDX expression checker') + ap.add_argument('path', nargs='*', help='Check path or file. If not given full git tree scan. For stdin use "-"') + ap.add_argument('-d', '--dirs', action='store_true', + help='Show [sub]directory statistics.') + ap.add_argument('-D', '--depth', type=int, default=-1, + help='Directory depth for -d statistics. Default: unlimited') + ap.add_argument('-e', '--exclude', + help='File containing file patterns to exclude. Default: scripts/spdxexclude') + ap.add_argument('-f', '--files', action='store_true', + help='Show files without SPDX.') + ap.add_argument('-m', '--maxlines', type=int, default=15, + help='Maximum number of lines to scan in a file. Default 15') + ap.add_argument('-v', '--verbose', action='store_true', help='Verbose statistics output') + args = ap.parse_args() + + # Sanity check path arguments + if '-' in args.path and len(args.path) > 1: + sys.stderr.write('stdin input "-" must be the only path argument\n') + sys.exit(1) + + try: + # Use git to get the valid license expressions + repo = git.Repo(os.getcwd()) + assert not repo.bare + + # Initialize SPDX data + spdx = read_spdxdata(repo) + + # Initialize the parser + parser = id_parser(spdx) + + except SPDXException as se: + if se.el: + sys.stderr.write('%s: %s\n' %(se.el.path, se.txt)) + else: + sys.stderr.write('%s\n' %se.txt) + sys.exit(1) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) + + try: + fname = args.exclude + if not fname: + fname = os.path.join(os.path.dirname(__file__), 'spdxexclude') + exclude_rules = read_exclude_file(fname) + except Exception as ex: + sys.stderr.write('FAIL: Reading exclude file %s: %s\n' %(fname, ex)) + sys.exit(1) + + try: + if len(args.path) and args.path[0] == '-': + stdin = os.fdopen(sys.stdin.fileno(), 'rb') + parser.parse_lines(stdin, args.maxlines, '-') + else: + if args.path: + for p in args.path: + if os.path.isfile(p): + parser.parse_lines(open(p, 'rb'), args.maxlines, p) + elif os.path.isdir(p): + scan_git_subtree(repo.head.reference.commit.tree, p, + args.depth) + else: + sys.stderr.write('path %s does not exist\n' %p) + sys.exit(1) + else: + # Full git tree scan + scan_git_tree(repo.head.commit.tree, '.', args.depth) + + ndirs = len(parser.spdx_dirs) + dirsok = 0 + if ndirs: + for di in parser.spdx_dirs.values(): + if not di.missing: + dirsok += 1 + + if args.verbose: + sys.stderr.write('\n') + sys.stderr.write('License files: %12d\n' %spdx.license_files) + sys.stderr.write('Exception files: %12d\n' %spdx.exception_files) + sys.stderr.write('License IDs %12d\n' %len(spdx.licenses)) + sys.stderr.write('Exception IDs %12d\n' %len(spdx.exceptions)) + sys.stderr.write('\n') + sys.stderr.write('Files excluded: %12d\n' %parser.excluded) + sys.stderr.write('Files checked: %12d\n' %parser.checked) + sys.stderr.write('Lines checked: %12d\n' %parser.lines_checked) + if parser.checked: + pc = int(100 * parser.spdx_valid / parser.checked) + sys.stderr.write('Files with SPDX: %12d %3d%%\n' %(parser.spdx_valid, pc)) + sys.stderr.write('Files with errors: %12d\n' %parser.spdx_errors) + if ndirs: + sys.stderr.write('\n') + sys.stderr.write('Directories accounted: %8d\n' %ndirs) + pc = int(100 * dirsok / ndirs) + sys.stderr.write('Directories complete: %8d %3d%%\n' %(dirsok, pc)) + + if ndirs and ndirs != dirsok and args.dirs: + if args.verbose: + sys.stderr.write('\n') + sys.stderr.write('Incomplete directories: SPDX in Files\n') + for f in sorted(parser.spdx_dirs.keys()): + di = parser.spdx_dirs[f] + if di.missing: + valid = di.total - di.missing + pc = int(100 * valid / di.total) + sys.stderr.write(' %-80s: %5d of %5d %3d%%\n' %(f, valid, di.total, pc)) + + if ndirs and ndirs != dirsok and args.files: + if args.verbose or args.dirs: + sys.stderr.write('\n') + sys.stderr.write('Files without SPDX:\n') + for f in sorted(parser.spdx_dirs.keys()): + di = parser.spdx_dirs[f] + for f in sorted(di.files): + sys.stderr.write(' %s\n' %f) + + sys.exit(0) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) diff --git a/tools/scripts/spdxexclude b/tools/scripts/spdxexclude new file mode 100644 index 0000000000..cea346781d --- /dev/null +++ b/tools/scripts/spdxexclude @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Patterns for excluding files and directories + +# Ignore the license directory and the licensing documentation which would +# create lots of noise for no value +LICENSES/ +license-rules.rst + +# Other files without copyrightable content +/NEWS* +testing/ + diff --git a/tools/scripts/spelling.txt b/tools/scripts/spelling.txt new file mode 100644 index 0000000000..8435b99452 --- /dev/null +++ b/tools/scripts/spelling.txt @@ -0,0 +1,1642 @@ +# Originally from Debian's Lintian tool. Various false positives have been +# removed, and various additions have been made as they've been discovered +# in the kernel source. +# +# License: GPLv2 +# +# The format of each line is: +# mistake||correction +# +abandonning||abandoning +abigious||ambiguous +abitrary||arbitrary +abitrate||arbitrate +abnornally||abnormally +abnrormal||abnormal +abord||abort +aboslute||absolute +abov||above +abreviated||abbreviated +absense||absence +absolut||absolute +absoulte||absolute +acccess||access +acceess||access +accelaration||acceleration +acceleratoin||acceleration +accelleration||acceleration +accesing||accessing +accesnt||accent +accessable||accessible +accesss||access +accidentaly||accidentally +accidentually||accidentally +acclerated||accelerated +accoding||according +accomodate||accommodate +accomodates||accommodates +accordign||according +accoring||according +accout||account +accquire||acquire +accquired||acquired +accross||across +accumalate||accumulate +accumalator||accumulator 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+unsinged||unsigned +unstabel||unstable +unsolicitied||unsolicited +unsuccessfull||unsuccessful +unsuported||unsupported +untill||until +ununsed||unused +unuseful||useless +unvalid||invalid +upate||update +upsupported||unsupported +useable||usable +usefule||useful +usefull||useful +usege||usage +usera||users +usualy||usually +usupported||unsupported +utilites||utilities +utillities||utilities +utilties||utilities +utiltity||utility +utitity||utility +utitlty||utility +vaid||valid +vaild||valid +valide||valid +variantions||variations +varible||variable +varient||variant +vaule||value +verbse||verbose +veify||verify +verfication||verification +veriosn||version +verisons||versions +verison||version +verson||version +vicefersa||vice-versa +virtal||virtual +virtaul||virtual +virtiual||virtual +visiters||visitors +vitual||virtual +vunerable||vulnerable +wakeus||wakeups +was't||wasn't +wathdog||watchdog +wating||waiting +wiat||wait +wether||whether +whataver||whatever +whcih||which +whenver||whenever +wheter||whether +whe||when +wierd||weird +wiil||will +wirte||write +withing||within +wnat||want +wont||won't +workarould||workaround +writeing||writing +writting||writing +wtih||with +zombe||zombie +zomebie||zombie diff --git a/tools/scripts/typedefs.txt b/tools/scripts/typedefs.txt new file mode 100644 index 0000000000..97f330d9dc --- /dev/null +++ b/tools/scripts/typedefs.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +fd_set +Jim_Cmd +Jim_CmdProc +Jim_DelCmdProc +Jim_Interp +Jim_Obj diff --git a/uncrustify.cfg b/uncrustify.cfg index 07d097818a..593bcc2adf 100644 --- a/uncrustify.cfg +++ b/uncrustify.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + tok_split_gte=false utf8_byte=false utf8_force=false